Add a `L2 cache line size' member to struct cpu_info. This allows R4k code to

stop abusing another field, and will be used by more routines RSN.

No functional change.

3 files changed, 11 insertions, 11 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 3a53e08ee4d..b64c4fbce89 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.80 2012/04/19 18:15:08 miod Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.81 2012/05/27 19:13:02 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -365,6 +365,7 @@ struct cpu_info {
 	uint		ci_l1datacacheline;
 	uint		ci_l1datacacheset;
 	uint		ci_l2size;
+	uint		ci_l2line;
 	uint		ci_l3size;
 
 	struct schedstate_percpu
diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c
index 0fe0127be23..6cd5d6d40ea 100644
--- a/sys/arch/mips64/mips64/cache_r4k.c
+++ b/sys/arch/mips64/mips64/cache_r4k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r4k.c,v 1.4 2012/05/17 19:34:04 miod Exp $	*/
+/*	$OpenBSD: cache_r4k.c,v 1.5 2012/05/27 19:13:04 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -82,7 +82,7 @@ Mips4k_ConfigCache(struct cpu_info *ci)
 		/* fixed 32KB aliasing to avoid VCE */
 		pmap_prefer_mask = ((1 << 15) - 1);
 	} else {
-		ci->ci_cacheconfiguration = 0;
+		ci->ci_l2line = 0;
 		ci->ci_l2size = 0;
 	}
 	ci->ci_l3size = 0;
@@ -141,7 +141,7 @@ Mips4k_SyncCache(struct cpu_info *ci)
 	if (ci->ci_l2size != 0) {
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
 		eva = sva + ci->ci_l2size;
-		line = ci->ci_cacheconfiguration;	/* L2 line size */
+		line = ci->ci_l2line;
 		while (sva != eva) {
 			cache(IndexWBInvalidate_S, sva);
 			sva += line;
@@ -203,7 +203,7 @@ Mips4k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 	}
 
 	if (ci->ci_l2size != 0) {
-		line = ci->ci_cacheconfiguration;	/* L2 line size */
+		line = ci->ci_l2line;
 		sva = PHYS_TO_XKPHYS(pa, CCA_CACHED);
 		eva = sva + PAGE_SIZE;
 		while (sva != eva) {
@@ -264,7 +264,7 @@ Mips4k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	mips4k_hitwbinv_primary(va, sz, line);
 
 	if (ci->ci_l2size != 0) {
-		line = ci->ci_cacheconfiguration;	/* L2 line size */
+		line = ci->ci_l2line;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
@@ -323,7 +323,7 @@ Mips4k_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	mips4k_hitinv_primary(va, sz, line);
 
 	if (ci->ci_l2size != 0) {
-		line = ci->ci_cacheconfiguration;	/* L2 line size */
+		line = ci->ci_l2line;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
@@ -391,7 +391,7 @@ Mips4k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 	 */
 
 	if (ci->ci_l2size != 0) {
-		line = ci->ci_cacheconfiguration;	/* L2 line size */
+		line = ci->ci_l2line;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
diff --git a/sys/arch/sgi/sgi/ip22_machdep.c b/sys/arch/sgi/sgi/ip22_machdep.c
index c5c52f89e5b..5b0d227668a 100644
--- a/sys/arch/sgi/sgi/ip22_machdep.c
+++ b/sys/arch/sgi/sgi/ip22_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip22_machdep.c,v 1.10 2012/05/27 14:27:10 miod Exp $	*/
+/*	$OpenBSD: ip22_machdep.c,v 1.11 2012/05/27 19:13:04 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -104,8 +104,7 @@ ip22_arcbios_walk_component(arc_config_t *cf)
 		 * SS is Log2(cache size in 4KB units) (should be 0007)
 		 */
 		ci->ci_l2size = (1 << 12) << (key & 0x0000ffff);
-		/* L2 line size */
-		ci->ci_cacheconfiguration = 1 << ((key >> 16) & 0xff);
+		ci->ci_l2line = 1 << ((key >> 16) & 0xff);
 
 		ip22_arcwalk_results |= IP22_HAS_L2;
 	}