diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2007-01-12 21:32:39 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2007-01-12 21:32:39 +0000 |
| commit | aedcd75a8bc5053452a057b0d504d1c476d6e86a (patch) | |
| tree | 9bd5ebb37486af94496b40592def07eee6bc2c8b | |
| parent | 43e4fb1a26fc0d9a065f128e8b8321aec8eebc88 (diff) | |
According to the OpenSolaris sources, the DTO bits are really MMU bit.
Add the real DTO bits for Tomatillo.
| -rw-r--r-- | sys/arch/sparc64/dev/schizo.c | 4 | ||||
| -rw-r--r-- | sys/arch/sparc64/dev/schizoreg.h | 10 |
2 files changed, 8 insertions, 6 deletions
diff --git a/sys/arch/sparc64/dev/schizo.c b/sys/arch/sparc64/dev/schizo.c index 501db2ab7b0..bc726f4dec7 100644 --- a/sys/arch/sparc64/dev/schizo.c +++ b/sys/arch/sparc64/dev/schizo.c @@ -1,4 +1,4 @@ -/* $OpenBSD: schizo.c,v 1.38 2006/12/24 01:25:01 deraadt Exp $ */ +/* $OpenBSD: schizo.c,v 1.39 2007/01/12 21:32:38 kettenis Exp $ */ /* * Copyright (c) 2002 Jason L. Wright (jason@thought.net) @@ -242,7 +242,7 @@ schizo_init(struct schizo_softc *sc, int busa) reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); /* enable/disable error interrupts and arbiter */ - reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_DTO_INT | SCZ_PCICTRL_ARB; + reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; reg &= ~SCZ_PCICTRL_SBH_INT; schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); diff --git a/sys/arch/sparc64/dev/schizoreg.h b/sys/arch/sparc64/dev/schizoreg.h index 7a3695d0d88..3e56b91f695 100644 --- a/sys/arch/sparc64/dev/schizoreg.h +++ b/sys/arch/sparc64/dev/schizoreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: schizoreg.h,v 1.15 2006/06/02 04:47:05 jason Exp $ */ +/* $OpenBSD: schizoreg.h,v 1.16 2007/01/12 21:32:38 kettenis Exp $ */ /* * Copyright (c) 2002 Jason L. Wright (jason@thought.net) @@ -182,22 +182,24 @@ struct schizo_regs { #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ #define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */ +#define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */ +#define TOM_PCICTRL_DTO_INT (1UL << 19UL) /* discard intr en */ #define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */ #define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */ #define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */ #define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */ -#define SCZ_PCICTRL_DTO_ERR (1UL << 36UL) /* pci discard timeout */ +#define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */ #define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */ #define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */ #define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */ #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */ -#define SCZ_PCICTRL_DTO_INT (1UL << 19UL) /* discard intr en */ +#define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */ #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */ #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */ #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */ #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */ #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */ -#define SCZ_PCICTRL_BITS "\20\277UNUS\263ESLCK\246TTO\245RTRY\244DTO\243SBH\242SERR\241SPD\223DTO_INT\222SBH_INT\221EEN\220PARK\210PCIRST" +#define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST" #define SCZ_PCIAFSR_PMA 0x8000000000000000UL #define SCZ_PCIAFSR_PTA 0x4000000000000000UL |