Use register definitions from AMD databook.

2 files changed, 39 insertions, 38 deletions

diff --git a/sys/arch/sparc/dev/qe.c b/sys/arch/sparc/dev/qe.c
index 3d9ab2caa12..91a8bb3730a 100644
--- a/sys/arch/sparc/dev/qe.c
+++ b/sys/arch/sparc/dev/qe.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: qe.c,v 1.1 1998/10/19 05:41:19 jason Exp $	*/
+/*	$OpenBSD: qe.c,v 1.2 1998/10/19 19:55:54 jason Exp $	*/
 
 /*
  * Copyright (c) 1998 Jason L. Wright.
@@ -739,7 +739,7 @@ qeinit(sc)
 	cr->ccnt = 0;
 	cr->pipg = 0;
 
-	mr->phycc = QE_MR_PHYCC_AUTO;
+	mr->phycc = QE_MR_PHYCC_ASEL;
 	mr->xmtfc = QE_MR_XMTFC_APADXMT;
 	mr->rcvfc = 0;
 	mr->imr = QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM;
@@ -748,7 +748,7 @@ qeinit(sc)
 	    QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU;
 	mr->plscc = QE_MR_PLSCC_TP;
 
-	mr->iac = QE_MR_IAC_ACHNGE | QE_MR_IAC_PARESET;
+	mr->iac = QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR;
 	mr->padr = sc->sc_arpcom.ac_enaddr[0];
 	mr->padr = sc->sc_arpcom.ac_enaddr[1];
 	mr->padr = sc->sc_arpcom.ac_enaddr[2];
@@ -756,18 +756,19 @@ qeinit(sc)
 	mr->padr = sc->sc_arpcom.ac_enaddr[4];
 	mr->padr = sc->sc_arpcom.ac_enaddr[5];
 
-	mr->iac = QE_MR_IAC_ACHNGE | QE_MR_IAC_LARESET;
+	mr->iac = QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR;
 	for (i = 0; i < 8; i++)
 		mr->ladrf = 0;
 	mr->iac = 0;
 
 	delay(50000);
-	if ((mr->phycc & QE_MR_PHYCC_LSTAT) == QE_MR_PHYCC_LSTAT)
+	if ((mr->phycc & QE_MR_PHYCC_LNKFL) == QE_MR_PHYCC_LNKFL)
 		printf("%s: no carrier\n", sc->sc_dev.dv_xname);
 
 	i = mr->mpc;	/* cleared on read */
 
-	mr->maccc = QE_MR_MACCC_TXENAB | QE_MR_MACCC_RXENAB;
+	mr->maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV |
+		((ifp->if_flags & IFF_PROMISC) ? QE_MR_MACCC_PROM : 0);
 
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
@@ -921,13 +922,13 @@ qe_mcreset(sc)
 	int i, j;
 
 	if (ifp->if_flags & IFF_ALLMULTI) {
-		mr->iac = QE_MR_IAC_ACHNGE | QE_MR_IAC_LARESET;
+		mr->iac = QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR;
 		for (i = 0; i < 8; i++)
 			mr->ladrf = 0xff;
 		mr->iac = 0;
 	}
 	else if (ifp->if_flags & IFF_PROMISC) {
-		maccc |= QE_MR_MACCC_PROMISC;
+		maccc |= QE_MR_MACCC_PROM;
 	}
 	else {
 
@@ -947,7 +948,7 @@ qe_mcreset(sc)
 				 * which the range is big enough to require
 				 * all bits set.)
 				 */
-				mr->iac = QE_MR_IAC_ACHNGE | QE_MR_IAC_LARESET;
+				mr->iac = QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR;
 				for (i = 0; i < 8; i++)
 					mr->ladrf = 0xff;
 				mr->iac = 0;
@@ -976,11 +977,11 @@ qe_mcreset(sc)
 			ETHER_NEXT_MULTI(step, enm);
 		}
 
-		mr->iac = QE_MR_IAC_ACHNGE | QE_MR_IAC_LARESET;
+		mr->iac = QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR;
 		for (i = 0; i < 8; i++)
 			mr->ladrf = ladrp[i];
 		mr->iac = 0;
 	}
 
-	mr->maccc = maccc | QE_MR_MACCC_TXENAB | QE_MR_MACCC_RXENAB;
+	mr->maccc = maccc | QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
 }
diff --git a/sys/arch/sparc/dev/qereg.h b/sys/arch/sparc/dev/qereg.h
index 81eb88b590c..15d440f6b1c 100644
--- a/sys/arch/sparc/dev/qereg.h
+++ b/sys/arch/sparc/dev/qereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: qereg.h,v 1.1 1998/10/19 05:41:20 jason Exp $	*/
+/*	$OpenBSD: qereg.h,v 1.2 1998/10/19 19:55:55 jason Exp $	*/
 
 /*
  * Copyright (c) 1998 Jason L. Wright.
@@ -223,47 +223,47 @@ struct qe_mregs {
 #define	QE_MR_FIFOCC_RXF16	0x00		/* rx fifo 16 write cycles */
 #define	QE_MR_FIFOCC_TFWU	0x08		/* tx fifo watermark update */
 #define	QE_MR_FIFOCC_RFWU	0x04		/* rx fifo watermark update */
-#define	QE_MR_FIFOCC_TBENAB	0x02		/* tx burst enable */
-#define	QE_MR_FIFOCC_RBENAB	0x01		/* rx burst enable */
+#define	QE_MR_FIFOCC_XMTBRST	0x02		/* tx burst enable */
+#define	QE_MR_FIFOCC_RCVBRST	0x01		/* rx burst enable */
 
 /* qe_mregs.maccc: mac config control. */
-#define	QE_MR_MACCC_PROMISC	0x80		/* promiscuous mode enable */
-#define	QE_MR_MACCC_TPDDISAB	0x40		/* tx 2part deferral enable */
-#define	QE_MR_MACCC_MBAENAB	0x20		/* modified backoff enable */
-#define	QE_MR_MACCC_RPADISAB	0x08		/* rx physical addr disable */
-#define	QE_MR_MACCC_RBDISAB	0x04		/* rx broadcast disable */
-#define	QE_MR_MACCC_TXENAB	0x02		/* enable transmitter */
-#define	QE_MR_MACCC_RXENAB	0x01		/* enable receiver */
+#define	QE_MR_MACCC_PROM	0x80		/* promiscuous mode enable */
+#define	QE_MR_MACCC_DXMT2PD	0x40		/* tx 2part deferral enable */
+#define	QE_MR_MACCC_EMBA	0x20		/* modified backoff enable */
+#define	QE_MR_MACCC_DRCVPA	0x08		/* rx physical addr disable */
+#define	QE_MR_MACCC_DRCVBC	0x04		/* rx broadcast disable */
+#define	QE_MR_MACCC_ENXMT	0x02		/* enable transmitter */
+#define	QE_MR_MACCC_ENRCV	0x01		/* enable receiver */
 
 /* qe_mregs.plscc: pls config control. */
-#define	QE_MR_PLSCC_TXMS	0x08		/* tx mode select */
+#define	QE_MR_PLSCC_XMTSEL	0x08		/* tx mode select */
 #define	QE_MR_PLSCC_GPSI	0x06		/* use gpsi connector */
 #define	QE_MR_PLSCC_DAI		0x04		/* use dai connector */
 #define	QE_MR_PLSCC_TP		0x02		/* use twistedpair connector */
 #define	QE_MR_PLSCC_AUI		0x00		/* use aui connector */
-#define	QE_MR_PLSCC_IOENAB	0x01		/* pls i/o enable */
+#define	QE_MR_PLSCC_ENPLSIO	0x01		/* pls i/o enable */
 
 /* qe_mregs.phycc: phy config control. */
-#define	QE_MR_PHYCC_LSTAT	0x80		/* link status */
-#define	QE_MR_PHYCC_LTSTDIS	0x40		/* disable link test logic */
-#define	QE_MR_PHYCC_RXPOLE	0x20		/* rx polarity */
-#define	QE_MR_PHYCC_APCDISB	0x10		/* autopolaritycorrect disab */
-#define	QE_MR_PHYCC_LTENAB	0x08		/* select low threshold */
-#define	QE_MR_PHYCC_AUTO	0x04		/* connector port auto-sel */
-#define	QE_MR_PHYCC_RWU		0x02		/* remote wakeup */
-#define	QE_MR_PHYCC_AW		0x01		/* auto wakeup */
+#define	QE_MR_PHYCC_LNKFL	0x80		/* link fail */
+#define	QE_MR_PHYCC_DLNKTST	0x40		/* disable link test logic */
+#define	QE_MR_PHYCC_REVPOL	0x20		/* rx polarity */
+#define	QE_MR_PHYCC_DAPC	0x10		/* autopolaritycorrect disab */
+#define	QE_MR_PHYCC_LRT		0x08		/* select low threshold */
+#define	QE_MR_PHYCC_ASEL	0x04		/* connector port auto-sel */
+#define	QE_MR_PHYCC_RWAKE	0x02		/* remote wakeup */
+#define	QE_MR_PHYCC_AWAKE	0x01		/* auto wakeup */
 
 /* qe_mregs.iac: internal address config. */
-#define	QE_MR_IAC_ACHNGE	0x80		/* start address change */
-#define	QE_MR_IAC_PARESET	0x04		/* physical address reset */
-#define	QE_MR_IAC_LARESET	0x02		/* logical address reset */
+#define	QE_MR_IAC_ADDRCHG	0x80		/* start address change */
+#define	QE_MR_IAC_PHYADDR	0x04		/* physical address reset */
+#define	QE_MR_IAC_LOGADDR	0x02		/* logical address reset */
 
 /* qe_mregs.utr: user test register. */
-#define	QE_MR_UTR_RTRENAB	0x80		/* enable resv test register */
-#define	QE_MR_UTR_RTRDISAB	0x40		/* disab resv test register */
-#define	QE_MR_UTR_RPACCEPT	0x20		/* accept runt packets */
+#define	QE_MR_UTR_RTRE		0x80		/* enable resv test register */
+#define	QE_MR_UTR_RTRD		0x40		/* disab resv test register */
+#define	QE_MR_UTR_RPA		0x20		/* accept runt packets */
 #define	QE_MR_UTR_FCOLL		0x10		/* force collision status */
-#define	QE_MR_UTR_FCSENAB	0x08		/* enable fcs on rx */
+#define	QE_MR_UTR_RCVSFCSE	0x08		/* enable fcs on rx */
 #define	QE_MR_UTR_INTLOOPM	0x06		/* Internal loopback w/mandec */
 #define	QE_MR_UTR_INTLOOP	0x04		/* Internal loopback */
 #define	QE_MR_UTR_EXTLOOP	0x02		/* external loopback */