Recent uvm code (and maybe not-so-recent, but it did not explode^WKASSERT at

my face then...) depends upon PMAP_PREFER_ALIGN to be a power of two, minus one.

On mips64 with 4KB pages, the runtime variable used to compute PMAP_PREFER_ALIGN
had the low PAGE_SHIFT bits zeroed (for no good reason I'd say). Don't bother
zeroing them anymore.

4 files changed, 12 insertions, 12 deletions

diff --git a/sys/arch/mips64/mips64/cache_loongson2.S b/sys/arch/mips64/mips64/cache_loongson2.S
index f05d3aee032..7772713d37f 100644
--- a/sys/arch/mips64/mips64/cache_loongson2.S
+++ b/sys/arch/mips64/mips64/cache_loongson2.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_loongson2.S,v 1.4 2010/01/09 23:34:29 miod Exp $	*/
+/*	$OpenBSD: cache_loongson2.S,v 1.5 2012/03/19 20:42:26 miod Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -151,8 +151,8 @@ ConfResult:
 	sw	ta3, CI_L3SIZE(a0)
 
 	addu	t1, ta0, -1			# Use icache for alias mask
-	srl	t1, t2				# Some cpus have different
-	and	t1, ~(PAGE_SIZE - 1)		# i and d cache sizes...
+	srl	t1, t2
+	or	t1, (PAGE_SIZE - 1)
 	PTR_S	t1, CpuCacheAliasMask
 
 	sw	ta0, CI_L1INSTCACHESIZE(a0)	# store cache size.
diff --git a/sys/arch/mips64/mips64/cache_r10k.S b/sys/arch/mips64/mips64/cache_r10k.S
index d55b3c21434..a9f2e03adf1 100644
--- a/sys/arch/mips64/mips64/cache_r10k.S
+++ b/sys/arch/mips64/mips64/cache_r10k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.S,v 1.12 2010/01/09 23:47:41 miod Exp $ */
+/*	$OpenBSD: cache_r10k.S,v 1.13 2012/03/19 20:42:26 miod Exp $ */
 
 /*
  * Copyright (c) 2004 Opsycon AB (www.opsycon.se)
@@ -158,7 +158,7 @@ ConfResult:
 
 	addu	t1, ta0, -1			# Use icache for alias mask
 	srl	t1, t2
-	and	t1, ~(NBPG - 1)
+	or	t1, (PAGE_SIZE - 1)
 #ifdef MULTIPROCESSOR
 	PTR_L	ta2, CpuCacheAliasMask
 	or	t1, ta2				# Pick largest mask
@@ -313,8 +313,8 @@ END(Mips10k_InvalidateICache)
  */
 LEAF(Mips10k_SyncDCachePage, 0)
 	LOAD_XKPHYS(a3, CCA_CACHED)
-	dsll	a1, 34
-	dsrl	a1, 34
+	dsll	a1, (64 - 57)
+	dsrl	a1, (64 - 57)
 	PTR_ADDU a1, a3				# a1 now new XKPHYS address
 	and	a1, ~PAGE_MASK			# Page align start address
 	PTR_ADDU a2, a1, PAGE_SIZE-128
diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S
index 04d82566c9a..45b5cf49517 100644
--- a/sys/arch/mips64/mips64/cache_r5k.S
+++ b/sys/arch/mips64/mips64/cache_r5k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.S,v 1.31 2012/02/16 20:31:30 miod Exp $ */
+/*	$OpenBSD: cache_r5k.S,v 1.32 2012/03/19 20:42:26 miod Exp $ */
 
 /*
  * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se)
@@ -367,8 +367,8 @@ ConfResult:
 	sw	ta3, CI_L3SIZE(a0)
 
 	addu	t1, ta0, -1			# Use icache for alias mask
-	srl	t1, t2				# Some cpus have different
-	and	t1, ~(NBPG - 1)			# I and D cache sizes...
+	srl	t1, t2
+	or	t1, (PAGE_SIZE - 1)
 	PTR_S	t1, CpuCacheAliasMask
 
 	sw	ta0, CI_L1INSTCACHESIZE(a0)	# store cache size.
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c
index 1a102f03543..d3edd57e995 100644
--- a/sys/arch/mips64/mips64/pmap.c
+++ b/sys/arch/mips64/mips64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.54 2011/09/22 17:41:00 jasper Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.55 2012/03/19 20:42:26 miod Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -1123,7 +1123,7 @@ vaddr_t
 pmap_prefer(paddr_t foff, vaddr_t va)
 {
 	if (CpuCacheAliasMask != 0)
-		va += (foff - va) & (CpuCacheAliasMask | PAGE_MASK);
+		va += (foff - va) & CpuCacheAliasMask;
 
 	return va;
 }