expand per-cpu control routines switch

2 files changed, 278 insertions, 83 deletions

diff --git a/sys/arch/hppa/hppa/locore.S b/sys/arch/hppa/hppa/locore.S
index 329fe0b51f5..8ec4ba41d58 100644
--- a/sys/arch/hppa/hppa/locore.S
+++ b/sys/arch/hppa/hppa/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.36 2000/08/15 19:56:17 mickey Exp $	*/
+/*	$OpenBSD: locore.S,v 1.37 2000/08/15 20:12:15 mickey Exp $	*/
 
 /*
  * Copyright (c) 1998-2000 Michael Shalayeff
@@ -70,11 +70,21 @@
 #include <machine/pdc.h>
 #include <machine/intr.h>
 #include <machine/frame.h>
+#include <machine/reg.h>
 #ifdef	GPROF
 #include <machine/gprof.h>
 #endif
 #include "assym.h"
 
+/*
+ * hv-specific instructions
+ */
+#define	DR_PAGE0	.word (5 << 26) | (0x70 << 5)
+#define	DR_PAGE1	.word (5 << 26) | (0x72 << 5)
+#define	MTCPU_T(x,t) .word (5 << 26) | ((t) << 21) | ((x) << 16) | (0xc0 << 5)
+#define	MTCPU_C(x,t) .word (5 << 26) | ((t) << 21) | ((x) << 16) | (0x12 << 5)
+#define	MFCPU_T(r,x) .word (5 << 26) | ((r) << 21) | (0xa0 << 5) | (x)
+#define	MFCPU_C(r,x) .word (5 << 26) | ((r) << 21) | ((x) << 16) | (0x30 << 5)
 
 	.import	$global$, data
 	.import pdc, data
@@ -864,21 +874,29 @@ $syscall_end
 	ldil	L%$name,%r1		! \
 	ldo	R%$name(%r1), %r1
 
+#ifdef HP7000_CPU
 LDILDO(itlb_x)
 LDILDO(dtlb_x)
 LDILDO(tlbd_x)
+#endif
 
+#ifdef HP7100_CPU
 LDILDO(itlb_s)
 LDILDO(dtlb_s)
 LDILDO(tlbd_s)
+#endif
 
+#ifdef HP7200_CPU
 LDILDO(itlb_t)
 LDILDO(dtlb_t)
 LDILDO(tlbd_t)
+#endif
 
+#ifdef HP7100LC_CPU
 LDILDO(itlb_l)
 LDILDO(dtlb_l)
 LDILDO(tlbd_l)
+#endif
 
 #define	ITLBPRE \
 	mfctl	pcoq,r9		/* Offset */			! \
@@ -1141,7 +1159,7 @@ TLABEL(excpt)
 	stw	r1, TF_CR11(r31)
 
 	extru,<> arg0, 10, 1, r0
-	extru,=  arg0, 11, 1, r0
+	extru,= arg0, 11, 1, r0
 	or,tr	r0, r0, r0
 	bl,n	$sfu_emu, rp
 
@@ -1198,7 +1216,7 @@ $sfu_emu
 	xor	r16, r24, r24		/* r24 ^= r16 */		! \
 	and	r17, r24, r24		/* r24 &= r17 */		! \
 	mfctl	vtop, r16		/* r16 = address of HPT table */! \
-	or	r24, r16, r16		/* r16 = HPT entry */
+	or	r16, r24, r24		/* r24 = HPT entry */
 
 	/* Construct the virtual address tag. */
 #define	VTAG ! \
@@ -1207,18 +1225,55 @@ $sfu_emu
 	depi	1, 0, 1, r16		/* and set the valid bit */
 
 	.align	64
+/*
+ * void desidhash_s(void)
+ */
+#if defined(HP7000_CPU) || defined(HP7100_CPU)
+ENTRY(desidhash_s)
+ALTENTRY(desidhash_x)
+	MFCPU_T(DR_CPUCFG,t1)
+	MFCPU_T(DR_CPUCFG,t1)
+	depi	0, DR0_PCXS_DHE, 3, t1	/* 3 4 DR0_PCXS_DOMAIN|DR0_PCXS_IHE */
+	depi	1, DR0_PCXS_EQWSTO, 1, t1
+	depi	0, DR0_PCXS_DHPMC, 1, t1
+	depi	0, DR0_PCXS_ILPMC, 1, t1
+	MTCPU_T(t1,DR_CPUCFG)
+	MTCPU_T(t1,DR_CPUCFG)
+	bv	0(rp)
+	extru	t1, 4, 5, ret0	/* return chip revision */
+EXIT(desidhash_s)
+#endif /* HP7000_CPU || HP7100_CPU */
+
+#ifdef HP7200_CPU
+/*
+ * void desidhash_t(void)
+ */
+ENTRY(desidhash_t)
+	MFCPU_T(DR_CPUCFG,t1)
+	MFCPU_T(DR_CPUCFG,t1)
+	depi	0, DR0_PCXT_IHE, 1, t1
+	depi	0, DR0_PCXT_DHE, 1, t1
+	depi	0, DR0_PCXT_DHPMC, 1, t1
+	depi	0, DR0_PCXT_ILPMC, 1, t1
+	MTCPU_T(t1,DR_CPUCFG)
+	MTCPU_T(t1,DR_CPUCFG)
+	bv	0(rp)
+	extru	t1, 4, 5, ret0	/* return chip revision */
+EXIT(desidhash_t)
+#endif
+
 $tlbd_x
 $tlbd_s
 $tlbd_t
 	HPTENT
-	mtctl	r16, cr28
+	mtctl	r24, cr28
 
 	/*
 	 * Chase the list of entries for this hash bucket until we find
 	 * the correct mapping or NULL.
 	 */
-	ldw	hpt_entry(r16), r24
-$hash_loop_tlbd_t		/* XXX must use ,sl */
+	ldw	hpt_entry(r24), r24
+$hash_loop_tlbd_t
 	comb,=,n r0, r24, TLABEL(all)
 	ldw	pv_va(r24), r25
 	ldw	pv_space(r24), r17
@@ -1233,7 +1288,6 @@ $hash_loop_tlbd_t		/* XXX must use ,sl */
 	b	$tlb_inshpt_t
 	depi	1, TLB_DIRTY_POS, 1, r25
 
-	.align	32
 $itlb_x
 $itlb_s
 $itlb_t
@@ -1250,10 +1304,9 @@ $dtlb_t
 	 */
 
 	HPTENT
-	mtctl	r16, cr28
-	copy	r16, r24
+	mtctl	r24, cr28
 
-	ldw	hpt_tag(r16),r17
+	ldw	hpt_tag(r24),r17
 	VTAG	/* (r8,r9) -> r16 */
 
 	/* Compare the tag against the HPT entry.
@@ -1285,7 +1338,6 @@ $hash_loop_t
 
 	/*
 	 * Load the HPT cache with the miss information for the next time.
-	 * The HPT entry address was saved by the HPTENT
 	 */
 $tlb_inshpt_t
 	stw	r25, pv_tlbprot(r24)
@@ -1303,6 +1355,7 @@ $tlb_gothpt_t
 
 	idtlba	r17,(sr1, r9)
 	idtlbp	r25,(sr1, r9)
+	nop ! nop
 	mtsp	r16, sr1
 	rfir
 	nop
@@ -1310,10 +1363,64 @@ $tlb_gothpt_t
 $tlb_itlb_t
 	iitlba	r17,(sr1, r9)
 	iitlbp	r25,(sr1, r9)
+	nop ! nop
 	mtsp	r16, sr1
 	rfir
 	nop
 
+#ifdef HP7100LC_CPU
+/*
+ * int
+ * ibtlb_l(int i, pa_space_t sp, vaddr_t va, paddr_t pa, vsize_t sz, u_int prot)
+ */
+ENTRY(ibtlb_l)
+	rsm	(PSW_R|PSW_I), t4
+
+	bv	0(rp)
+	mtsm	t4
+EXIT(ibtlb_l)
+
+/*
+ * int
+ * pbtlb_l(int i)
+ */
+ENTRY(pbtlb_l)
+	; DR_PAGE0
+	rsm	(PSW_R|PSW_I), t4
+	ldil	L%0xc041, t1
+	dep	arg0, 30, 3, t1
+	MTCPU_T(t1,DR_DTLB)
+	mtsp	r0, sr1
+	idtlba	r0,(sr1,r0)
+	idtlbp	r0,(sr1,r0)
+	zdepi	-1, 18, 1, t1
+	MTCPU_T(t1,DR_DTLB)
+	bv	0(rp)
+	mtsm	t4
+EXIT(pbtlb_l)
+
+ENTRY(hpti_l)
+	bv,n	r0(rp)
+	nop
+EXIT(hpti_l)
+
+/*
+ * int desidhash_l(void)
+ */
+ENTRY(desidhash_l)
+	MFCPU_C(DR_CPUCFG,t1)
+	depi	0, DR0_PCXL_L2IHASH_EN, 2, t1	/* 2 is 4 DR0_PCXL_L2DHASH_EN */
+	depi	0, DR0_PCXL_L2IHPMC, 1, t1	/* don't reset */
+	depi	0, DR0_PCXL_L2DHPMC, 1, t1	/* don't reset */
+	depi	0, DR0_PCXL_L1IHPMC, 1, t1	/* don't reset */
+	depi	0, DR0_PCXL_L2PARERR,1, t1	/* don't reset */
+		/* set DR0_PCXL_L1ICACHE_EN ??? */
+	MTCPU_C(t1,DR_CPUCFG)
+	bv	0(rp)
+	extru	t1, 4, 5, ret0	/* return chip revision */
+EXIT(desidhash_l)
+
+
 	.align	32
 $tlbd_l
 	mfctl	cr28, r16
@@ -1342,43 +1449,43 @@ $hash_loop_tlbd_l
 $itlb_l
 	HPTENT
 #ifdef DDB
-	mtctl	r16, cr28
+	mtctl	r24, cr28
 #endif
 	b	$tlbmiss_l
 	depi	1, TFF_ITLB_POS, 1, r1	/* mark for ITLB insert */
 
 	.align	8
 $dtlb_l
-	/*mfctl	cr28, r16*/
+	/*mfctl	cr28, r24*/
 	HPTENT	/* weird, but sometimes dtlbmissna does not set cr28 */
 #ifdef DDB
-	mtctl	r16, cr28
+	mtctl	r24, cr28
 #endif
 $tlbmiss_l
 	/*
 	 * r1 is the trap type
 	 * r8 is the space of the address that had the TLB miss
 	 * r9 is the offset of the address that had the TLB miss
-	 * r16 is the correspondent HPT entry pointer
+	 * r24 is the correspondent HPT entry pointer
 	 */
 
 	/*
 	 * Chase the list of entries for this hash bucket until we find
 	 * the correct mapping or NULL.
 	 */
-	ldw	hpt_entry(r16),r24
+	ldw	hpt_entry(r24),r16
 $hash_loop_l
-	comb,=,n r0, r24, $tlbiflpa
-	ldw	pv_va(r24),r25
-	ldw	pv_space(r24),r17
+	comb,=,n r0, r16, $tlbiflpa
+	ldw	pv_va(r16),r25
+	ldw	pv_space(r16),r17
 	comb,<>,n r9,r25,$hash_loop_l
-	ldw	pv_hash(r24),r24
+	ldw	pv_hash(r16),r16
 	comb,<>,n r8,r17,$hash_loop_l
-	ldw	pv_hash(r24),r24
+	ldw	pv_hash(r16),r16
 
 	/* Now set things up to enter the real mapping that we want */
-	ldw	pv_tlbpage(r24),r17
-	ldw	pv_tlbprot(r24),r25
+	ldw	pv_tlbpage(r16),r17
+	ldw	pv_tlbprot(r16),r25
 	depi	1, TLB_REF_POS, 1, r25
 
 	/*
@@ -1386,8 +1493,7 @@ $hash_loop_l
 	 * The HPT entry address was saved by the HPTENT
 	 */
 $tlb_inshpt_l
-	stw	r25, pv_tlbprot(r24)
-	copy	r16, r24
+	stw	r25, pv_tlbprot(r16)
 	VTAG	/* (r8,r9) -> r16 */
 
 	stw	r16, hpt_tag(r24)
@@ -1407,14 +1513,16 @@ $tlb_itlb_l
 	nop ! nop
 	rfir
 	nop
+#endif /* HP7100LC_CPU */
 
+	.export $tlbiflpa, entry
 $tlbiflpa
 	ldi	T_DTLBMISSNA, r16
-	comb,<>,n r1, r16, TLABEL(all)
 	mfctl	iir, r17
+	comb,<>,n r1, r16, TLABEL(all)
 	extru	r17, 5, 6, r16
-	comib,<>,n 1, r16, TLABEL(all)
 	ldi	0x4d, r25
+	comib,<>,n 1, r16, TLABEL(all)
 	extru	r17, 25, 8, r16
 	comb,<>,n r25, r16, TLABEL(all)
 
@@ -1746,7 +1854,7 @@ $trapnowvirt
 
 	/*
 	 * Copy partially saved state from the store into the frame
-	 * N.B. we are not doing any bundeling since it's only 16 words
+	 * N.B. we are not doing any bundleing since it's only 16 words
 	 */
 	ldil	$trap_tmp_save, arg0
 	copy	t3, arg1
@@ -1864,9 +1972,11 @@ fdc_short				/* flush one line at a time */
 	comb,<<,n arg1, arg0, fdc_short
 	fdc,m	arg3(sr1, arg1)
 
-	addi	-1, arg0, arg1
-	fdc	(sr1, arg1)
+	/*addi	-1, arg0, arg1
+	fdc	(sr1, arg1)*/
 
+	sync
+	syncdma
 	bv	r0(r2)
 	sync
 EXIT(fdcache)
@@ -1909,9 +2019,11 @@ pdc_short				/* flush one line at a time */
 	comb,<<,n arg1, arg0, pdc_short
 	pdc,m	arg3(sr1, arg1)
 
-	addi	-1, arg0, arg1
-	pdc	(sr1, arg1)
+	/*addi	-1, arg0, arg1
+	pdc	(sr1, arg1)*/
 
+	sync
+	syncdma
 	bv	r0(r2)
 	sync
 EXIT(pdcache)
@@ -1954,9 +2066,11 @@ fic_short				/* flush one line at a time */
 	comb,<<,n arg1, arg0, fic_short
 	fic,m	arg3(sr1, arg1)
 
-	addi	-1, arg0, arg1
-	fic	(sr1, arg1)
+	/*addi	-1, arg0, arg1
+	fic	(sr1, arg1)*/
 
+	sync
+	syncdma
 	bv	r0(r2)
 	sync
 EXIT(ficache)
@@ -2494,9 +2608,16 @@ EXIT(switch_trampoline)
  * Signal "trampoline" code. Invoked from RTE setup by sendsig().
  */
 ENTRY(sigcode)
-	/* TODO signal trampoline */
-	bv	0(rp)
-	nop
+	/* TODO call signal handler */
+
+	/*ldo	SIGF_SC(sp), arg0*/
+	ldil	L%SYSCALLGATE, r1
+	ble	4(sr7, r1)
+	ldi	SYS_sigreturn, t1
+	copy	ret0, arg0
+	ldil	L%SYSCALLGATE, r1
+	ble	4(sr7, r1)
+	ldi	SYS_exit, t1
 ALTENTRY(esigcode)
 EXIT(sigcode)
 
diff --git a/sys/arch/hppa/hppa/machdep.c b/sys/arch/hppa/hppa/machdep.c
index 15ce0e622f3..6a7e6933d98 100644
--- a/sys/arch/hppa/hppa/machdep.c
+++ b/sys/arch/hppa/hppa/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.27 2000/08/08 21:46:05 mickey Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.28 2000/08/15 20:12:14 mickey Exp $	*/
 
 /*
  * Copyright (c) 1999-2000 Michael Shalayeff
@@ -118,11 +118,12 @@ int cold = 1;		/* unset when engine is up to go */
 int msgbufmapped;	/* set when safe to use msgbuf */
 
 /*
- * things to kill
+ * cache configuration, for most machines is the same
+ * numbers, so it makes sense to do defines w/ numbers depending
+ * on cofigured cpu types in the kernel
  */
-int icache_stride;
-int dcache_stride;
-int dcache_line_mask;
+int icache_stride, icache_line_mask;
+int dcache_stride, dcache_line_mask;
 
 /*
  * things to not kill
@@ -135,18 +136,27 @@ int machine_ledword, machine_leds;
  */
 struct pdc_cache pdc_cache PDC_ALIGNMENT;
 struct pdc_btlb pdc_btlb PDC_ALIGNMENT;
+
 	/* w/ a little deviation should be the same for all installed cpus */
 u_int	cpu_ticksnum, cpu_ticksdenom, cpu_hzticks;
+
 	/* exported info */
 char	machine[] = MACHINE_ARCH;
 char	cpu_model[128];
 enum hppa_cpu_type cpu_type;
-int (*cpu_btlb_ins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
-	    vsize_t sz, u_int prot));
+const char *cpu_typename;
 #ifdef COMPAT_HPUX
 int	cpu_model_hpux;	/* contains HPUX_SYSCONF_CPU* kind of value */
 #endif
 
+/*
+ * exported methods for cpus
+ */
+int (*cpu_desidhash) __P((void));
+int (*cpu_hpt_init) __P((vaddr_t hpt, vsize_t hptsize));
+int (*cpu_btlb_ins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+	    vsize_t sz, u_int prot));
+
 dev_t	bootdev;
 int	totalphysmem, resvmem, physmem, esym;
 
@@ -173,6 +183,7 @@ void hpmc_dump __P((void));
 struct pdc_hwtlb pdc_hwtlb PDC_ALIGNMENT;
 struct pdc_coproc pdc_coproc PDC_ALIGNMENT;
 struct pdc_coherence pdc_coherence PDC_ALIGNMENT;
+struct pdc_spidb pdc_spidbits PDC_ALIGNMENT;
 
 #ifdef DEBUG
 int sigdebug = 0xff;
@@ -187,35 +198,68 @@ extern u_int itlb_x[], dtlb_x[], tlbd_x[];
 extern u_int itlb_s[], dtlb_s[], tlbd_s[];
 extern u_int itlb_t[], dtlb_t[], tlbd_t[];
 extern u_int itlb_l[], dtlb_l[], tlbd_l[];
-int btlb_g __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
-	    vsize_t sz, u_int prot));
+int ibtlb_s __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+    vsize_t sz, u_int prot));
+int ibtlb_t __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+    vsize_t sz, u_int prot));
+int ibtlb_l __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+    vsize_t sz, u_int prot));
+int ibtlb_g __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+    vsize_t sz, u_int prot));
+int pbtlb_g __P((int i));
+int hpti_l __P((vaddr_t, vsize_t));
+int hpti_g __P((vaddr_t, vsize_t));
+int desidhash_x __P((void));
+int desidhash_s __P((void));
+int desidhash_t __P((void));
+int desidhash_l __P((void));
+int desidhash_g __P((void));
 const struct hppa_cpu_typed {
-	char symid[8];
+	char name[8];
 	enum hppa_cpu_type type;
 	int  arch;
 	int  features;
+	int (*desidhash) __P((void));
 	u_int *itlbh, *dtlbh, *tlbdh;
 	int (*btlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
 	    vsize_t sz, u_int prot));
+	int (*btlbprg) __P((int i));
+	int (*hptinit) __P((vaddr_t hpt, vsize_t hptsize));
 } cpu_types[] = {
+#ifdef HP7000_CPU
 	{ "PCX",   hpcx,  0x10, 0,
-				itlb_x, dtlb_x, tlbd_x, btlb_g},
+	    desidhash_x, itlb_x, dtlb_x, tlbd_x, ibtlb_g, pbtlb_g},
+#endif
+#ifdef HP7100_CPU
 	{ "PCXS",  hpcxs, 0x11, HPPA_FTRS_BTLBS,
-				itlb_s, dtlb_s, tlbd_s, btlb_g},
+	    desidhash_s, itlb_s, dtlb_s, tlbd_s, ibtlb_g, pbtlb_g},
+#endif
+#ifdef HP7200_CPU
 	{ "PCXT",  hpcxt, 0x11, HPPA_FTRS_BTLBU,
-				itlb_t, dtlb_t, tlbd_t, btlb_g},
-	{ "PCXT'", hpcxta,0x11, HPPA_FTRS_BTLBU,
-				itlb_t, dtlb_t, tlbd_t, btlb_g},
+	    desidhash_t, itlb_t, dtlb_t, tlbd_t, ibtlb_g, pbtlb_g},
+/* HOW?	{ "PCXT'", hpcxta,0x11, HPPA_FTRS_BTLBU,
+	    desidhash_t, itlb_t, dtlb_t, tlbd_t, ibtlb_g, pbtlb_g}, */
+#endif
+#ifdef HP7100LC_CPU
 	{ "PCXL",  hpcxl, 0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
-				itlb_l, dtlb_l, tlbd_l, btlb_g},
-	{ "PCXL2", hpcxl2,0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
-				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	    desidhash_l, itlb_l, dtlb_l, tlbd_l, ibtlb_g, pbtlb_g, hpti_g},
+#endif
+#ifdef HP7300LC_CPU
+/* HOW?	{ "PCXL2", hpcxl2,0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+	    desidhash_l, itlb_l, dtlb_l, tlbd_l, ibtlb_g, pbtlb_g, hpti_g}, */
+#endif
+#ifdef HP8000_CPU
 	{ "PCXU",  hpcxu, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
-				itlb_l, dtlb_l, tlbd_l, btlb_g},
-	{ "PCXU2", hpcxu2,0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
-				itlb_l, dtlb_l, tlbd_l, btlb_g},
-	{ "PCXW",  hpcxw, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
-				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	    desidhash_g, itlb_l, dtlb_l, tlbd_l, ibtlb_g, pbtlb_g, hpti_g},
+#endif
+#ifdef HP8200_CPU
+/* HOW?	{ "PCXU2", hpcxu2,0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+	    desidhash_g, itlb_l, dtlb_l, tlbd_l, ibtlb_g, pbtlb_g, hpti_g}, */
+#endif
+#ifdef HP8500_CPU
+/* HOW?	{ "PCXW",  hpcxw, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+	    desidhash_g, itlb_l, dtlb_l, tlbd_l, ibtlb_g, pbtlb_g, hpti_g}, */
+#endif
 	{ "", 0 }
 };
 
@@ -244,9 +288,9 @@ hppa_init(start)
 #endif
 	}
 
-	/* XXX these gonna die */
 	dcache_line_mask = pdc_cache.dc_conf.cc_line * 16 - 1;
 	dcache_stride = pdc_cache.dc_stride;
+	icache_line_mask = pdc_cache.ic_conf.cc_line * 16 - 1;
 	icache_stride = pdc_cache.ic_stride;
 
 	/* cache coherence params (pbably available for 8k only) */
@@ -257,6 +301,9 @@ hppa_init(start)
 	    pdc_coherence.ia_cst, pdc_coherence.da_cst,
 	    pdc_coherence.ita_cst, pdc_coherence.dta_cst, error);
 #endif
+	error = pdc_call((iodcio_t)pdc, 0, PDC_CACHE, PDC_CACHE_GETSPIDB,
+	    &pdc_spidbits, 0, 0, 0, 0);
+	printf("SPID bits: 0x%x, error = %d\n", pdc_spidbits.spidbits, error);
 
 	/* setup hpmc handler */
 	{
@@ -335,24 +382,24 @@ hppa_init(start)
 			printf("WARNING: UNKNOWN CPU TYPE; GOOD LUCK (%x)\n",
 			    cpu_features);
 		else {
-		/*
-		 * Ptrs to various tlb handlers, to be filled based on cpu
-		 * features.
-		 * from locore.S
-		 */
-		extern u_int trap_ep_T_TLB_DIRTY[];
-		extern u_int trap_ep_T_ITLBMISS[];
-		extern u_int trap_ep_T_DTLBMISS[];
-		extern u_int trap_ep_T_ITLBMISSNA[];
-		extern u_int trap_ep_T_DTLBMISSNA[];
-#define	LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1])
+			/*
+			 * Ptrs to various tlb handlers, to be filled
+			 * based on cpu features.
+			 * from locore.S
+			 */
+			extern u_int trap_ep_T_TLB_DIRTY[];
+			extern u_int trap_ep_T_ITLBMISS[];
+			extern u_int trap_ep_T_DTLBMISS[];
+			extern u_int trap_ep_T_ITLBMISSNA[];
+			extern u_int trap_ep_T_DTLBMISSNA[];
+
+			cpu_type      = p->type;
+			cpu_typename  = p->name;
+			cpu_btlb_ins  = p->btlbins;
+			cpu_hpt_init  = p->hptinit;
+			cpu_desidhash = p->desidhash;
 
-#ifdef DEBUG
-			printf("cputype: %s\n", p->symid);
-#endif
-			cpu_type = p->type;
-
-			cpu_btlb_ins = p->btlbins;
+#define	LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1])
 			LDILDO(trap_ep_T_TLB_DIRTY , p->tlbdh);
 			LDILDO(trap_ep_T_ITLBMISS  , p->itlbh);
 			LDILDO(trap_ep_T_DTLBMISS  , p->dtlbh);
@@ -448,9 +495,7 @@ hppa_init(start)
 		u_int hpt;
 
 		mfctl(CR_VTOP, hpt);
-		if ((error = pdc_call((iodcio_t)pdc, 0, PDC_TLB,
-		    PDC_TLB_CONFIG, &pdc_hwtlb, hpt, hptsize,
-		    PDC_TLB_CURRPDE)) < 0) {
+		if ((error = (cpu_hpt_init)(hpt, hptsize)) < 0) {
 #ifdef DEBUG
 			printf("WARNING: HPT init error %d\n", error);
 #endif
@@ -498,7 +543,12 @@ cpu_startup()
 	pmapdebug = 0;
 #endif
 
-	/* good night */
+	/*
+	 * i won't understand a friend of mine,
+	 * who sat in a room full of artificial ice,
+	 * fogging the air w/ humid cries --
+	 *	WELCOME TO SUMMER!
+	 */
 	printf(version);
 
 	/* identify system type */
@@ -747,7 +797,31 @@ ptlball()
 }
 
 int
-btlb_g(i, sp, va, pa, sz, prot)
+desidhash_g()
+{
+	/* TODO call PDC to disable SID hashing in the cache index */
+
+	return 0;
+}
+
+int
+hpti_g(hpt, hptsize)
+	vaddr_t hpt;
+	vsize_t hptsize;
+{
+	return pdc_call((iodcio_t)pdc, 0, PDC_TLB, PDC_TLB_CONFIG,
+	    &pdc_hwtlb, hpt, hptsize, PDC_TLB_CURRPDE);
+}
+
+int
+pbtlb_g(i)
+	int i;
+{
+	return -1;
+}
+
+int
+ibtlb_g(i, sp, va, pa, sz, prot)
 	int i;
 	pa_space_t sp;
 	vaddr_t va;