diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2007-03-19 20:13:20 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2007-03-19 20:13:20 +0000 |
| commit | 4baf1f695dad1d6423107c450b7868fcf41e885d (patch) | |
| tree | fce578987f6a94b24f944b028e3f313c70211ec2 | |
| parent | a2fb92857fd5cb507071e8ec23d0b1a0e6787c2c (diff) | |
bus_dmamap_sync fixes to cope with real life.
| -rw-r--r-- | sys/arch/landisk/landisk/bus_dma.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/sys/arch/landisk/landisk/bus_dma.c b/sys/arch/landisk/landisk/bus_dma.c index dcd1f0ab9d1..2269feac674 100644 --- a/sys/arch/landisk/landisk/bus_dma.c +++ b/sys/arch/landisk/landisk/bus_dma.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bus_dma.c,v 1.2 2006/10/19 21:16:54 kettenis Exp $ */ +/* $OpenBSD: bus_dma.c,v 1.3 2007/03/19 20:13:19 miod Exp $ */ /* $NetBSD: bus_dma.c,v 1.1 2006/09/01 21:26:18 uwe Exp $ */ /* @@ -444,6 +444,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, DPRINTF(("bus_dmamap_sync: t = %p, map = %p, offset = %ld, len = %ld, ops = %x\n", t, map, offset, len, ops)); +#ifdef DIAGNOSTIC /* * Mixing PRE and POST operations is not allowed. */ @@ -451,7 +452,6 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0) panic("_bus_dmamap_sync: mix PRE and POST"); -#ifdef DIAGNOSTIC if (offset >= map->dm_mapsize) panic("_bus_dmamap_sync: bad offset"); if ((offset + len) > map->dm_mapsize) @@ -496,21 +496,28 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, switch (ops) { case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE: - sh_dcache_wbinv_range(naddr, minlen); + if (SH_HAS_WRITEBACK_CACHE) + sh_dcache_wbinv_range(naddr, minlen); + else + sh_dcache_inv_range(naddr, minlen); break; case BUS_DMASYNC_PREREAD: - if (((naddr | minlen) & (~(sh_cache_line_size - 1))) == 0) { - sh_dcache_inv_range(naddr, minlen); - } else { + if (SH_HAS_WRITEBACK_CACHE && + ((naddr | minlen) & (sh_cache_line_size - 1)) != 0) sh_dcache_wbinv_range(naddr, minlen); - } + else + sh_dcache_inv_range(naddr, minlen); break; case BUS_DMASYNC_PREWRITE: - if (SH_HAS_WRITEBACK_CACHE) { + if (SH_HAS_WRITEBACK_CACHE) sh_dcache_wb_range(naddr, minlen); - } + break; + + case BUS_DMASYNC_POSTREAD: + case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE: + sh_dcache_inv_range(naddr, minlen); break; } offset = 0; |