Improve the ARMv7 support, still work in progress.

6 files changed, 119 insertions, 13 deletions

diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 39a8ff8b33b..d72700ae2f7 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.c,v 1.10 2009/05/11 12:51:24 drahn Exp $	*/
+/*	$OpenBSD: cpufunc.c,v 1.11 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*
@@ -1283,7 +1283,7 @@ set_cpufuncs()
 	}
 #endif /* CPU_ARM11 */
 #ifdef CPU_ARMv7
-	if (cputype == CPU_ID_OMAP3430 || cputype == CPU_ID_OMAP3530) {
+	if ((cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8) {
 		cpufuncs = armv7_cpufuncs;
 		cpu_reset_needs_v4_MMU_disable = 1;	/* V4 or higher */
 		arm_get_cachetype_cp15v7();
diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c
index 312c77d7dc5..e2be286d732 100644
--- a/sys/arch/arm/arm/pmap.c
+++ b/sys/arch/arm/arm/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.22 2009/05/08 02:57:32 drahn Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.23 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $	*/
 
 /*
@@ -289,7 +289,7 @@ static paddr_t pmap_kernel_l2ptp_phys;
 /*
  * pmap copy/zero page, and mem(5) hook point
  */
-static pt_entry_t *csrc_pte, *cdst_pte;
+pt_entry_t *csrc_pte, *cdst_pte;
 static vaddr_t csrcp, cdstp;
 char *memhook;
 extern caddr_t msgbufaddr;
@@ -3468,6 +3468,50 @@ pmap_copy_page_xscale(struct vm_page *src_pg, struct vm_page *dst_pg)
 }
 #endif /* ARM_MMU_XSCALE == 1 */
 
+#if defined(CPU_ARMv7)
+void pmap_copy_page_v7(struct vm_page *src_pg, struct vm_page *dst_pg);
+void
+pmap_copy_page_v7(struct vm_page *src_pg, struct vm_page *dst_pg)
+{
+	paddr_t src = VM_PAGE_TO_PHYS(src_pg);
+	paddr_t dst = VM_PAGE_TO_PHYS(dst_pg);
+#ifdef DEBUG
+	if (dst_pg->mdpage.pvh_list != NULL)
+		panic("pmap_copy_page: dst page has mappings");
+#endif
+
+	KDASSERT((src & PGOFSET) == 0);
+	KDASSERT((dst & PGOFSET) == 0);
+
+	/*
+	 * Clean the source page.  Hold the source page's lock for
+	 * the duration of the copy so that no other mappings can
+	 * be created while we have a potentially aliased mapping.
+	 */
+	simple_lock(&src_pg->mdpage.pvh_slock);
+	(void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE);
+
+	/*
+	 * Map the pages into the page hook points, copy them, and purge
+	 * the cache for the appropriate page. Invalidate the TLB
+	 * as required.
+	 */
+	*csrc_pte = L2_S_PROTO | src |
+	    L2_V7_AP(0x5) | pte_l2_s_cache_mode;
+	PTE_SYNC(csrc_pte);
+	*cdst_pte = L2_S_PROTO | dst |
+	    L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
+	PTE_SYNC(cdst_pte);
+	cpu_tlb_flushD_SE(csrcp);
+	cpu_tlb_flushD_SE(cdstp);
+	cpu_cpwait();
+	bcopy_page(csrcp, cdstp);
+	cpu_dcache_inv_range(csrcp, PAGE_SIZE);
+	simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */
+	cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
+}
+#endif /* CPU_ARMv7 */
+
 /*
  * void pmap_virtual_space(vaddr_t *start, vaddr_t *end)
  *
@@ -4648,7 +4692,7 @@ pmap_pte_init_generic(void)
 	pte_l1_c_proto = L1_C_PROTO_generic;
 	pte_l2_s_proto = L2_S_PROTO_generic;
 
-	pmap_copy_page_func = pmap_copy_page_generic;
+	pmap_copy_page_func = pmap_copy_page_v7;
 	pmap_zero_page_func = pmap_zero_page_generic;
 }
 
@@ -4756,6 +4800,14 @@ pmap_pte_init_armv7(void)
 	pte_l2_l_cache_mode_pt = L2_C;
 	pte_l2_s_cache_mode_pt = L2_C;
 
+	pte_l2_s_prot_u = L2_S_PROT_U_v7;
+	pte_l2_s_prot_w = L2_S_PROT_W_v7;
+	pte_l2_s_prot_mask = L2_S_PROT_MASK_v7;
+
+	pte_l1_s_proto = L1_S_PROTO_v7;
+	pte_l1_c_proto = L1_C_PROTO_v7;
+	pte_l2_s_proto = L2_S_PROTO_v7;
+
 }
 #endif /* CPU_ARMv7 */
 
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index d54448b3965..a2f17a62823 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: armreg.h,v 1.6 2009/05/11 12:50:23 drahn Exp $	*/
+/*	$OpenBSD: armreg.h,v 1.7 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $	*/
 
 /*
@@ -220,8 +220,11 @@
 #define CPU_ID_IXP425_533	0x690541c0
 #define CPU_ID_IXP425_400	0x690541d0
 #define CPU_ID_IXP425_266	0x690541f0
+#define CPU_ID_CORTEX_A8	0x410fc080
+#define CPU_ID_CORTEX_A8_MASK	0xff0fffe0
 #define CPU_ID_OMAP3430		0x411fc080
-#define CPU_ID_OMAP3530		0x411fc090	/* XXX */
+#define CPU_ID_OMAP3530		0x411fc090      /* XXX */
+
 
 
 /* ARM3-specific coprocessor 15 registers */
diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h
index 00c6b909b9f..a02c98e0b6a 100644
--- a/sys/arch/arm/include/cpuconf.h
+++ b/sys/arch/arm/include/cpuconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpuconf.h,v 1.5 2009/05/08 02:57:32 drahn Exp $	*/
+/*	$OpenBSD: cpuconf.h,v 1.6 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $	*/
 
 /*
@@ -102,6 +102,8 @@
  *	ARM_MMU_XSCALE		XScale MMU.  Compatible with generic ARM
  *				MMU, but also has several extensions which
  *				require different PTE layout to use.
+ *      ARM_MMU_V7		v6/v7 MMU with XP bit enabled subpage
+ *				protection is not used, TEX/AP is used instead.
  */
 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
 #define	ARM_MMU_MEMC		1
@@ -132,13 +134,13 @@
 #endif
 
 #if defined(CPU_ARMv7)
-#define ARM_MMU_v7		1
+#define ARM_MMU_V7		1
 #else
-#define ARM_MMU_v7		0
+#define ARM_MMU_V7		0
 #endif
 
 #define	ARM_NMMUS		(ARM_MMU_MEMC + ARM_MMU_GENERIC +	\
-				 ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_v7)
+				 ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V7)
 
 /*
  * Define features that may be present on a subset of CPUs
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index 3d891b182f2..fdb0ba8b476 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.10 2009/05/08 02:57:32 drahn Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.11 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $	*/
 
 /*
@@ -415,6 +415,13 @@ void	pmap_pte_init_armv7(void);
 void	pmap_pte_init_sa1(void);
 #endif /* ARM_MMU_SA1 == 1 */
 
+#if ARM_MMU_V7 == 1
+void	pmap_copy_page_v7(struct vm_page *, struct vm_page *);
+void	pmap_zero_page_v7(struct vm_page *);
+
+void	pmap_pte_init_v7(void);
+#endif /* ARM_MMU_V7 == 1 */
+
 #if ARM_MMU_XSCALE == 1
 void	pmap_copy_page_xscale(struct vm_page *, struct vm_page *);
 void	pmap_zero_page_xscale(struct vm_page *);
@@ -478,6 +485,7 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 
 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X))
+#define	L1_S_CACHE_MASK_v7	(L1_S_B|L1_S_C|L1_S_V7_TEX(TEX_V7_X))
 
 #define	L2_L_PROT_U		(L2_AP(AP_U))
 #define	L2_L_PROT_W		(L2_AP(AP_W))
@@ -485,6 +493,7 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 
 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X))
+#define	L2_L_CACHE_MASK_v7	(L2_B|L2_C|L2_V7_L_TEX(TEX_V7_X))
 
 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
 #define	L2_S_PROT_W_generic	(L2_AP(AP_W))
@@ -494,19 +503,27 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 #define	L2_S_PROT_W_xscale	(L2_AP0(AP_W))
 #define	L2_S_PROT_MASK_xscale	(L2_S_PROT_U|L2_S_PROT_W)
 
+#define	L2_S_PROT_U_v7		(L2_AP0(AP_U))
+#define	L2_S_PROT_W_v7		(L2_AP0(AP_W))
+#define	L2_S_PROT_MASK_v7	(L2_S_PROT_U|L2_S_PROT_W)
+
 #define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
 #define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X))
+#define	L2_S_CACHE_MASK_v7	(L2_B|L2_C)
 
 #define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
 #define	L1_S_PROTO_xscale	(L1_TYPE_S)
+#define	L1_S_PROTO_v7		(L1_TYPE_S)
 
 #define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
 #define	L1_C_PROTO_xscale	(L1_TYPE_C)
+#define	L1_C_PROTO_v7		(L1_TYPE_C)
 
 #define	L2_L_PROTO		(L2_TYPE_L)
 
 #define	L2_S_PROTO_generic	(L2_TYPE_S)
 #define	L2_S_PROTO_xscale	(L2_TYPE_XSCALE_XS)
+#define	L2_S_PROTO_v7		(L2_TYPE_S)
 
 /*
  * User-visible names for the ones that vary with MMU class.
@@ -558,6 +575,21 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 
 #define	pmap_copy_page(s, d)	pmap_copy_page_xscale((s), (d))
 #define	pmap_zero_page(d)	pmap_zero_page_xscale((d))
+#elif ARM_MMU_V7 == 1
+#define	L2_S_PROT_U		L2_S_PROT_U_v7
+#define	L2_S_PROT_W		L2_S_PROT_W_v7
+#define	L2_S_PROT_MASK		L2_S_PROT_MASK_v7
+
+#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_v7
+#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_v7
+#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_v7
+
+#define	L1_S_PROTO		L1_S_PROTO_v7
+#define	L1_C_PROTO		L1_C_PROTO_v7
+#define	L2_S_PROTO		L2_S_PROTO_v7
+
+#define	pmap_copy_page(s, d)	pmap_copy_page_v7((s), (d))
+#define	pmap_zero_page(d)	pmap_zero_page_v7((d))
 #endif /* ARM_NMMUS > 1 */
 
 /*
diff --git a/sys/arch/arm/include/pte.h b/sys/arch/arm/include/pte.h
index f263fffc6cd..708ec9797cd 100644
--- a/sys/arch/arm/include/pte.h
+++ b/sys/arch/arm/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.1 2004/02/01 05:09:49 drahn Exp $	*/
+/*	$OpenBSD: pte.h,v 1.2 2009/05/24 04:56:19 drahn Exp $	*/
 /*	$NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $	*/
 
 /*
@@ -149,6 +149,14 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L1_S_XSCALE_P	0x00000200	/* ECC enable for this section */
 #define	L1_S_XSCALE_TEX(x) ((x) << 12)	/* Type Extension */
 
+#define	L1_S_V7_TEX(x)	((x) << 12)	/* Type Extension */
+#define	L1_S_V7_NS(x)	((x) << 12)	/* */
+#define	L1_S_V7_nG(x)	((x) << 12)	/* */
+#define	L1_S_V7_S(x)	((x) << 12)	/* */
+#define	L1_S_V7_S(x)	((x) << 12)	/* */
+#define	L1_S_V7_AP(x)	(((x << 13) & 0x4) | ((x) << 10 & 3))	/* AP*/
+#define	L1_S_V7_XN(x)	((x) << 4)	/* */
+
 /* L1 Coarse Descriptor */
 #define	L1_C_IMP0	0x00000004	/* implementation defined */
 #define	L1_C_IMP1	0x00000008	/* implementation defined */
@@ -198,6 +206,15 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_XSCALE_L_TEX(x) ((x) << 12)	/* Type Extension */
 #define	L2_XSCALE_T_TEX(x) ((x) << 6)	/* Type Extension */
 
+#define	L2_V7_L_TEX(x) ((x) << 12)	/* Type Extension */
+#define	L2_V7_L_XN(x)	((x) << 15)	/* eXecute Never */
+#define	L2_V7_T_TEX(x) ((x) << 6)	/* Type Extension */
+#define	L2_V7_T_XN(x)	((x) << 0)	/* eXecute Never */
+
+#define	L2_V7_AP(x)	((((x)& 4) << 7) | (((x) & 3) << 4))	/* AP */
+#define	L2_V7_S(x)	((x) << 10)	/* Shared */
+#define	L2_V7_nG(x)	((x) << 10)	/* not Global */
+
 /*
  * Access Permissions for L1 and L2 Descriptors.
  */