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authorVisa Hankala <visa@cvs.openbsd.org>2021-04-24 07:49:12 +0000
committerVisa Hankala <visa@cvs.openbsd.org>2021-04-24 07:49:12 +0000
commit1863763ec057a1e33218137818d1c964c733bb27 (patch)
treebdec899e72cefbae040ae95b42a089f69d3cde5b /Makefile.cross
parentc69311f4a3fe9c9313a4b5686dc7971619f0a3b5 (diff)
Add cduart(4), a driver for the Cadence UART found on Xilinx Zynq SoCs.
Tested on Xilinx Zynq-7000. Input and OK kettenis@
Diffstat (limited to 'Makefile.cross')
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