egcs projects compiler system

Exact copy of the snapshot, except for the removal of
	texinfo/
	gcc/ch/
	libchill/

3 files changed, 5308 insertions, 0 deletions

diff --git a/gnu/egcs/gcc/config/gmicro/gmicro.c b/gnu/egcs/gcc/config/gmicro/gmicro.c
new file mode 100644
index 00000000000..0029ccc07bd
--- /dev/null
+++ b/gnu/egcs/gcc/config/gmicro/gmicro.c
@@ -0,0 +1,982 @@
+/* Subroutines for insn-output.c for the Gmicro.
+   Ported by Masanobu Yuhara, Fujitsu Laboratories LTD.
+   (yuhara@flab.fujitsu.co.jp)
+
+   Copyright (C) 1990, 1991, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Among other things, the copyright
+notice and this notice must be preserved on all copies.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+#include "config.h"
+#include <stdio.h>
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+
+extern char *rtx_name[];
+
+mypr (s, a1, a2, a3, a4, a5)
+     char *s;
+     int a1, a2, a3, a4, a5;
+{
+  fprintf (stderr, s, a1, a2, a3, a4, a5);
+}
+
+myprcode (i)
+     int i;
+{
+  if (i < 0 || i > 90)
+    fprintf (stderr, "code = %d\n", i);
+  else
+    fprintf (stderr, "code = %s\n", rtx_name[i]);
+}
+
+myabort (i)
+     int i;
+{
+  fprintf (stderr, "myabort");
+  myprcode (i);
+}
+
+
+/* This is how to output an ascii string.  */
+/* See ASM_OUTPUT_ASCII in gmicro.h.  */
+output_ascii (file, p, size)
+     FILE *file;
+     char *p;
+     int size;
+{
+  int i;
+  int in_quote = 0;
+  register int c;
+
+  fprintf (file, "\t.sdata ");
+
+  for (i = 0; i < size; i++) 
+    {
+      c = p[i];
+      if (c >= ' ' && c < 0x7f) 
+	{
+	  if (!in_quote) 
+	    {
+	      putc ('"', file);
+	      in_quote = 1;
+	    }
+	  putc (c, file);
+	}
+      else 
+	{
+	  if (in_quote) 
+	    {
+	      putc ('"', file);
+	      in_quote = 0;
+	    }
+	  fprintf (file, "<%d>", c);
+	}
+    }
+  if (in_quote)
+    putc ('"', file);
+  putc ('\n', file);
+}
+
+
+/* call this when GET_CODE (index) is MULT. */
+print_scaled_index (file, index)
+     FILE *file;
+     register rtx index;
+{
+  register rtx ireg;
+  int scale;
+
+  if (GET_CODE (XEXP (index, 0)) == REG) 
+    {
+      ireg = XEXP (index, 0);
+      scale = INTVAL (XEXP (index, 1));
+    }
+  else 
+    {
+      ireg = XEXP (index, 1);
+      scale = INTVAL (XEXP (index, 0));
+    }
+  if (scale == 1)
+    fprintf (file, "%s", reg_names[REGNO (ireg)]);
+  else
+    fprintf (file, "%s*%d", reg_names[REGNO (ireg)], scale);
+}
+    
+
+print_operand_address (file, addr)
+     FILE *file;
+     register rtx addr;
+{
+  register rtx xtmp0, xtmp1, breg, ixreg;
+  int scale;
+  int needcomma = 0;
+  rtx offset;
+
+  fprintf (file, "@");
+ retry:
+  switch (GET_CODE (addr)) 
+    {
+    case MEM:
+      fprintf (file, "@");
+      addr = XEXP (addr, 0);
+      goto retry;
+
+    case REG:
+      fprintf (file, "%s", reg_names[REGNO (addr)]);
+      break;
+
+    case MULT:
+      print_scaled_index (file, addr);
+      break;
+
+    case PRE_DEC:
+      fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
+      break;
+
+    case POST_INC:
+      fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
+      break;
+
+    case PLUS:
+      xtmp0 = XEXP (addr, 0);
+      xtmp1 = XEXP (addr, 1);
+      ixreg = 0;	breg = 0;
+      offset = 0;
+      if (CONSTANT_ADDRESS_P (xtmp0)) 
+	{
+	  offset = xtmp0;
+	  breg = xtmp1;
+	}
+      else if (CONSTANT_ADDRESS_P (xtmp1)) 
+	{
+	  offset = xtmp1;
+	  breg = xtmp0;
+	}
+      else 
+	{
+	  goto NOT_DISP;
+	}
+
+      if (REG_CODE_BASE_P (breg))
+	goto PRINT_MEM;
+
+      if (GET_CODE (breg) == MULT) 
+	{
+	  if (REG_CODE_INDEX_P (XEXP (breg, 0))) 
+	    {
+	      ixreg = XEXP (breg, 0);
+	      scale = INTVAL (XEXP (breg, 1));
+	      breg = 0;
+	    }
+	  else 
+	    {
+	      ixreg = XEXP (breg, 1);
+	      scale = INTVAL (XEXP (breg, 0));
+	      breg = 0;
+	    }
+	  goto PRINT_MEM;
+	}
+
+      /* GET_CODE (breg) must be PLUS here. */
+      xtmp0 = XEXP (breg, 0);
+      xtmp1 = XEXP (breg, 1);
+      if (REG_CODE_BASE_P (xtmp0)) 
+	{
+	  breg = xtmp0;
+	  xtmp0 = xtmp1;
+	}
+      else 
+	{
+	  breg = xtmp1;
+	  /* xtmp0 = xtmp0; */
+	}
+
+      if (GET_CODE (xtmp0) == MULT) 
+	{
+	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
+	    {
+	      ixreg = XEXP (xtmp0, 0);
+	      scale = INTVAL (XEXP (xtmp0, 1));
+	    }
+	  else 
+	    {
+	      ixreg = XEXP (xtmp0, 1);
+	      scale = INTVAL (XEXP (xtmp0, 0));
+	    }
+	}
+      else 
+	{
+	  ixreg = xtmp0;
+	  scale = 1;
+	}
+      goto PRINT_MEM;
+
+    NOT_DISP:
+      if (REG_CODE_BASE_P (xtmp0)) 
+	{
+	  breg = xtmp0;
+	  xtmp0 = xtmp1;
+	}
+      else if (REG_CODE_BASE_P (xtmp1)) 
+	{
+	  breg = xtmp1;
+	  /* xtmp0 = xtmp0; */
+	}
+      else
+	goto NOT_BASE;
+    
+      if (REG_CODE_INDEX_P (xtmp0)) 
+	{
+	  ixreg = xtmp0;
+	  scale = 1;
+	  goto PRINT_MEM;
+	}
+      else if (CONSTANT_ADDRESS_P (xtmp0)) 
+	{
+	  offset = xtmp0;
+	  goto PRINT_MEM;
+	}
+      else if (GET_CODE (xtmp0) == MULT) 
+	{
+	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
+	    {
+	      ixreg = XEXP (xtmp0, 0);
+	      scale = INTVAL (XEXP (xtmp0, 1));
+	    }
+	  else 
+	    {
+	      ixreg = XEXP (xtmp0, 1);
+	      scale = INTVAL (XEXP (xtmp0, 0));
+	    }
+	  goto PRINT_MEM;
+	}
+
+      /* GET_CODE (xtmp0) must be PLUS. */
+      xtmp1 = XEXP (xtmp0, 1);
+      xtmp0 = XEXP (xtmp0, 0);
+
+      if (CONSTANT_ADDRESS_P (xtmp0)) 
+	{
+	  offset = xtmp0;
+	  xtmp0 = xtmp1;
+	}
+      else 
+	{
+	  offset = xtmp1;
+	  /* xtmp0 = xtmp0; */
+	}
+
+      if (REG_CODE_INDEX_P (xtmp0)) 
+	{
+	  ixreg = xtmp0;
+	}
+      else 
+	{			/* GET_CODE (xtmp0) must be MULT. */
+	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
+	    {
+	      ixreg = XEXP (xtmp0, 0);
+	      scale = INTVAL (XEXP (xtmp0, 1));
+	    }
+	  else 
+	    {
+	      ixreg = XEXP (xtmp0, 1);
+	      scale = INTVAL (XEXP (xtmp0, 0));
+	    }
+	}
+      goto PRINT_MEM;
+
+    NOT_BASE:
+      if (GET_CODE (xtmp0) == PLUS) 
+	{
+	  ixreg = xtmp1;
+	  /* xtmp0 = xtmp0; */
+	}
+      else 
+	{
+	  ixreg = xtmp0;
+	  xtmp0 = xtmp1;
+	}
+
+      if (REG_CODE_INDEX_P (ixreg)) 
+	{
+	  scale = 1;
+	}
+      else if (REG_CODE_INDEX_P (XEXP (ixreg, 0))) 
+	{
+	  scale = INTVAL (XEXP (ixreg, 1));
+	  ixreg = XEXP (ixreg, 0);
+	}
+      else 
+	{			/* was else if with no condition. OK ??? */
+	  scale = INTVAL (XEXP (ixreg, 0));
+	  ixreg = XEXP (ixreg, 1);
+	}
+
+      if (REG_CODE_BASE_P (XEXP (xtmp0, 0))) 
+	{
+	  breg = XEXP (xtmp0, 0);
+	  offset = XEXP (xtmp0, 1);
+	}
+      else 
+	{
+	  breg = XEXP (xtmp0, 1);
+	  offset = XEXP (xtmp0, 0);
+	}
+
+    PRINT_MEM:
+      if (breg == 0 && ixreg == 0) 
+	{
+	  output_address (offset);
+	  break;
+	}
+      else if (ixreg == 0 && offset == 0) 
+	{
+	  fprintf (file, "%s", reg_names[REGNO (breg)]);
+	  break;
+	}
+      else 
+	{
+	  fprintf (file, "(");
+	  if (offset != 0) 
+	    {
+	      output_addr_const (file, offset);
+	      needcomma = 1;
+	    }
+	  if (breg != 0) 
+	    {
+	      if (needcomma)
+		fprintf (file, ",");
+	      fprintf (file, "%s", reg_names[REGNO (breg)]);
+	      needcomma = 1;
+	    }
+	  if (ixreg != 0) 
+	    {
+	      if (needcomma)
+		fprintf (file, ",");
+	      fprintf (file, "%s", reg_names[REGNO (ixreg)]);
+	      if (scale != 1)
+		fprintf (file,"*%d", scale);
+	    }
+	  fprintf (file, ")");
+
+	  break;
+	}
+
+    default:
+      output_addr_const (file, addr);
+    }
+}
+
+
+
+/* Return a REG that occurs in ADDR with coefficient 1.
+   ADDR can be effectively incremented by incrementing REG.  */
+
+static rtx
+find_addr_reg (addr)
+     rtx addr;
+{
+  while (GET_CODE (addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (addr, 0)) == REG)
+	addr = XEXP (addr, 0);
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	addr = XEXP (addr, 1);
+      else if (GET_CODE (XEXP (addr, 0)) == PLUS)
+	addr = XEXP (addr, 0);
+      else if (GET_CODE (XEXP (addr, 1)) == PLUS)
+	addr = XEXP (addr, 1);
+    }
+  if (GET_CODE (addr) == REG)
+    return addr;
+  return 0;
+}
+
+
+    /* Return the best assembler insn template
+    for moving operands[1] into operands[0] as a fullword.  */
+
+static char *
+singlemove_string (operands)
+     rtx *operands;
+{
+  if (FPU_REG_P (operands[0]) || FPU_REG_P (operands[1])) 
+    {
+      if (GREG_P (operands[0]) || GREG_P (operands[1])) 
+	{
+	  myabort (101);	/* Not Supported yet !! */
+	}
+      else 
+	{
+	  return "fmov.s %1,%0";
+	}
+    }
+  return "mov.w %1,%0";
+}
+
+
+/* Output assembler code to perform a doubleword move insn
+   with operands OPERANDS.  */
+
+char *
+output_move_double (operands)
+     rtx *operands;
+{
+  enum 
+    { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }
+  optype0, optype1;
+  rtx latehalf[2];
+  rtx addreg0 = 0, addreg1 = 0;
+
+  /* First classify both operands.  */
+
+  if (REG_P (operands[0]))
+    optype0 = REGOP;
+  else if (offsettable_memref_p (operands[0]))
+    optype0 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    optype0 = POPOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    optype0 = PUSHOP;
+  else if (GET_CODE (operands[0]) == MEM)
+    optype0 = MEMOP;
+  else
+    optype0 = RNDOP;
+
+  if (REG_P (operands[1]))
+    optype1 = REGOP;
+  else if (CONSTANT_P (operands[1]))
+    optype1 = CNSTOP;
+  else if (offsettable_memref_p (operands[1]))
+    optype1 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
+    optype1 = POPOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+    optype1 = PUSHOP;
+  else if (GET_CODE (operands[1]) == MEM)
+    optype1 = MEMOP;
+  else
+    optype1 = RNDOP;
+
+  /* Check for the cases that the operand constraints are not
+     supposed to allow to happen.  Abort if we get one,
+     because generating code for these cases is painful.  */
+
+  if (optype0 == RNDOP || optype1 == RNDOP)
+    myabort (102);
+
+  /* If one operand is decrementing and one is incrementing
+     decrement the former register explicitly
+     and change that operand into ordinary indexing.  */
+
+  if (optype0 == PUSHOP && optype1 == POPOP)
+    {
+      operands[0] = XEXP (XEXP (operands[0], 0), 0);
+      output_asm_insn ("sub.w %#8,%0", operands);
+      operands[0] = gen_rtx (MEM, DImode, operands[0]);
+      optype0 = OFFSOP;
+    }
+  if (optype0 == POPOP && optype1 == PUSHOP)
+    {
+      operands[1] = XEXP (XEXP (operands[1], 0), 0);
+      output_asm_insn ("sub.w %#8,%1", operands);
+      operands[1] = gen_rtx (MEM, DImode, operands[1]);
+      optype1 = OFFSOP;
+    }
+
+  /* If an operand is an unoffsettable memory ref, find a register
+     we can increment temporarily to make it refer to the second word.  */
+
+  if (optype0 == MEMOP)
+    addreg0 = find_addr_reg (operands[0]);
+
+  if (optype1 == MEMOP)
+    addreg1 = find_addr_reg (operands[1]);
+
+  /* Ok, we can do one word at a time.
+     Normally we do the low-numbered word first,
+     but if either operand is autodecrementing then we
+     do the high-numbered word first.
+     
+     In either case, set up in LATEHALF the operands to use
+     for the high-numbered word and in some cases alter the
+     operands in OPERANDS to be suitable for the low-numbered word.  */
+
+  if (optype0 == REGOP)
+    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  else if (optype0 == OFFSOP)
+    latehalf[0] = adj_offsettable_operand (operands[0], 4);
+  else
+    latehalf[0] = operands[0];
+
+  if (optype1 == REGOP)
+    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  else if (optype1 == OFFSOP)
+    latehalf[1] = adj_offsettable_operand (operands[1], 4);
+  else if (optype1 == CNSTOP)
+    {
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	split_double (operands[1], &operands[1], &latehalf[1]);
+      else if (CONSTANT_P (operands[1]))
+	latehalf[1] = const0_rtx;
+    }
+  else
+    latehalf[1] = operands[1];
+
+  /* If insn is effectively movd N(sp),-(sp) then we will do the
+     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
+     for the low word as well, to compensate for the first decrement of sp.  */
+  if (optype0 == PUSHOP
+      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
+      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
+    operands[1] = latehalf[1];
+
+  /* If one or both operands autodecrementing,
+     do the two words, high-numbered first.  */
+
+  /* Likewise,  the first move would clobber the source of the second one,
+     do them in the other order.  This happens only for registers;
+     such overlap can't happen in memory unless the user explicitly
+     sets it up, and that is an undefined circumstance.  */
+
+  if (optype0 == PUSHOP || optype1 == PUSHOP
+      || (optype0 == REGOP && optype1 == REGOP
+	  && REGNO (operands[0]) == REGNO (latehalf[1])))
+    {
+      /* Make any unoffsettable addresses point at high-numbered word.  */
+      if (addreg0)
+	output_asm_insn ("add.w %#4,%0", &addreg0);
+      if (addreg1)
+	output_asm_insn ("add.w %#4,%0", &addreg1);
+
+      /* Do that word.  */
+      output_asm_insn (singlemove_string (latehalf), latehalf);
+
+      /* Undo the adds we just did.  */
+      if (addreg0)
+	output_asm_insn ("sub.w %#4,%0", &addreg0);
+      if (addreg1)
+	output_asm_insn ("sub.w %#4,%0", &addreg1);
+
+      /* Do low-numbered word.  */
+      return singlemove_string (operands);
+    }
+
+  /* Normal case: do the two words, low-numbered first.  */
+
+  output_asm_insn (singlemove_string (operands), operands);
+
+  /* Make any unoffsettable addresses point at high-numbered word.  */
+  if (addreg0)
+    output_asm_insn ("add.w %#4,%0", &addreg0);
+  if (addreg1)
+    output_asm_insn ("add.w %#4,%0", &addreg1);
+
+  /* Do that word.  */
+  output_asm_insn (singlemove_string (latehalf), latehalf);
+
+  /* Undo the adds we just did.  */
+  if (addreg0)
+    output_asm_insn ("sub.w %#4,%0", &addreg0);
+  if (addreg1)
+    output_asm_insn ("sub.w %#4,%0", &addreg1);
+
+  return "";
+}
+
+/* Move const_double to floating point register (DF) */
+char *
+output_move_const_double (operands)
+     rtx *operands;
+{
+  int code = standard_fpu_constant_p (operands[1]);
+
+  if (FPU_REG_P (operands[0])) 
+    {
+      if (code != 0)
+	{
+	  static char buf[40];
+
+	  sprintf (buf, "fmvr from%d,%%0.d", code);
+	  return buf;
+	}
+      else 
+	{
+	  return "fmov %1,%0.d";
+	}
+    }
+  else if (GREG_P (operands[0])) 
+    {
+      rtx xoperands[2];
+      xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+      output_asm_insn ("mov.w %1,%0", xoperands);
+      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+      return "mov.w %1,%0";
+    }
+  else 
+    {
+      return output_move_double (operands); /* ?????? */
+    }
+}
+
+char *
+output_move_const_single (operands)
+     rtx *operands;
+{
+  int code = standard_fpu_constant_p (operands[1]);
+  static char buf[40];
+
+  if (FPU_REG_P (operands[0])) 
+    {
+      if (code != 0)
+	{
+	  sprintf (buf, "fmvr from%d,%%0.s", code);
+	  return buf;
+	}
+      return "fmov.s %f1,%0";
+    }
+  else 
+    return "mov.w %f1,%0";
+}
+
+
+/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
+   from the "fmvr" instruction of the Gmicro FPU.
+   The value, anded with 0xff, gives the code to use in fmovecr
+   to get the desired constant.  */
+
+  u.i[0] = CONST_DOUBLE_LOW (x);
+  u.i[1] = CONST_DOUBLE_HIGH (x);
+  d = u.d;
+
+  if (d == 0.0)			/* +0.0 */
+    return 0x0;
+  /* Note: there are various other constants available
+     but it is a nuisance to put in their values here.  */
+  if (d == 1.0)			/* +1.0 */
+    return 0x1;
+
+  /*
+   * Stuff that looks different if it's single or double
+   */
+  if (GET_MODE (x) == SFmode)
+    {
+      if (d == S_PI)
+	return 0x2;
+      if (d == (S_PI / 2.0))
+	return 0x3;
+      if (d == S_E)
+	return 0x4;
+      if (d == S_LOGEof2)
+	return 0x5;
+      if (d == S_LOGEof10)
+	return 0x6;
+      if (d == S_LOG10of2)
+	return 0x7;
+      if (d == S_LOG10ofE)
+	return 0x8;
+      if (d == S_LOG2ofE)
+	return 0x9;
+    }
+  else
+    {
+      if (d == D_PI)
+	return 0x2;
+      if (d == (D_PI / 2.0))
+	return 0x3;
+      if (d == D_E)
+	return 0x4;
+      if (d == D_LOGEof2)
+	return 0x5;
+      if (d == D_LOGEof10)
+	return 0x6;
+      if (d == D_LOG10of2)
+	return 0x7;
+      if (d == D_LOG10ofE)
+	return 0x8;
+      if (d == D_LOG2ofE)
+	return 0x9;
+    }
+
+  return 0;
+}
+
+#undef S_PI
+#undef D_PI
+#undef S_E
+#undef D_E
+#undef S_LOGEof2
+#undef D_LOGEof2
+#undef S_LOGEof10
+#undef D_LOGEof10
+#undef S_LOG10of2
+#undef D_LOG10of2
+#undef S_LOG10ofE
+#undef D_LOG10ofE
+#undef S_LOG2ofE
+#undef D_LOG2ofE
+
+/* dest should be operand 0 */
+/* imm should be operand 1 */
+
+extern char *sub_imm_word ();
+
+char *
+add_imm_word (imm, dest, immp)
+     int imm;
+     rtx dest, *immp;
+{
+  int is_reg, short_ok;
+
+
+  if (imm < 0) 
+    {
+      *immp = GEN_INT (-imm);
+      return sub_imm_word (-imm, dest);
+    }
+    
+  if (imm == 0)
+    return "mov:l.w #0,%0";
+    
+  short_ok = short_format_ok (dest);
+
+  if (short_ok && imm <= 8)
+    return "add:q %1,%0.w";
+
+  if (imm < 128)
+    return "add:e %1,%0.w";
+
+  is_reg = (GET_CODE (dest) == REG);
+
+  if (is_reg)
+    return "add:l %1,%0.w";
+    
+  if (short_ok)
+    return "add:i %1,%0.w";
+    
+  return "add %1,%0.w";
+}
+
+char *
+sub_imm_word (imm, dest, immp)
+     int imm;
+     rtx dest, *immp;
+{
+  int is_reg, short_ok;
+
+  if (imm < 0 &&  imm != 0x80000000) 
+    {
+      *immp = GEN_INT (-imm);
+      return add_imm_word (-imm, dest);
+    }
+    
+  if (imm == 0)
+    return "mov:z.w #0,%0";
+    
+  short_ok = short_format_ok (dest);
+
+  if (short_ok && imm <= 8)
+    return "sub:q %1,%0.w";
+
+  if (imm < 128)
+    return "sub:e %1,%0.w";
+
+  is_reg = (GET_CODE (dest) == REG);
+
+  if (is_reg)
+    return "sub:l %1,%0.w";
+    
+  if (short_ok)
+    return "sub:i %1,%0.w";
+    
+  return "sub %1,%0.w";
+}
+
+int
+short_format_ok (x)
+     rtx x;
+{
+  rtx x0, x1;
+
+  if (GET_CODE (x) == REG)
+    return 1;
+
+  if (GET_CODE (x) == MEM 
+      && GET_CODE (XEXP (x, 0)) == PLUS) 
+    {
+      x0 = XEXP (XEXP (x, 0), 0);
+      x1 = XEXP (XEXP (x, 0), 1);
+      return ((GET_CODE (x0) == REG
+	       && CONSTANT_P (x1)
+	       && ((unsigned) (INTVAL (x1) + 0x8000)  < 0x10000))
+	      ||
+	      (GET_CODE (x1) == REG
+	       && CONSTANT_P (x0)
+	       && ((unsigned) (INTVAL (x0) + 0x8000)  < 0x10000)));
+    }
+
+  return 0;
+}
+
+myoutput_sp_adjust (file, op, fsize)
+     FILE *file;
+     char *op;
+     int fsize;
+{
+  if (fsize == 0)
+    ;
+  else if (fsize < 8)
+    fprintf (file, "\t%s:q #%d,sp.w\n", op, fsize);
+  else if (fsize < 128)
+    fprintf (file, "\t%s:e #%d,sp.w\n", op, fsize);
+  else
+    fprintf (file, "\t%s:l #%d,sp.w\n", op, fsize);
+}
+
+
+char *
+mov_imm_word (imm, dest)
+     int imm;
+     rtx dest;
+{
+  int is_reg, short_ok;
+
+  if (imm == 0)
+    return "mov:z.w #0,%0";
+    
+  short_ok = short_format_ok (dest);
+
+  if (short_ok && imm > 0 && imm <= 8)
+    return "mov:q %1,%0.w";
+
+  if (-128 <= imm && imm < 128)
+    return "mov:e %1,%0.w";
+
+  is_reg = (GET_CODE (dest) == REG);
+
+  if (is_reg)
+    return "mov:l %1,%0.w";
+    
+  if (short_ok)
+    return "mov:i %1,%0.w";
+    
+  return "mov %1,%0.w";
+}
+
+char *
+cmp_imm_word (imm, dest)
+     int imm;
+     rtx dest;
+{
+  int is_reg, short_ok;
+
+  if (imm == 0)
+    return "cmp:z.w #0,%0";
+    
+  short_ok = short_format_ok (dest);
+
+  if (short_ok && imm >0 && imm <= 8)
+    return "cmp:q %1,%0.w";
+
+  if (-128 <= imm && imm < 128)
+    return "cmp:e %1,%0.w";
+
+  is_reg = (GET_CODE (dest) == REG);
+
+  if (is_reg)
+    return "cmp:l %1,%0.w";
+    
+  if (short_ok)
+    return "cmp:i %1,%0.w";
+    
+  return "cmp %1,%0.w";
+}
+
+char *
+push_imm_word (imm)
+     int imm;
+{
+  if (imm == 0)
+    return "mov:z.w #0,%-";
+    
+  if (imm > 0 && imm <= 8)
+    return "mov:q %1,%-.w";
+
+  if (-128 <= imm && imm < 128)
+    return "mov:e %1,%-.w";
+
+  return "mov:g %1,%-.w";
+    
+  /* In some cases, g-format may be better than I format.??
+     return "mov %1,%0.w";
+     */
+}
+
+my_signed_comp (insn)
+     rtx insn;
+{
+  rtx my_insn;
+
+  my_insn = NEXT_INSN (insn);
+  if (GET_CODE (my_insn) != JUMP_INSN) 
+    {
+      fprintf (stderr, "my_signed_comp: Not Jump_insn ");
+      myabort (GET_CODE (my_insn));
+    }
+  my_insn = PATTERN (my_insn);
+  if (GET_CODE (my_insn) != SET) 
+    {
+      fprintf (stderr, "my_signed_comp: Not Set ");
+      myabort (GET_CODE (my_insn));
+    }
+  my_insn = SET_SRC (my_insn);
+  if (GET_CODE (my_insn) != IF_THEN_ELSE) 
+    {
+      fprintf (stderr, "my_signed_comp: Not if_then_else ");
+      myabort (GET_CODE (my_insn));
+    }
+  switch (GET_CODE (XEXP (my_insn, 0)))
+    {
+    case NE:
+    case EQ:
+    case GE:
+    case GT:
+    case LE:
+    case LT:
+      return 1;
+    case GEU:
+    case GTU:
+    case LEU:
+    case LTU:
+      return 0;
+    }
+  fprintf (stderr, "my_signed_comp: Not cccc ");
+  myabort (GET_CODE (XEXP (my_insn, 0)));
+}
diff --git a/gnu/egcs/gcc/config/gmicro/gmicro.h b/gnu/egcs/gcc/config/gmicro/gmicro.h
new file mode 100644
index 00000000000..789ca843982
--- /dev/null
+++ b/gnu/egcs/gcc/config/gmicro/gmicro.h
@@ -0,0 +1,1588 @@
+/* Definitions of target machine for GNU compiler.  Gmicro (TRON) version.
+   Copyright (C) 1987, 88, 89, 95, 96, 1997 Free Software Foundation, Inc.
+   Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
+   (yuhara@flab.fujitsu.co.jp)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.   */
+
+
+/* Note that some other tm.h files include this one and then override
+   many of the definitions that relate to assembler syntax.  */
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"
+
+/* #define CPP_SPEC    ** currently not defined **/
+
+/* #define CC1_SPEC    ** currently not defined **/
+
+
+/* Print subsidiary information on the compiler version in use.  */
+/*
+#define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
+*/
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+
+/* Macros used in the machine description to test the flags.  */
+
+/* Compile for a Gmicro/300.  */
+#define TARGET_G300 (target_flags & 1)
+/* Compile for a Gmicro/200. */
+#define TARGET_G200 (target_flags & 2)
+/* Compile for a Gmicro/100. */
+#define TARGET_G100 (target_flags & 4)
+
+/* Compile FPU insns for floating point (not library calls).  */
+#define TARGET_FPU (target_flags & 8)
+
+/* Pop up arguments by called function. */
+#define TARGET_RTD (target_flags & 0x10)
+
+/* Compile passing first args in regs 0 and 1.
+   This exists only to test compiler features that will be needed for
+   RISC chips. It is not usable and is not intended to be usable on
+   this cpu ;-< */
+#define TARGET_REGPARM (target_flags & 0x20)
+
+#define TARGET_BITFIELD (target_flags & 0x40)
+
+#define TARGET_NEWRETURN (target_flags & 0x80)
+
+/* Do not expand __builtin_smov (strcpy) to multiple movs.
+   Use the smov instruction. */
+#define TARGET_FORCE_SMOV (target_flags & 0x100)
+
+/* default options are -m300, -mFPU,
+   with bitfield instructions added because it won't always work otherwise.
+   If there are versions of the gmicro that don't support bitfield instructions
+   then it will take some thinking to figure out how to make them work.  */
+#define TARGET_DEFAULT 0x49
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES  \
+  { { "g300", 1},				\
+    { "g200", 2},				\
+    { "g100", 4},				\
+    { "fpu", 8},				\
+    { "soft-float", -8},			\
+    { "rtd", 0x10},				\
+    { "no-rtd", -0x10},				\
+    { "regparm", 0x20},				\
+    { "no-regparm", -0x20},			\
+#if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
+	 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions.  */
+    { "bitfield", 0x40},			\
+    { "no-bitfield", -0x40},			\
+#endif
+    { "newreturn", 0x80},			\
+    { "no-newreturn", -0x80},			\
+    { "force-smov", 0x100},			\
+    { "no-force-smov", -0x100},			\
+    { "", TARGET_DEFAULT}}
+
+
+/* Blow away G100 flag silently off TARGET_fpu (since we can't clear
+   any bits in TARGET_SWITCHES above) */
+#define OVERRIDE_OPTIONS		\
+{					\
+  if (TARGET_G100) target_flags &= ~8;	\
+}
+
+/* target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is true for Gmicro insns.
+   We make it true always by avoiding using the single-bit insns
+   except in special cases with constant bit numbers.  */
+#define BITS_BIG_ENDIAN 1
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+/* That is true on the Gmicro.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+/* For Gmicro we can decide arbitrarily
+   since there are no machine instructions for them.  ????? */
+#define WORDS_BIG_ENDIAN 0
+
+/* number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register. */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 32
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+/* Instructions of the Gmicro should be on half-word boundary */
+/* But word boundary gets better performance */
+#define FUNCTION_BOUNDARY 32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* No data type wants to be aligned rounder than this. */
+/* This is not necessarily 32 on the Gmicro */
+#define BIGGEST_ALIGNMENT 32
+
+/* Set this non-zero if move instructions will actually fail to work
+   when given unaligned data.
+   Unaligned data is allowed on Gmicro, though the access is slow. */
+
+#define STRICT_ALIGNMENT 1
+#define SLOW_UNALIGNED_ACCESS 1
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+  (TREE_CODE (EXP) == STRING_CST	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Define number of bits in most basic integer type.
+   (If undefined, default is BITS_PER_WORD).  */
+#define INT_TYPE_SIZE 32
+
+/* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
+
+/* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
+
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+   For the Gmicro, we give the general registers numbers 0-15,
+   and the FPU floating point registers numbers 16-31.  */
+#define FIRST_PSEUDO_REGISTER 32
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+   On the Gmicro, the stack pointer and the frame pointer are
+   such registers.  */
+/* frame pointer is not indicated as fixed, because fp may be used freely
+   when a frame is not built. */
+#define FIXED_REGISTERS  \
+ {0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 1, \
+  /* FPU registers.  */   \
+  0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, }
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+#define CALL_USED_REGISTERS \
+ {1, 1, 1, 1, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 1, \
+  /* FPU registers.  */   \
+  1, 1, 1, 1, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, }
+
+
+/* Make sure everything's fine if we *don't* have a given processor.
+   This assumes that putting a register in fixed_regs will keep the
+   compilers mitt's completely off it.  We don't bother to zero it out
+   of register classes.  If TARGET_FPU is not set,
+   the compiler won't touch since no instructions that use these
+   registers will be valid.  */
+/*  This Macro is not defined now.
+    #define CONDITIONAL_REGISTER_USAGE */
+
+/* The Gmicro has no overlapping register */
+/* #define OVERLAPPING_REGNO_P(REGNO) */
+
+/* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO)  */
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On the Gmicro, ordinary registers hold 32 bits worth;
+   for the Gmicro/FPU registers, a single register is always enough for
+   anything that can be stored in them at all.  */
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  ((REGNO) >= 16 ? 1				\
+   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   On the Gmicro, the cpu registers can hold any mode but the FPU registers
+   can hold only SFmode or DFmode.  And the FPU registers can't hold anything
+   if FPU use is disabled. */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+  ((REGNO) < 16								\
+   || ((REGNO) < 32							\
+       ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT ||		\
+			GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)	\
+       : 0 ))
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2)			\
+  (! TARGET_FPU						\
+   || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||		\
+	GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
+       == ((MODE2) == SFmode || (MODE2) == DFmode)))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* Gmicro pc isn't overloaded on a register.  */
+/* #define PC_REGNUM  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 14
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 0
+
+/* Base register for access to arguments of the function.  */
+/* The Gmicro does not have hardware ap. Fp is treated as ap */
+#define ARG_POINTER_REGNUM 14
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM 0
+
+/* Register in which address to store a structure value
+   is passed to a function.  */
+#define STRUCT_VALUE_REGNUM 1
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+/* The Gmicro has two kinds of registers, so four classes would be
+   a complete set.  */
+
+enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+   { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS \
+{						\
+     0,			/* NO_REGS */		\
+     0xffff0000,	/* FPU_REGS */		\
+     0x0000ffff,	/* GENERAL_REGS */	\
+     0xffffffff		/* ALL_REGS */		\
+}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+extern enum reg_class regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
+
+/* The class value for index registers, and the one for base regs.  */
+
+#define INDEX_REG_CLASS GENERAL_REGS
+#define BASE_REG_CLASS  GENERAL_REGS
+  
+/* Get reg_class from a letter such as appears in the machine description.
+   We do a trick here to modify the effective constraints on the
+   machine description; we zorch the constraint letters that aren't
+   appropriate for a specific target.  This allows us to guarantee
+   that a specific kind of register will not be used for a given target
+   without fiddling with the register classes above. */
+
+#define REG_CLASS_FROM_LETTER(C) \
+  ((C) == 'r' ? GENERAL_REGS :			\
+   ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) :	\
+     NO_REGS))
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+
+   For the Gmicro, all immediate value optimizations are done 
+   by assembler, so no machine dependent definition is necessary ??? */
+
+/* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
+#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
+
+/*
+ * The letters G defines all of the floating constants tha are *NOT*
+ * Gmicro-FPU constant.
+ */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
+    ((C) == 'F' ||				\
+     (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class. */
+/* On the Gmicro series, there is no restriction on GENERAL_REGS,
+   so CLASS is returned. I do not know whether I should treat FPU_REGS
+   specially or not (at least, m68k does not). */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+/* On the Gmicro, this is the size of MODE in words,
+   except in the FPU regs, where a single reg is always enough.  */
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+ ((CLASS) == FPU_REGS ? \
+   1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+/* On the Gmicro, FP points to the old FP and the first local variables are
+   at (FP - 4). */
+#define STARTING_FRAME_OFFSET 0
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by. */
+/* On the Gmicro, sp is decremented by the exact size of the operand */
+#define PUSH_ROUNDING(BYTES) (BYTES)
+
+/* Offset of first parameter from the argument pointer register value.  */
+/* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
+#define FIRST_PARM_OFFSET(FNDECL) 8
+
+/* Value is the number of byte of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack. 
+
+   On the Gmicro, the EXITD insn may be used to pop them if the number
+   of args is fixed, but if the number is variable then the caller must pop
+   them all. The adjsp operand of the EXITD insn can't be used for library
+   calls now because the library is compiled with the standard compiler.
+   Use of adjsp operand is a selectable option, since it is incompatible with
+   standard Unix calling sequences.  If the option is not selected,
+   the caller must always pop the args.
+   On the m68k this is an RTD option, so I use the same name
+   for the Gmicro. The option name may be changed in the future. */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
+  ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE)	\
+    && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
+	|| (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
+	    == void_type_node)))					\
+   ? (SIZE) : 0)
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+/* On the Gmicro the floating return value is in fr0 not r0.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)  LIBCALL_VALUE (TYPE_MODE (VALTYPE))
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+#define LIBCALL_VALUE(MODE)	\
+  (gen_rtx (REG, (MODE),		\
+    ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
+
+
+/* 1 if N is a possible register number for a function value.
+   On the Gmicro, r0 and fp0 are the possible registers.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
+
+/* Define this if PCC uses the nonreentrant convention for returning
+   structure and union values.  */
+
+#define PCC_STATIC_STRUCT_RETURN
+
+/* 1 if N is a possible register number for function argument passing.
+   On the Gmicro, no registers are used in this way.  */
+/* Really? For the performance improvement, registers should be used !! */
+
+#define FUNCTION_ARG_REGNO_P(N) 0
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the Gmicro, this is a single integer, which is a number of bytes
+   of arguments scanned so far.  */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On the Gmicro, the offset starts at 0.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
+ ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) += ((MODE) != BLKmode			\
+	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
+	    : (int_size_in_bytes (TYPE) + 3) & ~3))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+/* On the Gmicro all args are pushed, except if -mregparm is specified
+   then the first two words of arguments are passed in d0, d1.
+   *NOTE* -mregparm does not work.
+   It exists only to test register calling conventions.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+((TARGET_REGPARM && (CUM) < 8					\
+  && 8 < ((CUM) + ((MODE) == BLKmode				\
+		      ? int_size_in_bytes (TYPE)		\
+		      : GET_MODE_SIZE (MODE))))  		\
+ ? 2 - (CUM) / 4 : 0)
+
+/* The following macro is defined to output register list.
+   The LSB of Mask is the lowest number register.
+   Regoff is MY_GREG_OFF or MY_FREG_OFF.
+   Do NOT use <i> in File, Mask, Regoff !!
+   Should be changed from macros to functions.    M.Yuhara */
+
+#define MY_GREG_OFF 0
+#define MY_FREG_OFF 16
+
+#define MY_PRINT_MASK(File, Mask, Regoff)		\
+{							\
+    int i, first = -1;					\
+    if ((Mask) == 0) {					\
+	fprintf(File, "#0");				\
+    } else {						\
+	fprintf(File, "(");				\
+	for (i = 0; i < 16; i++) {			\
+	    if ( (Mask) & (1 << i) ) {			\
+		if (first < 0) {			\
+		    if (first == -2) {			\
+			fprintf(File, ",");		\
+		    }					\
+		    first = i;				\
+		    fprintf(File, "%s", reg_names[Regoff + i]);	\
+		}					\
+	    } else if (first >= 0) {			\
+		if (i > first + 1) {			\
+		    fprintf(File, "-%s", reg_names[Regoff + i - 1]);	\
+		}					\
+		first = -2;				\
+	    }						\
+	}						\
+	if ( (first >= 0) && (first != 15) )		\
+	    fprintf(File, "-%s", reg_names[Regoff + 15]);\
+	fprintf(File, ")");				\
+    }							\
+}
+
+
+#define MY_PRINT_ONEREG_L(FILE,MASK)		\
+{   register int i;				\
+    for (i = 0; i < 16; i++)			\
+	if ( (1 << i) & (MASK)) {		\
+	    fprintf(FILE, "%s", reg_names[i]);	\
+	    (MASK) &= ~(1 << i);		\
+	    break;				\
+	}					\
+}
+
+
+#define MY_PRINT_ONEREG_H(FILE,MASK)		\
+{   register int i;				\
+    for (i = 15; i >= 0; i--)			\
+	if ( (1 << i) & (MASK)) {		\
+	    fprintf(FILE, "%s", reg_names[i]);	\
+	    (MASK) &= ~(1 << i);		\
+	    break;				\
+	}					\
+}
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+/* The next macro needs much optimization !!
+   M.Yuhara */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE)     \
+{ register int regno;						\
+  register int mask = 0;					\
+  register int nregs = 0;					\
+  static char *reg_names[] = REGISTER_NAMES;			\
+  extern char call_used_regs[];					\
+  int fsize = ((SIZE) + 3) & -4;				\
+  for (regno = 0; regno < 16; regno++)				\
+    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
+	mask |= (1 << regno);					\
+	nregs++;						\
+    }								\
+  if (frame_pointer_needed) {					\
+    mask &= ~(1 << FRAME_POINTER_REGNUM);			\
+    if (nregs > 4) {						\
+	fprintf(FILE, "\tenter.w #%d,", fsize);			\
+	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
+	fprintf(FILE,"\n");					\
+    } else {							\
+	fprintf(FILE, "\tmov.w fp,@-sp\n");			\
+	fprintf(FILE, "\tmov.w sp,fp\n");			\
+	if (fsize > 0)						\
+	    myoutput_sp_adjust(FILE, "sub", fsize);		\
+	while (nregs--) {					\
+	    fprintf(FILE, "\tmov.w ");				\
+	    MY_PRINT_ONEREG_H(FILE, mask);			\
+	    fprintf(FILE, ",@-sp\n");				\
+	}							\
+    }								\
+  } else {							\
+    if (fsize > 0)						\
+	myoutput_sp_adjust(FILE, "sub", fsize);			\
+    if (mask != 0) {						\
+	if (nregs > 4) {					\
+	    fprintf(FILE, "\tstm.w ");				\
+	    MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);		\
+	    fprintf(FILE, ",@-sp\n");				\
+	} else {						\
+	    while (nregs--) {					\
+		fprintf(FILE, "\tmov.w ");			\
+		MY_PRINT_ONEREG_H(FILE, mask);			\
+		fprintf(FILE, ",@-sp\n");			\
+	    }							\
+	}							\
+    }								\
+  }								\
+  mask = 0;							\
+  for (regno = 16; regno < 32; regno++)				\
+        if (regs_ever_live[regno] && !call_used_regs[regno])	\
+            mask |= 1 << (regno - 16);				\
+  if (mask != 0) {						\
+	fprintf(FILE, "\tfstm.w ");				\
+	MY_PRINT_MASK(FILE, mask, MY_FREG_OFF);			\
+	fprintf(FILE, ",@-sp\n", mask);				\
+  }								\
+}
+
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+/* ??? M.Yuhara */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)  \
+  fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
+
+/* Output assembler code to FILE to initialize this source file's
+   basic block profiling info, if that has not already been done.  */
+
+#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
+  fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n",  \
+	   LABELNO, LABELNO);
+
+/* Output assembler code to FILE to increment the entry-count for
+   the BLOCKNO'th basic block in this source file.  */
+
+#define BLOCK_PROFILER(FILE, BLOCKNO)	\
+  fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer (when
+   frame_pinter_needed)  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+
+/* The Gmicro FPU seems to be unable to fldm/fstm double or single
+   floating. It only allows extended !! */
+/* Optimization is not enough, especially FREGs load !! M.Yuhara */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE) \
+{ register int regno;						\
+  register int mask, fmask;					\
+  register int nregs, nfregs;					\
+  int offset, foffset;						\
+  extern char call_used_regs[];					\
+  static char *reg_names[] = REGISTER_NAMES;			\
+  int fsize = ((SIZE) + 3) & -4;				\
+  FUNCTION_EXTRA_EPILOGUE (FILE, SIZE);				\
+  nfregs = 0;  fmask = 0; 					\
+  for (regno = 16; regno < 31; regno++)				\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
+      { nfregs++; fmask |= 1 << (regno - 16); }			\
+  foffset = nfregs * 12;					\
+  nregs = 0;  mask = 0;						\
+  if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
+  for (regno = 0; regno < 16; regno++)				\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
+      { nregs++; mask |= 1 << regno; }				\
+  if (frame_pointer_needed) {					\
+    offset = nregs * 4 + fsize;					\
+    if (nfregs > 0) {						\
+	fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
+	MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF);		\
+	fprintf(FILE, "\n");					\
+    }								\
+    if (nregs > 4						\
+	|| current_function_pops_args) {			\
+	fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset);		\
+	fprintf(FILE, "\texitd ");				\
+	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
+	fprintf(FILE, ",#%d\n", current_function_pops_args);	\
+    } else {							\
+	while (nregs--) {					\
+	    fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset);	\
+	    MY_PRINT_ONEREG_L(FILE, mask);			\
+	    fprintf(FILE, "\n");				\
+	    offset -= 4;					\
+	}							\
+	if (TARGET_NEWRETURN) {					\
+	    fprintf(FILE, "\tmova.w @(4,fp),sp\n");		\
+	    fprintf(FILE, "\tmov:l.w @fp,fp\n");		\
+	} else {						\
+	    fprintf(FILE, "\tmov.w fp,sp\n");			\
+	    fprintf(FILE, "\tmov.w @sp+,fp\n");			\
+	}							\
+	fprintf(FILE, "\trts\n");				\
+    }								\
+  } else {							\
+    if (nfregs > 0) {						\
+	fprintf(FILE, "\tfldm.w @sp+,");			\
+	MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF);		\
+	fprintf(FILE, "\n");					\
+    }								\
+    if (nregs > 4) {						\
+	fprintf(FILE, "\tldm.w @sp+,");				\
+	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
+	fprintf(FILE, "\n");					\
+    } else {							\
+	while (nregs--) {					\
+	    fprintf(FILE, "\tmov.w @sp+,");			\
+	    MY_PRINT_ONEREG_L(FILE,mask);			\
+	    fprintf(FILE, "\n");				\
+	}							\
+    }								\
+      if (current_function_pops_args) {				\
+	myoutput_sp_adjust(FILE, "add", 			\
+	    (fsize + 4 + current_function_pops_args));		\
+	fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
+    } else {							\
+	if (fsize > 0)						\
+	    myoutput_sp_adjust(FILE, "add", fsize);		\
+	fprintf(FILE, "\trts\n");				\
+    }								\
+  }								\
+}
+
+/* This is a hook for other tm files to change.  */
+#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
+
+/* If the memory address ADDR is relative to the frame pointer,
+   correct it to be relative to the stack pointer instead.
+   This is for when we don't use a frame pointer.
+   ADDR should be a variable name.  */
+
+/* You have to change the next macro if you want to use more complex
+   addressing modes (such as double indirection and  more than one
+   chain-addressing stages). */
+
+#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH)  \
+{ int offset = -1;							\
+  rtx regs = stack_pointer_rtx;						\
+  if (ADDR == frame_pointer_rtx)					\
+    offset = 0;								\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
+	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
+    offset = INTVAL (XEXP (ADDR, 1));					\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
+    { rtx other_reg = XEXP (ADDR, 1);					\
+      offset = 0;							\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
+    { rtx other_reg = XEXP (ADDR, 0);					\
+      offset = 0;							\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  else if (GET_CODE (ADDR) == PLUS					\
+	   && GET_CODE (XEXP (ADDR, 0)) == PLUS				\
+	   && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx		\
+	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
+    { rtx other_reg = XEXP (XEXP (ADDR, 0), 1);				\
+      offset = INTVAL (XEXP (ADDR, 1));					\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  else if (GET_CODE (ADDR) == PLUS					\
+	   && GET_CODE (XEXP (ADDR, 0)) == PLUS				\
+	   && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx		\
+	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
+    { rtx other_reg = XEXP (XEXP (ADDR, 0), 0);				\
+      offset = INTVAL (XEXP (ADDR, 1));					\
+      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
+  if (offset >= 0)							\
+    { int regno;							\
+      extern char call_used_regs[];					\
+      for (regno = 16; regno < 32; regno++)				\
+        if (regs_ever_live[regno] && ! call_used_regs[regno])		\
+          offset += 12;							\
+      for (regno = 0; regno < 16; regno++)				\
+	if (regs_ever_live[regno] && ! call_used_regs[regno])		\
+	  offset += 4;							\
+      offset -= 4;							\
+      ADDR = plus_constant (regs, offset + (DEPTH)); } }
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
+
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+/* Gmicro */
+#define REGNO_OK_FOR_GREG_P(REGNO) \
+((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
+#define REGNO_OK_FOR_FPU_P(REGNO) \
+(((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
+#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
+
+/* Now macros that check whether X is a register and also,
+   strictly, whether it is in a specified class.
+
+   These macros are specific to the Gmicro, and may be used only
+   in code for printing assembler insns and in conditions for
+   define_optimization.  */
+
+/* 1 if X is an fpu register.  */
+
+#define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
+
+/* I used GREG_P in the gmicro.md file. */
+
+#ifdef REG_OK_STRICT
+#define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
+#else
+#define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
+#endif
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+/* The Gmicro allows more registers in the chained addressing mode.
+   But I do not know gcc supports such an architecture. */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)   \
+  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
+   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
+   || GET_CODE (X) == HIGH)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_CONSTANT_P(X) 1
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* The gcc uses the following effective address of the Gmicro.
+					       (without using PC!!).
+   {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
+	where
+		@:     memory indirection.
+		Rbase: Base Register = General Register.
+		Disp:  Displacement (up to 32bits)
+		Rindex: Index Register = General Register.
+		[1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
+		The inside of { } can be omitted.
+    This restricts the chained addressing up to 1 stage.  */
+
+
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
+   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
+
+#define REG_CODE_BASE_P(X) \
+  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
+
+#define REG_CODE_INDEX_P(X) \
+  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
+
+/* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
+#define BASE_PLUS_DISP_P(X) \
+   ( REG_CODE_BASE_P (XEXP (X, 0)) 		\
+     && CONSTANT_ADDRESS_P (XEXP (X, 1))	\
+    ||						\
+     REG_CODE_BASE_P (XEXP (X, 1)) 		\
+     && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
+
+/* 1 if X is {0,Rbase} + {0,disp}.  */
+#define BASED_ADDRESS_P(X)  \
+  (CONSTANT_ADDRESS_P (X)	\
+   || REG_CODE_BASE_P (X)	\
+   || (GET_CODE (X) == PLUS)	\
+       && BASE_PLUS_DISP_P (X))
+
+/* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
+#define SCALE_OF_INDEX_P(X) \
+  ( INTVAL(X) == 4	\
+    || INTVAL(X) == 2	\
+    || INTVAL(X) == 8	\
+    || INTVAL(X) == 1 )
+
+/* #define INDEX_TERM_P(X,MODE)  */
+#define INDEX_TERM_P(X)  \
+  ( REG_CODE_INDEX_P(X)					\
+    || (GET_CODE (X) == MULT				\
+	&& ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
+	     ( ( (GET_CODE (xfoo0) == CONST_INT)	\
+	       && SCALE_OF_INDEX_P (xfoo0)		\
+	       && REG_CODE_INDEX_P (xfoo1) )		\
+	      ||					\
+	       ( (GET_CODE (xfoo1) == CONST_INT)		\
+	       && SCALE_OF_INDEX_P (xfoo1)		\
+	       && REG_CODE_INDEX_P (xfoo0) ) ))))
+
+/* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
+#define BASE_DISP_INDEX_P(X)  \
+  ( BASED_ADDRESS_P (X)							\
+   || ( (GET_CODE (X) == PLUS)						\
+      && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)),		\
+	  (REG_CODE_BASE_P (xboo0)					\
+	    && (GET_CODE (xboo1) == PLUS)				\
+	    && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0))			\
+		   && INDEX_TERM_P (XEXP (xboo1, 1)) )			\
+	         || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1))		\
+		     && INDEX_TERM_P (XEXP (xboo1, 0))) )))		\
+	 ||								\
+	  (CONSTANT_ADDRESS_P (xboo0)					\
+	    && (GET_CODE (xboo1) == PLUS)				\
+	    && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0))			\
+	 	   && INDEX_TERM_P (XEXP (xboo1, 1)) )			\
+	         || ( REG_CODE_BASE_P (XEXP (xboo1, 1))			\
+		      && INDEX_TERM_P (XEXP (xboo1, 0))) ))		\
+	||								\
+	  (INDEX_TERM_P (xboo0)						\
+	    && ( ( (GET_CODE (xboo1) == PLUS)				\
+	          && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0))		\
+		      && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) )		\
+	               || ( REG_CODE_BASE_P (XEXP (xboo1, 1))   	\
+		      && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) ))	\
+		||							\
+		 (CONSTANT_ADDRESS_P (xboo1))				\
+		||							\
+		 (REG_CODE_BASE_P (xboo1)) )))))
+
+/*
+	If you want to allow double-indirection,
+	you have to change the <fp-relative> => <sp-relative> conversion
+	routine. M.Yuhara
+
+#ifdef REG_OK_STRICT
+#define DOUBLE_INDIRECTION(X,ADDR) {\
+    if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
+    }
+#else
+#define DOUBLE_INDIRECTION(X,ADDR) { }
+#endif
+*/
+
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
+  register rtx xboo0, xboo1, xfoo0, xfoo1;		\
+  if (GET_CODE (X) == MEM) { 				\
+    /*							\
+    if (GET_CODE (XEXP (X,0)) == MEM) {			\
+	DOUBLE_INDIRECTION(X,ADDR);			\
+    } else {						\
+	if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR;	\
+    }							\
+    */							\
+  } else {						\
+	if (BASE_DISP_INDEX_P (X)) goto ADDR;		\
+	if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)	\
+	    && REG_P (XEXP (X, 0))					\
+	    && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM))		\
+		goto ADDR;						\
+  }							\
+}
+
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   For the Gmicro, nothing is done now. */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+   On the VAX, the predecrement and postincrement address depend thus
+   (the amount of decrement or increment being the length of the operand)
+   and all indexed address depend thus (because the index scale factor
+   is the length of the operand).
+   The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
+   include auto-inc/dec. */
+
+/* Unnecessary ??? */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
+ { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC)	\
+     goto LABEL; }
+
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+/* #define CASE_VECTOR_MODE HImode */
+#define CASE_VECTOR_MODE SImode
+
+/* Define as C expression which evaluates to nonzero if the tablejump
+   instruction expects the table to contain offsets from the address of the
+   table.
+   Do not define this if the table should contain absolute addresses. */
+#define CASE_VECTOR_PC_RELATIVE 1
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 1
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Define this if zero-extension is slow (more than one real instruction).  */
+/* #define SLOW_ZERO_EXTEND */
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+/* Define if shifts truncate the shift count
+   which implies one can omit a sign-extension or zero-extension
+   of a shift count.  */
+/* #define SHIFT_COUNT_TRUNCATED */
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+
+/* #define STORE_FLAG_VALUE -1 */
+
+/* When a prototype says `char' or `short', really pass an `int'.  */
+#define PROMOTE_PROTOTYPES
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* A function address in a call instruction
+   is a byte address (for indexing purposes)
+   so give the MEM rtx a byte's mode.  */
+#define FUNCTION_MODE QImode
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:						\
+    if ((unsigned) INTVAL (RTX) < 8) return 0;			\
+    if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1;	\
+    if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2;	\
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+    return 3;							\
+  case CONST_DOUBLE:						\
+    return 5;
+
+/* Define subroutines to call to handle multiply and divide.
+   The `*' prevents an underscore from being prepended by the compiler.  */
+/* Use libgcc on Gmicro */
+/* #define UDIVSI3_LIBCALL "*udiv" */
+/* #define UMODSI3_LIBCALL "*urem" */
+
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  */
+
+/* Set if the cc value is actually in the FPU, so a floating point
+   conditional branch must be output.  */
+#define CC_IN_FPU 04000
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+/* Since Gmicro's compare instructions depend on the branch condition,
+   all branch should be kept.
+   More work must be done to optimize condition code !! M.Yuhara */
+
+#define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
+
+/* The skeleton of the next macro is taken from "vax.h".
+   FPU-reg manipulation is added.  M.Yuhara */
+/* Now comment out.
+#define NOTICE_UPDATE_CC(EXP, INSN) {	\
+  if (GET_CODE (EXP) == SET) {					\
+      if ( !FPU_REG_P (XEXP (EXP, 0))				\
+	  && (XEXP (EXP, 0) != cc0_rtx)				\
+	  && (FPU_REG_P (XEXP (EXP, 1))				\
+	      || GET_CODE (XEXP (EXP, 1)) == FIX		\
+	      || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE	\
+	      || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) {	\
+	 CC_STATUS_INIT;					\
+      } else if (GET_CODE (SET_SRC (EXP)) == CALL) {		\
+	 CC_STATUS_INIT;					\
+      } else if (GET_CODE (SET_DEST (EXP)) != PC) {		\
+	  cc_status.flags = 0;					\
+	  cc_status.value1 = SET_DEST (EXP);			\
+	  cc_status.value2 = SET_SRC (EXP);			\
+      }								\
+  } else if (GET_CODE (EXP) == PARALLEL				\
+	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET		\
+	   && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
+      cc_status.flags = 0;					\
+      cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0));	\
+      cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); 	\
+  /* PARALLELs whose first element sets the PC are aob, sob VAX insns.	\
+     They do change the cc's.  So drop through and forget the cc's. * / \
+  } else CC_STATUS_INIT;						\
+  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
+      && cc_status.value2					\
+      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
+    cc_status.value2 = 0;					\
+  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM	\
+      && cc_status.value2					\
+      && GET_CODE (cc_status.value2) == MEM)			\
+    cc_status.value2 = 0;					\
+  if ( (cc_status.value1 && FPU_REG_P (cc_status.value1))	\
+      || (cc_status.value2 && FPU_REG_P (cc_status.value2)))	\
+    cc_status.flags = CC_IN_FPU;				\
+}
+*/
+
+#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
+{ if (cc_prev_status.flags & CC_IN_FPU)		\
+    return FLOAT;				\
+  if (cc_prev_status.flags & CC_NO_OVERFLOW)	\
+    return NO_OV;				\
+  return NORMAL; }
+
+/* Control the assembler format that we output.  */
+
+/* Output before read-only data.  */
+
+#define TEXT_SECTION_ASM_OP ".section text,code,align=4"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP ".section data,data,align=4"
+
+/* Output before uninitialized data. */
+
+#define BSS_SECTION_ASM_OP ".section bss,data,align=4"
+
+/* Output at beginning of assembler file.
+   It is not appropriate for this to print a list of the options used,
+   since that's not the convention that we use.  */
+
+#define ASM_FILE_START(FILE)
+
+/* Output at the end of assembler file. */
+
+#define ASM_FILE_END(FILE)  fprintf (FILE, "\t.end\n");
+
+
+/* Don't try to define `gcc_compiled.' since the assembler do not
+   accept symbols with periods and GDB doesn't run on this machine anyway.  */
+#define ASM_IDENTIFY_GCC(FILE)
+
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON ""
+/* #define ASM_APP_ON "#APP\n" */
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF ""
+/* #define ASM_APP_OFF ";#NO_APP\n" */
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",	\
+ "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp",	\
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
+ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
+
+/* How to renumber registers for dbx and gdb. */
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* Define this if gcc should produce debugging output for dbx in response
+   to the -g flag. This does not work for the Gmicro now */
+
+#define DBX_DEBUGGING_INFO
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME) {	\
+    assemble_name (FILE, NAME);	\
+    fputs (":\n", FILE);	\
+}
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
+    fputs ("\t.global ", FILE);	\
+    assemble_name (FILE, NAME);	\
+    fputs ("\n", FILE);		\
+}
+
+/* This is how to output a command to make the external label named NAME
+   which are not defined in the file to be referable */
+/* ".import" does not work ??? */
+
+#define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
+    fputs ("\t.global ", FILE);	\
+    assemble_name (FILE, NAME);	\
+    fputs ("\n", FILE);		\
+}
+
+
+/* The prefix to add to user-visible assembler symbols. */
+
+#define USER_LABEL_PREFIX "_"
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+/* do {...} while(0) is necessary, because these macros are used as
+    if (xxx) MACRO; else ....
+		  ^
+*/
+
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
+do { union { double d; long l[2];} tem;					\
+     tem.d = (VALUE);							\
+     fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]);	\
+} while(0)
+
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
+do { union { float f; long l;} tem;			\
+     tem.f = (VALUE);					\
+     fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l);	\
+} while(0)
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( fprintf (FILE, "\t.data.w "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.data.h "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.data.b "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
+
+#define ASM_OUTPUT_ASCII(FILE,P,SIZE)  \
+  output_ascii ((FILE), (P), (SIZE))
+
+/* This is how to output an insn to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute.
+   (The Gmicro does not use such vectors,
+   but we must define this macro anyway.)  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.data.w L%d\n", VALUE)
+
+
+/* This is how to output an element of a case-vector that is relative.  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
+  fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
+
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
+  fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.res.b %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( bss_section (),				\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
+  fprintf ((FILE), "\t.export "),		\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), "\n") )
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
+( bss_section (),				\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+/* $__ is unique ????? M.Yuhara */
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
+  sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Output a float value (represented as a C double) as an immediate operand.
+   This macro is a Gmicro/68k-specific macro.  */
+
+#define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE)	\
+do { union { float f; long l;} tem;		\
+  tem.f = (VALUE);				\
+  fprintf (FILE, "#h'%x.s", tem.l);		\
+} while(0)
+
+
+/* Output a double value (represented as a C double) as an immediate operand.
+   This macro is a 68k-specific macro.  */
+#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)	\
+do { union { double d; long l[2];} tem;		\
+  tem.d = (VALUE);				\
+  fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]);	\
+} while(0)
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.
+
+   On the Gmicro, we use several CODE characters:
+   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
+   'b' for branch target label.
+   '-' for an operand pushing on the stack.
+   '+' for an operand pushing on the stack.
+   '#' for an immediate operand prefix 
+*/
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE)	\
+  ( (CODE) == '#' || (CODE) == '-'		\
+     || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
+
+
+#define PRINT_OPERAND(FILE, X, CODE)  \
+{ int i;								\
+  static char *reg_name[] = REGISTER_NAMES;				\
+/* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
+myprcode(GET_CODE(X)); */	\
+  if (CODE == '#') fprintf (FILE, "#");					\
+  else if (CODE == '-') fprintf (FILE, "@-sp");				\
+  else if (CODE == '+') fprintf (FILE, "@sp+");				\
+  else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); 	\
+  else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); 	\
+  else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); 	\
+  else if (CODE == 'b') {						\
+    if (GET_CODE (X) == MEM)						\
+	output_addr_const (FILE, XEXP (X, 0));  /* for bsr */		\
+    else								\
+	output_addr_const (FILE, X);  /* for bcc */			\
+  }									\
+  else if (CODE == 'p')							\
+    print_operand_address (FILE, X);					\
+  else if (GET_CODE (X) == REG)						\
+    fprintf (FILE, "%s", reg_name[REGNO (X)]);				\
+  else if (GET_CODE (X) == MEM)						\
+    output_address (XEXP (X, 0));					\
+  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
+    { union { double d; int i[2]; } u;					\
+      union { float f; int i; } u1;					\
+      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
+      u1.f = u.d;							\
+      if (CODE == 'f')							\
+	ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f);				\
+      else								\
+	fprintf (FILE, "#h'%x", u1.i); }				\
+  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
+    { union { double d; int i[2]; } u;					\
+      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
+      ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); }				\
+  else { putc ('#', FILE);						\
+output_addr_const (FILE, X); }}
+
+/* Note that this contains a kludge that knows that the only reason
+   we have an address (plus (label_ref...) (reg...))
+   is in the insn before a tablejump, and we know that m68k.md
+   generates a label LInnn: on such an insn.  */
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
+    { print_operand_address (FILE, ADDR); }
+
+/*
+Local variables:
+version-control: t
+End:
+*/
diff --git a/gnu/egcs/gcc/config/gmicro/gmicro.md b/gnu/egcs/gcc/config/gmicro/gmicro.md
new file mode 100644
index 00000000000..35384ce044d
--- /dev/null
+++ b/gnu/egcs/gcc/config/gmicro/gmicro.md
@@ -0,0 +1,2738 @@
+;;- Machine description for GNU compiler, Fujitsu Gmicro Version
+;;  Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
+;;  Contributed by M.Yuhara, Fujitsu Laboratories LTD.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;; Among other things, the copyright
+;; notice and this notice must be preserved on all copies.
+
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+
+;;- instruction definitions
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;- When naming insn's (operand 0 of define_insn) be careful about using
+;;- names from other targets machine descriptions.
+
+;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the 
+;;- gmicro; no compares are eliminated.
+
+;;- The original structure of this file is m68k.md.
+
+;; ??? Work to be done:
+;; Add patterns for ACB and SCB instructions.
+;; Add define_insn patterns to recognize the insns that extend a byte
+;; to a word and add it into a word, etc.
+
+;;- Some of these insn's are composites of several Gmicro op codes.
+;;- The assembler (or final @@??) insures that the appropriate one is
+;;- selected.
+
+(define_insn ""
+  [(set (match_operand:DF 0 "push_operand" "=m")
+	(match_operand:DF 1 "general_operand" "rmfF"))]
+  ""
+  "*
+{
+  if (FPU_REG_P (operands[1]))
+    return \"fmov.d %f1,%0\";
+  return output_move_double (operands);
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "push_operand" "=m")
+	(match_operand:DF 1 "general_operand" "rmF"))]
+  ""
+  "*
+{
+  return output_move_double (operands);
+}")
+
+;; We don't want to allow a constant operand for test insns because
+;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
+;; be folded while optimizing anyway.
+
+(define_insn "tstsi"
+  [(set (cc0)
+	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
+  ""
+  "cmp:z.w #0,%0")
+
+(define_insn "tsthi"
+  [(set (cc0)
+	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
+  ""
+  "cmp:z.h #0,%0")
+
+(define_insn "tstqi"
+  [(set (cc0)
+	(match_operand:QI 0 "nonimmediate_operand" "rm"))]
+  ""
+  "cmp:z.b #0,%0")
+  
+
+(define_insn "tstsf"
+  [(set (cc0)
+	(match_operand:SF 0 "general_operand" "fmF"))]
+  "TARGET_FPU"
+  "*
+{
+  cc_status.flags = CC_IN_FPU;
+  return \"ftst.s %0\";
+}")
+
+
+(define_insn "tstdf"
+  [(set (cc0)
+	(match_operand:DF 0 "general_operand" "fmF"))]
+  "TARGET_FPU"
+  "*
+{
+  cc_status.flags = CC_IN_FPU;
+  return \"ftst.d %0\";
+}")
+
+;; compare instructions.
+
+;; (operand0 - operand1)
+(define_insn "cmpsi"
+  [(set (cc0)
+	(compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm")
+		 (match_operand:SI 1 "general_operand" "rm,rmi")))]
+  ""
+  "*
+{
+  int signed_flag = my_signed_comp (insn);
+
+  if (which_alternative == 0)
+    {
+      cc_status.flags |= CC_REVERSED;
+      if (signed_flag && GET_CODE (operands[0]) == CONST_INT)
+	{
+	  register rtx xfoo;
+	  xfoo = operands[1];
+	  operands[0] = operands[1];
+	  operands[1] = xfoo;
+	  return cmp_imm_word (INTVAL (operands[1]), operands[0]);
+	}
+      if (signed_flag)
+	return \"cmp.w %0,%1\"; 
+      return \"cmpu.w %0,%1\"; 
+    }
+  if (signed_flag)
+    {
+      if (GET_CODE (operands[1]) == CONST_INT)
+	return cmp_imm_word (INTVAL (operands[1]), operands[0]);
+      return \"cmp.w %1,%0\"; 
+    }
+  else
+    return \"cmpu.w %1,%0\"; 
+}")
+
+(define_insn "cmphi"
+  [(set (cc0)
+	(compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm")
+		 (match_operand:HI 1 "general_operand" "rm,rmi")))]
+  ""
+  "*
+{
+  int signed_flag = my_signed_comp (insn);
+
+  if (which_alternative == 0)
+    {
+      cc_status.flags |= CC_REVERSED;
+      if (signed_flag)
+	return \"cmp.h %0,%1\"; 
+      return \"cmpu.h %0,%1\"; 
+    }
+  if (signed_flag)
+    return \"cmp.h %1,%0\"; 
+  return \"cmpu.h %1,%0\"; 
+}")
+
+(define_insn "cmpqi"
+  [(set (cc0)
+	(compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm")
+		 (match_operand:QI 1 "general_operand" "rm,rmi")))]
+  ""
+  "*
+{
+  int signed_flag = my_signed_comp (insn);
+
+  if (which_alternative == 0)
+    {
+      cc_status.flags |= CC_REVERSED;
+      if (signed_flag)
+	return \"cmp.b %0,%1\"; 
+      return \"cmpu.b %0,%1\"; 
+    }
+  if (signed_flag)
+    return \"cmp.b %1,%0\"; 
+  return \"cmpu.b %1,%0\"; 
+}")
+
+
+(define_insn "cmpdf"
+  [(set (cc0)
+	(compare (match_operand:DF 0 "general_operand" "f,mG")
+		 (match_operand:DF 1 "general_operand" "fmG,f")))]
+  "TARGET_FPU"
+  "*
+{
+  cc_status.flags = CC_IN_FPU;
+
+  if (FPU_REG_P (operands[0]))
+    return \"fcmp.d %f1,%f0\";
+  cc_status.flags |= CC_REVERSED;
+  return \"fcmp.d %f0,%f1\";
+}")
+
+
+(define_insn "cmpsf"
+  [(set (cc0)
+	(compare (match_operand:SF 0 "general_operand" "f,mG")
+		 (match_operand:SF 1 "general_operand" "fmG,f")))]
+  "TARGET_FPU"
+  "*
+{
+  cc_status.flags = CC_IN_FPU;
+  if (FPU_REG_P (operands[0]))
+    return \"fcmp.s %f1,%0\";
+  cc_status.flags |= CC_REVERSED;
+  return \"fcmp.s %f0,%1\";
+}")
+
+;; Recognizers for btst instructions.
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
+			    (const_int 1)
+			    (match_operand:SI 1 "general_operand" "rmi")))]
+  ""
+  "btst %1.w,%0.b")
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "rm")
+			    (const_int 1)
+			    (match_operand:SI 1 "general_operand" "rmi")))]
+  ""
+  "btst %1.w,%0.w")
+
+;; The following two patterns are like the previous two
+;; except that they use the fact that bit-number operands (offset)
+;; are automatically masked to 3 or 5 bits when the base is a register.
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
+			    (const_int 1)
+			    (and:SI
+			       (match_operand:SI 1 "general_operand" "rmi")
+			       (const_int 7))))]
+  ""
+  "btst %1.w,%0.b")
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
+			    (const_int 1)
+			    (and:SI
+			       (match_operand:SI 1 "general_operand" "rmi")
+			       (const_int 31))))]
+  ""
+  "btst %1.w,%0.w")
+
+; More various size-patterns are allowed for btst, but not
+; included yet.  M.Yuhara
+
+
+(define_insn ""
+  [(set (cc0) (and:SI (sign_extend:SI
+		       (sign_extend:HI
+			(match_operand:QI 0 "nonimmediate_operand" "rm")))
+		      (match_operand:SI 1 "general_operand" "i")))]
+  "(GET_CODE (operands[1]) == CONST_INT
+    && (unsigned) INTVAL (operands[1]) < 0x100
+    && exact_log2 (INTVAL (operands[1])) >= 0)"
+  "*
+{
+  register int log = exact_log2 (INTVAL (operands[1]));
+  operands[1] = GEN_INT (log);
+  return \"btst %1,%0.b\";
+}")
+
+; I can add more patterns like above. But not yet.  M.Yuhara
+
+
+; mtst is supported only by G/300.
+
+(define_insn ""
+  [(set (cc0) 
+	(and:SI (match_operand:SI 0 "general_operand" "%rmi")
+		(match_operand:SI 1 "general_operand" "rm")))]
+  "TARGET_G300"
+  "*
+{
+  if (GET_CODE (operands[0]) == CONST_INT)
+    return \"mtst.w %0,%1\";
+  return \"mtst.w %1,%0\";
+}")
+
+(define_insn ""
+  [(set (cc0) 
+	(and:HI (match_operand:HI 0 "general_operand" "%rmi")
+		(match_operand:HI 1 "general_operand" "rm")))]
+  "TARGET_G300"
+  "*
+{
+  if (GET_CODE (operands[0]) == CONST_INT)
+    return \"mtst.h %0,%1\";
+  return \"mtst.h %1,%0\";
+}")
+
+(define_insn ""
+  [(set (cc0) 
+	(and:QI (match_operand:QI 0 "general_operand" "%rmi")
+		(match_operand:QI 1 "general_operand" "rm")))]
+  "TARGET_G300"
+  "*
+{
+  if (GET_CODE (operands[0]) == CONST_INT)
+    return \"mtst.b %0,%1\";
+  return \"mtst.b %1,%0\";
+}")
+
+
+
+;; move instructions
+
+/* added by M.Yuhara */
+;; 1.35.04 89.08.28 modification start
+;; register_operand -> general_operand
+;; ashift -> mult 
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (match_operand:SI 0 "general_operand" "r")
+		  (ashift:SI
+		      (match_operand:SI 1 "general_operand" "r")
+		      (const_int 2))))
+	(match_operand:SI 2 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %2,@(%0:b,%1*4)\";
+}")
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (ashift:SI
+		      (match_operand:SI 0 "general_operand" "r")
+		      (const_int 2))
+		  (match_operand:SI 1 "general_operand" "r")))
+	(match_operand:SI 2 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %2,@(%1:b,%0*4)\";
+}")
+
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (match_operand:SI 0 "register_operand" "r")
+		  (mult:SI
+		      (match_operand:SI 1 "register_operand" "r")
+		      (const_int 4))))
+	(match_operand:SI 2 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %2,@(%0:b,%1*4)\";
+}")
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (mult:SI
+		      (match_operand:SI 0 "register_operand" "r")
+		      (const_int 4))
+		  (match_operand:SI 1 "register_operand" "r")))
+	(match_operand:SI 2 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %2,@(%1:b,%0*4)\";
+}")
+
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (match_operand:SI 0 "general_operand" "r")
+		  (plus:SI
+		      (match_operand:SI 1 "register_operand" "r")
+		      (match_operand:SI 2 "register_operand" "i"))))
+	(match_operand:SI 3 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %3,@(%c2,%0,%1)\";
+}")
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (plus:SI
+		      (match_operand:SI 0 "register_operand" "r")
+		      (match_operand:SI 1 "register_operand" "r"))
+		  (match_operand:SI 2 "general_operand" "i")))
+	(match_operand:SI 3 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %3,@(%c2,%0,%1)\";
+}")
+
+
+(define_insn ""
+  [(set (mem:SI (plus:SI
+		  (match_operand:SI 0 "general_operand" "i")
+		  (plus:SI
+		      (match_operand:SI 1 "register_operand" "r")
+		      (mult:SI
+			  (match_operand:SI 2 "register_operand" "r")
+			  (const_int 4)))))
+	(match_operand:SI 3 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  return \"mov.w %3,@(%1:b,%0,%2*4)\";
+}")
+
+;; 89.08.28 1.35.04 modification end
+
+;; Should add "!" to op2 ??
+
+;; General move-address-to-operand should handle these.
+;; If that does not work, please figure out why.
+
+;(define_insn ""
+;  [(set (match_operand:SI 0 "push_operand" "=m")
+;	(plus:SI
+;	    (match_operand:SI 1 "immediate_operand" "i")
+;	    (match_operand:SI 2 "general_operand" "r")))]
+;  ""
+;  "mova.w @(%c1,%2),%-")
+
+;(define_insn ""
+;  [(set (match_operand:SI 0 "push_operand" "=m")
+;	(plus:SI
+;	    (match_operand:SI 1 "general_operand" "r")
+;	    (match_operand:SI 2 "immediate_operand" "i")))]
+;  ""
+;  "mova.w @(%c2,%1),%-")
+
+
+(define_insn ""
+  [(set (match_operand:SI 0 "push_operand" "=m")
+	(minus:SI
+	    (match_operand:SI 1 "general_operand" "r")
+	    (match_operand:SI 2 "immediate_operand" "i")))]
+  ""
+  "mova.w @(%n2,%1),%-")
+
+
+
+;; General case of fullword move.
+
+(define_insn "movsi"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(match_operand:SI 1 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    return mov_imm_word (INTVAL (operands[1]), operands[0]);
+  /* if (address_operand (operands[1], SImode))
+     return \"mova.w %1,%0\"; */
+  if (push_operand (operands[0], SImode))
+    return \"mov.w %1,%-\";
+  return \"mov.w %1,%0\";
+}")
+
+/* pushsi 89.08.10 for test M.Yuhara */
+/*
+(define_insn ""
+  [(set (match_operand:SI 0 "push_operand" "=m")
+	(match_operand:SI 1 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    return mov_imm_word (INTVAL (operands[1]), operands[0]);
+  if (push_operand (operands[0], SImode))
+    return \"mov.w %1,%-\";
+  return \"mov.w %1,%0\";
+}")
+*/
+
+
+(define_insn "movhi"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(match_operand:HI 1 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  if (push_operand (operands[0], SImode))
+    return \"mov.h %1,%-\";
+  return \"mov.h %1,%0\";
+}")
+
+;; Is the operand constraint "+" necessary ????
+;; Should I check push_operand ????
+
+(define_insn "movstricthi"
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
+	(match_operand:HI 1 "general_operand" "rmi"))]
+  ""
+  "mov.h %1,%0");
+
+(define_insn "movqi"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(match_operand:QI 1 "general_operand" "rmi"))]
+  ""
+  "*
+{
+  if (GREG_P (operands[0]))
+    {
+      if (CONSTANT_P (operands[1]))
+	return \"mov:l %1,%0.w\";
+      else
+	return \"mov:l %1.b,%0.w\";
+    }
+  if (GREG_P (operands[1]))
+    return \"mov:s %1.w,%0.b\";
+  return \"mov.b %1,%0\";
+}")
+
+(define_insn "movstrictqi"
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
+	(match_operand:QI 1 "general_operand" "rmi"))]
+  ""
+  "mov.b %1,%0")
+
+
+(define_insn "movsf"
+  [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr")
+	(match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))]
+  ""
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_single (operands);
+      return \"fmov.s %1,%0\";
+    case 1:
+      return \"fmov.s %1,%0\";
+    case 2:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_single (operands);
+      return \"mov.w %1,%0\";
+    case 3:
+      if (FPU_REG_P (operands[0]))
+	return \"mov.w %1,%-\\n\\tfmov.s %+,%0\";
+      return \"fmov.s %1,%-\\n\\tmov.w %+,%0\";
+    }
+}")
+
+(define_insn "movdf"
+  [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr")
+	(match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))]
+  ""
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_double (operands);
+      return \"fmov.d %1,%0\";
+    case 1:
+      return \"fmov.d %1,%0\";
+    case 2:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_double (operands);
+      return output_move_double (operands);
+    case 3:
+      if (FPU_REG_P (operands[0]))
+	{
+	  rtx xoperands[2];
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+	  output_asm_insn (\"mov.w %1,%-\", xoperands);
+	  output_asm_insn (\"mov.w %1,%-\", operands);
+	  return \"fmov.d %+,%0\";
+	}
+      else
+	{
+	  output_asm_insn (\"fmov.d %f1,%-\", operands);
+	  output_asm_insn (\"mov.w %+,%0\", operands);
+	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  return \"mov.w %+,%0\";
+	}
+    }
+}")
+
+
+;; movdi can apply to fp regs in some cases
+;; Must check again.  you can use fsti/fldi, etc.
+;; FPU reg should be included ??
+;; 89.12.13 for test
+
+(define_insn "movdi"
+  ;; Let's see if it really still needs to handle fp regs, and, if so, why.
+  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro")
+	(match_operand:DI 1 "general_operand" "rF,m,roiF"))]
+  ""
+  "*
+{
+  if (FPU_REG_P (operands[0]))
+    {
+      if (FPU_REG_P (operands[1]))
+	return \"fmov.d %1,%0\";
+      if (REG_P (operands[1]))
+	{
+	  rtx xoperands[2];
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+	  output_asm_insn (\"mov.w %1,%-\", xoperands);
+	  output_asm_insn (\"mov.w %1,%-\", operands);
+	  return \"fmov.d %+,%0\";
+	}
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_double (operands);
+      return \"fmov.d %f1,%0\";
+    }
+  else if (FPU_REG_P (operands[1]))
+    {
+      if (REG_P (operands[0]))
+	{
+	  output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands);
+	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  return \"mov.w %+,%0\";
+	}
+      else
+        return \"fmov.d %f1,%0\";
+    }
+  return output_move_double (operands);
+}
+")
+
+
+;; The definition of this insn does not really explain what it does,
+;; but it should suffice
+;; that anything generated as this insn will be recognized as one
+;; and that it won't successfully combine with anything.
+
+;; This is dangerous when %0 and %1 overlapped !!!!!
+;; Ugly code...
+
+(define_insn "movstrhi"
+  [(set (match_operand:BLK 0 "general_operand" "=m")
+	(match_operand:BLK 1 "general_operand" "m"))
+   (use (match_operand:HI 2 "general_operand" "rmi"))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 1))
+   (clobber (reg:SI 2))]
+  ""
+  "*
+{
+  int op2const;
+  rtx tmpx;
+
+  if (CONSTANT_P (operands[1]))
+    {
+      fprintf (stderr, \"smov 1 const err \");
+      abort ();
+    }
+  else if (GET_CODE (operands[1]) == REG)
+    {
+      fprintf (stderr, \"smov 1 reg err \");
+      abort ();
+    }
+  else if (GET_CODE (operands[1]) == MEM)
+    {
+      tmpx = XEXP (operands[1], 0);
+      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
+	{
+	  operands[1] = tmpx;
+	  output_asm_insn (\"mov.w %1,r0\", operands);
+	}
+      else
+	{
+	  output_asm_insn (\"mova %1,r0\", operands);
+	}
+    }
+  else
+    {
+      fprintf (stderr, \"smov 1 else err \");
+      abort ();
+      output_asm_insn (\"mova.w %p1,r0\", operands);
+    }
+    
+  if (CONSTANT_P (operands[0]))
+    {
+      fprintf (stderr, \"smov 0 const err \");
+      abort ();
+    }
+  else if (GET_CODE (operands[0]) == REG)
+    {
+      fprintf (stderr, \"smov 0 reg err \");
+      abort ();
+    }
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      tmpx = XEXP (operands[0], 0);
+      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
+	{
+	  operands[0] = tmpx;
+	  output_asm_insn (\"mov.w %0,r1\", operands);
+	}
+      else
+	{
+	  output_asm_insn (\"mova %0,r1\", operands);
+	}
+    }
+  else
+    {
+      fprintf (stderr, \"smov 0 else err \");
+      abort ();
+    }
+    
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      op2const = INTVAL (operands[2]);
+      if (op2const % 4 != 0)
+	{
+	  output_asm_insn (\"mov.w %2,r2\", operands);
+	  return \"smov/n/f.b\";
+	}
+      op2const = op2const / 4;
+      if (op2const <= 4)
+	{
+	  if (op2const == 0)
+	    abort (0);
+	  if (op2const == 1)
+	    return \"mov.w @r0,@r1\";
+	  output_asm_insn (\"mov.w @r0,@r1\", operands);
+	  if (op2const == 2)
+	    return \"mov.w @(4,r0),@(4,r1)\";
+	  output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands);
+	  if (op2const == 3)
+	    return \"mov.w @(8,r0),@(8,r1)\";
+	  output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands);
+	  return \"mov.w @(12,r0),@(12,r1)\";
+	}
+	    
+      operands[2] = GEN_INT (op2const);
+      output_asm_insn (\"mov.w %2,r2\", operands);
+      return \"smov/n/f.w\";
+    }
+  else
+    {
+      fprintf (stderr, \"smov 0 else err \");
+      abort ();
+      output_asm_insn (\"mov %2.h,r2.w\", operands);
+      return \"smov/n/f.b\";
+    }
+
+}")
+
+;; M.Yuhara 89.08.24
+;; experiment on the built-in strcpy (__builtin_smov)
+;;
+;; len = 0 means unknown string length.
+;;
+;; mem:SI is dummy. Necessary so as not to be deleted by optimization.
+;; Use of BLKmode would be better...
+;;
+;;
+(define_insn "smovsi"
+  [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm"))
+	(mem:SI (match_operand:SI 1 "general_operand" "rm")))
+   (use (match_operand:SI 2 "general_operand" "i"))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 1))
+   (clobber (reg:SI 2))
+   (clobber (reg:SI 3))]
+  ""
+  "*
+{
+  int len, wlen, blen, offset;
+  char tmpstr[128];
+  rtx xoperands[1];
+
+  len = INTVAL (operands[2]);
+  output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands);
+  output_asm_insn (\"mov.w %0,r1\", operands);
+
+  if (len == 0)
+    {
+      output_asm_insn (\"mov:z.w #0,r2\", operands);
+      output_asm_insn (\"mov:z.w #0,r3\", operands);
+      return \"smov/eq/f.b\\t; end built-in strcpy\";
+    }
+
+  wlen = len / 4;
+  blen = len - wlen * 4;
+
+  if (wlen > 0)
+    {
+      if (len <= 40 && !TARGET_FORCE_SMOV)
+	{
+	  output_asm_insn (\"mov.w @r0,@r1\", operands);
+	  offset = 4;
+	  while ( (blen = len - offset) > 0)
+	    {
+	      if (blen >= 4)
+		{
+		  sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\",
+			   offset, offset);
+		  output_asm_insn (tmpstr, operands);
+		  offset += 4;
+		}
+	      else if (blen >= 2)
+		{
+		  sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\",
+			   offset, offset);
+		  output_asm_insn (tmpstr, operands);
+		  offset += 2;
+		}
+	      else
+		{
+		  sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\",
+			   offset, offset);
+		  output_asm_insn (tmpstr, operands);
+		  offset++;
+		}
+	    }
+	  return \"\\t\\t; end built-in strcpy\";
+	}
+      else
+	{
+	  xoperands[0] = GEN_INT (wlen);
+	  output_asm_insn (\"mov.w %0,r2\", xoperands);
+	  output_asm_insn (\"smov/n/f.w\", operands);
+	}
+    }
+
+  if (blen >= 2)
+    {
+      output_asm_insn (\"mov.h @r0,@r1\", operands);
+      if (blen == 3)
+	output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands);
+    }
+  else if (blen == 1)
+    {
+      output_asm_insn (\"mov.b @r0,@r1\", operands);
+    }
+
+  return \"\\t\\t; end built-in strcpy\";
+}")
+
+;; truncation instructions
+(define_insn "truncsiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(truncate:QI
+	 (match_operand:SI 1 "general_operand" "rmi")))]
+  ""
+  "mov %1.w,%0.b")
+;  "*
+;{
+;  if (GET_CODE (operands[0]) == REG)
+;    return \"mov.w %1,%0\";
+;  if (GET_CODE (operands[1]) == MEM)
+;    operands[1] = adj_offsettable_operand (operands[1], 3);
+;  return \"mov.b %1,%0\";
+;}")
+
+(define_insn "trunchiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(truncate:QI
+	 (match_operand:HI 1 "general_operand" "rmi")))]
+  ""
+  "mov %1.h,%0.b")
+;  "*
+;{
+;  if (GET_CODE (operands[0]) == REG)
+;    return \"mov.h %1,%0\";
+;  if (GET_CODE (operands[1]) == MEM)
+;    operands[1] = adj_offsettable_operand (operands[1], 1);
+;  return \"mov.b %1,%0\";
+;}")
+
+(define_insn "truncsihi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(truncate:HI
+	 (match_operand:SI 1 "general_operand" "rmi")))]
+  ""
+  "mov %1.w,%0.h")
+;  "*
+;{
+;  if (GET_CODE (operands[0]) == REG)
+;    return \"mov.w %1,%0\";
+;  if (GET_CODE (operands[1]) == MEM)
+;    operands[1] = adj_offsettable_operand (operands[1], 2);
+;  return \"mov.h %1,%0\";
+;}")
+
+;; zero extension instructions
+;; define_expand (68k) -> define_insn (Gmicro)
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "movu %1.h,%0.w")
+
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "movu %1.b,%0.h")
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "movu %1.b,%0.w")
+
+
+;; sign extension instructions
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "mov %1.h,%0.w")
+
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "mov %1.b,%0.h")
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "mov %1.b,%0.w")
+
+
+
+;; Conversions between float and double.
+
+(define_insn "extendsfdf2"
+  [(set (match_operand:DF 0 "general_operand" "=*frm,f")
+	(float_extend:DF
+	  (match_operand:SF 1 "general_operand" "f,rmF")))]
+  "TARGET_FPU"
+  "*
+{
+  if (FPU_REG_P (operands[0]))
+    {
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	return output_move_const_double (operands);
+      if (GREG_P (operands[1]))
+	{
+	  output_asm_insn (\"mov.w %1,%-\", operands);
+	  return \"fmov %+.s,%0.d\";
+	}
+      return \"fmov %1.s,%0.d\";
+    }
+  else
+    {
+      if (GREG_P (operands[0]))
+	{
+	  output_asm_insn (\"fmov %1.s,%-.d\", operands);
+	  output_asm_insn (\"mov.w %+,%0\", operands);
+	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  return \"mov.w %+,%0\";
+	}
+      return \"fmov %1.s,%0.d\";
+    }
+}")
+
+
+(define_insn "truncdfsf2"
+  [(set (match_operand:SF 0 "general_operand" "=rfm")
+	(float_truncate:SF
+	  (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_FPU"
+  "*
+{
+  if (GREG_P (operands[0]))
+    {
+      output_asm_insn (\"fmov %1.d,%-.s\", operands);
+      return \"mov.w %+,%0\";
+    }
+  return \"fmov %1.d,%0.s\";
+}")
+
+;; Conversion between fixed point and floating point.
+;; Note that among the fix-to-float insns
+;; the ones that start with SImode come first.
+;; That is so that an operand that is a CONST_INT
+;; (and therefore lacks a specific machine mode).
+;; will be recognized as SImode (which is always valid)
+;; rather than as QImode or HImode.
+
+
+(define_insn "floatsisf2"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(float:SF (match_operand:SI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.w,%0.s")
+
+(define_insn "floatsidf2"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(float:DF (match_operand:SI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.w,%0.d")
+
+(define_insn "floathisf2"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(float:SF (match_operand:HI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.h,%0.s")
+
+(define_insn "floathidf2"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(float:DF (match_operand:HI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.h,%0.d")
+
+(define_insn "floatqisf2"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(float:SF (match_operand:QI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.b,%0.s")
+
+(define_insn "floatqidf2"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(float:DF (match_operand:QI 1 "general_operand" "rmi")))]
+  "TARGET_FPU"
+  "fldi %1.b,%0.d")
+
+;;; Convert a float to a float whose value is an integer.
+;;; This is the first stage of converting it to an integer type.
+;
+;(define_insn "ftruncdf2"
+;  [(set (match_operand:DF 0 "general_operand" "=f")
+;	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
+;  "TARGET_FPU"
+;  "*
+;{
+;  return \"fintrz.d %f1,%0\";
+;}")
+;
+;(define_insn "ftruncsf2"
+;  [(set (match_operand:SF 0 "general_operand" "=f")
+;	(fix:SF (match_operand:SF 1 "general_operand" "fFm")))]
+;  "TARGET_FPU"
+;  "*
+;{
+;  return \"fintrz.s %f1,%0\";
+;}")
+
+;; Convert a float to an integer.
+
+(define_insn "fix_truncsfqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.s,%0.b")
+
+(define_insn "fix_truncsfhi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.s,%0.h")
+
+(define_insn "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.s,%0.w")
+
+(define_insn "fix_truncdfqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.d,%0.b")
+
+(define_insn "fix_truncdfhi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.d,%0.h")
+
+(define_insn "fix_truncdfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
+  "TARGET_FPU"
+  "fsti %1.d,%0.w")
+
+
+;;; Special add patterns
+;;; 89.09.28
+
+;; This should be redundant; please find out why regular addsi3
+;; fails to match this case.
+
+;(define_insn ""
+;  [(set (mem:SI (plus:SI
+;		    (plus:SI (match_operand 0 "general_operand" "r")
+;			     (match_operand 1 "general_operand" "r"))
+;		    (match_operand 2 "general_operand" "i")))
+;	(plus:SI
+;	    (mem:SI (plus:SI
+;			(plus:SI (match_dup 0)
+;				 (match_dup 1))
+;			(match_dup 2)))
+;	    (match_operand 3 "general_operand" "rmi")))]
+;  ""
+;  "add.w %3,@(%c2,%0,%1)")
+
+
+;; add instructions
+
+;; Note that the last two alternatives are near-duplicates
+;; in order to handle insns generated by reload.
+;; This is needed since they are not themselves reloaded,
+;; so commutativity won't apply to them.
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r")
+	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri")
+		 (match_operand:SI 2 "general_operand" "rmi,ri,r")))]
+  ""
+  "*
+{
+  if (which_alternative == 0)
+    {
+      if (GET_CODE (operands[2]) == CONST_INT)
+	{
+	  operands[1] = operands[2];
+	  return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
+	}
+      else
+	return \"add.w %2,%0\";
+    }
+  else
+    {
+      if (GET_CODE (operands[1]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[1]))
+	return \"add.w %2,%0\";
+      if (GET_CODE (operands[2]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[2]))
+	return \"add.w %1,%0\";
+
+      if (GET_CODE (operands[1]) == REG)
+	{
+	  if (GET_CODE (operands[2]) == REG)
+	    return \"mova.w @(%1,%2),%0\";
+	  else
+	    return \"mova.w @(%c2,%1),%0\";
+	}
+      else
+	return \"mova.w @(%c1,%2),%0\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(plus:SI (match_operand:SI 1 "general_operand" "0")
+		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
+  ""
+  "*
+{
+  if (CONSTANT_P (operands[2]))
+    {
+      operands[1] = operands[2];
+      return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
+    }
+  else
+    return \"add %2.h,%0.w\";
+}")
+
+(define_insn "addhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(plus:HI (match_operand:HI 1 "general_operand" "%0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) < 0)
+    return \"sub.h #%n2,%0\";
+  if (GREG_P (operands[0]))
+    {
+      if (CONSTANT_P (operands[2]))
+	return \"add:l %2,%0.w\";
+      else
+	return \"add:l %2.h,%0.w\";
+    }
+  return \"add.h %2,%0\";
+}")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
+	(plus:HI (match_dup 0)
+		 (match_operand:HI 1 "general_operand" "rmi")))]
+  ""
+  "add.h %1,%0")
+
+(define_insn "addqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(plus:QI (match_operand:QI 1 "general_operand" "%0")
+		 (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) < 0)
+    return \"sub.b #%n2,%0\";
+  if (GREG_P (operands[0]))
+    {
+      if (CONSTANT_P (operands[2]))
+	return \"add:l %2,%0.w\";
+      else
+	return \"add:l %2.b,%0.w\";
+    }
+  return \"add.b %2,%0\";
+}")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
+	(plus:QI (match_dup 0)
+		 (match_operand:QI 1 "general_operand" "rmi")))]
+  ""
+  "add.b %1,%0")
+
+(define_insn "adddf3"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(plus:DF (match_operand:DF 1 "general_operand" "%0")
+		 (match_operand:DF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fadd.d %f2,%0")
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(plus:SF (match_operand:SF 1 "general_operand" "%0")
+		 (match_operand:SF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fadd.s %f2,%0")
+
+;; subtract instructions
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm,!r")
+	(minus:SI (match_operand:SI 1 "general_operand" "0,r")
+		  (match_operand:SI 2 "general_operand" "rmi,i")))]
+  ""
+  "*
+{
+  if (which_alternative == 0
+      || (GET_CODE (operands[1]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[1])))
+    {
+      if (GET_CODE (operands[2]) == CONST_INT)
+	{
+	  operands[1] = operands[2];
+	  return sub_imm_word (INTVAL (operands[1]),
+			       operands[0], &operands[1]);
+	}
+      else
+	return \"sub.w %2,%0\";
+    }
+  else
+    return \"mova.w @(%n2,%1),%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(minus:SI (match_operand:SI 1 "general_operand" "0")
+		  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
+  ""
+  "sub %2.h,%0.w")
+
+(define_insn "subhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(minus:HI (match_operand:HI 1 "general_operand" "0")
+		  (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) < 0
+      && INTVAL (operands[2]) != 0x8000)
+    return \"add.h #%n2,%0\";
+  return \"sub.h %2,%0\";
+}")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
+	(minus:HI (match_dup 0)
+		  (match_operand:HI 1 "general_operand" "rmi")))]
+  ""
+  "sub.h %1,%0")
+
+(define_insn "subqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(minus:QI (match_operand:QI 1 "general_operand" "0")
+		  (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) < 0
+      && INTVAL (operands[2]) != 0x80)
+    return \"add.b #%n2,%0\";
+  return \"sub.b %2,%0\";
+}")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
+	(minus:QI (match_dup 0)
+		  (match_operand:QI 1 "general_operand" "rmi")))]
+  ""
+  "sub.b %1,%0")
+
+(define_insn "subdf3"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(minus:DF (match_operand:DF 1 "general_operand" "0")
+		  (match_operand:DF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fsub.d %f2,%0")
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(minus:SF (match_operand:SF 1 "general_operand" "0")
+		  (match_operand:SF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fsub.s %f2,%0")
+
+
+;; multiply instructions
+
+(define_insn "mulqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(mult:QI (match_operand:QI 1 "general_operand" "%0")
+		 (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "mul.b %2,%0")
+
+
+(define_insn "mulhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(mult:HI (match_operand:HI 1 "general_operand" "%0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "mul.h %2,%0")
+
+;; define_insn "mulhisi3"
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(mult:SI (match_operand:SI 1 "general_operand" "%0")
+		 (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "mul.w %2,%0")
+
+(define_insn "muldf3"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(mult:DF (match_operand:DF 1 "general_operand" "%0")
+		 (match_operand:DF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fmul.d %f2,%0")
+
+(define_insn "mulsf3"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(mult:SF (match_operand:SF 1 "general_operand" "%0")
+		 (match_operand:SF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fmul.s %f2,%0")
+
+
+;; divide instructions
+
+(define_insn "divqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(div:QI (match_operand:QI 1 "general_operand" "0")
+		(match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "div.b %2,%0")
+
+(define_insn "divhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(div:HI (match_operand:HI 1 "general_operand" "0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "div.h %2,%0")
+
+(define_insn "divhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=r")
+	(div:HI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "div %2.h,%0.w")
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(div:SI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "div.w %2,%0")
+
+(define_insn "udivqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(udiv:QI (match_operand:QI 1 "general_operand" "0")
+		 (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "divu.b %2,%0")
+
+(define_insn "udivhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(udiv:HI (match_operand:HI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "divu.h %2,%0")
+
+(define_insn "udivhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=r")
+	(udiv:HI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "divu %2.h,%0.w")
+
+(define_insn "udivsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "divu.w %2,%0")
+
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(div:DF (match_operand:DF 1 "general_operand" "0")
+		(match_operand:DF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fdiv.d %f2,%0")
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(div:SF (match_operand:SF 1 "general_operand" "0")
+		(match_operand:SF 2 "general_operand" "fmG")))]
+  "TARGET_FPU"
+  "fdiv.s %f2,%0")
+
+;; Remainder instructions.
+
+(define_insn "modqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(mod:QI (match_operand:QI 1 "general_operand" "0")
+		(match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "rem.b %2,%0")
+
+(define_insn "modhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=r")
+	(mod:HI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "rem.h %2,%0")
+
+(define_insn "umodqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(umod:QI (match_operand:QI 1 "general_operand" "0")
+		 (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "remu.b %2,%0")
+
+(define_insn "umodhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(umod:HI (match_operand:HI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "remu.h %2,%0")
+
+(define_insn "umodhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=r")
+	(umod:HI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "remu %2.h,%0.w")
+
+;; define_insn "divmodsi4"
+
+(define_insn "udivmodsi4"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "rmi")))
+   (set (match_operand:SI 3 "general_operand" "=r")
+	(umod:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "mov.w #0,%3;divx.w %2,%0,%3")
+
+;; logical-and instructions
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(and:SI (match_operand:SI 1 "general_operand" "%0")
+		(match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
+      && (GREG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+   
+    { 
+      if (GET_CODE (operands[0]) != REG)
+        operands[0] = adj_offsettable_operand (operands[0], 2);
+      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      return \"and.h %2,%0\";
+    }
+  return \"and.w %2,%0\";
+}")
+
+(define_insn "andhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(and:HI (match_operand:HI 1 "general_operand" "%0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "and.h %2,%0")
+
+(define_insn "andqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(and:QI (match_operand:QI 1 "general_operand" "%0")
+		(match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "and.b %2,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))
+		(match_operand:SI 2 "general_operand" "0")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    return \"and %1,%0.w\";
+  return \"and %1.h,%0.w\";
+}")
+
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))
+		(match_operand:SI 2 "general_operand" "0")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    return \"and %1,%0.w\";
+  return \"and %1.b,%0.w\";
+}")
+
+;; inclusive-or instructions
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(ior:SI (match_operand:SI 1 "general_operand" "%0")
+		(match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  register int logval;
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) >> 16 == 0
+      && (GREG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+    { 
+      if (GET_CODE (operands[0]) != REG)
+        operands[0] = adj_offsettable_operand (operands[0], 2);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      return \"or.h %2,%0\";
+    }
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
+      && (GREG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+    { 
+      if (GREG_P (operands[0]))
+	{
+	  if (logval < 7)
+	    {
+	      operands[1] = GEN_INT (7 - logval);
+	      return \"bset.b %1,%0\";
+	    }
+	  operands[1] = GEN_INT (31 - logval);
+	  return \"bset.w %1,%0\";
+	}
+      else
+        {
+	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+	  operands[1] = GEN_INT (7 - (logval % 8));
+	}
+      return \"bset.b %1,%0\";
+    }
+  return \"or.w %2,%0\";
+}")
+
+(define_insn "iorhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(ior:HI (match_operand:HI 1 "general_operand" "%0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "or.h %2,%0")
+
+(define_insn "iorqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(ior:QI (match_operand:QI 1 "general_operand" "%0")
+		(match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "or.b %2,%0")
+
+;; xor instructions
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(xor:SI (match_operand:SI 1 "general_operand" "%0")
+		(match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) >> 16 == 0
+      && (offsettable_memref_p (operands[0]) || GREG_P (operands[0])))
+    { 
+      if (! GREG_P (operands[0]))
+	operands[0] = adj_offsettable_operand (operands[0], 2);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      return \"xor.h %2,%0\";
+    }
+  return \"xor.w %2,%0\";
+}")
+
+(define_insn "xorhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(xor:HI (match_operand:HI 1 "general_operand" "%0")
+		(match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "xor.h %2,%0")
+
+(define_insn "xorqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(xor:QI (match_operand:QI 1 "general_operand" "%0")
+		(match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "xor.b %2,%0")
+
+;; negation instructions
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
+  ""
+  "neg.w %0")
+
+(define_insn "neghi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
+  ""
+  "neg.h %0")
+
+(define_insn "negqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
+  ""
+  "neg.b %0")
+
+(define_insn "negsf2"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
+  "TARGET_FPU"
+  "fneg.s %f1,%0")
+
+
+(define_insn "negdf2"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
+  "TARGET_FPU"
+  "fneg.d %f1,%0")
+
+
+;; Absolute value instructions
+
+(define_insn "abssf2"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+	(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
+  "TARGET_FPU"
+  "fabs.s %f1,%0")
+
+(define_insn "absdf2"
+  [(set (match_operand:DF 0 "general_operand" "=f")
+	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
+  "TARGET_FPU"
+  "fabs.d %f1,%0")
+
+
+;; one complement instructions
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(not:SI (match_operand:SI 1 "general_operand" "0")))]
+  ""
+  "not.w %0")
+
+(define_insn "one_cmplhi2"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(not:HI (match_operand:HI 1 "general_operand" "0")))]
+  ""
+  "not.h %0")
+
+(define_insn "one_cmplqi2"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(not:QI (match_operand:QI 1 "general_operand" "0")))]
+  ""
+  "not.b %0")
+
+;; Optimized special case of shifting.
+;; Must precede the general case.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
+		     (const_int 24)))]
+  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
+   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
+  "mov:l %1.b,%0.w")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
+		     (const_int 24)))]
+  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
+   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
+  "movu %1.b,%0.w")
+
+(define_insn ""
+  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
+		       (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
+				    (const_int 24))))]
+  "(GET_CODE (operands[0]) == CONST_INT
+    && (INTVAL (operands[0]) & ~0xff) == 0)"
+  "*
+{
+  cc_status.flags |= CC_REVERSED;
+  if (my_signed_comp (insn))
+    return \"cmp.b %0,%1\";
+  return \"cmpu.b %0,%1\";
+}")
+
+(define_insn ""
+  [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
+				    (const_int 24))
+		       (match_operand:QI 1 "general_operand" "i")))]
+  "(GET_CODE (operands[1]) == CONST_INT
+    && (INTVAL (operands[1]) & ~0xff) == 0)"
+  "*
+  if (my_signed_comp (insn))
+	return \"cmp.b %1,%0\";
+  return \"cmpu.b %1,%0\";
+")
+
+(define_insn ""
+  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
+		       (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
+				    (const_int 24))))]
+  "(GET_CODE (operands[0]) == CONST_INT
+    && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
+  "*
+  cc_status.flags |= CC_REVERSED;
+  if (my_signed_comp (insn))
+	return \"cmp.b %0,%1\";
+  return \"cmpu.b %0,%1\";
+")
+
+(define_insn ""
+  [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
+				    (const_int 24))
+		       (match_operand:QI 1 "general_operand" "i")))]
+  "(GET_CODE (operands[1]) == CONST_INT
+    && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
+  "*
+  if (my_signed_comp (insn))
+	return \"cmp.b %1,%0\";
+  return \"cmpu.b %1,%0\";
+")
+
+;; arithmetic shift instructions
+;; We don't need the shift memory by 1 bit instruction
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(ashift:SI (match_operand:SI 1 "general_operand" "0")
+		   (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "sha.w %2,%0")
+
+(define_insn "ashlhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(ashift:HI (match_operand:HI 1 "general_operand" "0")
+		   (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "sha.h %2,%0")
+
+(define_insn "ashlqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(ashift:QI (match_operand:QI 1 "general_operand" "0")
+		   (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "sha.b %2,%0")
+
+;; Arithmetic right shift on the Gmicro works by negating the shift count
+
+;; ashiftrt -> ashift
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(ashift:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "{ operands[2] = negate_rtx (SImode, operands[2]); }")
+
+;; ashiftrt -> ashift
+(define_expand "ashrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(ashift:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  " { operands[2] = negate_rtx (HImode, operands[2]); }")
+
+;; ashiftrt -> ashift
+(define_expand "ashrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(ashift:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  " { operands[2] = negate_rtx (QImode, operands[2]); }")
+
+;; logical shift instructions
+
+;; Logical right shift on the gmicro works by negating the shift count,
+;; then emitting a right shift with the shift count negated.  This means
+;; that all actual shift counts in the RTL will be positive.  This 
+;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
+;; which isn't valid.
+
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
+		     (match_operand:SI 2 "general_operand" "g")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "const_int_operand" "n")))]
+  ""
+  "shl.w %n2,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
+		     (neg:SI (match_operand:SI 2 "general_operand" "rm"))))]
+  ""
+  "shl.w %2,%0")
+
+(define_expand "lshrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=g")
+	(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
+		     (match_operand:HI 2 "general_operand" "g")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "const_int_operand" "n")))]
+  ""
+  "shl.h %n2,%0")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
+		     (neg:HI (match_operand:HI 2 "general_operand" "rm"))))]
+  ""
+  "shl.h %2,%0")
+
+(define_expand "lshrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=g")
+	(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
+		     (match_operand:QI 2 "general_operand" "g")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
+}")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "const_int_operand" "n")))]
+  ""
+  "shl.b %n2,%0")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
+		     (neg:QI (match_operand:QI 2 "general_operand" "rm"))))]
+  ""
+  "shl.b %2,%0")
+
+;; rotate instructions
+
+(define_insn "rotlsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(rotate:SI (match_operand:SI 1 "general_operand" "0")
+		   (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  "rol.w %2,%0")
+
+(define_insn "rotlhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(rotate:HI (match_operand:HI 1 "general_operand" "0")
+		   (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  "rol.h %2,%0")
+
+(define_insn "rotlqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(rotate:QI (match_operand:QI 1 "general_operand" "0")
+		   (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  "rol.b %2,%0")
+
+(define_expand "rotrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "general_operand" "rmi")))]
+  ""
+  " { operands[2] = negate_rtx (SImode, operands[2]); }")
+
+(define_expand "rotrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=rm")
+	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "general_operand" "rmi")))]
+  ""
+  " { operands[2] = negate_rtx (HImode, operands[2]); }")
+
+(define_expand "rotrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=rm")
+	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "general_operand" "rmi")))]
+  ""
+  " { operands[2] = negate_rtx (QImode, operands[2]); }")
+
+;; Special cases of bit-field insns which we should
+;; recognize in preference to the general case.
+;; These handle aligned 8-bit and 16-bit fields,
+;; which can usually be done with move instructions.
+
+;; Should I add  mode_dependent_address_p ????
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
+			 (match_operand:SI 1 "immediate_operand" "i")
+			 (match_operand:SI 2 "immediate_operand" "i"))
+	(match_operand:SI 3 "general_operand" "rm"))]
+  "TARGET_BITFIELD
+   && GET_CODE (operands[1]) == CONST_INT
+   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
+   && (GET_CODE (operands[0]) != REG
+       || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))"
+  "*
+{
+  if (GET_CODE (operands[3]) == MEM)
+    operands[3] = adj_offsettable_operand (operands[3],
+					   (32 - INTVAL (operands[1])) / 8);
+
+  if (GET_CODE (operands[0]) == REG)
+    {
+      if (INTVAL (operands[1]) == 8)
+	return \"movu %3.b,%0.w\";
+      return \"movu %3.h,%0.w\";
+    }
+  else
+    {
+      operands[0]
+	= adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+      if (INTVAL (operands[1]) == 8)
+	return \"mov.b %3,%0\";
+      return \"mov.h %3,%0\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=&r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "rm")
+			 (match_operand:SI 2 "immediate_operand" "i")
+			 (match_operand:SI 3 "immediate_operand" "i")))]
+  "TARGET_BITFIELD
+   && GET_CODE (operands[2]) == CONST_INT
+   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
+   && GET_CODE (operands[3]) == CONST_INT
+   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
+  "*
+{
+  if (!REG_P (operands[1]))
+    operands[1]
+      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+
+  if (REG_P (operands[0]))
+    {
+      if (REG_P (operands[1]))
+	{
+	  if (INTVAL (operands[2]) == 8)
+	    {			/* width == 8 */
+	      switch (INTVAL (operands[3]))
+		{
+		case 0:
+		  return \"mov.w %1,%0;shl.w #-24,%0\";
+		  break;
+		case 8:
+		  return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\";
+		  break;
+		case 16:
+		  return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\";
+		  break;
+		case 24:
+		  return \"movu %1.b,%0.w\";
+		  break;
+		default:
+		  myabort (2);
+		}
+	    }
+	  else
+	    {
+	      switch (INTVAL (operands[3]))
+		{
+		case 0:
+		  return \"mov.w %1,%0;shl.w #-16,%0\";
+		  break;
+		case 16:
+		  return \"movu %1.h,%0.w\";
+		  break;
+		default:
+		  myabort (3);
+		}
+	    }
+	}
+      else
+	{
+	  if (INTVAL (operands[2]) == 8)
+	    return \"movu %1.h,%0.w\";
+	  else
+	    return \"movu %1.b,%0.w\";
+	}
+    }
+  else
+    {				/* op[0] == MEM */
+      if (INTVAL (operands[2]) == 8)
+	return \"movu %1.b,%0.w\";
+      return \"movu %1.h,%0.w\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
+			 (match_operand:SI 2 "immediate_operand" "i")
+			 (match_operand:SI 3 "immediate_operand" "i")))]
+  "TARGET_BITFIELD
+   && GET_CODE (operands[2]) == CONST_INT
+   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
+   && GET_CODE (operands[3]) == CONST_INT
+   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
+  "*
+{
+  if (!REG_P (operands[1]))
+    operands[1]
+      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+
+  if (REG_P (operands[0]))
+    {
+      if (REG_P (operands[1]))
+	{
+	  if (INTVAL (operands[2]) == 8)
+	    {			/* width == 8 */
+	      switch (INTVAL (operands[3]))
+		{
+		case 0:
+		  return \"mov.w %1,%0;sha.w #-24,%0\";
+		  break;
+		case 8:
+		  return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\";
+		  break;
+		case 16:
+		  return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\";
+		  break;
+		case 24:
+		  return \"mov %1.b,%0.w\";
+		  break;
+		default:
+		  myabort (4);
+		}
+	    }
+	  else
+	    {
+	      switch (INTVAL (operands[3]))
+		{
+		case 0:
+		  return \"mov.w %1,%0;sha.w #-16,%0\";
+		  break;
+		case 16:
+		  return \"mov %1.h,%0.w\";
+		  break;
+		default:
+		  myabort (5);
+		}
+	    }
+	}
+      else
+	{
+	  if (INTVAL (operands[2]) == 8)
+	    return \"mov %1.h,%0.w\";
+	  else
+	    return \"mov %1.b,%0.w\";
+	}
+    }
+  else
+    {				/* op[0] == MEM */
+      if (INTVAL (operands[2]) == 8)
+	return \"mov %1.b,%0.w\";
+      return \"mov %1.h,%0.w\";
+    }
+}")
+
+;; Bit field instructions, general cases.
+;; "o,d" constraint causes a nonoffsettable memref to match the "o"
+;; so that its address is reloaded.
+
+;; extv dest:SI src(:QI/:SI) width:SI pos:SI
+;;        r.w    m            r.w/#    rmi  
+;;        %0     %1           %2       %3
+
+(define_expand "extv"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extract:SI (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" "")
+			 (match_operand:SI 3 "general_operand" "")))]
+  "TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
+			 (match_operand:SI 2 "general_operand" "ri")
+			 (match_operand:SI 3 "general_operand" "rmi")))]
+  "TARGET_BITFIELD"
+  "bfext %3,%2,%1,%0")
+
+
+(define_expand "extzv"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" "")
+			 (match_operand:SI 3 "general_operand" "")))]
+  "TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
+			 (match_operand:SI 2 "general_operand" "ri")
+			 (match_operand:SI 3 "general_operand" "rmi")))]
+  "TARGET_BITFIELD"
+  "bfextu %3,%2,%1,%0")
+
+;; There is no insn on the Gmicro to NOT/SET/CLR bitfield.
+
+
+;; insv dest(BF):QI/SI  width:SI  pos:SI  src:SI
+;;        m                r.w      rmi     r.w/i
+;;        0                1        2       3
+
+
+(define_expand "insv"
+  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+			 (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" ""))
+	(match_operand:SI 3 "general_operand" ""))]
+  "TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m,m")
+			 (match_operand:SI 1 "general_operand" "r,i")
+			 (match_operand:SI 2 "general_operand" "rmi,i"))
+	(match_operand:SI 3 "general_operand" "ri,ri"))]
+  "TARGET_BITFIELD"
+  "bfinsu %3,%2,%1,%0")
+
+;;; bfins/bfinsu ????????
+
+;; == == == == == == == == == == == == == 
+
+;; Now recognize bit field insns that operate on registers
+;; (or at least were intended to do so).
+
+;; On the Gmicro/300,
+;; bitfield instructions are not applicable to registers ;-<
+;; But I write the register cases, because without them the gcc
+;; seems to use "and" instruction with some other instructions
+;; instead of using a shift instruction.
+;; It is because on many processors shift instructions are slower.
+;; On the Gmicro/300 which has a barrel shifter,
+;; it is faster to use a shift instruction.
+;;
+;; Restricts width and offset to be immediates.
+;;
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_operand:SI 2 "immediate_operand" "i")
+			 (match_operand:SI 3 "immediate_operand" "i")))]
+  "TARGET_BITFIELD"
+  "*
+{
+  if (REGNO (operands[0]) != REGNO (operands[1]))
+    output_asm_insn (\"mov.w %1,%0\", operands);
+  if (INTVAL (operands[3]) != 0)
+    output_asm_insn (\"shl.w %3,%0\", operands);
+  operands[2] = GEN_INT (-(32 - INTVAL (operands[2])));
+  return \"sha.w %3,%0\";
+}")
+    
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_operand:SI 2 "immediate_operand" "i")
+			 (match_operand:SI 3 "immediate_operand" "i")))]
+  "TARGET_BITFIELD"
+  "*
+{
+  if (REGNO (operands[0]) != REGNO (operands[1]))
+    output_asm_insn (\"mov.w %1,%0\", operands);
+  if (INTVAL (operands[3]) != 0)
+    output_asm_insn (\"shl.w %3,%0\", operands);
+  operands[2] = GEN_INT (-(32 - INTVAL (operands[2])));
+  return \"shl.w %3,%0\";
+}")
+
+
+;; There are more descriptions for m68k, but not yet for the Gmicro.
+;;
+
+;; Basic conditional jump instructions.
+
+
+(define_insn "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
+}")
+
+(define_insn "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
+}")
+
+(define_insn "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0);
+")
+
+(define_insn "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "bgt %b0")
+
+(define_insn "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\");
+")
+
+;; bms ?????
+;; 
+
+(define_insn "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "blt %b0")
+
+(define_insn "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\");
+")
+
+;; bmc ??
+
+(define_insn "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "bge %b0")
+
+(define_insn "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "ble %b0")
+
+(define_insn "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "ble %b0")
+
+;; Negated conditional jump instructions.
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
+}")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
+}")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0);
+")
+;; fbngt ???
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "ble %b0")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "blt %b0")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "blt %b0")
+;; ????
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0);
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "bgt %b0")
+
+;; Unconditional and other jump instructions
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "bra %b0")
+
+(define_insn "tablejump"
+  [(set (pc)
+	(plus:SI (pc) (match_operand:SI 0 "general_operand" "r")))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmp @(pc:b,4:4,%0)")
+
+;;
+;; Should Add code for "ACB", "SCB". !!! ????
+;; See m68k.h (dbra)
+;;
+
+;; Call subroutine with no return value.
+(define_insn "call"
+  [(call (match_operand:QI 0 "general_operand" "m")
+	 (match_operand:SI 1 "general_operand" "rmi"))]
+  ;; Operand 1 not really used on the Gmicro.
+
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM
+      && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF)
+    return \"bsr %b0\";
+  return \"jsr %0\";
+}")
+
+;; Call subroutine, returning value in operand 0
+;; (which must be a hard register).
+(define_insn "call_value"
+  [(set (match_operand 0 "" "=rf")
+	(call (match_operand:QI 1 "general_operand" "m")
+	      (match_operand:SI 2 "general_operand" "rmi")))]
+  ;; Operand 2 not really used on the Gmicro.
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == MEM
+      && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF)
+    return \"bsr %b1\";
+  return \"jsr %1\";
+}")
+
+;; Call subroutine returning any type.
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+		    (const_int 0))
+	      (match_operand 1 "" "")
+	      (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
+
+  /* The optimizer does not know that the call sets the function value
+     registers we stored in the result block.  We avoid problems by
+     claiming that all hard registers are used and clobbered at this
+     point.  */
+  emit_insn (gen_blockage ());
+
+  DONE;
+}")
+
+;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
+;; all of memory.  This blocks insns from being moved across this point.
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  "")
+
+(define_insn "nop"
+  [(const_int 0)]
+    ""
+    "nop")
+
+;; Turned off because the general move-an-address pattern handles it.
+;; 
+;; Thus goes after the move instructions
+;; because the move instructions are better (require no spilling)
+;; when they can apply. 
+;; After add/sub now !!
+
+;(define_insn "pushasi"
+;  [(set (match_operand:SI 0 "push_operand" "=m")
+;	(match_operand:SI 1 "address_operand" "p"))]
+;  ""
+;  "*
+;{
+;  if (GET_CODE (operands[1]) == CONST_INT)
+;    return push_imm_word (INTVAL (operands[1]), operands[0]);
+;  if (CONSTANT_P (operands[1]))
+;    return \"mov.w %1,%-\";
+;  if (GET_CODE (operands[1]) == REG)
+;    return \"mov.w %1,%-\";
+;  else if (GET_CODE (operands[1]) == MEM)
+;    {
+;      return \"mov.w %1,%-\";
+;    }
+;  else
+;    return \"mova.w %p1,%-\";
+;}")
+
+;; This should not be used unless the add/sub insns can't be.
+
+/* mova.[whq] 89.08.11 for test M.Yuhara */
+;(define_insn ""
+;  [(set (match_operand:SI 0 "general_operand" "=rm")
+;	(address (match_operand:SI 1 "address_operand" "p")))]
+;  ""
+;  "*
+;{
+;    if (GET_CODE (operands[1]) == CONST_INT)
+;        return mov_imm_word (INTVAL (operands[1]), operands[0]);
+;    if (CONSTANT_P (operands[1]))
+;        return \"mov.w %1,%0\";
+;    if (GET_CODE (operands[1]) == REG)
+;        return \"mov.w %1,%0\";
+;    else  if (GET_CODE (operands[1]) == MEM) {
+;	operands[1] = XEXP (operands[1],0);
+;        return \"mov.w %1,%0\";
+;    }
+;    else
+;        return \"mova.w %p1,%0\";
+;}")
+
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=rm")
+	(address (match_operand:HI 1 "address_operand" "")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    return mov_imm_word (INTVAL (operands[1]), operands[0]);
+  if (CONSTANT_P (operands[1]))
+    return \"mov.w %1,%0\";
+  if (GET_CODE (operands[1]) == REG)
+    return \"mov.w %1,%0\";
+  else  if (GET_CODE (operands[1]) == MEM)
+    {
+      operands[1] = XEXP (operands[1],0);
+      return \"mov.w %1,%0\";	/* OK ? */
+    }
+  else
+    return \"mova.w %p1,%0\";
+}")
+
+;(define_insn ""
+;  [(set (match_operand:SI 0 "general_operand" "=rm")
+;	(match_operand:QI 1 "address_operand" "p"))]
+;  ""
+;  "*
+;{
+;  if (push_operand (operands[0], SImode))
+;    return \"mova %1,%-\";
+;  return \"mova %1,%0\";
+;}")
+
+;(define_insn ""
+;  [(set (match_operand:SI 0 "general_operand" "=rm")
+;	(match_operand:QI 1 "address_operand" "p"))]
+;  ""
+;  "*
+;{
+;  if (CONSTANT_P (operands[1]))
+;    return \"mov.w %1,%0\";
+;  else if (GET_CODE (operands[1]) == REG)
+;    return \"mov.w %1,%0\";
+;  else if (GET_CODE (operands[1]) == MEM)
+;    {
+;      operands[1] = XEXP (operands[1],0);
+;      return \"mov.w %1,%0 ; OK?\";
+;    }
+;  else if (GET_CODE (operands[0]) == REG
+;	   && GET_CODE (operands[1]) == PLUS)
+;    {
+;      rtx xreg, xdisp;
+;
+;      if (GET_CODE (XEXP (operands[1], 0)) == REG 
+;	  && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0]))
+;	{
+;	  xreg = XEXP (operands[1], 0);
+;	  xdisp = XEXP (operands[1],1);
+;	}
+;      else
+;	{
+;	  xreg = XEXP (operands[1], 1);
+;	  xdisp = XEXP (operands[1],0);
+;	}
+;
+;      if (GET_CODE (xreg) == REG
+;	  && REGNO (xreg) == REGNO (operands[0])
+;	  && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG))
+;	{
+;	  operands[1] = xdisp;
+;	  if (CONSTANT_P (xdisp))
+;	    return add_imm_word (INTVAL (xdisp), xreg, &operands[1]);
+;	  else
+;	    return \"add.w %1,%0\";
+;	}
+;    }
+;  return \"mova.w %p1,%0\";
+;}")
+
+;; This is the first machine-dependent peephole optimization.
+;; It is useful when a floating value is returned from a function call
+;; and then is moved into an FP register.
+;; But it is mainly intended to test the support for these optimizations.
+
+(define_peephole
+  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
+   (set (match_operand:DF 0 "register_operand" "=f")
+	(match_operand:DF 1 "register_operand" "r"))]
+  "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  output_asm_insn (\"mov.w %1,@sp\", xoperands);
+  output_asm_insn (\"mov.w %1,%-\", operands);
+  return \"fmov.d %+,%0\";
+}
+")