egcs projects compiler system

Exact copy of the snapshot, except for the removal of
	texinfo/
	gcc/ch/
	libchill/

5 files changed, 3712 insertions, 0 deletions

diff --git a/gnu/egcs/gcc/config/mn10300/mn10300.c b/gnu/egcs/gcc/config/mn10300/mn10300.c
new file mode 100644
index 00000000000..9f1ff842ab3
--- /dev/null
+++ b/gnu/egcs/gcc/config/mn10300/mn10300.c
@@ -0,0 +1,949 @@
+/* Subroutines for insn-output.c for Matsushita MN10300 series
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Jeff Law (law@cygnus.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "config.h"
+#include <stdio.h>
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "expr.h"
+#include "tree.h"
+#include "obstack.h"
+
+/* The size of the callee register save area.  Right now we save everything
+   on entry since it costs us nothing in code size.  It does cost us from a
+   speed standpoint, so we want to optimize this sooner or later.  */
+#define REG_SAVE_BYTES (4 * regs_ever_live[2] \
+			+ 4 * regs_ever_live[3] \
+			+ 4 * regs_ever_live[6] \
+			+ 4 * regs_ever_live[7])
+
+void
+asm_file_start (file)
+     FILE *file;
+{
+  fprintf (file, "#\tGCC For the Matsushita MN10300\n");
+  if (optimize)
+    fprintf (file, "# -O%d\n", optimize);
+  else
+    fprintf (file, "\n\n");
+  output_file_directive (file, main_input_filename);
+}
+
+
+/* Print operand X using operand code CODE to assembly language output file
+   FILE.  */
+
+void
+print_operand (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
+{
+  switch (code)
+    {
+      case 'b':
+      case 'B':
+	/* These are normal and reversed branches.  */
+	switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
+	  {
+	  case NE:
+	    fprintf (file, "ne");
+	    break;
+	  case EQ:
+	    fprintf (file, "eq");
+	    break;
+	  case GE:
+	    fprintf (file, "ge");
+	    break;
+	  case GT:
+	    fprintf (file, "gt");
+	    break;
+	  case LE:
+	    fprintf (file, "le");
+	    break;
+	  case LT:
+	    fprintf (file, "lt");
+	    break;
+	  case GEU:
+	    fprintf (file, "cc");
+	    break;
+	  case GTU:
+	    fprintf (file, "hi");
+	    break;
+	  case LEU:
+	    fprintf (file, "ls");
+	    break;
+	  case LTU:
+	    fprintf (file, "cs");
+	    break;
+	  default:
+	    abort ();
+	  }
+	break;
+      case 'C':
+	/* This is used for the operand to a call instruction;
+	   if it's a REG, enclose it in parens, else output
+	   the operand normally.  */
+	if (GET_CODE (x) == REG)
+	  {
+	    fputc ('(', file);
+	    print_operand (file, x, 0);
+	    fputc (')', file);
+	  }
+	else
+	  print_operand (file, x, 0);
+	break;
+     
+      /* These are the least significant word in a 64bit value.  */
+      case 'L':
+	switch (GET_CODE (x))
+	  {
+	  case MEM:
+	    fputc ('(', file);
+	    output_address (XEXP (x, 0));
+	    fputc (')', file);
+	    break;
+
+	  case REG:
+	    fprintf (file, "%s", reg_names[REGNO (x)]);
+	    break;
+
+	  case SUBREG:
+	    fprintf (file, "%s",
+		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
+	    break;
+
+	  case CONST_DOUBLE:
+	      {
+		long val[2];
+		REAL_VALUE_TYPE rv;
+
+		switch (GET_MODE (x))
+		  {
+		    case DFmode:
+		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+		      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+		      print_operand_address (file, GEN_INT (val[0]));
+		      break;;
+		    case SFmode:
+		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+		      REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
+		      print_operand_address (file, GEN_INT (val[0]));
+		      break;;
+		    case VOIDmode:
+		    case DImode:
+		      print_operand_address (file,
+					     GEN_INT (CONST_DOUBLE_LOW (x)));
+		      break;
+		  }
+		break;
+	      }
+
+	  case CONST_INT:
+	    print_operand_address (file, x);
+	    break;
+
+	  default:
+	    abort ();
+	  }
+	break;
+
+      /* Similarly, but for the most significant word.  */
+      case 'H':
+	switch (GET_CODE (x))
+	  {
+	  case MEM:
+	    fputc ('(', file);
+	    x = adj_offsettable_operand (x, 4);
+	    output_address (XEXP (x, 0));
+	    fputc (')', file);
+	    break;
+
+	  case REG:
+	    fprintf (file, "%s", reg_names[REGNO (x) + 1]);
+	    break;
+
+	  case SUBREG:
+	    fprintf (file, "%s",
+		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1);
+	    break;
+
+	  case CONST_DOUBLE:
+	      {
+		long val[2];
+		REAL_VALUE_TYPE rv;
+
+		switch (GET_MODE (x))
+		  {
+		    case DFmode:
+		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+		      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+		      print_operand_address (file, GEN_INT (val[1]));
+		      break;;
+		    case SFmode:
+		      abort ();
+		    case VOIDmode:
+		    case DImode:
+		      print_operand_address (file, 
+					     GEN_INT (CONST_DOUBLE_HIGH (x)));
+		      break;
+		  }
+		break;
+	      }
+
+	  case CONST_INT:
+	    if (INTVAL (x) < 0)
+	      print_operand_address (file, GEN_INT (-1));
+ 	    else
+	      print_operand_address (file, GEN_INT (0));
+	    break;
+	  default:
+	    abort ();
+	  }
+	break;
+
+      case 'A':
+	fputc ('(', file);
+	if (GET_CODE (XEXP (x, 0)) == REG)
+	  output_address (gen_rtx (PLUS, SImode, XEXP (x, 0), GEN_INT (0)));
+	else
+	  output_address (XEXP (x, 0));
+	fputc (')', file);
+	break;
+
+      case 'N':
+	output_address (GEN_INT ((~INTVAL (x)) & 0xff));
+	break;
+
+      /* For shift counts.  The hardware ignores the upper bits of
+	 any immediate, but the assembler will flag an out of range
+	 shift count as an error.  So we mask off the high bits
+	 of the immediate here.  */
+      case 'S':
+	if (GET_CODE (x) == CONST_INT)
+	  {
+	    fprintf (file, "%d", INTVAL (x) & 0x1f);
+	    break;
+	  }
+	/* FALL THROUGH */
+
+      default:
+	switch (GET_CODE (x))
+	  {
+	  case MEM:
+	    fputc ('(', file);
+	    output_address (XEXP (x, 0));
+	    fputc (')', file);
+	    break;
+
+	  case PLUS:
+	    output_address (x);
+	    break;
+
+	  case REG:
+	    fprintf (file, "%s", reg_names[REGNO (x)]);
+	    break;
+
+	  case SUBREG:
+	    fprintf (file, "%s",
+		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
+	    break;
+
+	  /* This will only be single precision....  */
+	  case CONST_DOUBLE:
+	    {
+	      unsigned long val;
+	      REAL_VALUE_TYPE rv;
+
+	      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+	      REAL_VALUE_TO_TARGET_SINGLE (rv, val);
+	      print_operand_address (file, GEN_INT (val));
+	      break;
+	    }
+
+	  case CONST_INT:
+	  case SYMBOL_REF:
+	  case CONST:
+	  case LABEL_REF:
+	  case CODE_LABEL:
+	    print_operand_address (file, x);
+	    break;
+	  default:
+	    abort ();
+	  }
+	break;
+   }
+}
+
+/* Output assembly language output for the address ADDR to FILE.  */
+
+void
+print_operand_address (file, addr)
+     FILE *file;
+     rtx addr;
+{
+  switch (GET_CODE (addr))
+    {
+    case REG:
+      if (addr == stack_pointer_rtx)
+	print_operand_address (file, gen_rtx (PLUS, SImode,
+					      stack_pointer_rtx,
+					      GEN_INT (0)));
+      else
+	print_operand (file, addr, 0);
+      break;
+    case PLUS:
+      {
+	rtx base, index;
+	if (REG_P (XEXP (addr, 0))
+	    && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
+	  base = XEXP (addr, 0), index = XEXP (addr, 1);
+	else if (REG_P (XEXP (addr, 1))
+	    && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
+	  base = XEXP (addr, 1), index = XEXP (addr, 0);
+      	else
+	  abort ();
+	print_operand (file, index, 0);
+	fputc (',', file);
+	print_operand (file, base, 0);;
+	break;
+      }
+    case SYMBOL_REF:
+      output_addr_const (file, addr);
+      break;
+    default:
+      output_addr_const (file, addr);
+      break;
+    }
+}
+
+int
+can_use_return_insn ()
+{
+  /* size includes the fixed stack space needed for function calls.  */
+  int size = get_frame_size () + current_function_outgoing_args_size;
+
+  /* And space for the return pointer.  */
+  size += current_function_outgoing_args_size ? 4 : 0;
+
+  return (reload_completed
+	  && size == 0
+	  && !regs_ever_live[2]
+	  && !regs_ever_live[3]
+	  && !regs_ever_live[6]
+	  && !regs_ever_live[7]
+	  && !frame_pointer_needed);
+}
+
+void
+expand_prologue ()
+{
+  unsigned int size;
+
+  /* SIZE includes the fixed stack space needed for function calls.  */
+  size = get_frame_size () + current_function_outgoing_args_size;
+  size += (current_function_outgoing_args_size ? 4 : 0);
+
+  /* If this is an old-style varargs function, then its arguments
+     need to be flushed back to the stack.  */
+  if (current_function_varargs)
+    {
+      emit_move_insn (gen_rtx (MEM, SImode,
+			       gen_rtx (PLUS, Pmode, stack_pointer_rtx,
+					GEN_INT (4))),
+		      gen_rtx (REG, SImode, 0));
+      emit_move_insn (gen_rtx (MEM, SImode,
+			       gen_rtx (PLUS, Pmode, stack_pointer_rtx,
+					GEN_INT (8))),
+		      gen_rtx (REG, SImode, 1));
+    }
+
+  /* And now store all the registers onto the stack with a
+     single two byte instruction.  */
+  if (regs_ever_live[2] || regs_ever_live[3]
+      || regs_ever_live[6] || regs_ever_live[7]
+      || frame_pointer_needed)
+    emit_insn (gen_store_movm ());
+
+  /* Now put the frame pointer into the frame pointer register.  */
+  if (frame_pointer_needed)
+    emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
+
+  /* Allocate stack for this frame.  */
+  if (size)
+    emit_insn (gen_addsi3 (stack_pointer_rtx,
+			   stack_pointer_rtx,
+			   GEN_INT (-size)));
+}
+
+void
+expand_epilogue ()
+{
+  unsigned int size;
+
+  /* SIZE includes the fixed stack space needed for function calls.  */
+  size = get_frame_size () + current_function_outgoing_args_size;
+  size += (current_function_outgoing_args_size ? 4 : 0);
+
+  /* Maybe cut back the stack, except for the register save area.
+
+     If the frame pointer exists, then use the frame pointer to
+     cut back the stack.
+
+     If the stack size + register save area is more than 255 bytes,
+     then the stack must be cut back here since the size + register
+     save size is too big for a ret/retf instruction. 
+
+     Else leave it alone, it will be cut back as part of the
+     ret/retf instruction, or there wasn't any stack to begin with.
+
+     Under no circumstanes should the register save area be
+     deallocated here, that would leave a window where an interrupt
+     could occur and trash the register save area.  */
+  if (frame_pointer_needed)
+    {
+      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
+      size = 0;
+    }
+  else if ((regs_ever_live[2] || regs_ever_live[3]
+	    || regs_ever_live[6] || regs_ever_live[7])
+	   && size + REG_SAVE_BYTES > 255)
+    {
+      emit_insn (gen_addsi3 (stack_pointer_rtx,
+			     stack_pointer_rtx,
+			     GEN_INT (size)));
+      size = 0;
+    }
+
+  /* For simplicity, we just movm all the callee saved registers to
+     the stack with one instruction.
+
+     ?!? Only save registers which are actually used.  Reduces
+     stack requirements and is faster.  */
+  if (regs_ever_live[2] || regs_ever_live[3]
+      || regs_ever_live[6] || regs_ever_live[7]
+      || frame_pointer_needed)
+    emit_jump_insn (gen_return_internal_regs (GEN_INT (size + REG_SAVE_BYTES)));
+  else
+    {
+      if (size)
+	{
+	  emit_insn (gen_addsi3 (stack_pointer_rtx,
+				 stack_pointer_rtx,
+				 GEN_INT (size)));
+	  emit_jump_insn (gen_return_internal ());
+	}
+      else
+	{
+	  emit_jump_insn (gen_return ());
+	}
+    }
+}
+
+/* Update the condition code from the insn.  */
+
+void
+notice_update_cc (body, insn)
+     rtx body;
+     rtx insn;
+{
+  switch (get_attr_cc (insn))
+    {
+    case CC_NONE:
+      /* Insn does not affect CC at all.  */
+      break;
+
+    case CC_NONE_0HIT:
+      /* Insn does not change CC, but the 0'th operand has been changed.  */
+      if (cc_status.value1 != 0
+	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
+	cc_status.value1 = 0;
+      break;
+
+    case CC_SET_ZN:
+      /* Insn sets the Z,N flags of CC to recog_operand[0].
+	 V,C are unusable.  */
+      CC_STATUS_INIT;
+      cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
+      cc_status.value1 = recog_operand[0];
+      break;
+
+    case CC_SET_ZNV:
+      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
+	 C is unusable.  */
+      CC_STATUS_INIT;
+      cc_status.flags |= CC_NO_CARRY;
+      cc_status.value1 = recog_operand[0];
+      break;
+
+    case CC_COMPARE:
+      /* The insn is a compare instruction.  */
+      CC_STATUS_INIT;
+      cc_status.value1 = SET_SRC (body);
+      break;
+
+    case CC_INVERT:
+      /* The insn is a compare instruction.  */
+      CC_STATUS_INIT;
+      cc_status.value1 = SET_SRC (body);
+      cc_status.flags |= CC_INVERTED;
+      break;
+
+    case CC_CLOBBER:
+      /* Insn doesn't leave CC in a usable state.  */
+      CC_STATUS_INIT;
+      break;
+
+    default:
+      abort ();
+    }
+}
+
+/* Return true if OP is a valid call operand.  */
+
+int
+call_address_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+}
+
+/* What (if any) secondary registers are needed to move IN with mode
+   MODE into a register from in register class CLASS. 
+
+   We might be able to simplify this.  */
+enum reg_class
+secondary_reload_class (class, mode, in)
+     enum reg_class class;
+     enum machine_mode mode;
+     rtx in;
+{
+  int regno;
+
+  /* Memory loads less than a full word wide can't have an
+     address or stack pointer destination.  They must use
+     a data register as an intermediate register.  */
+  if (GET_CODE (in) == MEM
+      && (mode == QImode || mode == HImode)
+      && (class == ADDRESS_REGS || class == SP_REGS))
+    {
+      return DATA_REGS;
+    }
+
+  /* We can't directly load sp + const_int into a data register;
+     we must use an address register as an intermediate.  */
+  if (class != SP_REGS
+      && class != ADDRESS_REGS
+      && class != SP_OR_ADDRESS_REGS
+      && (in == stack_pointer_rtx
+	  || (GET_CODE (in) == PLUS
+	      && (XEXP (in, 0) == stack_pointer_rtx
+		  || XEXP (in, 1) == stack_pointer_rtx))))
+    return ADDRESS_REGS;
+
+  if (GET_CODE (in) == PLUS
+      && (XEXP (in, 0) == stack_pointer_rtx
+	  || XEXP (in, 1) == stack_pointer_rtx))
+    {
+      return DATA_REGS;
+    }
+ 
+  /* Otherwise assume no secondary reloads are needed.  */
+  return NO_REGS;
+}
+
+int
+initial_offset (from, to)
+     int from, to;
+{
+  /* The difference between the argument pointer and the frame pointer
+     is the size of the callee register save area.  */
+  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+    {
+      if (regs_ever_live[2] || regs_ever_live[3]
+	  || regs_ever_live[6] || regs_ever_live[7]
+	  || frame_pointer_needed)
+	return REG_SAVE_BYTES;
+      else
+	return 0;
+    }
+
+  /* The difference between the argument pointer and the stack pointer is
+     the sum of the size of this function's frame, the callee register save
+     area, and the fixed stack space needed for function calls (if any).  */
+  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    {
+      if (regs_ever_live[2] || regs_ever_live[3]
+	  || regs_ever_live[6] || regs_ever_live[7]
+	  || frame_pointer_needed)
+	return (get_frame_size () + REG_SAVE_BYTES
+		+ (current_function_outgoing_args_size
+		   ? current_function_outgoing_args_size + 4 : 0)); 
+      else
+	return (get_frame_size ()
+		+ (current_function_outgoing_args_size
+		   ? current_function_outgoing_args_size + 4 : 0)); 
+    }
+
+  /* The difference between the frame pointer and stack pointer is the sum
+     of the size of this function's frame and the fixed stack space needed
+     for function calls (if any).  */
+  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    return (get_frame_size ()
+	    + (current_function_outgoing_args_size
+	       ? current_function_outgoing_args_size + 4 : 0)); 
+
+  abort ();
+}
+
+/* Flush the argument registers to the stack for a stdarg function;
+   return the new argument pointer.  */
+rtx
+mn10300_builtin_saveregs (arglist)
+     tree arglist;
+{
+  rtx offset;
+  tree fntype = TREE_TYPE (current_function_decl);
+  int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
+                   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
+                       != void_type_node)))
+                ? UNITS_PER_WORD : 0);
+
+  if (argadj)
+    offset = plus_constant (current_function_arg_offset_rtx, argadj);
+  else
+    offset = current_function_arg_offset_rtx;
+
+  emit_move_insn (gen_rtx (MEM, SImode, current_function_internal_arg_pointer),
+		  gen_rtx (REG, SImode, 0));
+  emit_move_insn (gen_rtx (MEM, SImode,
+			   plus_constant
+			     (current_function_internal_arg_pointer, 4)),
+		  gen_rtx (REG, SImode, 1));
+  return copy_to_reg (expand_binop (Pmode, add_optab,
+				    current_function_internal_arg_pointer,
+				    offset, 0, 0, OPTAB_LIB_WIDEN));
+}
+
+/* Return an RTX to represent where a value with mode MODE will be returned
+   from a function.  If the result is 0, the argument is pushed.  */
+
+rtx
+function_arg (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  rtx result = 0;
+  int size, align;
+
+  /* We only support using 2 data registers as argument registers.  */
+  int nregs = 2;
+
+  /* Figure out the size of the object to be passed.  */
+  if (mode == BLKmode)
+    size = int_size_in_bytes (type);
+  else
+    size = GET_MODE_SIZE (mode);
+
+  /* Figure out the alignment of the object to be passed.  */
+  align = size;
+
+  cum->nbytes = (cum->nbytes + 3) & ~3;
+
+  /* Don't pass this arg via a register if all the argument registers
+     are used up.  */
+  if (cum->nbytes > nregs * UNITS_PER_WORD)
+    return 0;
+
+  /* Don't pass this arg via a register if it would be split between
+     registers and memory.  */
+  if (type == NULL_TREE
+      && cum->nbytes + size > nregs * UNITS_PER_WORD)
+    return 0;
+
+  switch (cum->nbytes / UNITS_PER_WORD)
+    {
+    case 0:
+      result = gen_rtx (REG, mode, 0);
+      break;
+    case 1:
+      result = gen_rtx (REG, mode, 1);
+      break;
+    default:
+      result = 0;
+    }
+
+  return result;
+}
+
+/* Return the number of registers to use for an argument passed partially
+   in registers and partially in memory.  */
+
+int
+function_arg_partial_nregs (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  int size, align;
+
+  /* We only support using 2 data registers as argument registers.  */
+  int nregs = 2;
+
+  /* Figure out the size of the object to be passed.  */
+  if (mode == BLKmode)
+    size = int_size_in_bytes (type);
+  else
+    size = GET_MODE_SIZE (mode);
+
+  /* Figure out the alignment of the object to be passed.  */
+  align = size;
+
+  cum->nbytes = (cum->nbytes + 3) & ~3;
+
+  /* Don't pass this arg via a register if all the argument registers
+     are used up.  */
+  if (cum->nbytes > nregs * UNITS_PER_WORD)
+    return 0;
+
+  if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
+    return 0;
+
+  /* Don't pass this arg via a register if it would be split between
+     registers and memory.  */
+  if (type == NULL_TREE
+      && cum->nbytes + size > nregs * UNITS_PER_WORD)
+    return 0;
+
+  return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
+}
+
+/* Output a tst insn.  */
+char *
+output_tst (operand, insn)
+     rtx operand, insn;
+{
+  rtx temp;
+  int past_call = 0;
+
+  /* We can save a byte if we can find a register which has the value
+     zero in it.  */
+  temp = PREV_INSN (insn);
+  while (optimize && temp)
+    {
+      rtx set;
+
+      /* We allow the search to go through call insns.  We record
+	 the fact that we've past a CALL_INSN and reject matches which
+	 use call clobbered registers.  */
+      if (GET_CODE (temp) == CODE_LABEL
+	  || GET_CODE (temp) == JUMP_INSN
+	  || GET_CODE (temp) == BARRIER)
+	break;
+
+      if (GET_CODE (temp) == CALL_INSN)
+	past_call = 1;
+
+      if (GET_CODE (temp) == NOTE)
+	{
+	  temp = PREV_INSN (temp);
+	  continue;
+	}
+
+      /* It must be an insn, see if it is a simple set. */
+      set = single_set (temp);
+      if (!set)
+	{
+	  temp = PREV_INSN (temp);
+	  continue;
+	}
+
+      /* Are we setting a data register to zero (this does not win for
+	 address registers)? 
+
+	 If it's a call clobbered register, have we past a call?
+
+	 Make sure the register we find isn't the same as ourself;
+	 the mn10300 can't encode that.
+
+	 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
+	 so the code to detect calls here isn't doing anything useful.  */
+      if (REG_P (SET_DEST (set))
+	  && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
+	  && !reg_set_between_p (SET_DEST (set), temp, insn)
+	  && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
+	      == REGNO_REG_CLASS (REGNO (operand)))
+	  && REGNO (SET_DEST (set)) != REGNO (operand)
+	  && (!past_call 
+	      || !call_used_regs[REGNO (SET_DEST (set))]))
+	{
+	  rtx xoperands[2];
+	  xoperands[0] = operand;
+	  xoperands[1] = SET_DEST (set);
+
+	  output_asm_insn ("cmp %1,%0", xoperands);
+	  return "";
+	}
+      temp = PREV_INSN (temp);
+    }
+  return "cmp 0,%0";
+}
+
+int
+impossible_plus_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  extern rtx *reg_equiv_mem;
+  rtx reg1, reg2;
+  
+  if (GET_CODE (op) != PLUS)
+    return 0;
+
+  if (XEXP (op, 0) == stack_pointer_rtx
+      || XEXP (op, 1) == stack_pointer_rtx)
+    return 1;
+
+  return 0;
+}
+
+/* Return 1 if X is a CONST_INT that is only 8 bits wide.  This is used
+   for the btst insn which may examine memory or a register (the memory
+   variant only allows an unsigned 8 bit integer).  */
+int
+const_8bit_operand (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return (GET_CODE (op) == CONST_INT
+	  && INTVAL (op) >= 0
+	  && INTVAL (op) < 256);
+}
+
+/* Similarly, but when using a zero_extract pattern for a btst where
+   the source operand might end up in memory.  */
+int
+mask_ok_for_mem_btst (len, bit)
+     int len;
+     int bit;
+{
+  int mask = 0;
+
+  while (len > 0)
+    {
+      mask |= (1 << bit);
+      bit++;
+      len--;
+    }
+
+  /* MASK must bit into an 8bit value.  */
+  return (((mask & 0xff) == mask)
+	  || ((mask & 0xff00) == mask)
+	  || ((mask & 0xff0000) == mask)
+	  || ((mask & 0xff000000) == mask));
+}
+
+/* Return 1 if X contains a symbolic expression.  We know these
+   expressions will have one of a few well defined forms, so
+   we need only check those forms.  */
+int
+symbolic_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case SYMBOL_REF:
+    case LABEL_REF:
+      return 1;
+    case CONST:
+      op = XEXP (op, 0);
+      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+               || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+              && GET_CODE (XEXP (op, 1)) == CONST_INT);
+    default:
+      return 0;
+    }
+}
+
+/* Try machine dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   Normally it is always safe for this macro to do nothing.  It exists to
+   recognize opportunities to optimize the output.
+
+   But on a few ports with segmented architectures and indexed addressing
+   (mn10300, hppa) it is used to rewrite certain problematical addresses.  */
+rtx
+legitimize_address (x, oldx, mode)
+     rtx x;
+     rtx oldx;
+     enum machine_mode mode;
+{
+  /* Uh-oh.  We might have an address for x[n-100000].  This needs
+     special handling to avoid creating an indexed memory address
+     with x-100000 as the base.  */
+  if (GET_CODE (x) == PLUS
+      && symbolic_operand (XEXP (x, 1), VOIDmode))
+    {
+      /* Ugly.  We modify things here so that the address offset specified
+         by the index expression is computed first, then added to x to form
+         the entire address.  */
+
+      rtx regx1, regx2, regy1, regy2, y;
+
+      /* Strip off any CONST.  */
+      y = XEXP (x, 1);
+      if (GET_CODE (y) == CONST)
+        y = XEXP (y, 0);
+
+      if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
+	{
+	  regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
+	  regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
+	  regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
+	  regx1 = force_reg (Pmode,
+			     gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
+	  return force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regy1));
+	}
+    }
+  return x;
+}
diff --git a/gnu/egcs/gcc/config/mn10300/mn10300.h b/gnu/egcs/gcc/config/mn10300/mn10300.h
new file mode 100644
index 00000000000..3c2a6a7c37a
--- /dev/null
+++ b/gnu/egcs/gcc/config/mn10300/mn10300.h
@@ -0,0 +1,1045 @@
+/* Definitions of target machine for GNU compiler. Matsushita MN10300 series
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Jeff Law (law@cygnus.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "svr4.h"
+
+#undef ASM_SPEC
+#undef ASM_FINAL_SPEC
+#undef LIB_SPEC
+#undef ENDFILE_SPEC
+#undef LINK_SPEC
+#undef STARTFILE_SPEC
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-D__mn10300__ -D__MN10300__"
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+
+/* Macros used in the machine description to test the flags.  */
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+/* Generate code to work around mul/mulq bugs on the mn10300.  */
+#define TARGET_MULT_BUG			(target_flags & 0x1)
+#define TARGET_SWITCHES  \
+  {{ "mult-bug",	0x1,  "Work around hardware multiply bug"},	\
+   { "no-mult-bug", 	-0x1, "Do not work around hardware multiply bug"},\
+   { "", TARGET_DEFAULT, NULL}}
+
+#ifndef TARGET_DEFAULT
+#define TARGET_DEFAULT 0x1
+#endif
+
+/* Print subsidiary information on the compiler version in use.  */
+
+#define TARGET_VERSION fprintf (stderr, " (MN10300)");
+
+
+/* Target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is not true on the Matsushita MN1003.  */
+#define BITS_BIG_ENDIAN 0
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+/* This is not true on the Matsushita MN10300.  */
+#define BYTES_BIG_ENDIAN 0
+
+/* Define this if most significant word of a multiword number is lowest
+   numbered.
+   This is not true on the Matsushita MN10300.  */
+#define WORDS_BIG_ENDIAN 0
+
+/* Number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD		32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD		4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 		32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY		32
+
+/* The stack goes in 32 bit lumps.  */
+#define STACK_BOUNDARY 		32
+
+/* Allocation boundary (in *bits*) for the code of a function.
+   8 is the minimum boundary; it's unclear if bigger alignments
+   would improve performance.  */
+#define FUNCTION_BOUNDARY 8
+
+/* No data type wants to be aligned rounder than this.   */
+#define BIGGEST_ALIGNMENT	32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Define this if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+
+#define FIRST_PSEUDO_REGISTER 10
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.  */
+
+#define FIXED_REGISTERS \
+  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you
+   like.  */
+
+#define CALL_USED_REGISTERS \
+  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
+
+#define REG_ALLOC_ORDER \
+  { 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.  */
+
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode
+   MODE.  */
+
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ (REGNO_REG_CLASS (REGNO) == DATA_REGS 			\
+  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
+  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+  (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
+
+/* 4 data, and effectively 3 address registers is small as far as I'm
+   concerned.  */
+#define SMALL_REGISTER_CLASSES 1
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+   
+enum reg_class {
+  NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
+  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, 
+  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
+  "SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
+  "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS  			\
+{      0,		/* No regs      */	\
+   0x00f,		/* DATA_REGS */		\
+   0x1f0,		/* ADDRESS_REGS */	\
+   0x200,		/* SP_REGS */		\
+   0x1ff,		/* DATA_OR_ADDRESS_REGS */\
+   0x1f0,		/* SP_OR_ADDRESS_REGS */\
+   0x1ff,		/* GENERAL_REGS */    	\
+   0x3ff,		/* ALL_REGS 	*/	\
+}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+#define REGNO_REG_CLASS(REGNO) \
+  ((REGNO) < 4 ? DATA_REGS : \
+   (REGNO) < 9 ? ADDRESS_REGS : \
+    (REGNO) == 9 ? SP_REGS : 0)
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS DATA_REGS
+#define BASE_REG_CLASS  SP_OR_ADDRESS_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) \
+  ((C) == 'd' ? DATA_REGS : \
+   (C) == 'a' ? ADDRESS_REGS : \
+   (C) == 'y' ? SP_REGS : NO_REGS)
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+ 
+#define REGNO_OK_FOR_BASE_P(regno) \
+  (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER)	\
+   || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
+
+#define REGNO_OK_FOR_BIT_BASE_P(regno) \
+  (((regno) > 3 && regno < 10)	\
+   || (reg_renumber[regno] > 3 && reg_renumber[regno] < 10))
+
+#define REGNO_OK_FOR_INDEX_P(regno) \
+  (((regno) >= 0 && regno < 4)	\
+   || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
+
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS) \
+  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
+  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+
+#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
+  ((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
+
+#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
+  secondary_reload_class(CLASS,MODE,IN)
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* The letters I, J, K, L, M, N, O, P in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.  */
+
+#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
+#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
+
+#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
+#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
+#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
+#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
+#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
+#define CONST_OK_FOR_N(VALUE) ((VALUE) == 255 || (VALUE) == 65535)
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
+  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
+   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
+   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
+   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
+   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
+   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : 0)
+
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself. 
+     
+  `G' is a floating-point zero.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
+  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
+		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) : 0)
+
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+
+#define STARTING_FRAME_OFFSET 0
+
+/* Offset of first parameter from the argument pointer register value.  */
+/* Is equal to the size of the saved fp + pc, even if an fp isn't
+   saved since the value is used before we know.  */
+
+#define FIRST_PARM_OFFSET(FNDECL) 4
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 9
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 7
+
+/* Base register for access to arguments of the function.  This
+   is a fake register and will be eliminated into either the frame
+   pointer or stack pointer.  */
+#define ARG_POINTER_REGNUM 8
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM 5
+
+#define ELIMINABLE_REGS				\
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+
+#define CAN_ELIMINATE(FROM, TO) 1
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+  OFFSET = initial_offset (FROM, TO)
+
+/* We can debug without frame pointers on the mn10300, so eliminate
+   them whenever possible.  */
+#define FRAME_POINTER_REQUIRED 0
+#define CAN_DEBUG_WITHOUT_FP
+
+/* A guess for the MN10300.  */
+#define PROMOTE_PROTOTYPES 1
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.  */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
+
+/* We use d0/d1 for passing parameters, so allocate 8 bytes of space
+   for a register flushback area.  */
+#define REG_PARM_STACK_SPACE(DECL) 8
+#define OUTGOING_REG_PARM_STACK_SPACE
+#define ACCUMULATE_OUTGOING_ARGS
+
+/* So we can allocate space for return pointers once for the function
+   instead of around every call.  */
+#define STACK_POINTER_OFFSET 4
+
+/* 1 if N is a possible register number for function argument passing.
+   On the MN10300, no registers are used in this way.  */
+
+#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
+
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the MN10300, this is a single integer, which is a number of bytes
+   of arguments scanned so far.  */
+
+#define CUMULATIVE_ARGS struct cum_arg
+struct cum_arg {int nbytes; };
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On the MN10300, the offset starts at 0.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
+ ((CUM).nbytes = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM).nbytes += ((MODE) != BLKmode			\
+	           ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
+	           : (int_size_in_bytes (TYPE) + 3) & ~3))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+/* On the MN10300 all args are pushed.  */   
+
+extern struct rtx_def *function_arg ();
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+  function_arg (&CUM, MODE, TYPE, NAMED)
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
+
+
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
+  ((TYPE) && int_size_in_bytes (TYPE) > 8)
+ 
+#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
+  ((TYPE) && int_size_in_bytes (TYPE) > 8)
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.   */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), POINTER_TYPE_P (VALTYPE) ? 4 : 0)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
+
+/* 1 if N is a possible register number for a function value.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
+
+/* Return values > 8 bytes in length in memory.  */
+#define DEFAULT_PCC_STRUCT_RETURN 0
+#define RETURN_IN_MEMORY(TYPE)  \
+  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
+
+/* Register in which address to store a structure value
+   is passed to a function.  On the MN10300 it's passed as
+   the first parameter.  */
+
+#define STRUCT_VALUE 0
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO) ;
+
+#define TRAMPOLINE_TEMPLATE(FILE)			\
+  do {							\
+    fprintf (FILE, "\tadd -4,sp\n");			\
+    fprintf (FILE, "\t.long 0x0004fffa\n");		\
+    fprintf (FILE, "\tmov (0,sp),a0\n");		\
+    fprintf (FILE, "\tadd 4,sp\n");			\
+    fprintf (FILE, "\tmov (13,a0),a1\n");		\
+    fprintf (FILE, "\tmov (17,a0),a0\n");		\
+    fprintf (FILE, "\tjmp (a0)\n");			\
+    fprintf (FILE, "\t.long 0\n");			\
+    fprintf (FILE, "\t.long 0\n");			\
+  } while (0)
+
+/* Length in units of the trampoline for entering a nested function.  */
+
+#define TRAMPOLINE_SIZE 0x1b
+
+#define TRAMPOLINE_ALIGNMENT 32
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
+{									\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x14)),	\
+ 		 (CXT));						\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x18)),	\
+		 (FNADDR));						\
+}
+/* A C expression whose value is RTL representing the value of the return
+   address for the frame COUNT steps up from the current frame.
+
+   On the mn10300, the return address is not at a constant location
+   due to the frame layout.  Luckily, it is at a constant offset from
+   the argument pointer, so we define RETURN_ADDR_RTX to return a
+   MEM using arg_pointer_rtx.  Reload will replace arg_pointer_rtx
+   with a reference to the stack/frame pointer + an appropriate offset.  */
+
+#define RETURN_ADDR_RTX(COUNT, FRAME)   \
+  ((COUNT == 0)                         \
+   ? gen_rtx (MEM, Pmode, arg_pointer_rtx) \
+   : (rtx) 0)
+
+/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
+   reference the 2 integer arg registers.
+   Ordinarily they are not call used registers, but they are for
+   _builtin_saveregs, so we must make this explicit.  */
+
+extern struct rtx_def *mn10300_builtin_saveregs ();
+#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) mn10300_builtin_saveregs (ARGLIST)
+
+/* Addressing modes, and classification of registers for them.  */
+
+
+/* 1 if X is an rtx for a constant that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
+
+/* Extra constraints.  */
+ 
+#define OK_FOR_R(OP) \
+   (GET_CODE (OP) == MEM					\
+    && GET_MODE (OP) == QImode					\
+    && (CONSTANT_ADDRESS_P (XEXP (OP, 0))			\
+	|| (GET_CODE (XEXP (OP, 0)) == REG			\
+	    && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0))		\
+	    && XEXP (OP, 0) != stack_pointer_rtx)		\
+	|| (GET_CODE (XEXP (OP, 0)) == PLUS			\
+	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG		\
+	    && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0))	\
+	    && XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx	\
+	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT	\
+	    && INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
+	 
+#define EXTRA_CONSTRAINT(OP, C) \
+ ((C) == 'R' ? OK_FOR_R (OP) : (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : 0)
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X)  \
+  ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= 10)
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) \
+  ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= 10)
+#define REG_OK_FOR_BIT_BASE_P(X) \
+  ((REGNO (X) >= 4 && REGNO(X) <= 9))
+#else
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BIT_BASE_P(X) REGNO_OK_FOR_BIT_BASE_P (REGNO (X))
+#endif
+
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
+   except for CONSTANT_ADDRESS_P which is actually
+   machine-independent.
+
+   On the mn10300, the value in the address register must be
+   in the same memory space/segment as the effective address.
+
+   This is problematical for reload since it does not understand
+   that base+index != index+base in a memory reference.
+
+   Note it is still possible to use reg+reg addressing modes,
+   it's just much more difficult.  For a discussion of a possible
+   workaround and solution, see the comments in pa.c before the
+   function record_unscaled_index_insn_codes.  */
+
+/* Accept either REG or SUBREG where a register is valid.  */
+  
+#define RTX_OK_FOR_BASE_P(X)					\
+  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
+   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
+       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
+{							\
+  if (CONSTANT_ADDRESS_P (X))				\
+    goto ADDR;						\
+  if (RTX_OK_FOR_BASE_P (X))				\
+    goto ADDR;						\
+  if (GET_CODE (X) == PLUS)				\
+    {							\
+      rtx base = 0, index = 0;				\
+      if (REG_P (XEXP (X, 0))				\
+	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
+	base = XEXP (X, 0), index = XEXP (X, 1);	\
+      if (REG_P (XEXP (X, 1))				\
+	  && REG_OK_FOR_BASE_P (XEXP (X, 1)))		\
+	base = XEXP (X, 1), index = XEXP (X, 0);	\
+      if (base != 0 && index != 0)			\
+	{						\
+	  if (GET_CODE (index) == CONST_INT)		\
+	    goto ADDR;					\
+	}						\
+    }							\
+}
+
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.   */
+
+extern struct rtx_def *legitimize_address ();
+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)  \
+{ rtx orig_x = (X);				\
+  (X) = legitimize_address (X, OLDX, MODE);	\
+  if ((X) != orig_x && memory_address_p (MODE, X)) \
+    goto WIN; }
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_CONSTANT_P(X) 1
+
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  No extra ones are needed for the vax.  */
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+#define CC_OVERFLOW_UNUSABLE 0x200
+#define CC_NO_CARRY CC_NO_OVERFLOW
+#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:							\
+    /* Zeros are extremely cheap.  */					\
+    if (INTVAL (RTX) == 0 && OUTER_CODE == SET)				\
+      return 0;								\
+    /* If it fits in 8 bits, then it's still relatively cheap.  */	\
+    if (INT_8_BITS (INTVAL (RTX)))					\
+      return 1;								\
+    /* This is the "base" cost, includes constants where either the	\
+       upper or lower 16bits are all zeros.  */				\
+    if (INT_16_BITS (INTVAL (RTX))					\
+	|| (INTVAL (RTX) & 0xffff) == 0					\
+	|| (INTVAL (RTX) & 0xffff0000) == 0)				\
+      return 2;								\
+    return 4;								\
+  /* These are more costly than a CONST_INT, but we can relax them,	\
+     so they're less costly than a CONST_DOUBLE.  */			\
+  case CONST:								\
+  case LABEL_REF:							\
+  case SYMBOL_REF:							\
+    return 6;								\
+  /* We don't optimize CONST_DOUBLEs well nor do we relax them well,	\
+     so their cost is very high.  */					\
+  case CONST_DOUBLE:							\
+    return 8;
+
+
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)  (CLASS1 != CLASS2 ? 4 : 2)
+
+/* A crude cut at RTX_COSTS for the MN10300.  */
+
+/* Provide the costs of a rtl expression.  This is in the body of a
+   switch on CODE.  */
+#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
+  case UMOD:		\
+  case UDIV:		\
+  case MOD:		\
+  case DIV:		\
+    return 8;		\
+  case MULT:		\
+    return 8;
+
+/* Nonzero if access to memory by bytes or half words is no faster
+   than accessing full words.  */
+#define SLOW_BYTE_ACCESS 1
+
+/* Dispatch tables on the mn10300 are extremely expensive in terms of code
+   and readonly data size.  So we crank up the case threshold value to
+   encourage a series of if/else comparisons to implement many small switch
+   statements.  In theory, this value could be increased much more if we
+   were solely optimizing for space, but we keep it "reasonable" to avoid
+   serious code efficiency lossage.  */
+#define CASE_VALUES_THRESHOLD 6
+
+#define NO_FUNCTION_CSE
+
+/* According expr.c, a value of around 6 should minimize code size, and
+   for the MN10300 series, that's our primary concern.  */
+#define MOVE_RATIO 6
+
+#define TEXT_SECTION_ASM_OP "\t.section .text"
+#define DATA_SECTION_ASM_OP "\t.section .data"
+#define BSS_SECTION_ASM_OP "\t.section .bss"
+
+/* Output at beginning/end of assembler file.  */
+#undef ASM_FILE_START
+#define ASM_FILE_START(FILE) asm_file_start(FILE)
+
+#define ASM_COMMENT_START "#"
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON "#APP\n"
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF "#NO_APP\n"
+
+/* This is how to output an assembler line defining a `double' constant.
+   It is .dfloat or .gfloat, depending.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
+do { char dstr[30];					\
+     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
+     fprintf (FILE, "\t.double %s\n", dstr);		\
+   } while (0)
+
+
+/* This is how to output an assembler line defining a `float' constant.  */
+#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
+do { char dstr[30];					\
+     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
+     fprintf (FILE, "\t.float %s\n", dstr);		\
+   } while (0)
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE, VALUE)		\
+( fprintf (FILE, "\t.long "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
+( fprintf (FILE, "\t.hword "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
+( fprintf (FILE, "\t.byte "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
+  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* This says how to output the assembler to define a global
+   uninitialized but not common symbol.
+   Try to use asm_output_bss to implement this macro.  */
+
+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
+  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE, NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
+  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* This is how to output a reference to a user-level label named NAME.
+   `assemble_name' uses this.  */
+
+#undef ASM_OUTPUT_LABELREF
+#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
+  do {                                            \
+  char* real_name;                                \
+  STRIP_NAME_ENCODING (real_name, (NAME));        \
+  fprintf (FILE, "_%s", real_name);               \
+  } while (0)           
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
+
+/* This is how we tell the assembler that two symbols have the same value.  */
+
+#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
+  do { assemble_name(FILE, NAME1); 	 \
+       fputs(" = ", FILE);		 \
+       assemble_name(FILE, NAME2);	 \
+       fputc('\n', FILE); } while (0)
+
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
+
+/* Print an instruction operand X on file FILE.
+   look in mn10300.c for details */
+
+#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
+
+/* Print a memory operand whose address is X, on file FILE.
+   This uses a function in output-vax.c.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)
+
+/* This is how to output an element of a case-vector that is absolute.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
+  asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
+  fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", (LOG))
+
+/* We don't have to worry about dbx compatibility for the mn10300.  */
+#define DEFAULT_GDB_EXTENSIONS 1
+
+/* Use stabs debugging info by default.  */
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+#define DBX_REGISTER_NUMBER(REGNO) REGNO
+
+/* GDB always assumes the current function's frame begins at the value
+   of the stack pointer upon entry to the current function.  Accessing
+   local variables and parameters passed on the stack is done using the
+   base of the frame + an offset provided by GCC.
+
+   For functions which have frame pointers this method works fine;
+   the (frame pointer) == (stack pointer at function entry) and GCC provides
+   an offset relative to the frame pointer.
+
+   This loses for functions without a frame pointer; GCC provides an offset
+   which is relative to the stack pointer after adjusting for the function's
+   frame size.  GDB would prefer the offset to be relative to the value of
+   the stack pointer at the function's entry.  Yuk!  */
+#define DEBUGGER_AUTO_OFFSET(X) \
+  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
+    + (frame_pointer_needed \
+       ? 0 : -initial_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM)))
+
+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
+  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
+    + (frame_pointer_needed \
+       ? 0 : -initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)))
+
+/* We need to prepend underscores.  */
+#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE,ADDR) \
+  fprintf ((FILE), "\t%s\t_%s", UNALIGNED_WORD_ASM_OP, (ADDR))
+
+/* Define to use software floating point emulator for REAL_ARITHMETIC and
+   decimal <-> binary conversion. */
+#define REAL_ARITHMETIC
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE Pmode
+
+/* Define if operations between registers always perform the operation
+   on the full register even if a narrower mode is specified.  */
+#define WORD_REGISTER_OPERATIONS
+
+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This flag, if defined, says the same insns that convert to a signed fixnum
+   also convert validly to an unsigned one.  */
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX	4
+
+/* Define if shifts truncate the shift count
+   which implies one can omit a sign-extension or zero-extension
+   of a shift count.  */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* A function address in a call instruction
+   is a byte address (for indexing purposes)
+   so give the MEM rtx a byte's mode.  */
+#define FUNCTION_MODE QImode
+
+/* The assembler op to get a word.  */
+
+#define FILE_ASM_OP "\t.file\n"
+
+extern void asm_file_start ();
+extern int const_costs ();
+extern void print_operand ();
+extern void print_operand_address ();
+extern void expand_prologue ();
+extern void expand_epilogue ();
+extern void notice_update_cc ();
+extern int call_address_operand ();
+extern int impossible_plus_operand ();
+extern enum reg_class secondary_reload_class ();
+extern int initial_offset ();
+extern char *output_tst ();
+int symbolic_operand ();
diff --git a/gnu/egcs/gcc/config/mn10300/mn10300.md b/gnu/egcs/gcc/config/mn10300/mn10300.md
new file mode 100644
index 00000000000..8c3e2ac3cc0
--- /dev/null
+++ b/gnu/egcs/gcc/config/mn10300/mn10300.md
@@ -0,0 +1,1648 @@
+;; GCC machine description for Matsushita MN10300
+;; Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+;;   Contributed by Jeff Law (law@cygnus.com).
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; The original PO technology requires these to be ordered by speed,
+;; so that assigner will pick the fastest.
+
+;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; Condition code settings.
+;; none - insn does not affect cc
+;; none_0hit - insn does not affect cc but it does modify operand 0
+;;	This attribute is used to keep track of when operand 0 changes.
+;; 	See the description of NOTICE_UPDATE_CC for more info.
+;; set_znv - insn sets z,n,v to usable values; c is unusable.
+;; set_zn  - insn sets z,n to usable values; v,c are unusable.
+;; compare - compare instruction
+;; invert -- like compare, but flags are inverted.
+;; clobber - value of cc is unknown
+(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
+  (const_string "clobber"))
+
+;; ----------------------------------------------------------------------
+;; MOVE INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+;; movqi
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand0, QImode)
+      && !register_operand (operand1, QImode))
+    operands[1] = copy_to_mode_reg (QImode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
+	(match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
+  "register_operand (operands[0], QImode)
+   || register_operand (operands[1], QImode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return \"nop\";
+    case 2:
+      return \"clr %0\";
+    case 3:
+    case 4:
+    case 5:
+    case 6:
+    case 7:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	{
+	  rtx xoperands[2];
+	  xoperands[0] = operands[0];
+	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+	  output_asm_insn (\"mov %1,%0\", xoperands);
+	  return \"\";
+	}
+
+      return \"mov %1,%0\";
+    case 8:
+    case 9:
+      return \"movbu %1,%0\";
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
+;; movhi
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand1, HImode)
+      && !register_operand (operand0, HImode))
+    operands[1] = copy_to_mode_reg (HImode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
+	(match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
+  "register_operand (operands[0], HImode)
+   || register_operand (operands[1], HImode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return \"nop\";
+    case 2:
+      return \"clr %0\";
+    case 3:
+    case 4:
+    case 5:
+    case 6:
+    case 7:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	{
+	  rtx xoperands[2];
+	  xoperands[0] = operands[0];
+	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+	  output_asm_insn (\"mov %1,%0\", xoperands);
+	  return \"\";
+	}
+      return \"mov %1,%0\";
+    case 8:
+    case 9:
+      return \"movhu %1,%0\";
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
+;; movsi and helpers
+
+;; We use this to handle addition of two values when one operand is the
+;; stack pointer and the other is a memory reference of some kind.  Reload
+;; does not handle them correctly without this expander.
+(define_expand "reload_insi"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(match_operand:SI 1 "impossible_plus_operand" ""))
+   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+  ""
+  "
+{
+  if (XEXP (operands[1], 0) == stack_pointer_rtx)
+    {
+      if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
+	  && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
+	      > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
+	emit_move_insn (operands[2],
+			gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 1)),
+				 SUBREG_REG (XEXP (operands[1], 1))));
+      else
+	emit_move_insn (operands[2], XEXP (operands[1], 1));
+      emit_move_insn (operands[0], XEXP (operands[1], 0));
+    }
+  else
+    {
+      if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
+	  && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
+	      > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
+	emit_move_insn (operands[2],
+			gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 0)),
+				 SUBREG_REG (XEXP (operands[1], 0))));
+      else
+	emit_move_insn (operands[2], XEXP (operands[1], 0));
+      emit_move_insn (operands[0], XEXP (operands[1], 1));
+    }
+  emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
+  DONE;
+}")
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand1, SImode)
+      && !register_operand (operand0, SImode))
+    operands[1] = copy_to_mode_reg (SImode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand"
+				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,y")
+	(match_operand:SI 1 "general_operand"
+				"0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,xy,axR"))]
+  "register_operand (operands[0], SImode)
+   || register_operand (operands[1], SImode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return \"nop\";
+    case 2:
+      return \"clr %0\";
+    case 3:
+    case 4:
+    case 5:
+    case 6:
+    case 7:
+    case 8:
+    case 9:
+    case 10:
+    case 11:
+    case 12:
+    case 13:
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	{
+	  rtx xoperands[2];
+	  xoperands[0] = operands[0];
+	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+	  output_asm_insn (\"mov %1,%0\", xoperands);
+	  return \"\";
+	}
+      return \"mov %1,%0\";
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand1, SFmode)
+      && !register_operand (operand0, SFmode))
+    operands[1] = copy_to_mode_reg (SFmode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "general_operand" "=dx,ax,dx,a,daxm,dax")
+	(match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxim"))]
+  "register_operand (operands[0], SFmode)
+   || register_operand (operands[1], SFmode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return \"nop\";
+    case 2:
+      return \"clr %0\";
+    case 3:
+    case 4:
+    case 5:
+      return \"mov %1,%0\";
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand1, DImode)
+      && !register_operand (operand0, DImode))
+    operands[1] = copy_to_mode_reg (DImode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "general_operand"
+				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
+	(match_operand:DI 1 "general_operand"
+				"0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
+  "register_operand (operands[0], DImode)
+   || register_operand (operands[1], DImode)"
+  "*
+{
+  long val[2];
+  REAL_VALUE_TYPE rv;
+
+  switch (which_alternative)
+    {
+      case 0:
+      case 1:
+	return \"nop\";
+
+      case 2:
+	return \"clr %L0\;clr %H0\";
+
+      case 3:
+	if (rtx_equal_p (operands[0], operands[1]))
+	  return \"sub %L1,%L0\;mov %L0,%H0\";
+	else
+	  return \"mov %1,%L0\;mov %L0,%H0\";
+      case 4:
+      case 5:
+      case 6:
+      case 7:
+      case 8:
+      case 9:
+      case 10:
+      case 11:
+	if (GET_CODE (operands[1]) == CONST_INT)
+	  {
+	    val[0] = INTVAL (operands[1]);
+	    val[1] = val[0] < 0 ? -1 : 0;
+	  }
+	if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	  {
+	    if (GET_MODE (operands[1]) == DFmode)
+	      {
+		REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
+		REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+	      }
+	    else if (GET_MODE (operands[1]) == VOIDmode
+		     || GET_MODE (operands[1]) == DImode)
+	      {
+		val[0] = CONST_DOUBLE_LOW (operands[1]);
+		val[1] = CONST_DOUBLE_HIGH (operands[1]);
+	      }
+	  }
+
+	if (GET_CODE (operands[1]) == MEM
+	    && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
+	  {
+	    rtx temp = operands[0];
+
+	    while (GET_CODE (temp) == SUBREG)
+	      temp = SUBREG_REG (temp);
+
+	    if (GET_CODE (temp) != REG)
+	      abort ();
+
+	    if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
+					 XEXP (operands[1], 0)))
+	      return \"mov %H1,%H0\;mov %L1,%L0\";
+	    else
+	      return \"mov %L1,%L0\;mov %H1,%H0\";
+	      
+	  }
+	else if (GET_CODE (operands[1]) == MEM
+		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
+		 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
+	  {
+	    rtx xoperands[2];
+
+	    xoperands[0] = operands[0];
+	    xoperands[1] = XEXP (operands[1], 0);
+
+	    output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
+			     xoperands);
+	    return \"\";
+	  }
+	else
+	  {
+	    if ((GET_CODE (operands[1]) == CONST_INT
+		 || GET_CODE (operands[1]) == CONST_DOUBLE)
+		&& val[0] == 0)
+	      {
+		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
+		  output_asm_insn (\"clr %L0\", operands);
+		else
+		  output_asm_insn (\"mov %L1,%L0\", operands);
+	      }
+	    else
+	      output_asm_insn (\"mov %L1,%L0\", operands);
+
+	    if ((GET_CODE (operands[1]) == CONST_INT
+		 || GET_CODE (operands[1]) == CONST_DOUBLE)
+		&& val[1] == 0)
+	      {
+		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
+		  output_asm_insn (\"clr %H0\", operands);
+		else
+		  output_asm_insn (\"mov %H1,%H0\", operands);
+	      }
+	    else if ((GET_CODE (operands[1]) == CONST_INT
+		      || GET_CODE (operands[1]) == CONST_DOUBLE)
+		     && val[0] == val[1])
+	      output_asm_insn (\"mov %L0,%H0\", operands);
+	    else
+	      output_asm_insn (\"mov %H1,%H0\", operands);
+	    return \"\";
+	  }
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+	(match_operand:DF 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* One of the ops has to be in a register */
+  if (!register_operand (operand1, DFmode)
+      && !register_operand (operand0, DFmode))
+    operands[1] = copy_to_mode_reg (DFmode, operand1);
+}")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand"
+				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
+	(match_operand:DF 1 "general_operand"
+				"0,0,G,G,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
+  "register_operand (operands[0], DFmode)
+   || register_operand (operands[1], DFmode)"
+  "*
+{
+  long val[2];
+  REAL_VALUE_TYPE rv;
+
+  switch (which_alternative)
+    {
+      case 0:
+      case 1:
+	return \"nop\";
+
+      case 2:
+	return \"clr %L0\;clr %H0\";
+
+      case 3:
+	 if (rtx_equal_p (operands[0], operands[1]))
+	   return \"sub %L1,%L0\;mov %L0,%H0\";
+	 else
+	   return \"mov %1,%L0\;mov %L0,%H0\";
+      case 4:
+      case 5:
+      case 6:
+      case 7:
+      case 8:
+      case 9:
+      case 10:
+      case 11:
+	if (GET_CODE (operands[1]) == CONST_INT)
+	  {
+	    val[0] = INTVAL (operands[1]);
+	    val[1] = val[0] < 0 ? -1 : 0;
+	  }
+	if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	  {
+	    if (GET_MODE (operands[1]) == DFmode)
+	      {
+		REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
+		REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
+	      }
+	    else if (GET_MODE (operands[1]) == VOIDmode
+		     || GET_MODE (operands[1]) == DImode)
+	      {
+		val[0] = CONST_DOUBLE_LOW (operands[1]);
+		val[1] = CONST_DOUBLE_HIGH (operands[1]);
+	      }
+	  }
+
+	if (GET_CODE (operands[1]) == MEM
+	    && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
+	  {
+	    rtx temp = operands[0];
+
+	    while (GET_CODE (temp) == SUBREG)
+	      temp = SUBREG_REG (temp);
+
+	    if (GET_CODE (temp) != REG)
+	      abort ();
+
+	    if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
+					 XEXP (operands[1], 0)))
+	      return \"mov %H1,%H0\;mov %L1,%L0\";
+	    else
+	      return \"mov %L1,%L0\;mov %H1,%H0\";
+	      
+	  }
+	else if (GET_CODE (operands[1]) == MEM
+		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
+		 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
+	  {
+	    rtx xoperands[2];
+
+	    xoperands[0] = operands[0];
+	    xoperands[1] = XEXP (operands[1], 0);
+
+	    output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
+			     xoperands);
+	    return \"\";
+	  }
+	else
+	  {
+	    if ((GET_CODE (operands[1]) == CONST_INT
+		 || GET_CODE (operands[1]) == CONST_DOUBLE)
+		&& val[0] == 0)
+	      {
+		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
+		  output_asm_insn (\"clr %L0\", operands);
+		else
+		  output_asm_insn (\"mov %L1,%L0\", operands);
+	      }
+	    else
+	      output_asm_insn (\"mov %L1,%L0\", operands);
+
+	    if ((GET_CODE (operands[1]) == CONST_INT
+		 || GET_CODE (operands[1]) == CONST_DOUBLE)
+		&& val[1] == 0)
+	      {
+		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
+		  output_asm_insn (\"clr %H0\", operands);
+		else
+		  output_asm_insn (\"mov %H1,%H0\", operands);
+	      }
+	    else if ((GET_CODE (operands[1]) == CONST_INT
+		      || GET_CODE (operands[1]) == CONST_DOUBLE)
+		     && val[0] == val[1])
+	      output_asm_insn (\"mov %L0,%H0\", operands);
+	    else
+	      output_asm_insn (\"mov %H1,%H0\", operands);
+	    return \"\";
+	  }
+    }
+}"
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+  
+
+
+;; ----------------------------------------------------------------------
+;; TEST INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+;; Go ahead and define tstsi so we can eliminate redundant tst insns
+;; when we start trying to optimize this port.
+(define_insn "tstsi"
+  [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
+  ""
+  "* return output_tst (operands[0], insn);"
+  [(set_attr "cc" "set_znv")])
+
+(define_insn ""
+  [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
+  ""
+  "* return output_tst (operands[0], insn);"
+  [(set_attr "cc" "set_znv")])
+
+(define_insn ""
+  [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
+  ""
+  "* return output_tst (operands[0], insn);"
+  [(set_attr "cc" "set_znv")])
+
+
+(define_insn "cmpsi"
+  [(set (cc0)
+	(compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
+		 (match_operand:SI 1 "nonmemory_operand" "!*0,daxi")))]
+  ""
+  "@
+  add 0,%0
+  cmp %1,%0"
+  [(set_attr "cc" "invert,compare")])
+
+;; ----------------------------------------------------------------------
+;; ADD INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (match_operand:SI 1 "register_operand" "")
+		 (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  /* We can't add a variable amount directly to the stack pointer;
+     so do so via a temporary register.  */
+  if (operands[0] == stack_pointer_rtx
+      && GET_CODE (operands[1]) != CONST_INT
+      && GET_CODE (operands[2]) != CONST_INT)
+   {
+     rtx temp = gen_reg_rtx (SImode);
+     emit_move_insn (temp, gen_rtx (PLUS, SImode, operands[1], operands[2]));
+     emit_move_insn (operands[0], temp);
+     DONE;
+   }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
+		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
+  ""
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return \"inc %0\";
+    case 2:
+      return \"inc4 %0\";
+    case 3:
+    case 4:
+      return \"add %2,%0\";
+    case 5:
+      /* I'm not sure if this can happen or not.  Might as well be prepared
+	 and generate the best possible code if it does happen.  */
+      if (true_regnum (operands[0]) == true_regnum (operands[1]))
+	return \"add %2,%0\";
+      if (true_regnum (operands[0]) == true_regnum (operands[2]))
+	return \"add %1,%0\";
+
+      /* We have to copy one of the sources into the destination, then add
+	 the other source to the destination.
+
+	 Carefully select which source to copy to the destination; a naive
+	 implementation will waste a byte when the source classes are different
+	 and the destination is an address register.  Selecting the lowest
+	 cost register copy will optimize this sequence.  */
+      if (REGNO_REG_CLASS (true_regnum (operands[1]))
+	  == REGNO_REG_CLASS (true_regnum (operands[0])))
+	return \"mov %1,%0\;add %2,%0\";
+      return \"mov %2,%0\;add %1,%0\";
+    }
+}"
+  [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
+
+;; ----------------------------------------------------------------------
+;; SUBTRACT INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dax")
+	(minus:SI (match_operand:SI 1 "register_operand" "0")
+		  (match_operand:SI 2 "nonmemory_operand" "daxi")))]
+  ""
+  "sub %2,%0"
+  [(set_attr "cc" "set_zn")])
+
+(define_expand "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+        (neg:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx target = gen_reg_rtx (SImode);
+
+  emit_move_insn (target, GEN_INT (0));
+  emit_insn (gen_subsi3 (target, target, operands[1]));
+  emit_move_insn (operands[0], target);
+  DONE;
+}")
+
+;; ----------------------------------------------------------------------
+;; MULTIPLY INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "mulsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(mult:SI (match_operand:SI 1 "register_operand" "")
+		 (match_operand:SI 2 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(mult:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "register_operand" "dx")))]
+  ""
+  "*
+{
+  if (TARGET_MULT_BUG)
+    return \"nop\;nop\;mul %2,%0\";
+  else
+    return \"mul %2,%0\";
+}"
+  [(set_attr "cc" "set_zn")])
+
+(define_insn "udivmodsi4"
+  [(set (match_operand:SI 0 "general_operand" "=dx")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "dx")))
+   (set (match_operand:SI 3 "general_operand" "=&d")
+	(umod:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "*
+{
+  output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
+
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divu %2,%0\";
+  else
+    return \"divu %2,%0\;mov mdr,%3\";
+}"
+  [(set_attr "cc" "set_zn")])
+
+(define_insn "divmodsi4"
+  [(set (match_operand:SI 0 "general_operand" "=dx")
+	(div:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "dx")))
+   (set (match_operand:SI 3 "general_operand" "=d")
+	(mod:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"ext %0\;div %2,%0\";
+  else
+    return \"ext %0\;div %2,%0\;mov mdr,%3\";
+}"
+  [(set_attr "cc" "set_zn")])
+
+
+;; ----------------------------------------------------------------------
+;; AND INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx,dx")
+	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
+		(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
+    return \"extbu %0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
+    return \"exthu %0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
+    return \"add %0,%0\;lsr 1,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
+    return \"asl2 %0\;lsr 2,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
+    return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
+    return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
+    return \"lsr 1,%0\;add %0,%0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
+    return \"lsr 2,%0\;asl2 %0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
+    return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
+    return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
+  return \"and %2,%0\";
+}"
+  [(set_attr "cc" "none_0hit,set_znv")])
+
+;; ----------------------------------------------------------------------
+;; OR INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ior:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(ior:SI (match_operand:SI 1 "register_operand" "%0")
+		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
+  ""
+  "or %2,%0"
+  [(set_attr "cc" "set_znv")])
+
+;; ----------------------------------------------------------------------
+;; XOR INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(xor:SI (match_operand:SI 1 "register_operand" "%0")
+		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
+  ""
+  "xor %2,%0"
+  [(set_attr "cc" "set_znv")])
+
+;; ----------------------------------------------------------------------
+;; NOT INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(not:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "")
+ 
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(not:SI (match_operand:SI 1 "register_operand" "0")))]
+  ""
+  "not %0"
+  [(set_attr "cc" "set_znv")])
+
+;; -----------------------------------------------------------------
+;; BIT FIELDS
+;; -----------------------------------------------------------------
+
+
+;; These set/clear memory in byte sized chunks.
+;;
+;; They are no smaller/faster than loading the value into a register
+;; and storing the register, but they don't need a scratch register
+;; which may allow for better code generation.
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int 0))]
+  ""
+  "@
+  bclr 255,%A0
+  clr %0"
+  [(set_attr "cc" "clobber")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int -1))]
+  ""
+  "@
+  bset 255,%A0
+  mov -1,%0"
+  [(set_attr "cc" "clobber,none_0hit")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "+R,d")
+	(subreg:QI
+	  (and:SI (subreg:SI (match_dup 0) 0)
+		  (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
+  ""
+  "@
+  bclr %N1,%A0
+  and %1,%0"
+  [(set_attr "cc" "clobber,set_znv")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "+R,d")
+	(subreg:QI
+	  (ior:SI (subreg:SI (match_dup 0) 0)
+		  (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
+  ""
+  "@
+  bset %1,%A0
+  or %1,%0"
+  [(set_attr "cc" "clobber,set_znv")])
+
+(define_insn ""
+  [(set (cc0)
+     (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
+		      (match_operand 1 "const_int_operand" "")
+		      (match_operand 2 "const_int_operand" "")))]
+  ""
+  "*
+{
+  int len = INTVAL (operands[1]);
+  int bit = INTVAL (operands[2]);
+  int mask = 0;
+  rtx xoperands[2];
+
+  while (len > 0)
+    {
+      mask |= (1 << bit);
+      bit++;
+      len--;
+    }
+
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (mask);
+  output_asm_insn (\"btst %1,%0\", xoperands);
+  return \"\";
+}"
+  [(set_attr "cc" "clobber")])
+
+(define_insn ""
+  [(set (cc0)
+     (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
+		      (match_operand 1 "const_int_operand" "")
+		      (match_operand 2 "const_int_operand" "")))]
+  "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
+  "*
+{
+  int len = INTVAL (operands[1]);
+  int bit = INTVAL (operands[2]);
+  int mask = 0;
+  rtx xoperands[2];
+
+  while (len > 0)
+    {
+      mask |= (1 << bit);
+      bit++;
+      len--;
+    }
+
+  /* If the source operand is not a reg (ie it is memory), then extract the
+     bits from mask that we actually want to test.  Note that the mask will
+     never cross a byte boundary.  */
+  if (!REG_P (operands[0]))
+    {
+      if (mask & 0xff)
+	mask = mask & 0xff;
+      else if (mask & 0xff00)
+	mask = (mask >> 8) & 0xff;
+      else if (mask & 0xff0000)
+	mask = (mask >> 16) & 0xff;
+      else if (mask & 0xff000000)
+	mask = (mask >> 24) & 0xff;
+    }
+  
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (mask);
+  if (GET_CODE (operands[0]) == REG)
+    output_asm_insn (\"btst %1,%0\", xoperands);
+  else
+    output_asm_insn (\"btst %1,%A0\", xoperands);
+  return \"\";
+}"
+  [(set_attr "cc" "clobber")])
+
+(define_insn ""
+  [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
+		      (match_operand:SI 1 "const_int_operand" "")))]
+  ""
+  "btst %1,%0"
+  [(set_attr "cc" "clobber")])
+
+(define_insn ""
+  [(set (cc0)
+     (and:SI
+       (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
+       (match_operand:SI 1 "const_8bit_operand" "")))]
+  ""
+  "@
+  btst %1,%A0
+  btst %1,%0"
+  [(set_attr "cc" "clobber")])
+
+
+;; ----------------------------------------------------------------------
+;; JUMP INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+;; Conditional jump instructions
+
+(define_expand "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 1 "comparison_operator"
+				      [(cc0) (const_int 0)])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
+      && (GET_CODE (operands[1]) == GT
+	  || GET_CODE (operands[1]) == GE
+	  || GET_CODE (operands[1]) == LE
+	  || GET_CODE (operands[1]) == LT))
+    return 0;
+  return \"b%b1 %0\";
+}"
+ [(set_attr "cc" "none")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 1 "comparison_operator"
+				      [(cc0) (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
+      && (GET_CODE (operands[1]) == GT
+	  || GET_CODE (operands[1]) == GE
+	  || GET_CODE (operands[1]) == LE
+	  || GET_CODE (operands[1]) == LT))
+    return 0;
+  return \"b%B1 %0\";
+}"
+ [(set_attr "cc" "none")])
+
+;; Unconditional and other jump instructions.
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "jmp %l0"
+ [(set_attr "cc" "none")])
+
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
+  ""
+  "jmp (%0)"
+  [(set_attr "cc" "none")])
+
+(define_insn "tablejump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "a"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmp  (%0)"
+  [(set_attr "cc" "none")])
+
+;; Call subroutine with no return value.
+
+(define_expand "call"
+  [(call (match_operand:QI 0 "general_operand" "")
+	 (match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (! call_address_operand (XEXP (operands[0], 0)))
+    XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
+  emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
+  DONE;
+}")
+
+(define_insn "call_internal"
+  [(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
+	 (match_operand:SI 1 "general_operand" "g"))]
+  ""
+  "*
+{
+  if (REG_P (operands[0]))
+    return \"calls %C0\";
+  else
+    return \"call %C0,[],0\";
+}"
+  [(set_attr "cc" "clobber")])
+
+;; Call subroutine, returning value in operand 0
+;; (which must be a hard register).
+
+(define_expand "call_value"
+  [(set (match_operand 0 "" "")
+	(call (match_operand:QI 1 "general_operand" "")
+	      (match_operand:SI 2 "general_operand" "")))]
+  ""
+  "
+{
+  if (! call_address_operand (XEXP (operands[1], 0)))
+    XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
+  emit_call_insn (gen_call_value_internal (operands[0],
+					   XEXP (operands[1], 0),
+					   operands[2]));
+  DONE;
+}")
+
+(define_insn "call_value_internal"
+  [(set (match_operand 0 "" "=dax")
+	(call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
+	      (match_operand:SI 2 "general_operand" "g")))]
+  ""
+  "*
+{
+  if (REG_P (operands[1]))
+    return \"calls %C1\";
+  else
+    return \"call %C1,[],0\";
+}"
+  [(set_attr "cc" "clobber")])
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+                    (const_int 0))
+              (match_operand 1 "" "")
+              (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call (operands[0], const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
+  DONE;
+}")
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop"
+  [(set_attr "cc" "none")])
+
+;; ----------------------------------------------------------------------
+;; EXTEND INSTRUCTIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extend:SI
+	 (match_operand:QI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
+	(zero_extend:SI
+	 (match_operand:QI 1 "general_operand" "0,d,m")))]
+  ""
+  "@
+  extbu %0
+  mov %1,%0\;extbu %0
+  movbu %1,%0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extend:SI
+	 (match_operand:HI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
+	(zero_extend:SI
+	 (match_operand:HI 1 "general_operand" "0,dx,m")))]
+  ""
+  "@
+  exthu %0
+  mov %1,%0\;exthu %0
+  movhu %1,%0"
+  [(set_attr "cc" "none_0hit")])
+
+;;- sign extension instructions
+
+(define_expand "extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extend:SI
+	 (match_operand:QI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=dx,dx")
+	(sign_extend:SI
+	 (match_operand:QI 1 "general_operand" "0,dx")))]
+  ""
+  "@
+  extb %0
+  mov %1,%0\;extb %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_expand "extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extend:SI
+	 (match_operand:HI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=dx,dx")
+	(sign_extend:SI
+	 (match_operand:HI 1 "general_operand" "0,dx")))]
+  ""
+  "@
+  exth %0
+  mov %1,%0\;exth %0"
+  [(set_attr "cc" "none_0hit")])
+
+;; ----------------------------------------------------------------------
+;; SHIFTS
+;; ----------------------------------------------------------------------
+
+(define_expand "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashift:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
+	(ashift:SI
+	 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
+	 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
+  ""
+  "@
+  add %0,%0
+  asl2 %0
+  asl2 %0\;add %0,%0
+  asl2 %0\;asl2 %0
+  asl %S2,%0"
+  [(set_attr "cc" "set_zn")])
+
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(lshiftrt:SI
+	 (match_operand:SI 1 "register_operand" "0")
+	 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
+  ""
+  "lsr %S2,%0"
+  [(set_attr "cc" "set_zn")])
+
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=dx")
+	(ashiftrt:SI
+	 (match_operand:SI 1 "register_operand" "0")
+	 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
+  ""
+  "asr %S2,%0"
+  [(set_attr "cc" "set_zn")])
+
+;; ----------------------------------------------------------------------
+;; FP INSTRUCTIONS
+;; ----------------------------------------------------------------------
+;;
+;; The mn103 series does not have floating point instructions, but since
+;; FP values are held in integer regs, we can clear the high bit easily
+;; which gives us an efficient inline floating point absolute value.
+;;
+;; Similarly for negation of a FP value.
+;;
+
+(define_expand "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+        (abs:DF (match_operand:DF 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx target, result, insns;
+
+  start_sequence ();
+  target = operand_subword (operands[0], 1, 1, DFmode);
+  result = expand_binop (SImode, and_optab,
+			 operand_subword_force (operands[1], 1, DFmode),
+			 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
+
+  if (result == 0)
+    abort ();
+
+  if (result != target)
+    emit_move_insn (result, target);
+
+  emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
+		  operand_subword_force (operands[1], 0, DFmode));
+
+  insns = get_insns ();
+  end_sequence ();
+
+  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+  DONE;
+}")
+
+(define_expand "abssf2"
+  [(set (match_operand:SF 0 "register_operand" "")
+        (abs:SF (match_operand:SF 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx result;
+  rtx target;
+
+  target = operand_subword_force (operands[0], 0, SFmode);
+  result = expand_binop (SImode, and_optab,
+			 operand_subword_force (operands[1], 0, SFmode),
+			 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
+  if (result == 0)
+    abort ();
+
+  if (result != target)
+    emit_move_insn (result, target);
+
+  /* Make a place for REG_EQUAL.  */
+  emit_move_insn (operands[0], operands[0]);
+  DONE;
+}")
+
+
+(define_expand "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+        (neg:DF (match_operand:DF 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx target, result, insns;
+
+  start_sequence ();
+  target = operand_subword (operands[0], 1, 1, DFmode);
+  result = expand_binop (SImode, xor_optab,
+			 operand_subword_force (operands[1], 1, DFmode),
+			 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
+
+  if (result == 0)
+    abort ();
+
+  if (result != target)
+    emit_move_insn (result, target);
+
+  emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
+		  operand_subword_force (operands[1], 0, DFmode));
+
+  insns = get_insns ();
+  end_sequence ();
+
+  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+  DONE;
+}")
+
+(define_expand "negsf2"
+  [(set (match_operand:SF 0 "register_operand" "")
+        (neg:SF (match_operand:SF 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx result;
+  rtx target;
+
+  target = operand_subword_force (operands[0], 0, SFmode);
+  result = expand_binop (SImode, xor_optab,
+			 operand_subword_force (operands[1], 0, SFmode),
+			 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
+  if (result == 0)
+    abort ();
+
+  if (result != target)
+    emit_move_insn (result, target);
+
+  /* Make a place for REG_EQUAL.  */
+  emit_move_insn (operands[0], operands[0]);
+  DONE;
+}")
+
+
+;; ----------------------------------------------------------------------
+;; PROLOGUE/EPILOGUE
+;; ----------------------------------------------------------------------
+(define_expand "prologue"
+  [(const_int 0)]
+  ""
+  "expand_prologue (); DONE;")
+
+(define_expand "epilogue"
+  [(return)]
+  ""
+  "
+{
+  expand_epilogue ();
+  DONE;
+}")
+
+(define_insn "return_internal"
+  [(const_int 2)]
+  ""
+  "rets"
+  [(set_attr "cc" "clobber")])
+
+;; This insn restores the callee saved registers and does a return, it
+;; can also deallocate stack space.
+(define_insn "return_internal_regs"
+  [(const_int 0)
+   (match_operand:SI 0  "const_int_operand" "i")
+   (return)]
+  ""
+  "*
+{
+  int i, need_comma;
+  int d2, d3, a2, a3;
+
+  need_comma = 0;
+  fputs (\"\\tret [\", asm_out_file);
+  if (regs_ever_live[2])
+    {
+      fputs (\"d2\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[3])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"d3\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[6])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"a2\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[7])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"a3\", asm_out_file);
+      need_comma = 1;
+    }
+  fprintf (asm_out_file, \"],%d\\n\", INTVAL (operands[0]));
+  return \"\";
+}"
+  [(set_attr "cc" "clobber")])
+
+(define_insn "store_movm"
+  [(const_int 1)]
+  ""
+  "*
+{
+  int i, need_comma;
+  int d2, d3, a2, a3;
+
+  need_comma = 0;
+  fputs (\"\\tmovm [\", asm_out_file);
+  if (regs_ever_live[2])
+    {
+      fputs (\"d2\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[3])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"d3\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[6])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"a2\", asm_out_file);
+      need_comma = 1;
+    }
+  if (regs_ever_live[7])
+    {
+      if (need_comma)
+	fputc (',', asm_out_file); 
+      fputs (\"a3\", asm_out_file);
+      need_comma = 1;
+    }
+  fputs (\"],(sp)\\n\", asm_out_file);
+  return \"\";
+}"
+  [(set_attr "cc" "clobber")])
+
+(define_insn "return"
+  [(return)]
+  "can_use_return_insn ()"
+  "*
+{
+  rtx next = next_active_insn (insn);
+
+  if (next
+      && GET_CODE (next) == JUMP_INSN
+      && GET_CODE (PATTERN (next)) == RETURN)
+    return \"\";
+  else
+    return \"rets\";
+}"
+  [(set_attr "cc" "clobber")])
+
+;; Try to combine consecutive updates of the stack pointer (or any
+;; other register for that matter).
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=dxay")
+	(plus:SI (match_dup 0)
+		 (match_operand 1 "const_int_operand" "")))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (match_operand 2 "const_int_operand" "")))]
+  ""
+  "*
+{
+  operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
+  return \"add %1,%0\";
+}"
+  [(set_attr "cc" "clobber")])
+
+;;
+;; We had patterns to check eq/ne, but the they don't work because
+;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
+;;
+;; The Z flag and C flag would be set, and we have no way to
+;; check for the Z flag set and C flag clear.
+;;
+;; This will work on the mn10200 because we can check the ZX flag
+;; if the comparison is in HImode.
+(define_peephole
+  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+   (set (pc) (if_then_else (ge (cc0) (const_int 0))
+			   (match_operand 1 "" "")
+			   (pc)))]
+  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
+  "add %0,%0\;bcc %1"
+  [(set_attr "cc" "clobber")])
+
+(define_peephole
+  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+   (set (pc) (if_then_else (lt (cc0) (const_int 0))
+			   (match_operand 1 "" "")
+			   (pc)))]
+  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
+  "add %0,%0\;bcs %1"
+  [(set_attr "cc" "clobber")])
+
+(define_peephole
+  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+   (set (pc) (if_then_else (ge (cc0) (const_int 0))
+			   (pc)
+			   (match_operand 1 "" "")))]
+  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
+  "add %0,%0\;bcs %1"
+  [(set_attr "cc" "clobber")])
+
+(define_peephole
+  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+   (set (pc) (if_then_else (lt (cc0) (const_int 0))
+			   (pc)
+			   (match_operand 1 "" "")))]
+  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
+  "add %0,%0\;bcc %1"
+  [(set_attr "cc" "clobber")])
+
diff --git a/gnu/egcs/gcc/config/mn10300/t-mn10300 b/gnu/egcs/gcc/config/mn10300/t-mn10300
new file mode 100644
index 00000000000..7e94656c223
--- /dev/null
+++ b/gnu/egcs/gcc/config/mn10300/t-mn10300
@@ -0,0 +1,23 @@
+LIBGCC1=libgcc1.null
+CROSS_LIBGCC1=libgcc1.null
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so...
+
+# We want fine grained libraries, so use the new code to build the
+# floating point emulation libraries.
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
+	echo '#endif' 		>> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
+	echo '#endif' 		>> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
diff --git a/gnu/egcs/gcc/config/mn10300/xm-mn10300.h b/gnu/egcs/gcc/config/mn10300/xm-mn10300.h
new file mode 100644
index 00000000000..63d61c276c2
--- /dev/null
+++ b/gnu/egcs/gcc/config/mn10300/xm-mn10300.h
@@ -0,0 +1,47 @@
+/* Configuration for Matsushita MN10300. 
+   Copyright (C) 1996 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+
+#include "tm.h"
+
+#ifndef __STDC__
+extern char *malloc (), *realloc (), *calloc ();
+#else
+extern void *malloc (), *realloc (), *calloc ();
+#endif
+extern void free ();