egcs projects compiler system

Exact copy of the snapshot, except for the removal of
	texinfo/
	gcc/ch/
	libchill/

4 files changed, 2508 insertions, 0 deletions

diff --git a/gnu/egcs/gcc/config/spur/spur.c b/gnu/egcs/gcc/config/spur/spur.c
new file mode 100644
index 00000000000..83e37b8aeef
--- /dev/null
+++ b/gnu/egcs/gcc/config/spur/spur.c
@@ -0,0 +1,326 @@
+/* Subroutines for insn-output.c for SPUR.  Adapted from routines for
+   the Motorola 68000 family.
+   Copyright (C) 1988, 1991, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "config.h"
+#include <stdio.h>
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+
+static rtx find_addr_reg ();
+
+char *
+output_compare (operands, opcode, exchange_opcode, 
+		neg_opcode, neg_exchange_opcode)
+     rtx *operands;
+     char *opcode;
+     char *exchange_opcode;
+     char *neg_opcode;
+     char *neg_exchange_opcode;
+{
+  static char buf[100];
+  operands[2] = operands[0];
+  if (GET_CODE (cc_prev_status.value1) == CONST_INT)
+    {
+      operands[1] = cc_prev_status.value1;
+      operands[0] = cc_prev_status.value2;
+      opcode = exchange_opcode, neg_opcode = neg_exchange_opcode;
+    }
+  else
+    {
+      operands[0] = cc_prev_status.value1;
+      operands[1] = cc_prev_status.value2;
+    }
+  if (TARGET_LONG_JUMPS)
+    sprintf (buf,
+	     "cmp_br_delayed %s,%%0,%%1,1f\n\tnop\n\tjump %%l2\n\tnop\n1:",
+	     neg_opcode);
+  else 
+    sprintf (buf, "cmp_br_delayed %s,%%0,%%1,%%l2\n\tnop", opcode);
+  return buf;
+}
+
+/* Return the best assembler insn template
+   for moving operands[1] into operands[0] as a fullword.  */
+
+static char *
+singlemove_string (operands)
+     rtx *operands;
+{
+  if (GET_CODE (operands[0]) == MEM)
+    return "st_32 %r1,%0";
+  if (GET_CODE (operands[1]) == MEM)
+    return "ld_32 %0,%1\n\tnop";
+  if (GET_CODE (operands[1]) == REG)
+    return "add_nt %0,%1,$0";
+  return "add_nt %0,r0,%1";
+}
+
+/* Output assembler code to perform a doubleword move insn
+   with operands OPERANDS.  */
+
+char *
+output_move_double (operands)
+     rtx *operands;
+{
+  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
+  rtx latehalf[2];
+  rtx addreg0 = 0, addreg1 = 0;
+
+  /* First classify both operands.  */
+
+  if (REG_P (operands[0]))
+    optype0 = REGOP;
+  else if (offsettable_memref_p (operands[0]))
+    optype0 = OFFSOP;
+  else if (GET_CODE (operands[0]) == MEM)
+    optype0 = MEMOP;
+  else
+    optype0 = RNDOP;
+
+  if (REG_P (operands[1]))
+    optype1 = REGOP;
+  else if (CONSTANT_P (operands[1]))
+    optype1 = CNSTOP;
+  else if (offsettable_memref_p (operands[1]))
+    optype1 = OFFSOP;
+  else if (GET_CODE (operands[1]) == MEM)
+    optype1 = MEMOP;
+  else
+    optype1 = RNDOP;
+
+  /* Check for the cases that the operand constraints are not
+     supposed to allow to happen.  Abort if we get one,
+     because generating code for these cases is painful.  */
+
+  if (optype0 == RNDOP || optype1 == RNDOP)
+    abort ();
+
+  /* If an operand is an unoffsettable memory ref, find a register
+     we can increment temporarily to make it refer to the second word.  */
+
+  if (optype0 == MEMOP)
+    addreg0 = find_addr_reg (XEXP (operands[0], 0));
+
+  if (optype1 == MEMOP)
+    addreg1 = find_addr_reg (XEXP (operands[1], 0));
+
+  /* Ok, we can do one word at a time.
+     Normally we do the low-numbered word first,
+     but if either operand is autodecrementing then we
+     do the high-numbered word first.
+
+     In either case, set up in LATEHALF the operands to use
+     for the high-numbered word and in some cases alter the
+     operands in OPERANDS to be suitable for the low-numbered word.  */
+
+  if (optype0 == REGOP)
+    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  else if (optype0 == OFFSOP)
+    latehalf[0] = adj_offsettable_operand (operands[0], 4);
+  else
+    latehalf[0] = operands[0];
+
+  if (optype1 == REGOP)
+    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  else if (optype1 == OFFSOP)
+    latehalf[1] = adj_offsettable_operand (operands[1], 4);
+  else if (optype1 == CNSTOP)
+    {
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	{
+	  latehalf[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+	  operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+	}
+      else if (CONSTANT_P (operands[1]))
+	latehalf[1] = const0_rtx;
+    }
+  else
+    latehalf[1] = operands[1];
+
+  /* If the first move would clobber the source of the second one,
+     do them in the other order.  This happens only for registers;
+     such overlap can't happen in memory unless the user explicitly
+     sets it up, and that is an undefined circumstance.  */
+
+  if (optype0 == REGOP && optype1 == REGOP
+      && REGNO (operands[0]) == REGNO (latehalf[1]))
+    {
+      /* Make any unoffsettable addresses point at high-numbered word.  */
+      if (addreg0)
+	output_asm_insn ("add_nt %0,%0,$4", &addreg0);
+      if (addreg1)
+	output_asm_insn ("add_nt %0,%0,$4", &addreg1);
+
+      /* Do that word.  */
+      output_asm_insn (singlemove_string (latehalf), latehalf);
+
+      /* Undo the adds we just did.  */
+      if (addreg0)
+	output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
+      if (addreg1)
+	output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
+
+      /* Do low-numbered word.  */
+      return singlemove_string (operands);
+    }
+
+  /* Normal case: do the two words, low-numbered first.  */
+
+  output_asm_insn (singlemove_string (operands), operands);
+
+  /* Make any unoffsettable addresses point at high-numbered word.  */
+  if (addreg0)
+    output_asm_insn ("add_nt %0,%0,$4", &addreg0);
+  if (addreg1)
+    output_asm_insn ("add_nt %0,%0,$4", &addreg1);
+
+  /* Do that word.  */
+  output_asm_insn (singlemove_string (latehalf), latehalf);
+
+  /* Undo the adds we just did.  */
+  if (addreg0)
+    output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
+  if (addreg1)
+    output_asm_insn ("add_nt %0,%0,$-4", &addreg1);
+
+  return "";
+}
+
+static char *
+output_fp_move_double (operands)
+     rtx *operands;
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return "fmov %0,%1";
+      if (GET_CODE (operands[1]) == REG)
+	{
+	  rtx xoperands[2];
+	  int offset = - get_frame_size () - 8;
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+	  xoperands[0] = GEN_INT (offset + 4);
+	  output_asm_insn ("st_32 %1,r25,%0", xoperands);
+	  xoperands[1] = operands[1];
+	  xoperands[0] = GEN_INT (offset);
+	  output_asm_insn ("st_32 %1,r25,%0", xoperands);
+	  xoperands[1] = operands[0];
+	  output_asm_insn ("ld_dbl %1,r25,%0\n\tnop", xoperands);
+	  return "";
+	}
+      return "ld_dbl %0,%1\n\tnop";
+    }
+  else if (FP_REG_P (operands[1]))
+    {
+      if (GET_CODE (operands[0]) == REG)
+	{
+	  rtx xoperands[2];
+	  int offset = - get_frame_size () - 8;
+	  xoperands[0] = GEN_INT (offset);
+	  xoperands[1] = operands[1];
+	  output_asm_insn ("st_dbl %1,r25,%0", xoperands);
+	  xoperands[1] = operands[0];
+	  output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  xoperands[0] = GEN_INT (offset + 4);
+	  output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
+	  return "";
+	}
+      return "st_dbl %1,%0";
+    }
+}
+
+/* Return a REG that occurs in ADDR with coefficient 1.
+   ADDR can be effectively incremented by incrementing REG.  */
+
+static rtx
+find_addr_reg (addr)
+     rtx addr;
+{
+  while (GET_CODE (addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (addr, 0)) == REG)
+	addr = XEXP (addr, 0);
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 0)))
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 1)))
+	addr = XEXP (addr, 0);
+      else
+	abort ();
+    }
+  if (GET_CODE (addr) == REG)
+    return addr;
+  abort ();
+}
+
+/* Generate code to add a large integer constant to register, reg, storing
+ * the result in a register, target.  Offset must be 27-bit signed quantity */
+
+static char *
+output_add_large_offset (target, reg, offset)
+     rtx target, reg;
+     int offset;
+{
+  rtx operands[3];
+  int high, n, i;
+  operands[0] = target, operands[1] = reg;
+    
+  for (high = offset, n = 0; 
+       (unsigned) (high + 0x2000) >= 0x4000; 
+       high >>= 1, n += 1)
+    ;
+  operands[2] = GEN_INT (high);
+  output_asm_insn ("add_nt r2,r0,%2", operands);
+  i = n;
+  while (i >= 3)
+    output_asm_insn ("sll r2,r2,$3", operands), i -= 3;
+  if (i == 2) 
+    output_asm_insn ("sll r2,r2,$2", operands);
+  else if (i == 1)
+    output_asm_insn ("sll r2,r2,$1", operands);
+  output_asm_insn ("add_nt %0,r2,%1", operands);
+  if (offset - (high << n) != 0)
+    {
+      operands[2] = GEN_INT (offset - (high << n));
+      output_asm_insn ("add_nt %0,%0,%2", operands);
+    }
+  return "";
+}
+
+/* Additional TESTFN for matching. Like immediate_operand, but matches big
+ * constants */
+
+int
+big_immediate_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (GET_CODE (op) == CONST_INT);
+}
diff --git a/gnu/egcs/gcc/config/spur/spur.h b/gnu/egcs/gcc/config/spur/spur.h
new file mode 100644
index 00000000000..e6d058a4491
--- /dev/null
+++ b/gnu/egcs/gcc/config/spur/spur.h
@@ -0,0 +1,1051 @@
+/* Definitions of target machine for GNU compiler, for SPUR chip.
+   Copyright (C) 1988, 1995, 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* Note that some other tm.h files include this one and then override
+   many of the definitions that relate to assembler syntax.  */
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-Dspur -Acpu(spur) -Amachine(spur)"
+
+/* Link with libg.a when debugging, for dbx's sake.  */
+
+#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
+
+/* Print subsidiary information on the compiler version in use.  */
+#define TARGET_VERSION fprintf (stderr, " (spur)");
+
+/* Run-time compilation parameters selecting different hardware subsets.
+
+   On the SPUR, we don't yet need any.  */
+
+extern int target_flags;
+
+/* Nonzero if we should generate code to use the fpu.  */
+#define TARGET_FPU (target_flags & 1)
+
+/* Nonzero if we should expand constant shifts into series of shift
+   instructions.  */
+#define TARGET_EXPAND_SHIFTS (target_flags & 2)
+
+/* Nonzero if we should generate long jumps for compares. */
+#define TARGET_LONG_JUMPS (target_flags & 4)
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES  \
+  { {"fpu", 1},			\
+    {"soft-float", -1},		\
+    {"expand-shifts", 2},       \
+    {"lib-shifts", -2},		\
+    {"long-jumps", 4},		\
+    {"short-jumps", -4},	\
+    { "", TARGET_DEFAULT}}
+
+#define TARGET_DEFAULT 0
+
+/* target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is a moot question on the SPUR due to the lack of bit-field insns.  */
+#define BITS_BIG_ENDIAN 0
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+/* That is not true on SPUR.  */
+#define BYTES_BIG_ENDIAN 0
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+/* For SPUR we can decide arbitrarily
+   since there are no machine instructions for them.  */
+#define WORDS_BIG_ENDIAN 0
+
+/* number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 64
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 64
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Every structure's size must be a multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY 32
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 64
+
+/* Set this nonzero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+
+   SPUR has 32 fullword registers and 15 floating point registers.  */
+
+#define FIRST_PSEUDO_REGISTER 47
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+   On SPUR, this includes all the global registers
+   and the callee return address register.  */
+#define FIXED_REGISTERS  \
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 0, 0, 0, 0, 0,		\
+  0, 0, 0, 0, 0, 0, 0, 0, 1, 1,	\
+  1, 0, 0, 0, 0, 0,		\
+  1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+#define CALL_USED_REGISTERS  \
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 0, 0, 0, 0, 0,		\
+  0, 0, 0, 0, 0, 0, 0, 0, 1, 1,	\
+  1, 1, 1, 1, 1, 1,		\
+  1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On SPUR, ordinary registers hold 32 bits worth;
+   a single floating point register is always enough for
+   anything that can be stored in them at all.  */
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  ((REGNO) >= 32 ? GET_MODE_NUNITS ((MODE))	\
+   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   On SPUR, the cpu registers can hold any mode but the float registers
+   can hold only floating point.  And they can't hold anything if use
+   of hardware floating point is disabled.  */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+  (((REGNO) < 32							\
+    && (REGNO) + ((GET_MODE_UNIT_SIZE ((MODE)) + 3) / 4) <= 32)		\
+   || (TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode		\
+		      || (MODE) == SCmode || (MODE) == DCmode)))
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+  (((MODE1) == SFmode || (MODE1) == DFmode		\
+    || (MODE1) == SCmode || (MODE1) == DCmode)		\
+   == ((MODE2) == SFmode || (MODE2) == DFmode		\
+       || (MODE2) == SCmode || (MODE2) == DCmode))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* SPUR pc isn't overloaded on a register that the compiler knows about.  */
+/* #define PC_REGNUM  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 4
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 25
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 1
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM 25
+
+/* Register in which static-chain is passed to a function.  */
+/* ??? */
+#define STATIC_CHAIN_REGNUM 8
+
+/* Register in which address to store a structure value
+   is passed to a function.  */
+#define STRUCT_VALUE_REGNUM 27
+#define STRUCT_VALUE_INCOMING_REGNUM 11
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+   
+/* The 68000 has two kinds of registers, hence four classes.  */
+
+enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+ {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS {{0, 0}, {-1, 0}, {0, 0x7fff}, {-1, 0x7fff}}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+#define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS GENERAL_REGS
+#define BASE_REG_CLASS GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) \
+  ((C) == 'f' ? FP_REGS : NO_REGS)
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+
+   For SPUR, `I' is used for the range of constants an insn
+   can actually contain.
+   `J' is used for the range which is just zero (since that is R0).
+   `K' is used for the 5-bit operand of a compare insns.  */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
+  ((C) == 'I' ? (unsigned) ((VALUE) + 0x2000) < 0x4000	\
+   : (C) == 'J' ? (VALUE) == 0				\
+   : (C) == 'K' ? (unsigned) (VALUE) < 0x20		\
+   : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  	\
+  ((C) == 'G' && CONST_DOUBLE_HIGH (VALUE) == 0		\
+   && CONST_DOUBLE_LOW (VALUE) == 0)
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+/* On SPUR, this is the size of MODE in words,
+   except in the FP regs, where a single reg is always enough.  */
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+ ((CLASS) == FP_REGS ? 1			\
+  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+#define STARTING_FRAME_OFFSET 0
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.
+   On SPUR, don't define this because there are no push insns.  */
+/*  #define PUSH_ROUNDING(BYTES) */
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL) 0
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.  */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+/* On SPUR the value is found in the second "output" register.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)  \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), 27)
+
+/* But the called function leaves it in the second "input" register.  */
+
+#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)  \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), 11)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 27)
+
+/* 1 if N is a possible register number for a function value
+   as seen by the caller.
+   On SPUR, the first "output" reg is the only register thus used.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 27)
+
+/* 1 if N is a possible register number for function argument passing.
+   On SPUR, these are the "output" registers.  */
+
+#define FUNCTION_ARG_REGNO_P(N) ((N) < 32 && (N) > 26)
+
+/* Define this macro if the target machine has "register windows".  This
+   C expression returns the register number as seen by the called function
+   corresponding to register number OUT as seen by the calling function.
+   Return OUT if register number OUT is not an outbound register.  */
+
+#define INCOMING_REGNO(OUT) \
+ (((OUT) < 27 || (OUT) > 31) ? (OUT) : (OUT) - 16)
+
+/* Define this macro if the target machine has "register windows".  This
+   C expression returns the register number as seen by the calling function
+   corresponding to register number IN as seen by the called function.
+   Return IN if register number IN is not an inbound register.  */
+
+#define OUTGOING_REGNO(IN) \
+ (((IN) < 11 || (IN) > 15) ? (IN) : (IN) + 16)
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On SPUR, this is a single integer, which is a number of words
+   of arguments scanned so far (including the invisible argument,
+   if any, which holds the structure-value-address).
+   Thus 5 or more means all following args should go on the stack.  */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On SPUR, the offset normally starts at 0, but starts at 4 bytes
+   when the function gets a structure-value-address as an
+   invisible first argument.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
+ ((CUM) = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE)))))
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) += ((MODE) != BLKmode			\
+	    ? (GET_MODE_SIZE (MODE) + 3) / 4	\
+	    : (int_size_in_bytes (TYPE) + 3) / 4))
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+/* On SPUR the first five words of args are normally in registers
+   and the rest are pushed.  But any arg that won't entirely fit in regs
+   is pushed.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)		\
+(5 >= ((CUM)						\
+       + ((MODE) == BLKmode				\
+	  ? (int_size_in_bytes (TYPE) + 3) / 4		\
+	  : (GET_MODE_SIZE (MODE) + 3) / 4))		\
+ ? gen_rtx (REG, (MODE), 27 + (CUM))			\
+ : 0)
+
+/* Define where a function finds its arguments.
+   This is different from FUNCTION_ARG because of register windows.  */
+
+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)	\
+(5 >= ((CUM)						\
+       + ((MODE) == BLKmode				\
+	  ? (int_size_in_bytes (TYPE) + 3) / 4		\
+	  : (GET_MODE_SIZE (MODE) + 3) / 4))		\
+ ? gen_rtx (REG, (MODE), 11 + (CUM))			\
+ : 0)
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+/* On spur, move-double insns between fpu and cpu need an 8-byte block
+   of memory.  If any fpu reg is used in the function, we allocate
+   such a block here, at the bottom of the frame, just in case it's needed.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE)				\
+{								\
+  extern char call_used_regs[];					\
+  extern int current_function_pretend_args_size;		\
+  int fsize = ((SIZE) + 7) & ~7;				\
+  int nregs, i, fp_used = 0;					\
+  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
+    {								\
+      if (regs_ever_live[i] && ! call_used_regs[i])		\
+        nregs++;						\
+      if (regs_ever_live[i]) fp_used = 1;			\
+    }								\
+  if (fp_used) fsize += 8;					\
+  fprintf (FILE, "0:\trd_special r24,pc\n");			\
+  fprintf (FILE, "\tand r24,r24,$~0x3\n");			\
+  fprintf (FILE, "\tadd_nt r25,r4,$%d\n",			\
+	   - current_function_pretend_args_size);		\
+  if (fsize + nregs != 0 || current_function_pretend_args_size > 0)\
+    {								\
+      int n = - fsize - nregs * 16;				\
+      if (n >= -8192)						\
+        fprintf (FILE, "\tadd_nt r4,r25,$%d\n", n);		\
+      else							\
+        {							\
+	  fprintf (FILE, "\tadd_nt r4,r25,$-8192\n");		\
+	  n += 8192;						\
+          while (n < -8192)					\
+            fprintf (FILE, "\tadd_nt r4,r4,$-8192\n"), n += 8192; \
+	  if (n != 0)						\
+            fprintf (FILE, "\tadd_nt r4,r4,$%d\n", n);		\
+        }							\
+      }								\
+  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
+    if (regs_ever_live[i] && ! call_used_regs[i])		\
+      {								\
+        fprintf (FILE, "\tst_ext1 %s,r4,$%d\n",			\
+	         reg_names[i], 8 * nregs++);			\
+        fprintf (FILE, "\tst_ext2 %s,r4,$%d\n",			\
+	         reg_names[i], 8 * nregs++);			\
+      }								\
+}
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)  \
+   abort ();
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+extern int current_function_calls_alloca;
+extern int current_function_pretend_args_size;
+
+#define EXIT_IGNORE_STACK	\
+ (get_frame_size () != 0	\
+  || current_function_calls_alloca || current_function_pretend_args_size)
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer!
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE)				\
+{								\
+  extern char call_used_regs[];					\
+  extern int current_function_calls_alloca;			\
+  extern int current_function_pretend_args_size;		\
+  int fsize = ((SIZE) + 7) & ~7;				\
+  int nregs, i, fp_used = 0;					\
+  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
+    {								\
+      if (regs_ever_live[i] && ! call_used_regs[i])		\
+	nregs++;						\
+      if (regs_ever_live[i]) fp_used = 1;			\
+    }								\
+  if (fp_used) fsize += 8;					\
+  if (nregs != 0)						\
+    {								\
+      fprintf (FILE, "\tadd_nt r4,r25,$%d\n", - fsize - nregs * 16); \
+      for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
+        if (regs_ever_live[i] && ! call_used_regs[i])		\
+	  {							\
+            fprintf (FILE, "\tld_ext1 %s,r4,$%d\n\tnop\n",	\
+		     reg_names[i], 8 * nregs++);		\
+            fprintf (FILE, "\tld_ext2 %s,r4,$%d\n\tnop\n",	\
+		     reg_names[i], 8 * nregs++);		\
+	  }							\
+    }								\
+  if (fsize != 0 || nregs != 0 || current_function_calls_alloca	\
+      || current_function_pretend_args_size > 0)		\
+    fprintf (FILE, "\tadd_nt r4,r25,$%d\n",			\
+	     current_function_pretend_args_size);		\
+  fprintf (FILE, "\treturn r10,$8\n\tnop\n");			\
+}
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
+
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
+#define REGNO_OK_FOR_FP_P(REGNO) \
+(((REGNO) ^ 0x20) < 14 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 14)
+
+/* Now macros that check whether X is a register and also,
+   strictly, whether it is in a specified class.
+
+   These macros are specific to the SPUR, and may be used only
+   in code for printing assembler insns and in conditions for
+   define_optimization.  */
+
+/* 1 if X is an fp register.  */
+
+#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)   \
+  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
+   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
+   || GET_CODE (X) == HIGH)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_CONSTANT_P(X)		\
+ ((GET_CODE (X) == CONST_INT			\
+   && (unsigned) (INTVAL (X) + 0x2000) < 0x4000)\
+  || (GET_CODE (X) == SYMBOL_REF && (X)->unchanging))
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   On SPUR, the actual legitimate addresses must be REG+SMALLINT or REG+REG.
+   Actually, REG+REG is not legitimate for stores, so 
+   it is obtained only by combination on loads.
+   We can treat a SYMBOL_REF as legitimate if it is part of this
+   function's constant-pool, because such addresses can actually
+   be output as REG+SMALLINT.  */
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
+{ if (GET_CODE (X) == REG			\
+      && REG_OK_FOR_BASE_P (X))			\
+    goto ADDR;					\
+  if (GET_CODE (X) == SYMBOL_REF && (X)->unchanging)	\
+    goto ADDR;					\
+  if (GET_CODE (X) == PLUS			\
+      && GET_CODE (XEXP (X, 0)) == REG		\
+      && REG_OK_FOR_BASE_P (XEXP (X, 0)))	\
+    {						\
+      if (GET_CODE (XEXP (X, 1)) == CONST_INT	\
+	  && INTVAL (XEXP (X, 1)) >= -0x2000	\
+	  && INTVAL (XEXP (X, 1)) < 0x2000)	\
+	goto ADDR;				\
+    }						\
+}
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.  */
+
+/* On SPUR, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	\
+{ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
+    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
+		   copy_to_mode_reg (SImode, XEXP (X, 1)));	\
+  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
+    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
+		   copy_to_mode_reg (SImode, XEXP (X, 0)));	\
+  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
+    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
+		   force_operand (XEXP (X, 0), 0));		\
+  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
+    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
+		   force_operand (XEXP (X, 1), 0));		\
+  if (memory_address_p (MODE, X))				\
+    goto WIN; }
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+   On the SPUR this is never true.  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE SImode
+
+/* Define as C expression which evaluates to nonzero if the tablejump
+   instruction expects the table to contain offsets from the address of the
+   table.
+   Do not define this if the table should contain absolute addresses. */
+/* #define CASE_VECTOR_PC_RELATIVE 1 */
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 1
+
+/* This is BSD, so it wants DBX format.  */
+#define DBX_DEBUGGING_INFO
+
+/* Do not break .stabs pseudos into continuations.  */
+#define DBX_CONTIN_LENGTH 0
+
+/* Don't try to use the `x' type-cross-reference character in DBX data.
+   Also has the consequence of putting each struct, union or enum
+   into a separate .stabs, containing only cross-refs to the others.  */
+#define DBX_NO_XREFS
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* A function address in a call instruction
+   is a byte address (for indexing purposes)
+   so give the MEM rtx a byte's mode.  */
+#define FUNCTION_MODE SImode
+
+/* Define this if addresses of constant functions
+   shouldn't be put through pseudo regs where they can be cse'd.
+   Desirable on machines where ordinary constants are expensive
+   but a CALL with constant address is cheap.  */
+#define NO_FUNCTION_CSE
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:						\
+    if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+    return 2;							\
+  case CONST_DOUBLE:						\
+    return 4;
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  */
+
+/* (None are needed on SPUR.)  */
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+/* The SPUR does not really have a condition code.  */
+
+#define NOTICE_UPDATE_CC(EXP, INSN) \
+{ CC_STATUS_INIT; }
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.  */
+
+#define ASM_FILE_START(FILE)
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON ""
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF ""
+
+/* Output before read-only data.  */
+
+#define TEXT_SECTION_ASM_OP ".text"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP ".data"
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",		\
+ "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",	\
+ "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",	\
+ "r30", "r31",								\
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",	\
+ "f10", "f11", "f12", "f13", "f14" }
+
+/* How to renumber registers for dbx and gdb.  */
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
+  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* The prefix to add to user-visible assembler symbols. */
+
+#define USER_LABEL_PREFIX "_"
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
+  fprintf (FILE, "\t.double %.20e\n", (VALUE))
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
+  fprintf (FILE, "\t.single %.12e\n", (VALUE))
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( fprintf (FILE, "\t.long "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.word "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.byte "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+/* This is how to output code to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tadd_nt r4,r4,$-4\n\tst_32 %s,r4,$0\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tld_32 %s,r4,$0\n\tadd_nt r4,r4,$4\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.long L%d\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.
+   (SPUR does not use such vectors,
+   but we must define this macro anyway.)  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
+  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", (LOG))
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.space %u\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs (".comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%u\n", (ROUNDED)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
+( fputs (".lcomm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%u\n", (ROUNDED)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.
+
+   On SPUR, the CODE can be `r', meaning this is a register-only operand
+   and an immediate zero should be represented as `r0'.  */
+
+#define PRINT_OPERAND(FILE, X, CODE)  \
+{ if (GET_CODE (X) == REG)						\
+    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
+  else if (GET_CODE (X) == MEM)						\
+    output_address (XEXP (X, 0));					\
+  else if (GET_CODE (X) == CONST_DOUBLE)				\
+    abort ();								\
+  else if ((CODE) == 'r' && (X) == const0_rtx)				\
+    fprintf (FILE, "r0");						\
+  else { putc ('$', FILE); output_addr_const (FILE, X); }}
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
+{ register rtx base, index = 0;					\
+  int offset = 0;						\
+  register rtx addr = ADDR;					\
+  if (GET_CODE (addr) == REG)					\
+    {								\
+      fprintf (FILE, "%s,$0", reg_names[REGNO (addr)]);		\
+    }								\
+  else if (GET_CODE (addr) == PLUS)				\
+    {								\
+      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)		\
+	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
+      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)		\
+	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
+      else							\
+	base = XEXP (addr, 0), index = XEXP (addr, 1);		\
+      fprintf (FILE, "%s,", reg_names[REGNO (base)]);		\
+      if (index == 0)						\
+	fprintf (FILE, "$%d", offset);				\
+      else							\
+	fprintf (FILE, "%s,", reg_names[REGNO (index)]);	\
+    }								\
+  else								\
+    {								\
+      fprintf (FILE, "r24,$(");					\
+      output_addr_const (FILE, addr);				\
+      fprintf (FILE, "-0b)");					\
+    }								\
+}
diff --git a/gnu/egcs/gcc/config/spur/spur.md b/gnu/egcs/gcc/config/spur/spur.md
new file mode 100644
index 00000000000..7ad4af5b342
--- /dev/null
+++ b/gnu/egcs/gcc/config/spur/spur.md
@@ -0,0 +1,1092 @@
+;;- Machine description for SPUR chip for GNU C compiler
+;;   Copyright (C) 1988 Free Software Foundation, Inc.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
+;;- updates for most instructions.
+
+;;- Operand classes for the register allocator:
+
+;; Compare instructions.
+;; This pattern is used for generating an "insn"
+;; which does just a compare and sets a (fictitious) condition code.
+
+;; The actual SPUR insns are compare-and-conditional-jump.
+;; The define_peephole's below recognize the combinations of
+;; compares and jumps, and output each pair as a single assembler insn.
+
+;; This controls RTL generation and register allocation.
+(define_insn "cmpsi"
+  [(set (cc0)
+	(compare (match_operand:SI 0 "register_operand" "rK")
+		 (match_operand:SI 1 "nonmemory_operand" "rK")))]
+  ""
+  "*
+{
+  cc_status.value1 = operands[0], cc_status.value2 = operands[1];
+  return \"\";
+}")
+
+;; We have to have this because cse can optimize the previous pattern
+;; into this one.
+
+(define_insn "tstsi"
+  [(set (cc0)
+	(match_operand:SI 0 "register_operand" "r"))]
+  ""
+  "*
+{
+  cc_status.value1 = operands[0], cc_status.value2 = const0_rtx;
+  return \"\";
+}")
+
+
+;; These control RTL generation for conditional jump insns
+;; and match them for register allocation.
+
+(define_insn "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"eq\", \"eq\", \"ne\", \"ne\"); ")
+
+(define_insn "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"ne\", \"ne\", \"eq\", \"eq\"); ")
+
+(define_insn "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"gt\", \"lt\", \"le\", \"ge\"); ")
+
+(define_insn "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"ugt\", \"ult\", \"ule\", \"uge\"); ")
+
+(define_insn "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"lt\", \"gt\", \"ge\", \"le\"); ")
+
+(define_insn "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"ult\", \"ugt\", \"uge\", \"ule\"); ")
+
+(define_insn "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"ge\", \"le\", \"lt\", \"gt\"); ")
+
+(define_insn "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"uge\", \"ule\", \"ult\", \"ugt\"); ")
+
+(define_insn "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"le\", \"ge\", \"gt\", \"lt\"); ")
+
+(define_insn "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "* return output_compare (operands, \"ule\", \"uge\", \"ugt\", \"ult\"); ")
+
+;; These match inverted jump insns for register allocation.
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"ne\", \"ne\", \"eq\", \"eq\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"eq\", \"eq\", \"ne\", \"ne\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"le\", \"ge\", \"gt\", \"lt\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"ule\", \"uge\", \"ugt\", \"ult\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"ge\", \"le\", \"lt\", \"gt\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"uge\", \"ule\", \"ult\", \"ugt\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"lt\", \"gt\", \"ge\", \"le\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"ult\", \"ugt\", \"uge\", \"ule\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"gt\", \"lt\", \"le\", \"ge\"); ")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_compare (operands, \"ugt\", \"ult\", \"ule\", \"uge\"); ")
+
+;; Move instructions
+
+(define_insn "movsi"
+  [(set (match_operand:SI 0 "general_operand" "=r,m")
+	(match_operand:SI 1 "general_operand" "rmi,rJ"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM)
+    return \"st_32 %r1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    return \"ld_32 %0,%1\;nop\";
+  if (GET_CODE (operands[1]) == REG)
+    return \"add_nt %0,%1,$0\";
+  if (GET_CODE (operands[1]) == SYMBOL_REF && operands[1]->unchanging)
+    return \"add_nt %0,r24,$(%1-0b)\";
+  return \"add_nt %0,r0,%1\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
+			 (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "ld_32 %0,%1,%2\;nop")
+
+;; Generate insns for moving single bytes.
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    operands[1] = copy_to_reg (operands[1]);
+
+  if (GET_CODE (operands[1]) == MEM)
+    {
+      rtx tem = gen_reg_rtx (SImode);
+      rtx addr = force_reg (SImode, XEXP (operands[1], 0));
+      rtx subreg;
+
+      emit_move_insn (tem, gen_rtx (MEM, SImode, addr));
+      if (GET_CODE (operands[0]) == SUBREG)
+	subreg = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[0]),
+			  SUBREG_WORD (operands[0]));
+      else
+	subreg = gen_rtx (SUBREG, SImode, operands[0], 0);
+
+      emit_insn (gen_rtx (SET, VOIDmode, subreg,
+			  gen_rtx (ZERO_EXTRACT, SImode, tem,
+				   GEN_INT (8),
+				   addr)));
+    }
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      rtx tem = gen_reg_rtx (SImode);
+      rtx addr = force_reg (SImode, XEXP (operands[0], 0));
+      rtx subreg;
+
+      emit_move_insn (tem, gen_rtx (MEM, SImode, addr));
+      if (! CONSTANT_ADDRESS_P (operands[1]))
+	{
+	  if (GET_CODE (operands[1]) == SUBREG)
+	    subreg = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
+			      SUBREG_WORD (operands[1]));
+	  else
+	    subreg = gen_rtx (SUBREG, SImode, operands[1], 0);
+	}
+
+      emit_insn (gen_rtx (SET, VOIDmode,
+			  gen_rtx (ZERO_EXTRACT, SImode, tem,
+				   GEN_INT (8),
+				   addr),
+			  subreg));
+      emit_move_insn (gen_rtx (MEM, SImode, addr), tem);
+    }
+  else
+    {
+      emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
+    }
+  DONE;
+}")
+
+;; Recognize insns generated for moving single bytes.
+
+(define_insn ""
+  [(set (match_operand:QI 0 "general_operand" "=r,m")
+	(match_operand:QI 1 "general_operand" "rmi,r"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM)
+    return \"st_32 %1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    return \"ld_32 %0,%1\;nop\";
+  if (GET_CODE (operands[1]) == REG)
+    return \"add_nt %0,%1,$0\";
+  return \"add_nt %0,r0,%1\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (const_int 8)
+			 (match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "extract %0,%1,%2")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+			 (const_int 8)
+			 (match_operand:SI 1 "nonmemory_operand" "rI"))
+	(match_operand:SI 2 "nonmemory_operand" "ri"))]
+  ""
+  "wr_insert %1\;insert %0,%0,%2")
+
+;; Constant propagation can optimize the previous pattern into this pattern.
+;[Not any more.  It could when the position-operand contains a MULT.]
+
+;(define_insn ""
+;  [(set (zero_extract:QI (match_operand:SI 0 "register_operand" "+r")
+;			 (const_int 8)
+;			 (match_operand:SI 1 "immediate_operand" "I"))
+;	(match_operand:QI 2 "register_operand" "r"))]
+;  "GET_CODE (operands[1]) == CONST_INT
+;   && INTVAL (operands[1]) % 8 == 0
+;   && (unsigned) INTVAL (operands[1]) < 32"
+;  "*
+;{
+;  operands[1] = GEN_INT (INTVAL (operands[1]) / 8);
+;  return \"wr_insert 0,0,%1\;insert %0,%0,%2\";
+;}")
+
+;; The three define_expand patterns on this page
+;; serve as subroutines of "movhi".
+
+;; Generate code to fetch an aligned halfword from memory.
+;; Operand 0 is the destination register (HImode).
+;; Operand 1 is the memory address (SImode).
+;; Operand 2 is a temporary (SImode).
+;; Operand 3 is a temporary (SImode).
+;; Operand 4 is a temporary (QImode).
+
+;; Operand 5 is an internal temporary (HImode).
+
+(define_expand "loadhi"
+  [(set (match_operand:SI 2 "register_operand" "")
+	(mem:SI (match_operand:SI 1 "register_operand" "")))
+   ;; Extract the low byte.
+   (set (subreg:SI (match_dup 5) 0)
+	(zero_extract:SI (match_dup 2) (const_int 8) (match_dup 1)))
+   ;; Form address of high byte.
+   (set (match_operand:SI 3 "register_operand" "")
+	(plus:SI (match_dup 1) (const_int 1)))
+   ;; Extract the high byte.
+   (set (subreg:SI (match_operand:QI 4 "register_operand" "") 0)
+	(zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3)))
+   ;; Put the high byte in with the low one.
+   (set (zero_extract:SI (match_dup 5) (const_int 8) (const_int 1))
+	(subreg:SI (match_dup 4) 0))
+   (set (match_operand:HI 0 "register_operand" "") (match_dup 5))]
+  ""
+  "operands[5] = gen_reg_rtx (HImode);")
+
+;; Generate code to store an aligned halfword into memory.
+;; Operand 0 is the destination address (SImode).
+;; Operand 1 is the source register (HImode, not constant).
+;; Operand 2 is a temporary (SImode).
+;; Operand 3 is a temporary (SImode).
+;; Operand 4 is a temporary (QImode).
+
+;; Operand 5 is an internal variable made from operand 1.
+
+(define_expand "storehi"
+  [(set (match_operand:SI 2 "register_operand" "")
+	(mem:SI (match_operand:SI 0 "register_operand" "")))
+   ;; Insert the low byte.
+   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 0))
+	(match_dup 5))
+   ;; Form address of high byte.
+   (set (match_operand:SI 3 "register_operand" "")
+	(plus:SI (match_dup 0) (const_int 1)))
+   ;; Extract the high byte from the source.
+   (set (subreg:SI (match_operand:QI 4 "register_operand" "") 0)
+	(zero_extract:SI (match_operand:HI 1 "register_operand" "")
+			 (const_int 8) (const_int 1)))
+   ;; Store high byte into the memory word
+   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3))
+	(subreg:SI (match_dup 4) 0))
+   ;; Put memory word back into memory.
+   (set (mem:SI (match_dup 0))
+	(match_dup 2))]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == SUBREG)
+    operands[5] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
+			   SUBREG_WORD (operands[1]));
+  else
+    operands[5] = gen_rtx (SUBREG, SImode, operands[1], 0);
+}")
+
+;; Like storehi but operands[1] is a CONST_INT.
+
+(define_expand "storeinthi"
+  [(set (match_operand:SI 2 "register_operand" "")
+	(mem:SI (match_operand:SI 0 "register_operand" "")))
+   ;; Insert the low byte.
+   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 0))
+	(match_dup 5))
+   ;; Form address of high byte.
+   (set (match_operand:SI 3 "register_operand" "")
+	(plus:SI (match_dup 0) (const_int 1)))
+   ;; Store high byte into the memory word
+   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3))
+	(match_dup 6))
+   ;; Put memory word back into memory.
+   (set (mem:SI (match_dup 0))
+	(match_dup 2))]
+  ""
+  " operands[5] = GEN_INT (INTVAL (operands[1]) & 255);
+    operands[6] = GEN_INT ((INTVAL (operands[1]) >> 8) & 255);
+")
+
+;; Main entry for generating insns to move halfwords.
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    operands[1] = copy_to_reg (operands[1]);
+  
+  if (GET_CODE (operands[1]) == MEM)
+    {
+      rtx insn =
+	emit_insn (gen_loadhi (operands[0],
+			       force_reg (SImode, XEXP (operands[1], 0)),
+			       gen_reg_rtx (SImode), gen_reg_rtx (SImode),
+			       gen_reg_rtx (QImode)));
+      /* Tell cse what value the loadhi produces, so it detect duplicates.  */
+      REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, operands[1],
+					     REG_NOTES (insn));
+    }
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      if (GET_CODE (operands[1]) == CONST_INT)
+	emit_insn (gen_storeinthi (force_reg (SImode, XEXP (operands[0], 0)),
+			           operands[1],
+				   gen_reg_rtx (SImode), gen_reg_rtx (SImode),
+				   gen_reg_rtx (QImode)));
+      else
+	{
+	  if (CONSTANT_P (operands[1]))
+            operands[1] = force_reg (HImode, operands[1]);
+	  emit_insn (gen_storehi (force_reg (SImode, XEXP (operands[0], 0)),
+				  operands[1],
+				  gen_reg_rtx (SImode), gen_reg_rtx (SImode),
+				  gen_reg_rtx (QImode)));
+	}
+    }
+  else
+    emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
+  DONE;
+}")
+
+;; Recognize insns generated for moving halfwords.
+;; (Note that the extract and insert patterns for single-byte moves
+;;  are also involved in recognizing some of the insns used for this purpose.)
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=r,m")
+	(match_operand:HI 1 "general_operand" "rmi,r"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM)
+    return \"st_32 %1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    return \"ld_32 %0,%1\;nop\";
+  if (GET_CODE (operands[1]) == REG)
+    return \"add_nt %0,%1,$0\";
+  return \"add_nt %0,r0,%1\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
+			 (const_int 8)
+			 (match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "extract %0,%1,%2")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:HI 0 "register_operand" "+r")
+			 (const_int 8)
+			 (match_operand:SI 1 "nonmemory_operand" "rI"))
+	(match_operand:SI 2 "nonmemory_operand" "ri"))]
+  ""
+  "wr_insert %1\;insert %0,%0,%2")
+
+;; Constant propagation can optimize the previous pattern into this pattern.
+
+;(define_insn ""
+;  [(set (zero_extract:QI (match_operand:HI 0 "register_operand" "+r")
+;			 (const_int 8)
+;			 (match_operand:SI 1 "immediate_operand" "I"))
+;	(match_operand:QI 2 "register_operand" "r"))]
+;  "GET_CODE (operands[1]) == CONST_INT
+;   && INTVAL (operands[1]) % 8 == 0
+;   && (unsigned) INTVAL (operands[1]) < 32"
+;  "*
+;{
+;  operands[1] = GEN_INT (INTVAL (operands[1]) / 8);
+;  return \"wr_insert 0,0,%1\;insert %0,%0,%2\";
+;}")
+
+;; This pattern forces (set (reg:DF ...) (const_double ...))
+;; to be reloaded by putting the constant into memory.
+;; It must come before the more general movdf pattern.
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand" "=&r,f,&o")
+	(match_operand:DF 1 "" "mG,m,G"))]
+  "GET_CODE (operands[1]) == CONST_DOUBLE"
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    return output_fp_move_double (operands);
+  if (operands[1] == CONST0_RTX (DFmode) && GET_CODE (operands[0]) == REG)
+    {
+      operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      return \"add_nt %0,r0,$0\;add_nt %1,r0,$0\";
+    }
+  if (operands[1] == CONST0_RTX (DFmode) && GET_CODE (operands[0]) == MEM)
+    {
+      operands[1] = adj_offsettable_operand (operands[0], 4);
+      return \"st_32 r0,%0\;st_32 r0,%1\";
+    }
+  return output_move_double (operands);
+}
+")
+  
+(define_insn "movdf"
+  [(set (match_operand:DF 0 "general_operand" "=r,&r,m,?f,?rm")
+	(match_operand:DF 1 "general_operand" "r,m,r,rfm,f"))]
+  ""
+  "*
+{
+  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
+    return output_fp_move_double (operands);
+  return output_move_double (operands);
+}
+")
+
+(define_insn "movdi"
+  [(set (match_operand:DI 0 "general_operand" "=r,&r,m,?f,?rm")
+	(match_operand:DI 1 "general_operand" "r,m,r,rfm,f"))]
+  ""
+  "*
+{
+  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
+    return output_fp_move_double (operands);
+  return output_move_double (operands);
+}
+")
+
+(define_insn "movsf"
+  [(set (match_operand:SF 0 "general_operand" "=rf,m")
+	(match_operand:SF 1 "general_operand" "rfm,rf"))]
+  ""
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return \"fmov %0,%1\";
+      if (GET_CODE (operands[1]) == REG)
+	{
+	  rtx xoperands[2];
+	  int offset = - get_frame_size () - 8;
+	  xoperands[1] = operands[1];
+	  xoperands[0] = GEN_INT (offset);
+	  output_asm_insn (\"st_32 %1,r25,%0\", xoperands);
+	  xoperands[1] = operands[0];
+	  output_asm_insn (\"ld_sgl %1,r25,%0\;nop\", xoperands);
+	  return \"\";
+	}
+      return \"ld_sgl %0,%1\;nop\";
+    }
+  if (FP_REG_P (operands[1]))
+    {
+      if (GET_CODE (operands[0]) == REG)
+	{
+	  rtx xoperands[2];
+	  int offset = - get_frame_size () - 8;
+	  xoperands[0] = GEN_INT (offset);
+	  xoperands[1] = operands[1];
+	  output_asm_insn (\"st_sgl %1,r25,%0\", xoperands);
+	  xoperands[1] = operands[0];
+	  output_asm_insn (\"ld_32 %1,r25,%0\;nop\", xoperands);
+	  return \"\";
+	}
+      return \"st_sgl %1,%0\";
+    }
+  if (GET_CODE (operands[0]) == MEM)
+    return \"st_32 %r1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    return \"ld_32 %0,%1\;nop\";
+  if (GET_CODE (operands[1]) == REG)
+    return \"add_nt %0,%1,$0\";
+  return \"add_nt %0,r0,%1\";
+}")
+
+;;- truncation instructions
+(define_insn "truncsiqi2"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(truncate:QI
+	 (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "add_nt %0,%1,$0")
+
+(define_insn "trunchiqi2"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(truncate:QI
+	 (match_operand:HI 1 "register_operand" "r")))]
+  ""
+  "add_nt %0,%1,$0")
+
+(define_insn "truncsihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(truncate:HI
+	 (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "add_nt %0,%1,$0")
+
+;;- zero extension instructions
+
+;; Note that the one starting from HImode comes before those for QImode
+;; so that a constant operand will match HImode, not QImode.
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:HI 1 "register_operand" "") ;Changed to SI below
+		;; This constant is invalid, but reloading will handle it.
+		;; It's useless to generate here the insns to construct it
+		;; because constant propagation would simplify them anyway.
+		(match_dup 2)))]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == SUBREG)
+    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
+			   SUBREG_WORD (operands[1]));
+  else
+    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
+
+  operands[2] = force_reg (SImode, GEN_INT (65535));
+}")
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(zero_extend:HI
+	 (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "extract %0,%1,$0")
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI
+	 (match_operand:QI 1 "register_operand" "r")))]
+  ""
+  "extract %0,%1,$0")
+
+;;- sign extension instructions
+;; Note that the one starting from HImode comes before those for QImode
+;; so that a constant operand will match HImode, not QImode.
+
+(define_expand "extendhisi2"
+  [(set (match_dup 2)
+	(and:SI (match_operand:HI 1 "register_operand" "") ;Changed to SI below
+		(match_dup 4)))
+   (set (match_dup 3) (plus:SI (match_dup 2) (match_dup 5)))
+   (set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_dup 3) (match_dup 5)))]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == SUBREG)
+    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
+			   SUBREG_WORD (operands[1]));
+  else
+    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
+
+  operands[2] = gen_reg_rtx (SImode);
+  operands[3] = gen_reg_rtx (SImode);
+  operands[4] = force_reg (SImode, GEN_INT (65535));
+  operands[5] = force_reg (SImode, GEN_INT (-32768));
+}")
+
+(define_expand "extendqihi2"
+  [(set (match_dup 2)
+	(and:HI (match_operand:QI 1 "register_operand" "") ;Changed to SI below
+		(const_int 255)))
+   (set (match_dup 3)
+	(plus:SI (match_dup 2) (const_int -128)))
+   (set (match_operand:HI 0 "register_operand" "")
+	(xor:SI (match_dup 3) (const_int -128)))]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == SUBREG)
+    operands[1] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[1]),
+			   SUBREG_WORD (operands[1]));
+  else
+    operands[1] = gen_rtx (SUBREG, HImode, operands[1], 0);
+
+  operands[2] = gen_reg_rtx (HImode);
+  operands[3] = gen_reg_rtx (HImode);
+}")
+
+(define_expand "extendqisi2"
+  [(set (match_dup 2)
+	(and:SI (match_operand:QI 1 "register_operand" "") ;Changed to SI below
+		(const_int 255)))
+   (set (match_dup 3) (plus:SI (match_dup 2) (const_int -128)))
+   (set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_dup 3) (const_int -128)))]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) == SUBREG)
+    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
+			   SUBREG_WORD (operands[1]));
+  else
+    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
+
+  operands[2] = gen_reg_rtx (SImode);
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+;;- arithmetic instructions
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")
+		 (match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "add %0,%1,%2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")
+		 (match_operand:SI 2 "big_immediate_operand" "g")))]
+  "GET_CODE (operands[2]) == CONST_INT 
+   && (unsigned) (INTVAL (operands[2]) + 0x8000000) < 0x10000000"
+  "*
+{
+  return 
+    output_add_large_offset (operands[0], operands[1], INTVAL (operands[2]));
+}")
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(minus:SI (match_operand:SI 1 "register_operand" "r")
+		  (match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "sub %0,%1,%2")
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
+		(match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "and %0,%1,%2")
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")
+		(match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "or %0,%1,%2")
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")
+		(match_operand:SI 2 "nonmemory_operand" "rI")))]
+  ""
+  "xor %0,%1,%2")
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operand:SI 1 "nonmemory_operand" "rI")))]
+  ""
+  "sub %0,r0,%1")
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "xor %0,%1,$-1")
+
+;; Floating point arithmetic instructions.
+
+(define_insn "adddf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(plus:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fadd %0,%1,%2")
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(plus:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fadd %0,%1,%2")
+
+(define_insn "subdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(minus:DF (match_operand:DF 1 "register_operand" "f")
+		  (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fsub %0,%1,%2")
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(minus:SF (match_operand:SF 1 "register_operand" "f")
+		  (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fsub %0,%1,%2")
+
+(define_insn "muldf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mult:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fmul %0,%1,%2")
+
+(define_insn "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mult:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fmul %0,%1,%2")
+
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(div:DF (match_operand:DF 1 "register_operand" "f")
+		(match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fdiv %0,%1,%2")
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(div:SF (match_operand:SF 1 "register_operand" "f")
+		(match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_FPU"
+  "fdiv %0,%1,%2")
+
+(define_insn "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(neg:DF (match_operand:DF 1 "nonmemory_operand" "f")))]
+  "TARGET_FPU"
+  "fneg %0,%1")
+
+(define_insn "negsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(neg:SF (match_operand:SF 1 "nonmemory_operand" "f")))]
+  "TARGET_FPU"
+  "fneg %0,%1")
+
+(define_insn "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(abs:DF (match_operand:DF 1 "nonmemory_operand" "f")))]
+  "TARGET_FPU"
+  "fabs %0,%1")
+
+(define_insn "abssf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(abs:SF (match_operand:SF 1 "nonmemory_operand" "f")))]
+  "TARGET_FPU"
+  "fabs %0,%1")
+
+;; Shift instructions
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:SI 2 "immediate_operand" "I")))]
+  "GET_CODE (operands[2]) == CONST_INT"
+  "*
+{
+  unsigned int amount = INTVAL (operands[2]);
+
+  switch (amount)
+    {
+    case 0:
+      return \"add_nt %0,%1,$0\";
+    case 1:
+      return \"sll %0,%1,$1\";
+    case 2:
+      return \"sll %0,%1,$2\";
+    default:
+      output_asm_insn (\"sll %0,%1,$3\", operands);
+
+      for (amount -= 3; amount >= 3; amount -= 3)
+	output_asm_insn (\"sll %0,%0,$3\", operands);
+
+      if (amount > 0)
+	output_asm_insn (amount == 1 ? \"sll %0,%0,$1\" : \"sll %0,%0,$2\",
+			 operands);
+      return \"\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+	             (match_operand:SI 2 "immediate_operand" "I")))]
+  "GET_CODE (operands[2]) == CONST_INT"
+  "*
+{
+  unsigned int amount = INTVAL (operands[2]);
+
+  if (amount == 0) 
+    return \"add_nt %0,%1,$0\";
+  else
+    output_asm_insn (\"sra %0,%1,$1\", operands);
+  
+  for (amount -= 1; amount > 0; amount -= 1)
+    output_asm_insn (\"sra %0,%0,$1\", operands);
+
+  return \"\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+	             (match_operand:SI 2 "immediate_operand" "I")))]
+  "GET_CODE (operands[2]) == CONST_INT"
+  "*
+{
+  unsigned int amount = INTVAL (operands[2]);
+
+  if (amount == 0) 
+    return \"add_nt %0,%1,$0\";
+  else
+    output_asm_insn (\"srl %0,%1,$1\", operands);
+  
+  for (amount -= 1; amount > 0; amount -= 1)
+    output_asm_insn (\"srl %0,%0,$1\", operands);
+
+  return \"\";
+}")
+
+(define_expand "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashift:SI (match_operand:SI 1 "register_operand" "")
+		   (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT
+      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 3))
+    FAIL;
+}")
+
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT
+      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))
+    FAIL;
+}")
+
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT
+      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))
+    FAIL;
+}")
+
+;; Unconditional and other jump instructions
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "jump %l0\;nop")
+
+(define_insn "tablejump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jump_reg r0,%0\;nop")
+
+;;- jump to subroutine
+(define_insn "call"
+  [(call (match_operand:SI 0 "memory_operand" "m")
+	 (match_operand:SI 1 "general_operand" "g"))]
+  ;;- Don't use operand 1 for most machines.
+  ""
+  "add_nt r2,%0\;call .+8\;jump_reg r0,r2\;nop")
+
+(define_insn "call_value"
+  [(set (match_operand 0 "" "=g")
+	(call (match_operand:SI 1 "memory_operand" "m")
+	      (match_operand:SI 2 "general_operand" "g")))]
+  ;;- Don't use operand 1 for most machines.
+  ""
+  "add_nt r2,%1\;call .+8\;jump_reg r0,r2\;nop")
+
+;; A memory ref with constant address is not normally valid.
+;; But it is valid in a call insns.  This pattern allows the
+;; loading of the address to combine with the call.
+(define_insn ""
+  [(call (mem:SI (match_operand:SI 0 "" "i"))
+	 (match_operand:SI 1 "general_operand" "g"))]
+  ;;- Don't use operand 1 for most machines.
+  "GET_CODE (operands[0]) == SYMBOL_REF"
+  "call %0\;nop")
+
+(define_insn ""
+  [(set (match_operand 0 "" "=g")
+	(call (mem:SI (match_operand:SI 1 "" "i"))
+	      (match_operand:SI 2 "general_operand" "g")))]
+  ;;- Don't use operand 1 for most machines.
+  "GET_CODE (operands[1]) == SYMBOL_REF"
+  "call %1\;nop")
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop")
diff --git a/gnu/egcs/gcc/config/spur/xm-spur.h b/gnu/egcs/gcc/config/spur/xm-spur.h
new file mode 100644
index 00000000000..1d30053bc53
--- /dev/null
+++ b/gnu/egcs/gcc/config/spur/xm-spur.h
@@ -0,0 +1,39 @@
+/* Configuration for GNU C-compiler for Berkeley SPUR processor.
+   Copyright (C) 1988, 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33