Update to 990629 snapshot

closer to gcc 2.95 release.

20 files changed, 308 insertions, 191 deletions

diff --git a/gnu/egcs/gcc/config/alpha/alpha.h b/gnu/egcs/gcc/config/alpha/alpha.h
index 85711182a52..e9c3f6d2f68 100644
--- a/gnu/egcs/gcc/config/alpha/alpha.h
+++ b/gnu/egcs/gcc/config/alpha/alpha.h
@@ -157,14 +157,14 @@ extern enum alpha_fp_trap_mode alpha_fptm;
 
 /* This means that the processor is an EV5, EV56, or PCA56.  This is defined
    only in TARGET_CPU_DEFAULT.  */
-#define MASK_CPU_EV5	(1 << 29)
+#define MASK_CPU_EV5	(1 << 28)
 
 /* Likewise for EV6.  */
-#define MASK_CPU_EV6	(1 << 30)
+#define MASK_CPU_EV6	(1 << 29)
 
 /* This means we support the .arch directive in the assembler.  Only
    defined in TARGET_CPU_DEFAULT.  */
-#define MASK_SUPPORT_ARCH (1 << 31)
+#define MASK_SUPPORT_ARCH (1 << 30)
 #define TARGET_SUPPORT_ARCH	(target_flags & MASK_SUPPORT_ARCH)
 
 /* These are for target os support and cannot be changed at runtime.  */
@@ -2145,6 +2145,11 @@ literal_section ()						\
   }									      \
   while (0)
 
+/* To get unaligned data, we have to turn off auto alignment.  */
+#define UNALIGNED_SHORT_ASM_OP		".align 0\n\t.word"
+#define UNALIGNED_INT_ASM_OP		".align 0\n\t.long"
+#define UNALIGNED_DOUBLE_INT_ASM_OP	".align 0\n\t.quad"
+
 /* This is how to output an insn to push a register on the stack.
    It need not be very fast code.  */
 
diff --git a/gnu/egcs/gcc/config/alpha/elf.h b/gnu/egcs/gcc/config/alpha/elf.h
index 0e647ef534c..6cea3da5d5b 100644
--- a/gnu/egcs/gcc/config/alpha/elf.h
+++ b/gnu/egcs/gcc/config/alpha/elf.h
@@ -526,3 +526,9 @@ do {									\
 
 /* We support #pragma.  */
 #define HANDLE_SYSV_PRAGMA
+
+/* Undo the auto-alignment stuff from alpha.h.  ELF has unaligned data
+   pseudos natively.  */
+#undef UNALIGNED_SHORT_ASM_OP
+#undef UNALIGNED_INT_ASM_OP
+#undef UNALIGNED_DOUBLE_INT_ASM_OP
diff --git a/gnu/egcs/gcc/config/alpha/vms.h b/gnu/egcs/gcc/config/alpha/vms.h
index 44cf5bf82df..44388b2cf33 100644
--- a/gnu/egcs/gcc/config/alpha/vms.h
+++ b/gnu/egcs/gcc/config/alpha/vms.h
@@ -439,10 +439,6 @@ extern int vms_valid_decl_attribute_p ();
 #define ASM_OUTPUT_ALIGN(FILE,LOG)	\
     fprintf (FILE, "\t.align %d\n", LOG);
 
-#define UNALIGNED_SHORT_ASM_OP	".word"
-#define UNALIGNED_INT_ASM_OP	".long"
-#define UNALIGNED_DOUBLE_INT_ASM_OP	".quad"
-
 #define ASM_OUTPUT_SECTION(FILE,SECTION)			\
    (strcmp (SECTION, ".text") == 0)				\
      ? text_section ()						\
diff --git a/gnu/egcs/gcc/config/arm/arm.c b/gnu/egcs/gcc/config/arm/arm.c
index 1ba5edd2e1b..553e25c7b76 100644
--- a/gnu/egcs/gcc/config/arm/arm.c
+++ b/gnu/egcs/gcc/config/arm/arm.c
@@ -486,13 +486,6 @@ arm_override_options ()
   if (flag_pic && ! TARGET_APCS_STACK)
     arm_pic_register = 10;
   
-  /* Well, I'm about to have a go, but pic is NOT going to be compatible
-     with APCS reentrancy, since that requires too much support in the
-     assembler and linker, and the ARMASM assembler seems to lack some
-     required directives.  */
-  if (flag_pic)
-    warning ("Position independent code not supported");
-  
   if (TARGET_APCS_FLOAT)
     warning ("Passing floating point arguments in fp regs not yet supported");
   
@@ -583,9 +576,14 @@ use_return_insn (iscond)
     return 0;
   if ((iscond && arm_is_strong)
       || TARGET_THUMB_INTERWORK)
-    for (regno = 0; regno < 16; regno++)
-      if (regs_ever_live[regno] && ! call_used_regs[regno])
+    {
+      for (regno = 0; regno < 16; regno++)
+	if (regs_ever_live[regno] && ! call_used_regs[regno])
+	  return 0;
+
+      if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
 	return 0;
+    }
       
   /* Can't be done if any of the FPU regs are pushed, since this also
      requires an insn */
@@ -3704,7 +3702,7 @@ arm_reload_in_hi (operands)
 				   gen_rtx_MEM (QImode, 
 						plus_constant (base,
 							       offset + 1))));
-  if (BYTES_BIG_ENDIAN)
+  if (! BYTES_BIG_ENDIAN)
     emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
 			gen_rtx_IOR (SImode, 
 				     gen_rtx_ASHIFT
@@ -5319,6 +5317,9 @@ output_return_instruction (operand, really_return, reverse)
     if (regs_ever_live[reg] && ! call_used_regs[reg])
       live_regs++;
 
+  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+    live_regs++;
+
   if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
     live_regs++;
 
@@ -5338,7 +5339,9 @@ output_return_instruction (operand, really_return, reverse)
 		reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
 
       for (reg = 0; reg <= 10; reg++)
-        if (regs_ever_live[reg] && ! call_used_regs[reg])
+        if (regs_ever_live[reg] 
+	    && (! call_used_regs[reg]
+		|| (flag_pic && reg == PIC_OFFSET_TABLE_REGNUM)))
           {
 	    strcat (instr, "%|");
             strcat (instr, reg_names[reg]);
@@ -5498,6 +5501,9 @@ output_func_prologue (f, frame_size)
     if (regs_ever_live[reg] && ! call_used_regs[reg])
       live_regs_mask |= (1 << reg);
 
+  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+    live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
+
   if (frame_pointer_needed)
     live_regs_mask |= 0xD800;
   else if (regs_ever_live[14])
@@ -5574,6 +5580,12 @@ output_func_epilogue (f, frame_size)
 	floats_offset += 4;
       }
 
+  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+    {
+      live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
+      floats_offset += 4;
+    }
+
   if (frame_pointer_needed)
     {
       if (arm_fpu_arch == FP_SOFT2)
@@ -5834,12 +5846,17 @@ arm_expand_prologue ()
     store_arg_regs = 1;
 
   if (! volatile_func)
-    for (reg = 0; reg <= 10; reg++)
-      if (regs_ever_live[reg] && ! call_used_regs[reg])
-	live_regs_mask |= 1 << reg;
+    {
+      for (reg = 0; reg <= 10; reg++)
+	if (regs_ever_live[reg] && ! call_used_regs[reg])
+	  live_regs_mask |= 1 << reg;
 
-  if (! volatile_func && regs_ever_live[14])
-    live_regs_mask |= 0x4000;
+      if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+	live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
+
+      if (regs_ever_live[14])
+	live_regs_mask |= 0x4000;
+    }
 
   if (frame_pointer_needed)
     {
diff --git a/gnu/egcs/gcc/config/arm/arm.h b/gnu/egcs/gcc/config/arm/arm.h
index 7b5cd490376..3c133a01b0e 100644
--- a/gnu/egcs/gcc/config/arm/arm.h
+++ b/gnu/egcs/gcc/config/arm/arm.h
@@ -726,7 +726,7 @@ extern const char * structure_size_string;
   if (flag_pic)						\
     {							\
       fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;		\
-      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0;	\
+      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
     }							\
   else if (TARGET_APCS_STACK)				\
     {							\
@@ -1263,6 +1263,9 @@ do {									\
           for (regno = 0; regno <= 10; regno++)				\
 	    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
 	      saved_hard_reg = 1, offset += 4;				\
+	  /* PIC register is a fixed reg, so call_used_regs set.  */	\
+	  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])	\
+	    saved_hard_reg = 1, offset += 4;				\
           for (regno = 16; regno <=23; regno++)				\
 	    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
 	      offset += 12;						\
diff --git a/gnu/egcs/gcc/config/c4x/c4x.c b/gnu/egcs/gcc/config/c4x/c4x.c
index 5c5690a4eaf..23f8bfa093f 100644
--- a/gnu/egcs/gcc/config/c4x/c4x.c
+++ b/gnu/egcs/gcc/config/c4x/c4x.c
@@ -1077,7 +1077,8 @@ c4x_emit_move_sequence (operands, mode)
      and emit associated (HIGH (SYMREF)) if large memory model.  
      c4x_legitimize_address could be used to do this,
      perhaps by calling validize_address.  */
-  if (! (reload_in_progress || reload_completed)
+  if (TARGET_EXPOSE_LDP
+      && ! (reload_in_progress || reload_completed)
       && GET_CODE (op1) == MEM
       && symbolic_address_operand (XEXP (op1, 0), Pmode))
     {
@@ -1088,7 +1089,8 @@ c4x_emit_move_sequence (operands, mode)
 			    gen_rtx_LO_SUM (Pmode, dp_reg, XEXP (op1, 0)));
     }
 
-  if (! (reload_in_progress || reload_completed)
+  if (TARGET_EXPOSE_LDP
+      && ! (reload_in_progress || reload_completed)
       && GET_CODE (op0) == MEM 
       && symbolic_address_operand (XEXP (op0, 0), Pmode))
     {
@@ -1409,12 +1411,14 @@ c4x_check_legit_addr (mode, addr, strict)
       /* Direct addressing.  */
     case LABEL_REF:
     case SYMBOL_REF:
+      if (! TARGET_EXPOSE_LDP && ! strict && mode != HFmode && mode != HImode)
+	return 1;
       /* These need to be converted to a LO_SUM (...). 
-	 c4x_legitimize_address will fix them up.  */
+	 LEGITIMIZE_RELOAD_ADDRESS will do this during reload.  */
       return 0;
 
       /* Do not allow direct memory access to absolute addresses.
-         This is more pain than its worth, especially for the
+         This is more pain than it's worth, especially for the
          small memory model where we can't guarantee that
          this address is within the data page---we don't want
          to modify the DP register in the small memory model,
@@ -1515,6 +1519,32 @@ c4x_legitimize_address (orig, mode)
 }
 
 
+rtx
+c4x_legitimize_reload_address (orig, mode, insn)
+     rtx orig ATTRIBUTE_UNUSED;
+     enum machine_mode mode;
+     rtx insn;
+{                                                                    	
+  if (mode != HImode 
+      && mode != HFmode
+      && GET_MODE (orig) != HImode
+      && GET_MODE (orig) != HFmode
+      && (GET_CODE (orig) == CONST					
+          || GET_CODE (orig) == SYMBOL_REF				
+          || GET_CODE (orig) == LABEL_REF))
+    {                                                                   
+      rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);			
+      if (! TARGET_SMALL)						
+        emit_insn_before (gen_rtx_SET (VOIDmode, dp_reg, 		
+				       gen_rtx_HIGH (Pmode, orig)),	
+			  insn);
+      return gen_rtx_LO_SUM (Pmode, dp_reg, orig);
+    }
+
+  return NULL_RTX;
+}
+
+
 /* Provide the costs of an addressing mode that contains ADDR.
    If ADDR is not a valid address, its cost is irrelevant.  
    This is used in cse and loop optimisation to determine
@@ -3002,20 +3032,24 @@ src_operand (op, mode)
   if (GET_CODE (op) == CONST_DOUBLE)
     return c4x_H_constant (op);
 
-  /* Disallow symbolic addresses.  */
+  /* Disallow symbolic addresses.  Only the predicate
+     symbolic_address_operand will match these.  */
   if (GET_CODE (op) == SYMBOL_REF
       || GET_CODE (op) == LABEL_REF
       || GET_CODE (op) == CONST)
     return 0;
 
-  /* Disallow direct memory access symbolic addresses. 
-     These are usually caught by the movqi expander and
-     converted to a LO_SUM.  */
+  /* If TARGET_EXPOSE_LDP is zero, allow direct memory access to
+     symbolic addresses.  These will be rejected by
+     GO_IF_LEGITIMATE_ADDRESS and fixed up by
+     LEGITIMIZE_RELOAD_ADDRESS.  If TARGET_EXPOSE_LDP is nonzero,
+     disallow direct memory access to symbolic addresses.  These
+     should be converted to a HIGH/LO_SUM pair by the movqi expander.  */
   if (GET_CODE (op) == MEM
       && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	   || GET_CODE (XEXP (op, 0)) == LABEL_REF
 	   || GET_CODE (XEXP (op, 0)) == CONST)))
-    return 0;
+    return ! TARGET_EXPOSE_LDP;
 
   return general_operand (op, mode);
 }
diff --git a/gnu/egcs/gcc/config/c4x/c4x.h b/gnu/egcs/gcc/config/c4x/c4x.h
index 1dc8d5c63ed..7ef0738f008 100644
--- a/gnu/egcs/gcc/config/c4x/c4x.h
+++ b/gnu/egcs/gcc/config/c4x/c4x.h
@@ -303,7 +303,9 @@ extern int target_flags;
 #define TARGET_C40		(target_flags & C40_FLAG)
 #define TARGET_C44		(target_flags & C44_FLAG)
 
+/* Define some options to control code generation.  */
 #define TARGET_LOAD_ADDRESS	(1 || (! TARGET_C3X && ! TARGET_SMALL))
+#define TARGET_EXPOSE_LDP	0
 
 /* -mrpts            allows the use of the RPTS instruction irregardless.
    -mrpts=max-cycles will use RPTS if the number of cycles is constant
@@ -1664,6 +1666,20 @@ extern struct rtx_def *c4x_legitimize_address ();
   }									\
 }
 
+extern struct rtx_def *c4x_legitimize_reload_address ();
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)     \
+{									\
+  rtx new;								\
+  new = c4x_legitimize_reload_address (X, MODE, insn);			\
+  if (new != NULL_RTX)							\
+  {									\
+    (X) = new;								\
+   /* We do not have to call push_reload because we do not require      \
+      any more reloads.  */						\
+    goto WIN;								\
+  }									\
+}
+
 
 /* No mode-dependent addresses on the C4x are autoincrements.  */
 
@@ -1684,7 +1700,9 @@ extern struct rtx_def *c4x_legitimize_address ();
    restricted subset of CONST_INT and CONST_DOUBLE.  Disallow
    LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
    model) so that the symbols will be forced into the constant pool.
-   On second thoughts, lets do this with the move expanders.
+   On second thoughts, let's do this with the move expanders since
+   the alias analysis has trouble if we force constant addresses
+   into memory.
 */
 
 #define LEGITIMATE_CONSTANT_P(X)				\
@@ -2078,7 +2096,7 @@ dtors_section ()							\
     fprintf (FILE, "\n");					\
 }
 
-#define ASM_FILE_END(FILE)   fprintf (FILE, "\t.end\n")
+#define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n")
 
 /* We need to have a data section we can identify so that we can set
    the DP register back to a data pointer in the small memory model.
@@ -2089,7 +2107,7 @@ dtors_section ()							\
     if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE);	\
       fputs ("\t.data\ndata_sec:\n", FILE);
 
-#define ASM_COMMENT_START	";"
+#define ASM_COMMENT_START ";"
 
 #define ASM_APP_ON ""
 #define ASM_APP_OFF ""
@@ -2248,8 +2266,10 @@ asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
 
 #define CPP_PREDEFINES ""
 
-/* This says how to output an assembler line
-   to define a local common symbol.  */
+/* Output of Uninitialized Variables  */
+
+/* This says how to output an assembler line to define a local
+   uninitialized variable.  */
 
 #undef ASM_OUTPUT_LOCAL
 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
@@ -2257,7 +2277,8 @@ asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
   assemble_name (FILE, (NAME)),		\
   fprintf (FILE, ",%u\n", (ROUNDED)))
 
-/* Output of Uninitialized Variables  */
+/* This says how to output an assembler line to define a global
+   uninitialized variable.  */
 
 #undef ASM_OUTPUT_COMMON
 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
diff --git a/gnu/egcs/gcc/config/c4x/c4x.md b/gnu/egcs/gcc/config/c4x/c4x.md
index a0a4e0b9dd9..7f1b0f309ab 100644
--- a/gnu/egcs/gcc/config/c4x/c4x.md
+++ b/gnu/egcs/gcc/config/c4x/c4x.md
@@ -68,6 +68,8 @@
 ; src_operand           general operand                            [rfHmI]
 ; par_ind_operand       indirect S mode (ARx + 0, 1, IRx)          [S<>]
 ; parallel_operand      par_ind_operand or ext_low_reg_operand
+; symbolic_address_operand
+; call_address_operand
 
 ; ADDI src2, src1, dst  three operand op
 ; ADDI src, dst         two operand op
@@ -1141,7 +1143,6 @@
    operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
 }")
 
-; This pattern is required to handle the case where a register that clobbers
 ; CC has been selected to load a symbolic address.  We force the address
 ; into memory and then generate LDP and LDIU insns.
 ; This is also required for the C30 if we pretend that we can 
diff --git a/gnu/egcs/gcc/config/i386/cygwin.h b/gnu/egcs/gcc/config/i386/cygwin.h
index 48b9eba1b1c..dbea466bc86 100644
--- a/gnu/egcs/gcc/config/i386/cygwin.h
+++ b/gnu/egcs/gcc/config/i386/cygwin.h
@@ -326,11 +326,7 @@ do {									\
 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED)	\
 do {							\
   if (i386_pe_dllexport_name_p (NAME))			\
-    {							\
-      drectve_section ();				\
-      fprintf ((STREAM), "\t.ascii \" -export:%s\"\n",	\
-               I386_PE_STRIP_ENCODING (NAME));		\
-    }							\
+    i386_pe_record_exported_symbol (NAME);		\
   if (! i386_pe_dllimport_name_p (NAME))		\
     {							\
       fprintf ((STREAM), "\t.comm\t"); 			\
@@ -345,13 +341,7 @@ do {							\
 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) 	\
 do {							\
   if (i386_pe_dllexport_name_p (NAME))			\
-    {							\
-      enum in_section save_section = in_section;	\
-      drectve_section ();				\
-      fprintf ((STREAM), "\t.ascii \" -export:%s\"\n",	\
-               I386_PE_STRIP_ENCODING (NAME));		\
-      switch_to_section (save_section, (DECL));		\
-    }							\
+    i386_pe_record_exported_symbol (NAME);		\
   ASM_OUTPUT_LABEL ((STREAM), (NAME));			\
 } while (0)
 
@@ -447,12 +437,7 @@ do {									\
   do									\
     {									\
       if (i386_pe_dllexport_name_p (NAME))				\
-	{								\
-	  drectve_section ();						\
-	  fprintf ((FILE), "\t.ascii \" -export:%s\"\n", 		\
-		   I386_PE_STRIP_ENCODING (NAME));			\
-	  function_section (DECL);					\
-	}								\
+	i386_pe_record_exported_symbol (NAME);				\
       if (write_symbols != SDB_DEBUG)					\
 	i386_pe_declare_function_type (FILE, NAME, TREE_PUBLIC (DECL));	\
       ASM_OUTPUT_LABEL (FILE, NAME);					\
@@ -518,6 +503,7 @@ do {									\
 
 extern void i386_pe_record_external_function PROTO((char *));
 extern void i386_pe_declare_function_type STDIO_PROTO((FILE *, char *, int));
+extern void i386_pe_record_exported_symbol PROTO((char *));
 extern void i386_pe_asm_file_end STDIO_PROTO((FILE *));
 
 /* For Win32 ABI compatibility */
@@ -532,3 +518,8 @@ extern void i386_pe_asm_file_end STDIO_PROTO((FILE *));
 #undef PCC_BITFIELDS_TYPE_MATTERS
 #define PCC_BITFIELDS_TYPE_MATTERS 0
 
+/* Enable alias attribute support.  */
+#ifndef SET_ASM_OP
+#define SET_ASM_OP "\t.set"
+#endif
+
diff --git a/gnu/egcs/gcc/config/i386/djgpp.h b/gnu/egcs/gcc/config/i386/djgpp.h
index 6cee75bc837..5727b0a9bbd 100644
--- a/gnu/egcs/gcc/config/i386/djgpp.h
+++ b/gnu/egcs/gcc/config/i386/djgpp.h
@@ -70,7 +70,15 @@ Boston, MA 02111-1307, USA.  */
 \t%{!A:%{!nostdlib:%{!nostartfiles:%E}}}\
 \t-Tdjgpp.djl %{T*}}}}}}}\n\
 %{!c:%{!M:%{!MM:%{!E:%{!S:stubify %{v} %{o*:%*} %{!o*:a.out} }}}}}"
- 
+
+/* Always just link in 'libc.a'.  */
+#undef LIB_SPEC
+#define LIB_SPEC "-lc"
+
+/* Pick the right startup code depending on the -pg flag.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s}"
+
 /* Make sure that gcc will not look for .h files in /usr/local/include 
    unless user explicitly requests it.  */
 #undef LOCAL_INCLUDE_DIR
diff --git a/gnu/egcs/gcc/config/i386/freebsd-elf.h b/gnu/egcs/gcc/config/i386/freebsd-elf.h
index c74ae992efc..e97d4ca07bb 100644
--- a/gnu/egcs/gcc/config/i386/freebsd-elf.h
+++ b/gnu/egcs/gcc/config/i386/freebsd-elf.h
@@ -135,23 +135,15 @@ Boston, MA 02111-1307, USA.  */
  : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
  : (-1))
 
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
+/* Tell final.c that we don't need a label passed to mcount.  */
 
 #undef FUNCTION_PROFILER
 #define FUNCTION_PROFILER(FILE, LABELNO)  \
 {									\
   if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
+      fprintf (FILE, "\tcall *.mcount@GOT(%%ebx)\n");			\
   else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
+      fprintf (FILE, "\tcall .mcount\n");				\
 }
 
 #undef SIZE_TYPE
@@ -210,22 +202,18 @@ Boston, MA 02111-1307, USA.  */
 #define ENDFILE_SPEC \
   "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
 
+/* Provide a LIB_SPEC appropriate for FreeBSD.  Just select the appropriate
+   libc, depending on whether we're doing profiling or need threads support.
+   (simular to the default, except no -lg, and no -p.  */
 
-#undef	LIB_SPEC
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
- * want to profile or debug the C library, please add
- * -lc_p or -ggdb to LDFLAGS at the link time, respectively.
- */
-#define LIB_SPEC \
-  "%{!shared: %{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} \
-     %{!ggdb:-lc} %{ggdb:-lg}}"
-#else
-#define LIB_SPEC \
-  "%{!shared: \
-     %{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
-       %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}"
-#endif
+#undef LIB_SPEC
+#define LIB_SPEC "%{!shared: \
+   %{!pg:%{!pthread:%{!kthread:-lc} \
+     %{kthread:-lpthread -lc}} \
+     %{pthread:-lc_r}} \
+   %{pg:%{!pthread:%{!kthread:-lc_p} \
+     %{kthread:-lpthread_p -lc_p}} \
+     %{pthread:-lc_r_p}}}"
 
 /* Provide a LINK_SPEC appropriate for FreeBSD.  Here we provide support
    for the special GCC options -static and -shared, which allow us to
@@ -242,13 +230,17 @@ Boston, MA 02111-1307, USA.  */
    done.  */
 
 #undef	LINK_SPEC
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
+#define LINK_SPEC "-m elf_i386 \
+  %{Wl,*:%*} \
+  %{v:-V} \
+  %{assert*} %{R*} %{rpath*} %{defsym*} \
+  %{shared:-Bshareable %{h*} %{soname*}} \
+    %{!shared: \
       %{!static: \
-	%{rdynamic:-export-dynamic} \
+        %{rdynamic:-export-dynamic} \
 	%{!dynamic-linker:-dynamic-linker /usr/libexec/ld-elf.so.1}} \
-	%{static:-Bstatic}}}"
+    %{static:-Bstatic}} \
+  %{symbolic:-Bsymbolic}"
 
 /* A C statement to output to the stdio stream FILE an assembler
    command to advance the location counter to a multiple of 1<<LOG
diff --git a/gnu/egcs/gcc/config/i386/uwin.h b/gnu/egcs/gcc/config/i386/uwin.h
index 0d5019d5b04..73e04add2e9 100644
--- a/gnu/egcs/gcc/config/i386/uwin.h
+++ b/gnu/egcs/gcc/config/i386/uwin.h
@@ -44,7 +44,7 @@ Boston, MA 02111-1307, USA. */
 #undef CPP_SPEC
 #define CPP_SPEC "-remap %(cpp_cpu) %{posix:-D_POSIX_SOURCE} \
   -include /usr/include/astwin32.h \
-  -iprefix /usr/gnu/include -iwithprefix /mingw32"
+  -idirafter /usr/gnu/include/mingw32"
 
 /* For Windows applications, include more libraries, but always include
    kernel32.  */
diff --git a/gnu/egcs/gcc/config/i386/winnt.c b/gnu/egcs/gcc/config/i386/winnt.c
index f1a2d4b83be..24d8617f8df 100644
--- a/gnu/egcs/gcc/config/i386/winnt.c
+++ b/gnu/egcs/gcc/config/i386/winnt.c
@@ -545,8 +545,29 @@ i386_pe_record_external_function (name)
   extern_head = p;
 }
 
+static struct extern_list *exports_head;
+
+/* Assemble an export symbol entry.  We need to keep a list of
+   these, so that we can output the export list at the end of the
+   assembly.  We used to output these export symbols in each function,
+   but that causes problems with GNU ld when the sections are 
+   linkonce.  */
+
+void
+i386_pe_record_exported_symbol (name)
+     char *name;
+{
+  struct extern_list *p;
+
+  p = (struct extern_list *) permalloc (sizeof *p);
+  p->next = exports_head;
+  p->name = name;
+  exports_head = p;
+}
+
 /* This is called at the end of assembly.  For each external function
-   which has not been defined, we output a declaration now.  */
+   which has not been defined, we output a declaration now.  We also
+   output the .drectve section.  */
 
 void
 i386_pe_asm_file_end (file)
@@ -567,4 +588,13 @@ i386_pe_asm_file_end (file)
 	  i386_pe_declare_function_type (file, p->name, TREE_PUBLIC (decl));
 	}
     }
+
+  if (exports_head)
+    drectve_section ();
+  for (p = exports_head; p != NULL; p = p->next)
+    {
+      fprintf (file, "\t.ascii \" -export:%s\"\n",
+               I386_PE_STRIP_ENCODING (p->name));
+    }
 }
+
diff --git a/gnu/egcs/gcc/config/i386/xm-djgpp.h b/gnu/egcs/gcc/config/i386/xm-djgpp.h
index 50034fd071d..ccf6e3cedf6 100644
--- a/gnu/egcs/gcc/config/i386/xm-djgpp.h
+++ b/gnu/egcs/gcc/config/i386/xm-djgpp.h
@@ -34,8 +34,6 @@ Boston, MA 02111-1307, USA.  */
 /* Allow test for DOS drive names.  */
 #define HAVE_DOS_BASED_FILESYSTEM
 
-#define NO_SYS_SIGLIST 1
-
 #define LIBSTDCXX "-lstdcxx"
 
 /* System dependant initialization for collect2
diff --git a/gnu/egcs/gcc/config/mips/mips.md b/gnu/egcs/gcc/config/mips/mips.md
index 6dde18bf372..81c5cd38e38 100644
--- a/gnu/egcs/gcc/config/mips/mips.md
+++ b/gnu/egcs/gcc/config/mips/mips.md
@@ -10416,3 +10416,27 @@ move\\t%0,%z4\\n\\
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"2")])
+
+;; For the rare case where we need to load an address into a register
+;; that can not be recognized by the normal movsi/addsi instructions.
+;; I have no idea how many insns this can actually generate.  It should
+;; be rare, so over-estimating as 10 instructions should not have any
+;; real performance impact.
+(define_insn "leasi"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (match_operand:SI 1 "address_operand" "p"))]
+  "Pmode == SImode"
+  "la %0,%a1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"10")])
+
+;; Similarly for targets where we have 64bit pointers.
+(define_insn "leadi"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (match_operand:DI 1 "address_operand" "p"))]
+  "Pmode == DImode"
+  "la %0,%a1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"10")])
diff --git a/gnu/egcs/gcc/config/rs6000/rs6000.md b/gnu/egcs/gcc/config/rs6000/rs6000.md
index 34ccacf9c2d..c2749f8222f 100644
--- a/gnu/egcs/gcc/config/rs6000/rs6000.md
+++ b/gnu/egcs/gcc/config/rs6000/rs6000.md
@@ -4079,7 +4079,7 @@
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))
 	      (clobber (reg:DF 76))])]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "
 {
   operands[2] = force_reg (SImode, GEN_INT (0x43300000));
@@ -4096,7 +4096,7 @@
    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
    (clobber (match_operand 5 "gpc_reg_operand" "=b"))
    (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "#"
   [(set_attr "length" "24")])
 
@@ -4108,7 +4108,7 @@
    (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
    (clobber (match_operand 5 "gpc_reg_operand" ""))
    (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   [(set (match_dup 4)
 	(xor:SI (match_dup 1)
 		(match_dup 6)))
@@ -4140,7 +4140,7 @@
 	      (use (match_dup 3))
 	      (clobber (match_dup 4))
 	      (clobber (reg:DF 76))])]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "
 {
   operands[2] = force_reg (SImode, GEN_INT (0x43300000));
@@ -4155,7 +4155,7 @@
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))
    (clobber (match_operand 4 "gpc_reg_operand" "=b"))
    (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "#"
   [(set_attr "length" "20")])
 
@@ -4166,7 +4166,7 @@
    (use (match_operand:DF 3 "gpc_reg_operand" ""))
    (clobber (match_operand 4 "gpc_reg_operand" ""))
    (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
+  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   [(set (match_dup 4)
 	(unspec [(const_int 0)] 11))
    (set (match_dup 5)
@@ -4294,7 +4294,7 @@
   "TARGET_HARD_FLOAT"
   "
 {
-  if (!TARGET_POWER2 && !TARGET_POWERPC)
+  if (! TARGET_POWER2 && ! TARGET_POWERPC)
     {
       emit_insn (gen_trunc_call (operands[0], operands[1],
 				 gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC)));
@@ -4323,8 +4323,8 @@
    (clobber (match_operand 3 "gpc_reg_operand" ""))
    (clobber (reg:DI 76))]
   "TARGET_HARD_FLOAT"
-  [(set (match_dup 2)
-	(sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
+  [(set (subreg:SI (match_dup 2) 0)
+	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
    (set (match_dup 3)
 	(unspec [(const_int 0)] 11))
    (set (match_dup 4)
@@ -4433,8 +4433,8 @@
 }")
 
 (define_insn "*fctiwz"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
-	(sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
+  [(set (subreg:SI (match_operand:DI 0 "gpc_reg_operand" "=f") 0)
+	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))]
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
   "{fcirz|fctiwz} %0,%1"
   [(set_attr "type" "fp")])
@@ -5809,21 +5809,6 @@
   "{l|lwz} %0,%a1@got(%2)"
   [(set_attr "type" "load")])
 
-;; Sometimes, though, the GOT `register' will be on the stack. Deal with
-;; this case specially.
-;; Force final to split this insn (if it hasn't been split already) to
-;; avoid having to create a suitable output template.
-(define_insn "*movsi_got_internal_mem"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unspec [(match_operand:SI 1 "got_no_const_operand" "")
-		 (match_operand:SI 2 "memory_operand" "m")] 8))]
-  "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    && flag_pic == 1
-    && (reload_in_progress || reload_completed)"
-  "#"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
 ;; didn't get allocated to a hard register.
 (define_split 
@@ -6322,8 +6307,8 @@
 ;; The "??" is a kludge until we can figure out a more reasonable way
 ;; of handling these non-offsettable values.
 (define_insn "*movdf_hardfloat32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
+	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
    && (gpc_reg_operand (operands[0], DFmode)
        || gpc_reg_operand (operands[1], DFmode))"
@@ -6335,24 +6320,74 @@
       abort ();
     case 0:
       /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
+	 the first register operand 0 is the same as the second register
+	 of operand 1, we must copy in the opposite order.  */
       if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
 	return \"mr %L0,%L1\;mr %0,%1\";
       else
 	return \"mr %0,%1\;mr %L0,%L1\";
     case 1:
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
+      if (offsettable_memref_p (operands[1])
+	  || (GET_CODE (operands[1]) == MEM
+	      && GET_CODE (XEXP (operands[1], 0)) == LO_SUM))
+	{
+	  /* If the low-address word is used in the address, we must load
+	     it last.  Otherwise, load it first.  Note that we cannot have
+	     auto-increment in that case since the address register is
+	     known to be dead.  */
+	  if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+				 operands[1], 0))
+	    return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
+	  else
+	    return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
+	}
       else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
+	{
+	  rtx addreg;
+
+	  if (GET_CODE (XEXP (operands[1], 0)) == PRE_INC
+	      || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+	    abort ();
+
+	  addreg = find_addr_reg (XEXP (operands[1], 0));
+	  if (refers_to_regno_p (REGNO (operands[0]),
+				 REGNO (operands[0]) + 1,
+				 operands[1], 0))
+	    {
+	      output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
+	      output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
+	      output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
+	      return \"{lx|lwzx} %0,%1\";
+	    }
+	  else
+	    {
+	      output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
+	      output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
+	      output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
+	      output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
+	      return \"\";
+	    }
+	}
     case 2:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
+      if (offsettable_memref_p (operands[0])
+	  || (GET_CODE (operands[0]) == MEM
+	      && GET_CODE (XEXP (operands[0], 0)) == LO_SUM))
+	return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
+      else
+	{
+	  rtx addreg;
+
+	  if (GET_CODE (XEXP (operands[0], 0)) == PRE_INC
+	      || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+	    abort ();
+
+	  addreg = find_addr_reg (XEXP (operands[0], 0));
+	  output_asm_insn (\"{stx|stwx} %1,%0\", operands);
+	  output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
+	  output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
+	  output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
+	  return \"\";
+	}
     case 3:
     case 4:
     case 5:
@@ -6366,7 +6401,7 @@
     }
 }"
   [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
-   (set_attr "length" "8,8,8,8,12,16,*,*,*")])
+   (set_attr "length" "8,16,16,8,12,16,*,*,*")])
 
 (define_insn "*movdf_softfloat32"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
@@ -9116,7 +9151,7 @@
 	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		     (const_int 31)))
    (clobber (match_scratch:SI 2 "=&r"))]
-  "!TARGET_POWER"
+  "! TARGET_POWER"
   "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
   [(set_attr "length" "8")])
 
diff --git a/gnu/egcs/gcc/config/sparc/pbd.h b/gnu/egcs/gcc/config/sparc/pbd.h
index 459bffd901b..b70fdcb259b 100644
--- a/gnu/egcs/gcc/config/sparc/pbd.h
+++ b/gnu/egcs/gcc/config/sparc/pbd.h
@@ -144,35 +144,7 @@ Boston, MA 02111-1307, USA.  */
 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
   fprintf (FILE, "\t.word .L%d\n", VALUE)
 
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(.LP%d),%%o0\n\tcall mcount\n\tor %%lo(.LP%d),%%o0,%%o0\n", \
-	   (LABELNO), (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#undef FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(.LPBX0),%%o0\n\tld [%%lo(.LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne .LPY%d\n\tnop\n\tcall ___bb_init_func\n\tnop\n.LPY%d:\n",  \
-	   (LABELNO), (LABELNO))
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#undef BLOCK_PROFILER
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{								\
-  int blockn = (BLOCKNO);					\
-  fprintf (FILE, "\tsethi %%hi(.LPBX2+%d),%%g1\n\tld [%%lo(.LPBX2+%d)+%%g1],%%g2\n\
-\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LPBX2+%d)+%%g1]\n",		\
-	   4 * blockn, 4 * blockn, 4 * blockn);			\
-  CC_STATUS_INIT;  /* We have clobbered %g1.  Also %g2.  */	\
-}
-/*   This is needed for SunOS 4.0, and should not hurt for 3.2
+/* This is needed for SunOS 4.0, and should not hurt for 3.2
    versions either.  */
 #undef ASM_OUTPUT_SOURCE_LINE(file, line) 
 #define ASM_OUTPUT_SOURCE_LINE(file, line)		\
diff --git a/gnu/egcs/gcc/config/sparc/sun4o3.h b/gnu/egcs/gcc/config/sparc/sun4o3.h
index 10c73916b60..d2a53c1f237 100644
--- a/gnu/egcs/gcc/config/sparc/sun4o3.h
+++ b/gnu/egcs/gcc/config/sparc/sun4o3.h
@@ -1,9 +1,9 @@
 #include "sparc/sparc.h"
 
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall .mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
-	   (LABELNO), (LABELNO))
+/* Override the name of the mcount profiling function.  */
+
+#undef MCOUNT_FUNCTION
+#define MCOUNT_FUNCTION "*.mcount"
 
 /* LINK_SPEC is needed only for SunOS 4.  */
 
diff --git a/gnu/egcs/gcc/config/sparc/sysv4.h b/gnu/egcs/gcc/config/sparc/sysv4.h
index 572b9dcde73..5f9bba9e594 100644
--- a/gnu/egcs/gcc/config/sparc/sysv4.h
+++ b/gnu/egcs/gcc/config/sparc/sysv4.h
@@ -200,28 +200,6 @@ do {									\
   else									\
     fprintf (FILE, ".section\t\"%s\",#alloc,#write\n", (NAME));		\
 } while (0)
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#undef FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  do { \
-    fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
-	     (LABELNO), (LABELNO)); \
-  } while (0)
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#undef BLOCK_PROFILER
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{ \
-  int blockn = (BLOCKNO); \
-  fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
-\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LLPBX2+%d)+%%g1]\n", \
-	   4 * blockn, 4 * blockn, 4 * blockn); \
-}
 
 /* A C statement (sans semicolon) to output to the stdio stream
    FILE the assembler definition of uninitialized global DECL named
@@ -231,3 +209,8 @@ do {									\
 #undef ASM_OUTPUT_ALIGNED_BSS
 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
+
+/* Override the name of the mcount profiling function.  */
+
+#undef MCOUNT_FUNCTION
+#define MCOUNT_FUNCTION "*_mcount"
diff --git a/gnu/egcs/gcc/config/svr4.h b/gnu/egcs/gcc/config/svr4.h
index 1c8482fd11d..7fa30e8ac26 100644
--- a/gnu/egcs/gcc/config/svr4.h
+++ b/gnu/egcs/gcc/config/svr4.h
@@ -247,8 +247,9 @@ do {				 				\
 #define DWARF_DEBUGGING_INFO
 
 /* All ELF targets can support DWARF-2.  */
-
+#ifndef DWARF2_DEBUGGING_INFO
 #define DWARF2_DEBUGGING_INFO
+#endif
 
 /* The numbers used to denote specific machine registers in the System V
    Release 4 DWARF debugging information are quite likely to be totally