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author	Marc Espie <espie@cvs.openbsd.org>	2000-01-19 16:07:14 +0000
committer	Marc Espie <espie@cvs.openbsd.org>	2000-01-19 16:07:14 +0000
commit	df2a34902b4aa73b54581f227c58a3ca95b37318 (patch)
tree	4aa817c78f627be1c77651c0fd6f13c2241e6c56 /gnu/egcs/gcc
parent	fab44a305f0ce081ffdf8c9602e66898ebc805b0 (diff)

Update to 2.95.2

Diffstat (limited to 'gnu/egcs/gcc')

-rw-r--r--

gnu/egcs/gcc/c-lang.c

-rw-r--r--

gnu/egcs/gcc/config/arm/linux-elf.h

-rw-r--r--

gnu/egcs/gcc/config/i386/sol2.h

-rw-r--r--

gnu/egcs/gcc/config/i386/sol2gas.h

-rw-r--r--

gnu/egcs/gcc/config/pa/pa.c

-rw-r--r--

gnu/egcs/gcc/config/rs6000/rs6000.md

339

-rw-r--r--

gnu/egcs/gcc/config/sparc/sparc.md

-rw-r--r--

gnu/egcs/gcc/cp/ChangeLog

-rw-r--r--

gnu/egcs/gcc/f/ChangeLog

-rw-r--r--

gnu/egcs/gcc/f/version.c

-rw-r--r--

gnu/egcs/gcc/fix-header.c

-rw-r--r--

gnu/egcs/gcc/haifa-sched.c

-rw-r--r--

gnu/egcs/gcc/intl/ChangeLog

-rw-r--r--

gnu/egcs/gcc/java/ChangeLog

-rw-r--r--

gnu/egcs/gcc/java/jvspec.c

-rw-r--r--

gnu/egcs/gcc/local-alloc.c

-rw-r--r--

gnu/egcs/gcc/po/ChangeLog

-rw-r--r--

gnu/egcs/gcc/po/POTFILES.in

-rw-r--r--

gnu/egcs/gcc/reg-stack.c

-rw-r--r--

gnu/egcs/gcc/sched.c

20 files changed, 421 insertions, 65 deletions

diff --git a/gnu/egcs/gcc/c-lang.c b/gnu/egcs/gcc/c-lang.c
index 4c554115b7c..7da67986af1 100644
--- a/gnu/egcs/gcc/c-lang.c
+++ b/gnu/egcs/gcc/c-lang.c

@@ -175,7 +175,9 @@ finish_file ()

{

tree fnname = get_file_function_name ('I');

start_function (void_list_node,

- build_parse_node (CALL_EXPR, fnname, void_list_node,

+ build_parse_node (CALL_EXPR, fnname,

+ tree_cons (NULL_TREE, NULL_TREE,

+ void_list_node),

NULL_TREE),

NULL_TREE, NULL_TREE, 0);

fnname = DECL_ASSEMBLER_NAME (current_function_decl);

@@ -195,7 +197,9 @@ finish_file ()

{

tree fnname = get_file_function_name ('D');

start_function (void_list_node,

- build_parse_node (CALL_EXPR, fnname, void_list_node,

+ build_parse_node (CALL_EXPR, fnname,

+ tree_cons (NULL_TREE, NULL_TREE,

+ void_list_node),

NULL_TREE),

NULL_TREE, NULL_TREE, 0);

fnname = DECL_ASSEMBLER_NAME (current_function_decl);

diff --git a/gnu/egcs/gcc/config/arm/linux-elf.h b/gnu/egcs/gcc/config/arm/linux-elf.h
index de45e1c4b53..e5b4de1c13b 100644
--- a/gnu/egcs/gcc/config/arm/linux-elf.h
+++ b/gnu/egcs/gcc/config/arm/linux-elf.h

@@ -22,6 +22,9 @@ Boston, MA 02111-1307, USA. */

/* Run-time Target Specification. */

#define TARGET_VERSION fputs (" (ARM GNU/Linux with ELF)", stderr);

+/* Do not assume anything about header files. */

+#define NO_IMPLICIT_EXTERN_C

/* We have libgcc2. */

#define HAVE_ATEXIT

diff --git a/gnu/egcs/gcc/config/i386/sol2.h b/gnu/egcs/gcc/config/i386/sol2.h
index cc5a089229f..b254a10f2ea 100644
--- a/gnu/egcs/gcc/config/i386/sol2.h
+++ b/gnu/egcs/gcc/config/i386/sol2.h

@@ -21,6 +21,33 @@ Boston, MA 02111-1307, USA. */

#include "i386/sysv4.h"

+/* We use stabs-in-elf for debugging, because that is what the native

+ toolchain uses. */

+#undef PREFERRED_DEBUGGING_TYPE

+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG

+#if ! GAS_REJECTS_MINUS_S

+/*

+ Changed from config/svr4.h in the following ways:

+ - Removed -Yd (neither the sun bundled assembler nor gas accept it).

+ - Added "-s" so that stabs are not discarded.

+*/

+#undef ASM_SPEC

+#define ASM_SPEC \

+ "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s"

+#else /* GAS_REJECTS_MINUS_S */

+/* Same as above, except for -s, unsupported by GNU as. */

+#undef ASM_SPEC

+#define ASM_SPEC \

+ "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*}"

+#endif /* GAS_REJECTS_MINUS_S */

/* The Solaris 2.0 x86 linker botches alignment of code sections.

It tries to align to a 16 byte boundary by padding with 0x00000090

ints, rather than 0x90 bytes (nop). This generates trash in the

diff --git a/gnu/egcs/gcc/config/i386/sol2gas.h b/gnu/egcs/gcc/config/i386/sol2gas.h
new file mode 100644
index 00000000000..7f2c9629d7c
--- /dev/null
+++ b/gnu/egcs/gcc/config/i386/sol2gas.h

@@ -0,0 +1,11 @@

+/* Definitions of target machine for GNU compiler, for SPARC running

+ Solaris 2 with GNU as up to 2.9.5.0.12.

+*/

+#ifndef GAS_DOES_NOT_SUPPORT_MINUS_S

+#define GAS_DOES_NOT_SUPPORT_MINUS_S 1

+#endif

+#include "i386/sol2.h"

diff --git a/gnu/egcs/gcc/config/pa/pa.c b/gnu/egcs/gcc/config/pa/pa.c
index fa1287e55e5..66ea980492d 100644
--- a/gnu/egcs/gcc/config/pa/pa.c
+++ b/gnu/egcs/gcc/config/pa/pa.c

@@ -1129,8 +1129,12 @@ emit_move_sequence (operands, mode, scratch_reg)

&& GET_CODE (SUBREG_REG (operand0)) == REG

&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)

{

- SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];

- operand0 = alter_subreg (operand0);

+ /* We must not alter SUBREG_WORD (operand0) since that would confuse

+ the code which tracks sets/uses for delete_output_reload. */

+ rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),

+ reg_equiv_mem [REGNO (SUBREG_REG (operand0))],

+ SUBREG_WORD (operand0));

+ operand0 = alter_subreg (temp);

}

if (scratch_reg

@@ -1142,8 +1146,12 @@ emit_move_sequence (operands, mode, scratch_reg)

&& GET_CODE (SUBREG_REG (operand1)) == REG

&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)

{

- SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];

- operand1 = alter_subreg (operand1);

+ /* We must not alter SUBREG_WORD (operand0) since that would confuse

+ the code which tracks sets/uses for delete_output_reload. */

+ rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),

+ reg_equiv_mem [REGNO (SUBREG_REG (operand1))],

+ SUBREG_WORD (operand1));

+ operand1 = alter_subreg (temp);

}

if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM

diff --git a/gnu/egcs/gcc/config/rs6000/rs6000.md b/gnu/egcs/gcc/config/rs6000/rs6000.md
index bb23a1a32a2..9b3c4306f77 100644
--- a/gnu/egcs/gcc/config/rs6000/rs6000.md
+++ b/gnu/egcs/gcc/config/rs6000/rs6000.md

@@ -4335,7 +4335,8 @@

(clobber (match_operand 3 "gpc_reg_operand" ""))

(clobber (reg:DI 76))]

"TARGET_HARD_FLOAT"

- [(set (subreg:SI (match_dup 2) 0)

+ [(clobber (match_dup 2))

+ (set (subreg:SI (match_dup 2) 0)

(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))

(set (match_dup 3)

(unspec [(const_int 0)] 11))

@@ -9009,7 +9010,7 @@

(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")

(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))

(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]

- ""

+ "! TARGET_POWERPC64"

xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0

{sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1

@@ -9041,7 +9042,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")

(eq:SI (match_dup 1) (match_dup 2)))

(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]

- ""

+ "! TARGET_POWERPC64"

xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0

{sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1

@@ -9091,7 +9092,7 @@

(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))

(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))

(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3

{sfi|subfic} %4,%1,0\;{aze|addze} %0,%3

@@ -9109,7 +9110,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3

{sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3

@@ -9130,7 +9131,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")

(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3

{sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3

@@ -9144,7 +9145,7 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")

(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")

(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]

- ""

+ "! TARGET_POWERPC64"

xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0

{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0

@@ -9181,7 +9182,7 @@

(const_int 31))

(match_operand:SI 2 "gpc_reg_operand" "r")))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"

[(set_attr "length" "8")])

@@ -9205,7 +9206,7 @@

(match_operand:SI 2 "gpc_reg_operand" "r"))

(const_int 0)))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"

[(set_attr "type" "compare")

(set_attr "length" "8")])

@@ -9236,7 +9237,7 @@

(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))

(match_dup 2)))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"

[(set_attr "type" "compare")

(set_attr "length" "8")])

@@ -9343,11 +9344,32 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "rI")))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI")))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"

+ [(set_attr "length" "12")])

+(define_insn ""

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

+ (compare:CC

+ (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (leu:DI (match_dup 1) (match_dup 2)))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 3 "cc_reg_operand" "=x")

(compare:CC

(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

@@ -9355,18 +9377,31 @@

(const_int 0)))

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(leu:SI (match_dup 1) (match_dup 2)))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"

[(set_attr "type" "compare")

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

+ (compare:CC

+ (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (leu:DI (match_dup 1) (match_dup 2)))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "rI"))

(match_operand:SI 3 "gpc_reg_operand" "r")))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"

[(set_attr "length" "8")])

@@ -9378,7 +9413,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"

[(set_attr "type" "compare")

(set_attr "length" "8")])

@@ -9393,7 +9428,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"

[(set_attr "type" "compare")

(set_attr "length" "8")])

@@ -9402,7 +9437,7 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "rI"))))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"

[(set_attr "length" "12")])

@@ -9413,7 +9448,7 @@

(match_operand:SI 2 "reg_or_short_operand" "rI")))

(match_operand:SI 3 "gpc_reg_operand" "r")))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"

[(set_attr "length" "12")])

@@ -9426,7 +9461,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"

[(set_attr "type" "compare")

(set_attr "length" "12")])

@@ -9442,7 +9477,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"

[(set_attr "type" "compare")

(set_attr "length" "12")])

@@ -9518,7 +9553,7 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0

{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"

@@ -9532,7 +9567,7 @@

(const_int 0)))

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(ltu:SI (match_dup 1) (match_dup 2)))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0

{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"

@@ -9545,7 +9580,7 @@

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))

(match_operand:SI 3 "reg_or_short_operand" "rI,rI")))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"

@@ -9559,7 +9594,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r,r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"

@@ -9576,7 +9611,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"

@@ -9587,7 +9622,7 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0

{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"

@@ -9663,6 +9698,7 @@

[(set_attr "length" "12")])

;; This is (and (neg (ge X (const_int 0))) Y).

+;; srawi sign-extends, so these patterrns are 64-bit safe.

(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(and:SI (neg:SI

@@ -9676,6 +9712,18 @@

[(set_attr "length" "8")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (and:DI (neg:DI

+ (lshiftrt:DI

+ (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))

+ (const_int 63)))

+ (match_operand:DI 2 "gpc_reg_operand" "r")))

+ (clobber (match_scratch:DI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "sradi %3,%1,63\;andc %0,%2,%3"

+ [(set_attr "length" "8")])

+(define_insn ""

[(set (match_operand:CC 0 "cc_reg_operand" "=x")

(compare:CC

(and:SI (neg:SI

@@ -9691,6 +9739,21 @@

(set_attr "length" "8")])

(define_insn ""

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

+ (compare:CC

+ (and:DI (neg:DI

+ (lshiftrt:DI

+ (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))

+ (const_int 63)))

+ (match_operand:DI 2 "gpc_reg_operand" "r"))

+ (const_int 0)))

+ (clobber (match_scratch:DI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "sradi %3,%1,63\;andc. %3,%2,%3"

+ [(set_attr "type" "compare")

+ (set_attr "length" "8")])

+(define_insn ""

[(set (match_operand:CC 4 "cc_reg_operand" "=x")

(compare:CC

(and:SI (neg:SI

@@ -9710,16 +9773,45 @@

(set_attr "length" "8")])

(define_insn ""

+ [(set (match_operand:CC 4 "cc_reg_operand" "=x")

+ (compare:CC

+ (and:DI (neg:DI

+ (lshiftrt:DI

+ (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))

+ (const_int 63)))

+ (match_operand:DI 2 "gpc_reg_operand" "r"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))

+ (const_int 63)))

+ (match_dup 2)))

+ (clobber (match_scratch:SI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "sradi %3,%1,63\;andc. %0,%2,%3"

+ [(set_attr "type" "compare")

+ (set_attr "length" "8")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0

{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

+ (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]

+ "TARGET_POWERPC64"

+ "@

+ subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0

+ addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"

+ [(set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")

(compare:CC

(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

@@ -9727,7 +9819,7 @@

(const_int 0)))

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(geu:SI (match_dup 1) (match_dup 2)))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0

{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"

@@ -9735,12 +9827,27 @@

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")

+ (compare:CC

+ (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

+ (geu:DI (match_dup 1) (match_dup 2)))]

+ "TARGET_POWERPC64"

+ "@

+ subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0

+ addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))

(match_operand:SI 3 "gpc_reg_operand" "r,r")))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{aze|addze} %0,%3

{ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"

@@ -9754,7 +9861,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r,r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3

{ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"

@@ -9771,7 +9878,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3

{ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3"

@@ -9782,7 +9889,7 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0

{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"

@@ -9795,7 +9902,7 @@

(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))

(match_operand:SI 3 "gpc_reg_operand" "r,r")))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"

@@ -9810,7 +9917,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r,r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"

@@ -9828,7 +9935,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4

{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"

@@ -9839,11 +9946,19 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(const_int 0)))]

- ""

+ "! TARGET_POWERPC64"

"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0)))]

+ "TARGET_POWERPC64"

+ "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"

+ [(set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 2 "cc_reg_operand" "=x")

(compare:CC

(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

@@ -9851,12 +9966,25 @@

(const_int 0)))

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(gt:SI (match_dup 1) (const_int 0)))]

- ""

+ "! TARGET_POWERPC64"

"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"

[(set_attr "type" "delayed_compare")

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 2 "cc_reg_operand" "=x")

+ (compare:CC

+ (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (gt:DI (match_dup 1) (const_int 0)))]

+ "TARGET_POWERPC64"

+ "subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63"

+ [(set_attr "type" "delayed_compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "r")))]

@@ -9883,11 +10011,21 @@

(const_int 0))

(match_operand:SI 2 "gpc_reg_operand" "r")))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0))

+ (match_operand:DI 2 "gpc_reg_operand" "r")))

+ (clobber (match_scratch:DI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"

+ [(set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 0 "cc_reg_operand" "=x")

(compare:CC

(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

@@ -9895,12 +10033,25 @@

(match_operand:SI 2 "gpc_reg_operand" "r"))

(const_int 0)))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"

[(set_attr "type" "compare")

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")

+ (compare:CC

+ (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0))

+ (match_operand:DI 2 "gpc_reg_operand" "r"))

+ (const_int 0)))

+ (clobber (match_scratch:DI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 4 "cc_reg_operand" "=x")

(compare:CC

(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

@@ -9910,12 +10061,27 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))

(clobber (match_scratch:SI 3 "=&r"))]

- ""

+ "! TARGET_POWERPC64"

"{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"

[(set_attr "type" "compare")

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 4 "cc_reg_operand" "=x")

+ (compare:CC

+ (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0))

+ (match_operand:DI 2 "gpc_reg_operand" "r"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))

+ (clobber (match_scratch:DI 3 "=&r"))]

+ "TARGET_POWERPC64"

+ "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "r"))

@@ -9957,11 +10123,19 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(const_int 0))))]

- ""

+ "! TARGET_POWERPC64"

"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (const_int 0))))]

+ "TARGET_POWERPC64"

+ "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"

+ [(set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "r"))))]

@@ -9973,11 +10147,19 @@

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "rI")))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"

[(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI")))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"

+ [(set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:CC 3 "cc_reg_operand" "=x")

(compare:CC

(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

@@ -9985,24 +10167,49 @@

(const_int 0)))

(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(gtu:SI (match_dup 1) (match_dup 2)))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"

[(set_attr "type" "compare")

(set_attr "length" "12")])

(define_insn ""

+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")

+ (compare:CC

+ (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (gtu:DI (match_dup 1) (match_dup 2)))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0"

+ [(set_attr "type" "compare")

+ (set_attr "length" "12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

(match_operand:SI 2 "reg_or_short_operand" "I,rI"))

(match_operand:SI 3 "reg_or_short_operand" "r,rI")))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{ai|addic} %4,%1,%k2\;{aze|addze} %0,%3

{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"

[(set_attr "length" "8,12")])

(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

+ (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

+ (match_operand:DI 2 "reg_or_short_operand" "I,rI"))

+ (match_operand:DI 3 "reg_or_short_operand" "r,rI")))

+ (clobber (match_scratch:DI 4 "=&r,&r"))]

+ "TARGET_POWERPC64"

+ "@

+ addic %4,%1,%k2\;addze %0,%3

+ subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"

+ [(set_attr "length" "8,12")])

+(define_insn ""

[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")

(compare:CC

(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

@@ -10010,7 +10217,7 @@

(match_operand:SI 3 "gpc_reg_operand" "r,r"))

(const_int 0)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3

{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"

@@ -10018,6 +10225,21 @@

(set_attr "length" "8,12")])

(define_insn ""

+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")

+ (compare:CC

+ (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

+ (match_operand:DI 2 "reg_or_short_operand" "I,r"))

+ (match_operand:DI 3 "gpc_reg_operand" "r,r"))

+ (const_int 0)))

+ (clobber (match_scratch:DI 4 "=&r,&r"))]

+ "TARGET_POWERPC64"

+ "@

+ addic %4,%1,%k2\;addze. %4,%3

+ subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3"

+ [(set_attr "type" "compare")

+ (set_attr "length" "8,12")])

+(define_insn ""

[(set (match_operand:CC 5 "cc_reg_operand" "=x,x")

(compare:CC

(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")

@@ -10027,7 +10249,7 @@

(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")

(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))

(clobber (match_scratch:SI 4 "=&r,&r"))]

- ""

+ "! TARGET_POWERPC64"

{ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3

{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"

@@ -10035,12 +10257,37 @@

(set_attr "length" "8,12")])

(define_insn ""

+ [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")

+ (compare:CC

+ (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")

+ (match_operand:DI 2 "reg_or_short_operand" "I,r"))

+ (match_operand:DI 3 "gpc_reg_operand" "r,r"))

+ (const_int 0)))

+ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")

+ (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))

+ (clobber (match_scratch:DI 4 "=&r,&r"))]

+ "TARGET_POWERPC64"

+ "@

+ addic %4,%1,%k2\;addze. %0,%3

+ subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3"

+ [(set_attr "type" "compare")

+ (set_attr "length" "8,12")])

+(define_insn ""

[(set (match_operand:SI 0 "gpc_reg_operand" "=r")

(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")

(match_operand:SI 2 "reg_or_short_operand" "rI"))))]

- ""

+ "! TARGET_POWERPC64"

"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"

[(set_attr "length" "8")])

+(define_insn ""

+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")

+ (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")

+ (match_operand:DI 2 "reg_or_short_operand" "rI"))))]

+ "TARGET_POWERPC64"

+ "subf%I2c %0,%1,%2\;subfe %0,%0,%0"

+ [(set_attr "length" "8")])

;; Define both directions of branch and return. If we need a reload

;; register, we'd rather use CR0 since it is much easier to copy a

diff --git a/gnu/egcs/gcc/config/sparc/sparc.md b/gnu/egcs/gcc/config/sparc/sparc.md
index 02170b75fca..cb008b169b1 100644
--- a/gnu/egcs/gcc/config/sparc/sparc.md
+++ b/gnu/egcs/gcc/config/sparc/sparc.md

@@ -2838,7 +2838,7 @@

return \"#\";

[(set_attr "type" "move")

- (set_attr "length" "1")])

+ (set_attr "length" "1,2")])

;; There isn't much I can do about this, if I change the

;; mode then flow info gets really confused because the

@@ -3013,7 +3013,7 @@

return \"#\";

[(set_attr "type" "move")

- (set_attr "length" "1")])

+ (set_attr "length" "1,2,2")])

(define_split

[(set (match_operand:DF 0 "register_operand" "")

diff --git a/gnu/egcs/gcc/cp/ChangeLog b/gnu/egcs/gcc/cp/ChangeLog
index 82d1a8bc239..efa30edcad2 100644
--- a/gnu/egcs/gcc/cp/ChangeLog
+++ b/gnu/egcs/gcc/cp/ChangeLog

@@ -1,3 +1,24 @@

+Sun Oct 24 23:54:10 PDT 1999 Jeff Law (law@cygnus.com)

+ * gcc-2.95.2 Released.

+1999-09-06 Mark Mitchell <mark@codesourcery.com>

+ * pt.c (tsubst): Back out 1999-08-06 patch. Use fold and

+ decl_constant_value to simplify array bounds.

+1999-08-19 Jason Merrill <jason@yorick.cygnus.com>

+ * cp-tree.h: Declare flag_use_repository.

+ * pt.c (do_decl_instantiation): Don't complain about duplicate

+ instantiation with -frepo.

+ (do_type_instantiation): Likewise.

+1999-08-14 Jason Merrill <jason@yorick.cygnus.com>

+ * decl2.c (lookup_arg_dependent): Note that we've already checked

+ the current namespace.

Mon Aug 16 01:29:24 PDT 1999 Jeff Law (law@cygnus.com)

* gcc-2.95.1 Released.

diff --git a/gnu/egcs/gcc/f/ChangeLog b/gnu/egcs/gcc/f/ChangeLog
index a3755f4c2e1..2e818152ca1 100644
--- a/gnu/egcs/gcc/f/ChangeLog
+++ b/gnu/egcs/gcc/f/ChangeLog

@@ -1,3 +1,7 @@

+Sun Oct 24 23:54:10 PDT 1999 Jeff Law (law@cygnus.com)

+ * gcc-2.95.2 Released.

Mon Aug 16 01:29:24 PDT 1999 Jeff Law (law@cygnus.com)

* gcc-2.95.1 Released.

diff --git a/gnu/egcs/gcc/f/version.c b/gnu/egcs/gcc/f/version.c
index 97605df107c..5e8381f0fc4 100644
--- a/gnu/egcs/gcc/f/version.c
+++ b/gnu/egcs/gcc/f/version.c

@@ -1 +1 @@

-const char *ffe_version_string = "0.5.25 19990816 (release)";

+const char *ffe_version_string = "0.5.25 19991024 (release)";

diff --git a/gnu/egcs/gcc/fix-header.c b/gnu/egcs/gcc/fix-header.c
index af0577e43c4..1e6c5c47b8a 100644
--- a/gnu/egcs/gcc/fix-header.c
+++ b/gnu/egcs/gcc/fix-header.c

@@ -1140,7 +1140,7 @@ main (argc, argv)

if (entry->flags)

add_symbols (entry->flags, entry->names);

entry++;

- if (strcmp (entry->name, CONTINUED) != 0)

+ if (!entry->name || strcmp (entry->name, CONTINUED) != 0)

break;

}

diff --git a/gnu/egcs/gcc/haifa-sched.c b/gnu/egcs/gcc/haifa-sched.c
index d4d2121a9d5..42144769201 100644
--- a/gnu/egcs/gcc/haifa-sched.c
+++ b/gnu/egcs/gcc/haifa-sched.c

@@ -2849,7 +2849,7 @@ insn_unit (insn)

range, don't cache it. */

if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT

|| unit >= 0

- || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)

+ || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)

INSN_UNIT (insn) = unit;

}

return (unit > 0 ? unit - 1 : unit);

diff --git a/gnu/egcs/gcc/intl/ChangeLog b/gnu/egcs/gcc/intl/ChangeLog
index 4d91d013124..3938710c673 100644
--- a/gnu/egcs/gcc/intl/ChangeLog
+++ b/gnu/egcs/gcc/intl/ChangeLog

@@ -1,3 +1,7 @@

+Sun Oct 24 23:54:10 PDT 1999 Jeff Law (law@cygnus.com)

+ * gcc-2.95.2 Released.

Mon Aug 16 01:29:24 PDT 1999 Jeff Law (law@cygnus.com)

* gcc-2.95.1 Released.

diff --git a/gnu/egcs/gcc/java/ChangeLog b/gnu/egcs/gcc/java/ChangeLog
index c31058f1b53..8a7265e25b9 100644
--- a/gnu/egcs/gcc/java/ChangeLog
+++ b/gnu/egcs/gcc/java/ChangeLog

@@ -1,3 +1,12 @@

+Sun Oct 24 23:54:10 PDT 1999 Jeff Law (law@cygnus.com)

+ * gcc-2.95.2 Released.

+Sat Oct 16 15:18:42 1999 Jeffrey A Law (law@cygnus.com)

+ 1999-10-14 Tom Tromey <tromey@cygnus.com>

+ * jvspec.c (jvgenmain_spec): Use `%umain', not just `%u'.

Mon Aug 16 01:29:24 PDT 1999 Jeff Law (law@cygnus.com)

* gcc-2.95.1 Released.

diff --git a/gnu/egcs/gcc/java/jvspec.c b/gnu/egcs/gcc/java/jvspec.c
index eba801cb32a..61cd89b0d97 100644
--- a/gnu/egcs/gcc/java/jvspec.c
+++ b/gnu/egcs/gcc/java/jvspec.c

@@ -54,15 +54,15 @@ int lang_specific_extra_outfiles = 0;

#define COMBINE_INPUTS 0

char jvgenmain_spec[] =

- "jvgenmain %i %{!pipe:%u.i} |\n\

- cc1 %{!pipe:%U.i} %1 \

+ "jvgenmain %i %{!pipe:%umain.i} |\n\

+ cc1 %{!pipe:%Umain.i} %1 \

%{!Q:-quiet} -dumpbase %b.c %{d*} %{m*} %{a*}\

%{g*} %{O*} \

%{v:-version} %{pg:-p} %{p} %{f*}\

%{aux-info*}\

%{pg:%{fomit-frame-pointer:%e-pg and -fomit-frame-pointer are incompatible}}\

- %{S:%W{o*}%{!o*:-o %b.s}}%{!S:-o %{|!pipe:%U.s}} |\n\

- %{!S:as %a %Y -o %d%w%u%O %{!pipe:%U.s} %A\n }";

+ %{S:%W{o*}%{!o*:-o %b.s}}%{!S:-o %{|!pipe:%Umain.s}} |\n\

+ %{!S:as %a %Y -o %d%w%umain%O %{!pipe:%Umain.s} %A\n }";

/* Return full path name of spec file if it is in DIR, or NULL if

not. */

diff --git a/gnu/egcs/gcc/local-alloc.c b/gnu/egcs/gcc/local-alloc.c
index d1df595c4c1..2fc3aec4977 100644
--- a/gnu/egcs/gcc/local-alloc.c
+++ b/gnu/egcs/gcc/local-alloc.c

@@ -759,7 +759,8 @@ update_equiv_regs ()

&& REG_N_SETS (regno) == 1

&& reg_equiv_init_insns[regno] != 0

&& reg_equiv_init_insns[regno] != const0_rtx

- && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)

+ && ! find_reg_note (XEXP (reg_equiv_init_insns[regno], 0),

+ REG_EQUIV, NULL_RTX)

&& ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))

{

rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);

diff --git a/gnu/egcs/gcc/po/ChangeLog b/gnu/egcs/gcc/po/ChangeLog
index 416a951f7e2..83babc471a0 100644
--- a/gnu/egcs/gcc/po/ChangeLog
+++ b/gnu/egcs/gcc/po/ChangeLog

@@ -1,3 +1,11 @@

+Sun Oct 24 23:54:10 PDT 1999 Jeff Law (law@cygnus.com)

+ * gcc-2.95.2 Released.

+1999-10-18 Manfred Hollstein <mhollstein@cygnus.com>

+ * POTFILES.in: Track files recently added/deleted/moved.

Mon Aug 16 01:29:24 PDT 1999 Jeff Law (law@cygnus.com)

* gcc-2.95.1 Released.

diff --git a/gnu/egcs/gcc/po/POTFILES.in b/gnu/egcs/gcc/po/POTFILES.in
index e4020c9c3a0..9fd586c3113 100644
--- a/gnu/egcs/gcc/po/POTFILES.in
+++ b/gnu/egcs/gcc/po/POTFILES.in

@@ -208,7 +208,7 @@ config/i386/seq-sysv3.h

config/i386/seq2-sysv3.h

config/i386/sequent.h

config/i386/sol2.h

-config/i386/sol2dbg.h

+config/i386/sol2gas.h

config/i386/sun.h

config/i386/sun386.h

config/i386/svr3dbx.h

@@ -653,6 +653,7 @@ ginclude/math-68881.h

ginclude/ppc-asm.h

ginclude/proto.h

ginclude/stdarg.h

+ginclude/stdbool.h

ginclude/stddef.h

ginclude/va-alpha.h

ginclude/va-arc.h

diff --git a/gnu/egcs/gcc/reg-stack.c b/gnu/egcs/gcc/reg-stack.c
index dd4a87e697c..42caefa0a42 100644
--- a/gnu/egcs/gcc/reg-stack.c
+++ b/gnu/egcs/gcc/reg-stack.c

@@ -1186,8 +1186,16 @@ static rtx

stack_result (decl)

tree decl;

{

- rtx result = DECL_RTL (DECL_RESULT (decl));

+ rtx result;

+ /* If the value is supposed to be returned in memory, then clearly

+ it is not returned in a stack register. */

+ if (aggregate_value_p (DECL_RESULT (decl)))

+ return 0;

+ result = DECL_RTL (DECL_RESULT (decl));

+ /* ?!? What is this code supposed to do? Can this code actually

+ trigger if we kick out aggregates above? */

if (result != 0

&& ! (GET_CODE (result) == REG

&& REGNO (result) < FIRST_PSEUDO_REGISTER))

diff --git a/gnu/egcs/gcc/sched.c b/gnu/egcs/gcc/sched.c
index e8cd070e45c..f09a68ae369 100644
--- a/gnu/egcs/gcc/sched.c
+++ b/gnu/egcs/gcc/sched.c

@@ -587,7 +587,7 @@ insn_unit (insn)

range, don't cache it. */

if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT

|| unit >= 0

- || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)

+ || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)

INSN_UNIT (insn) = unit;

}

return (unit > 0 ? unit - 1 : unit);