Don't turn -fstrict-aliasing on automatically for now.

2 files changed, 153 insertions, 10 deletions

diff --git a/gnu/egcs/gcc/invoke.texi b/gnu/egcs/gcc/invoke.texi
index 8d597342a72..3f9c45ed31b 100644
--- a/gnu/egcs/gcc/invoke.texi
+++ b/gnu/egcs/gcc/invoke.texi
@@ -107,7 +107,7 @@ in the following sections.
 -fno-for-scope  -fno-gnu-keywords  -fguiding-decls  -fhandle-signatures
 -fhonor-std -fhuge-objects  -fno-implicit-templates  -finit-priority
 -fno-implement-inlines -fname-mangling-version-@var{n}  -fno-default-inline  
--foperator-names  -fno-optional-diags  -frepo  -fstrict-prototype
+-foperator-names  -fno-optional-diags  -fpermissive -frepo  -fstrict-prototype
 -fsquangle  -ftemplate-depth-@var{n}  -fthis-is-variable  -fvtable-thunks
 -nostdinc++  -Wctor-dtor-privacy -Wno-deprecated -Weffc++  
 -Wno-non-template-friend 
@@ -342,7 +342,7 @@ in the following sections.
 -mno-wide-multiply  -mrtd  -malign-double
 -mreg-alloc=@var{list}  -mregparm=@var{num}
 -malign-jumps=@var{num}  -malign-loops=@var{num}
--malign-functions=@var{num} -mpreferred_stack_boundary=@var{num}
+-malign-functions=@var{num} -mpreferred-stack-boundary=@var{num}
 
 @emph{HPPA Options}
 -march=@var{architecture type}
@@ -393,6 +393,12 @@ in the following sections.
 -mmangle-cpu  -mcpu=@var{cpu}  -mtext=@var{text section}
 -mdata=@var{data section}  -mrodata=@var{readonly data section}
 
+@emph{TMS320C3x/C4x Options}
+-mcpu=@var{cpu} -mbig -msmall -mregparm -mmemparm
+-mfast-fix -mmpyi -mbk -mti -mdp-isr-reload
+-mrpts=@var{count}  -mrptb -mdb -mloop-unsigned
+-mparallel-insns -mparallel-mpy -mpreserve-float
+
 @emph{V850 Options}
 -mlong-calls -mno-long-calls -mep -mno-ep
 -mprolog-function -mno-prolog-function -mspace
@@ -2088,7 +2094,8 @@ Print statistics on memory usage, at the end of the run, to
 standard error.
 @item p
 Annotate the assembler output with a comment indicating which
-pattern and alternative was used.
+pattern and alternative was used.  The length of each instruction is
+also printed.
 @item x
 Just generate RTL for a function instead of compiling it.  Usually used
 with @samp{r}.
@@ -2194,6 +2201,7 @@ and the performance of the generated code.
 and function inlining.  It also turns on the @samp{-fforce-mem} option
 on all machines and frame pointer elimination on machines where doing so
 does not interfere with debugging.
+It does not turn on @samp{-fstrict-aliasing} on OpenBSD platforms.
 
 @item -O3
 Optimize yet more.  @samp{-O3} turns on all optimizations specified by
@@ -2462,7 +2470,7 @@ default.
 @item -funroll-loops
 Perform the optimization of loop unrolling.  This is only done for loops
 whose number of iterations can be determined at compile time or run time.
-@samp{-funroll-loop} implies both @samp{-fstrength-reduce} and
+@samp{-funroll-loops} implies both @samp{-fstrength-reduce} and
 @samp{-frerun-cse-after-loop}.
 
 @item -funroll-all-loops
@@ -2479,7 +2487,7 @@ Forces all general-induction variables in loops to be
 strength-reduced.
 
 @emph{Note:} When compiling programs written in Fortran,
-@samp{-fmove-all-moveables} and @samp{-freduce-all-givs} are enabled
+@samp{-fmove-all-movables} and @samp{-freduce-all-givs} are enabled
 by default when you use the optimizer.
 
 These options may generate better or worse code; results are highly
@@ -3109,6 +3117,7 @@ that macro, which enables you to change the defaults.
 * H8/300 Options::
 * SH Options::
 * System V Options::
+* TMS320C3x/C4x Options::
 * V850 Options::
 * ARC Options::
 * NS32K Options::
@@ -5043,7 +5052,9 @@ instructions.  The choices for @var{cpu type} are:
 While picking a specific @var{cpu type} will schedule things appropriately
 for that particular chip, the compiler will not generate any code that
 does not run on the i386 without the @samp{-march=@var{cpu type}} option
-being used.
+being used.  @samp{i586} is equivalent to @samp{pentium} and @samp{i686}
+is equivalent to @samp{pentiumpro}.  @samp{k6} is the AMD chip as
+opposed to the Intel ones.
 
 @item -march=@var{cpu type}
 Generate instructions for the machine type @var{cpu type}.  The choices
@@ -5055,7 +5066,7 @@ specifying @samp{-march=@var{cpu type}} implies @samp{-mcpu=@var{cpu type}}.
 @itemx -mpentium
 @itemx -mpentiumpro
 Synonyms for -mcpu=i386, -mcpu=i486, -mcpu=pentium, and -mcpu=pentiumpro
-respectively.  These synonyms are depricated.
+respectively.  These synonyms are deprecated.
 
 @item -mieee-fp
 @itemx -mno-ieee-fp
@@ -5517,7 +5528,8 @@ Dynamic rounding mode.  A field in the floating point control register
 (@var{fpcr}, see Alpha architecture reference manual) controls the
 rounding mode in effect.  The C library initializes this register for
 rounding towards plus infinity.  Thus, unless your program modifies the
-@var{fpcr}, @samp{d} corresponds to round towards plus infinity.@end table
+@var{fpcr}, @samp{d} corresponds to round towards plus infinity.
+@end table
 
 @item -mtrap-precision=@var{trap precision}
 In the Alpha architecture, floating point traps are imprecise.  This
@@ -5746,6 +5758,130 @@ The assembler uses this option.
 @c the generic assembler that comes with Solaris takes just -Ym.
 @end table
 
+@node TMS320C3x/C4x Options
+@subsection TMS320C3x/C4x Options
+@cindex TMS320C3x/C4x Options
+
+These @samp{-m} options are defined for TMS320C3x/C4x implementations:
+
+@table @code
+
+@item -mcpu=@var{cpu_type}
+Set the instruction set, register set, and instruction scheduling
+parameters for machine type @var{cpu_type}.  Supported values for
+@var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
+@samp{c44}.  The default is @samp{c40} to generate code for the
+TMS320C40.
+
+@item -mbig-memory
+@item -mbig
+@itemx -msmall-memory
+@itemx -msmall
+Generates code for the big or small memory model.  The small memory
+model assumed that all data fits into one 64K word page.  At run-time
+the data page (DP) register must be set to point to the 64K page
+containing the .bss and .data program sections.  The big memory model is
+the default and requires reloading of the DP register for every direct
+memory access.
+
+@item -mbk
+@itemx -mno-bk
+Allow (disallow) allocation of general integer operands into the block
+count register BK. 
+
+@item -mdb
+@itemx -mno-db
+Enable (disable) generation of code using decrement and branch,
+DBcond(D), instructions.  This is enabled by default for the C4x.  To be
+on the safe side, this is disabled for the C3x, since the maximum
+iteration count on the C3x is 2^23 + 1 (but who iterates loops more than
+2^23 times on the C3x?).  Note that GCC will try to reverse a loop so
+that it can utilise the decrement and branch instruction, but will give
+up if there is more than one memory reference in the loop.  Thus a loop
+where the loop counter is decremented can generate slightly more
+efficient code, in cases where the RPTB instruction cannot be utilised.
+
+@item -mdp-isr-reload
+@itemx -mparanoid
+Force the DP register to be saved on entry to an interrupt service
+routine (ISR), reloaded to point to the data section, and restored on
+exit from the ISR.  This should not be required unless someone has
+violated the small memory model by modifying the DP register, say within
+an object library.
+
+@item -mmpyi
+@itemx -mno-mpyi
+For the C3x use the 24-bit MPYI instruction for integer multiplies
+instead of a library call to guarantee 32-bit results.  Note that if one
+of the operands is a constant, then the multiplication will be performed
+using shifts and adds.  If the -mmpyi option is not specified for the C3x,
+then squaring operations are performed inline instead of a library call.
+
+@item -mfast-fix
+@itemx -mno-fast-fix
+The C3x/C4x FIX instruction to convert a floating point value to an
+integer value chooses the nearest integer less than or equal to the
+floating point value rather than to the nearest integer.  Thus if the
+floating point number is negative, the result will be incorrectly
+truncated an additional code is necessary to detect and correct this
+case.  This option can be used to disable generation of the additional
+code required to correct the result.
+
+@item -mrptb
+@itemx -mno-rptb
+Enable (disable) generation of repeat block sequences using the RPTB
+instruction for zero overhead looping.  The RPTB construct is only used
+for innermost loops that do not call functions or jump across the loop
+boundaries.  There is no advantage having nested RPTB loops due to the
+overhead required to save and restore the RC, RS, and RE registers.
+This is enabled by default with -O2.
+
+@item -mrpts=@var{count}
+@itemx -mno-rpts
+Enable (disable) the use of the single instruction repeat instruction
+RPTS.  If a repeat block contains a single instruction, and the loop
+count can be guaranteed to be less than the value @var{count}, GCC will
+emit a RPTS instruction instead of a RPTB.  If no value is specified,
+then a RPTS will be emitted even if the loop count cannot be determined
+at compile time.  Note that the repeated instruction following RPTS does
+not have to be reloaded from memory each iteration, thus freeing up the
+CPU buses for oeprands.  However, since interrupts are blocked by this
+instruction, it is disabled by default.
+
+@item -mloop-unsigned
+@itemx -mno-loop-unsigned
+The maximum iteration count when using RPTS and RPTB (and DB on the C40)
+is 2^31 + 1 since these instructions test if the iteration count is
+negative to terminate the loop.  If the iteration count is unsigned
+there is a possibility than the 2^31 + 1 maximum iteration count may be
+exceeded.  This switch allows an unsigned iteration count.
+
+@item -mti
+Try to emit an assembler syntax that the TI assembler (asm30) is happy
+with.  This also enforces compatibility with the API employed by the TI
+C3x C compiler.  For example, long doubles are passed as structures
+rather than in floating point registers.
+
+@item -mregparm
+@itemx -mmemparm
+Generate code that uses registers (stack) for passing arguments to functions.
+By default, arguments are passed in registers where possible rather
+than by pushing arguments on to the stack.
+
+@item -mparallel-insns
+@itemx -mno-parallel-insns
+Allow the generation of parallel instructions.  This is enabled by
+default with -O2.
+
+@item -mparallel-mpy
+@itemx -mno-parallel-mpy
+Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
+provided -mparallel-insns is also specified.  These instructions have
+tight register constraints which can pessimize the code generation
+of large functions.
+
+@end table
+
 @node V850 Options
 @subsection V850 Options
 @cindex V850 Options
diff --git a/gnu/egcs/gcc/toplev.c b/gnu/egcs/gcc/toplev.c
index 7a1277cedce..9dac1fdbd9c 100644
--- a/gnu/egcs/gcc/toplev.c
+++ b/gnu/egcs/gcc/toplev.c
@@ -375,6 +375,8 @@ typedef rtx (*lang_expand_expr_t)
 
 lang_expand_expr_t lang_expand_expr = 0;
 
+tree (*lang_expand_constant) PROTO((tree)) = 0;
+
 /* Pointer to function to finish handling an incomplete decl at the
    end of compilation.  */
 
@@ -563,6 +565,12 @@ int flag_fast_math = 0;
 
 int flag_errno_math = 1;
 
+/* 0 means straightforward implementation of complex divide acceptable.
+   1 means wide ranges of inputs must work for complex divide.
+   2 means C9X-like requirements for complex divide (not yet implemented).  */
+
+int flag_complex_divide_method = 0;
+
 /* Nonzero means all references through pointers are volatile.  */
 
 int flag_volatile;
@@ -4862,7 +4870,6 @@ main (argc, argv)
       flag_schedule_insns_after_reload = 1;
 #endif
       flag_regmove = 1;
-      flag_strict_aliasing = 1;
     }
 
   if (optimize >= 3)
@@ -5239,7 +5246,7 @@ main (argc, argv)
 		      else
 			level = 2;
 
-		      if (da_len > 1 && !strncmp (str, "gdwarf", da_len))
+		      if (da_len > 1 && *p && !strncmp (str, "gdwarf", da_len))
 			{
 			  error ("use -gdwarf -g%d for DWARF v1, level %d",
 				 level, level);