Use the space freed up by sparc and zaurus to import LLVM.

ok hackroom@

3 files changed, 45 insertions, 49 deletions

diff --git a/gnu/llvm/lib/Target/Mips/CMakeLists.txt b/gnu/llvm/lib/Target/Mips/CMakeLists.txt
index b67fb46cf66..bde843afd3d 100644
--- a/gnu/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/gnu/llvm/lib/Target/Mips/CMakeLists.txt
@@ -1,19 +1,16 @@
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
-tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
+tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
-tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
-tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
-tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
-tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
-
+tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
 add_public_tablegen_target(MipsCommonTableGen)
 
 add_llvm_target(MipsCodeGen
@@ -26,26 +23,20 @@ add_llvm_target(MipsCodeGen
   Mips16RegisterInfo.cpp
   MipsAnalyzeImmediate.cpp
   MipsAsmPrinter.cpp
-  MipsCallLowering.cpp
   MipsCCState.cpp
   MipsConstantIslandPass.cpp
   MipsDelaySlotFiller.cpp
-  MipsExpandPseudo.cpp
   MipsFastISel.cpp
   MipsInstrInfo.cpp
-  MipsInstructionSelector.cpp
   MipsISelDAGToDAG.cpp
   MipsISelLowering.cpp
   MipsFrameLowering.cpp
-  MipsLegalizerInfo.cpp
-  MipsBranchExpansion.cpp
+  MipsLongBranch.cpp
   MipsMCInstLower.cpp
   MipsMachineFunction.cpp
   MipsModuleISelDAGToDAG.cpp
   MipsOptimizePICCall.cpp
   MipsOs16.cpp
-  MipsPreLegalizerCombiner.cpp
-  MipsRegisterBankInfo.cpp
   MipsRegisterInfo.cpp
   MipsSEFrameLowering.cpp
   MipsSEInstrInfo.cpp
@@ -55,11 +46,11 @@ add_llvm_target(MipsCodeGen
   MipsSubtarget.cpp
   MipsTargetMachine.cpp
   MipsTargetObjectFile.cpp
-  MicroMipsSizeReduction.cpp
   )
 
-add_subdirectory(AsmParser)
-add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
-add_subdirectory(MCTargetDesc)
+add_subdirectory(Disassembler)
 add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)
+add_subdirectory(AsmParser)
+
diff --git a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
index 27a85970da6..a74c8abd2e2 100644
--- a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
@@ -13,6 +13,7 @@
 
 #include "MipsFrameLowering.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
+#include "MipsAnalyzeImmediate.h"
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
 #include "MipsTargetMachine.h"
@@ -23,6 +24,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
@@ -92,50 +94,57 @@ const MipsFrameLowering *MipsFrameLowering::create(const MipsSubtarget &ST) {
 // if it needs dynamic stack realignment, if frame pointer elimination is
 // disabled, or if the frame address is taken.
 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
-  const MachineFrameInfo &MFI = MF.getFrameInfo();
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
-      MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
+      MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() ||
       TRI->needsStackRealignment(MF);
 }
 
 bool MipsFrameLowering::hasBP(const MachineFunction &MF) const {
-  const MachineFrameInfo &MFI = MF.getFrameInfo();
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
+  return MFI->hasVarSizedObjects() && TRI->needsStackRealignment(MF);
 }
 
-// Estimate the size of the stack, including the incoming arguments. We need to
-// account for register spills, local objects, reserved call frame and incoming
-// arguments. This is required to determine the largest possible positive offset
-// from $sp so that it can be determined if an emergency spill slot for stack
-// addresses is required.
 uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
-  const MachineFrameInfo &MFI = MF.getFrameInfo();
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 
-  int64_t Size = 0;
+  int64_t Offset = 0;
 
-  // Iterate over fixed sized objects which are incoming arguments.
-  for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
-    if (MFI.getObjectOffset(I) > 0)
-      Size += MFI.getObjectSize(I);
+  // Iterate over fixed sized objects.
+  for (int I = MFI->getObjectIndexBegin(); I != 0; ++I)
+    Offset = std::max(Offset, -MFI->getObjectOffset(I));
 
   // Conservatively assume all callee-saved registers will be saved.
   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
-    unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
-    Size = alignTo(Size + RegSize, RegSize);
+    unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
+    Offset = RoundUpToAlignment(Offset + Size, Size);
   }
 
-  // Get the size of the rest of the frame objects and any possible reserved
-  // call frame, accounting for alignment.
-  return Size + MFI.estimateStackSize(MF);
+  unsigned MaxAlign = MFI->getMaxAlignment();
+
+  // Check that MaxAlign is not zero if there is a stack object that is not a
+  // callee-saved spill.
+  assert(!MFI->getObjectIndexEnd() || MaxAlign);
+
+  // Iterate over other objects.
+  for (unsigned I = 0, E = MFI->getObjectIndexEnd(); I != E; ++I)
+    Offset = RoundUpToAlignment(Offset + MFI->getObjectSize(I), MaxAlign);
+
+  // Call frame.
+  if (MFI->adjustsStack() && hasReservedCallFrame(MF))
+    Offset = RoundUpToAlignment(Offset + MFI->getMaxCallFrameSize(),
+                                std::max(MaxAlign, getStackAlignment()));
+
+  return RoundUpToAlignment(Offset, getStackAlignment());
 }
 
 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
-MachineBasicBlock::iterator MipsFrameLowering::
+void MipsFrameLowering::
 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator I) const {
   unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
@@ -148,5 +157,5 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
     STI.getInstrInfo()->adjustStackPtr(SP, Amount, MBB, I);
   }
 
-  return MBB.erase(I);
+  MBB.erase(I);
 }
diff --git a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.h b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.h
index 0ead56eddd2..5eabd58e868 100644
--- a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.h
+++ b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.h
@@ -15,7 +15,7 @@
 #define LLVM_LIB_TARGET_MIPS_MIPSFRAMELOWERING_H
 
 #include "Mips.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/Target/TargetFrameLowering.h"
 
 namespace llvm {
   class MipsSubtarget;
@@ -36,11 +36,7 @@ public:
 
   bool isFPCloseToIncomingSP() const override { return false; }
 
-  bool enableShrinkWrapping(const MachineFunction &MF) const override {
-    return true;
-  }
-
-  MachineBasicBlock::iterator
+  void
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;