Import LLVM 10.0.0 release including clang, lld and lldb.

ok hackroom
tested by plenty

1 files changed, 102 insertions, 596 deletions

diff --git a/gnu/llvm/lld/ELF/Arch/PPC64.cpp b/gnu/llvm/lld/ELF/Arch/PPC64.cpp
index a0c2d1617ca..e48a184c9db 100644
--- a/gnu/llvm/lld/ELF/Arch/PPC64.cpp
+++ b/gnu/llvm/lld/ELF/Arch/PPC64.cpp
@@ -6,24 +6,23 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SymbolTable.h"
 #include "Symbols.h"
 #include "SyntheticSections.h"
 #include "Target.h"
 #include "Thunks.h"
 #include "lld/Common/ErrorHandler.h"
-#include "lld/Common/Memory.h"
 #include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace llvm::object;
 using namespace llvm::support::endian;
 using namespace llvm::ELF;
-using namespace lld;
-using namespace lld::elf;
 
-constexpr uint64_t ppc64TocOffset = 0x8000;
-constexpr uint64_t dynamicThreadPointerOffset = 0x8000;
+namespace lld {
+namespace elf {
+
+static uint64_t ppc64TocOffset = 0x8000;
+static uint64_t dynamicThreadPointerOffset = 0x8000;
 
 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
 // instructions that can be used as part of the initial exec TLS sequence.
@@ -62,93 +61,7 @@ enum DFormOpcd {
   ADDI = 14
 };
 
-constexpr uint32_t NOP = 0x60000000;
-
-enum class PPCLegacyInsn : uint32_t {
-  NOINSN = 0,
-  // Loads.
-  LBZ = 0x88000000,
-  LHZ = 0xa0000000,
-  LWZ = 0x80000000,
-  LHA = 0xa8000000,
-  LWA = 0xe8000002,
-  LD = 0xe8000000,
-  LFS = 0xC0000000,
-  LXSSP = 0xe4000003,
-  LFD = 0xc8000000,
-  LXSD = 0xe4000002,
-  LXV = 0xf4000001,
-  LXVP = 0x18000000,
-
-  // Stores.
-  STB = 0x98000000,
-  STH = 0xb0000000,
-  STW = 0x90000000,
-  STD = 0xf8000000,
-  STFS = 0xd0000000,
-  STXSSP = 0xf4000003,
-  STFD = 0xd8000000,
-  STXSD = 0xf4000002,
-  STXV = 0xf4000005,
-  STXVP = 0x18000001
-};
-enum class PPCPrefixedInsn : uint64_t {
-  NOINSN = 0,
-  PREFIX_MLS = 0x0610000000000000,
-  PREFIX_8LS = 0x0410000000000000,
-
-  // Loads.
-  PLBZ = PREFIX_MLS,
-  PLHZ = PREFIX_MLS,
-  PLWZ = PREFIX_MLS,
-  PLHA = PREFIX_MLS,
-  PLWA = PREFIX_8LS | 0xa4000000,
-  PLD = PREFIX_8LS | 0xe4000000,
-  PLFS = PREFIX_MLS,
-  PLXSSP = PREFIX_8LS | 0xac000000,
-  PLFD = PREFIX_MLS,
-  PLXSD = PREFIX_8LS | 0xa8000000,
-  PLXV = PREFIX_8LS | 0xc8000000,
-  PLXVP = PREFIX_8LS | 0xe8000000,
-
-  // Stores.
-  PSTB = PREFIX_MLS,
-  PSTH = PREFIX_MLS,
-  PSTW = PREFIX_MLS,
-  PSTD = PREFIX_8LS | 0xf4000000,
-  PSTFS = PREFIX_MLS,
-  PSTXSSP = PREFIX_8LS | 0xbc000000,
-  PSTFD = PREFIX_MLS,
-  PSTXSD = PREFIX_8LS | 0xb8000000,
-  PSTXV = PREFIX_8LS | 0xd8000000,
-  PSTXVP = PREFIX_8LS | 0xf8000000
-};
-static bool checkPPCLegacyInsn(uint32_t encoding) {
-  PPCLegacyInsn insn = static_cast<PPCLegacyInsn>(encoding);
-  if (insn == PPCLegacyInsn::NOINSN)
-    return false;
-#define PCREL_OPT(Legacy, PCRel, InsnMask)                                     \
-  if (insn == PPCLegacyInsn::Legacy)                                           \
-    return true;
-#include "PPCInsns.def"
-#undef PCREL_OPT
-  return false;
-}
-
-// Masks to apply to legacy instructions when converting them to prefixed,
-// pc-relative versions. For the most part, the primary opcode is shared
-// between the legacy instruction and the suffix of its prefixed version.
-// However, there are some instances where that isn't the case (DS-Form and
-// DQ-form instructions).
-enum class LegacyToPrefixMask : uint64_t {
-  NOMASK = 0x0,
-  OPC_AND_RST = 0xffe00000, // Primary opc (0-5) and R[ST] (6-10).
-  ONLY_RST = 0x3e00000,     // [RS]T (6-10).
-  ST_STX28_TO5 =
-      0x8000000003e00000, // S/T (6-10) - The [S/T]X bit moves from 28 to 5.
-};
-
-uint64_t elf::getPPC64TocBase() {
+uint64_t getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
@@ -162,7 +75,7 @@ uint64_t elf::getPPC64TocBase() {
   return tocVA + ppc64TocOffset;
 }
 
-unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) {
+unsigned getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) {
   // The offset is encoded into the 3 most significant bits of the st_other
   // field, with some special values described in section 3.4.1 of the ABI:
   // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
@@ -187,94 +100,11 @@ unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) {
   return 0;
 }
 
-bool elf::isPPC64SmallCodeModelTocReloc(RelType type) {
+bool isPPC64SmallCodeModelTocReloc(RelType type) {
   // The only small code model relocations that access the .toc section.
   return type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS;
 }
 
-void elf::writePrefixedInstruction(uint8_t *loc, uint64_t insn) {
-  insn = config->isLE ? insn << 32 | insn >> 32 : insn;
-  write64(loc, insn);
-}
-
-static bool addOptional(StringRef name, uint64_t value,
-                        std::vector<Defined *> &defined) {
-  Symbol *sym = symtab->find(name);
-  if (!sym || sym->isDefined())
-    return false;
-  sym->resolve(Defined{/*file=*/nullptr, saver.save(name), STB_GLOBAL,
-                       STV_HIDDEN, STT_FUNC, value,
-                       /*size=*/0, /*section=*/nullptr});
-  defined.push_back(cast<Defined>(sym));
-  return true;
-}
-
-// If from is 14, write ${prefix}14: firstInsn; ${prefix}15:
-// firstInsn+0x200008; ...; ${prefix}31: firstInsn+(31-14)*0x200008; $tail
-// The labels are defined only if they exist in the symbol table.
-static void writeSequence(MutableArrayRef<uint32_t> buf, const char *prefix,
-                          int from, uint32_t firstInsn,
-                          ArrayRef<uint32_t> tail) {
-  std::vector<Defined *> defined;
-  char name[16];
-  int first;
-  uint32_t *ptr = buf.data();
-  for (int r = from; r < 32; ++r) {
-    format("%s%d", prefix, r).snprint(name, sizeof(name));
-    if (addOptional(name, 4 * (r - from), defined) && defined.size() == 1)
-      first = r - from;
-    write32(ptr++, firstInsn + 0x200008 * (r - from));
-  }
-  for (uint32_t insn : tail)
-    write32(ptr++, insn);
-  assert(ptr == &*buf.end());
-
-  if (defined.empty())
-    return;
-  // The full section content has the extent of [begin, end). We drop unused
-  // instructions and write [first,end).
-  auto *sec = make<InputSection>(
-      nullptr, SHF_ALLOC, SHT_PROGBITS, 4,
-      makeArrayRef(reinterpret_cast<uint8_t *>(buf.data() + first),
-                   4 * (buf.size() - first)),
-      ".text");
-  inputSections.push_back(sec);
-  for (Defined *sym : defined) {
-    sym->section = sec;
-    sym->value -= 4 * first;
-  }
-}
-
-// Implements some save and restore functions as described by ELF V2 ABI to be
-// compatible with GCC. With GCC -Os, when the number of call-saved registers
-// exceeds a certain threshold, GCC generates _savegpr0_* _restgpr0_* calls and
-// expects the linker to define them. See
-// https://sourceware.org/pipermail/binutils/2002-February/017444.html and
-// https://sourceware.org/pipermail/binutils/2004-August/036765.html . This is
-// weird because libgcc.a would be the natural place. The linker generation
-// approach has the advantage that the linker can generate multiple copies to
-// avoid long branch thunks. However, we don't consider the advantage
-// significant enough to complicate our trunk implementation, so we take the
-// simple approach and synthesize .text sections providing the implementation.
-void elf::addPPC64SaveRestore() {
-  static uint32_t savegpr0[20], restgpr0[21], savegpr1[19], restgpr1[19];
-  constexpr uint32_t blr = 0x4e800020, mtlr_0 = 0x7c0803a6;
-
-  // _restgpr0_14: ld 14, -144(1); _restgpr0_15: ld 15, -136(1); ...
-  // Tail: ld 0, 16(1); mtlr 0; blr
-  writeSequence(restgpr0, "_restgpr0_", 14, 0xe9c1ff70,
-                {0xe8010010, mtlr_0, blr});
-  // _restgpr1_14: ld 14, -144(12); _restgpr1_15: ld 15, -136(12); ...
-  // Tail: blr
-  writeSequence(restgpr1, "_restgpr1_", 14, 0xe9ccff70, {blr});
-  // _savegpr0_14: std 14, -144(1); _savegpr0_15: std 15, -136(1); ...
-  // Tail: std 0, 16(1); blr
-  writeSequence(savegpr0, "_savegpr0_", 14, 0xf9c1ff70, {0xf8010010, blr});
-  // _savegpr1_14: std 14, -144(12); _savegpr1_15: std 15, -136(12); ...
-  // Tail: blr
-  writeSequence(savegpr1, "_savegpr1_", 14, 0xf9ccff70, {blr});
-}
-
 // Find the R_PPC64_ADDR64 in .rela.toc with matching offset.
 template <typename ELFT>
 static std::pair<Defined *, int64_t>
@@ -307,7 +137,7 @@ getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {
 
 // When accessing a symbol defined in another translation unit, compilers
 // reserve a .toc entry, allocate a local label and generate toc-indirect
-// instructions:
+// instuctions:
 //
 //   addis 3, 2, .LC0@toc@ha  # R_PPC64_TOC16_HA
 //   ld    3, .LC0@toc@l(3)   # R_PPC64_TOC16_LO_DS, load the address from a .toc entry
@@ -325,7 +155,8 @@ getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {
 //   ld/lwa 3, 0(3)           # load the value from the address
 //
 // Returns true if the relaxation is performed.
-bool elf::tryRelaxPPC64TocIndirection(const Relocation &rel, uint8_t *bufLoc) {
+bool tryRelaxPPC64TocIndirection(RelType type, const Relocation &rel,
+                                 uint8_t *bufLoc) {
   assert(config->tocOptimize);
   if (rel.addend < 0)
     return false;
@@ -355,8 +186,8 @@ bool elf::tryRelaxPPC64TocIndirection(const Relocation &rel, uint8_t *bufLoc) {
   if (!isInt<32>(tocRelative))
     return false;
 
-  // Add PPC64TocOffset that will be subtracted by PPC64::relocate().
-  target->relaxGot(bufLoc, rel, tocRelative + ppc64TocOffset);
+  // Add PPC64TocOffset that will be subtracted by relocateOne().
+  target->relaxGot(bufLoc, type, tocRelative + ppc64TocOffset);
   return true;
 }
 
@@ -374,27 +205,20 @@ public:
                 uint64_t pltEntryAddr) const override;
   void writeIplt(uint8_t *buf, const Symbol &sym,
                  uint64_t pltEntryAddr) const override;
-  void relocate(uint8_t *loc, const Relocation &rel,
-                uint64_t val) const override;
+  void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
   void writeGotHeader(uint8_t *buf) const override;
   bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
                   uint64_t branchAddr, const Symbol &s,
                   int64_t a) const override;
   uint32_t getThunkSectionSpacing() const override;
   bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
-  RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override;
-  RelExpr adjustGotPcExpr(RelType type, int64_t addend,
-                          const uint8_t *loc) const override;
-  void relaxGot(uint8_t *loc, const Relocation &rel,
-                uint64_t val) const override;
-  void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
-                      uint64_t val) const override;
-  void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
-                      uint64_t val) const override;
-  void relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
-                      uint64_t val) const override;
-  void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
-                      uint64_t val) const override;
+  RelExpr adjustRelaxExpr(RelType type, const uint8_t *data,
+                          RelExpr expr) const override;
+  void relaxGot(uint8_t *loc, RelType type, uint64_t val) const override;
+  void relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const override;
+  void relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const override;
+  void relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const override;
+  void relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const override;
 
   bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
                                         uint8_t stOther) const override;
@@ -407,7 +231,7 @@ public:
 // document.
 static uint16_t lo(uint64_t v) { return v; }
 static uint16_t hi(uint64_t v) { return v >> 16; }
-static uint64_t ha(uint64_t v) { return (v + 0x8000) >> 16; }
+static uint16_t ha(uint64_t v) { return (v + 0x8000) >> 16; }
 static uint16_t higher(uint64_t v) { return v >> 32; }
 static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; }
 static uint16_t highest(uint64_t v) { return v >> 48; }
@@ -420,7 +244,6 @@ static bool isDQFormInstruction(uint32_t encoding) {
   switch (getPrimaryOpCode(encoding)) {
   default:
     return false;
-  case 6: // Power10 paired loads/stores (lxvp, stxvp).
   case 56:
     // The only instruction with a primary opcode of 56 is `lq`.
     return true;
@@ -432,78 +255,6 @@ static bool isDQFormInstruction(uint32_t encoding) {
   }
 }
 
-static bool isDSFormInstruction(PPCLegacyInsn insn) {
-  switch (insn) {
-  default:
-    return false;
-  case PPCLegacyInsn::LWA:
-  case PPCLegacyInsn::LD:
-  case PPCLegacyInsn::LXSD:
-  case PPCLegacyInsn::LXSSP:
-  case PPCLegacyInsn::STD:
-  case PPCLegacyInsn::STXSD:
-  case PPCLegacyInsn::STXSSP:
-    return true;
-  }
-}
-
-static PPCLegacyInsn getPPCLegacyInsn(uint32_t encoding) {
-  uint32_t opc = encoding & 0xfc000000;
-
-  // If the primary opcode is shared between multiple instructions, we need to
-  // fix it up to match the actual instruction we are after.
-  if ((opc == 0xe4000000 || opc == 0xe8000000 || opc == 0xf4000000 ||
-       opc == 0xf8000000) &&
-      !isDQFormInstruction(encoding))
-    opc = encoding & 0xfc000003;
-  else if (opc == 0xf4000000)
-    opc = encoding & 0xfc000007;
-  else if (opc == 0x18000000)
-    opc = encoding & 0xfc00000f;
-
-  // If the value is not one of the enumerators in PPCLegacyInsn, we want to
-  // return PPCLegacyInsn::NOINSN.
-  if (!checkPPCLegacyInsn(opc))
-    return PPCLegacyInsn::NOINSN;
-  return static_cast<PPCLegacyInsn>(opc);
-}
-
-static PPCPrefixedInsn getPCRelativeForm(PPCLegacyInsn insn) {
-  switch (insn) {
-#define PCREL_OPT(Legacy, PCRel, InsnMask)                                     \
-  case PPCLegacyInsn::Legacy:                                                  \
-    return PPCPrefixedInsn::PCRel
-#include "PPCInsns.def"
-#undef PCREL_OPT
-  }
-  return PPCPrefixedInsn::NOINSN;
-}
-
-static LegacyToPrefixMask getInsnMask(PPCLegacyInsn insn) {
-  switch (insn) {
-#define PCREL_OPT(Legacy, PCRel, InsnMask)                                     \
-  case PPCLegacyInsn::Legacy:                                                  \
-    return LegacyToPrefixMask::InsnMask
-#include "PPCInsns.def"
-#undef PCREL_OPT
-  }
-  return LegacyToPrefixMask::NOMASK;
-}
-static uint64_t getPCRelativeForm(uint32_t encoding) {
-  PPCLegacyInsn origInsn = getPPCLegacyInsn(encoding);
-  PPCPrefixedInsn pcrelInsn = getPCRelativeForm(origInsn);
-  if (pcrelInsn == PPCPrefixedInsn::NOINSN)
-    return UINT64_C(-1);
-  LegacyToPrefixMask origInsnMask = getInsnMask(origInsn);
-  uint64_t pcrelEncoding =
-      (uint64_t)pcrelInsn | (encoding & (uint64_t)origInsnMask);
-
-  // If the mask requires moving bit 28 to bit 5, do that now.
-  if (origInsnMask == LegacyToPrefixMask::ST_STX28_TO5)
-    pcrelEncoding |= (encoding & 0x8) << 23;
-  return pcrelEncoding;
-}
-
 static bool isInstructionUpdateForm(uint32_t encoding) {
   switch (getPrimaryOpCode(encoding)) {
   default:
@@ -528,25 +279,6 @@ static bool isInstructionUpdateForm(uint32_t encoding) {
   }
 }
 
-// Compute the total displacement between the prefixed instruction that gets
-// to the start of the data and the load/store instruction that has the offset
-// into the data structure.
-// For example:
-// paddi 3, 0, 1000, 1
-// lwz 3, 20(3)
-// Should add up to 1020 for total displacement.
-static int64_t getTotalDisp(uint64_t prefixedInsn, uint32_t accessInsn) {
-  int64_t disp34 = llvm::SignExtend64(
-      ((prefixedInsn & 0x3ffff00000000) >> 16) | (prefixedInsn & 0xffff), 34);
-  int32_t disp16 = llvm::SignExtend32(accessInsn & 0xffff, 16);
-  // For DS and DQ form instructions, we need to mask out the XO bits.
-  if (isDQFormInstruction(accessInsn))
-    disp16 &= ~0xf;
-  else if (isDSFormInstruction(getPPCLegacyInsn(accessInsn)))
-    disp16 &= ~0x3;
-  return disp34 + disp16;
-}
-
 // There are a number of places when we either want to read or write an
 // instruction when handling a half16 relocation type. On big-endian the buffer
 // pointer is pointing into the middle of the word we want to extract, and on
@@ -560,11 +292,6 @@ static uint32_t readFromHalf16(const uint8_t *loc) {
   return read32(config->isLE ? loc : loc - 2);
 }
 
-static uint64_t readPrefixedInstruction(const uint8_t *loc) {
-  uint64_t fullInstr = read64(loc);
-  return config->isLE ? (fullInstr << 32 | fullInstr >> 32) : fullInstr;
-}
-
 PPC64::PPC64() {
   copyRel = R_PPC64_COPY;
   gotRel = R_PPC64_GLOB_DAT;
@@ -621,8 +348,8 @@ int PPC64::getTlsGdRelaxSkip(RelType type) const {
 
 static uint32_t getEFlags(InputFile *file) {
   if (config->ekind == ELF64BEKind)
-    return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader().e_flags;
-  return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader().e_flags;
+    return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader()->e_flags;
+  return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader()->e_flags;
 }
 
 // This file implements v2 ABI. This function makes sure that all
@@ -638,11 +365,11 @@ uint32_t PPC64::calcEFlags() const {
   return 2;
 }
 
-void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const {
-  switch (rel.type) {
+void PPC64::relaxGot(uint8_t *loc, RelType type, uint64_t val) const {
+  switch (type) {
   case R_PPC64_TOC16_HA:
     // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop".
-    relocate(loc, rel, val);
+    relocateOne(loc, type, val);
     break;
   case R_PPC64_TOC16_LO_DS: {
     // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or
@@ -651,50 +378,7 @@ void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const {
     if (getPrimaryOpCode(insn) != LD)
       error("expected a 'ld' for got-indirect to toc-relative relaxing");
     writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000);
-    relocateNoSym(loc, R_PPC64_TOC16_LO, val);
-    break;
-  }
-  case R_PPC64_GOT_PCREL34: {
-    // Clear the first 8 bits of the prefix and the first 6 bits of the
-    // instruction (the primary opcode).
-    uint64_t insn = readPrefixedInstruction(loc);
-    if ((insn & 0xfc000000) != 0xe4000000)
-      error("expected a 'pld' for got-indirect to pc-relative relaxing");
-    insn &= ~0xff000000fc000000;
-
-    // Replace the cleared bits with the values for PADDI (0x600000038000000);
-    insn |= 0x600000038000000;
-    writePrefixedInstruction(loc, insn);
-    relocate(loc, rel, val);
-    break;
-  }
-  case R_PPC64_PCREL_OPT: {
-    // We can only relax this if the R_PPC64_GOT_PCREL34 at this offset can
-    // be relaxed. The eligibility for the relaxation needs to be determined
-    // on that relocation since this one does not relocate a symbol.
-    uint64_t insn = readPrefixedInstruction(loc);
-    uint32_t accessInsn = read32(loc + rel.addend);
-    uint64_t pcRelInsn = getPCRelativeForm(accessInsn);
-
-    // This error is not necessary for correctness but is emitted for now
-    // to ensure we don't miss these opportunities in real code. It can be
-    // removed at a later date.
-    if (pcRelInsn == UINT64_C(-1)) {
-      errorOrWarn(
-          "unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x" +
-          Twine::utohexstr(accessInsn));
-      break;
-    }
-
-    int64_t totalDisp = getTotalDisp(insn, accessInsn);
-    if (!isInt<34>(totalDisp))
-      break; // Displacement doesn't fit.
-    // Convert the PADDI to the prefixed version of accessInsn and convert
-    // accessInsn to a nop.
-    writePrefixedInstruction(loc, pcRelInsn |
-                                      ((totalDisp & 0x3ffff0000) << 16) |
-                                      (totalDisp & 0xffff));
-    write32(loc + rel.addend, NOP); // nop accessInsn.
+    relocateOne(loc, R_PPC64_TOC16_LO, val);
     break;
   }
   default:
@@ -702,8 +386,7 @@ void PPC64::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   }
 }
 
-void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
-                           uint64_t val) const {
+void PPC64::relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const {
   // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
   // The general dynamic code sequence for a global `x` will look like:
   // Instruction                    Relocation                Symbol
@@ -719,54 +402,30 @@ void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
   // bl __tls_get_addr(x@tlsgd)      into      nop
   // nop                             into      addi r3, r3, x@tprel@l
 
-  switch (rel.type) {
+  switch (type) {
   case R_PPC64_GOT_TLSGD16_HA:
-    writeFromHalf16(loc, NOP);
+    writeFromHalf16(loc, 0x60000000); // nop
     break;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13
-    relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
+    relocateOne(loc, R_PPC64_TPREL16_HA, val);
     break;
-  case R_PPC64_GOT_TLSGD_PCREL34:
-    // Relax from paddi r3, 0, x@got@tlsgd@pcrel, 1 to
-    //            paddi r3, r13, x@tprel, 0
-    writePrefixedInstruction(loc, 0x06000000386d0000);
-    relocateNoSym(loc, R_PPC64_TPREL34, val);
-    break;
-  case R_PPC64_TLSGD: {
-    // PC Relative Relaxation:
-    // Relax from bl __tls_get_addr@notoc(x@tlsgd) to
-    //            nop
-    // TOC Relaxation:
-    // Relax from bl __tls_get_addr(x@tlsgd)
-    //            nop
-    // to
-    //            nop
-    //            addi r3, r3, x@tprel@l
-    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
-    if (locAsInt % 4 == 0) {
-      write32(loc, NOP);            // nop
-      write32(loc + 4, 0x38630000); // addi r3, r3
-      // Since we are relocating a half16 type relocation and Loc + 4 points to
-      // the start of an instruction we need to advance the buffer by an extra
-      // 2 bytes on BE.
-      relocateNoSym(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0),
-                    R_PPC64_TPREL16_LO, val);
-    } else if (locAsInt % 4 == 1) {
-      write32(loc - 1, NOP);
-    } else {
-      errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment");
-    }
+  case R_PPC64_TLSGD:
+    write32(loc, 0x60000000);     // nop
+    write32(loc + 4, 0x38630000); // addi r3, r3
+    // Since we are relocating a half16 type relocation and Loc + 4 points to
+    // the start of an instruction we need to advance the buffer by an extra
+    // 2 bytes on BE.
+    relocateOne(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0),
+                R_PPC64_TPREL16_LO, val);
     break;
-  }
   default:
     llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
   }
 }
 
-void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
-                           uint64_t val) const {
+void PPC64::relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const {
   // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
   // The local dynamic code sequence for a global `x` will look like:
   // Instruction                    Relocation                Symbol
@@ -782,55 +441,31 @@ void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
   // bl __tls_get_addr(x@tlsgd)     into      nop
   // nop                            into      addi r3, r3, 4096
 
-  switch (rel.type) {
+  switch (type) {
   case R_PPC64_GOT_TLSLD16_HA:
-    writeFromHalf16(loc, NOP);
+    writeFromHalf16(loc, 0x60000000); // nop
     break;
   case R_PPC64_GOT_TLSLD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0
     break;
-  case R_PPC64_GOT_TLSLD_PCREL34:
-    // Relax from paddi r3, 0, x1@got@tlsld@pcrel, 1 to
-    //            paddi r3, r13, 0x1000, 0
-    writePrefixedInstruction(loc, 0x06000000386d1000);
-    break;
-  case R_PPC64_TLSLD: {
-    // PC Relative Relaxation:
-    // Relax from bl __tls_get_addr@notoc(x@tlsld)
-    // to
-    //            nop
-    // TOC Relaxation:
-    // Relax from bl __tls_get_addr(x@tlsld)
-    //            nop
-    // to
-    //            nop
-    //            addi r3, r3, 4096
-    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
-    if (locAsInt % 4 == 0) {
-      write32(loc, NOP);
-      write32(loc + 4, 0x38631000); // addi r3, r3, 4096
-    } else if (locAsInt % 4 == 1) {
-      write32(loc - 1, NOP);
-    } else {
-      errorOrWarn("R_PPC64_TLSLD has unexpected byte alignment");
-    }
+  case R_PPC64_TLSLD:
+    write32(loc, 0x60000000);     // nop
+    write32(loc + 4, 0x38631000); // addi r3, r3, 4096
     break;
-  }
   case R_PPC64_DTPREL16:
   case R_PPC64_DTPREL16_HA:
   case R_PPC64_DTPREL16_HI:
   case R_PPC64_DTPREL16_DS:
   case R_PPC64_DTPREL16_LO:
   case R_PPC64_DTPREL16_LO_DS:
-  case R_PPC64_DTPREL34:
-    relocate(loc, rel, val);
+    relocateOne(loc, type, val);
     break;
   default:
     llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
   }
 }
 
-unsigned elf::getPPCDFormOp(unsigned secondaryOp) {
+unsigned getPPCDFormOp(unsigned secondaryOp) {
   switch (secondaryOp) {
   case LBZX:
     return LBZ;
@@ -855,8 +490,7 @@ unsigned elf::getPPCDFormOp(unsigned secondaryOp) {
   }
 }
 
-void PPC64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
-                           uint64_t val) const {
+void PPC64::relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const {
   // The initial exec code sequence for a global `x` will look like:
   // Instruction                    Relocation                Symbol
   // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
@@ -877,68 +511,27 @@ void PPC64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
   // indexed load or store instructions.
 
   unsigned offset = (config->ekind == ELF64BEKind) ? 2 : 0;
-  switch (rel.type) {
+  switch (type) {
   case R_PPC64_GOT_TPREL16_HA:
-    write32(loc - offset, NOP);
+    write32(loc - offset, 0x60000000); // nop
     break;
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS: {
     uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10
     write32(loc - offset, 0x3C0D0000 | regNo);          // addis RegNo, r13
-    relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
-    break;
-  }
-  case R_PPC64_GOT_TPREL_PCREL34: {
-    const uint64_t pldRT = readPrefixedInstruction(loc) & 0x0000000003e00000;
-    // paddi RT(from pld), r13, symbol@tprel, 0
-    writePrefixedInstruction(loc, 0x06000000380d0000 | pldRT);
-    relocateNoSym(loc, R_PPC64_TPREL34, val);
+    relocateOne(loc, R_PPC64_TPREL16_HA, val);
     break;
   }
   case R_PPC64_TLS: {
-    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
-    if (locAsInt % 4 == 0) {
-      uint32_t primaryOp = getPrimaryOpCode(read32(loc));
-      if (primaryOp != 31)
-        error("unrecognized instruction for IE to LE R_PPC64_TLS");
-      uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30
-      uint32_t dFormOp = getPPCDFormOp(secondaryOp);
-      if (dFormOp == 0)
-        error("unrecognized instruction for IE to LE R_PPC64_TLS");
-      write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF)));
-      relocateNoSym(loc + offset, R_PPC64_TPREL16_LO, val);
-    } else if (locAsInt % 4 == 1) {
-      // If the offset is not 4 byte aligned then we have a PCRel type reloc.
-      // This version of the relocation is offset by one byte from the
-      // instruction it references.
-      uint32_t tlsInstr = read32(loc - 1);
-      uint32_t primaryOp = getPrimaryOpCode(tlsInstr);
-      if (primaryOp != 31)
-        errorOrWarn("unrecognized instruction for IE to LE R_PPC64_TLS");
-      uint32_t secondaryOp = (tlsInstr & 0x000007FE) >> 1; // bits 21-30
-      // The add is a special case and should be turned into a nop. The paddi
-      // that comes before it will already have computed the address of the
-      // symbol.
-      if (secondaryOp == 266) {
-        // Check if the add uses the same result register as the input register.
-        uint32_t rt = (tlsInstr & 0x03E00000) >> 21; // bits 6-10
-        uint32_t ra = (tlsInstr & 0x001F0000) >> 16; // bits 11-15
-        if (ra == rt) {
-          write32(loc - 1, NOP);
-        } else {
-          // mr rt, ra
-          write32(loc - 1, 0x7C000378 | (rt << 16) | (ra << 21) | (ra << 11));
-        }
-      } else {
-        uint32_t dFormOp = getPPCDFormOp(secondaryOp);
-        if (dFormOp == 0)
-          errorOrWarn("unrecognized instruction for IE to LE R_PPC64_TLS");
-        write32(loc - 1, ((dFormOp << 26) | (tlsInstr & 0x03FF0000)));
-      }
-    } else {
-      errorOrWarn("R_PPC64_TLS must be either 4 byte aligned or one byte "
-                  "offset from 4 byte aligned");
-    }
+    uint32_t primaryOp = getPrimaryOpCode(read32(loc));
+    if (primaryOp != 31)
+      error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30
+    uint32_t dFormOp = getPPCDFormOp(secondaryOp);
+    if (dFormOp == 0)
+      error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF)));
+    relocateOne(loc + offset, R_PPC64_TPREL16_LO, val);
     break;
   }
   default:
@@ -956,7 +549,6 @@ RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_ADDR16_DS:
   case R_PPC64_ADDR16_HA:
   case R_PPC64_ADDR16_HI:
-  case R_PPC64_ADDR16_HIGH:
   case R_PPC64_ADDR16_HIGHER:
   case R_PPC64_ADDR16_HIGHERA:
   case R_PPC64_ADDR16_HIGHEST:
@@ -978,10 +570,6 @@ RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
     return R_GOTREL;
-  case R_PPC64_GOT_PCREL34:
-  case R_PPC64_GOT_TPREL_PCREL34:
-  case R_PPC64_PCREL_OPT:
-    return R_GOT_PC;
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_LO_DS:
     return config->tocOptimize ? R_PPC64_RELAX_TOC : R_GOTREL;
@@ -990,29 +578,22 @@ RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_REL14:
   case R_PPC64_REL24:
     return R_PPC64_CALL_PLT;
-  case R_PPC64_REL24_NOTOC:
-    return R_PLT_PC;
   case R_PPC64_REL16_LO:
   case R_PPC64_REL16_HA:
   case R_PPC64_REL16_HI:
   case R_PPC64_REL32:
   case R_PPC64_REL64:
-  case R_PPC64_PCREL34:
     return R_PC;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_HA:
   case R_PPC64_GOT_TLSGD16_HI:
   case R_PPC64_GOT_TLSGD16_LO:
     return R_TLSGD_GOT;
-  case R_PPC64_GOT_TLSGD_PCREL34:
-    return R_TLSGD_PC;
   case R_PPC64_GOT_TLSLD16:
   case R_PPC64_GOT_TLSLD16_HA:
   case R_PPC64_GOT_TLSLD16_HI:
   case R_PPC64_GOT_TLSLD16_LO:
     return R_TLSLD_GOT;
-  case R_PPC64_GOT_TLSLD_PCREL34:
-    return R_TLSLD_PC;
   case R_PPC64_GOT_TPREL16_HA:
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS:
@@ -1033,8 +614,7 @@ RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_TPREL16_HIGHERA:
   case R_PPC64_TPREL16_HIGHEST:
   case R_PPC64_TPREL16_HIGHESTA:
-  case R_PPC64_TPREL34:
-    return R_TPREL;
+    return R_TLS;
   case R_PPC64_DTPREL16:
   case R_PPC64_DTPREL16_DS:
   case R_PPC64_DTPREL16_HA:
@@ -1046,7 +626,6 @@ RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_DTPREL16_LO:
   case R_PPC64_DTPREL16_LO_DS:
   case R_PPC64_DTPREL64:
-  case R_PPC64_DTPREL34:
     return R_DTPREL;
   case R_PPC64_TLSGD:
     return R_TLSDESC_CALL;
@@ -1191,8 +770,11 @@ static bool isTocOptType(RelType type) {
   }
 }
 
-void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
-  RelType type = rel.type;
+void PPC64::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
+  // We need to save the original relocation type to use in diagnostics, and
+  // use the original type to determine if we should toc-optimize the
+  // instructions being relocated.
+  RelType originalType = type;
   bool shouldTocOptimize =  isTocOptType(type);
   // For dynamic thread pointer relative, toc-relative, and got-indirect
   // relocations, proceed in terms of the corresponding ADDR16 relocation type.
@@ -1200,46 +782,40 @@ void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
 
   switch (type) {
   case R_PPC64_ADDR14: {
-    checkAlignment(loc, val, 4, rel);
+    checkAlignment(loc, val, 4, type);
     // Preserve the AA/LK bits in the branch instruction
     uint8_t aalk = loc[3];
     write16(loc + 2, (aalk & 3) | (val & 0xfffc));
     break;
   }
   case R_PPC64_ADDR16:
-    checkIntUInt(loc, val, 16, rel);
+    checkIntUInt(loc, val, 16, originalType);
     write16(loc, val);
     break;
   case R_PPC64_ADDR32:
-    checkIntUInt(loc, val, 32, rel);
+    checkIntUInt(loc, val, 32, originalType);
     write32(loc, val);
     break;
   case R_PPC64_ADDR16_DS:
   case R_PPC64_TPREL16_DS: {
-    checkInt(loc, val, 16, rel);
+    checkInt(loc, val, 16, originalType);
     // DQ-form instructions use bits 28-31 as part of the instruction encoding
     // DS-form instructions only use bits 30-31.
     uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 0xf : 0x3;
-    checkAlignment(loc, lo(val), mask + 1, rel);
+    checkAlignment(loc, lo(val), mask + 1, originalType);
     write16(loc, (read16(loc) & mask) | lo(val));
   } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
     if (config->tocOptimize && shouldTocOptimize && ha(val) == 0)
-      writeFromHalf16(loc, NOP);
-    else {
-      checkInt(loc, val + 0x8000, 32, rel);
+      writeFromHalf16(loc, 0x60000000);
+    else
       write16(loc, ha(val));
-    }
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
   case R_PPC64_TPREL16_HI:
-    checkInt(loc, val, 32, rel);
-    write16(loc, hi(val));
-    break;
-  case R_PPC64_ADDR16_HIGH:
     write16(loc, hi(val));
     break;
   case R_PPC64_ADDR16_HIGHER:
@@ -1281,7 +857,7 @@ void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
     // DS-form instructions only use bits 30-31.
     uint32_t insn = readFromHalf16(loc);
     uint16_t mask = isDQFormInstruction(insn) ? 0xf : 0x3;
-    checkAlignment(loc, lo(val), mask + 1, rel);
+    checkAlignment(loc, lo(val), mask + 1, originalType);
     if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) {
       // When the high-adjusted part of a toc relocation evaluates to 0, it is
       // changed into a nop. The lo part then needs to be updated to use the toc
@@ -1297,11 +873,11 @@ void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
     }
   } break;
   case R_PPC64_TPREL16:
-    checkInt(loc, val, 16, rel);
+    checkInt(loc, val, 16, originalType);
     write16(loc, val);
     break;
   case R_PPC64_REL32:
-    checkInt(loc, val, 32, rel);
+    checkInt(loc, val, 32, type);
     write32(loc, val);
     break;
   case R_PPC64_ADDR64:
@@ -1311,47 +887,21 @@ void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
     break;
   case R_PPC64_REL14: {
     uint32_t mask = 0x0000FFFC;
-    checkInt(loc, val, 16, rel);
-    checkAlignment(loc, val, 4, rel);
+    checkInt(loc, val, 16, type);
+    checkAlignment(loc, val, 4, type);
     write32(loc, (read32(loc) & ~mask) | (val & mask));
     break;
   }
-  case R_PPC64_REL24:
-  case R_PPC64_REL24_NOTOC: {
+  case R_PPC64_REL24: {
     uint32_t mask = 0x03FFFFFC;
-    checkInt(loc, val, 26, rel);
-    checkAlignment(loc, val, 4, rel);
+    checkInt(loc, val, 26, type);
+    checkAlignment(loc, val, 4, type);
     write32(loc, (read32(loc) & ~mask) | (val & mask));
     break;
   }
   case R_PPC64_DTPREL64:
     write64(loc, val - dynamicThreadPointerOffset);
     break;
-  case R_PPC64_DTPREL34:
-    // The Dynamic Thread Vector actually points 0x8000 bytes past the start
-    // of the TLS block. Therefore, in the case of R_PPC64_DTPREL34 we first
-    // need to subtract that value then fallthrough to the general case.
-    val -= dynamicThreadPointerOffset;
-    LLVM_FALLTHROUGH;
-  case R_PPC64_PCREL34:
-  case R_PPC64_GOT_PCREL34:
-  case R_PPC64_GOT_TLSGD_PCREL34:
-  case R_PPC64_GOT_TLSLD_PCREL34:
-  case R_PPC64_GOT_TPREL_PCREL34:
-  case R_PPC64_TPREL34: {
-    const uint64_t si0Mask = 0x00000003ffff0000;
-    const uint64_t si1Mask = 0x000000000000ffff;
-    const uint64_t fullMask = 0x0003ffff0000ffff;
-    checkInt(loc, val, 34, rel);
-
-    uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
-    writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |
-                             (val & si1Mask));
-    break;
-  }
-  // If we encounter a PCREL_OPT relocation that we won't optimize.
-  case R_PPC64_PCREL_OPT:
-    break;
   default:
     llvm_unreachable("unknown relocation");
   }
@@ -1359,23 +909,13 @@ void PPC64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
 
 bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
                        uint64_t branchAddr, const Symbol &s, int64_t a) const {
-  if (type != R_PPC64_REL14 && type != R_PPC64_REL24 &&
-      type != R_PPC64_REL24_NOTOC)
+  if (type != R_PPC64_REL14 && type != R_PPC64_REL24)
     return false;
 
   // If a function is in the Plt it needs to be called with a call-stub.
   if (s.isInPlt())
     return true;
 
-  // This check looks at the st_other bits of the callee with relocation
-  // R_PPC64_REL14 or R_PPC64_REL24. If the value is 1, then the callee
-  // clobbers the TOC and we need an R2 save stub.
-  if (type != R_PPC64_REL24_NOTOC && (s.stOther >> 5) == 1)
-    return true;
-
-  if (type == R_PPC64_REL24_NOTOC && (s.stOther >> 5) > 1)
-    return true;
-
   // If a symbol is a weak undefined and we are compiling an executable
   // it doesn't need a range-extending thunk since it can't be called.
   if (s.isUndefWeak() && !config->shared)
@@ -1401,31 +941,20 @@ bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
   int64_t offset = dst - src;
   if (type == R_PPC64_REL14)
     return isInt<16>(offset);
-  if (type == R_PPC64_REL24 || type == R_PPC64_REL24_NOTOC)
+  if (type == R_PPC64_REL24)
     return isInt<26>(offset);
   llvm_unreachable("unsupported relocation type used in branch");
 }
 
-RelExpr PPC64::adjustTlsExpr(RelType type, RelExpr expr) const {
-  if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE)
+RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data,
+                               RelExpr expr) const {
+  if (expr == R_RELAX_TLS_GD_TO_IE)
     return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
   if (expr == R_RELAX_TLS_LD_TO_LE)
     return R_RELAX_TLS_LD_TO_LE_ABS;
   return expr;
 }
 
-RelExpr PPC64::adjustGotPcExpr(RelType type, int64_t addend,
-                               const uint8_t *loc) const {
-  if ((type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT) &&
-      config->pcRelOptimize) {
-    // It only makes sense to optimize pld since paddi means that the address
-    // of the object in the GOT is required rather than the object itself.
-    if ((readPrefixedInstruction(loc) & 0xfc000000) == 0xe4000000)
-      return R_PPC64_RELAX_GOT_PC;
-  }
-  return R_GOT_PC;
-}
-
 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
 // The general dynamic code sequence for a global `x` uses 4 instructions.
 // Instruction                    Relocation                Symbol
@@ -1443,13 +972,12 @@ RelExpr PPC64::adjustGotPcExpr(RelType type, int64_t addend,
 //    thread pointer.
 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
 // used as the relaxation hint for both steps 2 and 3.
-void PPC64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
-                           uint64_t val) const {
-  switch (rel.type) {
+void PPC64::relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const {
+  switch (type) {
   case R_PPC64_GOT_TLSGD16_HA:
     // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
     //                      addis rT, r2, sym@got@tprel@ha.
-    relocateNoSym(loc, R_PPC64_GOT_TPREL16_HA, val);
+    relocateOne(loc, R_PPC64_GOT_TPREL16_HA, val);
     return;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_LO: {
@@ -1457,38 +985,13 @@ void PPC64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
     //            ld r3, sym@got@tprel@l(rA)
     uint32_t ra = (readFromHalf16(loc) & (0x1f << 16));
     writeFromHalf16(loc, 0xe8600000 | ra);
-    relocateNoSym(loc, R_PPC64_GOT_TPREL16_LO_DS, val);
-    return;
-  }
-  case R_PPC64_GOT_TLSGD_PCREL34: {
-    // Relax from paddi r3, 0, sym@got@tlsgd@pcrel, 1 to
-    //            pld r3, sym@got@tprel@pcrel
-    writePrefixedInstruction(loc, 0x04100000e4600000);
-    relocateNoSym(loc, R_PPC64_GOT_TPREL_PCREL34, val);
+    relocateOne(loc, R_PPC64_GOT_TPREL16_LO_DS, val);
     return;
   }
-  case R_PPC64_TLSGD: {
-    // PC Relative Relaxation:
-    // Relax from bl __tls_get_addr@notoc(x@tlsgd) to
-    //            nop
-    // TOC Relaxation:
-    // Relax from bl __tls_get_addr(x@tlsgd)
-    //            nop
-    // to
-    //            nop
-    //            add r3, r3, r13
-    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
-    if (locAsInt % 4 == 0) {
-      write32(loc, NOP);            // bl __tls_get_addr(sym@tlsgd) --> nop
-      write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
-    } else if (locAsInt % 4 == 1) {
-      // bl __tls_get_addr(sym@tlsgd) --> add r3, r3, r13
-      write32(loc - 1, 0x7c636a14);
-    } else {
-      errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment");
-    }
+  case R_PPC64_TLSGD:
+    write32(loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
+    write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
     return;
-  }
   default:
     llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
   }
@@ -1557,7 +1060,7 @@ bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
   uint32_t secondInstr = read32(loc + 8);
   if (!loImm && getPrimaryOpCode(secondInstr) == 14) {
     loImm = secondInstr & 0xFFFF;
-  } else if (secondInstr != NOP) {
+  } else if (secondInstr != 0x60000000) {
     return false;
   }
 
@@ -1571,7 +1074,7 @@ bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
   };
   if (!checkRegOperands(firstInstr, 12, 1))
     return false;
-  if (secondInstr != NOP && !checkRegOperands(secondInstr, 12, 12))
+  if (secondInstr != 0x60000000 && !checkRegOperands(secondInstr, 12, 12))
     return false;
 
   int32_t stackFrameSize = (hiImm * 65536) + loImm;
@@ -1590,18 +1093,21 @@ bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
   if (hiImm) {
     write32(loc + 4, 0x3D810000 | (uint16_t)hiImm);
     // If the low immediate is zero the second instruction will be a nop.
-    secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : NOP;
+    secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : 0x60000000;
     write32(loc + 8, secondInstr);
   } else {
     // addi r12, r1, imm
     write32(loc + 4, (0x39810000) | (uint16_t)loImm);
-    write32(loc + 8, NOP);
+    write32(loc + 8, 0x60000000);
   }
 
   return true;
 }
 
-TargetInfo *elf::getPPC64TargetInfo() {
+TargetInfo *getPPC64TargetInfo() {
   static PPC64 target;
   return &target;
 }
+
+} // namespace elf
+} // namespace lld