Import binutils-2.10

- only the binutils package (no gdb here)
- don't import libiberty and texinfo, they are elsewhere
- remove all .info* generated files

9 files changed, 1376 insertions, 0 deletions

diff --git a/gnu/usr.bin/binutils/gas/doc/Makefile.am b/gnu/usr.bin/binutils/gas/doc/Makefile.am
new file mode 100644
index 00000000000..c6eaf77bd7b
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/Makefile.am
@@ -0,0 +1,52 @@
+## Process this file with automake to generate Makefile.in
+
+AUTOMAKE_OPTIONS = cygnus
+
+# What version of the manual you want; "all" includes everything
+CONFIG=all
+
+man_MANS = as.1
+
+info_TEXINFOS = as.texinfo gasp.texi
+
+asconfig.texi: $(CONFIG).texi
+	rm -f asconfig.texi
+	ln -s $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
+	  || ln $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
+	  || cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
+
+CPU_DOCS = \
+	c-a29k.texi \
+	c-arm.texi \
+	c-d10v.texi \
+	c-h8300.texi \
+	c-h8500.texi \
+	c-hppa.texi \
+	c-i370.texi \
+	c-i386.texi \
+	c-i960.texi \
+	c-m32r.texi \
+	c-m68k.texi \
+	c-mips.texi \
+	c-ns32k.texi \
+	c-pj.texi \
+	c-sh.texi \
+	c-sparc.texi \
+	c-vax.texi \
+	c-v850.texi \
+	c-z8k.texi
+
+gasver.texi: Makefile
+	rm -f $@
+	echo '@set VERSION $(VERSION)' > $@
+
+as.info: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+as.dvi: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+
+# This one isn't ready for prime time yet.  Not even a little bit.
+
+noinst_TEXINFOS = internals.texi
+
+DISTCLEANFILES = asconfig.texi
+
+MAINTAINERCLEANFILES = gasver.texi
diff --git a/gnu/usr.bin/binutils/gas/doc/c-arm.texi b/gnu/usr.bin/binutils/gas/doc/c-arm.texi
new file mode 100644
index 00000000000..e3549824032
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-arm.texi
@@ -0,0 +1,294 @@
+@c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node ARM-Dependent
+@chapter ARM Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter ARM Dependent Features
+@end ifclear
+
+@cindex ARM support
+@cindex Thumb support
+@menu
+* ARM Options::              Options
+* ARM Syntax::               Syntax
+* ARM Floating Point::       Floating Point
+* ARM Directives::           ARM Machine Directives
+* ARM Opcodes::              Opcodes
+@end menu
+
+@node ARM Options
+@section Options
+@cindex ARM options (none)
+@cindex options for ARM (none)
+
+@table @code
+
+@cindex @code{-marm} command line option, ARM
+@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
+This option specifies the target processor.  The assembler will issue an
+error message if an attempt is made to assemble an instruction which
+will not execute on the target processor.
+
+@cindex @code{-marmv} command line option, ARM
+@item -marmv@code{[2|2a|3|3m|4|4t|5|5t]}
+This option specifies the target architecture.  The assembler will issue
+an error message if an attempt is made to assemble an instruction which
+will not execute on the target architecture.
+
+@cindex @code{-mthumb} command line option, ARM
+@item -mthumb
+This option specifies that only Thumb instructions should be assembled.
+
+@cindex @code{-mall} command line option, ARM
+@item -mall
+This option specifies that any Arm or Thumb instruction should be assembled.
+
+@cindex @code{-mfpa} command line option, ARM
+@item -mfpa @var{[10|11]}
+This option specifies the floating point architecture in use on the
+target processor. 
+
+@cindex @code{-mfpe-old} command line option, ARM
+@item -mfpe-old
+Do not allow the assemble of floating point multiple instructions.
+
+@cindex @code{-mno-fpu} command line option, ARM
+@item -mno-fpu
+Do not allow the assembly of any floating point instructions.
+
+@cindex @code{-mthumb-interwork} command line option, ARM
+@item -mthumb-interwork
+This option specifies that the output generated by the assembler should
+be marked as supporting interworking.
+
+@cindex @code{-mapcs} command line option, ARM
+@item -mapcs @var{[26|32]}
+This option specifies that the output generated by the assembler should
+be marked as supporting the indicated version of the Arm Procedure.
+Calling Standard.
+
+@cindex @code{-mapcs-float} command line option, ARM
+@item -mapcs-float
+This indicates the the floating point variant of the APCS should be
+used.  In this variant floating point arguments are passed in FP
+registers rather than integer registers.
+
+@cindex @code{-mapcs-reentrant} command line option, ARM
+@item -mapcs-reentrant
+This indicates that the reentrant variant of the APCS should be used.
+This variant supports position independent code.
+
+@cindex @code{-EB} command line option, ARM
+@item -EB
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a big-endian processor.
+
+@cindex @code{-EL} command line option, ARM
+@item -EL
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a little-endian processor.
+
+@cindex @code{-k} command line option, ARM
+@cindex PIC code generation for ARM
+@item -k
+This option enables the generation of PIC (position independent code).
+
+@cindex @code{-moabi} command line option, ARM
+@item -moabi
+This indicates that the code should be assembled using the old ARM ELF
+conventions, based on a beta release release of the ARM-ELF
+specifications, rather than the default conventions which are based on
+the final release of the ARM-ELF specifications.
+
+@end table
+
+
+@node ARM Syntax
+@section Syntax
+@menu
+* ARM-Chars::                Special Characters
+* ARM-Regs::                 Register Names
+@end menu
+
+@node ARM-Chars
+@subsection Special Characters
+
+@cindex line comment character, ARM
+@cindex ARM line comment character
+The presence of a @samp{@@} on a line indicates the start of a comment
+that extends to the end of the current line.  If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, ARM
+@cindex statement separator, ARM
+@cindex ARM line separator
+On ARM systems running the GNU/Linux operating system, @samp{;} can be
+used instead of a newline to separate statements.
+
+@cindex immediate character, ARM
+@cindex ARM immediate character
+Either @samp{#} or @samp{$} can be used to indicate immediate operands.
+
+@cindex identifiers, ARM
+@cindex ARM identifiers
+*TODO* Explain about /data modifier on symbols.
+
+@node ARM-Regs
+@subsection Register Names
+
+@cindex ARM register names
+@cindex register names, ARM
+*TODO* Explain about ARM register naming, and the predefined names.
+
+@node ARM Floating Point
+@section Floating Point
+
+@cindex floating point, ARM (@sc{ieee})
+@cindex ARM floating point (@sc{ieee})
+The ARM family uses @sc{ieee} floating-point numbers.
+
+
+
+@node ARM Directives
+@section ARM Machine Directives
+
+@cindex machine directives, ARM
+@cindex ARM machine directives
+@table @code
+
+@cindex @code{align} directive, ARM
+@item .align @var{expression} [, @var{expression}]
+This is the generic @var{.align} directive.  For the ARM however if the
+first argument is zero (ie no alignment is needed) the assembler will
+behave as if the argument had been 2 (ie pad to the next four byte
+boundary).  This is for compatability with ARM's own assembler.
+
+@cindex @code{req} directive, ARM
+@item @var{name} .req @var{register name}
+This creates an alias for @var{register name} called @var{name}.  For
+example:
+
+@smallexample
+        foo .req r0
+@end smallexample
+
+@cindex @code{code} directive, ARM
+@item .code @var{[16|32]}
+This directive selects the instruction set being generated. The value 16
+selects Thumb, with the value 32 selecting ARM.
+
+@cindex @code{thumb} directive, ARM
+@item .thumb
+This performs the same action as @var{.code 16}.
+
+@cindex @code{arm} directive, ARM
+@item .arm
+This performs the same action as @var{.code 32}.
+
+@cindex @code{force_thumb} directive, ARM
+@item .force_thumb
+This directive forces the selection of Thumb instructions, even if the
+target processor does not support those instructions
+
+@cindex @code{thumb_func} directive, ARM
+@item .thumb_func
+This directive specifies that the following symbol is the name of a
+Thumb encoded function.  This information is necessary in order to allow
+the assembler and linker to generate correct code for interworking
+between Arm and Thumb instructions and should be used even if
+interworking is not going to be performed.
+
+@cindex @code{thumb_set} directive, ARM
+@item .thumb_set
+This performs the equivalent of a @code{.set} directive in that it
+creates a symbol which is an alias for another symbol (possibly not yet
+defined).  This directive also has the added property in that it marks
+the aliased symbol as being a thumb function entry point, in the same
+way that the @code{.thumb_func} directive does.
+
+@cindex @code{.ltorg} directive, ARM
+@item .ltorg
+This directive causes the current contents of the literal pool to be
+dumped into the current section (which is assumed to be the .text
+section) at the current location (aligned to a word boundary).
+
+@cindex @code{.pool} directive, ARM
+@item .pool
+This is a synonym for .ltorg.
+
+@end table
+
+@node ARM Opcodes
+@section Opcodes
+
+@cindex ARM opcodes
+@cindex opcodes for ARM
+@code{@value{AS}} implements all the standard ARM opcodes.  It also
+implements several pseudo opcodes, including several synthetic load
+instructions. 
+
+@table @code
+
+@cindex @code{NOP} pseudo op, ARM
+@item NOP
+@smallexample
+  nop
+@end smallexample
+
+This pseudo op will always evaluate to a legal ARM instruction that does
+nothing.  Currently it will evaluate to MOV r0, r0.
+
+@cindex @code{LDR reg,=<label>} pseudo op, ARM
+@item LDR 
+@smallexample
+  ldr <register> , = <expression>
+@end smallexample
+
+If expression evaluates to a numeric constant then a MOV or MVN
+instruction will be used in place of the LDR instruction, if the
+constant can be generated by either of these instructions.  Otherwise
+the constant will be placed into the nearest literal pool (if it not
+already there) and a PC relative LDR instruction will be generated.
+
+@cindex @code{ADR reg,<label>} pseudo op, ARM
+@item ADR
+@smallexample
+  adr <register> <label>
+@end smallexample
+
+This instruction will load the address of @var{label} into the indicated
+register.  The instruction will evaluate to a PC relative ADD or SUB
+instruction depending upon where the label is located.  If the label is
+out of range, or if it is not defined in the same file (and section) as
+the ADR instruction, then an error will be generated.  This instruction
+will not make use of the literal pool.
+
+@cindex @code{ADRL reg,<label>} pseudo op, ARM
+@item ADRL 
+@smallexample
+  adrl <register> <label>
+@end smallexample
+
+This instruction will load the address of @var{label} into the indicated
+register.  The instruction will evaluate to one or two a PC relative ADD
+or SUB instructions depending upon where the label is located.  If a
+second instruction is not needed a NOP instruction will be generated in
+its place, so that this instruction is always 8 bytes long.
+
+If the label is out of range, or if it is not defined in the same file
+(and section) as the ADRL instruction, then an error will be generated.
+This instruction will not make use of the literal pool.
+
+@end table
+
+For information on the ARM or Thumb instruction sets, see @cite{ARM
+Software Development Toolkit Reference Manual}, Advanced RISC Machines
+Ltd.
+
diff --git a/gnu/usr.bin/binutils/gas/doc/c-d10v.texi b/gnu/usr.bin/binutils/gas/doc/c-d10v.texi
index b2593473196..8d7bf88c99d 100644
--- a/gnu/usr.bin/binutils/gas/doc/c-d10v.texi
+++ b/gnu/usr.bin/binutils/gas/doc/c-d10v.texi
@@ -31,6 +31,10 @@ dependent options.
 The D10V can often execute two sub-instructions in parallel. When this option
 is used, @code{@value{AS}} will attempt to optimize its output by detecting when
 instructions can be executed in parallel.
+@item --nowarnswap
+To optimize execution performance, @code{@value{AS}} will sometimes swap the
+order of instructions. Normally this generates a warning. When this option 
+is used, no warning will be generated when instructions are swapped.
 @end table
 
 @node D10V-Syntax
diff --git a/gnu/usr.bin/binutils/gas/doc/c-d30v.texi b/gnu/usr.bin/binutils/gas/doc/c-d30v.texi
new file mode 100644
index 00000000000..731b3441e0f
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-d30v.texi
@@ -0,0 +1,292 @@
+@c Copyright (C) 1997 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node D30V-Dependent
+@chapter D30V Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter D30V Dependent Features
+@end ifclear
+
+@cindex D30V support
+@menu
+* D30V-Opts::                   D30V Options
+* D30V-Syntax::                 Syntax
+* D30V-Float::                  Floating Point
+* D30V-Opcodes::                Opcodes
+@end menu
+
+@node D30V-Opts
+@section D30V Options
+@cindex options, D30V
+@cindex D30V options
+The Mitsubishi D30V version of @code{@value{AS}} has a few machine
+dependent options.
+
+@table @samp
+@item -O
+The D30V can often execute two sub-instructions in parallel. When this option
+is used, @code{@value{AS}} will attempt to optimize its output by detecting when
+instructions can be executed in parallel.
+
+@item -n
+When this option is used, @code{@value{AS}} will issue a warning every
+time it adds a nop instruction.
+
+@item -N
+When this option is used, @code{@value{AS}} will issue a warning if it
+needs to insert a nop after a 32-bit multiply before a load or 16-bit
+multiply instruction.
+@end table
+
+@node D30V-Syntax
+@section Syntax
+@cindex D30V syntax
+@cindex syntax, D30V
+
+The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual.
+The differences are detailed below.
+
+@menu
+* D30V-Size::                 Size Modifiers
+* D30V-Subs::                 Sub-Instructions
+* D30V-Chars::                Special Characters
+* D30V-Guarded::              Guarded Execution
+* D30V-Regs::                 Register Names
+* D30V-Addressing::           Addressing Modes
+@end menu
+
+
+@node D30V-Size
+@subsection Size Modifiers
+@cindex D30V size modifiers
+@cindex size modifiers, D30V
+The D30V version of @code{@value{AS}} uses the instruction names in the D30V
+Architecture Manual.  However, the names in the manual are sometimes ambiguous.
+There are instruction names that can assemble to a short or long form opcode.
+How does the assembler pick the correct form?  @code{@value{AS}} will always pick the
+smallest form if it can.  When dealing with a symbol that is not defined yet when a
+line is being assembled, it will always use the long form.  If you need to force the 
+assembler to use either the short or long form of the instruction, you can append
+either @samp{.s} (short) or @samp{.l} (long) to it.  For example, if you are writing 
+an assembly program and you want to do a branch to a symbol that is defined later
+in your program, you can write @samp{bra.s foo}. 
+Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
+have both short and long forms.
+
+@node D30V-Subs
+@subsection Sub-Instructions
+@cindex D30V sub-instructions
+@cindex sub-instructions, D30V
+The D30V assembler takes as input a series of instructions, either one-per-line,
+or in the special two-per-line format described in the next section.  Some of these
+instructions will be short-form or sub-instructions.  These sub-instructions can be packed
+into a single instruction.  The assembler will do this automatically.  It will also detect
+when it should not pack instructions.  For example, when a label is defined, the next
+instruction will never be packaged with the previous one.  Whenever a branch and link
+instruction is called, it will not be packaged with the next instruction so the return
+address will be valid.  Nops are automatically inserted when necessary.
+
+If you do not want the assembler automatically making these decisions, you can control
+the packaging and execution type (parallel or sequential) with the special execution 
+symbols described in the next section.  
+
+@node D30V-Chars
+@subsection Special Characters
+@cindex line comment character, D30V
+@cindex D30V line comment character
+@samp{;} and @samp{#} are the line comment characters.
+@cindex sub-instruction ordering, D30V
+@cindex D30V sub-instruction ordering
+Sub-instructions may be executed in order, in reverse-order, or in parallel.
+Instructions listed in the standard one-per-line format will be executed
+sequentially unless you use the @samp{-O} option.
+
+To specify the executing order, use the following symbols: 
+@table @samp
+@item ->
+Sequential with instruction on the left first.
+
+@item <-
+Sequential with instruction on the right first.
+
+@item ||
+Parallel
+@end table
+
+The D30V syntax allows either one instruction per line, one instruction per line with
+the execution symbol, or two instructions per line.  For example
+@table @code
+@item abs r2,r3 -> abs r4,r5
+Execute these sequentially.  The instruction on the right is in the right
+container and is executed second.
+
+@item abs r2,r3 <- abs r4,r5
+Execute these reverse-sequentially.  The instruction on the right is in the right
+container, and is executed first.
+
+@item abs r2,r3 || abs r4,r5
+Execute these in parallel.
+
+@item ldw r2,@@(r3,r4) ||
+@itemx mulx r6,r8,r9
+Two-line format. Execute these in parallel.
+
+@item mulx a0,r8,r9
+@itemx stw r2,@@(r3,r4)
+Two-line format. Execute these sequentially unless @samp{-O} option is
+used.  If the @samp{-O} option is used, the assembler will determine if
+the instructions could be done in parallel (the above two instructions
+can be done in parallel), and if so, emit them as parallel instructions.
+The assembler will put them in the proper containers.  In the above
+example, the assembler will put the @samp{stw} instruction in left
+container and the @samp{mulx} instruction in the right container.
+
+@item stw r2,@@(r3,r4) ->
+@itemx mulx a0,r8,r9
+Two-line format.  Execute the @samp{stw} instruction followed by the
+@samp{mulx} instruction sequentially.  The first instruction goes in the
+left container and the second instruction goes into right container.
+The assembler will give an error if the machine ordering constraints are
+violated.
+
+@item stw r2,@@(r3,r4) <-
+@itemx mulx a0,r8,r9
+Same as previous example, except that the @samp{mulx} instruction is
+executed before the @samp{stw} instruction.
+@end table
+
+@cindex symbol names, @samp{$} in
+@cindex @code{$} in symbol names
+Since @samp{$} has no special meaning, you may use it in symbol names.
+
+@node D30V-Guarded
+@subsection Guarded Execution
+@cindex D30V Guarded Execution
+@code{@value{AS}} supports the full range of guarded execution
+directives for each instruction.  Just append the directive after the
+instruction proper.  The directives are:
+
+@table @samp
+@item /tx
+Execute the instruction if flag f0 is true.
+@item /fx
+Execute the instruction if flag f0 is false.
+@item /xt
+Execute the instruction if flag f1 is true.
+@item /xf
+Execute the instruction if flag f1 is false.
+@item /tt
+Execute the instruction if both flags f0 and f1 are true.
+@item /tf
+Execute the instruction if flag f0 is true and flag f1 is false.
+@end table
+
+@node D30V-Regs
+@subsection Register Names
+@cindex D30V registers
+@cindex registers, D30V
+You can use the predefined symbols @samp{r0} through @samp{r63} to refer
+to the D30V registers.  You can also use @samp{sp} as an alias for
+@samp{r63} and @samp{link} as an alias for @samp{r62}.  The accumulators
+are @samp{a0} and @samp{a1}.
+
+The D30V also has predefined symbols for these control registers and status bits:
+@table @code
+@item psw
+Processor Status Word
+@item bpsw
+Backup Processor Status Word
+@item pc
+Program Counter
+@item bpc
+Backup Program Counter
+@item rpt_c
+Repeat Count
+@item rpt_s
+Repeat Start address
+@item rpt_e
+Repeat End address
+@item mod_s
+Modulo Start address
+@item mod_e
+Modulo End address
+@item iba
+Instruction Break Address
+@item f0
+Flag 0
+@item f1
+Flag 1
+@item f2
+Flag 2
+@item f3
+Flag 3
+@item f4
+Flag 4
+@item f5
+Flag 5
+@item f6
+Flag 6
+@item f7
+Flag 7
+@item s
+Same as flag 4 (saturation flag)
+@item v
+Same as flag 5 (overflow flag)
+@item va
+Same as flag 6 (sticky overflow flag)
+@item c
+Same as flag 7 (carry/borrow flag)
+@item b
+Same as flag 7 (carry/borrow flag)
+@end table
+        
+@node D30V-Addressing
+@subsection Addressing Modes
+@cindex addressing modes, D30V
+@cindex D30V addressing modes
+@code{@value{AS}} understands the following addressing modes for the D30V.
+@code{R@var{n}} in the following refers to any of the numbered
+registers, but @emph{not} the control registers.
+@table @code
+@item R@var{n}
+Register direct
+@item @@R@var{n}
+Register indirect
+@item @@R@var{n}+
+Register indirect with post-increment
+@item @@R@var{n}-
+Register indirect with post-decrement
+@item @@-SP
+Register indirect with pre-decrement
+@item @@(@var{disp}, R@var{n})
+Register indirect with displacement
+@item @var{addr}
+PC relative address (for branch or rep). 
+@item #@var{imm}
+Immediate data (the @samp{#} is optional and ignored)
+@end table
+
+@node D30V-Float
+@section Floating Point
+@cindex floating point, D30V
+@cindex D30V floating point
+The D30V has no hardware floating point, but the @code{.float} and @code{.double}
+directives generates @sc{ieee} floating-point numbers for compatibility
+with other development tools. 
+
+@node D30V-Opcodes
+@section Opcodes
+@cindex D30V opcode summary
+@cindex opcode summary, D30V
+@cindex mnemonics, D30V
+@cindex instruction summary, D30V
+For detailed information on the D30V machine instruction set, see
+@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications} 
+(Mitsubishi Electric Corp.).
+@code{@value{AS}} implements all the standard D30V opcodes.  The only changes are those
+described in the section on size modifiers
+
diff --git a/gnu/usr.bin/binutils/gas/doc/c-i370.texi b/gnu/usr.bin/binutils/gas/doc/c-i370.texi
new file mode 100644
index 00000000000..18b41b25ca0
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-i370.texi
@@ -0,0 +1,200 @@
+@c Copyright (C) 2000 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node ESA/390-Dependent
+@chapter ESA/390 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter ESA/390 Dependent Features
+@end ifclear
+
+@cindex i370 support
+@cindex ESA/390 support
+
+@menu
+* ESA/390 Notes::                Notes
+* ESA/390 Options::              Options
+* ESA/390 Syntax::               Syntax
+* ESA/390 Floating Point::       Floating Point
+* ESA/390 Directives::           ESA/390 Machine Directives
+* ESA/390 Opcodes::              Opcodes
+@end menu
+
+@node ESA/390 Notes
+@section Notes
+The ESA/390 @code{@value{AS}} port is currently intended to be a back-end
+for the @sc{gnu} @sc{cc} compiler.  It is not HLASM compatible, although
+it does support a subset of some of the HLASM directives.  The only 
+supported binary file format is ELF; none of the usual MVS/VM/OE/USS 
+object file formats, such as ESD or XSD, are supported.
+
+When used with the @sc{gnu} @sc{cc} compiler, the ESA/390 @code{@value{AS}}
+will produce correct, fully relocated, functional binaries, and has been 
+used to compile and execute large projects.  However, many aspects should 
+still be considered experimental; these include shared library support, 
+dynamically loadable objects, and any relocation other than the 31-bit 
+relocation.
+
+@node ESA/390 Options
+@section Options
+@code{@value{AS}} has no machine-dependent command-line options for the ESA/390.
+
+@cindex ESA/390 Syntax
+@node ESA/390 Syntax
+@section Syntax
+The opcode/operand syntax follows the ESA/390 Principles of Operation
+manual; assembler directives and general syntax are loosely based on the 
+prevailing AT&T/SVR4/ELF/Solaris style notation.  HLASM-style directives
+are @emph{not} supported for the most part, with the exception of those 
+described herein.
+
+A leading dot in front of directives is optional, and the case of
+directives is ignored; thus for example, .using and USING have the same
+effect.
+
+A colon may immediately follow a label definition.  This is
+simply for compatibility with how most assembly language programmers
+write code.
+
+@samp{#} is the line comment character.
+
+@samp{;} can be used instead of a newline to separate statements.
+
+Since @samp{$} has no special meaning, you may use it in symbol names.
+
+Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
+By using thesse symbolic names, @code{@value{AS}} can detect simple 
+syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
+for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 
+for r3 and rpgt or r.pgt for r4.
+
+@samp{*} is the current location counter.  Unlike @samp{.} it is always
+relative to the last USING directive.  Note that this means that 
+expressions cannot use multiplication, as any occurence of @samp{*}
+will be interpreted as a location counter.
+
+All labels are relative to the last USING.  Thus, branches to a label 
+always imply the use of base+displacement.
+
+Many of the usual forms of address constants / address literals 
+are supported.  Thus,
+@example
+	.using	*,r3
+	L	r15,=A(some_routine)
+	LM	r6,r7,=V(some_longlong_extern)
+	A	r1,=F'12'
+	AH	r0,=H'42'
+	ME	r6,=E'3.1416'
+	MD	r6,=D'3.14159265358979'
+	O	r6,=XL4'cacad0d0'
+	.ltorg
+@end example
+should all behave as expected: that is, an entry in the literal
+pool will be created (or reused if it already exists), and the 
+instruction operands will be the displacement into the literal pool
+using the current base register (as last declared with the @code{.using}
+directive).
+
+@node ESA/390 Floating Point
+@section Floating Point
+@cindex floating point, ESA/390 (@sc{ieee})
+@cindex ESA/390 floating point (@sc{ieee})
+The assembler generates only @sc{ieee} floating-point numbers.  The older
+floiating point formats are not supported.
+
+
+@node ESA/390 Directives
+@section ESA/390 Assembler Directives
+
+@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4 
+assembler directives that are documented in the main part of this
+documentation.  Several additional directives are supported in order
+to implement the ESA/390 addressing model.  The most important of these
+are @code{.using} and @code{.ltorg}
+
+@cindex ESA/390-only directives
+These are the additional directives in @code{@value{AS}} for the ESA/390:
+
+@table @code
+@item .dc 
+A small subset of the usual DC directive is supported.
+
+@item .drop @var{regno}
+Stop using @var{regno} as the base register.  The @var{regno} must
+have been previously declared with a @code{.using} directive in the
+same section as the current section.
+
+@item .ebcdic @var{string}
+Emit the EBCDIC equivalent of the indicated string.  The emitted string
+will be null terminated.  Note that the directives @code{.string} etc. emit
+ascii strings by default.
+
+@item EQU 
+The standard HLASM-style EQU directive is not supported; however, the 
+standard @code{@value{AS}} directive .equ can be used to the same effect.
+
+@item .ltorg 
+Dump the literal pool accumulated so far; begin a new literal pool.
+The literal pool will be written in the current section; in order to
+generate correct assembly, a @code{.using} must have been previously
+specified in the same section.
+
+@item .using @var{expr},@var{regno}
+Use @var{regno} as the base register for all subsequent RX, RS, and SS form
+instructions. The @var{expr} will be evaluated to obtain the base address;
+usually, @var{expr} will merely be @samp{*}.
+
+This assembler allows two @code{.using} directives to be simultaneously
+outstanding, one in the @code{.text} section, and one in another section 
+(typically, the @code{.data} section).  This feature allows 
+dynamically loaded objects to be implemented in a relatively 
+straightforward way.  A @code{.using} directive must always be specified 
+in the @code{.text} section; this will specify the base register that
+will be used for branches in the @code{.text} section.  A second
+@code{.using} may be specified in another section; this will specify
+the base register that is used for non-label address literals.
+When a second @code{.using} is specified, then the subsequent
+@code{.ltorg} must be put in the same section; otherwise an error will 
+result.
+
+Thus, for example, the following code uses @code{r3} to address branch 
+targets and @code{r4} to address the literal pool, which has been written 
+to the @code{.data} section.  The is, the constants @code{=A(some_routine)},
+@code{=H'42'} and @code{=E'3.1416'} will all appear in the @code{.data}
+section.
+
+@example
+.data
+	.using  LITPOOL,r4
+.text
+	BASR	r3,0
+	.using	*,r3
+        B       START
+	.long	LITPOOL
+START:
+	L	r4,4(,r3)
+	L	r15,=A(some_routine)
+	LTR	r15,r15
+	BNE	LABEL
+	AH	r0,=H'42'
+LABEL:
+	ME	r6,=E'3.1416'
+.data
+LITPOOL:
+	.ltorg
+@end example
+
+
+Note that this dual-@code{.using} directive semantics extends 
+and is not compatible with HLASM semantics.  Note that this assembler 
+directive does not support the full range of HLASM semantics.
+
+@end table
+
+@node ESA/390 Opcodes
+@section Opcodes
+For detailed information on the ESA/390 machine instruction set, see
+@cite{ESA/390 Principles of Operation} (IBM Publication Number DZ9AR004).
diff --git a/gnu/usr.bin/binutils/gas/doc/c-m32r.texi b/gnu/usr.bin/binutils/gas/doc/c-m32r.texi
new file mode 100644
index 00000000000..b733fb30189
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-m32r.texi
@@ -0,0 +1,142 @@
+@c Copyright (C) 1991, 92-98, 1999 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node M32R-Dependent
+@chapter M32R Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter M32R Dependent Features
+@end ifclear
+
+@cindex M32R support
+@menu
+* M32R-Opts::                   M32R Options
+* M32R-Warnings::               M32R Warnings
+@end menu
+
+@node M32R-Opts
+@section M32R Options
+
+@cindex options, M32R
+@cindex M32R options
+
+The Mitsubishi M32R version of @code{@value{AS}} has a few machine
+dependent options:
+
+@table @code
+@item -m32rx
+@cindex @samp{-m32rx} option, M32RX
+@cindex architecture options, M32RX
+@cindex M32R architecture options
+@code{@value{AS}} can assemble code for several different members of the
+Mitsubishi M32R family.  Normally the default is to assemble code for
+the M32R microprocessor.  This option may be used to change the default
+to the M32RX microprocessor, which adds some more instructions to the
+basic M32R instruction set, and some additional parameters to some of
+the original instructions.
+
+@item -m32r
+@cindex @samp{-m32r} option, M32R
+@cindex architecture options, M32R
+@cindex M32R architecture options
+This option can be used to restore the assembler's default behaviour of
+assembling for the M32R microprocessor.  This can be useful if the
+default has been changed by a previous command line option.
+
+@item -warn-explicit-parallel-conflicts
+@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
+Instructs @code{@value{AS}} to produce warning messages when
+questionable parallel instructions are encountered.  This option is
+enabled by default, but @code{@value{GCC}} disables it when it invokes
+@code{@value{AS}} directly.  Questionable instructions are those whoes
+behaviour would be different if they were executed sequentially.  For
+example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
+different result from @samp{mv r1, r2 \n mv r3, r1} since the former
+moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
+and r3.
+
+@item -Wp
+@cindex @samp{-Wp} option, M32RX
+This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts}
+option.
+
+@item -no-warn-explicit-parallel-conflicts
+@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX
+Instructs @code{@value{AS}} not to produce warning messages when
+questionable parallel instructions are encountered.
+
+@item -Wnp
+@cindex @samp{-Wnp} option, M32RX
+This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
+option.
+
+@end table
+
+@node M32R-Warnings
+@section M32R Warnings
+
+@cindex warnings, M32R
+@cindex M32R warnings
+
+There are several warning and error messages that can be produced by
+@code{@value{AS}} which are specific to the M32R:
+
+@table @code
+
+@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
+This message is only produced if warnings for explicit parallel
+conflicts have been enabled.  It indicates that the assembler has
+encountered a parallel instruction in which the destination register of
+the left hand instruction is used as an input register in the right hand
+instruction.  For example in this code fragment
+@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
+move instruction and the input to the neg instruction.
+
+@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
+This message is only produced if warnings for explicit parallel
+conflicts have been enabled.  It indicates that the assembler has
+encountered a parallel instruction in which the destination register of
+the right hand instruction is used as an input register in the left hand
+instruction.  For example in this code fragment
+@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
+neg instruction and the input to the move instruction.
+
+@item instruction @samp{...} is for the M32RX only
+This message is produced when the assembler encounters an instruction
+which is only supported by the M32Rx processor, and the @samp{-m32rx}
+command line flag has not been specified to allow assembly of such
+instructions. 
+
+@item unknown instruction @samp{...}
+This message is produced when the assembler encounters an instruction
+which it doe snot recognise.
+
+@item only the NOP instruction can be issued in parallel on the m32r
+This message is produced when the assembler encounters a parallel
+instruction which does not involve a NOP instruction and the
+@samp{-m32rx} command line flag has not been specified.  Only the M32Rx
+processor is able to execute two instructions in parallel.
+
+@item instruction @samp{...} cannot be executed in parallel.
+This message is produced when the assembler encounters a parallel
+instruction which is made up of one or two instructions which cannot be
+executed in parallel.
+
+@item Instructions share the same execution pipeline
+This message is produced when the assembler encounters a parallel
+instruction whoes components both use the same execution pipeline.
+
+@item Instructions write to the same destination register.
+This message is produced when the assembler encounters a parallel
+instruction where both components attempt to modify the same register.
+For example these code fragments will produce this message:
+@samp{mv r1, r2 || neg r1, r3}
+@samp{jl r0 || mv r14, r1}
+@samp{st r2, @@-r1 || mv r1, r3} 
+@samp{mv r1, r2 || ld r0, @@r1+} 
+@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
+
+@end table
diff --git a/gnu/usr.bin/binutils/gas/doc/c-pj.texi b/gnu/usr.bin/binutils/gas/doc/c-pj.texi
new file mode 100644
index 00000000000..70600157bb4
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-pj.texi
@@ -0,0 +1,28 @@
+@c Copyright (C) 1999 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@page
+@node PJ-Dependent
+@chapter picoJava Dependent Features
+
+@cindex PJ support
+@menu
+* PJ Options::              Options
+@end menu
+
+@node PJ Options
+@section Options
+
+@cindex PJ options
+@cindex options, PJ
+@code{@value{AS}} has two addiitional command-line options for the picoJava
+architecture.
+@table @code
+@item -ml
+This option selects little endian data output.
+
+@item -mb
+This option selects big endian data output.
+@end table
+
+
diff --git a/gnu/usr.bin/binutils/gas/doc/c-v850.texi b/gnu/usr.bin/binutils/gas/doc/c-v850.texi
new file mode 100644
index 00000000000..5416e0f1b8f
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/c-v850.texi
@@ -0,0 +1,363 @@
+@c Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@node V850-Dependent
+@chapter v850 Dependent Features
+
+@cindex V850 support
+@menu
+* V850 Options::              Options
+* V850 Syntax::               Syntax
+* V850 Floating Point::       Floating Point
+* V850 Directives::           V850 Machine Directives
+* V850 Opcodes::              Opcodes
+@end menu
+
+@node V850 Options
+@section Options
+@cindex V850 options (none)
+@cindex options for V850 (none)
+@code{@value{AS}} supports the following additional command-line options
+for the V850 processor family:
+
+@cindex command line options, V850
+@cindex V850 command line options
+@table @code
+
+@cindex @code{-wsigned_overflow} command line option, V850
+@item -wsigned_overflow
+Causes warnings to be produced when signed immediate values overflow the
+space available for then within their opcodes.  By default this option
+is disabled as it is possible to receive spurious warnings due to using
+exact bit patterns as immediate constants.
+
+@cindex @code{-wunsigned_overflow} command line option, V850
+@item -wunsigned_overflow
+Causes warnings to be produced when unsigned immediate values overflow
+the space available for then within their opcodes.  By default this
+option is disabled as it is possible to receive spurious warnings due to
+using exact bit patterns as immediate constants.
+
+@cindex @code{-mv850} command line option, V850
+@item -mv850
+Specifies that the assembled code should be marked as being targeted at
+the V850 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{-mv850e} command line option, V850
+@item -mv850e
+Specifies that the assembled code should be marked as being targeted at
+the V850E processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{-mv850any} command line option, V850
+@item -mv850any
+Specifies that the assembled code should be marked as being targeted at
+the V850 processor but support instructions that are specific to the
+extended variants of the process.  This allows the production of
+binaries that contain target specific code, but which are also intended
+to be used in a generic fashion.  For example libgcc.a contains generic
+routines used by the code produced by GCC for all versions of the v850
+architecture, together with support routines only used by the V850E
+architecture.
+
+@end table
+
+
+@node V850 Syntax
+@section Syntax
+@menu
+* V850-Chars::                Special Characters
+* V850-Regs::                 Register Names
+@end menu
+
+@node V850-Chars
+@subsection Special Characters
+
+@cindex line comment character, V850
+@cindex V850 line comment character
+@samp{#} is the line comment character.
+@node V850-Regs
+@subsection Register Names
+
+@cindex V850 register names
+@cindex register names, V850
+@code{@value{AS}} supports the following names for registers:
+@table @code
+@cindex @code{zero} register, V850
+@item general register 0
+r0, zero
+@item general register 1
+r1
+@item general register 2
+r2, hp
+@cindex @code{sp} register, V850
+@item general register 3
+r3, sp
+@cindex @code{gp} register, V850
+@item general register 4
+r4, gp
+@cindex @code{tp} register, V850
+@item general register 5
+r5, tp
+@item general register 6
+r6
+@item general register 7
+r7
+@item general register 8
+r8
+@item general register 9
+r9
+@item general register 10
+r10
+@item general register 11
+r11
+@item general register 12
+r12
+@item general register 13
+r13
+@item general register 14
+r14
+@item general register 15
+r15
+@item general register 16
+r16
+@item general register 17
+r17
+@item general register 18
+r18
+@item general register 19
+r19
+@item general register 20
+r20
+@item general register 21
+r21
+@item general register 22
+r22
+@item general register 23
+r23
+@item general register 24
+r24
+@item general register 25
+r25
+@item general register 26
+r26
+@item general register 27
+r27
+@item general register 28
+r28
+@item general register 29
+r29
+@cindex @code{ep} register, V850
+@item general register 30
+r30, ep
+@cindex @code{lp} register, V850
+@item general register 31
+r31, lp
+@cindex @code{eipc} register, V850
+@item system register 0
+eipc
+@cindex @code{eipsw} register, V850
+@item system register 1
+eipsw
+@cindex @code{fepc} register, V850
+@item system register 2
+fepc
+@cindex @code{fepsw} register, V850
+@item system register 3
+fepsw
+@cindex @code{ecr} register, V850
+@item system register 4
+ecr
+@cindex @code{psw} register, V850
+@item system register 5
+psw
+@cindex @code{ctpc} register, V850
+@item system register 16
+ctpc
+@cindex @code{ctpsw} register, V850
+@item system register 17
+ctpsw
+@cindex @code{dbpc} register, V850
+@item system register 18
+dbpc
+@cindex @code{dbpsw} register, V850
+@item system register 19
+dbpsw
+@cindex @code{ctbp} register, V850
+@item system register 20
+ctbp
+@end table
+
+@node V850 Floating Point
+@section Floating Point
+
+@cindex floating point, V850 (@sc{ieee})
+@cindex V850 floating point (@sc{ieee})
+The V850 family uses @sc{ieee} floating-point numbers.
+
+@node V850 Directives
+@section V850 Machine Directives
+
+@cindex machine directives, V850
+@cindex V850 machine directives
+@table @code
+@cindex @code{offset} directive, V850
+@item .offset @var{<expression>}
+Moves the offset into the current section to the specified amount. 
+
+@cindex @code{section} directive, V850
+@item .section "name", <type>
+This is an extension to the standard .section directive.  It sets the
+current section to be <type> and creates an alias for this section
+called "name". 
+
+@cindex @code{.v850} directive, V850
+@item .v850
+Specifies that the assembled code should be marked as being targeted at
+the V850 processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{.v850e} directive, V850
+@item .v850e
+Specifies that the assembled code should be marked as being targeted at
+the V850E processor.  This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@end table
+
+@node V850 Opcodes
+@section Opcodes
+
+@cindex V850 opcodes
+@cindex opcodes for V850
+@code{@value{AS}} implements all the standard V850 opcodes.
+
+@code{@value{AS}} also implements the following pseudo ops:
+
+@table @code
+
+@cindex @code{hi0} pseudo-op, V850
+@item hi0()
+Computes the higher 16 bits of the given expression and stores it into
+the immediate operand field of the given instruction.  For example:
+
+    @samp{mulhi hi0(here - there), r5, r6}
+
+computes the difference between the address of labels 'here' and
+'there', takes the upper 16 bits of this difference, shifts it down 16
+bits and then mutliplies it by the lower 16 bits in register 5, putting
+the result into register 6. 
+
+@cindex @code{lo} pseudo-op, V850
+@item lo()
+Computes the lower 16 bits of the given expression and stores it into
+the immediate operand field of the given instruction.  For example:
+
+    @samp{addi lo(here - there), r5, r6}
+
+computes the difference between the address of labels 'here' and
+'there', takes the lower 16 bits of this difference and adds it to
+register 5, putting the result into register 6.
+
+@cindex @code{hi} pseudo-op, V850
+@item hi()
+Computes the higher 16 bits of the given expression and then adds the
+value of the most significant bit of the lower 16 bits of the expression
+and stores the result into the immediate operand field of the given
+instruction.  For example the following code can be used to compute the
+address of the label 'here' and store it into register 6:
+
+    @samp{movhi hi(here), r0, r6}
+    @samp{movea lo(here), r6, r6}
+
+The reason for this special behaviour is that movea performs a sign
+extention on its immediate operand.  So for example if the address of
+'here' was 0xFFFFFFFF then without the special behaviour of the hi()
+pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
+movea instruction would takes its immediate operand, 0xFFFF, sign extend
+it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
+which is wrong (the fifth nibble is E).  With the hi() pseudo op adding
+in the top bit of the lo() pseudo op, the movhi instruction actually
+stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
+stores 0xFFFFFFFF into r6 - the right value.
+
+@cindex @code{hilo} pseudo-op, V850
+@item hilo()
+Computes the 32 bit value of the given expression and stores it into
+the immediate operand field of the given instruction (which must be a
+mov instruction).  For example:
+
+    @samp{mov hilo(here), r6}
+
+computes the absolute address of label 'here' and puts the result into
+register 6.  
+
+@cindex @code{sdaoff} pseudo-op, V850
+@item sdaoff()
+Computes the offset of the named variable from the start of the Small
+Data Area (whoes address is held in register 4, the GP register) and
+stores the result as a 16 bit signed value in the immediate operand
+field of the given instruction.  For example: 
+
+      @samp{ld.w sdaoff(_a_variable)[gp],r6}
+
+loads the contents of the location pointed to by the label '_a_variable'
+into register 6, provided that the label is located somewhere within +/-
+32K of the address held in the GP register.  [Note the linker assumes
+that the GP register contains a fixed address set to the address of the
+label called '__gp'.  This can either be set up automatically by the
+linker, or specifically set by using the @samp{--defsym __gp=<value>}
+command line option].
+
+@cindex @code{tdaoff} pseudo-op, V850
+@item tdaoff()
+Computes the offset of the named variable from the start of the Tiny
+Data Area (whoes address is held in register 30, the EP register) and
+stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
+operand field of the given instruction.  For example:
+
+      @samp{sld.w tdaoff(_a_variable)[ep],r6}
+
+loads the contents of the location pointed to by the label '_a_variable'
+into register 6, provided that the label is located somewhere within +256
+bytes of the address held in the EP register.  [Note the linker assumes
+that the EP register contains a fixed address set to the address of the
+label called '__ep'.  This can either be set up automatically by the
+linker, or specifically set by using the @samp{--defsym __ep=<value>}
+command line option].
+
+@cindex @code{zdaoff} pseudo-op, V850
+@item zdaoff()
+Computes the offset of the named variable from address 0 and stores the
+result as a 16 bit signed value in the immediate operand field of the
+given instruction.  For example:
+
+      @samp{movea zdaoff(_a_variable),zero,r6}
+
+puts the address of the label '_a_variable' into register 6, assuming
+that the label is somewhere within the first 32K of memory.  (Strictly
+speaking it also possible to access the last 32K of memory as well, as
+the offsets are signed).
+
+@cindex @code{ctoff} pseudo-op, V850
+@item ctoff()
+Computes the offset of the named variable from the start of the Call
+Table Area (whoes address is helg in system register 20, the CTBP
+register) and stores the result a 6 or 16 bit unsigned value in the
+immediate field of then given instruction or piece of data.  For
+example:
+
+     @samp{callt ctoff(table_func1)}
+
+will put the call the function whoes address is held in the call table
+at the location labeled 'table_func1'.
+
+@end table
+
+
+For information on the V850 instruction set, see @cite{V850
+Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.
+Ltd.
+
diff --git a/gnu/usr.bin/binutils/gas/doc/gasver.texi b/gnu/usr.bin/binutils/gas/doc/gasver.texi
new file mode 100644
index 00000000000..b696ac718c9
--- /dev/null
+++ b/gnu/usr.bin/binutils/gas/doc/gasver.texi
@@ -0,0 +1 @@
+@set VERSION 2.10