Help stupid cvs fixing basic conflicts.

9 files changed, 3608 insertions, 1367 deletions

diff --git a/gnu/usr.bin/binutils/include/opcode/ChangeLog b/gnu/usr.bin/binutils/include/opcode/ChangeLog
index 907be2031a7..4e8dbf1a6f9 100644
--- a/gnu/usr.bin/binutils/include/opcode/ChangeLog
+++ b/gnu/usr.bin/binutils/include/opcode/ChangeLog
@@ -1,3 +1,1170 @@
+2000-05-23  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* i386.h: Allow d suffix on iret, and add DefaultSize modifier.
+
+2000-05-23  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386.h: Delete redundant fp instruction comments.
+
+	From Gavin Romig-Koch <gavin@cygnus.com>
+	* i386.h (wld_Suf): Define.  Use on pushf, popf, pusha, popa.
+
+2000-05-17  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* i386.h: Use sl_FP, not sl_Suf for fild.
+
+2000-03-27  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (SHORT_A1): Fix value.
+	(SHORT_AR): Renumber so that it is at the end of the list of short
+	instructions, not the end of the list of long instructions.
+
+2000-03-26  Alan Modra  <alan@linuxcare.com>
+
+	* i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the
+	problem isn't really specific to Unixware.
+	(OLDGCC_COMPAT): Define.
+	(i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with
+	destination %st(0).
+	Fix lots of comments.
+
+2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+        * d30v.h:
+        (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
+        (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
+        (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
+        (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
+        (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
+        (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
+        (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
+
+2000-02-25  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (fild, fistp): Change intel d_Suf form to fildd and
+	fistpd without suffix.
+
+2000-02-24  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h (cgen_cpu_desc): Rename field 'flags' to
+        'signed_overflow_ok_p'.
+	Delete prototypes for cgen_set_flags() and cgen_get_flags().
+
+2000-02-24  Andrew Haley  <aph@cygnus.com>
+
+	* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+	(CGEN_CPU_TABLE): flags: new field.
+	Add prototypes for new functions.
+	
+2000-02-24  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add some more UNIXWARE_COMPAT comments.
+
+2000-02-23  Linas Vepstas <linas@linas.org>
+
+	* i370.h: New file.
+
+2000-02-22  Andrew Haley  <aph@cygnus.com>
+
+	* mips.h: (OPCODE_IS_MEMBER): Add comment.
+
+1999-12-30  Andrew Haley  <aph@cygnus.com>
+
+	* mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
+	whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
+	insns.
+
+2000-01-15  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Qualify intel mode far call and jmp with x_Suf.
+
+1999-12-27  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add JumpAbsolute qualifier to all non-intel mode
+	indirect jumps and calls.  Add FF/3 call for intel mode.
+
+Wed Dec  1 03:05:25 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add new operand types.  Add new instruction formats.
+
+Wed Nov 24 20:28:58 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
+	instruction.
+
+1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (INSN_ISA5): New.
+
+1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (OPCODE_IS_MEMBER): New.
+
+1999-10-29  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (SHORT_AR): Define.
+
+1999-10-18  Michael Meissner  <meissner@cygnus.com>
+
+	* alpha.h (alpha_num_opcodes): Convert to unsigned.
+	(alpha_num_operands): Ditto.
+
+Sun Oct 10 01:46:56 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
+
+	* hppa.h (pa_opcodes):  Add load and store cache control to
+	instructions.  Add ordered access load and store.
+
+	* hppa.h (pa_opcode): Add new entries for addb and addib.
+
+	* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
+
+	* hppa.h (pa_opcodes):  Add entries for cmpb and cmpib.
+
+Thu Oct  7 00:12:25 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
+
+	* d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
+
+Thu Sep 23 07:08:38 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Add "call" and "ret".  Clean up "b", "bve"
+	and "be" using completer prefixes.
+
+	* hppa.h (pa_opcodes): Add initializers to silence compiler.
+
+	* hppa.h: Update comments about character usage.
+
+Mon Sep 20 03:55:31 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
+	up the new fstw & bve instructions.
+
+Sun Sep 19 10:40:59 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
+	instructions.
+
+	* hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
+
+	* hppa.h (pa_opcodes): Add long offset double word load/store
+	instructions.
+
+	* hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
+	stores.
+
+	* hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
+
+	* hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
+
+	* hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
+
+	* hppa.h (pa_opcodes): Add new syntax "be" instructions.
+
+	* hppa.h (pa_opcodes): Note use of 'M' and 'L'.
+
+	* hppa.h (pa_opcodes): Add support for "b,l".
+
+	* hppa.h (pa_opcodes): Add support for "b,gate".
+
+Sat Sep 18 11:41:16 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Use 'fX' for first register operand
+	in xmpyu.  
+
+	* hppa.h (pa_opcodes): Fix mask for probe and probei.
+
+	* hppa.h (pa_opcodes): Fix mask for depwi.
+
+Tue Sep  7 13:44:25 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
+	an explicit output argument.
+
+Mon Sep  6 04:41:42 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
+	Add a few PA2.0 loads and store variants.
+
+1999-09-04  Steve Chamberlain  <sac@pobox.com>
+
+	* pj.h: New file.
+
+1999-08-29  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_regtab): Move %st to top of table, and split off
+	other fp reg entries.
+	(i386_float_regtab): To here.
+
+Sat Aug 28 00:25:25 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Replace 'f' by 'v'.  Prefix float register args
+	by 'f'.
+
+	* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
+	Add supporting args.
+
+	* hppa.h:  Document new completers and args.
+	* hppa.h (pa_opcodes):  Add 64 bit patterns and pa2.0 syntax for uxor,
+	uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe.  Add pa2.0
+	extensions for ssm, rsm, pdtlb, pitlb.  Add performance instructions
+	pmenb and pmdis.
+
+	* hppa.h (pa_opcodes):  Add pa2.0 instructions hadd, hshl,
+	hshr, hsub, mixh, mixw, permh.
+
+	* hppa.h (pa_opcodes): Change completers in instructions to
+	use 'c' prefix.
+
+	* hppa.h (pa_opcodes):  Add popbts, new forms of bb, havg,
+	hshladd, hshradd, shrpd, and shrpw instructions.  Update arg comments.
+
+	* hppa.h (pa_opcodes):  Change fmpyfadd, fmpynfadd, fneg,
+	fnegabs to use 'I' instead of 'F'.
+
+1999-08-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
+	Document pf2iw and pi2fw as athlon insns.  Remove pswapw.
+	Alphabetically sort PIII insns.
+
+Wed Aug 18 18:14:40 1999  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+
+Fri Aug  6 09:46:35 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
+	and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
+
+	* hppa.h:  Document 64 bit condition completers.
+
+Thu Aug  5 16:56:07 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Change condition args to use '?' prefix.
+
+1999-08-04  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Add DefaultSize modifier to all insns
+	that implicitly modify %esp.  #undef d_Suf, x_suf, sld_suf,
+	sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
+
+Wed Jul 28 02:04:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+			  Jeff Law <law@cygnus.com>
+
+	* hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
+
+	* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
+
+	* hppa.h (pa_opcodes):  Change xmpyu, fmpyfadd, 
+	and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
+
+1999-07-13  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
+
+Thu Jul  1 00:17:24 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (struct pa_opcode): Add new field "flags".
+	(FLAGS_STRICT): Define.
+
+Fri Jun 25 04:22:04 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+			  Jeff Law <law@cygnus.com>
+
+	* hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
+
+	* hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
+
+1999-06-23  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Allow `l' suffix on bswap.  Allow `w' suffix on arpl,
+	lldt, lmsw, ltr, str, verr, verw.  Add FP flag to fcmov*.  Add FP
+	flag to fcomi and friends.
+
+Fri May 28 15:26:11 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Move integer arithmetic instructions after
+	integer logical instructions.  
+
+1999-05-28  Linus Nordberg  <linus.nordberg@canit.se>
+
+	* m68k.h: Document new formats `E', `G', `H' and new places `N',
+	`n', `o'.
+
+	* m68k.h: Define mcf5206e, mcf5307, mcf.  Document new format `u'
+	and new places `m', `M', `h'.
+
+Thu May 27 04:13:54 1999  Joel Sherrill (joel@OARcorp.com
+
+	* hppa.h (pa_opcodes): Add several processor specific system
+	instructions.
+
+Wed May 26 16:57:44 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add second entry for "comb", "comib", 
+	"addb", and "addib" to be used by the disassembler.
+
+1999-05-12  Alan Modra  <alan@apri.levels.unisa.edu.au>
+
+	* i386.h (ReverseModrm): Remove all occurences.
+	(InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
+	movmskps, pextrw, pmovmskb, maskmovq.
+	Change NoSuf to FP on all MMX, XMM and AMD insns as these all
+	ignore the data size prefix.
+
+	* i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
+	Mostly stolen from Doug Ledford <dledford@redhat.com>
+
+Sat May  8 23:27:35 1999  Richard Henderson  <rth@cygnus.com>
+
+	* ppc.h (PPC_OPCODE_64_BRIDGE): New.
+
+1999-04-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ATTR): Delete member num_nonbools.
+	(CGEN_ATTR_TYPE): Update.
+	(CGEN_ATTR_MASK): Number booleans starting at 0.
+	(CGEN_ATTR_VALUE): Update.
+	(CGEN_INSN_ATTR): Update.
+
+Mon Apr 12 23:43:27 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
+	instructions.
+
+Tue Mar 23 11:24:38 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (bb, bvb): Tweak opcode/mask.
+
+
+1999-03-22  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
+	(struct cgen_cpu_desc): Rename member mach to machs.  New member isas.
+	New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
+	min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
+	Delete member max_insn_size.
+	(enum cgen_cpu_open_arg): New enum.
+	(cpu_open): Update prototype.
+	(cpu_open_1): Declare.
+	(cgen_set_cpu): Delete.
+
+1999-03-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
+	(CGEN_OPERAND_NIL): New macro.
+	(CGEN_OPERAND): New member `type'.
+	(@arch@_cgen_operand_table): Delete decl.
+	(CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
+	(CGEN_OPERAND_TABLE): New struct.
+	(cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
+	(CGEN_OPINST): Pointer to operand table entry replaced with enum.
+	(CGEN_CPU_TABLE): New member `isa'.  Change member `operand_table',
+	now a CGEN_OPERAND_TABLE.  Add CGEN_CPU_DESC arg to
+	{get,set}_{int,vma}_operand.
+	(@arch@_cgen_cpu_open): New arg `isa'.
+	(cgen_set_cpu): Ditto.
+
+Fri Feb 26 02:36:45 1999  Richard Henderson  <rth@cygnus.com>
+
+	* i386.h: Fill in cmov and fcmov alternates.  Add fcomi short forms.
+
+1999-02-25  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
+	(CGEN_HW_ENTRY): Delete member `next'.  Change type of `type' to
+	enum cgen_hw_type.
+	(CGEN_HW_TABLE): New struct.
+	(hw_table): Delete declaration.
+	(CGEN_OPERAND): Change member hw to hw_type, change type from pointer
+	to table entry to enum.
+	(CGEN_OPINST): Ditto.
+	(CGEN_CPU_TABLE): Change member hw_list to hw_table.
+
+Sat Feb 13 14:13:44 1999  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.h (AXP_OPCODE_EV6): New.
+	(AXP_OPCODE_NOPAL): Include it.
+
+1999-02-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
+	All uses updated.  New members int_insn_p, max_insn_size,
+	parse_operand,insert_operand,extract_operand,print_operand,
+	sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
+	get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
+	extract_handlers,print_handlers.
+	(CGEN_ATTR): Change type of num_nonbools to unsigned int.
+	(CGEN_ATTR_BOOL_OFFSET): New macro.
+	(CGEN_ATTR_MASK): Subtract it to compute bit number.
+	(CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
+	(cgen_opcode_handler): Renamed from cgen_base.
+	(CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
+	(CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
+	all uses updated.
+	(CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
+	(enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
+	(CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
+	(CGEN_OPCODE,CGEN_IBASE): New types.
+	(CGEN_INSN): Rewrite.
+	(CGEN_{ASM,DIS}_HASH*): Delete.
+	(init_opcode_table,init_ibld_table): Declare.
+	(CGEN_INSN_ATTR): New type.
+
+Mon Feb  1 21:09:14 1999  Catherine Moore  <clm@cygnus.com>
+ 
+        * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf):  Define.
+        (x_FP, d_FP, dls_FP, sldx_FP):  Define.
+        Change *Suf definitions to include x and d suffixes.
+        (movsx):  Use w_Suf and b_Suf.
+        (movzx):  Likewise.
+        (movs):  Use bwld_Suf.
+        (fld):  Change ordering.  Use sld_FP.
+        (fild):  Add Intel Syntax equivalent of fildq.
+        (fst):  Use sld_FP.
+        (fist):  Use sld_FP.
+        (fstp):  Use sld_FP.  Add x_FP version.
+        (fistp):  LLongMem version for Intel Syntax.
+        (fcom, fcomp):  Use sld_FP.
+        (fadd, fiadd, fsub):  Use sld_FP.
+        (fsubr):  Use sld_FP.
+        (fmul, fimul, fdvi, fidiv, fdivr):  Use sld_FP.
+
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
+	CGEN_MODE_UINT.
+
+Sat Jan 16 01:29:25 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (bv): Fix mask.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
+	(CGEN_ATTR): Use it.
+	(CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
+	(CGEN_ATTR_TABLE): New member dfault.
+
+1998-12-30  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (MIPS16_INSN_BRANCH): New.
+
+Wed Dec  9 10:38:48 1998  David Taylor  <taylor@texas.cygnus.com>
+
+	The following is part of a change made by Edith Epstein
+ 	<eepstein@sophia.cygnus.com> as part of a project to merge in
+ 	changes by HP; HP did not create ChangeLog entries.
+
+	* hppa.h (completer_chars): list of chars to not put a space
+ 	after.
+
+Sun Dec  6 13:21:34 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (i386_optab): Permit w suffix on processor control and
+ 	status word instructions.
+
+1998-11-30  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (struct cgen_hw_entry): Delete const on attrs member.
+	(struct cgen_keyword_entry): Ditto.
+	(struct cgen_operand): Ditto.
+	(CGEN_IFLD): New typedef, with associated access macros.
+	(CGEN_IFMT): New typedef, with associated access macros.
+	(CGEN_IFMT): Renamed from CGEN_FORMAT.  New member `iflds'.
+	(CGEN_IVALUE): New typedef.
+	(struct cgen_insn): Delete const on syntax,attrs members.
+	`format' now points to format data.  Type of `value' is now
+	CGEN_IVALUE.
+	(struct cgen_opcode_table): New member ifld_table.
+
+1998-11-18  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
+	(CGEN_OPERAND_INSTANCE): New member `attrs'.
+	(CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
+	(cgen_dis_lookup_insn): Update type of `base_insn' arg.
+	(cgen_opcode_table): Update type of dis_hash fn.
+	(extract_operand): Update type of `insn_value' arg.
+
+Thu Oct 29 11:38:36 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
+
+Tue Oct 27 08:57:59 1998  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (INSN_MULT): Added.
+
+Tue Oct 20 11:31:34 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
+
+Mon Oct 19 12:50:00 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_INSN_INT): New typedef.
+	(CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
+	(CGEN_INSN_BYTES): Renamed from cgen_insn_t.
+	(CGEN_INSN_BYTES_PTR): New typedef.
+	(CGEN_EXTRACT_INFO): New typedef.
+	(cgen_insert_fn,cgen_extract_fn): Update.
+	(cgen_opcode_table): New member `insn_endian'.
+	(assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
+	(insert_operand,extract_operand): Update.
+	(cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
+
+Fri Oct  9 13:38:13 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_BOOLS): New macro.
+	(struct CGEN_HW_ENTRY): New member `attrs'.
+	(CGEN_HW_ATTR): New macro.
+	(struct CGEN_OPERAND_INSTANCE): New member `name'.
+	(CGEN_INSN_INVALID_P): New macro.
+
+Mon Oct  5 00:21:07 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add "fid".
+	
+Sun Oct  4 21:00:00 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	From Robert Andrew Dale <rob@nb.net>
+	* i386.h (i386_optab): Add AMD 3DNow! instructions.
+	(AMD_3DNOW_OPCODE): Define.
+
+Tue Sep 22 17:53:47 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (EITHER_BUT_PREFER_MU): Define.
+
+Mon Aug 10 14:09:38 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (cgen_insn): #if 0 out element `cdx'.
+
+Mon Aug  3 12:21:57 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	Move all global state data into opcode table struct, and treat
+	opcode table as something that is "opened/closed".
+	* cgen.h (CGEN_OPCODE_DESC): New type.
+	(all fns): New first arg of opcode table descriptor.
+	(cgen_set_parse_operand_fn): Add prototype.
+	(cgen_current_machine,cgen_current_endian): Delete.
+	(CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
+	parse_operand_fn,asm_hash_table,asm_hash_table_entries,
+	dis_hash_table,dis_hash_table_entries.
+	(opcode_open,opcode_close): Add prototypes.
+
+	* cgen.h (cgen_insn): New element `cdx'.
+
+Thu Jul 30 21:44:25 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+	* d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
+
+Tue Jul 28 10:59:07 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add "no_match_operands" field for instructions.
+	(MN10300_MAX_OPERANDS): Define.
+
+Fri Jul 24 11:44:24 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (cgen_macro_insn_count): Declare.
+
+Tue Jul 21 13:12:13 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
+	(cgen_insert_fn,cgen_extract_fn): New arg `pc'.
+	(get_operand,put_operand): Replaced with get_{int,vma}_operand,
+	set_{int,vma}_operand.
+
+Fri Jun 26 11:09:06 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add "machine" field for instructions.
+	(MN103, AM30): Define machine types.
+	
+Fri Jun 19 16:09:09 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
+
+1998-06-18  Ulrich Drepper  <drepper@cygnus.com>
+
+	* i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
+
+Sat Jun 13 11:31:35 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Add general form of aad and aam.  Add ud2a
+	and ud2b.
+	(i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
+	those that happen to be implemented on pentiums.
+
+Tue Jun  9 12:16:01 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Change occurences of Data16 to Size16, Data32 to Size32,
+	IgnoreDataSize to IgnoreSize.  Flag address and data size prefixes
+	with Size16|IgnoreSize or Size32|IgnoreSize.
+
+Mon Jun  8 12:15:52 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
+	(REPE): Rename to REPE_PREFIX_OPCODE.
+	(i386_regtab_end): Remove.
+	(i386_prefixtab, i386_prefixtab_end): Remove.
+	(i386_optab): Use NULL as sentinel rather than "" to suit rewrite
+	of md_begin.
+	(MAX_OPCODE_SIZE): Define.
+	(i386_optab_end): Remove.
+	(sl_Suf): Define.
+	(sl_FP): Use sl_Suf.
+
+	* i386.h (i386_optab): Allow 16 bit displacement for `mov
+	mem,acc'.  Combine 16 and 32 bit forms of various insns.  Allow 16
+	bit form of ljmp.  Add IsPrefix modifier to prefixes.  Add addr32,
+	data32, dword, and adword prefixes.
+	(i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
+	regs.
+
+Fri Jun  5 23:42:43 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_regtab): Remove BaseIndex modifier from esp.
+
+	* i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with
+	register operands, because this is a common idiom.  Flag them with
+	a warning.  Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp,
+	fdivrp because gcc erroneously generates them.  Also flag with a
+	warning.
+
+	* i386.h: Add suffix modifiers to most insns, and tighter operand
+	checks in some cases.  Fix a number of UnixWare compatibility
+	issues with float insns.  Merge some floating point opcodes, using
+	new FloatMF modifier.
+	(WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for
+	consistency.
+
+	* i386.h: Change occurence of ShortformW to W|ShortForm.  Add
+	IgnoreDataSize where appropriate.
+
+Wed Jun  3 18:28:45 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: (one_byte_segment_defaults): Remove.
+	(two_byte_segment_defaults): Remove.
+	(i386_regtab): Add BaseIndex to 32 bit regs reg_type.
+
+Fri May 15 15:59:04 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
+	(cgen_hw_lookup_by_num): Declare.
+
+Thu May  7 09:27:58 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+	* mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower
+	ten bits of MIPS ISA1 "break" instruction, and for "sdbbp"
+
+Thu May  7 02:14:08 1998  Doug Evans  <devans@charmed.cygnus.com>
+
+	* cgen.h (cgen_asm_init_parse): Delete.
+	(cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete.
+	(cgen_asm_record_register,cgen_asm_finish_insn): Delete.
+
+Mon Apr 27 10:13:11 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses.
+	(cgen_asm_finish_insn): Update prototype.
+	(cgen_insn): New members num, data.
+	(CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size,
+	dis_hash, dis_hash_table_size moved to ...
+	(CGEN_OPCODE_TABLE).  Here.  Renamed from CGEN_OPCODE_DATA.
+	All uses updated.  New members asm_hash_p, dis_hash_p.
+	(CGEN_MINSN_EXPANSION): New struct.
+	(cgen_expand_macro_insn): Declare.
+	(cgen_macro_insn_count): Declare.
+	(get_insn_operands): Update prototype.
+	(lookup_get_insn_operands): Declare.
+
+Tue Apr 21 17:11:32 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Change iclrKludge and imulKludge to
+	regKludge.  Add operands types for string instructions.
+
+Mon Apr 20 14:40:29 1998  Tom Tromey  <tromey@cygnus.com>
+
+	* i386.h (X): Renamed from `Z_' to preserve formatting of opcode
+	table.
+
+Sun Apr 19 13:54:06 1998  Tom Tromey  <tromey@cygnus.com>
+
+	* i386.h (Z_): Renamed from `_' to avoid clash with common alias
+	for `gettext'.
+
+Fri Apr  3 12:04:48 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Remove NoModrm flag from all insns: it's never checked.
+	Add IsString flag to string instructions.
+	(IS_STRING): Don't define.
+	(LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define.
+	(ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define.
+	(SS_PREFIX_OPCODE): Define.
+
+Mon Mar 30 21:31:56 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert March 24 patch; no more LinearAddress.
+
+Mon Mar 30 10:25:54 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Remove fwait (9b) from all floating point
+	instructions, and instead add FWait opcode modifier.  Add short
+	form of fldenv and fstenv.
+	(FWAIT_OPCODE): Define.
+
+	* i386.h (i386_optab): Change second operand constraint of `mov
+	sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to
+	allow legal instructions such as `movl %gs,%esi'
+
+Fri Mar 27 18:30:52 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* h8300.h: Various changes to fully bracket initializers.
+
+Tue Mar 24 18:32:47 1998  H.J. Lu  <hjl@gnu.org>
+
+	* i386.h: Set LinearAddress for lidt and lgdt.
+
+Mon Mar  2 10:44:07 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_BOOL_ATTR): New macro.
+
+Thu Feb 26 15:54:31 1998  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (FLAG_DELAY): New flag for delayed branches/jumps.
+
+Mon Feb 23 10:38:21 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_CAT3): Delete.  Use CONCAT3 now.
+	(cgen_insn): Record syntax and format entries here, rather than
+	separately.
+
+Tue Feb 17 21:42:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro.
+
+Tue Feb 17 16:00:56 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (cgen_insert_fn): Change type of result to const char *.
+	(cgen_parse_{signed,unsigned}_integer): Delete min,max arguments.
+	(CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS.
+
+Thu Feb 12 18:30:41 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (lookup_insn): New argument alias_p.
+
+Thu Feb 12 03:41:00 1998  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+Fix rac to accept only a0:
+	* d10v.h (OPERAND_ACC): Split into:
+	(OPERAND_ACC0, OPERAND_ACC1) .
+	(OPERAND_GPR): Define.
+
+Wed Feb 11 17:31:53 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_FIELDS): Define here.
+	(CGEN_HW_ENTRY): New member `type'.
+	(hw_list): Delete decl.
+	(enum cgen_mode): Declare.
+	(CGEN_OPERAND): New member `hw'.
+	(enum cgen_operand_instance_type): Declare.
+	(CGEN_OPERAND_INSTANCE): New type.
+	(CGEN_INSN): New member `operands'.
+	(CGEN_OPCODE_DATA): Make hw_list const.
+	(get_insn_operands,lookup_insn): Add prototypes for.
+
+Tue Feb  3 17:11:23 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS.
+	(CGEN_HW_ENTRY): Move `next' entry to end of struct.
+	(CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS.
+	(CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS.
+
+Mon Feb  2 19:19:15 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* cgen.h: Correct typo in comment end marker.
+
+Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* tic30.h: New file.
+
+Thu Jan 22 17:54:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Add prototypes for cgen_save_fixups(),
+	cgen_restore_fixups(), and cgen_swap_fixups().  Change prototype
+	of cgen_asm_finish_insn() to return a char *.
+
+Wed Jan 14 17:21:43 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Formatting changes to improve readability.
+
+Mon Jan 12 11:37:36 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (*): Clean up pass over `struct foo' usage.
+	(CGEN_ATTR): Make unsigned char.
+	(CGEN_ATTR_TYPE): Update.
+	(CGEN_ATTR_{ENTRY,TABLE}): New types.
+	(cgen_base): Move member `attrs' to cgen_insn.
+	(CGEN_KEYWORD): New member `null_entry'.
+	(CGEN_{SYNTAX,FORMAT}): New types.
+	(cgen_insn): Format and syntax separated from each other.
+
+Tue Dec 16 15:15:52 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for
+	2 word load/store, ADDppp/SUBppp, 16/32 bit multiply.  Make
+	flags_{used,set} long.
+	(d30v_operand): Make flags field long.
+
+Mon Dec  1 12:24:44 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* m68k.h: Fix comment describing operand types.
+
+Sun Nov 23 22:31:27 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move
+	everything else after down.
+
+Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+	* d10v.h (OPERAND_FLAG): Split into:
+	(OPERAND_FFLAG, OPERAND_CFLAG) .
+
+Thu Nov 13 11:04:24 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): Changed comments to reflect new
+	field usage.
+
+Fri Oct 24 22:36:20 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	* mips.h: Added to comments a quick-ref list of all assigned
+	operand type characters.
+	(OP_{MASK,SH}_PERFREG): New macros.
+
+Wed Oct 22 17:28:33 1997  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h: Add '_' and '/' for v9a asr's.
+	Patch from David Miller <davem@vger.rutgers.edu>
+
+Tue Oct 14 13:22:29 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h: Bit ops with absolute addresses not in the 8 bit
+	area are not available in the base model (H8/300).
+
+Thu Sep 25 13:03:41 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Remove documentation of ` operand specifier.
+
+Wed Sep 24 19:00:34 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Document q and v operand specifiers.
+
+Mon Sep 15 18:28:37 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add processors field.
+	(PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
+	(PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants.
+	(PROCESSOR_V850EA): New bit constants.
+
+Mon Sep 15 11:29:43 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	Merge changes from Martin Hunt:
+
+	* d30v.h: Allow up to 64 control registers. Add
+	SHORT_A5S format.
+
+	* d30v.h (LONG_Db): New form for delayed branches.
+
+	* d30v.h: (LONG_Db): New form for repeati.
+
+	* d30v.h (SHORT_D2B): New form.
+
+	* d30v.h (SHORT_A2): New form.
+
+	* d30v.h (OPERAND_2REG): Add new operand to indicate 2
+	registers are used.  Needed for VLIW optimization.
+
+Mon Sep  8 14:05:45 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: Move assembler interface section
+	up so cgen_parse_operand_result is defined for cgen_parse_address.
+	(cgen_parse_address): Update prototype.
+
+Tue Sep  2 15:32:32 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
+
+Tue Aug 26 12:21:52 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (two_byte_segment_defaults): Correct base register 5 in
+	modes 1 and 2 to be ss rather than ds.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Set ud2 to 0x0f0b.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
+	(JUMP_ON_ECX_ZERO): Remove commented out macro.
+
+Fri Aug 22 10:38:29 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_NOT_R0): New flag.
+
+Mon Aug 18 11:05:58 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Remove flags field.
+
+Wed Aug 13 18:45:48 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add flags field.
+	(struct v850_operand): Extend meaning of 'bits' and 'shift'
+	fields.
+	(V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
+	(V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags.
+
+Fri Aug  8 16:58:42 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h: New file.
+
+Thu Jul 24 21:16:58 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_opcodes): Declare as const.
+
+Thu Jul 10 12:53:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mips.h (FP_S, FP_D): Define.  Bitmasks indicating if an insn
+	uses single or double precision floating point resources.
+	(INSN_NO_ISA, INSN_ISA1): Define.
+	(cpu specific INSN macros): Tweak into bitmasks outside the range
+	of INSN_ISA field.
+
+Mon Jun 16 14:10:00 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Fix pand opcode.
+
+Mon Jun  2 11:35:09 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h: Widen INSN_ISA and move it to a more convenient
+	bit position.  Add INSN_3900.
+
+Tue May 20 11:25:29 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): added new field membership.
+
+Mon May 12 16:26:50 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h (movd): only Reg32 is allowed.
+
+	* i386.h: add fcomp and ud2.  From Wayne Scott
+	<wscott@ichips.intel.com>.
+
+Mon May  5 17:16:21 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add MMX instructions.
+
+Mon May  5 12:45:19 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Remove W modifier from conditional move instructions.
+
+Mon Apr 14 14:56:58 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
+	with no arguments to match that generated by the UnixWare
+	assembler.
+
+Thu Apr 10 14:35:00 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
+	(cgen_parse_operand_fn): Declare.
+	(cgen_init_parse_operand): Declare.
+	(cgen_parse_operand): Renamed from cgen_asm_parse_operand,
+	new argument `want'.
+	(enum cgen_parse_operand_result): Renamed from cgen_asm_result.
+	(enum cgen_parse_operand_type): New enum.
+
+Sat Apr  5 13:14:05 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
+
+Fri Apr  4 11:46:11 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: New file.
+
+Fri Apr  4 14:02:32 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
+	fdivrp.
+
+Tue Mar 25 22:57:26 1997  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h (extract):  Make unsigned.
+
+Mon Mar 24 14:38:15 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add iclr.
+
+Thu Mar 20 19:49:10 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change DW to W for cmpxchg and xadd, since they don't
+	take a direction bit.
+
+Sat Mar 15 19:03:29 1997  H.J. Lu  <hjl@lucon.org>
+
+	* sparc.h (sparc_opcode_lookup_arch): Use full prototype.
+
+Fri Mar 14 15:22:01 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sparc.h: Include <ansidecl.h>.  Update function declarations to
+	use prototypes, and to use const when appropriate.
+
+Thu Mar  6 14:18:30 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_RELAX): Define.
+
+Mon Feb 24 15:15:56 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Change pre_defined_registers to
+	d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+Sat Feb 22 21:25:00 1997  Dawn Perchik  <dawn@cygnus.com>
+
+	* mips.h: Add macros for cop0, cop1 cop2 and cop3.
+	Change mips_opcodes from const array to a pointer,
+	and change bfd_mips_num_opcodes from const int to int,
+	so that we can increase the size of the mips opcodes table
+	dynamically.
+
+Fri Feb 21 16:34:18 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d30v.h (FLAG_X): Remove unused flag.
+
+Tue Feb 18 17:37:20 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d30v.h: New file.
+
+Fri Feb 14 13:16:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (PDS_NAME): Macro to access name field of predefined symbols.
+	(PDS_VALUE): Macro to access value field of predefined symbols.
+	(tic80_next_predefined_symbol): Add prototype.
+
+Mon Feb 10 10:32:17 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (tic80_symbol_to_value): Change prototype to match
+	change in function, added class parameter.
+
+Thu Feb  6 17:30:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
+	endmask fields, which are somewhat weird in that 0 and 32 are
+	treated exactly the same.
+
+Thu Jan 30 13:46:18 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h: Change all the OPERAND defines to use the form (1 << X)
+	rather than a constant that is 2**X.  Reorder them to put bits for
+	operands that have symbolic names in the upper bits, so they can
+	be packed into an int where the lower bits contain the value that
+	corresponds to that symbolic name.
+	(predefined_symbo): Add struct.
+	(tic80_predefined_symbols): Declare array of translations.
+	(tic80_num_predefined_symbols): Declare size of that array.
+	(tic80_value_to_symbol): Declare function.
+	(tic80_symbol_to_value): Declare function.
+
+Wed Jan 29 09:37:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_RELAX): Define.
+
+Sat Jan 18 15:18:59 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
+	be the destination register.
+
+Thu Jan 16 20:48:55 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (struct tic80_opcode): Change "format" field to "flags".
+	(FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
+	(TIC80_VECTOR): Define a flag bit for the flags.  This one means
+	that the opcode can have two vector instructions in a single
+	32 bit word and we have to encode/decode both.
+
+Tue Jan 14 19:37:09 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_PCREL): Renamed from
+	TIC80_OPERAND_RELATIVE for PC relative.
+	(TIC80_OPERAND_BASEREL): New flag bit for register
+	base relative.
+
+Mon Jan 13 15:56:38 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands.
+
+Mon Jan  6 10:51:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_SCALED): Operand may have optional
+	":s" modifier for scaling.
+
+Sun Jan  5 12:12:19 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m".
+	(TIC80_OPERAND_M_LI): Ditto
+
+Sat Jan  4 19:02:44 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ.
+	(TIC80_OPERAND_CC): New define for condition code operand.
+	(TIC80_OPERAND_CR): New define for control register operand.
+
+Fri Jan  3 16:22:23 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (struct tic80_opcode): Name changed.
+	(struct tic80_opcode): Remove format field.
+	(struct tic80_operand): Add insertion and extraction functions.
+	(TIC80_OPERAND_*): Remove old bogus values, start adding new
+	correct ones.
+	(FMT_*): Ditto.
+
+Tue Dec 31 15:05:41 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
+	type IV instruction offsets.
+
+Fri Dec 27 22:23:10 1996  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h: New file.
+
+Wed Dec 18 10:06:31 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_NOCHECK): Define.
+
+Sat Dec 14 10:48:31 1996  Fred Fish  <fnf@ninemoons.com>
+
+	* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
+	* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
+	* v850.h: Fix comment, v850_operand not powerpc_operand.
+
+Mon Dec  9 16:45:39 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h: Flesh out structures and definitions needed by
+	the mn10200 assembler & disassembler.
+
+Tue Nov 26 10:46:56 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h: Add mips16 definitions.
+
+Mon Nov 25 17:56:54 1996  J.T. Conklin  <jtc@cygnus.com>
+
+	* m68k.h: Document new <, >, m, n, o and p operand specifiers.
+
+Wed Nov 20 10:59:41 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_PCREL): Define.
+	(MN10300_OPERAND_MEMADDR): Define.
+
+Tue Nov 19 13:30:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_REG_LIST): Define.
+
 Wed Nov  6 13:41:08 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300.h (MN10300_OPERAND_SPLIT): Define.
@@ -18,6 +1185,10 @@ Fri Nov  1 10:31:02 1996  Richard Henderson  <rth@tamu.edu>
  	implementation.
 	(struct alpha_operand): Move flags slot for better packing.
 
+Tue Oct 29 12:19:10 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_RELAX): New operand flag.
+
 Thu Oct 10 14:29:11 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300.h (FMT_*): Move operand format definitions
@@ -41,10 +1212,42 @@ Wed Oct  2 21:31:26 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10x00.h: New file.
 
+Fri Sep 27 18:26:46 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h:  Add new flag to indicate this instruction uses a PC
+	displacement.
+
 Fri Sep 13 14:58:13 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* h8300.h (stmac): Add missing instruction.
 
+Sat Aug 31 16:02:03 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (v850_opcode): Remove "size" field.  Add "memop"
+	field.
+
+Fri Aug 23 10:39:08 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_EP): Define.
+
+	* v850.h (v850_opcode): Add size field.
+
+Thu Aug 22 16:51:25 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add insert and extract fields, pointers
+ 	to functions used to handle unusual operand encoding.
+	(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
+ 	V850_OPERAND_SIGNED): Defined.
+
+Wed Aug 21 17:45:10 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add flags field.
+	(OPERAND_REG, OPERAND_NUM): Defined.
+
+Tue Aug 20 14:52:02 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h: New file.
+
 Fri Aug 16 14:44:15 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
@@ -59,6 +1262,11 @@ Fri Aug 16 00:15:15 1996  Jeffrey A Law  (law@cygnus.com)
 	* hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
 	a 3 bit space id instead of a 2 bit space id.
 
+Thu Aug 15 13:11:46 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Add some additional defines to support the
+ 	assembler in determining which operations can be done in parallel.
+
 Tue Aug  6 11:13:22 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* h8300.h (SN): Define.
@@ -66,11 +1274,29 @@ Tue Aug  6 11:13:22 1996  Jeffrey A Law  (law@cygnus.com)
 	(nop, bpt, rte, rts, sleep, clrmac): These have no size associated
 	with them.
 
+Fri Jul 26 11:47:10 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (OPERAND_SHIFT): New operand flag.
+
+Thu Jul 25 12:06:22 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Changes for divs, parallel-only instructions, and
+ 	signed numbers.
+
+Mon Jul 22 11:21:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (pd_reg): Define. Putting the definition here allows
+	the assembler and disassembler to share the same struct.
+
 Mon Jul 22 12:15:25 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* i960.h (i960_opcodes): "halt" takes an argument.  From Stephen
 	Williams <steve@icarus.com>.
 
+Wed Jul 17 14:46:38 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: New file.
+
 Thu Jul 11 12:09:15 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* h8300.h (band, bclr): Force high bit of immediate nibble to zero.
@@ -111,7 +1337,7 @@ Tue Jun 18 16:06:00 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
 	(EBITOP): Likewise.
 	(O_LAST): Bump.
 	(ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
-	
+
 	* h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
 	(O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
 	(BITOP, EBITOP): Handle new H8/S addressing modes for
@@ -119,7 +1345,7 @@ Tue Jun 18 16:06:00 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
 	(UNOP3): Handle new shift/rotate insns on the H8/S.
 	(insns using exr): New instructions.
 	(tas, mac, ldmac, clrmac, ldm, stm): New instructions.
-	
+
 Thu May 23 16:56:48 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* h8300.h (add.l): Undo Apr 5th change.  The manual I had
@@ -282,14 +1508,12 @@ Wed Jun 21 18:49:51 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 	[!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
 	(m68k_opcode_aliases): Add more aliases.
 
-
 Fri Apr 14 22:15:34 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	* m68k.h: Added explcitly short-sized conditional branches, and a
 	bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
 	svr4-based configurations.
 
-
 Mon Mar 13 21:30:01 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	Mon Feb 27 08:36:39 1995  Bryan Ford  <baford@cs.utah.edu>
@@ -318,7 +1542,6 @@ Wed Mar  8 03:13:23 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 	[DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
 	m68k_opcode_aliases; update declaration of m68k_opcodes.
 
-
 Mon Mar  6 10:02:00 1995  Jeff Law  (law@snake.cs.utah.edu)
 
 	* hppa.h (delay_type): Delete unused enumeration.
@@ -342,7 +1565,6 @@ Wed Feb 15 12:19:52 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
 
-
 Mon Feb  6 10:35:23 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* i386.h: added cpuid instruction , and dr[0-7] aliases for the
@@ -373,8 +1595,6 @@ Tue Jan 17 10:55:30 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* mips.h (INSN_ISA, INSN_4650): Define.
 
-
-
 Wed Oct 19 13:34:17 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* a29k.h: Add operand type 'I' for `inv' and `iretinv'.  On
@@ -413,7 +1633,7 @@ Sun Jul 10 11:01:09 1994  Ian Dall  (dall@hfrd.dsto.gov.au)
 
 Thu Jul  7 12:34:48 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
 
-	* h8300.h (xor.l) :fix bit pattern. 
+	* h8300.h (xor.l) :fix bit pattern.
 	(L_2): New size of operand.
 	(trapa): Use it.
 
@@ -514,7 +1734,7 @@ Sat Dec 11 16:14:06 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
 
 Wed Dec  1 12:15:32 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
 
-	* From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>     
+	* From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
 	* hppa.h: #undef NONE to avoid conflict with hiux include files.
 
 Sun Nov 21 22:06:57 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
@@ -667,11 +1887,11 @@ Fri Jun 11 18:38:44 1993  Ken Raeburn  (raeburn@cygnus.com)
 	Patches from Jeff Law, law@cs.utah.edu:
 	* hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
 	Make the tables be the same for the following instructions:
-	"bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", 
+	"bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
 	"sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
-	"ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", 
-	"comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", 
-	"frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", 
+	"ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
+	"comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
+	"frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
 	"fcmp", and "ftest".
 
 	* hppa.h: Make new and old tables the same for "break", "mtctl",
@@ -692,7 +1912,7 @@ Fri Jun  4 15:41:37 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
 Thu Jun  3 15:42:59 1993  Stu Grossman  (grossman@cygnus.com)
 
 	* Patches from Jeffrey Law <law@cs.utah.edu>.
-	* hppa.h: Rework single precision FP 
+	* hppa.h: Rework single precision FP
 	instructions so that they correctly disassemble code
 	PA1.1 code.
 
@@ -739,7 +1959,7 @@ Thu Feb 18 02:03:14 1993  John Gilmore  (gnu@cygnus.com)
 
 	* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART):  Add kludge which
 	allows callers to break up the large initialized struct full of
-	opcodes into two half-sized ones.  This permits GCC to compile 
+	opcodes into two half-sized ones.  This permits GCC to compile
 	this module, since it takes exponential space for initializers.
 	(numopcodes, endop):  Revise to use AND_OTHER_PART in size calcs.
 
@@ -962,7 +2182,7 @@ Tue Dec 10 00:22:20 1991  K. Richard Pixley  (rich at rtl.cygnus.com)
 
 Sat Nov 30 20:40:51 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
 
-	* a29k.h, arm.h, h8300.h,  i386.h,  i860.h, i960.h , m68k.h, 
+	* a29k.h, arm.h, h8300.h,  i386.h,  i860.h, i960.h , m68k.h,
 	m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
 	vax.h, ChangeLog: renamed from ../<foo>-opcode.h
 
diff --git a/gnu/usr.bin/binutils/include/opcode/h8300.h b/gnu/usr.bin/binutils/include/opcode/h8300.h
index c9cf9e250cd..3a05e4ee21c 100644
--- a/gnu/usr.bin/binutils/include/opcode/h8300.h
+++ b/gnu/usr.bin/binutils/include/opcode/h8300.h
@@ -1,5 +1,5 @@
 /* Opcode table for the H8-300
-   Copyright (C) 1991,1992 Free Software Foundation.
+   Copyright (C) 1991, 92, 93, 95, 96, 97, 1998 Free Software Foundation.
    Written by Steve Chamberlain, sac@cygnus.com.
    
    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
@@ -16,7 +16,8 @@
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
 
 /* Instructions are stored as a sequence of nibbles.
    If the nibble has value 15 or less then the representation is complete.
@@ -158,11 +159,11 @@ struct h8_opcode
 #ifdef DEFINE_TABLE
 
 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
-{ code, 1, 2, name,	{imm,RD8,E},	{op00, op01, imm, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0},\
-{ code, 1, 6, name,	{imm,RDIND,E},	{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}, 0, 0, 0, 0},\
-{ code, 1, 6, name,	{imm,ABS8DST,E},{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0}\
-,{ code, 1, 6, name,	{imm,ABS16DST,E},{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0},\
-{ code, 1, 6, name,	{imm,ABS32DST,E},{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0}
+{ code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
+{ code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
+{ code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
+,{ code, 0, 6, name,	{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
+{ code, 0, 6, name,	{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
 
 
 #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
@@ -170,11 +171,11 @@ struct h8_opcode
    BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)
 
 #define WTWOP(code,name, op1, op2) \
-{ code, 1, 2, name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E, 0, 0, 0, 0}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
 
 #define BRANCH(code, name, op) \
-{ code, 1, 4,name,{DISP8,E,0}, { 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
-{ code, 0, 6,name,{DISP16,E,0}, { 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}, 0, 0, 0, 0} 
+{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
+{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0} 
 
 #define SOP(code, x,name) \
 {code, 1, x,  name 
@@ -184,19 +185,19 @@ struct h8_opcode
 #define EOP  ,0,0,0 }
 
 #define TWOOP(code, name, op1, op2,op3) \
-{ code,1, 2,name, {IMM8, RD8, E},	{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0},\
-{ code, 1, 2,name, {RS8, RD8, E},	{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0} 
+{ code,1, 2,name, {{IMM8, RD8, E}},	{{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
+{ code, 1, 2,name, {{RS8, RD8, E}},	{{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} 
 
 #define UNOP(code,name, op1, op2) \
-{ code, 1, 2, name, {OR8, E, 0}, { op1, op2, 0, OR8, E, 0, 0, 0, 0}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
 
 #define UNOP3(code, name, op1, op2, op3) \
-{ O(code,SB), 1, 2, name, {OR8,  E, 0}, {op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
-,{ O(code,SB), 1, 2, name, {IMM, OR8 | SRC_IN_DST,  E}, {op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {IMM, OR16 | SRC_IN_DST, E}, {op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {IMM, OR32 | SRC_IN_DST, E}, {op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}, 0, 0, 0, 0}
+{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
+{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
+{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \
+,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
+{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
+{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0}
 
 
 #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
@@ -316,23 +317,23 @@ struct h8_opcode h8_opcodes[] =
 {
   TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
   
-  NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{RS16,RD16,E },{0x0,0x9,RS16,RD16,E} EOP,
-  NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{IMM16,RD16,E },{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
-  NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{RS32,RD32,E }, {0x0,0xA,B31|RS32,B30|RD32,E} EOP,
-  NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{IMM32,RD32,E },{0x7,0xA,0x1,B30|RD32,IMM32LIST,E} EOP,
-  NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {KBIT,RDP,E},   {0x0,0xB,KBIT,RDP,E,0,0,0,0} EOP,
+  NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{{RS16,RD16,E}},{{0x0,0x9,RS16,RD16,E}} EOP,
+  NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
+  NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP,
+  NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP,
+  NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}},   {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP,
 
   TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE),
   TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6),
 
-  NEW_SOP(O(O_AND,SW),0,2,"and.w"),{RS16,RD16,E },{0x6,0x6,RS16,RD16,E} EOP,
-  NEW_SOP(O(O_AND,SW),0,4,"and.w"),{IMM16,RD16,E },{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
+  NEW_SOP(O(O_AND,SW),0,2,"and.w"),{{RS16,RD16,E }},{{0x6,0x6,RS16,RD16,E}} EOP,
+  NEW_SOP(O(O_AND,SW),0,4,"and.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
   
-  NEW_SOP(O(O_AND,SL),0,6,"and.l"),{IMM32,RD32,E },{0x7,0xA,0x6,B30|RD32,IMM32LIST,E} EOP,
-  NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E} EOP,
+  NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP,
+  NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,CCR,E},{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP,
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
 
   BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
   BRANCH(O(O_BRA,SB),"bra",0x0),
@@ -367,8 +368,8 @@ struct h8_opcode h8_opcodes[] =
   BITOP(O(O_BOR,SB),  IMM3|B30,"bor",  0x7,0x4,0x7,0xC,0x7,0xE,0x0),
   EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8),
 
-  SOP(O(O_BSR,SB),6,"bsr"),{DISP8,E,0},{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0} EOP,
-  SOP(O(O_BSR,SB),6,"bsr"),{DISP16,E,0},{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0} EOP,
+  SOP(O(O_BSR,SB),6,"bsr"),{{DISP8,E,0}},{{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0}} EOP,
+  SOP(O(O_BSR,SB),6,"bsr"),{{DISP16,E,0}},{{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0}} EOP,
   BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8),
   EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0),
   BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
@@ -376,223 +377,223 @@ struct h8_opcode h8_opcodes[] =
   TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC),
   WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD),
 
-  NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{RS16,RD16,E },{0x1,0xD,RS16,RD16,E} EOP,
-  NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{IMM16,RD16,E },{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
+  NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{{RS16,RD16,E }},{{0x1,0xD,RS16,RD16,E}} EOP,
+  NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 
-  NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{IMM32,RD32,E },{0x7,0xA,0x2,B30|RD32,IMM32LIST,E} EOP,
-  NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{RS32,RD32,E },{0x1,0xF,B31|RS32,B30|RD32,E} EOP,
+  NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x2,B30|RD32,IMM32LIST,E}} EOP,
+  NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{{RS32,RD32,E }},{{0x1,0xF,B31|RS32,B30|RD32,E}} EOP,
 
   UNOP(O(O_DAA,SB), "daa",0x0,0xF),
   UNOP(O(O_DAS,SB), "das",0x1,0xF),
   UNOP(O(O_DEC,SB), "dec.b",0x1,0xA),
 
-  NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{DBIT,RD16,E },{0x1,0xB,0x5|DBIT,RD16,E} EOP,
-  NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{DBIT,RD32,E },{0x1,0xB,0x7|DBIT,RD32|B30,E} EOP,
+  NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP,
+  NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
 
-  NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {RS8,RD16,E}, {0x5,0x1,RS8,RD16,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{RS16,RD32,E},{0x5,0x3,RS16,B30|RD32,E}EOP,
+  NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
     
-  NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{RS8,RD16,E },{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E} EOP,
-  NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{RS16,RD32,E },{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E} EOP,
+  NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
+  NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{E,0,0},{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}EOP,
-  NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{E,0,0},{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E} EOP,
+  NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
+  NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
     
-  NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{OR16,E,0},{0x1,0x7,0xD,OR16,E   }EOP,
-  NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{OR32,E,0},{0x1,0x7,0xF,OR32|B30,E   }EOP,
+  NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E   }}EOP,
+  NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E   }}EOP,
 
-  NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{OR16,E,0},{0x1,0x7,0x5,OR16,E   }EOP,
-  NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{OR32,E,0},{0x1,0x7,0x7,OR32|B30,E   }EOP,
+  NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{{OR16,E,0}},{{0x1,0x7,0x5,OR16,E   }}EOP,
+  NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{{OR32,E,0}},{{0x1,0x7,0x7,OR32|B30,E   }}EOP,
     
   UNOP(O(O_INC,SB), "inc",0x0,0xA),
 
-  NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{DBIT,RD16,E },{0x0,0xB,0x5|DBIT,RD16,E} EOP,
-  NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{DBIT,RD32,E },{0x0,0xB,0x7|DBIT,RD32|B30,E} EOP,
-
-  SOP(O(O_JMP,SB),4,"jmp"),{RSIND,E,0},{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}EOP,
-  SOP(O(O_JMP,SB),6,"jmp"),{SRC|ABSJMP,E,0},{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_JMP,SB),8,"jmp"),{SRC|MEMIND,E,0},{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP,
-
-  SOP(O(O_JSR,SB),6,"jsr"),{SRC|RSIND,E,0}, {0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}EOP,
-  SOP(O(O_JSR,SB),8,"jsr"),{SRC|ABSJMP,E,0},{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_JSR,SB),8,"jsr"),{SRC|MEMIND,E,0},{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,CCR,E},         { 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,CCR,E},          { 0x0,0x3,0x0,OR8,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,CCR,E},     {PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,CCR,E},     {PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,CCR,E},{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,CCR,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,CCR,E},        {PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,CCR,E},        {PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E} EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,EXR,E},         { 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,EXR,E},          { 0x0,0x3,0x1,OR8,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,EXR,E},     { 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,EXR,E},     { 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,EXR,E},{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,EXR,E},{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,EXR,E},        { 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,EXR,E},        { 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E} EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS|SRC|L_16|MEMRELAX,RD8,E},  { 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{ABS|SRC|L_32|MEMRELAX,RD8,E }, { 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS|L_16|MEMRELAX|DST,E},     { 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,ABS|DST|L_32|MEMRELAX,E },    { 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }EOP,
+  NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP,
+  NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP,
+
+  SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP,
+  SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
+
+  SOP(O(O_JSR,SB),6,"jsr"),{{SRC|RSIND,E,0}}, {{0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}}EOP,
+  SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
+
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR,E}},         {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR,E}},          {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR,E}},     {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR,E}},     {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR,E}},        {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR,E}},        {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR,E}},         {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR,E}},          {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+
+  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}},  {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS|L_16|MEMRELAX|DST,E}},     {{ 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,ABS|DST|L_32|MEMRELAX,E }},    {{ 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }}EOP,
     
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP|L_32|SRC,RD8,E},  { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP|L_32|DST,E},  { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}EOP,
-
-
-
-  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{RS8,RD8,E},	    { 0x0,0xC,RS8,RD8,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{IMM8,RD8,E},           { 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{RSIND,RD8,E},          { 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP16SRC,RD8,E},      { 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{RSINC,RD8,E},          { 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS8SRC,RD8,E},        { 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,RDIND,E},          { 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP16DST,E},      { 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,RDDEC|B31,E},      { 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS8DST,E},        { 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDIND,E},        { 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP|L_32|SRC,RD16,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP|L_32|DST,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS|L_32|MEMRELAX|SRC,RD16,E },{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS|L_32|MEMRELAX|DST,E },{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }EOP,
-  SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{RS16,RD16,E},         { 0x0,0xD,RS16, RD16,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{IMM16,RD16,E},        { 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{RSIND,RD16,E},        { 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP16SRC,RD16,E},    { 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{RSINC,RD16,E},        { 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS16SRC,RD16,E},     { 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP16DST,E},    { 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDDEC,E},        { 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS16DST,E},     { 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-
-  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{IMM32,RD32,E},        { 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}EOP,
-  SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{RS32,RD32,E},         { 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}EOP,
-
-  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{RSIND,RD32,E},        { PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP16SRC,RD32,E},    { PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP|L_32|SRC,RD32,E},{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{RSINC,RD32,E},        { PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS16SRC,RD32,E},     { PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS32SRC|MEMRELAX,RD32,E },    { PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDIND,E},        { PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP16DST,E},    { PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP|L_32|DST,E},{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDDEC,E},        { PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS16DST,E},     { PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS32DST|MEMRELAX,E },    { PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{ABS16SRC,RD8,E},{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{RS8,ABS16DST,E},{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-
-  NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{RS8,RD16,E}, { 0x5,0x0,RS8,RD16,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{RS16,RD32,E},{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}EOP,
-
-  NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{RS8,RD16,E}, { 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}EOP,
-  NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{RS16,RD32,E},{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}EOP,
+  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP|L_32|SRC,RD8,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP|L_32|DST,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}}EOP,
+
+
+
+  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{RS8,RD8,E}},	    {{ 0x0,0xC,RS8,RD8,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{IMM8,RD8,E}},           {{ 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{RSIND,RD8,E}},          {{ 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP16SRC,RD8,E}},      {{ 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{RSINC,RD8,E}},          {{ 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}}EOP,
+
+  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS8SRC,RD8,E}},        {{ 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,RDIND,E}},          {{ 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP16DST,E}},      {{ 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,RDDEC|B31,E}},      {{ 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}}EOP,
+
+  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS8DST,E}},        {{ 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}}EOP,
+
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDIND,E}},        {{ 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP|L_32|SRC,RD16,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP|L_32|DST,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS|L_32|MEMRELAX|SRC,RD16,E }},{{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS|L_32|MEMRELAX|DST,E }},{{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{{RS16,RD16,E}},         {{ 0x0,0xD,RS16, RD16,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{IMM16,RD16,E}},        {{ 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{RSIND,RD16,E}},        {{ 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP16SRC,RD16,E}},    {{ 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{RSINC,RD16,E}},        {{ 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS16SRC,RD16,E}},     {{ 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP16DST,E}},    {{ 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDDEC,E}},        {{ 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}}EOP,
+  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS16DST,E}},     {{ 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+
+  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{IMM32,RD32,E}},        {{ 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}}EOP,
+  SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{{RS32,RD32,E}},         {{ 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}}EOP,
+
+  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{RSIND,RD32,E}},        {{ PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }}EOP,
+  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP16SRC,RD32,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
+  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP|L_32|SRC,RD32,E}},{{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{RSINC,RD32,E}},        {{ PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }}EOP,
+  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS16SRC,RD32,E}},     {{ PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
+  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS32SRC|MEMRELAX,RD32,E }},    {{ PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDIND,E}},        {{ PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP16DST,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP|L_32|DST,E}},{{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDDEC,E}},        {{ PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS16DST,E}},     {{ PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
+  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS32DST|MEMRELAX,E }},    {{ PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }}EOP,
+
+  SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{{ABS16SRC,RD8,E}},{{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{{RS8,ABS16DST,E}},{{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+
+  NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{{RS8,RD16,E}}, {{ 0x5,0x0,RS8,RD16,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{{RS16,RD32,E}},{{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}}EOP,
+
+  NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{{RS8,RD16,E}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}}EOP,
+  NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{{RS16,RD32,E}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}}EOP,
   
   /* ??? This can use UNOP3.  */
-  NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{ OR8,E, 0},{ 0x1,0x7,0x8,OR8,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{ OR16,E,0},{ 0x1,0x7,0x9,OR16,E}EOP,
-  NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{ OR32,E,0},{ 0x1,0x7,0xB,B30|OR32,E}EOP,
+  NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x8,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x9,OR16,E}}EOP,
+  NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{{ OR32,E,0}},{{ 0x1,0x7,0xB,B30|OR32,E}}EOP,
     
-  NEW_SOP(O(O_NOP,SN),1,2,"nop"),{E,0,0},{ 0x0,0x0,0x0,0x0,E,0,0,0,0}EOP,
+  NEW_SOP(O(O_NOP,SN),1,2,"nop"),{{E,0,0}},{{ 0x0,0x0,0x0,0x0,E,0,0,0,0}}EOP,
 
   /* ??? This can use UNOP3.  */
-  NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{ OR8,E, 0},{ 0x1,0x7,0x0,OR8,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{ OR16,E,0},{ 0x1,0x7,0x1,OR16,E}EOP,
-  NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{ OR32,E,0},{ 0x1,0x7,0x3,B30|OR32,E}EOP,
+  NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x0,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x1,OR16,E}}EOP,
+  NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{{ OR32,E,0}},{{ 0x1,0x7,0x3,B30|OR32,E}}EOP,
 
   TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4),
-  NEW_SOP(O(O_OR,SW),0,4,"or.w"),{IMM16,RD16,E },{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
-  NEW_SOP(O(O_OR,SW),0,2,"or.w"),{RS16,RD16,E },{0x6,0x4,RS16,RD16,E} EOP,
+  NEW_SOP(O(O_OR,SW),0,4,"or.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
+  NEW_SOP(O(O_OR,SW),0,2,"or.w"),{{RS16,RD16,E }},{{0x6,0x4,RS16,RD16,E}} EOP,
 
-  NEW_SOP(O(O_OR,SL),0,6,"or.l"),{IMM32,RD32,E },{0x7,0xA,0x4,B30|RD32,IMM32LIST,E} EOP,
-  NEW_SOP(O(O_OR,SL),0,2,"or.l"),{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E} EOP,
+  NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP,
+  NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,CCR,E},{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
-  NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{OR16,E,0},{ 0x6,0xD,0x7,OR16,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{OR16,E,0},{ 0x6,0xD,0xF,OR16,E,0,0,0,0}EOP,
-  NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}EOP,
+  NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{{OR16,E,0}},{{ 0x6,0xD,0xF,OR16,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}}EOP,
 
   UNOP3(O_ROTL,  "rotl", 0x1,0x2,0x8),
   UNOP3(O_ROTR,  "rotr", 0x1,0x3,0x8),
   UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0),
   UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0),
 
-  SOP(O(O_BPT,SN),  10,"bpt"),{E,0,0},{ 0x7,0xA,0xF,0xF,E,0,0,0,0}EOP,
-  SOP(O(O_RTE,SN),  10,"rte"),{E,0,0},{ 0x5,0x6,0x7,0x0,E,0,0,0,0}EOP,
-  SOP(O(O_RTS,SN),   8,"rts"),{E,0,0},{ 0x5,0x4,0x7,0x0,E,0,0,0,0}EOP,
+  SOP(O(O_BPT,SN),  10,"bpt"),{{E,0,0}},{{ 0x7,0xA,0xF,0xF,E,0,0,0,0}}EOP,
+  SOP(O(O_RTE,SN),  10,"rte"),{{E,0,0}},{{ 0x5,0x6,0x7,0x0,E,0,0,0,0}}EOP,
+  SOP(O(O_RTS,SN),   8,"rts"),{{E,0,0}},{{ 0x5,0x4,0x7,0x0,E,0,0,0,0}}EOP,
 
   UNOP3(O_SHAL,  "shal",0x1,0x0,0x8),
   UNOP3(O_SHAR,  "shar",0x1,0x1,0x8),
   UNOP3(O_SHLL,  "shll",0x1,0x0,0x0),
   UNOP3(O_SHLR,  "shlr",0x1,0x1,0x0),
 
-  SOP(O(O_SLEEP,SN),2,"sleep"),{E,0,0},{ 0x0,0x1,0x8,0x0,E,0,0,0,0} EOP,
+  SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{CCR,RD8,E},{ 0x0,0x2,0x0,RD8,E,0,0,0,0} EOP,
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RSIND,E},        {PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_16,E},{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_32,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RDDEC,E},        {PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RSIND,E}},        {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RDDEC,E}},        {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS16SRC,E},     {PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS32SRC,E},     {PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS16SRC,E}},     {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS32SRC,E}},     {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{EXR,RD8,E},{ 0x0,0x2,0x1,RD8,E,0,0,0,0} EOP,
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RSIND,E},        {0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_16,E},{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_32,E},{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RDDEC,E},        {0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RSIND,E}},        {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RDDEC,E}},        {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS16SRC,E},     {0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS32SRC,E},     {0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS16SRC,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS32SRC,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 
-  SOP(O(O_SUB,SB),2,"sub.b"),{RS8,RD8,E},{ 0x1,0x8,RS8,RD8,E,0,0,0,0}EOP,
+  SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
 
-  NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{RS16,RD16,E },  {0x1,0x9,RS16,RD16,E} EOP,
-  NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{IMM16,RD16,E }, {0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
-  NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{RS32,RD32,E }, {0x1,0xA,B31|RS32,B30|RD32,E} EOP,
-  NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {IMM32,RD32,E },{0x7,0xA,0x3,B30|RD32,IMM32LIST,E} EOP,
+  NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{{RS16,RD16,E }},  {{0x1,0x9,RS16,RD16,E}} EOP,
+  NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{{IMM16,RD16,E }}, {{0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
+  NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{{RS32,RD32,E }}, {{0x1,0xA,B31|RS32,B30|RD32,E}} EOP,
+  NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {{IMM32,RD32,E }},{{0x7,0xA,0x3,B30|RD32,IMM32LIST,E}} EOP,
 
-  SOP(O(O_SUBS,SL),2,"subs"),{KBIT,RDP,E},{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}EOP,
+  SOP(O(O_SUBS,SL),2,"subs"),{{KBIT,RDP,E}},{{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}}EOP,
   TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE),
 
-  NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{ IMM2,E},  {0x5,0x7,IMM2,IGNORE,E  }EOP,
-  NEW_SOP(O(O_TAS,SB),0,2,"tas"),{RSIND,E},  {0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E  }EOP,
+  NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{{ IMM2,E}},  {{0x5,0x7,IMM2,IGNORE,E  }}EOP,
+  NEW_SOP(O(O_TAS,SB),0,2,"tas"),{{RSIND,E}},  {{0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E  }}EOP,
 
   TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5),
 
-  NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{IMM16,RD16,E },{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
-  NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{RS16,RD16,E },{0x6,0x5,RS16,RD16,E} EOP,
+  NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
+  NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{{RS16,RD16,E }},{{0x6,0x5,RS16,RD16,E}} EOP,
 
-  NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{IMM32,RD32,E },{0x7,0xA,0x5,B30|RD32,IMM32LIST,E} EOP,
-  NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E} EOP,
+  NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP,
+  NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
 
-  SOP(O(O_XORC,SB),2,"xorc"),{IMM8,CCR,E},{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP,
-  SOP(O(O_XORC,SB),2,"xorc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
-  NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{E, 0, 0},{0x0,0x1,0xa,0x0,E} EOP,
-  NEW_SOP(O(O_MAC,SL),1,2,"mac"),{RSINC,RDINC,E},{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E} EOP,
-  NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{RS32,MACREG,E},{0x0,0x3,MACREG,RS32,E} EOP,
-  NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{MACREG,RD32,E},{0x0,0x2,MACREG,RD32,E} EOP,
-  NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{RSINC, RS32, E},{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}EOP,
-  NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{RS32, RDDEC, E},{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}EOP,
-  0
+  NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
+  NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
+  NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MACREG,E}},{{0x0,0x3,MACREG,RS32,E}} EOP,
+  NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP,
+  NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
+  { 0 }
 };
 #else
 extern struct h8_opcode h8_opcodes[] ;
diff --git a/gnu/usr.bin/binutils/include/opcode/hppa.h b/gnu/usr.bin/binutils/include/opcode/hppa.h
index 88bc942a054..1c41ff07c25 100644
--- a/gnu/usr.bin/binutils/include/opcode/hppa.h
+++ b/gnu/usr.bin/binutils/include/opcode/hppa.h
@@ -1,5 +1,5 @@
 /* Table of opcodes for the PA-RISC.
-   Copyright (C) 1990, 1991, 1993, 1995 Free Software Foundation, Inc.
+   Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
 
    Contributed by the Center for Software Science at the
    University of Utah (pa-gdb-bugs@cs.utah.edu).
@@ -43,8 +43,13 @@ struct pa_opcode
     unsigned long int mask;	/* ... in these bits. */
     char *args;
     enum pa_arch arch;
+    char flags;
 };
 
+/* Enable/disable strict syntax checking.  Not currently used, but will
+   be necessary for PA2.0 support in the future.  */
+#define FLAG_STRICT 0x1
+
 /*
    All hppa opcodes are 32 bits.
 
@@ -52,8 +57,9 @@ struct pa_opcode
    particular opcode in order for an instruction to be an instance
    of that opcode.
 
-   The args component is a string containing one character
-   for each operand of the instruction.
+   The args component is a string containing one character for each operand of
+   the instruction.  Characters used as a prefix allow any second character to
+   be used without conflicting with the main operand characters.
 
    Bit positions in this description follow HP usage of lsb = 31,
    "at" is lsb of field.
@@ -64,9 +70,9 @@ struct pa_opcode
 
    In the args field, the following characters are unused:
 
-	'  "#$%    *+- ./   3      :; =   '
-	' B         L              [\] _'
-	'    e gh   lm   qr        { } '
+	'  "   &     -  /   34 6789:;< > @'
+	'  C         M             [\]  '
+	'    e g    l            y   } '
 
    Here are all the characters:
 
@@ -78,20 +84,10 @@ Kinds of operands:
    x    integer register field at 15.
    b    integer register field at 10.
    t    integer register field at 31.
-   y    floating point register field at 31
+   a	integer register field at 10 and 15 (for PERMH)
    5    5 bit immediate at 15.
    s    2 bit space specifier at 17.
    S    3 bit space specifier at 18.
-   c    indexed load completer.
-   C    short load and store completer.
-   Y	Store Bytes Short completer
-   <    non-negated compare/subtract conditions.
-   a	compare/subtract conditions
-   d    non-negated add conditions
-   &    logical instruction conditions
-   U    unit instruction conditions
-   >    shift/extract/deposit conditions.
-   ~    bvb,bb conditions
    V    5 bit immediate value at 31
    i    11 bit immediate value at 31
    j    14 bit immediate value at 31
@@ -100,20 +96,28 @@ Kinds of operands:
    N	nullification for spop and copr instructions
    w    12 bit branch displacement
    W    17 bit branch displacement (PC relative)
+   X    22 bit branch displacement (PC relative)
    z    17 bit branch displacement (just a number, not an address)
 
 Also these:
 
+   .    2 bit shift amount at 25
+   *    4 bit shift amount at 25
    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
         31-p
+   ~    6 bit shift count at 20,22:26 encoded as 63-~.
    P    5 bit bit position at 26
+   q    6 bit bit position at 20,22:26
    T    5 bit field length at 31 (encoded as 32-T)
+   %	6 bit field length at 23,27:31 (variable extract/deposit)
+   |	6 bit field length at 19,27:31 (fixed extract/deposit)
    A    13 bit immediate at 18 (to support the BREAK instruction)
    ^	like b, but describes a control register
-   Z    System Control Completer (to support LPA, LHA, etc.)
+   !    sar (cr11) register
    D    26 bit immediate at 31 (to support the DIAG instruction)
+   $    9 bit immediate at 28 (to support POPBTS)
 
-   f    3 bit Special Function Unit identifier at 25
+   v    3 bit Special Function Unit identifier at 25
    O    20 bit Special Function Unit operation split between 15 bits at 20
         and 5 bits at 31
    o    15 bit Special Function Unit operation at 20
@@ -128,39 +132,134 @@ Also these:
    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 	(for 0xe format FP instructions)
    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
-   M    Floating-Point Compare Conditions (encoded as 5 bits at 31)
-   ?    non-negated/negated compare/subtract conditions.
-   @    non-negated/negated add conditions.
-   !    non-negated add conditions.
+   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
+        (very similar to 'F')
 
-   s    2 bit space specifier at 17.
-   b    register field at 10.
    r	5 bit immediate value at 31 (for the break instruction)
 	(very similar to V above, except the value is unsigned instead of
 	low_sign_ext)
    R	5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 	(same as r above, except the value is in a different location)
+   U	10 bit immediate value at 15 (for SSM, RSM on pa2.0)
    Q	5 bit immediate value at 10 (a bit position specified in
 	the bb instruction. It's the same as r above, except the
         value is in a different location)
-   |	shift/extract/deposit conditions when used in a conditional branch
-
-And these (PJH) for PA-89 F.P. registers and instructions:
-
-   v    a 't' operand type extended to handle L/R register halves.
-   E    a 'b' operand type extended to handle L/R register halves.
-   X    an 'x' operand type extended to handle L/R register halves.
-   J    a 'b' operand type further extended to handle extra 1.1 registers
-   K    a 'x' operand type further extended to handle extra 1.1 registers
-   4    a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
-   6    a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
-   7    a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
-   8    5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
-   9    5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
-   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
-        (very similar to 'F')
+   B	5 bit immediate value at 10 (a bit position specified in
+	the bb instruction. Similar to Q, but 64bit handling is
+	different.
+   Z    %r1 -- implicit target of addil instruction.
+   L    ,%r2 completer for new syntax branch
+   {    Source format completer for fcnv
+   _    Destination format completer for fcnv
+   h    cbit for fcmp
+   =    gfx tests for ftest
+   d    14bit offset for single precision FP long load/store.
+   #    14bit offset for double precision FP load long/store.
+   J    Yet another 14bit offset with an unusual encoding.
+   K    Yet another 14bit offset with an unusual encoding.
+   Y    %sr0,%r31 -- implicit target of be,l instruction.
+   @	implicit immediate value of 0
+
+Completer operands all have 'c' as the prefix:
+
+   cx   indexed load completer.
+   cm   short load and store completer.
+   cq   long load and store completer (like cm, but inserted into a
+	different location in the target instruction).
+   cs   store bytes short completer.
+   ce   long load/store completer for LDW/STW with a different encoding than the
+	others
+   cc   load cache control hint
+   cd   load and clear cache control hint
+   cC   store cache control hint
+   co	ordered access
+
+   cp	branch link and push completer
+   cP	branch pop completer
+   cl	branch link completer
+   cg	branch gate completer
+
+   cw	read/write completer for PROBE
+   cW	wide completer for MFCTL
+   cL	local processor completer for cache control
+   cZ   System Control Completer (to support LPA, LHA, etc.)
+
+   ci	correction completer for DCOR
+   ca	add completer
+   cy	32 bit add carry completer
+   cY	64 bit add carry completer
+   cv	signed overflow trap completer
+   ct	trap on condition completer for ADDI, SUB
+   cT	trap on condition completer for UADDCM
+   cb	32 bit borrow completer for SUB
+   cB	64 bit borrow completer for SUB
+
+   ch	left/right half completer
+   cH	signed/unsigned saturation completer
+   cS	signed/unsigned completer at 21
+   c*	permutation completer
+
+Condition operands all have '?' as the prefix:
+
+   ?f   Floating point compare conditions (encoded as 5 bits at 31)
+
+   ?a	add conditions
+   ?A	64 bit add conditions
+   ?@   add branch conditions followed by nullify
+   ?d	non-negated add branch conditions
+   ?D	negated add branch conditions
+   ?w	wide mode non-negated add branch conditions
+   ?W	wide mode negated add branch conditions
+
+   ?s   compare/subtract conditions
+   ?S	64 bit compare/subtract conditions
+   ?t   non-negated compare and branch conditions
+   ?n   32 bit compare and branch conditions followed by nullify
+   ?N   64 bit compare and branch conditions followed by nullify
+   ?Q	64 bit compare and branch conditions for CMPIB instruction
+
+   ?l   logical conditions
+   ?L	64 bit logical conditions
+
+   ?b   branch on bit conditions
+   ?B	64 bit branch on bit conditions
+
+   ?x   shift/extract/deposit conditions
+   ?X	64 bit shift/extract/deposit conditions
+   ?y   shift/extract/deposit conditions followed by nullify for conditional
+        branches
+
+   ?u   unit conditions
+   ?U   64 bit unit conditions
+
+Floating point registers all have 'f' as a prefix:
+
+   ft	target register at 31
+   fT	target register with L/R halves at 31
+   fa	operand 1 register at 10
+   fA   operand 1 register with L/R halves at 10
+   fX   Same as fA, except prints a space before register during disasm
+   fb	operand 2 register at 15
+   fB   operand 2 register with L/R halves at 15
+   fC   operand 3 register with L/R halves at 16:18,21:23
+   fe   Like fT, but encoding is different.
+
+Float registers for fmpyadd and fmpysub:
+
+   fi	mult operand 1 register at 10
+   fj	mult operand 2 register at 15
+   fk	mult target register at 20
+   fl	add/sub operand register at 25
+   fm	add/sub target register at 31
+
 */
 
+
+/* List of characters not to put a space after.  Note that
+   "," is included, as the "spopN" operations use literal
+   commas in their completer sections. */
+static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
+
 /* The order of the opcodes in this table is significant:
 
    * The assembler requires that all instances of the same mnemonic must be
@@ -173,293 +272,560 @@ static const struct pa_opcode pa_opcodes[] =
 
 /* pseudo-instructions */
 
-{ "b",		0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */
-{ "ldi",	0x34000000, 0xffe0c000, "j,x", pa10},	/* ldo val(r0),r */
-{ "comib", 	0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/
-{ "comb",	0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */
-{ "addb",	0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */
-{ "addib",	0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/
-{ "nop",        0x08000240, 0xffffffff, "", pa10},      /* or 0,0,0 */
-{ "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10},   /* or r,0,t */
-{ "mtsar",      0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */
+{ "ldi",	0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
+
+{ "call",	0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
+{ "call",	0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
+{ "ret",	0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
+
+{ "cmpib", 	0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
+{ "cmpib", 	0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
+{ "comib", 	0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "comib", 	0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
+{ "cmpb",	0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
+{ "cmpb",	0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
+{ "comb",	0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "comb",	0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
+{ "addb",	0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT},
+{ "addb",	0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "addb",	0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
+{ "addib",	0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT},
+{ "addib",	0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "addib",	0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
+{ "nop",        0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */
+{ "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */
+{ "mtsar",      0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
 
 /* Loads and Stores for integer registers.  */
-{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10},
-{ "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10},
-{ "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10},
-{ "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10},
-{ "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10},
-{ "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10},
-{ "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10},
-{ "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10},
-{ "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10},
-{ "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10},
-{ "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10},
-{ "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10},
-{ "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10},
-{ "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10},
-{ "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10},
-{ "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10},
-{ "ldwx",       0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10},
-{ "ldwx",       0x0c000080, 0xfc001fc0, "cx(b),t", pa10},
-{ "ldhx",       0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10},
-{ "ldhx",       0x0c000040, 0xfc001fc0, "cx(b),t", pa10},
-{ "ldbx",       0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10},
-{ "ldbx",       0x0c000000, 0xfc001fc0, "cx(b),t", pa10},
-{ "ldwax",      0x0c000180, 0xfc00dfc0, "cx(b),t", pa10},
-{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10},
-{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10},
-{ "ldws",	0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10},
-{ "ldws",	0x0c001080, 0xfc001fc0, "C5(b),t", pa10},
-{ "ldhs",	0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10},
-{ "ldhs",	0x0c001040, 0xfc001fc0, "C5(b),t", pa10},
-{ "ldbs",	0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10},
-{ "ldbs",	0x0c001000, 0xfc001fc0, "C5(b),t", pa10},
-{ "ldwas",	0x0c001180, 0xfc00dfc0, "C5(b),t", pa10},
-{ "ldcws",	0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10},
-{ "ldcws",	0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10},
-{ "stws",	0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10},
-{ "stws",	0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10},
-{ "sths",	0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10},
-{ "sths",	0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10},
-{ "stbs",	0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10},
-{ "stbs",	0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10},
-{ "stwas",	0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10},
-{ "stbys",	0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10},
-{ "stbys",	0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10},
+
+{ "ldd",	0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldd",        0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",        0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT},
+{ "ldd",        0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
+{ "ldd",        0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT},
+{ "ldw",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
+{ "ldw",        0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldw",	0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
+{ "ldw",        0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
+{ "ldw",        0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT},
+{ "ldw",        0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
+{ "ldw",        0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT},
+{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10, 0},
+{ "ldh",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
+{ "ldh",        0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldh",	0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
+{ "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10, 0},
+{ "ldb",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
+{ "ldb",        0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldb",	0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
+{ "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10, 0},
+{ "std",	0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
+{ "std",        0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
+{ "std",        0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
+{ "stw",        0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
+{ "stw",        0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT},
+{ "stw",        0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
+{ "stw",        0x7c000004, 0xfc000006, "cex,K(b)", pa20, FLAG_STRICT},
+{ "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "sth",	0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "sth",	0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
+{ "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "stb",	0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "stb",	0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
+{ "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10, 0},
+{ "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "ldwx",       0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
+{ "ldwx",       0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0},
+{ "ldhx",       0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
+{ "ldhx",       0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0},
+{ "ldbx",       0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
+{ "ldbx",       0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0},
+{ "ldwa",       0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldwa",	0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT},
+{ "ldcw",       0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT},
+{ "ldcw",       0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT},
+{ "stwa",	0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stwa",	0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT},
+{ "ldda",       0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
+{ "ldda",	0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
+{ "ldcd",       0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
+{ "ldcd",       0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
+{ "ldwax",      0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0},
+{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
+{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0},
+{ "ldws",	0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
+{ "ldws",	0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0},
+{ "ldhs",	0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
+{ "ldhs",	0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0},
+{ "ldbs",	0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
+{ "ldbs",	0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0},
+{ "ldwas",	0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0},
+{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
+{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0},
+{ "stws",	0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
+{ "stws",	0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0},
+{ "sths",	0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
+{ "sths",	0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0},
+{ "stbs",	0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
+{ "stbs",	0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0},
+{ "stwas",	0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0},
+{ "stdby",	0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
+{ "stdby",	0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0},
+{ "stbys",	0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0},
 
 /* Immediate instructions.  */
-{ "ldo",	0x34000000, 0xfc00c000, "j(b),x", pa10},
-{ "ldil",	0x20000000, 0xfc000000, "k,b", pa10},
-{ "addil",	0x28000000, 0xfc000000, "k,b", pa10},
+{ "ldo",	0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldil",	0x20000000, 0xfc000000, "k,b", pa10, 0},
+{ "addil",	0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
+{ "addil",	0x28000000, 0xfc000000, "k,b", pa10, 0},
 
 /* Branching instructions. */
-{ "bl",		0xe8000000, 0xfc00e000, "nW,b", pa10},
-{ "gate",	0xe8002000, 0xfc00e000, "nW,b", pa10},
-{ "blr",	0xe8004000, 0xfc00e001, "nx,b", pa10},
-{ "bv",		0xe800c000, 0xfc00e001, "nx(b)", pa10},
-{ "bv",		0xe800c000, 0xfc00e001, "n(b)", pa10},
-{ "be",		0xe0000000, 0xfc000000, "nz(S,b)", pa10},
-{ "ble",	0xe4000000, 0xfc000000, "nz(S,b)", pa10},
-{ "movb",	0xc8000000, 0xfc000000, "|nx,b,w", pa10},
-{ "movib",	0xcc000000, 0xfc000000, "|n5,b,w", pa10},
-{ "combt",	0x80000000, 0xfc000000, "<nx,b,w", pa10},
-{ "combf",	0x88000000, 0xfc000000, "<nx,b,w", pa10},
-{ "comibt",	0x84000000, 0xfc000000, "<n5,b,w", pa10},
-{ "comibf",	0x8c000000, 0xfc000000, "<n5,b,w", pa10},
-{ "addbt",	0xa0000000, 0xfc000000, "!nx,b,w", pa10},
-{ "addbf",	0xa8000000, 0xfc000000, "!nx,b,w", pa10},
-{ "addibt",	0xa4000000, 0xfc000000, "!n5,b,w", pa10},
-{ "addibf",	0xac000000, 0xfc000000, "!n5,b,w", pa10},
-{ "bvb",	0xc0000000, 0xffe00000, "~nx,w", pa10},
-{ "bb",		0xc4000000, 0xfc000000, "~nx,Q,w", pa10}, 
+{ "b",		0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
+{ "b",		0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
+{ "b",		0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
+{ "b",		0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
+{ "b",		0xe8000000, 0xffe0e000, "nW", pa10, 0},  /* b,l foo,r0 */
+{ "bl",		0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
+{ "gate",	0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
+{ "blr",	0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
+{ "bv",		0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
+{ "bv",		0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
+{ "bve",	0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
+{ "bve",	0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
+{ "bve",	0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
+{ "bve",	0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
+{ "be",		0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
+{ "be",		0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
+{ "be",		0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
+{ "be",		0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
+{ "ble",	0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
+{ "movb",	0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
+{ "movib",	0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
+{ "combt",	0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
+{ "combf",	0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
+{ "comibt",	0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
+{ "comibf",	0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
+{ "addbt",	0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
+{ "addbf",	0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
+{ "addibt",	0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
+{ "addibf",	0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
+{ "bb",		0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, 
+{ "bb",		0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, 
+{ "bb",		0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, 
+{ "bb",		0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, 
+{ "bvb",	0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
+{ "clrbts",	0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
+{ "popbts",	0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
+{ "pushnom",	0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
+{ "pushbts",	0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 
 /* Computation Instructions */
 
-{ "add",        0x08000600, 0xfc000fe0, "dx,b,t", pa10},
-{ "addl",       0x08000a00, 0xfc000fe0, "dx,b,t", pa10},
-{ "addo",       0x08000e00, 0xfc000fe0, "dx,b,t", pa10},
-{ "addc",       0x08000700, 0xfc000fe0, "dx,b,t", pa10},
-{ "addco",      0x08000f00, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh1add",     0x08000640, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh1addl",    0x08000a40, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh1addo",    0x08000e40, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh2add",     0x08000680, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh2addl",    0x08000a80, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh2addo",    0x08000e80, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh3add",     0x080006c0, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh3addl",    0x08000ac0, 0xfc000fe0, "dx,b,t", pa10},
-{ "sh3addo",    0x08000ec0, 0xfc000fe0, "dx,b,t", pa10},
-{ "sub",        0x08000400, 0xfc000fe0, "ax,b,t", pa10},
-{ "subo",       0x08000c00, 0xfc000fe0, "ax,b,t", pa10},
-{ "subb",       0x08000500, 0xfc000fe0, "ax,b,t", pa10},
-{ "subbo",      0x08000d00, 0xfc000fe0, "ax,b,t", pa10},
-{ "subt",       0x080004c0, 0xfc000fe0, "ax,b,t", pa10},
-{ "subto",      0x08000cc0, 0xfc000fe0, "ax,b,t", pa10},
-{ "ds",         0x08000440, 0xfc000fe0, "ax,b,t", pa10},
-{ "comclr",     0x08000880, 0xfc000fe0, "ax,b,t", pa10},
-{ "or",         0x08000240, 0xfc000fe0, "&x,b,t", pa10},
-{ "xor",        0x08000280, 0xfc000fe0, "&x,b,t", pa10},
-{ "and",        0x08000200, 0xfc000fe0, "&x,b,t", pa10},
-{ "andcm",      0x08000000, 0xfc000fe0, "&x,b,t", pa10},
-{ "uxor",       0x08000380, 0xfc000fe0, "Ux,b,t", pa10},
-{ "uaddcm",     0x08000980, 0xfc000fe0, "Ux,b,t", pa10},
-{ "uaddcmt",    0x080009c0, 0xfc000fe0, "Ux,b,t", pa10},
-{ "dcor",       0x08000b80, 0xfc1f0fe0, "Ub,t",   pa10},
-{ "idcor",      0x08000bc0, 0xfc1f0fe0, "Ub,t",   pa10},
-{ "addi",       0xb4000000, 0xfc000800, "di,b,x", pa10},
-{ "addio",      0xb4000800, 0xfc000800, "di,b,x", pa10},
-{ "addit",      0xb0000000, 0xfc000800, "di,b,x", pa10},
-{ "addito",     0xb0000800, 0xfc000800, "di,b,x", pa10},
-{ "subi",       0x94000000, 0xfc000800, "ai,b,x", pa10},
-{ "subio",      0x94000800, 0xfc000800, "ai,b,x", pa10},
-{ "comiclr",    0x90000000, 0xfc000800, "ai,b,x", pa10},
+{ "cmpclr",     0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
+{ "cmpclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
+{ "comclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "or",         0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "or",         0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "xor",        0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "xor",        0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "and",        0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "and",        0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "andcm",      0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "andcm",      0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "uxor",       0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
+{ "uxor",       0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "uaddcm",     0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
+{ "uaddcm",     0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
+{ "uaddcm",     0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "uaddcmt",    0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "dcor",       0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
+{ "dcor",       0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
+{ "dcor",       0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10, 0},
+{ "idcor",      0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10, 0},
+{ "addi",       0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
+{ "addi",       0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
+{ "addi",       0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addio",      0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addit",      0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addito",     0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "add",        0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
+{ "add",        0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
+{ "add",        0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
+{ "add",        0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
+{ "add",        0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addl",       0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addo",       0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addc",       0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addco",      0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sub",        0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",        0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",        0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",        0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",        0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",        0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",        0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subo",       0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subb",       0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subbo",      0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subt",       0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subto",      0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "ds",         0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subi",       0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
+{ "subi",       0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
+{ "subio",      0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
+{ "cmpiclr",    0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
+{ "cmpiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
+{ "comiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
+{ "shladd",     0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
+{ "shladd",     0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
+{ "sh1add",     0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh1addl",    0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh1addo",    0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2add",     0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2addl",    0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2addo",    0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3add",     0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3addl",    0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3addo",    0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+
+/* Subword Operation Instructions */
+
+{ "hadd",       0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
+{ "havg",       0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
+{ "hshl",       0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
+{ "hshladd",    0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
+{ "hshr",       0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
+{ "hshradd",    0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
+{ "hsub",       0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
+{ "mixh",       0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
+{ "mixw",       0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
+{ "permh",      0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
+
 
 /* Extract and Deposit Instructions */
 
-{ "vshd",       0xd0000000, 0xfc001fe0, ">x,b,t", pa10},
-{ "shd",        0xd0000800, 0xfc001c00, ">x,b,p,t", pa10},
-{ "vextru",     0xd0001000, 0xfc001fe0, ">b,T,x", pa10},
-{ "vextrs",     0xd0001400, 0xfc001fe0, ">b,T,x", pa10},
-{ "extru",      0xd0001800, 0xfc001c00, ">b,P,T,x", pa10},
-{ "extrs",      0xd0001c00, 0xfc001c00, ">b,P,T,x", pa10},
-{ "zvdep",      0xd4000000, 0xfc001fe0, ">x,T,b", pa10},
-{ "vdep",       0xd4000400, 0xfc001fe0, ">x,T,b", pa10},
-{ "zdep",       0xd4000800, 0xfc001c00, ">x,p,T,b", pa10},
-{ "dep",        0xd4000c00, 0xfc001c00, ">x,p,T,b", pa10},
-{ "zvdepi",     0xd4001000, 0xfc001fe0, ">5,T,b", pa10},
-{ "vdepi",      0xd4001400, 0xfc001fe0, ">5,T,b", pa10},
-{ "zdepi",      0xd4001800, 0xfc001c00, ">5,p,T,b", pa10},
-{ "depi",       0xd4001c00, 0xfc001c00, ">5,p,T,b", pa10},
+{ "shrpd",      0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
+{ "shrpd",      0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
+{ "shrpw",      0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
+{ "shrpw",      0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
+{ "vshd",       0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
+{ "shd",        0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
+{ "extrd",      0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
+{ "extrd",      0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
+{ "extrw",      0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
+{ "extrw",      0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
+{ "vextru",     0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
+{ "vextrs",     0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
+{ "extru",      0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
+{ "extrs",      0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
+{ "depd",       0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
+{ "depd",       0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
+{ "depdi",      0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
+{ "depdi",      0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
+{ "depw",       0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
+{ "depw",       0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
+{ "depwi",      0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
+{ "depwi",      0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
+{ "zvdep",      0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
+{ "vdep",       0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
+{ "zdep",       0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
+{ "dep",        0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
+{ "zvdepi",     0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
+{ "vdepi",      0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
+{ "zdepi",      0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
+{ "depi",       0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
 
 /* System Control Instructions */
 
-{ "break",      0x00000000, 0xfc001fe0, "r,A", pa10},
-{ "rfi",        0x00000c00, 0xffffffff, "", pa10},
-{ "rfir",       0x00000ca0, 0xffffffff, "", pa11},
-{ "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10},
-{ "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10},
-{ "mtsm",       0x00001860, 0xffe0ffff, "x", pa10},
-{ "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10},
-{ "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10},
-{ "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10},
-{ "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10},
-{ "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10},
-{ "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10},
-{ "sync",       0x00000400, 0xffffffff, "", pa10},
-{ "syncdma",    0x00100400, 0xffffffff, "", pa10},
-{ "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10},
-{ "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10},
-{ "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10},
-{ "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10},
-{ "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10},
-{ "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10},
-{ "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10},
-{ "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10},
-{ "lpa",        0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10},
-{ "lpa",        0x04001340, 0xfc003fc0, "Zx(b),t", pa10},
-{ "lha",        0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10},
-{ "lha",        0x04001300, 0xfc003fc0, "Zx(b),t", pa10},
-{ "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10},
-{ "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10},
-{ "pdtlb",      0x04001200, 0xfc003fdf, "Zx(s,b)", pa10},
-{ "pdtlb",      0x04001200, 0xfc003fdf, "Zx(b)", pa10},
-{ "pitlb",      0x04000200, 0xfc001fdf, "Zx(S,b)", pa10},
-{ "pitlb",      0x04000200, 0xfc001fdf, "Zx(b)", pa10},
-{ "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(s,b)", pa10},
-{ "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(b)", pa10},
-{ "pitlbe",     0x04000240, 0xfc001fdf, "Zx(S,b)", pa10},
-{ "pitlbe",     0x04000240, 0xfc001fdf, "Zx(b)", pa10},
-{ "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10},
-{ "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10},
-{ "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10},
-{ "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10},
-{ "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10},
-{ "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10},
-{ "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10},
-{ "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10},
-{ "pdc",        0x04001380, 0xfc003fdf, "Zx(s,b)", pa10},
-{ "pdc",        0x04001380, 0xfc003fdf, "Zx(b)", pa10},
-{ "fdc",        0x04001280, 0xfc003fdf, "Zx(s,b)", pa10},
-{ "fdc",        0x04001280, 0xfc003fdf, "Zx(b)", pa10},
-{ "fic",        0x04000280, 0xfc001fdf, "Zx(S,b)", pa10},
-{ "fic",        0x04000280, 0xfc001fdf, "Zx(b)", pa10},
-{ "fdce",       0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10},
-{ "fdce",       0x040012c0, 0xfc003fdf, "Zx(b)", pa10},
-{ "fice",       0x040002c0, 0xfc001fdf, "Zx(S,b)", pa10},
-{ "fice",       0x040002c0, 0xfc001fdf, "Zx(b)", pa10},
-{ "diag",       0x14000000, 0xfc000000, "D", pa10},
-{ "mtcpu",      0x14001600, 0xfc00ffff, "x,^", pa10},
-{ "mfcpu",      0x14001a00, 0xfc00ffff, "x,^", pa10},
-{ "mtcpu2",     0x14000240, 0xfc00ffff, "x,^", pa10},
-{ "mfcpu2",     0x14000600, 0xfc00ffff, "x,^", pa10},
+{ "break",      0x00000000, 0xfc001fe0, "r,A", pa10, 0},
+{ "rfi",        0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
+{ "rfi",        0x00000c00, 0xffffffff, "", pa10, 0},
+{ "rfir",       0x00000ca0, 0xffffffff, "", pa11, 0},
+{ "ssm",        0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
+{ "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
+{ "rsm",        0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
+{ "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
+{ "mtsm",       0x00001860, 0xffe0ffff, "x", pa10, 0},
+{ "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
+{ "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0},
+{ "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10, 0},
+{ "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10, 0},
+{ "mtsarcm",    0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
+{ "mfia",       0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
+{ "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
+{ "mfctl",      0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
+{ "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
+{ "sync",       0x00000400, 0xffffffff, "", pa10, 0},
+{ "syncdma",    0x00100400, 0xffffffff, "", pa10, 0},
+{ "probe",      0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
+{ "probe",      0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT},
+{ "probei",     0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
+{ "probei",     0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT},
+{ "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
+{ "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0},
+{ "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
+{ "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0},
+{ "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
+{ "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0},
+{ "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
+{ "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0},
+{ "lpa",        0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
+{ "lpa",        0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0},
+{ "lha",        0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
+{ "lha",        0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0},
+{ "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0},
+{ "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10, 0},
+{ "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
+{ "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT},
+{ "pdtlb",      0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "pdtlb",      0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0},
+{ "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
+{ "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT},
+{ "pitlb",      0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "pitlb",      0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0},
+{ "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0},
+{ "pitlbe",     0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "pitlbe",     0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0},
+{ "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
+{ "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10, 0},
+{ "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
+{ "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10, 0},
+{ "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
+{ "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10, 0},
+{ "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
+{ "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10, 0},
+{ "pdc",        0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "pdc",        0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0},
+{ "fdc",        0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "fdc",        0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0},
+{ "fic",        0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "fic",        0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0},
+{ "fdce",       0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "fdce",       0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0},
+{ "fice",       0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "fice",       0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0},
+{ "diag",       0x14000000, 0xfc000000, "D", pa10, 0},
+{ "idtlbt",     0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
+{ "iitlbt",     0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
+
+/* These may be specific to certain versions of the PA.  Joel claimed
+   they were 72000 (7200?) specific.  However, I'm almost certain the
+   mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
+{ "mtcpu",      0x14001600, 0xfc00ffff, "x,^", pa10, 0},
+{ "mfcpu",      0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
+{ "tocen",      0x14403600, 0xffffffff, "", pa10, 0},
+{ "tocdis",     0x14401620, 0xffffffff, "", pa10, 0},
+{ "shdwgr",     0x14402600, 0xffffffff, "", pa10, 0},
+{ "grshdw",     0x14400620, 0xffffffff, "", pa10, 0},
 
 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
    the Timex FPU or the Mustang ERS (not sure which) manual.  */
-{ "gfw",	0x04001680, 0xfc003fdf, "Zx(s,b)", pa11},
-{ "gfw",	0x04001680, 0xfc003fdf, "Zx(b)", pa11},
-{ "gfr",	0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11},
-{ "gfr",	0x04001a80, 0xfc003fdf, "Zx(b)", pa11},
+{ "gfw",	0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
+{ "gfw",	0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0},
+{ "gfr",	0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
+{ "gfr",	0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0},
 
 /* Floating Point Coprocessor Instructions */
-  
-{ "fldwx",      0x24000000, 0xfc001f80, "cx(s,b),v", pa10},
-{ "fldwx",      0x24000000, 0xfc001f80, "cx(b),v", pa10},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cx(b),y", pa10},
-{ "fstwx",      0x24000200, 0xfc001f80, "cv,x(s,b)", pa10},
-{ "fstwx",      0x24000200, 0xfc001f80, "cv,x(b)", pa10},
-{ "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
-{ "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(b)", pa10},
-{ "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
-{ "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(b)", pa10},
-{ "fldws",      0x24001000, 0xfc001f80, "C5(s,b),v", pa10},
-{ "fldws",      0x24001000, 0xfc001f80, "C5(b),v", pa10},
-{ "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10},
-{ "fldds",      0x2c001000, 0xfc001fc0, "C5(b),y", pa10},
-{ "fstws",      0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10},
-{ "fstws",      0x24001200, 0xfc001f80, "Cv,5(b)", pa10},
-{ "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
-{ "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10},
-{ "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
-{ "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10},
-{ "fadd",       0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
-{ "fadd",       0x38000600, 0xfc00e720, "IJ,K,v", pa10},
-{ "fsub",       0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
-{ "fsub",       0x38002600, 0xfc00e720, "IJ,K,v", pa10},
-{ "fmpy",       0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
-{ "fmpy",       0x38004600, 0xfc00e720, "IJ,K,v", pa10},
-{ "fdiv",       0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
-{ "fdiv",       0x38006600, 0xfc00e720, "IJ,K,v", pa10},
-{ "fsqrt",      0x30008000, 0xfc1fe7e0, "FE,v", pa10},
-{ "fsqrt",      0x38008000, 0xfc1fe720, "FJ,v", pa10},
-{ "fabs",       0x30006000, 0xfc1fe7e0, "FE,v", pa10},
-{ "fabs",       0x38006000, 0xfc1fe720, "FJ,v", pa10},
-{ "frem",       0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
-{ "frem",       0x38008600, 0xfc00e720, "FJ,K,v", pa10},
-{ "frnd",       0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
-{ "frnd",       0x3800a000, 0xfc1fe720, "FJ,v", pa10},
-{ "fcpy",       0x30004000, 0xfc1fe7e0, "FE,v", pa10},
-{ "fcpy",       0x38004000, 0xfc1fe720, "FJ,v", pa10},
-{ "fcnvff",     0x30000200, 0xfc1f87e0, "FGE,v", pa10},
-{ "fcnvff",     0x38000200, 0xfc1f8720, "FGJ,v", pa10},
-{ "fcnvxf",     0x30008200, 0xfc1f87e0, "FGE,v", pa10},
-{ "fcnvxf",     0x38008200, 0xfc1f8720, "FGJ,v", pa10},
-{ "fcnvfx",     0x30010200, 0xfc1f87e0, "FGE,v", pa10},
-{ "fcnvfx",     0x38010200, 0xfc1f8720, "FGJ,v", pa10},
-{ "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGE,v", pa10},
-{ "fcnvfxt",    0x38018200, 0xfc1f8720, "FGJ,v", pa10},
-{ "fcmp",       0x30000400, 0xfc00e7e0, "FME,X", pa10},
-{ "fcmp",       0x38000400, 0xfc00e720, "IMJ,K", pa10},
-{ "xmpyu",	0x38004700, 0xfc00e720, "E,X,v", pa11},
-{ "fmpyadd",	0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
-{ "fmpysub",	0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
-{ "ftest",      0x30002420, 0xffffffff, "", pa10},
-
+ 
+{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
+{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT},
+{ "fldw",       0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT},
+{ "fldw",       0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT},
+{ "fldw",       0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT},
+{ "fldw",       0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT},
+{ "fldw",       0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
+{ "fldw",       0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT},
+{ "fldw",       0x58000000, 0xfc000004, "cJd(s,b),fe", pa20, FLAG_STRICT},
+{ "fldw",       0x58000000, 0xfc000004, "cJd(b),fe", pa20, FLAG_STRICT},
+{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
+{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT},
+{ "fldd",       0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT},
+{ "fldd",       0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT},
+{ "fldd",       0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT},
+{ "fldd",       0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT},
+{ "fldd",       0x50000002, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
+{ "fldd",       0x50000002, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT},
+{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT},
+{ "fstw",       0x7c000000, 0xfc000004, "fe,d(s,b)", pa20, FLAG_STRICT},
+{ "fstw",       0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT},
+{ "fstw",       0x78000000, 0xfc000004, "cJfe,d(s,b)", pa20, FLAG_STRICT},
+{ "fstw",       0x78000000, 0xfc000004, "cJfe,d(b)", pa20, FLAG_STRICT},
+{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT},
+{ "fstd",       0x70000002, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
+{ "fstd",       0x70000002, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT},
+{ "fldwx",      0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0},
+{ "fldwx",      0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0},
+{ "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
+{ "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0},
+{ "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
+{ "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0},
+{ "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
+{ "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0},
+{ "fldws",      0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
+{ "fldws",      0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0},
+{ "fldds",      0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
+{ "fldds",      0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0},
+{ "fstws",      0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
+{ "fstws",      0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0},
+{ "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
+{ "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0},
+{ "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
+{ "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0},
+{ "fadd",       0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fadd",       0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fsub",       0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fsub",       0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fmpy",       0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fmpy",       0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fdiv",       0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fdiv",       0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fsqrt",      0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fsqrt",      0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fabs",       0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fabs",       0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "frem",       0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "frem",       0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
+{ "frnd",       0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "frnd",       0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fcpy",       0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fcpy",       0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fcnvff",     0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvff",     0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvxf",     0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvxf",     0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvfx",     0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvfx",     0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvfxt",    0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fmpyfadd",   0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
+{ "fmpynfadd",  0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
+{ "fneg",       0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
+{ "fneg",       0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
+{ "fnegabs",    0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
+{ "fnegabs",    0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
+{ "fcnv",       0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
+{ "fcnv",       0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
+{ "fcmp",       0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
+{ "fcmp",       0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
+{ "fcmp",       0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
+{ "fcmp",       0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
+{ "xmpyu",	0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
+{ "fmpyadd",	0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
+{ "fmpysub",	0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
+{ "ftest",      0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
+{ "ftest",      0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
+{ "ftest",      0x30002420, 0xffffffff, "", pa10, 0},
+{ "fid",        0x30000000, 0xffffffff, "", pa11, 0},
+
+/* Performance Monitor Instructions */
+
+{ "pmdis",	0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
+{ "pmenb",	0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
 
 /* Assist Instructions */
 
-{ "spop0",      0x10000000, 0xfc000600, "f,ON", pa10},
-{ "spop1",      0x10000200, 0xfc000600, "f,oNt", pa10},
-{ "spop2",      0x10000400, 0xfc000600, "f,1Nb", pa10},
-{ "spop3",      0x10000600, 0xfc000600, "f,0Nx,b", pa10},
-{ "copr",       0x30000000, 0xfc000000, "u,2N", pa10},
-{ "cldwx",      0x24000000, 0xfc001e00, "ucx(s,b),t", pa10},
-{ "cldwx",      0x24000000, 0xfc001e00, "ucx(b),t", pa10},
-{ "clddx",      0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10},
-{ "clddx",      0x2c000000, 0xfc001e00, "ucx(b),t", pa10},
-{ "cstwx",      0x24000200, 0xfc001e00, "uct,x(s,b)", pa10},
-{ "cstwx",      0x24000200, 0xfc001e00, "uct,x(b)", pa10},
-{ "cstdx",      0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10},
-{ "cstdx",      0x2c000200, 0xfc001e00, "uct,x(b)", pa10},
-{ "cldws",      0x24001000, 0xfc001e00, "uC5(s,b),t", pa10},
-{ "cldws",      0x24001000, 0xfc001e00, "uC5(b),t", pa10},
-{ "cldds",      0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10},
-{ "cldds",      0x2c001000, 0xfc001e00, "uC5(b),t", pa10},
-{ "cstws",      0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10},
-{ "cstws",      0x24001200, 0xfc001e00, "uCt,5(b)", pa10},
-{ "cstds",      0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10},
-{ "cstds",      0x2c001200, 0xfc001e00, "uCt,5(b)", pa10},
+{ "spop0",      0x10000000, 0xfc000600, "v,ON", pa10, 0},
+{ "spop1",      0x10000200, 0xfc000600, "v,oNt", pa10, 0},
+{ "spop2",      0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
+{ "spop3",      0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
+{ "copr",       0x30000000, 0xfc000000, "u,2N", pa10, 0},
+{ "cldwx",      0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
+{ "cldwx",      0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
+{ "clddx",      0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
+{ "clddx",      0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
+{ "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
+{ "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
+{ "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
+{ "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
+{ "cldws",      0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
+{ "cldws",      0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
+{ "cldds",      0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
+{ "cldds",      0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
+{ "cstws",      0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
+{ "cstws",      0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
+{ "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
+{ "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
+{ "cldw",       0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT},
+{ "cstw",       0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
 };
 
 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
diff --git a/gnu/usr.bin/binutils/include/opcode/i386.h b/gnu/usr.bin/binutils/include/opcode/i386.h
index e18b8f9b3d0..d00d3311cc5 100644
--- a/gnu/usr.bin/binutils/include/opcode/i386.h
+++ b/gnu/usr.bin/binutils/include/opcode/i386.h
@@ -1,5 +1,6 @@
-/* i386-opcode.h -- Intel 80386 opcode table
-   Copyright 1989, 91, 92, 93, 94, 95, 1996 Free Software Foundation.
+/* opcode/i386.h -- Intel 80386 opcode table
+   Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
+   Free Software Foundation.
 
 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
 
@@ -17,831 +18,1188 @@ You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-static const template i386_optab[] = {
-
-#define _ None
-/* move instructions */
-#define MOV_AX_DISP32 0xa0
-{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
-{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
-{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
-{ "mov", 2, 0xc6, _,  W|Modrm,  { Imm, Reg|Mem, 0 } },
-{ "mov", 2, 0x8c, _, D|Modrm,  { SReg3|SReg2, Reg16|Mem, 0 } },
-/* move to/from control debug registers */
-{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
-{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
-{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
-
-/* move with sign extend */
-/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
-   conflict with the "movs" string move instruction.  Thus,
-   {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem,  Reg16|Reg32, 0} },
-   is not kosher; we must seperate the two instructions. */
-{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem,  Reg32, 0} },
-{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem,  Reg16, 0} },
-{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
-
-/* move with zero extend */
-{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
-{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
-
-/* push instructions */
-{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
-{"push", 1, 0xff, 0x6,  Modrm, { WordReg|WordMem, 0, 0 } },
-{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
-{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} },
-{"push", 1, 0x06, _,  Seg2ShortForm, { SReg2,0,0 } },
-{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
-/* push all */
-{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
-
-/* pop instructions */
-{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
-{"pop", 1, 0x8f, 0x0,  Modrm, { WordReg|WordMem, 0, 0 } },
-#define POP_SEG_SHORT 0x7
-{"pop", 1, 0x07, _,  Seg2ShortForm, { SReg2,0,0 } },
-{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
-/* pop all */
-{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
-
-/* xchg exchange instructions
-   xchg commutes:  we allow both operand orders */
-{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
-{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
-{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
-{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
-
-/* in/out from ports */
-{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
-{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
-{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
-{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
-{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
-{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
-{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
-{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
-
-/* load effective address */
-{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
-
-/* load segment registers from memory */
-{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
-{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
-{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
-{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
-{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
-
-/* flags register instructions */
-{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
-{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
-{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
-{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
-{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
-{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
-{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
-{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} },
-{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} },
-{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} },
-{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} },
-{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
-{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
-{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
-{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
-{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
-
-{"add", 2, 0x0,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"add", 2, 0x83, 0,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"add", 2, 0x4,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
-{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"sub", 2, 0x28,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"sub", 2, 0x83, 5,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"sub", 2, 0x2c,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"sub", 2, 0x80, 5,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
-{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"sbb", 2, 0x18,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"sbb", 2, 0x83, 3,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"sbb", 2, 0x1c,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"sbb", 2, 0x80, 3,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"cmp", 2, 0x38,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"cmp", 2, 0x83, 7,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"cmp", 2, 0x3c,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"cmp", 2, 0x80, 7,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
-{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
-{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
-{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"and", 2, 0x20,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"and", 2, 0x83, 4,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"and", 2, 0x24,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"and", 2, 0x80, 4,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"or", 2, 0x08,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"or", 2, 0x83, 1,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"or", 2, 0x0c,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"or", 2, 0x80, 1,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"xor", 2, 0x30,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"xor", 2, 0x83, 6,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"xor", 2, 0x34,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"xor", 2, 0x80, 6,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"adc", 2, 0x10,  _, DW|Modrm, { Reg, Reg|Mem, 0} },
-{"adc", 2, 0x83, 2,  Modrm, { Imm8S, WordReg|WordMem, 0} },
-{"adc", 2, 0x14,  _,  W|NoModrm, { Imm,  Acc,    0} },
-{"adc", 2, 0x80, 2,  W|Modrm, { Imm, Reg|Mem, 0} },
-
-{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
-{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
-{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
-{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
-{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
-{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
-{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
-
-/* conversion insns */
-/* conversion:  intel naming */
-{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
-{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
-{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
-{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
-/*  att naming */
-{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
-{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
-{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
-{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
-
-/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
-   expanding 64-bit multiplies, and *cannot* be selected to accomplish
-   'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
-   These multiplies can only be selected with single operand forms. */
-{"mul",  1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
-{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
-
-
-
-
-/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
-   These instructions are exceptions:  'imul $2, %eax, %ecx' would put
-   '%eax' in the reg field and '%ecx' in the regmem field if we did not
-   switch them. */
-{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
-{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
-{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
-/*
-  imul with 2 operands mimicks imul with 3 by puting register both
-  in i.rm.reg & i.rm.regmem fields
-*/
-{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
-{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
-{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
-{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
-{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
-{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
-
-{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
-{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
-{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
-{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
-
-{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
-
-{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
-{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
-{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
-
-{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
-{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
-{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
-{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
-
-/* control transfer instructions */
-#define CALL_PC_RELATIVE 0xe8
-{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
-{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
-{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
-#define CALL_FAR_IMMEDIATE 0x9a
-{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} },
-{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
-{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
-
-#define JUMP_PC_RELATIVE 0xeb
-{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
-{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
-#define JUMP_FAR_IMMEDIATE 0xea
-{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
-{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
-
-{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} },
-{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} },
-{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} },
-{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} },
-{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} },
-{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} },
-{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} },
-{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} },
-{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} },
-{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} },
-{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} },
-{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} },
-
-/* conditional jumps */
-{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
-
-{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
-
-{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
-{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
-{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
-
-{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
-{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
-{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
-
-{"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
-{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
-
-{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
-{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
-
-{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
-{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
-
-{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
-{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
-
-{"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
-
-{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
+/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
+   ix86 Unix assemblers, generate floating point instructions with
+   reversed source and destination registers in certain cases.
+   Unfortunately, gcc and possibly many other programs use this
+   reversed syntax, so we're stuck with it.
 
-{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
-{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
+   eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
+   `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
+   the expected st(3) = st(3) - st
 
-{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
-{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
+   This happens with all the non-commutative arithmetic floating point
+   operations with two register operands, where the source register is
+   %st, and destination register is %st(i).  See FloatDR below.
 
-{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
-{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
+   The affected opcode map is dceX, dcfX, deeX, defX.  */
 
-{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
-{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
-
-{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
-{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
-
-{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
-{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
-
-#if 0  /* XXX where are these macros used?
-	  To get them working again, they need to take
-	  an entire template as the parameter,
-	  and check for Data16/Data32 flags.  */
-/* these turn into pseudo operations when disp is larger than 8 bits */
-#define IS_JUMP_ON_CX_ZERO(o) \
-  (o == 0x66e3)
-#define IS_JUMP_ON_ECX_ZERO(o) \
-  (o == 0xe3)
+#ifndef SYSV386_COMPAT
+/* Set non-zero for broken, compatible instructions.  Set to zero for
+   non-broken opcodes at your peril.  gcc generates SystemV/386
+   compatible instructions.  */
+#define SYSV386_COMPAT 1
+#endif
+#ifndef OLDGCC_COMPAT
+/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
+   generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
+   reversed.  */
+#define OLDGCC_COMPAT SYSV386_COMPAT
 #endif
 
-{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} },
-{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} },
-
-#define IS_LOOP_ECX_TIMES(o) \
-  (o == 0xe2 || o == 0xe1 || o == 0xe0)
-
-{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
-
-{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
-{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
-
-{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
-{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
-
-/* set byte on flag instructions */
-{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
-
-{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
-{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
+static const template i386_optab[] = {
 
-#define IS_STRING_INSTRUCTION(o) \
-  ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
-   (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
-   (o) == 0xd7)
+#define X None
+#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
+#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
+#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
+#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf)
+#define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
+#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf)
+#define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
+#define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
+#define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
+#define wld_Suf (No_bSuf|No_sSuf|No_xSuf)
+#define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
+#define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
+#define sldx_Suf (No_bSuf|No_wSuf)
+#define bwl_Suf (No_sSuf|No_dSuf|No_xSuf)
+#define bwld_Suf (No_sSuf|No_xSuf)
+#define FP (NoSuf|IgnoreSize)
+#define l_FP (l_Suf|IgnoreSize)
+#define d_FP (d_Suf|IgnoreSize)
+#define x_FP (x_Suf|IgnoreSize)
+#define sl_FP (sl_Suf|IgnoreSize)
+#define sld_FP (sld_Suf|IgnoreSize)
+#define sldx_FP (sldx_Suf|IgnoreSize)
+#if SYSV386_COMPAT
+/* Someone forgot that the FloatR bit reverses the operation when not
+   equal to the FloatD bit.  ie. Changing only FloatD results in the
+   destination being swapped *and* the direction being reversed.  */
+#define FloatDR FloatD
+#else
+#define FloatDR (FloatD|FloatR)
+#endif
 
-/* string manipulation */
-{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
-{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
-{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
-{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
-{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
-{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
-{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
-{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
-{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
-{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
-{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
-{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
-{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
+/* Move instructions.  */
+#define MOV_AX_DISP32 0xa0
+{ "mov",   2,	0xa0, X, bwl_Suf|D|W,			{ Disp16|Disp32, Acc, 0 } },
+{ "mov",   2,	0x88, X, bwl_Suf|D|W|Modrm,		{ Reg, Reg|AnyMem, 0 } },
+{ "mov",   2,	0xb0, X, bwl_Suf|W|ShortForm,		{ Imm, Reg, 0 } },
+{ "mov",   2,	0xc6, X, bwl_Suf|W|Modrm,		{ Imm, Reg|AnyMem, 0 } },
+/* The next two instructions accept WordReg so that a segment register
+   can be copied to a 32 bit register, and vice versa, without using a
+   size prefix.  When moving to a 32 bit register, the upper 16 bits
+   are set to an implementation defined value (on the Pentium Pro,
+   the implementation defined value is zero).  */
+{ "mov",   2,	0x8c, X, wl_Suf|Modrm,			{ SReg3|SReg2, WordReg|WordMem, 0 } },
+{ "mov",   2,	0x8e, X, wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg3|SReg2, 0 } },
+/* Move to/from control debug registers.  */
+{ "mov",   2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize,	{ Control, Reg32|InvMem, 0} },
+{ "mov",   2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize,	{ Debug, Reg32|InvMem, 0} },
+{ "mov",   2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize,	{ Test, Reg32|InvMem, 0} },
+
+/* Move with sign extend.  */
+/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
+   conflict with the "movs" string move instruction.  */
+{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm,			{ Reg8|ByteMem, Reg32, 0} },
+{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm,			{ Reg8|ByteMem, Reg16, 0} },
+{"movswl", 2, 0x0fbf, X, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
+/* Intel Syntax next 2 insns */
+{"movsx",  2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
+{"movsx",  2, 0x0fbe, X, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+
+/* Move with zero extend.  */
+{"movzb",  2, 0x0fb6, X, wl_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
+/* Intel Syntax next 2 insns */
+{"movzx",  2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
+{"movzx",  2, 0x0fb6, X, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+
+/* Push instructions.  */
+{"push",   1,	0x50, X, wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
+{"push",   1,	0xff, 6, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
+{"push",   1,	0x6a, X, wl_Suf|DefaultSize,		{ Imm8S, 0, 0} },
+{"push",   1,	0x68, X, wl_Suf|DefaultSize,		{ Imm16|Imm32, 0, 0} },
+{"push",   1,	0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
+{"push",   1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
+{"pusha",  0,	0x60, X, wld_Suf|DefaultSize,		{ 0, 0, 0 } },
+
+/* Pop instructions.  */
+{"pop",	   1,	0x58, X, wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
+{"pop",	   1,	0x8f, 0, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
+#define POP_SEG_SHORT 0x07
+{"pop",	   1,	0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
+{"pop",	   1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
+{"popa",   0,	0x61, X, wld_Suf|DefaultSize,		{ 0, 0, 0 } },
+
+/* Exchange instructions.
+   xchg commutes:  we allow both operand orders.  */
+{"xchg",   2,	0x90, X, wl_Suf|ShortForm,	{ WordReg, Acc, 0 } },
+{"xchg",   2,	0x90, X, wl_Suf|ShortForm,	{ Acc, WordReg, 0 } },
+{"xchg",   2,	0x86, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"xchg",   2,	0x86, X, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0 } },
+
+/* In/out from ports.  */
+{"in",	   2,	0xe4, X, bwl_Suf|W,		{ Imm8, Acc, 0 } },
+{"in",	   2,	0xec, X, bwl_Suf|W,		{ InOutPortReg, Acc, 0 } },
+{"in",	   1,	0xe4, X, bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"in",	   1,	0xec, X, bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
+{"out",	   2,	0xe6, X, bwl_Suf|W,		{ Acc, Imm8, 0 } },
+{"out",	   2,	0xee, X, bwl_Suf|W,		{ Acc, InOutPortReg, 0 } },
+{"out",	   1,	0xe6, X, bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"out",	   1,	0xee, X, bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
+
+/* Load effective address.  */
+{"lea",	   2, 0x8d,   X, wl_Suf|Modrm,		{ WordMem, WordReg, 0 } },
+
+/* Load segment registers from memory.  */
+{"lds",	   2,	0xc5, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"les",	   2,	0xc4, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lfs",	   2, 0x0fb4, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lgs",	   2, 0x0fb5, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lss",	   2, 0x0fb2, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+
+/* Flags register instructions.  */
+{"clc",	   0,	0xf8, X, NoSuf,			{ 0, 0, 0} },
+{"cld",	   0,	0xfc, X, NoSuf,			{ 0, 0, 0} },
+{"cli",	   0,	0xfa, X, NoSuf,			{ 0, 0, 0} },
+{"clts",   0, 0x0f06, X, NoSuf,			{ 0, 0, 0} },
+{"cmc",	   0,	0xf5, X, NoSuf,			{ 0, 0, 0} },
+{"lahf",   0,	0x9f, X, NoSuf,			{ 0, 0, 0} },
+{"sahf",   0,	0x9e, X, NoSuf,			{ 0, 0, 0} },
+{"pushf",  0,	0x9c, X, wld_Suf|DefaultSize,	{ 0, 0, 0} },
+{"popf",   0,	0x9d, X, wld_Suf|DefaultSize,	{ 0, 0, 0} },
+{"stc",	   0,	0xf9, X, NoSuf,			{ 0, 0, 0} },
+{"std",	   0,	0xfd, X, NoSuf,			{ 0, 0, 0} },
+{"sti",	   0,	0xfb, X, NoSuf,			{ 0, 0, 0} },
+
+/* Arithmetic.  */
+{"add",	   2,	0x00, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"add",	   2,	0x83, 0, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"add",	   2,	0x04, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"add",	   2,	0x80, 0, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"inc",	   1,	0x40, X, wl_Suf|ShortForm,	{ WordReg, 0, 0} },
+{"inc",	   1,	0xfe, 0, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sub",	   2,	0x28, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"sub",	   2,	0x83, 5, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"sub",	   2,	0x2c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"sub",	   2,	0x80, 5, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"dec",	   1,	0x48, X, wl_Suf|ShortForm,	{ WordReg, 0, 0} },
+{"dec",	   1,	0xfe, 1, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sbb",	   2,	0x18, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"sbb",	   2,	0x83, 3, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"sbb",	   2,	0x1c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"sbb",	   2,	0x80, 3, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"cmp",	   2,	0x38, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"cmp",	   2,	0x83, 7, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"cmp",	   2,	0x3c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"cmp",	   2,	0x80, 7, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"test",   2,	0x84, X, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0} },
+{"test",   2,	0x84, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"test",   2,	0xa8, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"test",   2,	0xf6, 0, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"and",	   2,	0x20, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"and",	   2,	0x83, 4, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"and",	   2,	0x24, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"and",	   2,	0x80, 4, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"or",	   2,	0x08, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"or",	   2,	0x83, 1, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"or",	   2,	0x0c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"or",	   2,	0x80, 1, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"xor",	   2,	0x30, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"xor",	   2,	0x83, 6, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"xor",	   2,	0x34, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"xor",	   2,	0x80, 6, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+/* clr with 1 operand is really xor with 2 operands.  */
+{"clr",	   1,	0x30, X, bwl_Suf|W|Modrm|regKludge,	{ Reg, 0, 0 } },
+
+{"adc",	   2,	0x10, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"adc",	   2,	0x83, 2, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"adc",	   2,	0x14, X, bwl_Suf|W,		{ Imm, Acc, 0} },
+{"adc",	   2,	0x80, 2, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"neg",	   1,	0xf6, 3, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"not",	   1,	0xf6, 2, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"aaa",	   0,	0x37, X, NoSuf,			{ 0, 0, 0} },
+{"aas",	   0,	0x3f, X, NoSuf,			{ 0, 0, 0} },
+{"daa",	   0,	0x27, X, NoSuf,			{ 0, 0, 0} },
+{"das",	   0,	0x2f, X, NoSuf,			{ 0, 0, 0} },
+{"aad",	   0, 0xd50a, X, NoSuf,			{ 0, 0, 0} },
+{"aad",	   1,   0xd5, X, NoSuf,			{ Imm8S, 0, 0} },
+{"aam",	   0, 0xd40a, X, NoSuf,			{ 0, 0, 0} },
+{"aam",	   1,   0xd4, X, NoSuf,			{ Imm8S, 0, 0} },
+
+/* Conversion insns.  */
+/* Intel naming */
+{"cbw",	   0,	0x98, X, NoSuf|Size16,		{ 0, 0, 0} },
+{"cwde",   0,	0x98, X, NoSuf|Size32,		{ 0, 0, 0} },
+{"cwd",	   0,	0x99, X, NoSuf|Size16,		{ 0, 0, 0} },
+{"cdq",	   0,	0x99, X, NoSuf|Size32,		{ 0, 0, 0} },
+/* AT&T naming */
+{"cbtw",   0,	0x98, X, NoSuf|Size16,		{ 0, 0, 0} },
+{"cwtl",   0,	0x98, X, NoSuf|Size32,		{ 0, 0, 0} },
+{"cwtd",   0,	0x99, X, NoSuf|Size16,		{ 0, 0, 0} },
+{"cltd",   0,	0x99, X, NoSuf|Size32,		{ 0, 0, 0} },
 
-/* bit manipulation */
-{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
-{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
-{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
-{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
-{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
-{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
-{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
-{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
-{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
-{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
+/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
+   expanding 64-bit multiplies, and *cannot* be selected to accomplish
+   'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
+   These multiplies can only be selected with single operand forms.  */
+{"mul",	   1,	0xf6, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"imul",   1,	0xf6, 5, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"imul",   2, 0x0faf, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"imul",   3,	0x6b, X, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, WordReg} },
+{"imul",   3,	0x69, X, wl_Suf|Modrm,		{ Imm16|Imm32, WordReg|WordMem, WordReg} },
+/* imul with 2 operands mimics imul with 3 by putting the register in
+   both i.rm.reg & i.rm.regmem fields.  regKludge enables this
+   transformation.  */
+{"imul",   2,	0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
+{"imul",   2,	0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
+
+{"div",	   1,	0xf6, 6, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"div",	   2,	0xf6, 6, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
+{"idiv",   1,	0xf6, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"idiv",   2,	0xf6, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
+
+{"rol",	   2,	0xd0, 0, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rol",	   2,	0xc0, 0, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rol",	   2,	0xd2, 0, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rol",	   1,	0xd0, 0, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"ror",	   2,	0xd0, 1, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"ror",	   2,	0xc0, 1, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"ror",	   2,	0xd2, 1, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"ror",	   1,	0xd0, 1, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"rcl",	   2,	0xd0, 2, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rcl",	   2,	0xc0, 2, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rcl",	   2,	0xd2, 2, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rcl",	   1,	0xd0, 2, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"rcr",	   2,	0xd0, 3, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rcr",	   2,	0xc0, 3, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rcr",	   2,	0xd2, 3, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rcr",	   1,	0xd0, 3, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sal",	   2,	0xd0, 4, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"sal",	   2,	0xc0, 4, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"sal",	   2,	0xd2, 4, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"sal",	   1,	0xd0, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"shl",	   2,	0xd0, 4, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"shl",	   2,	0xc0, 4, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"shl",	   2,	0xd2, 4, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"shl",	   1,	0xd0, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"shr",	   2,	0xd0, 5, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"shr",	   2,	0xc0, 5, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"shr",	   2,	0xd2, 5, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"shr",	   1,	0xd0, 5, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sar",	   2,	0xd0, 7, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"sar",	   2,	0xc0, 7, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"sar",	   2,	0xd2, 7, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"sar",	   1,	0xd0, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"shld",   3, 0x0fa4, X, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
+{"shld",   3, 0x0fa5, X, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
+{"shld",   2, 0x0fa5, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+
+{"shrd",   3, 0x0fac, X, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
+{"shrd",   3, 0x0fad, X, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
+{"shrd",   2, 0x0fad, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+
+/* Control transfer instructions.  */
+{"call",   1,	0xe8, X, wl_Suf|JumpDword|DefaultSize,	{ Disp16|Disp32, 0, 0} },
+{"call",   1,	0xff, 2, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+/* Intel Syntax */
+{"call",   2,	0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
+/* Intel Syntax */
+{"call",   1,	0xff, 3, x_Suf|Modrm|DefaultSize,	{ WordMem, 0, 0} },
+{"lcall",  2,	0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
+{"lcall",  1,	0xff, 3, wl_Suf|Modrm|DefaultSize,	{ WordMem|JumpAbsolute, 0, 0} },
 
-/* interrupts & op. sys insns */
+#define JUMP_PC_RELATIVE 0xeb
+{"jmp",	   1,	0xeb, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jmp",	   1,	0xff, 4, wl_Suf|Modrm,		{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+/* Intel Syntax */
+{"jmp",    2,	0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
+/* Intel Syntax */
+{"jmp",    1,	0xff, 5, x_Suf|Modrm,		{ WordMem, 0, 0} },
+{"ljmp",   2,	0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
+{"ljmp",   1,	0xff, 5, wl_Suf|Modrm,		{ WordMem|JumpAbsolute, 0, 0} },
+
+{"ret",	   0,	0xc3, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
+{"ret",	   1,	0xc2, X, wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
+{"lret",   0,	0xcb, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
+{"lret",   1,	0xca, X, wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
+{"enter",  2,	0xc8, X, wl_Suf|DefaultSize,	{ Imm16, Imm8, 0} },
+{"leave",  0,	0xc9, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
+
+/* Conditional jumps.  */
+{"jo",	   1,	0x70, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jno",	   1,	0x71, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jb",	   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jc",	   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnae",   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnb",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnc",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jae",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"je",	   1,	0x74, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jz",	   1,	0x74, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jne",	   1,	0x75, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnz",	   1,	0x75, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jbe",	   1,	0x76, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jna",	   1,	0x76, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnbe",   1,	0x77, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"ja",	   1,	0x77, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"js",	   1,	0x78, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jns",	   1,	0x79, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jp",	   1,	0x7a, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jpe",	   1,	0x7a, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnp",	   1,	0x7b, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jpo",	   1,	0x7b, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jl",	   1,	0x7c, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnge",   1,	0x7c, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnl",	   1,	0x7d, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jge",	   1,	0x7d, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jle",	   1,	0x7e, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jng",	   1,	0x7e, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnle",   1,	0x7f, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jg",	   1,	0x7f, X, NoSuf|Jump,		{ Disp, 0, 0} },
+
+/* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
+{"jcxz",   1,	0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
+{"jecxz",  1,	0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+
+/* The loop instructions also use the address size prefix to select
+   %cx rather than %ecx for the loop count, so the `w' form of these
+   instructions emit an address size prefix rather than a data size
+   prefix.  */
+{"loop",   1,	0xe2, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopz",  1,	0xe1, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loope",  1,	0xe1, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopnz", 1,	0xe0, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopne", 1,	0xe0, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+
+/* Set byte on flag instructions.  */
+{"seto",   1, 0x0f90, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setno",  1, 0x0f91, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setb",   1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setc",   1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnae", 1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnb",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnc",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setae",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"sete",   1, 0x0f94, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setz",   1, 0x0f94, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setne",  1, 0x0f95, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnz",  1, 0x0f95, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setbe",  1, 0x0f96, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setna",  1, 0x0f96, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"seta",   1, 0x0f97, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"sets",   1, 0x0f98, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setns",  1, 0x0f99, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setp",   1, 0x0f9a, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setpe",  1, 0x0f9a, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnp",  1, 0x0f9b, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setpo",  1, 0x0f9b, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setl",   1, 0x0f9c, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnl",  1, 0x0f9d, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setge",  1, 0x0f9d, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setle",  1, 0x0f9e, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setng",  1, 0x0f9e, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setg",   1, 0x0f9f, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+
+/* String manipulation.  */
+{"cmps",   0,	0xa6, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"cmps",   2,	0xa6, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
+{"scmp",   0,	0xa6, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"scmp",   2,	0xa6, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
+{"ins",	   0,	0x6c, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ins",	   2,	0x6c, X, bwld_Suf|W|IsString,	{ InOutPortReg, AnyMem|EsSeg, 0} },
+{"outs",   0,	0x6e, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"outs",   2,	0x6e, X, bwld_Suf|W|IsString,	{ AnyMem, InOutPortReg, 0} },
+{"lods",   0,	0xac, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"lods",   1,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
+{"lods",   2,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
+{"slod",   0,	0xac, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"slod",   1,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
+{"slod",   2,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
+{"movs",   0,	0xa4, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"movs",   2,	0xa4, X, bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
+{"smov",   0,	0xa4, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"smov",   2,	0xa4, X, bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
+{"scas",   0,	0xae, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"scas",   1,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"scas",   2,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
+{"ssca",   0,	0xae, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ssca",   1,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"ssca",   2,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
+{"stos",   0,	0xaa, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"stos",   1,	0xaa, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"stos",   2,	0xaa, X, bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
+{"ssto",   0,	0xaa, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ssto",   1,	0xaa, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"ssto",   2,	0xaa, X, bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
+{"xlat",   0,	0xd7, X, b_Suf|IsString,	{ 0, 0, 0} },
+{"xlat",   1,	0xd7, X, b_Suf|IsString,	{ AnyMem, 0, 0} },
+
+/* Bit manipulation.  */
+{"bsf",	   2, 0x0fbc, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"bsr",	   2, 0x0fbd, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"bt",	   2, 0x0fa3, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"bt",	   2, 0x0fba, 4, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"btc",	   2, 0x0fbb, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"btc",	   2, 0x0fba, 7, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"btr",	   2, 0x0fb3, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"btr",	   2, 0x0fba, 6, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"bts",	   2, 0x0fab, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"bts",	   2, 0x0fba, 5, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+
+/* Interrupts & op. sys insns.  */
 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
-   int 3 insn. */
+   int 3 insn.  */
 #define INT_OPCODE 0xcd
 #define INT3_OPCODE 0xcc
-{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
-{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
-{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
-{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} },
-{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} },
-/* i386sl, i486sl, later 486, and Pentium */
-{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} },
-
-{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} },
-{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} },
-
-{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
-{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
-/* nop is actually 'xchgl %eax, %eax' */
-{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
-
-/* protection control */
-{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
-{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
-{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
-{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
-{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
-{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
-{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
-{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
-
-{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
-{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
-{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
-{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
-{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
-
-{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
-{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
-
-/* floating point instructions */
+{"int",	   1,	0xcd, X, NoSuf,			{ Imm8, 0, 0} },
+{"int3",   0,	0xcc, X, NoSuf,			{ 0, 0, 0} },
+{"into",   0,	0xce, X, NoSuf,			{ 0, 0, 0} },
+{"iret",   0,	0xcf, X, wld_Suf|DefaultSize,	{ 0, 0, 0} },
+/* i386sl, i486sl, later 486, and Pentium.  */
+{"rsm",	   0, 0x0faa, X, NoSuf,			{ 0, 0, 0} },
+
+{"bound",  2,	0x62, X, wl_Suf|Modrm,		{ WordReg, WordMem, 0} },
+
+{"hlt",	   0,	0xf4, X, NoSuf,			{ 0, 0, 0} },
+/* nop is actually 'xchgl %eax, %eax'.  */
+{"nop",	   0,	0x90, X, NoSuf,			{ 0, 0, 0} },
+
+/* Protection control.  */
+{"arpl",   2,	0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
+{"lar",	   2, 0x0f02, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"lgdt",   1, 0x0f01, 2, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"lidt",   1, 0x0f01, 3, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"lldt",   1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"lmsw",   1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"lsl",	   2, 0x0f03, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"ltr",	   1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+
+{"sgdt",   1, 0x0f01, 0, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"sidt",   1, 0x0f01, 1, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
+{"str",	   1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+
+{"verr",   1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"verw",   1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+
+/* Floating point instructions.  */
 
 /* load */
-{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem float */
-{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem double */
-{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem word (16) */
-{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} },	/* %st0 <-- mem dword (32) */
-{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem qword (64) */
-{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} },	/* %st0 <-- mem qword (64) */
-{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem efloat */
-{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} },		/* %st0 <-- mem bcd */
+{"fld",	   1, 0xd9c0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fld",	   1,	0xd9, 0, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fld",	   1, 0xd9c0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+/* Intel Syntax */
+{"fld",    1,	0xdb, 5, x_FP|Modrm,		{ LLongMem, 0, 0} },
+{"fild",   1,	0xdf, 0, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+/* Intel Syntax */
+{"fildd",  1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fildq",  1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fildll", 1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fldt",   1,	0xdb, 5, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fbld",   1,	0xdf, 4, FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* store (no pop) */
-{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem float */
-{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem double */
-{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} },		/* %st0 --> mem word (16) */
-{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} },	/* %st0 --> mem dword (32) */
+{"fst",	   1, 0xddd0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fst",	   1,	0xd9, 2, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fst",	   1, 0xddd0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fist",   1,	0xdf, 2, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 /* store (with pop) */
-{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem float */
-{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem double */
-{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
-{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem word (16) */
-{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} },	/* %st0 --> mem dword (32) */
-{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem qword (64) */
-{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem qword (64) */
-{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} },	/* %st0 --> mem efloat */
-{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} },	/* %st0 --> mem bcd */
+{"fstp",   1, 0xddd8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fstp",   1,	0xd9, 3, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fstp",   1, 0xddd8, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+/* Intel Syntax */
+{"fstp",   1,	0xdb, 7, x_FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistp",  1,	0xdf, 3, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+/* Intel Syntax */
+{"fistpd", 1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistpq", 1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistpll",1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fstpt",  1,	0xdb, 7, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fbstp",  1,	0xdf, 6, FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* exchange %st<n> with %st0 */
-{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
-{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
+{"fxch",   1, 0xd9c8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fxch %st(1) */
+{"fxch",   0, 0xd9c9, X, FP,			{ 0, 0, 0} },
 
 /* comparison (without pop) */
-{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
-{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
-{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */ 
-{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
-{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
-{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
+{"fcom",   1, 0xd8d0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fcom %st(1) */
+{"fcom",   0, 0xd8d1, X, FP,			{ 0, 0, 0} },
+{"fcom",   1,	0xd8, 2, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fcom",   1, 0xd8d0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"ficom",  1,	0xde, 2, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 /* comparison (with pop) */
-{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
-{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
-{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */ 
-{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
-{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
-{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
-{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} },	/* compare %st0, %st1 & pop 2 */
+{"fcomp",  1, 0xd8d8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fcomp %st(1) */
+{"fcomp",  0, 0xd8d9, X, FP,			{ 0, 0, 0} },
+{"fcomp",  1,	0xd8, 3, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fcomp",  1, 0xd8d8, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"ficomp", 1,	0xde, 3, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fcompp", 0, 0xded9, X, FP,			{ 0, 0, 0} },
 
 /* unordered comparison (with pop) */
-{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
-{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
-{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
+{"fucom",  1, 0xdde0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fucom %st(1) */
+{"fucom",  0, 0xdde1, X, FP,			{ 0, 0, 0} },
+{"fucomp", 1, 0xdde8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fucomp %st(1) */
+{"fucomp", 0, 0xdde9, X, FP,			{ 0, 0, 0} },
+{"fucompp",0, 0xdae9, X, FP,			{ 0, 0, 0} },
 
-{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} },	/* test %st0 */
-{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} },	/* examine %st0 */
+{"ftst",   0, 0xd9e4, X, FP,			{ 0, 0, 0} },
+{"fxam",   0, 0xd9e5, X, FP,			{ 0, 0, 0} },
 
 /* load constants into %st0 */
-{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- 1.0 */
-{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log2(10) */
-{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log2(e) */
-{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- pi */
-{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- log10(2) */
-{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- ln(2) */
-{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} },	/* %st0 <-- 0.0 */
+{"fld1",   0, 0xd9e8, X, FP,			{ 0, 0, 0} },
+{"fldl2t", 0, 0xd9e9, X, FP,			{ 0, 0, 0} },
+{"fldl2e", 0, 0xd9ea, X, FP,			{ 0, 0, 0} },
+{"fldpi",  0, 0xd9eb, X, FP,			{ 0, 0, 0} },
+{"fldlg2", 0, 0xd9ec, X, FP,			{ 0, 0, 0} },
+{"fldln2", 0, 0xd9ed, X, FP,			{ 0, 0, 0} },
+{"fldz",   0, 0xd9ee, X, FP,			{ 0, 0, 0} },
 
 /* arithmetic */
 
 /* add */
-{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
-{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
-{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
-{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} },
-{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} },
-{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
-{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
-{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
-{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
-{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
-
-/* sub */
-/* Note:  intel has decided that certain of these operations are reversed
-   in assembler syntax. */
-{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
-{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
-#else
-{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fadd",   2, 0xd8c0, X, FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
+/* alias for fadd %st(i), %st */
+{"fadd",   1, 0xd8c0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for faddp */
+{"fadd",   0, 0xdec1, X, FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
-{"fsubp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} },
-{"fsubp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
-#else
-{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fadd",   1,	0xd8, 0, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fiadd",  1,	0xde, 0, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+{"faddp",  2, 0xdec0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"faddp",  1, 0xdec0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for faddp %st, %st(1) */
+{"faddp",  0, 0xdec1, X, FP,			{ 0, 0, 0} },
+{"faddp",  2, 0xdec0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+
+/* subtract */
+{"fsub",   2, 0xd8e0, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fsub",   1, 0xd8e0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for fsubp */
+{"fsub",   0, 0xdee1, X, FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
-{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
-{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
-{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
-{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
-
-/* sub reverse */
-{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
-{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
-#else
-{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsub",   1,	0xd8, 4, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fisub",  1,	0xde, 4, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+#if SYSV386_COMPAT
+{"fsubp",  2, 0xdee0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubp",  1, 0xdee0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubp",  0, 0xdee1, X, FP,			{ 0, 0, 0} },
+#if OLDGCC_COMPAT
+{"fsubp",  2, 0xdee0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
-{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
-{"fsubrp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} },
-{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
 #else
-{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubp",  2, 0xdee8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubp",  1, 0xdee8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubp",  0, 0xdee9, X, FP,			{ 0, 0, 0} },
 #endif
-{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
-{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
-{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
-{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
-{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
-
-/* mul */
-{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
-{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
-{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
-{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} },
-{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} },
-{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
-{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
-{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
-{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
-{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
-
-/* div */
-/* Note:  intel has decided that certain of these operations are reversed
-   in assembler syntax. */
-{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
-{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
-#else
-{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+
+/* subtract reverse */
+{"fsubr",  2, 0xd8e8, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fsubr",  1, 0xd8e8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for fsubrp */
+{"fsubr",  0, 0xdee9, X, FP|Ugh,		{ 0, 0, 0} },
+#endif
+{"fsubr",  1,	0xd8, 5, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fisubr", 1,	0xde, 5, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+#if SYSV386_COMPAT
+{"fsubrp", 2, 0xdee8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee9, X, FP,			{ 0, 0, 0} },
+#if OLDGCC_COMPAT
+{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
-{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
-{"fdivp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} },
-{"fdivp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
 #else
-{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fsubrp", 2, 0xdee0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee1, X, FP,			{ 0, 0, 0} },
+#endif
+
+/* multiply */
+{"fmul",   2, 0xd8c8, X, FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
+{"fmul",   1, 0xd8c8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for fmulp */
+{"fmul",   0, 0xdec9, X, FP|Ugh,		{ 0, 0, 0} },
+#endif
+{"fmul",   1,	0xd8, 1, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fimul",  1,	0xde, 1, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+{"fmulp",  2, 0xdec8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fmulp",  1, 0xdec8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fmulp",  0, 0xdec9, X, FP,			{ 0, 0, 0} },
+{"fmulp",  2, 0xdec8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+
+/* divide */
+{"fdiv",   2, 0xd8f0, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fdiv",   1, 0xd8f0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for fdivp */
+{"fdiv",   0, 0xdef1, X, FP|Ugh,		{ 0, 0, 0} },
+#endif
+{"fdiv",   1,	0xd8, 6, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fidiv",  1,	0xde, 6, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+#if SYSV386_COMPAT
+{"fdivp",  2, 0xdef0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivp",  1, 0xdef0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivp",  0, 0xdef1, X, FP,			{ 0, 0, 0} },
+#if OLDGCC_COMPAT
+{"fdivp",  2, 0xdef0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
-{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
-{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
-{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
-{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
-{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
-
-/* div reverse */
-{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
-{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
 #else
-{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivp",  2, 0xdef8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivp",  1, 0xdef8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivp",  0, 0xdef9, X, FP,			{ 0, 0, 0} },
+#endif
+
+/* divide reverse */
+{"fdivr",  2, 0xd8f8, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fdivr",  1, 0xd8f8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+#if SYSV386_COMPAT
+/* alias for fdivrp */
+{"fdivr",  0, 0xdef9, X, FP|Ugh,		{ 0, 0, 0} },
+#endif
+{"fdivr",  1,	0xd8, 7, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fidivr", 1,	0xde, 7, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+
+#if SYSV386_COMPAT
+{"fdivrp", 2, 0xdef8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef9, X, FP,			{ 0, 0, 0} },
+#if OLDGCC_COMPAT
+{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
-{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
-{"fdivrp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} },
-{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-#ifdef NON_BROKEN_OPCODES
-{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
 #else
-{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
+{"fdivrp", 2, 0xdef0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef1, X, FP,			{ 0, 0, 0} },
 #endif
-{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
-{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
-{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
-{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
-{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
-
-{"f2xm1", 0,   0xd9f0, _, NoModrm, { 0, 0, 0} },
-{"fyl2x", 0,   0xd9f1, _, NoModrm, { 0, 0, 0} },
-{"fptan", 0,   0xd9f2, _, NoModrm, { 0, 0, 0} },
-{"fpatan", 0,  0xd9f3, _, NoModrm, { 0, 0, 0} },
-{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
-{"fprem1", 0,  0xd9f5, _, NoModrm, { 0, 0, 0} },
-{"fdecstp", 0,  0xd9f6, _, NoModrm, { 0, 0, 0} },
-{"fincstp", 0,  0xd9f7, _, NoModrm, { 0, 0, 0} },
-{"fprem", 0,   0xd9f8, _, NoModrm, { 0, 0, 0} },
-{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
-{"fsqrt", 0,   0xd9fa, _, NoModrm, { 0, 0, 0} },
-{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
-{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
-{"fscale", 0,  0xd9fd, _, NoModrm, { 0, 0, 0} },
-{"fsin", 0,    0xd9fe, _, NoModrm, { 0, 0, 0} },
-{"fcos", 0,    0xd9ff, _, NoModrm, { 0, 0, 0} },
-
-{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
-{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
+
+{"f2xm1",  0, 0xd9f0, X, FP,			{ 0, 0, 0} },
+{"fyl2x",  0, 0xd9f1, X, FP,			{ 0, 0, 0} },
+{"fptan",  0, 0xd9f2, X, FP,			{ 0, 0, 0} },
+{"fpatan", 0, 0xd9f3, X, FP,			{ 0, 0, 0} },
+{"fxtract",0, 0xd9f4, X, FP,			{ 0, 0, 0} },
+{"fprem1", 0, 0xd9f5, X, FP,			{ 0, 0, 0} },
+{"fdecstp",0, 0xd9f6, X, FP,			{ 0, 0, 0} },
+{"fincstp",0, 0xd9f7, X, FP,			{ 0, 0, 0} },
+{"fprem",  0, 0xd9f8, X, FP,			{ 0, 0, 0} },
+{"fyl2xp1",0, 0xd9f9, X, FP,			{ 0, 0, 0} },
+{"fsqrt",  0, 0xd9fa, X, FP,			{ 0, 0, 0} },
+{"fsincos",0, 0xd9fb, X, FP,			{ 0, 0, 0} },
+{"frndint",0, 0xd9fc, X, FP,			{ 0, 0, 0} },
+{"fscale", 0, 0xd9fd, X, FP,			{ 0, 0, 0} },
+{"fsin",   0, 0xd9fe, X, FP,			{ 0, 0, 0} },
+{"fcos",   0, 0xd9ff, X, FP,			{ 0, 0, 0} },
+{"fchs",   0, 0xd9e0, X, FP,			{ 0, 0, 0} },
+{"fabs",   0, 0xd9e1, X, FP,			{ 0, 0, 0} },
 
 /* processor control */
-{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
-{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} },
-{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
-{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
-{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} },
-{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
-{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
-{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
-{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} },
-{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} },
-{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} },
-{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
-{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} },
-/*
- We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
- instructions;  i'm not sure how to add them or how they are different.
- My 386/387 book offers no details about this.
-*/
-{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
-{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} },
-{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
-{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
-{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} },
-{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
-
-{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
+{"fninit", 0, 0xdbe3, X, FP,			{ 0, 0, 0} },
+{"finit",  0, 0xdbe3, X, FP|FWait,		{ 0, 0, 0} },
+{"fldcw",  1,	0xd9, 5, FP|Modrm,		{ ShortMem, 0, 0} },
+{"fnstcw", 1,	0xd9, 7, FP|Modrm,		{ ShortMem, 0, 0} },
+{"fstcw",  1,	0xd9, 7, FP|FWait|Modrm,	{ ShortMem, 0, 0} },
+{"fnstsw", 1, 0xdfe0, X, FP,			{ Acc, 0, 0} },
+{"fnstsw", 1,	0xdd, 7, FP|Modrm,		{ ShortMem, 0, 0} },
+{"fnstsw", 0, 0xdfe0, X, FP,			{ 0, 0, 0} },
+{"fstsw",  1, 0xdfe0, X, FP|FWait,		{ Acc, 0, 0} },
+{"fstsw",  1,	0xdd, 7, FP|FWait|Modrm,	{ ShortMem, 0, 0} },
+{"fstsw",  0, 0xdfe0, X, FP|FWait,		{ 0, 0, 0} },
+{"fnclex", 0, 0xdbe2, X, FP,			{ 0, 0, 0} },
+{"fclex",  0, 0xdbe2, X, FP|FWait,		{ 0, 0, 0} },
+/* Short forms of fldenv, fstenv use data size prefix.  */
+{"fnstenv",1,	0xd9, 6, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fstenv", 1,	0xd9, 6, sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
+{"fldenv", 1,	0xd9, 4, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fnsave", 1,	0xdd, 6, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fsave",  1,	0xdd, 6, sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
+{"frstor", 1,	0xdd, 4, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+
+{"ffree",  1, 0xddc0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
 /* P6:free st(i), pop st */
-{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} },
-{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
-{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
-
-/*
-  opcode prefixes; we allow them as seperate insns too
-  (see prefix table below)
-*/
-{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
-{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
-{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
-{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
-{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
-{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
-{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
-{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
-{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
-{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
-{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
-{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
-{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
-{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
-{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
-{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
-
-/* 486 extensions */
-
-{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
-{"xadd", 2, 0x0fc0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
-{"cmpxchg", 2, 0x0fb0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
-{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
-{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
-{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
-
-/* 586 and late 486 extensions */
-{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} },
-
-/* Pentium extensions */
-{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} },
-{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} },
-{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} },
-{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
-
-/* Pentium Pro extensions */
-{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} },
-
-{"cmovo",  2, 0x0f40, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovno", 2, 0x0f41, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovb",  2, 0x0f42, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovae", 2, 0x0f43, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmove",  2, 0x0f44, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovne", 2, 0x0f45, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovbe", 2, 0x0f46, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmova",  2, 0x0f47, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovs",  2, 0x0f48, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovns", 2, 0x0f49, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovp",  2, 0x0f4a, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovnp", 2, 0x0f4b, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovl",  2, 0x0f4c, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovge", 2, 0x0f4d, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovle", 2, 0x0f4e, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-{"cmovg",  2, 0x0f4f, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
-
-{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-
-{"fcomi",  2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} },
-{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
-
-{"", 0, 0, 0, 0, { 0, 0, 0} }	/* sentinel */
-};
-#undef _
+{"ffreep", 1, 0xdfc0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fnop",   0, 0xd9d0, X, FP,			{ 0, 0, 0} },
+#define FWAIT_OPCODE 0x9b
+{"fwait",  0,	0x9b, X, FP,			{ 0, 0, 0} },
 
-static const template *const i386_optab_end
-  = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
+/* Opcode prefixes; we allow them as separate insns too.  */
 
-/* 386 register table */
+#define ADDR_PREFIX_OPCODE 0x67
+{"addr16", 0,	0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"addr32", 0,	0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"aword",  0,	0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"adword", 0,	0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+#define DATA_PREFIX_OPCODE 0x66
+{"data16", 0,	0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"data32", 0,	0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"word",   0,	0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"dword",  0,	0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+#define LOCK_PREFIX_OPCODE 0xf0
+{"lock",   0,	0xf0, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"wait",   0,   0x9b, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define CS_PREFIX_OPCODE 0x2e
+{"cs",	   0,	0x2e, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define DS_PREFIX_OPCODE 0x3e
+{"ds",	   0,	0x3e, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define ES_PREFIX_OPCODE 0x26
+{"es",	   0,	0x26, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define FS_PREFIX_OPCODE 0x64
+{"fs",	   0,	0x64, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define GS_PREFIX_OPCODE 0x65
+{"gs",	   0,	0x65, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define SS_PREFIX_OPCODE 0x36
+{"ss",	   0,	0x36, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+#define REPNE_PREFIX_OPCODE 0xf2
+#define REPE_PREFIX_OPCODE  0xf3
+{"rep",	   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repe",   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repz",   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repne",  0,	0xf2, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repnz",  0,	0xf2, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+
+/* 486 extensions.  */
+
+{"bswap",   1, 0x0fc8, X, l_Suf|ShortForm,	{ Reg32, 0, 0 } },
+{"xadd",    2, 0x0fc0, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"invd",    0, 0x0f08, X, NoSuf,		{ 0, 0, 0} },
+{"wbinvd",  0, 0x0f09, X, NoSuf,		{ 0, 0, 0} },
+{"invlpg",  1, 0x0f01, 7, NoSuf|Modrm,		{ AnyMem, 0, 0} },
+
+/* 586 and late 486 extensions.  */
+{"cpuid",   0, 0x0fa2, X, NoSuf,		{ 0, 0, 0} },
+
+/* Pentium extensions.  */
+{"wrmsr",   0, 0x0f30, X, NoSuf,		{ 0, 0, 0} },
+{"rdtsc",   0, 0x0f31, X, NoSuf,		{ 0, 0, 0} },
+{"rdmsr",   0, 0x0f32, X, NoSuf,		{ 0, 0, 0} },
+{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm,		{ LLongMem, 0, 0} },
+
+/* Pentium II/Pentium Pro extensions.  */
+{"sysenter",0, 0x0f34, X, NoSuf,		{ 0, 0, 0} },
+{"sysexit", 0, 0x0f35, X, NoSuf,		{ 0, 0, 0} },
+{"fxsave",  1, 0x0fae, 0, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fxrstor", 1, 0x0fae, 1, FP|Modrm,		{ LLongMem, 0, 0} },
+{"rdpmc",   0, 0x0f33, X, NoSuf,		{ 0, 0, 0} },
+/* official undefined instr. */
+{"ud2",	    0, 0x0f0b, X, NoSuf,		{ 0, 0, 0} },
+/* alias for ud2 */
+{"ud2a",    0, 0x0f0b, X, NoSuf,		{ 0, 0, 0} },
+/* 2nd. official undefined instr. */
+{"ud2b",    0, 0x0fb9, X, NoSuf,		{ 0, 0, 0} },
+
+{"cmovo",   2, 0x0f40, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovno",  2, 0x0f41, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovb",   2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovc",   2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovae",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnc",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnb",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmove",   2, 0x0f44, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovz",   2, 0x0f44, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovne",  2, 0x0f45, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnz",  2, 0x0f45, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovbe",  2, 0x0f46, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovna",  2, 0x0f46, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmova",   2, 0x0f47, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovs",   2, 0x0f48, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovns",  2, 0x0f49, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovp",   2, 0x0f4a, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnp",  2, 0x0f4b, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovl",   2, 0x0f4c, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovge",  2, 0x0f4d, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnl",  2, 0x0f4d, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovle",  2, 0x0f4e, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovng",  2, 0x0f4e, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovg",   2, 0x0f4f, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+
+{"fcmovb",  2, 0xdac0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnae",2, 0xdac0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmove",  2, 0xdac8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovbe", 2, 0xdad0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovna", 2, 0xdad0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovu",  2, 0xdad8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovae", 2, 0xdbc0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovne", 2, 0xdbc8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmova",  2, 0xdbd0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+
+{"fcomi",   2, 0xdbf0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcomi",   0, 0xdbf1, X, FP|ShortForm,		{ 0, 0, 0} },
+{"fcomi",   1, 0xdbf0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fucomi",  2, 0xdbe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucomi",  0, 0xdbe9, X, FP|ShortForm,		{ 0, 0, 0} },
+{"fucomi",  1, 0xdbe8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fcomip",  2, 0xdff0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcompi",  2, 0xdff0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcompi",  0, 0xdff1, X, FP|ShortForm,		{ 0, 0, 0} },
+{"fcompi",  1, 0xdff0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fucomip", 2, 0xdfe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucompi", 2, 0xdfe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucompi", 0, 0xdfe9, X, FP|ShortForm,		{ 0, 0, 0} },
+{"fucompi", 1, 0xdfe8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+
+/* MMX instructions.  */
+
+{"emms",     0, 0x0f77, X, FP,			{ 0, 0, 0 } },
+{"movd",     2, 0x0f6e, X, FP|Modrm,		{ Reg32|LongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, FP|Modrm,		{ RegMMX, Reg32|LongMem, 0 } },
+{"movq",     2, 0x0f6f, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"movq",     2, 0x0f7f, X, FP|Modrm,		{ RegMMX, RegMMX|LongMem, 0 } },
+{"packssdw", 2, 0x0f6b, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packsswb", 2, 0x0f63, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packuswb", 2, 0x0f67, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddb",    2, 0x0ffc, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddw",    2, 0x0ffd, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddd",    2, 0x0ffe, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsb",   2, 0x0fec, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsw",   2, 0x0fed, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusb",  2, 0x0fdc, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusw",  2, 0x0fdd, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pand",     2, 0x0fdb, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pandn",    2, 0x0fdf, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqb",  2, 0x0f74, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqw",  2, 0x0f75, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqd",  2, 0x0f76, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtb",  2, 0x0f64, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtw",  2, 0x0f65, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtd",  2, 0x0f66, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddwd",  2, 0x0ff5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhw",   2, 0x0fe5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmullw",   2, 0x0fd5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"por",	     2, 0x0feb, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x0ff1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x0f71, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"pslld",    2, 0x0ff2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pslld",    2, 0x0f72, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psllq",    2, 0x0ff3, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllq",    2, 0x0f73, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psraw",    2, 0x0fe1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psraw",    2, 0x0f71, 4, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrad",    2, 0x0fe2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrad",    2, 0x0f72, 4, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlw",    2, 0x0fd1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlw",    2, 0x0f71, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrld",    2, 0x0fd2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrld",    2, 0x0f72, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlq",    2, 0x0fd3, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlq",    2, 0x0f73, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psubb",    2, 0x0ff8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubw",    2, 0x0ff9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubd",    2, 0x0ffa, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsb",   2, 0x0fe8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsw",   2, 0x0fe9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusb",  2, 0x0fd8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusw",  2, 0x0fd9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhbw",2, 0x0f68, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhwd",2, 0x0f69, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhdq",2, 0x0f6a, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklbw",2, 0x0f60, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklwd",2, 0x0f61, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckldq",2, 0x0f62, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pxor",     2, 0x0fef, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+
+
+/* PIII Katmai New Instructions / SIMD instructions.  */
+
+{"addps",     2, 0x0f58,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addss",     2, 0xf30f58,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"andnps",    2, 0x0f55,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"andps",     2, 0x0f54,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqps",   2, 0x0fc2,    0, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqss",   2, 0xf30fc2,  0, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpleps",   2, 0x0fc2,    2, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpless",   2, 0xf30fc2,  2, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpltps",   2, 0x0fc2,    1, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltss",   2, 0xf30fc2,  1, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpneqps",  2, 0x0fc2,    4, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqss",  2, 0xf30fc2,  4, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnleps",  2, 0x0fc2,    6, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnless",  2, 0xf30fc2,  6, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnltps",  2, 0x0fc2,    5, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltss",  2, 0xf30fc2,  5, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpordps",  2, 0x0fc2,    7, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordss",  2, 0xf30fc2,  7, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpunordps",2, 0x0fc2,    3, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordss",2, 0xf30fc2,  3, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpps",     3, 0x0fc2,    X, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"cmpss",     3, 0xf30fc2,  X, FP|Modrm,	{ Imm8, RegXMM|WordMem, RegXMM } },
+{"comiss",    2, 0x0f2f,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cvtpi2ps",  2, 0x0f2a,    X, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
+{"cvtps2pi",  2, 0x0f2d,    X, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtsi2ss",  2, 0xf30f2a,  X, FP|Modrm,	{ Reg32|WordMem, RegXMM, 0 } },
+{"cvtss2si",  2, 0xf30f2d,  X, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
+{"cvttps2pi", 2, 0x0f2c,    X, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttss2si", 2, 0xf30f2c,  X, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
+{"divps",     2, 0x0f5e,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"divss",     2, 0xf30f5e,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ldmxcsr",   1, 0x0fae,    2, FP|Modrm, 	{ WordMem, 0, 0 } },
+{"maskmovq",  2, 0x0ff7,    X, FP|Modrm,	{ RegMMX|InvMem, RegMMX, 0 } },
+{"maxps",     2, 0x0f5f,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"maxss",     2, 0xf30f5f,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"minps",     2, 0x0f5d,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"minss",     2, 0xf30f5d,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f28,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f29,    X, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movhlps",   2, 0x0f12,    X, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f16,    X, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f17,    X, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movlhps",   2, 0x0f16,    X, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f12,    X, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f13,    X, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movmskps",  2, 0x0f50,    X, FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
+{"movntps",   2, 0x0f2b,    X, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
+{"movntq",    2, 0x0fe7,    X, FP|Modrm, 	{ RegMMX, LLongMem, 0 } },
+{"movss",     2, 0xf30f10,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movss",     2, 0xf30f11,  X, FP|Modrm,	{ RegXMM, RegXMM|WordMem, 0 } },
+{"movups",    2, 0x0f10,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movups",    2, 0x0f11,    X, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"mulps",     2, 0x0f59,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mulss",     2, 0xf30f59,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"orps",      2, 0x0f56,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgb",     2, 0x0fe0,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgw",     2, 0x0fe3,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pextrw",    3, 0x0fc5,    X, FP|Modrm,	{ Imm8, RegMMX, Reg32|InvMem } },
+{"pinsrw",    3, 0x0fc4,    X, FP|Modrm,	{ Imm8, Reg32|ShortMem, RegMMX } },
+{"pmaxsw",    2, 0x0fee,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxub",    2, 0x0fde,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminsw",    2, 0x0fea,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminub",    2, 0x0fda,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmovmskb",  2, 0x0fd7,    X, FP|Modrm,	{ RegMMX, Reg32|InvMem, 0 } },
+{"pmulhuw",   2, 0x0fe4,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"prefetchnta", 1, 0x0f18,  0, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht0",  1, 0x0f18,  1, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht1",  1, 0x0f18,  2, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht2",  1, 0x0f18,  3, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"psadbw",    2, 0x0ff6,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pshufw",    3, 0x0f70,    X, FP|Modrm,	{ Imm8, RegMMX|LLongMem, RegMMX } },
+{"rcpps",     2, 0x0f53,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rcpss",     2, 0xf30f53,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"rsqrtps",   2, 0x0f52,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rsqrtss",   2, 0xf30f52,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"sfence",    0, 0x0faef8,  X, FP,		{ 0, 0, 0 } },
+{"shufps",    3, 0x0fc6,    X, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtps",    2, 0x0f51,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtss",    2, 0xf30f51,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"stmxcsr",   1, 0x0fae,    3, FP|Modrm, 	{ WordMem, 0, 0 } },
+{"subps",     2, 0x0f5c,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"subss",     2, 0xf30f5c,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ucomiss",   2, 0x0f2e,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"unpckhps",  2, 0x0f15,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklps",  2, 0x0f14,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"xorps",     2, 0x0f57,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+
+/* AMD 3DNow! instructions.  */
+
+{"prefetch", 1, 0x0f0d,	   0, FP|Modrm,		{ ByteMem, 0, 0 } },
+{"prefetchw",1, 0x0f0d,	   1, FP|Modrm,		{ ByteMem, 0, 0 } },
+{"femms",    0, 0x0f0e,	   X, FP,		{ 0, 0, 0 } },
+{"pavgusb",  2, 0x0f0f, 0xbf, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2id",    2, 0x0f0f, 0x1d, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2iw",    2, 0x0f0f, 0x1c, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
+{"pfacc",    2, 0x0f0f, 0xae, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfadd",    2, 0x0f0f, 0x9e, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpeq",  2, 0x0f0f, 0xb0, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpge",  2, 0x0f0f, 0x90, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpgt",  2, 0x0f0f, 0xa0, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmax",    2, 0x0f0f, 0xa4, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmin",    2, 0x0f0f, 0x94, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmul",    2, 0x0f0f, 0xb4, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfnacc",   2, 0x0f0f, 0x8a, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
+{"pfpnacc",  2, 0x0f0f, 0x8e, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
+{"pfrcp",    2, 0x0f0f, 0x96, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqrt",  2, 0x0f0f, 0x97, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsub",    2, 0x0f0f, 0x9a, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsubr",   2, 0x0f0f, 0xaa, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fd",    2, 0x0f0f, 0x0d, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fw",    2, 0x0f0f, 0x0c, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
+{"pmulhrw",  2, 0x0f0f, 0xb7, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pswapd",   2, 0x0f0f, 0xbb, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
+
+/* sentinel */
+{NULL, 0, 0, 0, 0, { 0, 0, 0} }
+};
+#undef X
+#undef NoSuf
+#undef b_Suf
+#undef w_Suf
+#undef l_Suf
+#undef d_Suf
+#undef x_Suf
+#undef bw_Suf
+#undef bl_Suf
+#undef wl_Suf
+#undef wld_Suf
+#undef sl_Suf
+#undef sld_Suf
+#undef sldx_Suf
+#undef bwl_Suf
+#undef bwld_Suf
+#undef FP
+#undef l_FP
+#undef d_FP
+#undef x_FP
+#undef sl_FP
+#undef sld_FP
+#undef sldx_FP
+
+#define MAX_MNEM_SIZE 16	/* for parsing insn mnemonics from input */
+
+
+/* 386 register table.  */
 
 static const reg_entry i386_regtab[] = {
+  /* make %st first as we test for it */
+  {"st", FloatReg|FloatAcc, 0},
   /* 8 bit regs */
-  {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
+  {"al", Reg8|Acc, 0},
+  {"cl", Reg8|ShiftCount, 1},
+  {"dl", Reg8, 2},
   {"bl", Reg8, 3},
-  {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
+  {"ah", Reg8, 4},
+  {"ch", Reg8, 5},
+  {"dh", Reg8, 6},
+  {"bh", Reg8, 7},
   /* 16 bit regs */
-  {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
-  {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
+  {"ax", Reg16|Acc, 0},
+  {"cx", Reg16, 1},
+  {"dx", Reg16|InOutPortReg, 2},
+  {"bx", Reg16|BaseIndex, 3},
+  {"sp", Reg16, 4},
+  {"bp", Reg16|BaseIndex, 5},
+  {"si", Reg16|BaseIndex, 6},
+  {"di", Reg16|BaseIndex, 7},
   /* 32 bit regs */
-  {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
-  {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
+  {"eax", Reg32|BaseIndex|Acc, 0},
+  {"ecx", Reg32|BaseIndex, 1},
+  {"edx", Reg32|BaseIndex, 2},
+  {"ebx", Reg32|BaseIndex, 3},
+  {"esp", Reg32, 4},
+  {"ebp", Reg32|BaseIndex, 5},
+  {"esi", Reg32|BaseIndex, 6},
+  {"edi", Reg32|BaseIndex, 7},
   /* segment registers */
-  {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
-  {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
+  {"es", SReg2, 0},
+  {"cs", SReg2, 1},
+  {"ss", SReg2, 2},
+  {"ds", SReg2, 3},
+  {"fs", SReg3, 4},
+  {"gs", SReg3, 5},
   /* control registers */
-  {"cr0", Control, 0},   {"cr2", Control, 2},   {"cr3", Control, 3},
+  {"cr0", Control, 0},
+  {"cr1", Control, 1},
+  {"cr2", Control, 2},
+  {"cr3", Control, 3},
   {"cr4", Control, 4},
+  {"cr5", Control, 5},
+  {"cr6", Control, 6},
+  {"cr7", Control, 7},
   /* debug registers */
-  {"db0", Debug, 0},   {"db1", Debug, 1},   {"db2", Debug, 2},
-  {"db3", Debug, 3},   {"db6", Debug, 6},   {"db7", Debug, 7},
-  {"dr0", Debug, 0},   {"dr1", Debug, 1},   {"dr2", Debug, 2},
-  {"dr3", Debug, 3},   {"dr6", Debug, 6},   {"dr7", Debug, 7},
+  {"db0", Debug, 0},
+  {"db1", Debug, 1},
+  {"db2", Debug, 2},
+  {"db3", Debug, 3},
+  {"db4", Debug, 4},
+  {"db5", Debug, 5},
+  {"db6", Debug, 6},
+  {"db7", Debug, 7},
+  {"dr0", Debug, 0},
+  {"dr1", Debug, 1},
+  {"dr2", Debug, 2},
+  {"dr3", Debug, 3},
+  {"dr4", Debug, 4},
+  {"dr5", Debug, 5},
+  {"dr6", Debug, 6},
+  {"dr7", Debug, 7},
   /* test registers */
-  {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5},
-  {"tr6", Test, 6}, {"tr7", Test, 7},
-  /* float registers */
+  {"tr0", Test, 0},
+  {"tr1", Test, 1},
+  {"tr2", Test, 2},
+  {"tr3", Test, 3},
+  {"tr4", Test, 4},
+  {"tr5", Test, 5},
+  {"tr6", Test, 6},
+  {"tr7", Test, 7},
+  /* mmx and simd registers */
+  {"mm0", RegMMX, 0},
+  {"mm1", RegMMX, 1},
+  {"mm2", RegMMX, 2},
+  {"mm3", RegMMX, 3},
+  {"mm4", RegMMX, 4},
+  {"mm5", RegMMX, 5},
+  {"mm6", RegMMX, 6},
+  {"mm7", RegMMX, 7},
+  {"xmm0", RegXMM, 0},
+  {"xmm1", RegXMM, 1},
+  {"xmm2", RegXMM, 2},
+  {"xmm3", RegXMM, 3},
+  {"xmm4", RegXMM, 4},
+  {"xmm5", RegXMM, 5},
+  {"xmm6", RegXMM, 6},
+  {"xmm7", RegXMM, 7}
+};
+
+static const reg_entry i386_float_regtab[] = {
   {"st(0)", FloatReg|FloatAcc, 0},
-  {"st", FloatReg|FloatAcc, 0},
-  {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 
-  {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 
-  {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
+  {"st(1)", FloatReg, 1},
+  {"st(2)", FloatReg, 2},
+  {"st(3)", FloatReg, 3},
+  {"st(4)", FloatReg, 4},
+  {"st(5)", FloatReg, 5},
+  {"st(6)", FloatReg, 6},
+  {"st(7)", FloatReg, 7}
 };
 
 #define MAX_REG_NAME_SIZE 8	/* for parsing register names from input */
 
-static const reg_entry *const i386_regtab_end
-  = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
-
 /* segment stuff */
 static const seg_entry cs = { "cs", 0x2e };
 static const seg_entry ds = { "ds", 0x3e };
@@ -849,54 +1207,5 @@ static const seg_entry ss = { "ss", 0x36 };
 static const seg_entry es = { "es", 0x26 };
 static const seg_entry fs = { "fs", 0x64 };
 static const seg_entry gs = { "gs", 0x65 };
-static const seg_entry null = { "", 0x0 };
-
-/*
-  This table is used to store the default segment register implied by all
-  possible memory addressing modes.
-  It is indexed by the mode & modrm entries of the modrm byte as follows:
-      index = (mode<<3) | modrm;
-*/
-static const seg_entry *const one_byte_segment_defaults[] = {
-  /* mode 0 */
-  &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
-  /* mode 1 */
-  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
-  /* mode 2 */
-  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
-  /* mode 3 --- not a memory reference; never referenced */
-};
-
-static const seg_entry *const two_byte_segment_defaults[] = {
-  /* mode 0 */
-  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
-  /* mode 1 */
-  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
-  /* mode 2 */
-  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
-  /* mode 3 --- not a memory reference; never referenced */
-};
-
-static const prefix_entry i386_prefixtab[] = {
-#define ADDR_PREFIX_OPCODE 0x67
-  { "addr16", 0x67 },		/* address size prefix ==> 16bit addressing
-				 * (How is this useful?) */
-#define WORD_PREFIX_OPCODE 0x66
-  { "data16", 0x66 },		/* operand size prefix */
-  { "lock", 0xf0 },		/* bus lock prefix */
-  { "wait", 0x9b },		/* wait for coprocessor */
-  { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
-  { "es", 0x26 }, { "fs", 0x64 },
-  { "gs", 0x65 }, { "ss", 0x36 },
-/* REPE & REPNE used to detect rep/repne with a non-string instruction */
-#define REPNE 0xf2
-#define REPE  0xf3
-  { "rep", 0xf3 }, 		/* repeat string instructions */
-  { "repe", 0xf3 },  { "repz", 0xf3 },
-  { "repne", 0xf2 }, { "repnz", 0xf2 }
-};
-
-static const prefix_entry *const i386_prefixtab_end
-  = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
 
-/* end of i386-opcode.h */
+/* end of opcode/i386.h */
diff --git a/gnu/usr.bin/binutils/include/opcode/m68k.h b/gnu/usr.bin/binutils/include/opcode/m68k.h
index d81967d16e2..3208b77f4f0 100644
--- a/gnu/usr.bin/binutils/include/opcode/m68k.h
+++ b/gnu/usr.bin/binutils/include/opcode/m68k.h
@@ -1,5 +1,5 @@
 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
-   Copyright 1989, 1991, 1992, 1993, 1994, 1995 Free Software Foundation.
+   Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1999 Free Software Foundation.
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -36,6 +36,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #define	m68851  0x080
 #define cpu32	0x100	/* e.g., 68332 */
 #define mcf5200 0x200
+#define mcf5206e 0x400
+#define mcf5307 0x800
 
  /* handy aliases */
 #define	m68040up  (m68040 | m68060)
@@ -43,6 +45,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #define	m68020up  (m68020 | m68030up)
 #define	m68010up  (m68010 | cpu32 | m68020up)
 #define	m68000up  (m68000 | m68010up)
+#define mcf       (mcf5200 | mcf5206e | mcf5307)
 
 #define	mfloat  (m68881 | m68882 | m68040 | m68060)
 #define	mmmu    (m68851 | m68030 | m68040 | m68060)
@@ -87,7 +90,7 @@ struct m68k_opcode_alias
    operand; the second, the place it is stored.  */
 
 /* Kinds of operands:
-   Characters used: AaBCcDdFfIJkLlMOQRrSsTtUVWXYZ0123|*~%;@!&$?/#^+-
+   Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+-
 
    D  data register only.  Stored as 3 bits.
    A  address register only.  Stored as 3 bits.
@@ -121,6 +124,9 @@ struct m68k_opcode_alias
    C  the CCR.  No need to store it; this is just for filtering validity.
    S  the SR.  No need to store, just as with CCR.
    U  the USP.  No need to store, just as with CCR.
+   E  the ACC.  No need to store, just as with CCR.
+   G  the MACSR.  No need to store, just as with CCR.
+   H  the MASK.  No need to store, just as with CCR.
 
    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
       extracted from the 'd' field of word one, which means that an extended
@@ -170,30 +176,46 @@ struct m68k_opcode_alias
        for both caches.  Used in cinv and cpush.  Always
        stored in position "d".
 
+    u  Any register, with ``upper'' or ``lower'' specification.  Used
+       in the mac instructions with size word.
+
  The remainder are all stored as 6 bits using an address mode and a
  register number; they differ in which addressing modes they match.
 
-   *  all					(modes 0-6,7.*)
+   *  all					(modes 0-6,7.0-4)
    ~  alterable memory				(modes 2-6,7.0,7.1)
-   						(not 0,1,7.~)
-   %  alterable					(modes 0-6,7.0,7.1)(not 7.~)
-   ;  data					(modes 0,2-6,7.*)(not 1)
-   @  data, but not immediate			(modes 0,2-6,7.? ? ?)
-						(not 1,7.?)
-						This may really be ;,
-						the 68020 book says it is
-   !  control					(modes 2,5,6,7.*-)
+   						(not 0,1,7.2-4)
+   %  alterable					(modes 0-6,7.0,7.1)
+						(not 7.2-4)
+   ;  data					(modes 0,2-6,7.0-4)
+						(not 1)
+   @  data, but not immediate			(modes 0,2-6,7.0-3)
+						(not 1,7.4)
+   !  control					(modes 2,5,6,7.0-3)
 						(not 0,1,3,4,7.4)
    &  alterable control				(modes 2,5,6,7.0,7.1)
-						(not 0,1,7.? ? ?)
+						(not 0,1,7.2-4)
    $  alterable data				(modes 0,2-6,7.0,7.1)
-						(not 1,7.~)
+						(not 1,7.2-4)
    ?  alterable control, or data register	(modes 0,2,5,6,7.0,7.1)
-						(not 1,3,4,7.~)
-   /  control, or data register			(modes 0,2,5,6,7.0,7.1,7.2,7.3)
+						(not 1,3,4,7.2-4)
+   /  control, or data register			(modes 0,2,5,6,7.0-3)
 						(not 1,3,4,7.4)
-   `  control, plus pre-dec, not simple indir.	(modes 4,5,6,7.*-)
-						(not 0,1,2,3,7.4) */
+   >  *save operands				(modes 2,4,5,6,7.0,7.1)
+						(not 0,1,3,7.2-4)
+   <  *restore operands				(modes 2,3,5,6,7.0-3)
+						(not 0,1,4,7.4)
+
+   coldfire move operands:
+   m  						(modes 0-4)
+   n						(modes 5,7.2)
+   o						(modes 6,7.0,7.1,7.3,7.4)
+   p						(modes 0-5)
+
+   coldfire bset/bclr/btst/mulsl/mulul operands:
+   q						(modes 0,2-5)
+   v						(modes 0,2-5,7.0,7.1)
+*/
 
 /* For the 68851: */
 /*
@@ -247,6 +269,8 @@ struct m68k_opcode_alias
 */
 
 /* Places to put an operand, for non-general operands:
+   Characters used: BbCcDdghijkLlMmNnostWw123456789
+
    s  source, low bits of first word.
    d  dest, shifted 9 in first word
    1  second word, shifted 12
@@ -280,6 +304,24 @@ struct m68k_opcode_alias
    C  floating point coprocessor constant - 7 bits.  Also used for static
       K-factors...
    j  Movec register #, stored in 12 low bits of second word.
+   m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
+      and remaining 3 bits of register shifted 9 bits in first word.
+      Indicate upper/lower in 1 bit shifted 7 bits in second word.
+      Use with `R' or `u' format.
+   n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
+      with MSB shifted 6 bits in first word and remaining 3 bits of
+      register shifted 9 bits in first word.  No upper/lower
+      indication is done.)  Use with `R' or `u' format.
+   o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
+      Indicate upper/lower in 1 bit shifted 7 bits in second word.
+      Use with `R' or `u' format.
+   M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
+      upper/lower in 1 bit shifted 6 bits in second word.  Use with
+      `R' or `u' format.
+   N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
+      upper/lower in 1 bit shifted 6 bits in second word.  Use with
+      `R' or `u' format.
+   h  shift indicator (scale factor), 1 bit shifted 10 in second word
 
  Places to put operand, for general operands:
    d  destination, shifted 6 bits in first word
diff --git a/gnu/usr.bin/binutils/include/opcode/mips.h b/gnu/usr.bin/binutils/include/opcode/mips.h
index 9de3c32b99c..68fe57a8aae 100644
--- a/gnu/usr.bin/binutils/include/opcode/mips.h
+++ b/gnu/usr.bin/binutils/include/opcode/mips.h
@@ -1,5 +1,5 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
-   Copyright 1993, 1995 Free Software Foundation, Inc.
+   Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
 
@@ -19,6 +19,9 @@ You should have received a copy of the GNU General Public License
 along with this file; see the file COPYING.  If not, write to the Free
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
+#ifndef _MIPS_H_
+#define _MIPS_H_
+
 /* These are bit masks and shift counts to use to access the various
    fields of an instruction.  To retrieve the X field of an
    instruction, use the expression
@@ -44,7 +47,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
    breakpoint instruction are not defined; Kane says the breakpoint
    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
-   only use ten bits).
+   only use ten bits).  An optional two-operand form of break/sdbbp
+   allows the lower ten bits to be set too.
 
    The syscall instruction uses SYSCALL.
 
@@ -62,6 +66,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_SH_BCC		18
 #define OP_MASK_CODE		0x3ff
 #define OP_SH_CODE		16
+#define OP_MASK_CODE2		0x3ff
+#define OP_SH_CODE2		6
 #define OP_MASK_RT		0x1f
 #define OP_SH_RT		16
 #define OP_MASK_FT		0x1f
@@ -114,6 +120,12 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_MASK_UNSIGNED        0x1
 #define OP_SH_HINT              16
 #define OP_MASK_HINT            0x1f
+#define OP_SH_MMI               0       /* Multimedia (parallel) op */
+#define OP_MASK_MMI             0x3f 
+#define OP_SH_MMISUB            6
+#define OP_MASK_MMISUB          0x1f
+#define OP_MASK_PERFREG		0x1f	/* Performance monitoring */
+#define OP_SH_PERFREG		1
 
 /* This structure holds information for a particular instruction.  */
 
@@ -125,9 +137,7 @@ struct mips_opcode
   const char *args;
   /* The basic opcode for the instruction.  When assembling, this
      opcode is modified by the arguments to produce the actual opcode
-     that is used.  If pinfo is INSN_MACRO, then this is instead the
-     ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
-     etc.).  */
+     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
   unsigned long match;
   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
      relevant portions of the opcode when disassembling.  If the
@@ -139,6 +149,9 @@ struct mips_opcode
      of bits describing the instruction, notably any relevant hazard
      information.  */
   unsigned long pinfo;
+  /* A collection of bits describing the instruction sets of which this
+     instruction or macro is a member. */
+  unsigned long membership;
 };
 
 /* These are the characters which may appears in the args field of an
@@ -161,6 +174,7 @@ struct mips_opcode
    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
    "o" 16 bit signed offset (OP_*_DELTA)
    "p" 16 bit PC relative branch target address (OP_*_DELTA)
+   "q" 10 bit extra breakpoint code (OP_*_CODE2)
    "r" 5 bit same register used as both source and target (OP_*_RS)
    "s" 5 bit source register specifier (OP_*_RS)
    "t" 5 bit target register (OP_*_RT)
@@ -185,6 +199,7 @@ struct mips_opcode
    Coprocessor instructions:
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
+   "P" 5 bit performance-monitor register (OP_*_PERFREG)
 
    Macro instructions:
    "A" General 32 bit expression
@@ -193,6 +208,15 @@ struct mips_opcode
    "L" 64 bit floating point constant in .lit8
    "f" 32 bit floating point constant
    "l" 32 bit floating point constant in .lit4
+
+   Other:
+   "()" parens surrounding optional value
+   ","  separates operands
+
+   Characters used so far, for quick reference when adding more:
+   "<>(),"
+   "ABCDEFGILMNSTRVW"
+   "abcdfhijklopqrstuvwxz"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -254,24 +278,73 @@ struct mips_opcode
 #define INSN_TRAP                   0x04000000
 /* Instruction stores value into memory.  */
 #define INSN_STORE_MEMORY	    0x08000000
+/* Instruction uses single precision floating point.  */
+#define FP_S			    0x10000000
+/* Instruction uses double precision floating point.  */
+#define FP_D			    0x20000000
+/* Instruction is part of the tx39's integer multiply family.    */
+#define INSN_MULT                   0x40000000
+/* Instruction synchronize shared memory.  */
+#define INSN_SYNC		    0x80000000
+
+/* Instruction is actually a macro.  It should be ignored by the
+   disassembler, and requires special treatment by the assembler.  */
+#define INSN_MACRO                  0xffffffff
+
+
+
+
+
 /* MIPS ISA field--CPU level at which insn is supported.  */
-#define INSN_ISA		    0x70000000
+#define INSN_ISA		    0x0000000F
+/* An instruction which is not part of any basic MIPS ISA.
+   (ie it is a chip specific instruction)  */
+#define INSN_NO_ISA		    0x00000000
+/* MIPS ISA 1 instruction.  */
+#define INSN_ISA1		    0x00000001
 /* MIPS ISA 2 instruction (R6000 or R4000).  */
-#define INSN_ISA2		    0x10000000
+#define INSN_ISA2		    0x00000002
 /* MIPS ISA 3 instruction (R4000).  */
-#define INSN_ISA3		    0x20000000
-/* MIPS R4650 instruction.  */
-#define INSN_4650		    0x30000000
+#define INSN_ISA3		    0x00000003
 /* MIPS ISA 4 instruction (R8000).  */
-#define INSN_ISA4		    0x40000000
+#define INSN_ISA4		    0x00000004
+#define INSN_ISA5		    0x00000005
+
+/* Chip specific instructions.  These are bitmasks.  */
+/* MIPS R4650 instruction.  */
+#define INSN_4650		    0x00000010
 /* LSI R4010 instruction.  */
-#define INSN_4010		    0x50000000
+#define INSN_4010		    0x00000020
 /* NEC VR4100 instruction. */
-#define INSN_4100                   0x60000000
+#define INSN_4100                   0x00000040
+/* Toshiba R3900 instruction.  */
+#define INSN_3900                   0x00000080
 
-/* Instruction is actually a macro.  It should be ignored by the
-   disassembler, and requires special treatment by the assembler.  */
-#define INSN_MACRO                  0xffffffff
+/* 32-bit code running on a ISA3+ CPU. */
+#define INSN_GP32                   0x00001000
+
+/* Test for membership in an ISA including chip specific ISAs.
+   INSN is pointer to an element of the opcode table; ISA is the
+   specified ISA to test against; and CPU is the CPU specific ISA
+   to test, or zero if no CPU specific ISA test is desired.  
+   The gp32 arg is set when you need to force 32-bit register usage on
+   a machine with 64-bit registers; see the documentation under -mgp32
+   in the MIPS gas docs. */
+
+#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) 	       		\
+    ((((insn)->membership & INSN_ISA) != 0			\
+      && ((insn)->membership & INSN_ISA) <= isa			\
+      && ((insn)->membership & INSN_GP32 ? gp32 : 1))		\
+     || (cpu == 4650						\
+	 && ((insn)->membership & INSN_4650) != 0)		\
+     || (cpu == 4010						\
+	 && ((insn)->membership & INSN_4010) != 0)		\
+     || ((cpu == 4100						\
+	  || cpu == 4111					\
+	  )							\
+	 && ((insn)->membership & INSN_4100) != 0)		\
+     || (cpu == 3900						\
+	 && ((insn)->membership & INSN_3900) != 0))
 
 /* This is a list of macro expanded instructions.
  *
@@ -286,6 +359,7 @@ enum {
     M_ADD_I,
     M_ADDU_I,
     M_AND_I,
+    M_BEQ,
     M_BEQ_I,
     M_BEQL_I,
     M_BGE,
@@ -320,6 +394,7 @@ enum {
     M_BLTUL,
     M_BLTU_I,
     M_BLTUL_I,
+    M_BNE,
     M_BNE_I,
     M_BNEL_I,
     M_DABS,
@@ -347,6 +422,7 @@ enum {
     M_DREMU_3I,
     M_DSUB_I,
     M_DSUBU_I,
+    M_DSUBU_I_2,
     M_J_A,
     M_JAL_1,
     M_JAL_2,
@@ -461,6 +537,7 @@ enum {
     M_SWR_AB,
     M_SUB_I,
     M_SUBU_I,
+    M_SUBU_I_2,
     M_TEQ_I,
     M_TGE_I,
     M_TGEU_I,
@@ -483,9 +560,15 @@ enum {
     M_USW_A,
     M_USD,
     M_USD_A,
-    M_XOR_I
+    M_XOR_I,
+    M_COP0,
+    M_COP1,
+    M_COP2,
+    M_COP3,
+    M_NUM_MACROS
 };
 
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -496,6 +579,171 @@ enum {
    Many instructions are short hand for other instructions (i.e., The
    jal <register> instruction is short for jalr <register>).  */
 
-extern const struct mips_opcode mips_opcodes[];
-extern const int bfd_mips_num_opcodes;
+extern const struct mips_opcode mips_builtin_opcodes[];
+extern const int bfd_mips_num_builtin_opcodes;
+extern struct mips_opcode *mips_opcodes;
+extern int bfd_mips_num_opcodes;
 #define NUMOPCODES bfd_mips_num_opcodes
+
+
+/* The rest of this file adds definitions for the mips16 TinyRISC
+   processor.  */
+
+/* These are the bitmasks and shift counts used for the different
+   fields in the instruction formats.  Other than OP, no masks are
+   provided for the fixed portions of an instruction, since they are
+   not needed.
+
+   The I format uses IMM11.
+
+   The RI format uses RX and IMM8.
+
+   The RR format uses RX, and RY.
+
+   The RRI format uses RX, RY, and IMM5.
+
+   The RRR format uses RX, RY, and RZ.
+
+   The RRI_A format uses RX, RY, and IMM4.
+
+   The SHIFT format uses RX, RY, and SHAMT.
+
+   The I8 format uses IMM8.
+
+   The I8_MOVR32 format uses RY and REGR32.
+
+   The IR_MOV32R format uses REG32R and MOV32Z.
+
+   The I64 format uses IMM8.
+
+   The RI64 format uses RY and IMM5.
+   */
+
+#define MIPS16OP_MASK_OP	0x1f
+#define MIPS16OP_SH_OP		11
+#define MIPS16OP_MASK_IMM11	0x7ff
+#define MIPS16OP_SH_IMM11	0
+#define MIPS16OP_MASK_RX	0x7
+#define MIPS16OP_SH_RX		8
+#define MIPS16OP_MASK_IMM8	0xff
+#define MIPS16OP_SH_IMM8	0
+#define MIPS16OP_MASK_RY	0x7
+#define MIPS16OP_SH_RY		5
+#define MIPS16OP_MASK_IMM5	0x1f
+#define MIPS16OP_SH_IMM5	0
+#define MIPS16OP_MASK_RZ	0x7
+#define MIPS16OP_SH_RZ		2
+#define MIPS16OP_MASK_IMM4	0xf
+#define MIPS16OP_SH_IMM4	0
+#define MIPS16OP_MASK_REGR32	0x1f
+#define MIPS16OP_SH_REGR32	0
+#define MIPS16OP_MASK_REG32R	0x1f
+#define MIPS16OP_SH_REG32R	3
+#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
+#define MIPS16OP_MASK_MOVE32Z	0x7
+#define MIPS16OP_SH_MOVE32Z	0
+#define MIPS16OP_MASK_IMM6	0x3f
+#define MIPS16OP_SH_IMM6	5
+
+/* These are the characters which may appears in the args field of an
+   instruction.  They appear in the order in which the fields appear
+   when the instruction is used.  Commas and parentheses in the args
+   string are ignored when assembling, and written into the output
+   when disassembling.
+
+   "y" 3 bit register (MIPS16OP_*_RY)
+   "x" 3 bit register (MIPS16OP_*_RX)
+   "z" 3 bit register (MIPS16OP_*_RZ)
+   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
+   "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
+   "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
+   "0" zero register ($0)
+   "S" stack pointer ($sp or $29)
+   "P" program counter
+   "R" return address register ($ra or $31)
+   "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
+   "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+   "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
+   "a" 26 bit jump address
+   "e" 11 bit extension value
+   "l" register list for entry instruction
+   "L" register list for exit instruction
+
+   The remaining codes may be extended.  Except as otherwise noted,
+   the full extended operand is a 16 bit signed value.
+   "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
+   ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
+   "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
+   "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
+   "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
+   "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
+   "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
+   "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
+   "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
+   "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
+   "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
+   "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
+   "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
+   "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
+   "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
+   "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
+   "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
+   "q" 11 bit branch address (MIPS16OP_*_IMM11)
+   "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
+   "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
+   "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
+   */
+
+/* For the mips16, we use the same opcode table format and a few of
+   the same flags.  However, most of the flags are different.  */
+
+/* Modifies the register in MIPS16OP_*_RX.  */
+#define MIPS16_INSN_WRITE_X		    0x00000001
+/* Modifies the register in MIPS16OP_*_RY.  */
+#define MIPS16_INSN_WRITE_Y		    0x00000002
+/* Modifies the register in MIPS16OP_*_RZ.  */
+#define MIPS16_INSN_WRITE_Z		    0x00000004
+/* Modifies the T ($24) register.  */
+#define MIPS16_INSN_WRITE_T		    0x00000008
+/* Modifies the SP ($29) register.  */
+#define MIPS16_INSN_WRITE_SP		    0x00000010
+/* Modifies the RA ($31) register.  */
+#define MIPS16_INSN_WRITE_31		    0x00000020
+/* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
+#define MIPS16_INSN_WRITE_GPR_Y		    0x00000040
+/* Reads the register in MIPS16OP_*_RX.  */
+#define MIPS16_INSN_READ_X		    0x00000080
+/* Reads the register in MIPS16OP_*_RY.  */
+#define MIPS16_INSN_READ_Y		    0x00000100
+/* Reads the register in MIPS16OP_*_MOVE32Z.  */
+#define MIPS16_INSN_READ_Z		    0x00000200
+/* Reads the T ($24) register.  */
+#define MIPS16_INSN_READ_T		    0x00000400
+/* Reads the SP ($29) register.  */
+#define MIPS16_INSN_READ_SP		    0x00000800
+/* Reads the RA ($31) register.  */
+#define MIPS16_INSN_READ_31		    0x00001000
+/* Reads the program counter.  */
+#define MIPS16_INSN_READ_PC		    0x00002000
+/* Reads the general purpose register in MIPS16OP_*_REGR32.  */
+#define MIPS16_INSN_READ_GPR_X		    0x00004000
+/* Is a branch insn. */
+#define MIPS16_INSN_BRANCH                  0x00010000
+
+/* The following flags have the same value for the mips16 opcode
+   table:
+   INSN_UNCOND_BRANCH_DELAY
+   INSN_COND_BRANCH_DELAY
+   INSN_COND_BRANCH_LIKELY (never used)
+   INSN_READ_HI
+   INSN_READ_LO
+   INSN_WRITE_HI
+   INSN_WRITE_LO
+   INSN_TRAP
+   INSN_ISA3
+   */
+
+extern const struct mips_opcode mips16_opcodes[];
+extern const int bfd_mips16_num_opcodes;
+
+#endif /* _MIPS_H_ */
diff --git a/gnu/usr.bin/binutils/include/opcode/mn10300.h b/gnu/usr.bin/binutils/include/opcode/mn10300.h
index e2e69843e87..12f03670f6d 100644
--- a/gnu/usr.bin/binutils/include/opcode/mn10300.h
+++ b/gnu/usr.bin/binutils/include/opcode/mn10300.h
@@ -1,5 +1,5 @@
 /* mn10300.h -- Header file for Matsushita 10300 opcode table
-   Copyright 1996 Free Software Foundation, Inc.
+   Copyright 1996, 1997 Free Software Foundation, Inc.
    Written by Jeff Law, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -23,6 +23,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 /* The opcode table is an array of struct mn10300_opcode.  */
 
+#define MN10300_MAX_OPERANDS 8
 struct mn10300_opcode
 {
   /* The opcode name.  */
@@ -38,13 +39,25 @@ struct mn10300_opcode
      match (and are presumably filled in by operands).  */
   unsigned long mask;
 
+  /* A bitmask.  For each operand, nonzero if it must not have the same
+     register specification as all other operands with a nonzero bit in
+     this flag.  ie 0x81 would indicate that operands 7 and 0 must not
+     match.  Note that we count operands from left to right as they appear
+     in the operands specification below.  */
+  unsigned int no_match_operands;
+
   /* The format of this opcode.  */
   unsigned char format;
 
+  /* Bitmask indicating what cpu variants this opcode is available on.
+     We assume mn10300 base opcodes are available everywhere, so we only
+     have to note opcodes which are available on other variants.  */
+  unsigned int machine;
+
   /* An array of operand codes.  Each code is an index into the
      operand table.  They appear in the order which the operands must
      appear in assembly code, and are terminated by a zero.  */
-  unsigned char operands[8];
+  unsigned char operands[MN10300_MAX_OPERANDS];
 };
 
 /* The table itself is sorted by major opcode number, and is otherwise
@@ -54,7 +67,7 @@ extern const struct mn10300_opcode mn10300_opcodes[];
 extern const int mn10300_num_opcodes;
 
 
-/* The operands table is an array of struct powerpc_operand.  */
+/* The operands table is an array of struct mn10300_operand.  */
 
 struct mn10300_operand
 {
@@ -96,6 +109,32 @@ extern const struct mn10300_operand mn10300_operands[];
 
 #define MN10300_OPERAND_SPLIT 0x400
 
+#define MN10300_OPERAND_REG_LIST 0x800
+
+#define MN10300_OPERAND_PCREL 0x1000
+
+#define MN10300_OPERAND_MEMADDR 0x2000
+
+#define MN10300_OPERAND_RELAX 0x4000
+
+#define MN10300_OPERAND_USP 0x8000
+
+#define MN10300_OPERAND_SSP 0x10000
+
+#define MN10300_OPERAND_MSP 0x20000
+
+#define MN10300_OPERAND_PC 0x40000
+
+#define MN10300_OPERAND_EPSW 0x80000
+
+#define MN10300_OPERAND_RREG 0x100000
+
+#define MN10300_OPERAND_XRREG 0x200000
+
+#define MN10300_OPERAND_PLUS 0x400000
+
+#define MN10300_OPERAND_24BIT 0x800000
+
 /* Opcode Formats.  */
 #define FMT_S0 1
 #define FMT_S1 2
@@ -107,5 +146,16 @@ extern const struct mn10300_operand mn10300_operands[];
 #define FMT_D2 8
 #define FMT_D4 9
 #define FMT_D5 10
+#define FMT_D6 11
+#define FMT_D7 12
+#define FMT_D8 13
+#define FMT_D9 14
+#define FMT_D10 15
+
+/* Variants of the mn10300 which have additional opcodes.  */
+#define MN103 300
+#define AM30  300
+
+#define AM33 330
 
 #endif /* MN10300_H */
diff --git a/gnu/usr.bin/binutils/include/opcode/ppc.h b/gnu/usr.bin/binutils/include/opcode/ppc.h
index a9e3b24ab30..974f0dfa569 100644
--- a/gnu/usr.bin/binutils/include/opcode/ppc.h
+++ b/gnu/usr.bin/binutils/include/opcode/ppc.h
@@ -85,6 +85,9 @@ extern const int powerpc_num_opcodes;
    for the assembler's -many option, and it eliminates duplicates).  */
 #define PPC_OPCODE_ANY (0200)
 
+/* Opcode is supported as part of the 64-bit bridge.  */
+#define PPC_OPCODE_64_BRIDGE (0400)
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 
diff --git a/gnu/usr.bin/binutils/include/opcode/sparc.h b/gnu/usr.bin/binutils/include/opcode/sparc.h
index 431c55666db..7728253f1ef 100644
--- a/gnu/usr.bin/binutils/include/opcode/sparc.h
+++ b/gnu/usr.bin/binutils/include/opcode/sparc.h
@@ -179,6 +179,8 @@ Kinds of operands:
 	*	Prefetch function constant. (v9)
 	x	OPF field (v9 impdep).
 	0	32/64 bit immediate for set or setx (v9) insns
+	_	Ancillary state register in rd (v9a)
+	/	Ancillary state register in rs1 (v9a)
 
 The following chars are unused: (note: ,[] are used as punctuation)
 [345]
@@ -212,7 +214,7 @@ The following chars are unused: (note: ,[] are used as punctuation)
 #define	RS1_G0	RS1(~0)
 #define	RS2_G0	RS2(~0)
 
-extern struct sparc_opcode sparc_opcodes[];
+extern const struct sparc_opcode sparc_opcodes[];
 extern const int sparc_num_opcodes;
 
 int sparc_encode_asi ();