Import binutils-2.11.2

- only the binutils package (no gdb here)
- don't import libiberty and texinfo, they are elsewhere
- remove all .info* generated files

57 files changed, 3662 insertions, 262 deletions

diff --git a/gnu/usr.bin/binutils/include/MAINTAINERS b/gnu/usr.bin/binutils/include/MAINTAINERS
new file mode 100644
index 00000000000..d59a3bd7f88
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/MAINTAINERS
@@ -0,0 +1 @@
+See ../binutils/MAINTAINERS
diff --git a/gnu/usr.bin/binutils/include/alloca-conf.h b/gnu/usr.bin/binutils/include/alloca-conf.h
new file mode 100644
index 00000000000..9c3eea396c1
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/alloca-conf.h
@@ -0,0 +1,24 @@
+#include "config.h"
+
+#if defined(__GNUC__) && !defined(C_ALLOCA)
+# ifndef alloca
+#  define alloca __builtin_alloca
+# endif
+#else /* ! defined (__GNUC__) */
+#  ifdef _AIX
+ #pragma alloca
+#  else
+#  if defined(HAVE_ALLOCA_H) && !defined(C_ALLOCA)
+#   include <alloca.h>
+#  else /* ! defined (HAVE_ALLOCA_H) */
+#   ifdef __STDC__
+extern PTR alloca (size_t);
+#   else /* ! defined (__STDC__) */
+extern PTR alloca ();
+#   endif /* ! defined (__STDC__) */
+#  endif /* ! defined (HAVE_ALLOCA_H) */
+#  ifdef _WIN32
+#   include <malloc.h>
+#  endif
+# endif /* ! defined (_AIX) */
+#endif /* ! defined (__GNUC__) */
diff --git a/gnu/usr.bin/binutils/include/bin-bugs.h b/gnu/usr.bin/binutils/include/bin-bugs.h
index cb14a66bf66..3c97715add4 100644
--- a/gnu/usr.bin/binutils/include/bin-bugs.h
+++ b/gnu/usr.bin/binutils/include/bin-bugs.h
@@ -1,3 +1,3 @@
 #ifndef REPORT_BUGS_TO
-#define REPORT_BUGS_TO	"bug-gnu-utils@gnu.org"
+#define REPORT_BUGS_TO	"bug-binutils@gnu.org"
 #endif
diff --git a/gnu/usr.bin/binutils/include/coff/go32exe.h b/gnu/usr.bin/binutils/include/coff/go32exe.h
index 5bd26c13401..97f5341b185 100644
--- a/gnu/usr.bin/binutils/include/coff/go32exe.h
+++ b/gnu/usr.bin/binutils/include/coff/go32exe.h
@@ -1,4 +1,20 @@
-/* COFF information for PC running go32.  */
+/* COFF information for PC running go32.
+
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #define STUBSIZE 2048
 
diff --git a/gnu/usr.bin/binutils/include/coff/ia64.h b/gnu/usr.bin/binutils/include/coff/ia64.h
new file mode 100644
index 00000000000..496a8779b4f
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/coff/ia64.h
@@ -0,0 +1,238 @@
+/* coff information for HP/Intel IA-64.
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr {
+	char f_magic[2];	/* magic number			*/
+	char f_nscns[2];	/* number of sections		*/
+	char f_timdat[4];	/* time & date stamp		*/
+	char f_symptr[4];	/* file pointer to symtab	*/
+	char f_nsyms[4];	/* number of symtab entries	*/
+	char f_opthdr[2];	/* sizeof(optional hdr)		*/
+	char f_flags[2];	/* flags			*/
+};
+
+#define IA64MAGIC	0x200
+
+#define IA64BADMAG(x)	(((x).f_magic != IA64MAGIC))
+
+/* Bits for f_flags:
+ *	F_RELFLG	relocation info stripped from file
+ *	F_EXEC		file is executable (no unresolved external references)
+ *	F_LNNO		line numbers stripped from file
+ *	F_LSYMS		local symbols stripped from file
+ *	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax)
+ */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	20
+
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file				*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file	*/
+#ifndef BFD64
+  char 	data_start[4];		/* base of data used for this file	*/
+#endif
+}
+AOUTHDR;
+
+#define PE32MAGIC	0x10b	/* 32-bit image */
+#define PE32PMAGIC	0x20b	/* 32-bit image inside 64-bit address space */
+
+#define PE32PBADMAG(x) (((x).f_magic != PE32PMAGIC))
+
+#define AOUTSZ		108
+#define AOUTHDRSZ	108
+
+#define OMAGIC          0404    /* object files, eg as output */
+#define ZMAGIC          0413    /* demand load format, eg normal ld output */
+#define STMAGIC		0401	/* target shlib */
+#define SHMAGIC		0443	/* host   shlib */
+
+
+/* define some NT default values */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/********************** SECTION HEADER **********************/
+
+
+struct external_scnhdr {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size			*/
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[4];	/* flags			*/
+};
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _COMMENT ".comment"
+#define _LIB ".lib"
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+	union {
+		char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+		char l_paddr[4];	/* (physical) address of line number	*/
+	} l_addr;
+	char l_lnno[2];	/* line number		*/
+};
+
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	6
+
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+#define N_BTMASK	(0xf)
+#define N_TMASK		(0x30)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+union external_auxent {
+	struct {
+		char x_tagndx[4];	/* str, un, or enum tag indx */
+		union {
+			struct {
+			    char  x_lnno[2]; /* declaration line number */
+			    char  x_size[2]; /* str/union/array size */
+			} x_lnsz;
+			char x_fsize[4];	/* size of function */
+		} x_misc;
+		union {
+			struct {		/* if ISFCN, tag, or .bb */
+			    char x_lnnoptr[4];	/* ptr to fcn line # */
+			    char x_endndx[4];	/* entry ndx past block end */
+			} x_fcn;
+			struct {		/* if ISARY, up to 4 dimen. */
+			    char x_dimen[E_DIMNUM][2];
+			} x_ary;
+		} x_fcnary;
+		char x_tvndx[2];		/* tv index */
+	} x_sym;
+
+	union {
+		char x_fname[E_FILNMLEN];
+		struct {
+			char x_zeroes[4];
+			char x_offset[4];
+		} x_n;
+	} x_file;
+
+	struct {
+		char x_scnlen[4];	/* section length */
+		char x_nreloc[2];	/* # relocation entries */
+		char x_nlinno[2];	/* # line numbers */
+		char x_checksum[4];	/* section COMDAT checksum */
+		char x_associated[2];	/* COMDAT associated section index */
+		char x_comdat[1];	/* COMDAT selection number */
+	} x_scn;
+
+        struct {
+		char x_tvfill[4];	/* tv fill value */
+		char x_tvlen[2];	/* length of .tv */
+		char x_tvran[2][2];	/* tv range */
+	} x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+
+
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+
+
+#	define _ETEXT	"etext"
+
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+
+
+struct external_reloc {
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
diff --git a/gnu/usr.bin/binutils/include/coff/mcore.h b/gnu/usr.bin/binutils/include/coff/mcore.h
index 0fa319c977f..daf0247bb56 100644
--- a/gnu/usr.bin/binutils/include/coff/mcore.h
+++ b/gnu/usr.bin/binutils/include/coff/mcore.h
@@ -1,5 +1,5 @@
 /* Motorola MCore support for BFD.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright 1999 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
diff --git a/gnu/usr.bin/binutils/include/coff/mipspe.h b/gnu/usr.bin/binutils/include/coff/mipspe.h
index 1927d991d3b..b00b5d0e52e 100644
--- a/gnu/usr.bin/binutils/include/coff/mipspe.h
+++ b/gnu/usr.bin/binutils/include/coff/mipspe.h
@@ -1,4 +1,20 @@
-/*** coff information for Windows CE with MIPS VR4111 */
+/* coff information for Windows CE with MIPS VR4111
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /********************** FILE HEADER **********************/
 
diff --git a/gnu/usr.bin/binutils/include/coff/rs6k64.h b/gnu/usr.bin/binutils/include/coff/rs6k64.h
new file mode 100644
index 00000000000..ed1098e6d30
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/coff/rs6k64.h
@@ -0,0 +1,251 @@
+/* IBM RS/6000 "XCOFF64" file definitions for BFD.
+   Copyright (C) 2000 Free Software Foundation, Inc.  
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr {
+	char f_magic[2];	/* magic number			*/
+	char f_nscns[2];	/* number of sections		*/
+	char f_timdat[4];	/* time & date stamp		*/
+	char f_symptr[8];/* file pointer to symtab 	*/
+	char f_opthdr[2];	/* sizeof(optional hdr)		*/
+	char f_flags[2];	/* flags			*/
+	char f_nsyms[4];	/* number of symtab entries	*/
+};
+
+        /* IBM RS/6000 */
+#define U803XTOCMAGIC 0757	/* readonly text segments and TOC, XCOFF64 */
+
+#define BADMAG(x) ((x).f_magic != U803XTOCMAGIC)
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	24
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+
+typedef struct 
+{
+  unsigned char	magic[2];		/* type of file			*/
+  unsigned char	vstamp[2];		/* version stamp		*/
+  unsigned char	o_debugger[4];		/* reserved 			*/
+  unsigned char	text_start[8];	/* base of text used for this file */
+  unsigned char	data_start[8];	/* base of data used for this file */
+  unsigned char	o_toc[8];	/* address of TOC */
+  unsigned char	o_snentry[2];		/* section number of entry point */
+  unsigned char	o_sntext[2];		/* section number of .text section */
+  unsigned char	o_sndata[2];		/* section number of .data section */
+  unsigned char	o_sntoc[2];		/* section number of TOC */
+  unsigned char	o_snloader[2];		/* section number of .loader section */
+  unsigned char	o_snbss[2];		/* section number of .bss section */
+  unsigned char	o_algntext[2];		/* .text alignment */
+  unsigned char	o_algndata[2];		/* .data alignment */
+  unsigned char	o_modtype[2];		/* module type (??) */
+  unsigned char o_cputype[2];		/* cpu type */
+  unsigned char	o_resv2[4];		/* reserved 			*/
+  unsigned char	tsize[8];		/* text size bytes, padded to FW bdry */
+  unsigned char	dsize[8];		/* initialized data "  "	*/
+  unsigned char	bsize[8];		/* uninitialized data "   "	*/
+  unsigned char	entry[8];		/* entry pt.			*/
+  unsigned char	o_maxstack[8];	/* max stack size (??) 		*/
+  unsigned char o_maxdata[8];	/* max data size (??) 		*/
+  unsigned char	o_resv3[16];		/* reserved 			*/
+}
+AOUTHDR;
+
+#define AOUTSZ 120
+#define SMALL_AOUTSZ (0)
+#define AOUTHDRSZ 72
+
+#define	RS6K_AOUTHDR_OMAGIC	0x0107	/* old: text & data writeable */
+#define	RS6K_AOUTHDR_NMAGIC	0x0108	/* new: text r/o, data r/w */
+#define	RS6K_AOUTHDR_ZMAGIC	0x010B	/* paged: text r/o, both page-aligned */
+
+
+/********************** SECTION HEADER **********************/
+
+
+struct external_scnhdr {
+	char	s_name[8];		/* section name			*/
+	char	s_paddr[8];	/* physical address, aliased s_nlib */
+	char	s_vaddr[8];	/* virtual address		*/
+	char	s_size[8];	/* section size			*/
+	char	s_scnptr[8];	/* file ptr to raw data for section */
+	char	s_relptr[8];	/* file ptr to relocation	*/
+	char	s_lnnoptr[8];	/* file ptr to line numbers	*/
+	char	s_nreloc[4];	/* number of relocation entries	*/
+	char	s_nlnno[4];	/* number of line number entries*/
+	char	s_flags[4];		/* flags			*/
+	char    s_pad[4];		/* padding */  
+};
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _PAD	".pad"
+#define _LOADER	".loader"
+
+#define	SCNHDR	struct external_scnhdr
+
+#define	SCNHSZ	72
+
+/* XCOFF uses a special .loader section with type STYP_LOADER.  */
+#define STYP_LOADER 0x1000
+
+/* XCOFF uses a special .debug section with type STYP_DEBUG.  */
+#define STYP_DEBUG 0x2000
+
+/* XCOFF handles line number or relocation overflow by creating
+   another section header with STYP_OVRFLO set.  */
+#define STYP_OVRFLO 0x8000
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+	union {
+		char l_symndx[8];/* function name symbol index, iff l_lnno == 0*/
+		char l_paddr[8];	/* (physical) address of line number	*/
+	} l_addr;
+	char l_lnno[4];		/* line number		*/
+};
+
+
+#define	LINENO	struct external_lineno
+
+#define	LINESZ	12
+
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_value[8];
+  } e;
+  char e_offset[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+
+union external_auxent {
+
+    struct {
+    	union {
+	    struct {
+		char x_lnno[4]; 	/* declaration line number */
+		char x_size[2]; 	/* str/union/array size */
+	    } x_lnsz;
+	    struct {
+		char x_lnnoptr[8];/* ptr to fcn line */
+		char x_fsize[4];	 /* size of function */
+		char x_endndx[4];	 /* entry ndx past block end */
+	    } x_fcn;
+ 	} x_fcnary;
+    } x_sym;
+         
+    union {
+	char x_fname[E_FILNMLEN];
+	struct {
+	    char x_zeroes[4];
+	    char x_offset[4];
+	    char          x_pad[6];
+	    unsigned char x_ftype[1];
+	    unsigned char x_resv[2];
+	} x_n;
+    } x_file;
+
+    struct {
+	char x_exptr[8];
+	char x_fsize[4];
+	char x_endndx[4];
+	char x_pad[1];
+    } x_except;
+
+    struct {
+	    unsigned char x_scnlen_lo[4];
+	    unsigned char x_parmhash[4];
+	    unsigned char x_snhash[2];
+	    unsigned char x_smtyp[1];
+	    unsigned char x_smclas[1];
+	    unsigned char x_scnlen_hi[4];
+	    unsigned char x_pad[1];
+    } x_csect;	
+
+    struct {
+	char x_pad[17];
+	char x_auxtype[1];
+    } x_auxtype;
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+#define DBXMASK 0x80		/* for dbx storage mask */
+#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK)
+
+/* Values for auxtype field in XCOFF64, taken from AIX 4.3 sym.h */
+#define _AUX_EXCEPT     255
+#define _AUX_FCN        254
+#define _AUX_SYM        253
+#define _AUX_FILE       252
+#define _AUX_CSECT      251
+
+
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+
+struct external_reloc {
+  char r_vaddr[8];
+  char r_symndx[4];
+  char r_size[1];
+  char r_type[1];
+};
+
+
+#define RELOC struct external_reloc
+#define RELSZ 14
+
+#define DEFAULT_DATA_SECTION_ALIGNMENT 4
+#define DEFAULT_BSS_SECTION_ALIGNMENT 4
+#define DEFAULT_TEXT_SECTION_ALIGNMENT 4
+/* For new sections we havn't heard of before */
+#define DEFAULT_SECTION_ALIGNMENT 4
diff --git a/gnu/usr.bin/binutils/include/coff/ti.h b/gnu/usr.bin/binutils/include/coff/ti.h
new file mode 100644
index 00000000000..8fa35e3756b
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/coff/ti.h
@@ -0,0 +1,451 @@
+/* COFF information for TI COFF support.  Definitions in this file should be
+   customized in a target-specific file, and then this file included (see
+   tic54x.h for an example).
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef COFF_TI_H
+#define COFF_TI_H
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr {
+	char f_magic[2];	/* magic number			*/
+	char f_nscns[2];	/* number of sections		*/
+	char f_timdat[4];	/* time & date stamp		*/
+	char f_symptr[4];	/* file pointer to symtab	*/
+	char f_nsyms[4];	/* number of symtab entries	*/
+	char f_opthdr[2];	/* sizeof(optional hdr)		*/
+	char f_flags[2];	/* flags			*/
+        char f_target_id[2];    /* magic no. (TI COFF-specific) */
+};
+
+/* COFF0 has magic number in f_magic, and omits f_target_id from the file
+   header; for later versions, f_magic is 0xC1 for COFF1 and 0xC2 for COFF2
+   and the target-specific magic number is found in f_target_id */ 
+
+#define TICOFF0MAGIC    TI_TARGET_ID
+#define TICOFF1MAGIC    0x00C1
+#define TICOFF2MAGIC    0x00C2
+#define TICOFF_AOUT_MAGIC    0x0108 /* magic number in optional header */
+#define TICOFF          1 /* customize coffcode.h */
+
+/* The target_id field changes depending on the particular CPU target */
+/* for COFF0, the target id appeared in f_magic, where COFFX magic is now */
+#ifndef TI_TARGET_ID
+#error "TI_TARGET_ID needs to be defined for your CPU"
+#endif
+
+/* Which bfd_arch to use... */
+#ifndef TICOFF_TARGET_ARCH
+#error "TICOFF_TARGET_ARCH needs to be defined for your CPU"
+#endif
+
+/* Default to COFF2 for file output */
+#ifndef TICOFF_DEFAULT_MAGIC
+#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
+#endif
+
+/* This value is made available in the rare case where a bfd is unavailable */
+#ifndef OCTETS_PER_BYTE_POWER
+#error "OCTETS_PER_BYTE_POWER not defined for this CPU"
+#else
+#define OCTETS_PER_BYTE (1<<OCTETS_PER_BYTE_POWER)
+#endif
+
+/* default alignment is on a byte (not octet!) boundary */
+#ifndef COFF_DEFAULT_SECTION_ALIGNMENT_POWER
+#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 0
+#endif
+
+/* TI COFF encodes the section alignment in the section header flags */
+#define COFF_ALIGN_IN_SECTION_HEADER 1
+#define COFF_ALIGN_IN_S_FLAGS 1
+/* requires a power-of-two argument */
+#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8))
+/* result is a power of two */
+#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF)
+
+#define COFF0_P(ABFD) (bfd_coff_filhsz(ABFD) == FILHSZ_V0)
+#define COFF2_P(ABFD) (bfd_coff_scnhsz(ABFD) != SCNHSZ_V01)
+
+#define COFF0_BADMAG(x) ((x).f_magic != TICOFF0MAGIC)
+#define COFF1_BADMAG(x) ((x).f_magic != TICOFF1MAGIC || (x).f_target_id != TI_TARGET_ID)
+#define COFF2_BADMAG(x) ((x).f_magic != TICOFF2MAGIC || (x).f_target_id != TI_TARGET_ID)
+
+/* we need to read/write an extra field in the coff file header */
+#ifndef COFF_ADJUST_FILEHDR_IN_POST
+#define COFF_ADJUST_FILEHDR_IN_POST(abfd,src,dst) \
+do { ((struct internal_filehdr *)(dst))->f_target_id = \
+bfd_h_get_16(abfd, (bfd_byte *)(((FILHDR *)(src))->f_target_id)); \
+} while(0)
+#endif
+
+#ifndef COFF_ADJUST_FILEHDR_OUT_POST
+#define COFF_ADJUST_FILEHDR_OUT_POST(abfd,src,dst) \
+do { bfd_h_put_16(abfd, ((struct internal_filehdr *)(src))->f_target_id, \
+             (bfd_byte *)(((FILHDR *)(dst))->f_target_id)); \
+} while(0)
+#endif
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	22
+#define FILHSZ_V0 20                /* COFF0 omits target_id field */
+
+/* File header flags */
+#define	F_RELFLG	(0x0001)
+#define	F_EXEC		(0x0002)
+#define	F_LNNO		(0x0004)
+/* F_LSYMS needs to be redefined in your source file */
+#define	F_LSYMS_TICOFF	(0x0010) /* normal COFF is 0x8 */
+
+#define F_10            0x00    /* file built for TMS320C1x devices */
+#define F_20            0x10    /* file built for TMS320C2x devices */
+#define F_25            0x20    /* file built for TMS320C2x/C5x devices */
+#define F_LENDIAN       0x0100  /* 16 bits/word, LSB first */
+#define F_SYMMERGE      0x1000  /* duplicate symbols were removed */
+
+/********************** OPTIONAL HEADER **********************/
+
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file (0x108) 		*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file */
+  char 	data_start[4];		/* base of data used for this file */
+}
+AOUTHDR;
+
+
+#define AOUTHDRSZ 28
+#define AOUTSZ 28
+
+
+/********************** SECTION HEADER **********************/
+/* COFF0, COFF1 */
+struct external_scnhdr_v01 {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size (in WORDS)      */
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[2];	/* flags			*/
+        char            s_reserved[1];  /* reserved                     */ 
+        char            s_page[1];      /* section page number (LOAD)   */
+};
+
+/* COFF2 */
+struct external_scnhdr {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size (in WORDS)      */
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[4];	/* number of relocation entries	*/
+	char		s_nlnno[4];	/* number of line number entries*/
+	char		s_flags[4];	/* flags			*/
+        char            s_reserved[2];  /* reserved                     */ 
+        char            s_page[2];      /* section page number (LOAD)   */
+};
+
+/*
+ * Special section flags
+ */
+
+/* TI COFF defines these flags; 
+   STYP_CLINK: the section should be excluded from the final
+   linker output if there are no references found to any symbol in the section
+   STYP_BLOCK: the section should be blocked, i.e. if the section would cross
+   a page boundary, it is started at a page boundary instead.
+   TI COFF puts the section alignment power of two in the section flags
+   e.g. 2**N is alignment, flags |= (N & 0xF) << 8
+*/ 
+#define STYP_CLINK      (0x4000)
+#define STYP_BLOCK      (0x1000)
+#define STYP_ALIGN      (0x0F00) /* TI COFF stores section alignment here */
+
+#define	SCNHDR_V01 struct external_scnhdr_v01
+#define SCNHDR struct external_scnhdr
+#define	SCNHSZ_V01 40                  /* for v0 and v1 */
+#define SCNHSZ 48
+
+/* COFF2 changes the offsets and sizes of these fields 
+   Assume we're dealing with the COFF2 scnhdr structure, and adjust
+   accordingly 
+ */
+#define GET_SCNHDR_NRELOC(ABFD,PTR) \
+(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, PTR))
+#define PUT_SCNHDR_NRELOC(ABFD,VAL,PTR) \
+(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,PTR))
+#define GET_SCNHDR_NLNNO(ABFD,PTR) \
+(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, (PTR)-2))
+#define PUT_SCNHDR_NLNNO(ABFD,VAL,PTR) \
+(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,(PTR)-2))
+#define GET_SCNHDR_FLAGS(ABFD,PTR) \
+(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, (PTR)-4))
+#define PUT_SCNHDR_FLAGS(ABFD,VAL,PTR) \
+(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,(PTR)-4))
+#define GET_SCNHDR_PAGE(ABFD,PTR) \
+(COFF2_P(ABFD) ? bfd_h_get_16 (ABFD,PTR) : bfd_h_get_8 (ABFD, (PTR)-7))
+/* on output, make sure that the "reserved" field is zero */
+#define PUT_SCNHDR_PAGE(ABFD,VAL,PTR) \
+(COFF2_P(ABFD) ? bfd_h_put_16 (ABFD,VAL,PTR) : \
+bfd_h_put_8 (ABFD,VAL,(PTR)-7), bfd_h_put_8 (ABFD, 0, (PTR)-8))
+
+/* TI COFF stores section size as number of bytes (address units, not octets),
+   so adjust to be number of octets, which is what BFD expects */ 
+#define GET_SCNHDR_SIZE(ABFD,SZP) \
+(bfd_h_get_32(ABFD,SZP)*bfd_octets_per_byte(ABFD))
+#define PUT_SCNHDR_SIZE(ABFD,SZ,SZP) \
+bfd_h_put_32(ABFD,(SZ)/bfd_octets_per_byte(ABFD),SZP)
+
+#define COFF_ADJUST_SCNHDR_IN_POST(ABFD,EXT,INT) \
+do { ((struct internal_scnhdr *)(INT))->s_page = \
+GET_SCNHDR_PAGE(ABFD,(bfd_byte *)((SCNHDR *)(EXT))->s_page); \
+} while(0)
+
+/* The line number and reloc overflow checking in coff_swap_scnhdr_out in
+   coffswap.h doesn't use PUT_X for s_nlnno and s_nreloc.
+   Due to different sized v0/v1/v2 section headers, we have to re-write these
+   fields.
+ */
+#define COFF_ADJUST_SCNHDR_OUT_POST(ABFD,INT,EXT) \
+do { \
+PUT_SCNHDR_NLNNO(ABFD,((struct internal_scnhdr *)(INT))->s_nlnno,\
+                (bfd_byte *)((SCNHDR *)(EXT))->s_nlnno); \
+PUT_SCNHDR_NRELOC(ABFD,((struct internal_scnhdr *)(INT))->s_nreloc,\
+                (bfd_byte *)((SCNHDR *)(EXT))->s_nreloc); \
+PUT_SCNHDR_FLAGS(ABFD,((struct internal_scnhdr *)(INT))->s_flags, \
+                (bfd_byte *)((SCNHDR *)(EXT))->s_flags); \
+PUT_SCNHDR_PAGE(ABFD,((struct internal_scnhdr *)(INT))->s_page, \
+                (bfd_byte *)((SCNHDR *)(EXT))->s_page); \
+} while(0)
+
+/* Page macros
+
+   The first GDB port requires flags in its remote memory access commands to
+   distinguish between data/prog space.  Hopefully we can make this go away
+   eventually.  Stuff the page in the upper bits of a 32-bit address, since
+   the c5x family only uses 16 or 23 bits.
+
+   c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has
+   23-bit program addresses.  Make sure the page flags don't interfere.
+   These flags are used by GDB to identify the destination page for
+   addresses. 
+*/
+
+/* recognized load pages */
+#define PG_PROG         0x0         /* PROG page */
+#define PG_DATA         0x1         /* DATA page */
+
+#define ADDR_MASK       0x00FFFFFF
+#define PG_TO_FLAG(p)   (((unsigned long)(p) & 0xFF) << 24)
+#define FLAG_TO_PG(f)   (((f) >> 24) & 0xFF)
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _CINIT  ".cinit"            /* initialized C data */
+#define _SCONST  ".const"           /* constants */
+#define _SWITCH ".switch"           /* switch tables */
+#define _STACK  ".stack"            /* C stack */
+#define _SYSMEM ".sysmem"           /* used for malloc et al. syscalls */
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+  union {
+    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[4];	/* (physical) address of line number	*/
+  } l_addr;
+  char l_lnno[2];	/* line number		*/
+};
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	6
+
+
+/********************** SYMBOLS **********************/
+
+/* NOTE: this is what a local label looks like in assembly source; what it
+   looks like in COFF output is undefined */
+#define TICOFF_LOCAL_LABEL_P(NAME) \
+((NAME[0] == '$' && NAME[1] >= '0' && NAME[1] <= '9' && NAME[2] == '\0') \
+ || NAME[strlen(NAME)-1] == '?')
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+
+union external_auxent {
+  struct {
+	char x_tagndx[4];	/* str, un, or enum tag indx */
+	union {
+	  struct {
+		char  x_lnno[2]; /* declaration line number */
+		char  x_size[2]; /* str/union/array size */
+	  } x_lnsz;
+	  char x_fsize[4];	/* size of function */
+	} x_misc;
+	union {
+	  struct {		/* if ISFCN, tag, or .bb */
+		char x_lnnoptr[4];	/* ptr to fcn line # */
+		char x_endndx[4];	/* entry ndx past block end */
+	  } x_fcn;
+	  struct {		/* if ISARY, up to 4 dimen. */
+		char x_dimen[E_DIMNUM][2];
+	  } x_ary;
+	} x_fcnary;
+	char x_tvndx[2];		/* tv index */
+  } x_sym;
+  
+  union {
+	char x_fname[E_FILNMLEN];
+	struct {
+	  char x_zeroes[4];
+	  char x_offset[4];
+	} x_n;
+  } x_file;
+  
+  struct {
+	char x_scnlen[4];			/* section length */
+	char x_nreloc[2];	/* # relocation entries */
+	char x_nlinno[2];	/* # line numbers */
+  } x_scn;
+  
+  struct {
+	char x_tvfill[4];	/* tv fill value */
+	char x_tvlen[2];	/* length of .tv */
+	char x_tvran[2][2];	/* tv range */
+  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+  
+
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+
+/* section lengths are in target bytes (not host bytes) */
+#define GET_SCN_SCNLEN(ABFD,EXT) \
+(bfd_h_get_32(ABFD,(bfd_byte *)(EXT)->x_scn.x_scnlen)*bfd_octets_per_byte(ABFD))
+#define PUT_SCN_SCNLEN(ABFD,INT,EXT) \
+bfd_h_put_32(ABFD,(INT)/bfd_octets_per_byte(ABFD),\
+             (bfd_byte *)(EXT)->x_scn.x_scnlen)
+
+/* lnsz size is in bits in COFF file, in bytes in BFD */
+#define GET_LNSZ_SIZE(abfd, ext) \
+(bfd_h_get_16(abfd, (bfd_byte *)ext->x_sym.x_misc.x_lnsz.x_size) / \
+ (class != C_FIELD ? 8 : 1))
+
+#define PUT_LNSZ_SIZE(abfd, in, ext) \
+ bfd_h_put_16(abfd, ((class != C_FIELD) ? (in)*8 : (in)), \
+              (bfd_byte*) ext->x_sym.x_misc.x_lnsz.x_size)
+ 
+/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes */
+#define COFF_ADJUST_SYM_IN_POST(ABFD,EXT,INT) \
+do { struct internal_syment *dst = (struct internal_syment *)(INT); \
+if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU) dst->n_value /= 8; \
+} while (0)
+
+#define COFF_ADJUST_SYM_OUT_POST(ABFD,INT,EXT) \
+do { struct internal_syment *src = (struct internal_syment *)(INT); \
+SYMENT *dst = (SYMENT *)(EXT); \
+if(src->n_sclass == C_MOU || src->n_sclass == C_MOS) \
+bfd_h_put_32(abfd,src->n_value * 8,(bfd_byte *)dst->e_value); \
+} while (0)
+
+/* Detect section-relative absolute symbols so they get flagged with a sym
+   index of -1.
+*/
+#define SECTION_RELATIVE_ABSOLUTE_SYMBOL_P(RELOC,SECT) \
+((*(RELOC)->sym_ptr_ptr)->section->output_section == (SECT) \
+ && (RELOC)->howto->name[0] == 'A')
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc_v0 {
+  char r_vaddr[4];
+  char r_symndx[2];
+  char r_reserved[2];
+  char r_type[2];
+};
+
+struct external_reloc {
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_reserved[2]; /* extended pmad byte for COFF2 */
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ_V0 10                 /* FIXME -- coffcode.h needs fixing */
+#define RELSZ 12                    /* for COFF1/2 */
+
+/* various relocation types.  */
+#define R_ABS     0x0000            /* no relocation */
+#define R_REL13   0x002A            /* 13-bit direct reference (???) */
+#define R_PARTLS7 0x0028            /* 7 LSBs of an address */
+#define R_PARTMS9 0x0029            /* 9MSBs of an address */
+#define R_EXTWORD 0x002B            /* 23-bit direct reference */
+#define R_EXTWORD16 0x002C          /* 16-bit direct reference to 23-bit addr*/
+#define R_EXTWORDMS7 0x002D         /* upper 7 bits of 23-bit address */
+
+#endif /* COFF_TI_H */
diff --git a/gnu/usr.bin/binutils/include/coff/tic30.h b/gnu/usr.bin/binutils/include/coff/tic30.h
index 10b026cebe2..1b5b5fdc5e2 100644
--- a/gnu/usr.bin/binutils/include/coff/tic30.h
+++ b/gnu/usr.bin/binutils/include/coff/tic30.h
@@ -1,4 +1,20 @@
-/*** coff information for Texas Instruments TMS320C3X */
+/* coff information for Texas Instruments TMS320C3X
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /********************** FILE HEADER **********************/
 
diff --git a/gnu/usr.bin/binutils/include/coff/tic54x.h b/gnu/usr.bin/binutils/include/coff/tic54x.h
new file mode 100644
index 00000000000..a41c8d25091
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/coff/tic54x.h
@@ -0,0 +1,34 @@
+/* TI COFF information for Texas Instruments TMS320C54X.
+   This file customizes the settings in coff/ti.h. 
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef COFF_TIC54X_H
+
+#define COFF_TIC54X_H
+#define TIC54X_TARGET_ID 0x98
+#define TIC54XALGMAGIC  0x009B  /* c54x algebraic assembler output */
+#define TIC5X_TARGET_ID  0x92
+#define TI_TARGET_ID TIC54X_TARGET_ID
+#define OCTETS_PER_BYTE_POWER 1 /* octets per byte, as a power of two */
+#define HOWTO_BANK 6 /* add to howto to get absolute/sect-relative version */
+#define TICOFF_TARGET_ARCH bfd_arch_tic54x
+#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */
+
+#include "coff/ti.h"
+
+#endif /* COFF_TIC54X_H */
diff --git a/gnu/usr.bin/binutils/include/coff/tic80.h b/gnu/usr.bin/binutils/include/coff/tic80.h
index 5d938f7b1f0..5f14d00958d 100644
--- a/gnu/usr.bin/binutils/include/coff/tic80.h
+++ b/gnu/usr.bin/binutils/include/coff/tic80.h
@@ -1,4 +1,20 @@
-/*** coff information for TI TMS320C80 (MVP) */
+/* coff information for TI TMS320C80 (MVP)
+   
+   Copyright 2001 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /********************** FILE HEADER **********************/
 
diff --git a/gnu/usr.bin/binutils/include/elf/alpha.h b/gnu/usr.bin/binutils/include/elf/alpha.h
index 1ae9d5efd6d..8bf67bd3d0f 100644
--- a/gnu/usr.bin/binutils/include/elf/alpha.h
+++ b/gnu/usr.bin/binutils/include/elf/alpha.h
@@ -1,5 +1,5 @@
 /* ALPHA ELF support for BFD.
-   Copyright (C) 1996, 1998 Free Software Foundation, Inc.
+   Copyright 1996, 1998, 2000 Free Software Foundation, Inc.
 
    By Eric Youngdale, <eric@aib.com>.  No processor supplement available
    for this platform.
@@ -102,7 +102,6 @@ START_RELOC_NUMBERS (elf_alpha_reloc_type)
   RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26)	/* Create PLT entry */
   RELOC_NUMBER (R_ALPHA_RELATIVE, 27)	/* Adjust by program base */
 
-  EMPTY_RELOC  (R_ALPHA_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_ALPHA_max)
 
 #endif /* _ELF_ALPHA_H */
diff --git a/gnu/usr.bin/binutils/include/elf/arc.h b/gnu/usr.bin/binutils/include/elf/arc.h
index 334b55fa6d0..6e94c29dbce 100644
--- a/gnu/usr.bin/binutils/include/elf/arc.h
+++ b/gnu/usr.bin/binutils/include/elf/arc.h
@@ -1,5 +1,5 @@
 /* ARC ELF support for BFD.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
+   Copyright 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
    Contributed by Doug Evans, (dje@cygnus.com)
 
 This file is part of BFD, the Binary File Descriptor library.
@@ -26,29 +26,31 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include "elf/reloc-macros.h"
 
 /* Relocations.  */
+
 START_RELOC_NUMBERS (elf_arc_reloc_type)
   RELOC_NUMBER (R_ARC_NONE, 0)
   RELOC_NUMBER (R_ARC_32, 1)
   RELOC_NUMBER (R_ARC_B26, 2)
   RELOC_NUMBER (R_ARC_B22_PCREL, 3)
-  EMPTY_RELOC  (R_ARC_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_ARC_max)
 
 /* Processor specific flags for the ELF header e_flags field.  */
 
 /* Four bit ARC machine type field.  */
-#define EF_ARC_MACH		0x0000000f
+
+#define EF_ARC_MACH 0x0000000f
 
 /* Various CPU types.  */
-#define E_ARC_MACH_BASE		0x00000000
-#define E_ARC_MACH_UNUSED1	0x00000001
-#define E_ARC_MACH_UNUSED2	0x00000002
-#define E_ARC_MACH_UNUSED4	0x00000003
 
-/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
-   Highly unlikely, but what the heck.  */
+#define E_ARC_MACH_ARC5 0
+#define E_ARC_MACH_ARC6 1	
+#define E_ARC_MACH_ARC7 2
+#define E_ARC_MACH_ARC8 3
+
+/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.  */
 
 /* File contains position independent code.  */
-#define EF_ARC_PIC		0x00000100
+
+#define EF_ARC_PIC 0x00000100
 
 #endif /* _ELF_ARC_H */
diff --git a/gnu/usr.bin/binutils/include/elf/arm.h b/gnu/usr.bin/binutils/include/elf/arm.h
index 4d3405dd7e6..28e87a81948 100644
--- a/gnu/usr.bin/binutils/include/elf/arm.h
+++ b/gnu/usr.bin/binutils/include/elf/arm.h
@@ -1,5 +1,5 @@
 /* ARM ELF support for BFD.
-   Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -34,6 +34,14 @@
 #define EF_OLD_ABI         0x100
 #define EF_SOFT_FLOAT      0x200
 
+/* Other constants defined in the ARM ELF spec. version A-08.  */
+#define EF_ARM_SYMSARESORTED 0x04	/* NB conflicts with EF_INTERWORK */
+#define EF_ARM_EABIMASK      0xFF000000
+
+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
+#define EF_ARM_EABI_UNKNOWN  0x00000000
+#define EF_ARM_EABI_VER1     0x01000000
+
 /* Local aliases for some flags to match names used by COFF port.  */
 #define F_INTERWORK	   EF_INTERWORK
 #define F_APCS26	   EF_APCS_26
@@ -51,49 +59,71 @@
 
 /* ARM-specific program header flags.  */
 #define PF_ARM_SB          0x10000000   /* Segment contains the location addressed by the static base.  */
+#define PF_ARM_PI          0x20000000   /* Segment is position-independent.  */
+#define PF_ARM_ABS         0x40000000   /* Segment must be loaded at its base address.  */
 
 /* Relocation types.  */
+
 START_RELOC_NUMBERS (elf_arm_reloc_type)
-  RELOC_NUMBER (R_ARM_NONE,         0)
-  RELOC_NUMBER (R_ARM_PC24,         1)
-  RELOC_NUMBER (R_ARM_ABS32,        2)
-  RELOC_NUMBER (R_ARM_REL32,        3)
-  RELOC_NUMBER (R_ARM_PC13,         4)
-  RELOC_NUMBER (R_ARM_ABS16,        5)
-  RELOC_NUMBER (R_ARM_ABS12,        6)
-  RELOC_NUMBER (R_ARM_THM_ABS5,     7)
-  RELOC_NUMBER (R_ARM_ABS8,         8)
-  RELOC_NUMBER (R_ARM_SBREL32,      9)
-  RELOC_NUMBER (R_ARM_THM_PC22,    10)
-  RELOC_NUMBER (R_ARM_THM_PC8,     11)
-  RELOC_NUMBER (R_ARM_AMP_VCALL9,  12)
-  RELOC_NUMBER (R_ARM_SWI24,       13)
-  RELOC_NUMBER (R_ARM_THM_SWI8,    14)
-  RELOC_NUMBER (R_ARM_XPC25,       15)
-  RELOC_NUMBER (R_ARM_THM_XPC22,   16)
-  RELOC_NUMBER (R_ARM_COPY,        20)       /* copy symbol at runtime */
-  RELOC_NUMBER (R_ARM_GLOB_DAT,    21)       /* create GOT entry */
-  RELOC_NUMBER (R_ARM_JUMP_SLOT,   22)       /* create PLT entry */
-  RELOC_NUMBER (R_ARM_RELATIVE,    23)       /* adjust by program base */
-  RELOC_NUMBER (R_ARM_GOTOFF,      24)       /* 32 bit offset to GOT */
-  RELOC_NUMBER (R_ARM_GOTPC,       25)       /* 32 bit PC relative offset to GOT */
-  RELOC_NUMBER (R_ARM_GOT32,       26)       /* 32 bit GOT entry */
-  RELOC_NUMBER (R_ARM_PLT32,       27)       /* 32 bit PLT address */
-  FAKE_RELOC   (FIRST_INVALID_RELOC1, 28)
-  FAKE_RELOC   (LAST_INVALID_RELOC1,  99)
-  RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100)
-  RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101)
-  RELOC_NUMBER (R_ARM_THM_PC11,    102)       /* Cygnus extension to abi: Thumb unconditional branch */
-  RELOC_NUMBER (R_ARM_THM_PC9,     103)       /* Cygnus extension to abi: Thumb conditional branch */
+  RELOC_NUMBER (R_ARM_NONE,             0)
+  RELOC_NUMBER (R_ARM_PC24,             1)
+  RELOC_NUMBER (R_ARM_ABS32,            2)
+  RELOC_NUMBER (R_ARM_REL32,            3)
+#ifdef OLD_ARM_ABI
+  RELOC_NUMBER (R_ARM_ABS8,             4)
+  RELOC_NUMBER (R_ARM_ABS16,            5)
+  RELOC_NUMBER (R_ARM_ABS12,            6)
+  RELOC_NUMBER (R_ARM_THM_ABS5,         7)
+  RELOC_NUMBER (R_ARM_THM_PC22,         8)
+  RELOC_NUMBER (R_ARM_SBREL32,          9)
+  RELOC_NUMBER (R_ARM_AMP_VCALL9,      10)
+  RELOC_NUMBER (R_ARM_THM_PC11,        11)   /* Cygnus extension to abi: Thumb unconditional branch.  */
+  RELOC_NUMBER (R_ARM_THM_PC9,         12)   /* Cygnus extension to abi: Thumb conditional branch.  */
+  RELOC_NUMBER (R_ARM_GNU_VTINHERIT,   13)  
+  RELOC_NUMBER (R_ARM_GNU_VTENTRY,     14)  
+#else /* not OLD_ARM_ABI */
+  RELOC_NUMBER (R_ARM_PC13,             4)
+  RELOC_NUMBER (R_ARM_ABS16,            5)
+  RELOC_NUMBER (R_ARM_ABS12,            6)
+  RELOC_NUMBER (R_ARM_THM_ABS5,         7)
+  RELOC_NUMBER (R_ARM_ABS8,             8)
+  RELOC_NUMBER (R_ARM_SBREL32,          9)
+  RELOC_NUMBER (R_ARM_THM_PC22,        10)
+  RELOC_NUMBER (R_ARM_THM_PC8,         11)
+  RELOC_NUMBER (R_ARM_AMP_VCALL9,      12)
+  RELOC_NUMBER (R_ARM_SWI24,           13)
+  RELOC_NUMBER (R_ARM_THM_SWI8,        14)
+  RELOC_NUMBER (R_ARM_XPC25,           15)
+  RELOC_NUMBER (R_ARM_THM_XPC22,       16)
+#endif /* not OLD_ARM_ABI */
+  RELOC_NUMBER (R_ARM_COPY,            20)   /* Copy symbol at runtime.  */
+  RELOC_NUMBER (R_ARM_GLOB_DAT,        21)   /* Create GOT entry.  */
+  RELOC_NUMBER (R_ARM_JUMP_SLOT,       22)   /* Create PLT entry.  */
+  RELOC_NUMBER (R_ARM_RELATIVE,        23)   /* Adjust by program base.  */
+  RELOC_NUMBER (R_ARM_GOTOFF,          24)   /* 32 bit offset to GOT.  */
+  RELOC_NUMBER (R_ARM_GOTPC,           25)   /* 32 bit PC relative offset to GOT.  */
+  RELOC_NUMBER (R_ARM_GOT32,           26)   /* 32 bit GOT entry.  */
+  RELOC_NUMBER (R_ARM_PLT32,           27)   /* 32 bit PLT address.  */
+#ifdef OLD_ARM_ABI
+  FAKE_RELOC   (FIRST_INVALID_RELOC,   28)
+  FAKE_RELOC   (LAST_INVALID_RELOC,   249)
+#else /* not OLD_ARM_ABI */
+  FAKE_RELOC   (FIRST_INVALID_RELOC1,  28)
+  FAKE_RELOC   (LAST_INVALID_RELOC1,   99)
+  RELOC_NUMBER (R_ARM_GNU_VTENTRY,    100)
+  RELOC_NUMBER (R_ARM_GNU_VTINHERIT,  101)
+  RELOC_NUMBER (R_ARM_THM_PC11,       102)   /* Cygnus extension to abi: Thumb unconditional branch.  */
+  RELOC_NUMBER (R_ARM_THM_PC9,        103)   /* Cygnus extension to abi: Thumb conditional branch.  */
   FAKE_RELOC   (FIRST_INVALID_RELOC2, 104)
   FAKE_RELOC   (LAST_INVALID_RELOC2,  248)
-  RELOC_NUMBER (R_ARM_RXPC25,     249)
-  RELOC_NUMBER (R_ARM_RSBREL32,   250)
-  RELOC_NUMBER (R_ARM_THM_RPC22,  251)
-  RELOC_NUMBER (R_ARM_RREL32,     252)
-  RELOC_NUMBER (R_ARM_RABS32,     253)
-  RELOC_NUMBER (R_ARM_RPC24,      254)
-  RELOC_NUMBER (R_ARM_RBASE,      255)
-END_RELOC_NUMBERS
-
-#endif
+  RELOC_NUMBER (R_ARM_RXPC25,         249)
+#endif /* not OLD_ARM_ABI */
+  RELOC_NUMBER (R_ARM_RSBREL32,       250)
+  RELOC_NUMBER (R_ARM_THM_RPC22,      251)
+  RELOC_NUMBER (R_ARM_RREL32,         252)
+  RELOC_NUMBER (R_ARM_RABS32,         253)
+  RELOC_NUMBER (R_ARM_RPC24,          254)
+  RELOC_NUMBER (R_ARM_RBASE,          255)
+END_RELOC_NUMBERS (R_ARM_max)
+
+#endif /* _ELF_ARM_H */
diff --git a/gnu/usr.bin/binutils/include/elf/avr.h b/gnu/usr.bin/binutils/include/elf/avr.h
index 1527455995e..59cf0734715 100644
--- a/gnu/usr.bin/binutils/include/elf/avr.h
+++ b/gnu/usr.bin/binutils/include/elf/avr.h
@@ -1,5 +1,5 @@
 /* AVR ELF support for BFD.
-   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1999, 2000 Free Software Foundation, Inc.
    Contributed by Denis Chertykov <denisc@overta.ru>
 
 This file is part of BFD, the Binary File Descriptor library.
@@ -30,6 +30,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define E_AVR_MACH_AVR2 2
 #define E_AVR_MACH_AVR3 3
 #define E_AVR_MACH_AVR4 4
+#define E_AVR_MACH_AVR5 5
 
 /* Relocations.  */
 START_RELOC_NUMBERS (elf_avr_reloc_type)
@@ -52,7 +53,6 @@ START_RELOC_NUMBERS (elf_avr_reloc_type)
      RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG,       16)
      RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG,       17)
      RELOC_NUMBER (R_AVR_CALL,		       18)
-     EMPTY_RELOC  (R_AVR_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_AVR_max)
 
 #endif /* _ELF_AVR_H */
diff --git a/gnu/usr.bin/binutils/include/elf/cris.h b/gnu/usr.bin/binutils/include/elf/cris.h
new file mode 100644
index 00000000000..860537534b5
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/elf/cris.h
@@ -0,0 +1,47 @@
+/* CRIS ELF support for BFD.
+   Copyright 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Axis Communications AB, Lund, Sweden.
+   Written by Hans-Peter Nilsson.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_CRIS_H
+#define _ELF_CRIS_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_cris_reloc_type)
+  RELOC_NUMBER (R_CRIS_NONE,		0)
+  RELOC_NUMBER (R_CRIS_8,		1)
+  RELOC_NUMBER (R_CRIS_16,		2)
+  RELOC_NUMBER (R_CRIS_32,		3)
+  RELOC_NUMBER (R_CRIS_8_PCREL,		4)
+  RELOC_NUMBER (R_CRIS_16_PCREL,	5)
+  RELOC_NUMBER (R_CRIS_32_PCREL,	6)
+
+  RELOC_NUMBER (R_CRIS_GNU_VTINHERIT,	7)
+  RELOC_NUMBER (R_CRIS_GNU_VTENTRY,	8)
+
+  /* No other relocs must be visible outside the assembler.  */
+
+END_RELOC_NUMBERS (R_CRIS_max)
+
+/* User symbols in this file have a leading underscore.  */
+#define EF_CRIS_UNDERSCORE		0x00000001
+
+#endif /* _ELF_CRIS_H */
diff --git a/gnu/usr.bin/binutils/include/elf/d10v.h b/gnu/usr.bin/binutils/include/elf/d10v.h
index 63b79c801b1..5bc613bc3bf 100644
--- a/gnu/usr.bin/binutils/include/elf/d10v.h
+++ b/gnu/usr.bin/binutils/include/elf/d10v.h
@@ -1,5 +1,5 @@
 /* d10v ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -33,6 +33,6 @@ START_RELOC_NUMBERS (elf_d10v_reloc_type)
   RELOC_NUMBER (R_D10V_32, 6)
   RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7)
   RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_D10V_max)
 
 #endif
diff --git a/gnu/usr.bin/binutils/include/elf/d30v.h b/gnu/usr.bin/binutils/include/elf/d30v.h
index adbad192325..5abb06a551f 100644
--- a/gnu/usr.bin/binutils/include/elf/d30v.h
+++ b/gnu/usr.bin/binutils/include/elf/d30v.h
@@ -1,5 +1,5 @@
 /* d30v ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -37,6 +37,6 @@ START_RELOC_NUMBERS (elf_d30v_reloc_type)
   RELOC_NUMBER (R_D30V_32, 10)
   RELOC_NUMBER (R_D30V_32_PCREL, 11)
   RELOC_NUMBER (R_D30V_32_NORMAL, 12)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_D30V_max)
 
 #endif
diff --git a/gnu/usr.bin/binutils/include/elf/dwarf2.h b/gnu/usr.bin/binutils/include/elf/dwarf2.h
index 1bd4fa6cac9..82586bb2321 100644
--- a/gnu/usr.bin/binutils/include/elf/dwarf2.h
+++ b/gnu/usr.bin/binutils/include/elf/dwarf2.h
@@ -1,6 +1,6 @@
 /* Declarations and definitions of codes relating to the DWARF symbolic
    debugging information format.
-   Copyright (C) 1992, 1993, 1995, 1996, 1999 Free Software Foundation, Inc.
+   Copyright 1992, 1993, 1995, 1996, 1999 Free Software Foundation, Inc.
 
    Written by Gary Funck (gary@intrepid.com) The Ada Joint Program
    Office (AJPO), Florida State Unviversity and Silicon Graphics Inc.
diff --git a/gnu/usr.bin/binutils/include/elf/fr30.h b/gnu/usr.bin/binutils/include/elf/fr30.h
index 223b052973a..12a450dffd0 100644
--- a/gnu/usr.bin/binutils/include/elf/fr30.h
+++ b/gnu/usr.bin/binutils/include/elf/fr30.h
@@ -1,5 +1,5 @@
 /* FR30 ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -37,7 +37,6 @@ START_RELOC_NUMBERS (elf_fr30_reloc_type)
   RELOC_NUMBER (R_FR30_12_PCREL, 10)
   RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11)
   RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12)
-  EMPTY_RELOC  (R_FR30_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_FR30_max)
 
 #endif /* _ELF_FR30_H */
diff --git a/gnu/usr.bin/binutils/include/elf/i370.h b/gnu/usr.bin/binutils/include/elf/i370.h
index 9c021f00e89..b6f478535a5 100644
--- a/gnu/usr.bin/binutils/include/elf/i370.h
+++ b/gnu/usr.bin/binutils/include/elf/i370.h
@@ -1,5 +1,5 @@
 /* i370 ELF support for BFD.
-   Copyright (C) 1995, 2000 Free Software Foundation, Inc.
+   Copyright 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
diff --git a/gnu/usr.bin/binutils/include/elf/i386.h b/gnu/usr.bin/binutils/include/elf/i386.h
index 0586661720e..4a15efc4912 100644
--- a/gnu/usr.bin/binutils/include/elf/i386.h
+++ b/gnu/usr.bin/binutils/include/elf/i386.h
@@ -1,5 +1,5 @@
 /* ix86 ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -40,10 +40,9 @@ START_RELOC_NUMBERS (elf_i386_reloc_type)
      RELOC_NUMBER (R_386_PC16,     21)
      RELOC_NUMBER (R_386_8,	   22)
      RELOC_NUMBER (R_386_PC8,      23)
-     RELOC_NUMBER (R_386_max,	   24)
      /* These are GNU extensions to enable C++ vtable garbage collection.  */
      RELOC_NUMBER (R_386_GNU_VTINHERIT, 250)
      RELOC_NUMBER (R_386_GNU_VTENTRY, 251)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_386_max)
 
 #endif
diff --git a/gnu/usr.bin/binutils/include/elf/i860.h b/gnu/usr.bin/binutils/include/elf/i860.h
new file mode 100644
index 00000000000..de34aeb0141
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/elf/i860.h
@@ -0,0 +1,66 @@
+/* i860 ELF support for BFD.
+   Copyright 2000 Free Software Foundation, Inc.
+
+   Contributed by Jason Eckhardt <jle@cygnus.com>.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_I860_H
+#define _ELF_I860_H
+
+/* Note: i860 ELF is defined to use only RELA relocations.  */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_i860_reloc_type)
+     RELOC_NUMBER (R_860_NONE,      0x00)	/* No reloc */
+     RELOC_NUMBER (R_860_32,        0x01)	/* S+A  */
+     RELOC_NUMBER (R_860_COPY,	    0x02)	/* No calculation */
+     RELOC_NUMBER (R_860_GLOB_DAT,  0x03)	/* S, Create GOT entry */
+     RELOC_NUMBER (R_860_JUMP_SLOT, 0x04)	/* S+A, Create PLT entry */
+     RELOC_NUMBER (R_860_RELATIVE,  0x05)	/* B+A, Adj by program base */
+     RELOC_NUMBER (R_860_PC26,      0x30)	/* (S+A-P) >> 2 */ 
+     RELOC_NUMBER (R_860_PLT26,	    0x31)	/* (L+A-P) >> 2 */
+     RELOC_NUMBER (R_860_PC16,      0x32)	/* (S+A-P) >> 2 */
+     RELOC_NUMBER (R_860_LOW0,      0x40)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT0,    0x42)	/* S+A */       
+     RELOC_NUMBER (R_860_LOW1,      0x44)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT1,    0x46)	/* S+A */
+     RELOC_NUMBER (R_860_LOW2,      0x48)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT2,    0x4A)	/* S+A */
+     RELOC_NUMBER (R_860_LOW3,      0x4C)	/* S+A */
+     RELOC_NUMBER (R_860_LOGOT0,    0x50)	/* G */
+     RELOC_NUMBER (R_860_SPGOT0,    0x52)	/* G */
+     RELOC_NUMBER (R_860_LOGOT1,    0x54)	/* G */
+     RELOC_NUMBER (R_860_SPGOT1,    0x56)	/* G */
+     RELOC_NUMBER (R_860_LOGOTOFF0, 0x60)	/* O */
+     RELOC_NUMBER (R_860_SPGOTOFF0, 0x62)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF1, 0x64)	/* O */
+     RELOC_NUMBER (R_860_SPGOTOFF1, 0x66)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF2, 0x68)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C)	/* O */
+     RELOC_NUMBER (R_860_LOPC,      0x70)	/* (S+A-P) >> 2 */
+     RELOC_NUMBER (R_860_HIGHADJ,   0x80)	/* hiadj(S+A) */
+     RELOC_NUMBER (R_860_HAGOT,     0x90)	/* hiadj(G) */
+     RELOC_NUMBER (R_860_HAGOTOFF,  0xA0)	/* hiadj(O) */
+     RELOC_NUMBER (R_860_HAPC,      0xB0)	/* hiadj((S+A-P) >> 2) */
+     RELOC_NUMBER (R_860_HIGH,      0xC0)	/* (S+A) >> 16 */
+     RELOC_NUMBER (R_860_HIGOT,     0xD0)	/* G >> 16 */
+     RELOC_NUMBER (R_860_HIGOTOFF,  0xE0)	/* O */
+END_RELOC_NUMBERS (R_860_max)
+
+#endif
diff --git a/gnu/usr.bin/binutils/include/elf/i960.h b/gnu/usr.bin/binutils/include/elf/i960.h
index 3e60289ea99..253e438522d 100644
--- a/gnu/usr.bin/binutils/include/elf/i960.h
+++ b/gnu/usr.bin/binutils/include/elf/i960.h
@@ -1,5 +1,5 @@
 /* Intel 960 ELF support for BFD.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright 1999, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -32,7 +32,6 @@ START_RELOC_NUMBERS (elf_i960_reloc_type)
      RELOC_NUMBER (R_960_OPTCALL,   5)
      RELOC_NUMBER (R_960_OPTCALLX,  6)
      RELOC_NUMBER (R_960_OPTCALLXA, 7)
-     EMPTY_RELOC (R_960_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_960_max)
 
 #endif /* _ELF_I960_H */
diff --git a/gnu/usr.bin/binutils/include/elf/ia64.h b/gnu/usr.bin/binutils/include/elf/ia64.h
new file mode 100644
index 00000000000..edfc7c5b532
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/elf/ia64.h
@@ -0,0 +1,192 @@
+/* IA-64 ELF support for BFD.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+
+#ifndef _ELF_IA64_H
+#define _ELF_IA64_H
+
+/* Bits in the e_flags field of the Elf64_Ehdr:  */
+
+#define EF_IA_64_MASKOS	 0x0000000f	/* os-specific flags */
+#define EF_IA_64_ARCH	 0xff000000	/* arch. version mask */
+
+/* ??? These four definitions are not part of the SVR4 ABI.
+   They were present in David's initial code drop, so it is probable
+   that they are used by HP/UX.  */
+#define EF_IA_64_TRAPNIL (1 << 0)	/* trap NIL pointer dereferences */
+#define EF_IA_64_EXT	 (1 << 2)	/* program uses arch. extensions */
+#define EF_IA_64_BE	 (1 << 3)	/* PSR BE bit set (big-endian) */
+#define EFA_IA_64_EAS2_3 0x23000000	/* ia64 EAS 2.3 */
+
+#define EF_IA_64_ABI64		    (1 << 4) /* 64-bit ABI */
+/* Not used yet.  */
+#define EF_IA_64_REDUCEDFP	    (1 << 5) /* Only FP6-FP11 used.  */
+#define EF_IA_64_CONS_GP	    (1 << 6) /* gp as program wide constant. */
+#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptors. */
+/* Not used yet.  */
+#define EF_IA_64_ABSOLUTE	    (1 << 8) /* Load at absolute addresses.  */
+
+#define ELF_STRING_ia64_archext		".IA_64.archext"
+#define ELF_STRING_ia64_pltoff		".IA_64.pltoff"
+#define ELF_STRING_ia64_unwind		".IA_64.unwind"
+#define ELF_STRING_ia64_unwind_info	".IA_64.unwind_info"
+#define ELF_STRING_ia64_unwind_once	".gnu.linkonce.ia64unw."
+#define ELF_STRING_ia64_unwind_info_once ".gnu.linkonce.ia64unwi."
+
+/* Bits in the sh_flags field of Elf64_Shdr:  */
+
+#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
+#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
+
+/* Possible values for sh_type in Elf64_Shdr: */
+
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0)	/* extension bits */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1)	/* unwind bits */
+
+/* Bits in the p_flags field of Elf64_Phdr:  */
+
+#define PF_IA_64_NORECOV	0x80000000
+
+/* Possible values for p_type in Elf64_Phdr:  */
+
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
+#define PT_IA_64_UNWIND 	(PT_LOPROC + 1)	/* ia64 unwind bits */
+
+/* Possible values for d_tag in Elf64_Dyn:  */
+
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+
+/* ia64-specific relocation types: */
+
+/* Relocs apply to specific instructions within a bundle.  The least
+   significant 2 bits of the address indicate which instruction in the
+   bundle the reloc refers to (0=first slot, 1=second slow, 2=third
+   slot, 3=undefined) and the remaining bits give the address of the
+   bundle (16 byte aligned).
+
+   The top 5 bits of the reloc code specifies the expression type, the
+   low 3 bits the format of the data word being relocated.  */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_ia64_reloc_type)
+  RELOC_NUMBER (R_IA64_NONE, 0x00)	/* none */
+
+  RELOC_NUMBER (R_IA64_IMM14, 0x21)	/* symbol + addend, add imm14 */
+  RELOC_NUMBER (R_IA64_IMM22, 0x22)	/* symbol + addend, add imm22 */
+  RELOC_NUMBER (R_IA64_IMM64, 0x23)	/* symbol + addend, mov imm64 */
+  RELOC_NUMBER (R_IA64_DIR32MSB, 0x24)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_DIR32LSB, 0x25)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_DIR64MSB, 0x26)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_DIR64LSB, 0x27)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_GPREL22, 0x2a)	/* @gprel(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_GPREL64I, 0x2b)	/* @gprel(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF22, 0x32)	/* @ltoff(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF64I, 0x33)	/* @ltoff(sym+add), mov imm64 */
+
+  RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a)	/* @pltoff(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b)	/* @pltoff(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_FPTR64I, 0x43)	/* @fptr(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44)	/* @fptr(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45)	/* @fptr(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46)	/* @fptr(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47)	/* @fptr(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_PCREL60B, 0x48)	/* @pcrel(sym+add), brl */
+  RELOC_NUMBER (R_IA64_PCREL21B, 0x49)	/* @pcrel(sym+add), ptb, call */
+  RELOC_NUMBER (R_IA64_PCREL21M, 0x4a)	/* @pcrel(sym+add), chk.s */
+  RELOC_NUMBER (R_IA64_PCREL21F, 0x4b)	/* @pcrel(sym+add), fchkf */
+  RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB */
+
+  RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_REL32MSB, 0x6c)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL32LSB, 0x6d)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL64MSB, 0x6e)	/* data 8 + REL */
+  RELOC_NUMBER (R_IA64_REL64LSB, 0x6f)	/* data 8 + REL */
+
+  RELOC_NUMBER (R_IA64_LTV32MSB, 0x74)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_LTV32LSB, 0x75)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_LTV64MSB, 0x76)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_LTV64LSB, 0x77)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_PCREL21BI, 0x79)	/* @pcrel(sym+add), ptb, call */
+  RELOC_NUMBER (R_IA64_PCREL22, 0x7a)	/* @pcrel(sym+add), imm22 */
+  RELOC_NUMBER (R_IA64_PCREL64I, 0x7b)	/* @pcrel(sym+add), imm64 */
+
+  RELOC_NUMBER (R_IA64_IPLTMSB, 0x80)	/* dynamic reloc, imported PLT, MSB */
+  RELOC_NUMBER (R_IA64_IPLTLSB, 0x81)	/* dynamic reloc, imported PLT, LSB */
+  RELOC_NUMBER (R_IA64_COPY, 0x84)	/* dynamic reloc, data copy */
+  RELOC_NUMBER (R_IA64_LTOFF22X, 0x86)  /* LTOFF22, relaxable.  */
+  RELOC_NUMBER (R_IA64_LDXMOV, 0x87)	/* Use of LTOFF22X.  */
+
+  RELOC_NUMBER (R_IA64_TPREL14, 0x91)	 /* @tprel(sym+add), add imm14 */
+  RELOC_NUMBER (R_IA64_TPREL22, 0x92)	 /* @tprel(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_TPREL64I, 0x93)	 /* @tprel(sym+add), add imm64 */
+  RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */
+
+  RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */
+  RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm22 */
+
+  RELOC_NUMBER (R_IA64_DTPREL14, 0xb1)    /* @dtprel(sym+add), imm14 */
+  RELOC_NUMBER (R_IA64_DTPREL22, 0xb2)    /* @dtprel(sym+add), imm22 */
+  RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3)   /* @dtprel(sym+add), imm64 */
+  RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm22 */
+
+  FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba)
+END_RELOC_NUMBERS (R_IA64_max)
+
+#endif /* _ELF_IA64_H */
diff --git a/gnu/usr.bin/binutils/include/elf/m32r.h b/gnu/usr.bin/binutils/include/elf/m32r.h
index a12ae16aea5..2cb308d3a94 100644
--- a/gnu/usr.bin/binutils/include/elf/m32r.h
+++ b/gnu/usr.bin/binutils/include/elf/m32r.h
@@ -1,5 +1,5 @@
 /* M32R ELF support for BFD.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -37,8 +37,7 @@ START_RELOC_NUMBERS (elf_m32r_reloc_type)
   RELOC_NUMBER (R_M32R_SDA16, 10)
   RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)
   RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12)
-  EMPTY_RELOC  (R_M32R_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_M32R_max)
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/gnu/usr.bin/binutils/include/elf/m68hc11.h b/gnu/usr.bin/binutils/include/elf/m68hc11.h
new file mode 100644
index 00000000000..0f9546d7404
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/elf/m68hc11.h
@@ -0,0 +1,42 @@
+/* m68hc11 & m68hc12 ELF support for BFD.
+   Copyright 1999, 2000 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_M68HC11_H
+#define _ELF_M68HC11_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_m68hc11_reloc_type)
+  RELOC_NUMBER (R_M68HC11_NONE, 0)
+  RELOC_NUMBER (R_M68HC11_8, 1)
+  RELOC_NUMBER (R_M68HC11_HI8, 2)
+  RELOC_NUMBER (R_M68HC11_LO8, 3)
+  RELOC_NUMBER (R_M68HC11_PCREL_8, 4)
+  RELOC_NUMBER (R_M68HC11_16, 5)
+  RELOC_NUMBER (R_M68HC11_32, 6)
+  RELOC_NUMBER (R_M68HC11_3B, 7)
+  RELOC_NUMBER (R_M68HC11_PCREL_16, 8)
+
+     /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9)
+  RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10)
+END_RELOC_NUMBERS (R_M68HC11_max)
+
+#endif
diff --git a/gnu/usr.bin/binutils/include/elf/m68k.h b/gnu/usr.bin/binutils/include/elf/m68k.h
index e2d51ef4a90..03bf465e2b0 100644
--- a/gnu/usr.bin/binutils/include/elf/m68k.h
+++ b/gnu/usr.bin/binutils/include/elf/m68k.h
@@ -1,5 +1,5 @@
 /* MC68k ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -50,8 +50,7 @@ START_RELOC_NUMBERS (elf_m68k_reloc_type)
   /* These are GNU extensions to enable C++ vtable garbage collection.  */
   RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23)
   RELOC_NUMBER (R_68K_GNU_VTENTRY, 24)
-  EMPTY_RELOC  (R_68K_max)   
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_68K_max)
 
 #define EF_CPU32    0x00810000
 
diff --git a/gnu/usr.bin/binutils/include/elf/mcore.h b/gnu/usr.bin/binutils/include/elf/mcore.h
index 62a88c9093e..387a57d4517 100644
--- a/gnu/usr.bin/binutils/include/elf/mcore.h
+++ b/gnu/usr.bin/binutils/include/elf/mcore.h
@@ -1,5 +1,5 @@
 /* Motorola MCore support for BFD.
-   Copyright (C) 1995, 1999 Free Software Foundation, Inc.
+   Copyright 1995, 1999, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -38,8 +38,7 @@ START_RELOC_NUMBERS (elf_mcore_reloc_type)
   RELOC_NUMBER (R_MCORE_COPY, 10)
   RELOC_NUMBER (R_MCORE_GLOB_DAT, 11)
   RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12)
-  EMPTY_RELOC  (R_MCORE_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_MCORE_max)
 
 /* Section Attributes.  */
 #define SHF_MCORE_NOREAD	0x80000000
diff --git a/gnu/usr.bin/binutils/include/elf/mn10200.h b/gnu/usr.bin/binutils/include/elf/mn10200.h
index 5e29e0ad211..1dfade5ccd0 100644
--- a/gnu/usr.bin/binutils/include/elf/mn10200.h
+++ b/gnu/usr.bin/binutils/include/elf/mn10200.h
@@ -1,5 +1,5 @@
 /* MN10200 ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -34,6 +34,6 @@ START_RELOC_NUMBERS (elf_mn10200_reloc_type)
   RELOC_NUMBER (R_MN10200_PCREL8, 5)
   RELOC_NUMBER (R_MN10200_PCREL16, 6)
   RELOC_NUMBER (R_MN10200_PCREL24, 7)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_MN10200_max)
 
 #endif /* _ELF_MN10200_H */
diff --git a/gnu/usr.bin/binutils/include/elf/mn10300.h b/gnu/usr.bin/binutils/include/elf/mn10300.h
index 1b90a137961..e10be900a40 100644
--- a/gnu/usr.bin/binutils/include/elf/mn10300.h
+++ b/gnu/usr.bin/binutils/include/elf/mn10300.h
@@ -1,5 +1,5 @@
 /* MN10300 ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -36,8 +36,7 @@ START_RELOC_NUMBERS (elf_mn10300_reloc_type)
   RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7)
   RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8)
   RELOC_NUMBER (R_MN10300_24, 9)
-  EMPTY_RELOC  (R_MN10300_MAX)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_MN10300_MAX)
 
 /* Machine variant if we know it.  This field was invented at Cygnus,
    but it is hoped that other vendors will adopt it.  If some standard
diff --git a/gnu/usr.bin/binutils/include/elf/pj.h b/gnu/usr.bin/binutils/include/elf/pj.h
index 6bb8306523e..586fd3a3608 100644
--- a/gnu/usr.bin/binutils/include/elf/pj.h
+++ b/gnu/usr.bin/binutils/include/elf/pj.h
@@ -1,5 +1,5 @@
 /* picoJava ELF support for BFD.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright 1999, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -35,8 +35,7 @@ START_RELOC_NUMBERS (elf_pj_reloc_type)
   RELOC_NUMBER (R_PJ_CODE_HI16, 14)
   RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15)
   RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16)
-  EMPTY_RELOC (R_PJ_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_PJ_max)
 
 #define EF_PICOJAVA_ARCH     0x0000000f
 #define EF_PICOJAVA_NEWCALLS 0x00000010
diff --git a/gnu/usr.bin/binutils/include/elf/reloc-macros.h b/gnu/usr.bin/binutils/include/elf/reloc-macros.h
index 42174caeeae..9ad346c9f3d 100644
--- a/gnu/usr.bin/binutils/include/elf/reloc-macros.h
+++ b/gnu/usr.bin/binutils/include/elf/reloc-macros.h
@@ -1,5 +1,5 @@
 /* Generic relocation support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -27,20 +27,20 @@
    	START_RELOC_NUMBERS (foo)
    	    RELOC_NUMBER (R_foo_NONE,    0)
    	    RELOC_NUMBER (R_foo_32,      1)
-   	    FAKE_RELOC   (R_foo_illegal, 2)
-   	    EMPTY_RELOC  (R_foo_max)
-   	END_RELOC_NUMBERS
+   	    EMPTY_RELOC  (R_foo_good)
+   	    FAKE_RELOC   (R_foo_illegal, 9)
+   	END_RELOC_NUMBERS (R_foo_count)
 
    Then the following will be produced by default (ie if
    RELOC_MACROS_GEN_FUNC is *not* defined).
 
    	enum foo
 	{
-	  foo = -1,
    	  R_foo_NONE = 0,
    	  R_foo_32 = 1,
-   	  R_foo_illegal = 2,
-   	  R_foo_max
+	  R_foo_good,
+   	  R_foo_illegal = 9,
+   	  R_foo_count
    	};
 
    If RELOC_MACROS_GEN_FUNC *is* defined, then instead the
@@ -59,7 +59,7 @@
    	   }
    	}
    */
-   
+
 #ifndef _RELOC_MACROS_H
 #define _RELOC_MACROS_H
 
@@ -78,16 +78,16 @@ name (rtype)							\
   switch (rtype)						\
   {
 
-#ifdef __STDC__					  
+#if defined (__STDC__) || defined (ALMOST_STDC)
 #define RELOC_NUMBER(name, number)  case number : return #name ;
 #else
 #define RELOC_NUMBER(name, number)  case number : return "name" ;
 #endif
 
-#define FAKE_RELOC(name, number)    
+#define FAKE_RELOC(name, number)
 #define EMPTY_RELOC(name)
-					  
-#define END_RELOC_NUMBERS	\
+
+#define END_RELOC_NUMBERS(name)	\
     default: return NULL;	\
   }				\
 }
@@ -95,21 +95,11 @@ name (rtype)							\
 
 #else /* Default to generating enum.  */
 
-/* Some compilers cannot cope with an enum that ends with a trailing
-   comma, so START_RELOC_NUMBERS creates a fake reloc entry, (initialised
-   to -1 so that the first real entry will still default to 0).  Further
-   entries then prepend a comma to their definitions, creating a list
-   of enumerator entries that will satisfy these compilers.  */
-#ifdef __STDC__
-#define START_RELOC_NUMBERS(name)   enum name { _##name = -1
-#else
-#define START_RELOC_NUMBERS(name)   enum name { name = -1
-#endif
-						
-#define RELOC_NUMBER(name, number)  , name = number
-#define FAKE_RELOC(name, number)    , name = number 
-#define EMPTY_RELOC(name)           , name 
-#define END_RELOC_NUMBERS           };
+#define START_RELOC_NUMBERS(name)   enum name {
+#define RELOC_NUMBER(name, number)  name = number,
+#define FAKE_RELOC(name, number)    name = number,
+#define EMPTY_RELOC(name)           name,
+#define END_RELOC_NUMBERS(name)     name };
 
 #endif
 
diff --git a/gnu/usr.bin/binutils/include/elf/sh.h b/gnu/usr.bin/binutils/include/elf/sh.h
index faee5099435..700ca3ec9ae 100644
--- a/gnu/usr.bin/binutils/include/elf/sh.h
+++ b/gnu/usr.bin/binutils/include/elf/sh.h
@@ -1,5 +1,5 @@
 /* SH ELF support for BFD.
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 2000 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -76,7 +76,18 @@ START_RELOC_NUMBERS (elf_sh_reloc_type)
   RELOC_NUMBER (R_SH_SWITCH8, 33)
   RELOC_NUMBER (R_SH_GNU_VTINHERIT, 34)
   RELOC_NUMBER (R_SH_GNU_VTENTRY, 35)
-  EMPTY_RELOC (R_SH_max)
-END_RELOC_NUMBERS
+  RELOC_NUMBER (R_SH_LOOP_START, 36)
+  RELOC_NUMBER (R_SH_LOOP_END, 37)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_2, 38)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_2, 159)
+  RELOC_NUMBER (R_SH_GOT32, 160)
+  RELOC_NUMBER (R_SH_PLT32, 161)
+  RELOC_NUMBER (R_SH_COPY, 162)
+  RELOC_NUMBER (R_SH_GLOB_DAT, 163)
+  RELOC_NUMBER (R_SH_JMP_SLOT, 164)
+  RELOC_NUMBER (R_SH_RELATIVE, 165)
+  RELOC_NUMBER (R_SH_GOTOFF, 166)
+  RELOC_NUMBER (R_SH_GOTPC, 167)
+END_RELOC_NUMBERS (R_SH_max)
 
 #endif
diff --git a/gnu/usr.bin/binutils/include/elf/v850.h b/gnu/usr.bin/binutils/include/elf/v850.h
index d443b7fdc0d..62b9541e8e9 100644
--- a/gnu/usr.bin/binutils/include/elf/v850.h
+++ b/gnu/usr.bin/binutils/include/elf/v850.h
@@ -1,5 +1,5 @@
 /* V850 ELF support for BFD.
-   Copyright (C) 1997 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2000 Free Software Foundation, Inc.
    Created by Michael Meissner, Cygnus Support <meissner@cygnus.com>
 
 This file is part of BFD, the Binary File Descriptor library.
@@ -67,19 +67,15 @@ START_RELOC_NUMBERS (v850_reloc_type)
      RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14)		/* For sst.h, sld.h */
      RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15)		/* For sst.b, sld.b */
      RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16)		/* For set1, clr1, not1, tst1, movea, movhi */
-/* CYGNUS LOCAL v850e */
      RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17)		/* For sld.hu */
      RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18)		/* For sld.bu */
      RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19)	/* For ld.bu */
      RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20)	/* For ld.bu */
      RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21)		/* For callt */
      RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22)	/* For callt */
-/* END CYGNUS LOCAL */
      RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23)
      RELOC_NUMBER (R_V850_GNU_VTENTRY, 24)
-
-     EMPTY_RELOC (R_V850_max)
-END_RELOC_NUMBERS
+END_RELOC_NUMBERS (R_V850_max)
 
 
 /* Processor specific section indices.  These sections do not actually
diff --git a/gnu/usr.bin/binutils/include/elf/x86-64.h b/gnu/usr.bin/binutils/include/elf/x86-64.h
new file mode 100644
index 00000000000..a4da0a37522
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/elf/x86-64.h
@@ -0,0 +1,46 @@
+/* x86_64 ELF support for BFD.
+   Copyright (C) 2000 Free Software Foundation, Inc.
+   Contributed by Jan Hubicka <jh@suse.cz>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_X86_64_H
+#define _ELF_X86_64_H
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_x86_64_reloc_type)
+     RELOC_NUMBER (R_X86_64_NONE,     0)      /* No reloc */
+     RELOC_NUMBER (R_X86_64_64,               1)      /* Direct 64 bit  */
+     RELOC_NUMBER (R_X86_64_PC32,     2)      /* PC relative 32 bit signed */
+     RELOC_NUMBER (R_X86_64_GOT32,    3)      /* 32 bit GOT entry */
+     RELOC_NUMBER (R_X86_64_PLT32,    4)      /* 32 bit PLT address */
+     RELOC_NUMBER (R_X86_64_COPY,     5)      /* Copy symbol at runtime */
+     RELOC_NUMBER (R_X86_64_GLOB_DAT, 6)      /* Create GOT entry */
+     RELOC_NUMBER (R_X86_64_JUMP_SLOT,        7)      /* Create PLT entry */
+     RELOC_NUMBER (R_X86_64_RELATIVE, 8)      /* Adjust by program base */
+     RELOC_NUMBER (R_X86_64_GOTPCREL, 9)      /* 32 bit signed pc relative
+                                                 offset to GOT */
+     RELOC_NUMBER (R_X86_64_32,               10)     /* Direct 32 bit zero extended */
+     RELOC_NUMBER (R_X86_64_32S,              11)     /* Direct 32 bit sign extended */
+     RELOC_NUMBER (R_X86_64_16,               12)     /* Direct 16 bit zero extended */
+     RELOC_NUMBER (R_X86_64_PC16,     13)     /* 16 bit sign extended pc relative*/
+     RELOC_NUMBER (R_X86_64_8,                14)     /* Direct 8 bit sign extended */
+     RELOC_NUMBER (R_X86_64_PC8,              15)     /* 8 bit sign extended pc relative*/
+END_RELOC_NUMBERS (R_X86_64_max)
+
+#endif
diff --git a/gnu/usr.bin/binutils/include/hashtab.h b/gnu/usr.bin/binutils/include/hashtab.h
index 5fe239391ff..a577c5e2afe 100644
--- a/gnu/usr.bin/binutils/include/hashtab.h
+++ b/gnu/usr.bin/binutils/include/hashtab.h
@@ -1,5 +1,5 @@
 /* An expandable hash tables datatype.  
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
    Contributed by Vladimir Makarov (vmakarov@cygnus.com).
 
 This program is free software; you can redistribute it and/or modify
@@ -38,10 +38,13 @@ extern "C" {
 
 #include <ansidecl.h>
 
+/* The type for a hash code.  */
+typedef unsigned int hashval_t;
+
 /* Callback function pointer types.  */
 
 /* Calculate hash of a table entry.  */
-typedef unsigned int (*htab_hash) PARAMS ((const void *));
+typedef hashval_t (*htab_hash) PARAMS ((const void *));
 
 /* Compare a table entry with a possible entry.  The entry already in
    the table always comes first, so the second element can be of a
@@ -77,7 +80,7 @@ struct htab
   htab_del del_f;
 
   /* Table itself.  */
-  void **entries;
+  PTR *entries;
 
   /* Current size (in entries) of the hash table */
   size_t size;
@@ -95,23 +98,38 @@ struct htab
   /* The following member is used for debugging.  Its value is number
      of collisions fixed for time of work with the hash table. */
   unsigned int collisions;
+
+  /* This is non-zero if we are allowed to return NULL for function calls
+     that allocate memory.  */
+  int return_allocation_failure;
 };
 
 typedef struct htab *htab_t;
 
+/* An enum saying whether we insert into the hash table or not.  */
+enum insert_option {NO_INSERT, INSERT};
+
 /* The prototypes of the package functions. */
 
 extern htab_t	htab_create	PARAMS ((size_t, htab_hash,
 					 htab_eq, htab_del));
+
+/* This function is like htab_create, but may return NULL if memory
+   allocation fails, and also signals that htab_find_slot_with_hash and
+   htab_find_slot are allowed to return NULL when inserting.  */
+extern htab_t	htab_try_create	PARAMS ((size_t, htab_hash,
+					 htab_eq, htab_del));
 extern void	htab_delete	PARAMS ((htab_t));
 extern void	htab_empty	PARAMS ((htab_t));
 
-extern void    *htab_find	PARAMS ((htab_t, const void *));
-extern void   **htab_find_slot	PARAMS ((htab_t, const void *, int));
-extern void    *htab_find_with_hash		PARAMS ((htab_t, const void *,
-							 unsigned int));
-extern void   **htab_find_slot_with_hash	PARAMS ((htab_t, const void *,
-							 unsigned int, int));
+extern PTR	htab_find	PARAMS ((htab_t, const void *));
+extern PTR     *htab_find_slot	PARAMS ((htab_t, const void *,
+					 enum insert_option));
+extern PTR	htab_find_with_hash	  PARAMS ((htab_t, const void *,
+						   hashval_t));
+extern PTR     *htab_find_slot_with_hash  PARAMS ((htab_t, const void *,
+						   hashval_t,
+						   enum insert_option));
 extern void	htab_clear_slot	PARAMS ((htab_t, void **));
 extern void	htab_remove_elt	PARAMS ((htab_t, void *));
 
@@ -121,6 +139,12 @@ extern size_t	htab_size	PARAMS ((htab_t));
 extern size_t	htab_elements	PARAMS ((htab_t));
 extern double	htab_collisions	PARAMS ((htab_t));
 
+/* A hash function for pointers.  */
+extern htab_hash htab_hash_pointer;
+
+/* An equality function for pointers.  */
+extern htab_eq htab_eq_pointer;
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/gnu/usr.bin/binutils/include/md5.h b/gnu/usr.bin/binutils/include/md5.h
new file mode 100644
index 00000000000..ad51f19877a
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/md5.h
@@ -0,0 +1,142 @@
+/* md5.h - Declaration of functions and data types used for MD5 sum
+   computing library functions.
+   Copyright 1995, 1996, 2000 Free Software Foundation, Inc.
+   NOTE: The canonical source of this file is maintained with the GNU C
+   Library.  Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _MD5_H
+#define _MD5_H 1
+
+#include <stdio.h>
+
+#if defined HAVE_LIMITS_H || _LIBC
+# include <limits.h>
+#endif
+
+/* The following contortions are an attempt to use the C preprocessor
+   to determine an unsigned integral type that is 32 bits wide.  An
+   alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but
+   doing that would require that the configure script compile and *run*
+   the resulting executable.  Locally running cross-compiled executables
+   is usually not possible.  */
+
+#ifdef _LIBC
+# include <sys/types.h>
+typedef u_int32_t md5_uint32;
+#else
+#  define INT_MAX_32_BITS 2147483647
+
+/* If UINT_MAX isn't defined, assume it's a 32-bit type.
+   This should be valid for all systems GNU cares about because
+   that doesn't include 16-bit systems, and only modern systems
+   (that certainly have <limits.h>) have 64+-bit integral types.  */
+
+# ifndef INT_MAX
+#  define INT_MAX INT_MAX_32_BITS
+# endif
+
+# if INT_MAX == INT_MAX_32_BITS
+   typedef unsigned int md5_uint32;
+# else
+#  if SHRT_MAX == INT_MAX_32_BITS
+    typedef unsigned short md5_uint32;
+#  else
+#   if LONG_MAX == INT_MAX_32_BITS
+     typedef unsigned long md5_uint32;
+#   else
+     /* The following line is intended to evoke an error.
+        Using #error is not portable enough.  */
+     "Cannot determine unsigned 32-bit data type."
+#   endif
+#  endif
+# endif
+#endif
+
+#undef __P
+#if defined (__STDC__) && __STDC__
+#define	__P(x) x
+#else
+#define	__P(x) ()
+#endif
+
+/* Structure to save state of computation between the single steps.  */
+struct md5_ctx
+{
+  md5_uint32 A;
+  md5_uint32 B;
+  md5_uint32 C;
+  md5_uint32 D;
+
+  md5_uint32 total[2];
+  md5_uint32 buflen;
+  char buffer[128];
+};
+
+/*
+ * The following three functions are build up the low level used in
+ * the functions `md5_stream' and `md5_buffer'.
+ */
+
+/* Initialize structure containing state of computation.
+   (RFC 1321, 3.3: Step 3)  */
+extern void md5_init_ctx __P ((struct md5_ctx *ctx));
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is necessary that LEN is a multiple of 64!!! */
+extern void md5_process_block __P ((const void *buffer, size_t len,
+				    struct md5_ctx *ctx));
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is NOT required that LEN is a multiple of 64.  */
+extern void md5_process_bytes __P ((const void *buffer, size_t len,
+				    struct md5_ctx *ctx));
+
+/* Process the remaining bytes in the buffer and put result from CTX
+   in first 16 bytes following RESBUF.  The result is always in little
+   endian byte order, so that a byte-wise output yields to the wanted
+   ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF is correctly
+   aligned for a 32 bits value.  */
+extern void *md5_finish_ctx __P ((struct md5_ctx *ctx, void *resbuf));
+
+
+/* Put result from CTX in first 16 bytes following RESBUF.  The result is
+   always in little endian byte order, so that a byte-wise output yields
+   to the wanted ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF is correctly
+   aligned for a 32 bits value.  */
+extern void *md5_read_ctx __P ((const struct md5_ctx *ctx, void *resbuf));
+
+
+/* Compute MD5 message digest for bytes read from STREAM.  The
+   resulting message digest number will be written into the 16 bytes
+   beginning at RESBLOCK.  */
+extern int md5_stream __P ((FILE *stream, void *resblock));
+
+/* Compute MD5 message digest for LEN bytes beginning at BUFFER.  The
+   result is always in little endian byte order, so that a byte-wise
+   output yields to the wanted ASCII representation of the message
+   digest.  */
+extern void *md5_buffer __P ((const char *buffer, size_t len, void *resblock));
+
+#endif
diff --git a/gnu/usr.bin/binutils/include/opcode/arc.h b/gnu/usr.bin/binutils/include/opcode/arc.h
index a1e0ca15263..81e5bd847dc 100644
--- a/gnu/usr.bin/binutils/include/opcode/arc.h
+++ b/gnu/usr.bin/binutils/include/opcode/arc.h
@@ -1,93 +1,110 @@
 /* Opcode table for the ARC.
-   Copyright 1994, 1995, 1997 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
-This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
-the GNU Binutils.
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
 
-GAS/GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
 
-GAS/GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-GNU General Public License for more details.
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING.	If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-You should have received a copy of the GNU General Public License
-along with GAS or GDB; see the file COPYING.	If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
 
 /* List of the various cpu types.
    The tables currently use bit masks to say whether the instruction or
    whatever is supported by a particular cpu.  This lets us have one entry
    apply to several cpus.
 
-   This duplicates bfd_mach_arc_xxx.  For now I wish to isolate this from bfd
-   and bfd from this.  Also note that these numbers are bit values as we want
-   to allow for things available on more than one ARC (but not necessarily all
-   ARCs).  */
-
-/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
-   The cpu type is treated independently of endianness.
-   The complete `mach' number includes endianness.
+   The `base' cpu must be 0. The cpu type is treated independently of
+   endianness. The complete `mach' number includes endianness.
    These values are internal to opcodes/bfd/binutils/gas.  */
-#define ARC_MACH_BASE 0
-#define ARC_MACH_UNUSED1 1
-#define ARC_MACH_UNUSED2 2
-#define ARC_MACH_UNUSED4 4
+#define ARC_MACH_5 0
+#define ARC_MACH_6 1
+#define ARC_MACH_7 2
+#define ARC_MACH_8 4
+
 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
-#define ARC_MACH_BIG 8
+#define ARC_MACH_BIG 16
 
 /* Mask of number of bits necessary to record cpu type.  */
-#define ARC_MACH_CPU_MASK 7
+#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
+
 /* Mask of number of bits necessary to record cpu type + endianness.  */
-#define ARC_MACH_MASK 15
+#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
 
 /* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+
 typedef unsigned int arc_insn;
 
 struct arc_opcode {
-  char *syntax;			/* syntax of insn */
-  unsigned long mask, value;	/* recognize insn if (op&mask)==value */
-  int flags;			/* various flag bits */
+  char *syntax;              /* syntax of insn  */
+  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
+  int flags;                 /* various flag bits  */
 
 /* Values for `flags'.  */
 
 /* Return CPU number, given flag bits.  */
 #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+
 /* Return MACH number, given flag bits.  */
 #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+
 /* First opcode flag bit available after machine mask.  */
-#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0)
+#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
+
 /* This insn is a conditional branch.  */
 #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
-
-  /* These values are used to optimize assembly and disassembly.  Each insn is
-     on a list of related insns (same first letter for assembly, same insn code
-     for disassembly).  */
-  struct arc_opcode *next_asm;	/* Next instruction to try during assembly.  */
-  struct arc_opcode *next_dis;	/* Next instruction to try during disassembly.  */
-
-  /* Macros to create the hash values for the lists.  */
+#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
+#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
+#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
+#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
+#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
+#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
+
+#define I(x) (((x) & 31) << 27)
+#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
+#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
+#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
+#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
+
+/* These values are used to optimize assembly and disassembly.  Each insn
+   is on a list of related insns (same first letter for assembly, same
+   insn code for disassembly).  */
+
+  struct arc_opcode *next_asm;	/* Next instr to try during assembly.  */
+  struct arc_opcode *next_dis;	/* Next instr to try during disassembly.  */
+
+/* Macros to create the hash values for the lists.  */
 #define ARC_HASH_OPCODE(string) \
   ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
 #define ARC_HASH_ICODE(insn) \
   ((unsigned int) (insn) >> 27)
 
-  /* Macros to access `next_asm', `next_dis' so users needn't care about the
-     underlying mechanism.  */
+ /* Macros to access `next_asm', `next_dis' so users needn't care about the
+    underlying mechanism.  */
 #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
 #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
 };
 
+/* this is an "insert at front" linked list per Metaware spec
+   that new definitions override older ones.  */
+struct arc_opcode *arc_ext_opcodes;
+
 struct arc_operand_value {
-  char *name;			/* eg: "eq" */
-  short value;			/* eg: 1 */
-  unsigned char type;		/* index into `arc_operands' */
-  unsigned char flags;		/* various flag bits */
+  char *name;          /* eg: "eq"  */
+  short value;         /* eg: 1  */
+  unsigned char type;  /* index into `arc_operands'  */
+  unsigned char flags; /* various flag bits  */
 
 /* Values for `flags'.  */
 
@@ -97,18 +114,23 @@ struct arc_operand_value {
 #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
 };
 
+struct arc_ext_operand_value {
+  struct arc_ext_operand_value *next;
+  struct arc_operand_value operand;
+} *arc_ext_operands;
+
 struct arc_operand {
-  /* One of the insn format chars.  */
+/* One of the insn format chars.  */
   unsigned char fmt;
 
-  /* The number of bits in the operand (may be unused for a modifier).  */
+/* The number of bits in the operand (may be unused for a modifier).  */
   unsigned char bits;
 
-  /* How far the operand is left shifted in the instruction, or
-     the modifier's flag bit (may be unused for a modifier.  */
+/* How far the operand is left shifted in the instruction, or
+   the modifier's flag bit (may be unused for a modifier.  */
   unsigned char shift;
 
-  /* Various flag bits.  */
+/* Various flag bits.  */
   int flags;
 
 /* Values for `flags'.  */
@@ -150,6 +172,19 @@ struct arc_operand {
    in special ways.  */
 #define ARC_OPERAND_FAKE 0x100
 
+/* separate flags operand for j and jl instructions  */
+#define ARC_OPERAND_JUMPFLAGS 0x200
+
+/* allow warnings and errors to be issued after call to insert_xxxxxx  */
+#define ARC_OPERAND_WARN  0x400
+#define ARC_OPERAND_ERROR 0x800
+
+/* this is a load operand */
+#define ARC_OPERAND_LOAD  0x8000
+
+/* this is a store operand */
+#define ARC_OPERAND_STORE 0x10000
+
 /* Modifier values.  */
 /* A dot is required before a suffix.  Eg: .le  */
 #define ARC_MOD_DOT 0x1000
@@ -166,52 +201,57 @@ struct arc_operand {
 /* Non-zero if the operand type is really a modifier.  */
 #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
 
-  /* Insertion function.  This is used by the assembler.  To insert an
-     operand value into an instruction, check this field.
-
-     If it is NULL, execute
-         i |= (p & ((1 << o->bits) - 1)) << o->shift;
-     (I is the instruction which we are filling in, O is a pointer to
-     this structure, and OP is the opcode value; this assumes twos
-     complement arithmetic).
-
-     If this field is not NULL, then simply call it with the
-     instruction and the operand value.  It will return the new value
-     of the instruction.  If the ERRMSG argument is not NULL, then if
-     the operand value is illegal, *ERRMSG will be set to a warning
-     string (the operand will be inserted in any case).  If the
-     operand value is legal, *ERRMSG will be unchanged.
-
-     REG is non-NULL when inserting a register value.  */
+/* enforce read/write only register restrictions  */
+#define ARC_REGISTER_READONLY    0x01
+#define ARC_REGISTER_WRITEONLY   0x02
+#define ARC_REGISTER_NOSHORT_CUT 0x04
+
+/* Insertion function.  This is used by the assembler.  To insert an
+   operand value into an instruction, check this field.
+
+   If it is NULL, execute
+   i |= (p & ((1 << o->bits) - 1)) << o->shift;
+   (I is the instruction which we are filling in, O is a pointer to
+   this structure, and OP is the opcode value; this assumes twos
+   complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction and the operand value.  It will return the new value
+   of the instruction.  If the ERRMSG argument is not NULL, then if
+   the operand value is illegal, *ERRMSG will be set to a warning
+   string (the operand will be inserted in any case).  If the
+   operand value is legal, *ERRMSG will be unchanged.
+
+   REG is non-NULL when inserting a register value.  */
 
   arc_insn (*insert) PARAMS ((arc_insn insn,
 			      const struct arc_operand *operand, int mods,
 			      const struct arc_operand_value *reg, long value,
 			      const char **errmsg));
 
-  /* Extraction function.  This is used by the disassembler.  To
-     extract this operand type from an instruction, check this field.
-
-     If it is NULL, compute
-         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
-	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
-	     && (op & (1 << (o->bits - 1))) != 0)
-	   op -= 1 << o->bits;
-     (I is the instruction, O is a pointer to this structure, and OP
-     is the result; this assumes twos complement arithmetic).
-
-     If this field is not NULL, then simply call it with the
-     instruction value.  It will return the value of the operand.  If
-     the INVALID argument is not NULL, *INVALID will be set to
-     non-zero if this operand type can not actually be extracted from
-     this operand (i.e., the instruction does not match).  If the
-     operand is valid, *INVALID will not be changed.
-
-     INSN is a pointer to an array of two `arc_insn's.  The first element is
-     the insn, the second is the limm if present.
-
-     Operands that have a printable form like registers and suffixes have
-     their struct arc_operand_value pointer stored in OPVAL.  */
+/* Extraction function.  This is used by the disassembler.  To
+   extract this operand type from an instruction, check this field.
+   
+   If it is NULL, compute
+     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+     if ((o->flags & ARC_OPERAND_SIGNED) != 0
+          && (op & (1 << (o->bits - 1))) != 0)
+       op -= 1 << o->bits;
+   (I is the instruction, O is a pointer to this structure, and OP
+   is the result; this assumes twos complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction value.  It will return the value of the operand.  If
+   the INVALID argument is not NULL, *INVALID will be set to
+   non-zero if this operand type can not actually be extracted from
+   this operand (i.e., the instruction does not match).  If the
+   operand is valid, *INVALID will not be changed.
+
+   INSN is a pointer to an array of two `arc_insn's.  The first element is
+   the insn, the second is the limm if present.
+
+   Operands that have a printable form like registers and suffixes have
+   their struct arc_operand_value pointer stored in OPVAL.  */
 
   long (*extract) PARAMS ((arc_insn *insn,
 			   const struct arc_operand *operand,
@@ -219,9 +259,8 @@ struct arc_operand {
 			   int *invalid));
 };
 
-/* Bits that say what version of cpu we have.
-   These should be passed to arc_init_opcode_tables.
-   At present, all there is is the cpu type.  */
+/* Bits that say what version of cpu we have. These should be passed to
+   arc_init_opcode_tables. At present, all there is is the cpu type.  */
 
 /* CPU number, given value passed to `arc_init_opcode_tables'.  */
 #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
@@ -243,16 +282,16 @@ struct arc_operand {
 #define ARC_MASK_REG 63
 
 /* Delay slot types.  */
-#define ARC_DELAY_NONE 0	/* no delay slot */
-#define ARC_DELAY_NORMAL 1	/* delay slot in both cases */
-#define ARC_DELAY_JUMP 2	/* delay slot only if branch taken */
+#define ARC_DELAY_NONE 0   /* no delay slot */
+#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
+#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
 
 /* Non-zero if X will fit in a signed 9 bit field.  */
 #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
 
 extern const struct arc_operand arc_operands[];
 extern const int arc_operand_count;
-extern /*const*/ struct arc_opcode arc_opcodes[];
+extern struct arc_opcode arc_opcodes[];
 extern const int arc_opcodes_count;
 extern const struct arc_operand_value arc_suffixes[];
 extern const int arc_suffixes_count;
@@ -262,6 +301,7 @@ extern unsigned char arc_operand_map[];
 
 /* Utility fns in arc-opc.c.  */
 int arc_get_opcode_mach PARAMS ((int, int));
+
 /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
 void arc_opcode_init_tables PARAMS ((int));
 void arc_opcode_init_insert PARAMS ((void));
@@ -269,6 +309,7 @@ void arc_opcode_init_extract PARAMS ((void));
 const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
 const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
 int arc_opcode_limm_p PARAMS ((long *));
-const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value));
+const struct arc_operand_value *arc_opcode_lookup_suffix
+  PARAMS ((const struct arc_operand *type, int value));
 int arc_opcode_supported PARAMS ((const struct arc_opcode *));
 int arc_opval_supported PARAMS ((const struct arc_operand_value *));
diff --git a/gnu/usr.bin/binutils/include/opcode/avr.h b/gnu/usr.bin/binutils/include/opcode/avr.h
new file mode 100644
index 00000000000..393ca22d66b
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/opcode/avr.h
@@ -0,0 +1,256 @@
+/* Opcode table for the Atmel AVR micro controllers.
+
+   Copyright 2000 Free Software Foundation, Inc.
+   Contributed by Denis Chertykov <denisc@overta.ru>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define AVR_ISA_1200  0x0001 /* in the beginning there was ... */
+#define AVR_ISA_LPM   0x0002 /* device has LPM */
+#define AVR_ISA_LPMX  0x0004 /* device has LPM Rd,Z[+] */
+#define AVR_ISA_SRAM  0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
+#define AVR_ISA_MEGA  0x0020 /* device has >8K program memory (JMP and CALL
+				supported, no 8K wrap on RJMP and RCALL) */
+#define AVR_ISA_MUL   0x0040 /* device has new core (MUL, MOVW, ...) */
+#define AVR_ISA_ELPM  0x0080 /* device has >64K program memory (ELPM) */
+#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] (none yet) */
+#define AVR_ISA_SPM   0x0200 /* device can program itself */
+#define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
+
+#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
+#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
+#define AVR_ISA_M83  (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
+#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
+#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_94K  (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX)
+
+#define AVR_ISA_ALL   0xFFFF
+
+#define REGISTER_P(x) ((x) == 'r'		\
+		       || (x) == 'd'		\
+		       || (x) == 'w'		\
+		       || (x) == 'a'		\
+		       || (x) == 'v')
+
+/* Undefined combination of operands - does the register
+   operand overlap with pre-decremented or post-incremented
+   pointer register (like ld r31,Z+)?  */
+#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 ||		\
+  ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE ||	\
+  ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA ||	\
+  ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
+
+/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}?  */
+#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 ||		\
+  ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
+
+/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
+   `ld r,b' or `st b,r' respectively - next opcode entry)?  */
+#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
+
+/* constraint letters
+   r - any register
+   d - `ldi' register (r16-r31)
+   v - `movw' even register (r0, r2, ..., r28, r30)
+   a - `fmul' register (r16-r23)
+   w - `adiw' register (r24,r26,r28,r30)
+   e - pointer registers (X,Y,Z)
+   b - base pointer register and displacement ([YZ]+disp)
+   z - Z pointer register (for [e]lpm Rd,Z[+])
+   M - immediate value from 0 to 255
+   n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
+   s - immediate value from 0 to 7
+   P - Port address value from 0 to 63. (in, out)
+   p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
+   K - immediate value from 0 to 63 (used in `adiw', `sbiw')
+   i - immediate value
+   l - signed pc relative offset from -64 to 63
+   L - signed pc relative offset from -2048 to 2047
+   h - absolute code address (call, jmp)
+   S - immediate value from 0 to 7 (S = s << 4)
+   ? - use this opcode entry if no parameters, else use next opcode entry
+
+   Order is important - some binary opcodes have more than one name,
+   the disassembler will only see the first match.
+
+   Remaining undefined opcodes (1700 total - some of them might work
+   as normal instructions if not all of the bits are decoded):
+
+    0x0001...0x00ff    (255) (known to be decoded as `nop' by the old core)
+   "100100xxxxxxx011"  (128) 0x9[0-3][0-9a-f][3b]
+   "100100xxxxxx1000"   (64) 0x9[0-3][0-9a-f]8
+   "1001001xxxxx01xx"  (128) 0x9[23][0-9a-f][4-7]
+   "1001010xxxxx0100"   (32) 0x9[45][0-9a-f]4
+   "1001010x001x1001"    (4) 0x9[45][23]9
+   "1001010x01xx1001"    (8) 0x9[45][4-7]9
+   "1001010x1xxx1001"   (16) 0x9[45][8-9a-f]9
+   "1001010xxxxx1011"   (32) 0x9[45][0-9a-f]b
+   "10010101001x1000"    (2) 0x95[23]8
+   "1001010101xx1000"    (4) 0x95[4-7]8
+   "1001010110x11000"    (2) 0x95[9b]8
+   "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
+   "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
+ */
+
+AVR_INSN (clc,  "",    "1001010010001000", 1, AVR_ISA_1200, 0x9488)
+AVR_INSN (clh,  "",    "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
+AVR_INSN (cli,  "",    "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
+AVR_INSN (cln,  "",    "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
+AVR_INSN (cls,  "",    "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
+AVR_INSN (clt,  "",    "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
+AVR_INSN (clv,  "",    "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
+AVR_INSN (clz,  "",    "1001010010011000", 1, AVR_ISA_1200, 0x9498)
+
+AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
+AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
+AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
+AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
+AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
+AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
+AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
+AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
+
+   /* Same as {cl,se}[chinstvz] above.  */
+AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
+AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
+
+AVR_INSN (icall,"",    "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
+AVR_INSN (ijmp, "",    "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
+
+AVR_INSN (lpm,  "?",   "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
+AVR_INSN (lpm,  "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
+AVR_INSN (elpm, "?",   "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
+AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
+
+AVR_INSN (nop,  "",    "0000000000000000", 1, AVR_ISA_1200, 0x0000)
+AVR_INSN (ret,  "",    "1001010100001000", 1, AVR_ISA_1200, 0x9508)
+AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
+AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
+AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
+AVR_INSN (spm,  "",    "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
+
+AVR_INSN (adc,  "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
+AVR_INSN (add,  "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
+AVR_INSN (and,  "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
+AVR_INSN (cp,   "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
+AVR_INSN (cpc,  "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
+AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
+AVR_INSN (eor,  "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
+AVR_INSN (mov,  "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
+AVR_INSN (mul,  "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL,  0x9c00)
+AVR_INSN (or,   "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
+AVR_INSN (sbc,  "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
+AVR_INSN (sub,  "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
+
+   /* Shorthand for {eor,add,adc,and} r,r above.  */
+AVR_INSN (clr,  "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
+AVR_INSN (lsl,  "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
+AVR_INSN (rol,  "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
+AVR_INSN (tst,  "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
+
+AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
+  /*XXX special case*/
+AVR_INSN (cbr,  "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
+
+AVR_INSN (ldi,  "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
+AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
+
+AVR_INSN (ori,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
+AVR_INSN (sbr,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
+
+AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
+AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
+AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
+
+AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
+AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
+AVR_INSN (bld,  "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
+AVR_INSN (bst,  "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
+
+AVR_INSN (in,   "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
+AVR_INSN (out,  "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
+
+AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
+AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
+
+AVR_INSN (cbi,  "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
+AVR_INSN (sbi,  "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
+AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
+AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
+
+AVR_INSN (brcc, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brcs, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
+AVR_INSN (breq, "l",   "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
+AVR_INSN (brge, "l",   "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
+AVR_INSN (brhc, "l",   "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
+AVR_INSN (brhs, "l",   "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
+AVR_INSN (brid, "l",   "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
+AVR_INSN (brie, "l",   "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
+AVR_INSN (brlo, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
+AVR_INSN (brlt, "l",   "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
+AVR_INSN (brmi, "l",   "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
+AVR_INSN (brne, "l",   "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
+AVR_INSN (brpl, "l",   "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
+AVR_INSN (brsh, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brtc, "l",   "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
+AVR_INSN (brts, "l",   "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
+AVR_INSN (brvc, "l",   "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
+AVR_INSN (brvs, "l",   "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
+
+   /* Same as br?? above.  */
+AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
+
+AVR_INSN (rcall, "L",  "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
+AVR_INSN (rjmp,  "L",  "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
+
+AVR_INSN (call, "h",   "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
+AVR_INSN (jmp,  "h",   "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
+
+AVR_INSN (asr,  "r",   "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
+AVR_INSN (com,  "r",   "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
+AVR_INSN (dec,  "r",   "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
+AVR_INSN (inc,  "r",   "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
+AVR_INSN (lsr,  "r",   "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
+AVR_INSN (neg,  "r",   "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
+AVR_INSN (pop,  "r",   "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
+AVR_INSN (push, "r",   "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
+AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
+AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
+
+   /* Known to be decoded as `nop' by the old core.  */
+AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MUL,  0x0100)
+AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL,  0x0200)
+AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL,  0x0300)
+AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL,  0x0308)
+AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL,  0x0380)
+AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL,  0x0388)
+
+AVR_INSN (sts,  "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
+AVR_INSN (lds,  "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
+
+   /* Special case for b+0, `e' must be next entry after `b',
+      b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X.  */
+AVR_INSN (ldd,  "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
+AVR_INSN (ld,   "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
+AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
+AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
+
+   /* These are for devices that don't exist yet
+      (>128K program memory, PC = EIND:Z).  */
+AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
+AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
+
diff --git a/gnu/usr.bin/binutils/include/opcode/cgen.h b/gnu/usr.bin/binutils/include/opcode/cgen.h
index 0cff7c82682..8cf31232225 100644
--- a/gnu/usr.bin/binutils/include/opcode/cgen.h
+++ b/gnu/usr.bin/binutils/include/opcode/cgen.h
@@ -1,6 +1,6 @@
 /* Header file for targets using CGEN: Cpu tools GENerator.
 
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
 
 This file is part of GDB, the GNU debugger, and the GNU Binutils.
 
@@ -452,7 +452,7 @@ typedef struct {
 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
      PARAMS ((CGEN_CPU_DESC, const char *));
 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
-     PARAMS ((CGEN_CPU_DESC, int));
+     PARAMS ((CGEN_CPU_DESC, unsigned int));
 
 /* This struct is used to describe things like register names, etc.  */
 
@@ -735,18 +735,31 @@ typedef struct
    into the operand table.  The operand table doesn't exist in C, per se, as
    the data is recorded in the parse/insert/extract/print switch statements. */
 
-#ifndef CGEN_MAX_SYNTAX_BYTES
-#define CGEN_MAX_SYNTAX_BYTES 16
+/* This should be at least as large as necessary for any target. */
+#define CGEN_MAX_SYNTAX_BYTES 40
+
+/* A target may know its own precise maximum.  Assert that it falls below
+   the above limit. */
+#ifdef CGEN_ACTUAL_MAX_SYNTAX_BYTES
+#if CGEN_ACTUAL_MAX_SYNTAX_BYTES > CGEN_MAX_SYNTAX_BYTES
+#error "CGEN_ACTUAL_MAX_SYNTAX_BYTES too high - enlarge CGEN_MAX_SYNTAX_BYTES"
+#endif
+#endif
+
+#if !defined(MAX_OPERANDS) || MAX_OPERANDS <= 127
+typedef unsigned char CGEN_SYNTAX_CHAR_TYPE;
+#else
+typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
 #endif
 
 typedef struct
 {
-  unsigned char syntax[CGEN_MAX_SYNTAX_BYTES];
+  CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_BYTES];
 } CGEN_SYNTAX;
 
 #define CGEN_SYNTAX_STRING(syn) (syn->syntax)
 #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
-#define CGEN_SYNTAX_CHAR(c) (c)
+#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
 #define CGEN_SYNTAX_FIELD(c) ((c) - 128)
 #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
 
@@ -824,9 +837,17 @@ typedef struct {
 #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
 } CGEN_IFMT_IFLD;
 
-#ifndef CGEN_MAX_IFMT_OPERANDS
-#define CGEN_MAX_IFMT_OPERANDS 1
+/* This should be at least as large as necessary for any target. */
+#define CGEN_MAX_IFMT_OPERANDS 16
+
+/* A target may know its own precise maximum.  Assert that it falls below
+   the above limit. */
+#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
+#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
+#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
 #endif
+#endif
+
 
 typedef struct
 {
diff --git a/gnu/usr.bin/binutils/include/opcode/cris.h b/gnu/usr.bin/binutils/include/opcode/cris.h
new file mode 100644
index 00000000000..83f26d1f83e
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/opcode/cris.h
@@ -0,0 +1,298 @@
+/* cris.h -- Header file for CRIS opcode and register tables.
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Axis Communications AB, Lund, Sweden.
+   Originally written for GAS 1.38.1 by Mikael Asker.
+   Updated, BFDized and GNUified by Hans-Peter Nilsson.
+
+This file is part of GAS, GDB and the GNU binutils.
+
+GAS, GDB, and GNU binutils is free software; you can redistribute it
+and/or modify it under the terms of the GNU General Public License as
+published by the Free Software Foundation; either version 2, or (at your
+option) any later version.
+
+GAS, GDB, and GNU binutils are distributed in the hope that they will be
+useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef __CRIS_H_INCLUDED_
+#define __CRIS_H_INCLUDED_
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+
+/* Registers.  */
+#define MAX_REG (15)
+#define REG_SP (14)
+#define REG_PC (15)
+
+/* CPU version control of disassembly and assembly of instructions.
+   May affect how the instruction is assembled, at least the size of
+   immediate operands.  */
+enum cris_insn_version_usage
+{
+  /* Any version. */
+  cris_ver_version_all=0,
+
+  /* Indeterminate (intended for disassembly only, or obsolete).  */
+  cris_ver_warning,
+
+  /* Simulator only (reserved).  */
+  cris_ver_sim,
+
+  /* Only for v0..3 (Etrax 1..4).  */
+  cris_ver_v0_3,
+
+  /* Only for v3 or higher (ETRAX 1..4 and beyond).  */
+  cris_ver_v3p,
+
+  /* Only for v8 (Etrax 100).  */
+  cris_ver_v8,
+
+  /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
+  cris_ver_v8p,
+
+  /* Only for v10 or higher (ETRAX 100 LX).
+     Of course some or all these of may change to cris_ver_v10p if/when
+     there's a new revision. */
+  cris_ver_v10p
+};
+
+
+/* Special registers.  */
+struct cris_spec_reg
+{
+  const char *const name;
+  unsigned int number;
+
+  /* The size of the register.  */
+  unsigned int reg_size;
+
+  /* What CPU version the special register of that name is implemented
+     in.  If cris_ver_warning, emit an unimplemented-warning.  */
+  enum cris_insn_version_usage applicable_version;
+
+  /* There might be a specific warning for using a special register
+     here.  */
+  const char *const warning;
+};
+extern const struct cris_spec_reg cris_spec_regs[];
+
+/* Opcode-dependent constants.  */
+#define AUTOINCR_BIT (0x04)
+
+/* Prefixes.  */
+#define BDAP_QUICK_OPCODE (0x0100)
+#define BDAP_QUICK_Z_BITS (0x0e00)
+
+#define BIAP_OPCODE	  (0x0540)
+#define BIAP_Z_BITS	  (0x0a80)
+
+#define DIP_OPCODE	  (0x0970)
+#define DIP_Z_BITS	  (0xf280)
+
+#define BDAP_INDIR_LOW	  (0x40)
+#define BDAP_INDIR_LOW_Z  (0x80)
+#define BDAP_INDIR_HIGH	  (0x09)
+#define BDAP_INDIR_HIGH_Z (0x02)
+
+#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
+#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
+#define BDAP_PC_LOW	  (BDAP_INDIR_LOW + REG_PC)
+#define BDAP_INCR_HIGH	  (BDAP_INDIR_HIGH + AUTOINCR_BIT)
+
+/* No prefix must have this code for its "match" bits in the
+   opcode-table.  "BCC .+2" will do nicely.  */
+#define NO_CRIS_PREFIX 0
+
+/* Definitions for condition codes.  */
+#define CC_CC  0x0
+#define CC_HS  0x0
+#define CC_CS  0x1
+#define CC_LO  0x1
+#define CC_NE  0x2
+#define CC_EQ  0x3
+#define CC_VC  0x4
+#define CC_VS  0x5
+#define CC_PL  0x6
+#define CC_MI  0x7
+#define CC_LS  0x8
+#define CC_HI  0x9
+#define CC_GE  0xA
+#define CC_LT  0xB
+#define CC_GT  0xC
+#define CC_LE  0xD
+#define CC_A   0xE
+#define CC_EXT 0xF
+
+/* A table of strings "cc", "cs"... indexed with condition code
+   values as above.  */
+extern const char *const cris_cc_strings[];
+
+/* Bcc quick.  */
+#define BRANCH_QUICK_LOW  (0)
+#define BRANCH_QUICK_HIGH (0)
+#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
+#define BRANCH_QUICK_Z_BITS (0x0F00)
+
+/* BA quick.  */
+#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
+#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
+
+/* Bcc [PC+].  */
+#define BRANCH_PC_LOW	 (0xFF)
+#define BRANCH_INCR_HIGH (0x0D)
+#define BA_PC_INCR_OPCODE \
+ ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
+
+/* Jump.  */
+/* Note that old versions generated special register 8 (in high bits)
+   and not-that-old versions recognized it as a jump-instruction.
+   That opcode now belongs to JUMPU.  */
+#define JUMP_INDIR_OPCODE (0x0930)
+#define JUMP_INDIR_Z_BITS (0xf2c0)
+#define JUMP_PC_INCR_OPCODE \
+ (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
+
+/* Nop.  */
+#define NOP_OPCODE (0x050F)
+#define NOP_Z_BITS (0xFAF0)
+
+/* Structure of an opcode table entry.  */
+enum cris_imm_oprnd_size_type
+{
+  /* No size is applicable.  */
+  SIZE_NONE,
+
+  /* Always 32 bits.  */
+  SIZE_FIX_32,
+
+  /* Indicated by size of special register.  */
+  SIZE_SPEC_REG,
+
+  /* Indicated by size field.  */
+  SIZE_FIELD
+};
+
+/* For GDB.  FIXME: Is this the best way to handle opcode
+   interpretation?  */
+enum cris_op_type
+{
+  cris_not_implemented_op = 0,
+  cris_abs_op,
+  cris_addi_op,
+  cris_asr_op,
+  cris_asrq_op,
+  cris_ax_ei_setf_op,
+  cris_bdap_prefix,
+  cris_biap_prefix,
+  cris_break_op,
+  cris_btst_nop_op,
+  cris_clearf_di_op,
+  cris_dip_prefix,
+  cris_dstep_logshift_mstep_neg_not_op,
+  cris_eight_bit_offset_branch_op,
+  cris_move_mem_to_reg_movem_op,
+  cris_move_reg_to_mem_movem_op,
+  cris_move_to_preg_op,
+  cris_muls_op,
+  cris_mulu_op,
+  cris_none_reg_mode_add_sub_cmp_and_or_move_op,
+  cris_none_reg_mode_clear_test_op,
+  cris_none_reg_mode_jump_op,
+  cris_none_reg_mode_move_from_preg_op,
+  cris_quick_mode_add_sub_op,
+  cris_quick_mode_and_cmp_move_or_op,
+  cris_quick_mode_bdap_prefix,
+  cris_reg_mode_add_sub_cmp_and_or_move_op,
+  cris_reg_mode_clear_op,
+  cris_reg_mode_jump_op,
+  cris_reg_mode_move_from_preg_op,
+  cris_reg_mode_test_op,
+  cris_scc_op,
+  cris_sixteen_bit_offset_branch_op,
+  cris_three_operand_add_sub_cmp_and_or_op,
+  cris_three_operand_bound_op,
+  cris_two_operand_bound_op,
+  cris_xor_op
+};
+
+struct cris_opcode
+{
+  /* The name of the insn.  */
+  const char *name;
+
+  /* Bits that must be 1 for a match.  */
+  unsigned int match;
+
+  /* Bits that must be 0 for a match.  */
+  unsigned int lose;
+
+  /* See the table in "opcodes/cris-opc.c".  */
+  const char *args;
+
+  /* Nonzero if this is a delayed branch instruction.  */
+  char delayed;
+
+  /* Size of immediate operands.  */
+  enum cris_imm_oprnd_size_type imm_oprnd_size;
+
+  /* Indicates which version this insn was first implemented in.  */
+  enum cris_insn_version_usage applicable_version;
+
+  /* What kind of operation this is.  */
+  enum cris_op_type op;
+};
+extern const struct cris_opcode cris_opcodes[];
+
+
+/* These macros are for the target-specific flags in disassemble_info
+   used at disassembly.  */
+
+/* This insn accesses memory.  This flag is more trustworthy than
+   checking insn_type for "dis_dref" which does not work for
+   e.g. "JSR [foo]".  */
+#define CRIS_DIS_FLAG_MEMREF (1 << 0)
+
+/* The "target" field holds a register number.  */
+#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
+
+/* The "target2" field holds a register number; add it to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
+
+/* Yet another add-on: the register in "target2" must be multiplied
+   by 2 before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
+
+/* Yet another add-on: the register in "target2" must be multiplied
+   by 4 (mutually exclusive with .._MULT2).  */ 
+#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
+
+/* The register in "target2" is an indirect memory reference (of the
+   register there), add to "target".  Assumed size is dword (mutually
+   exclusive with .._MULT[24]).  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
+
+/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
+   sign-extended before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
+
+/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
+   sign-extended before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
+
+#endif /* __CRIS_H_INCLUDED_ */
+
+/*
+ * Local variables:
+ * eval: (c-set-style "gnu")
+ * indent-tabs-mode: t
+ * End:
+ */
diff --git a/gnu/usr.bin/binutils/include/opcode/d10v.h b/gnu/usr.bin/binutils/include/opcode/d10v.h
index 7c6d32ddffa..a1fe770a7c6 100644
--- a/gnu/usr.bin/binutils/include/opcode/d10v.h
+++ b/gnu/usr.bin/binutils/include/opcode/d10v.h
@@ -1,5 +1,5 @@
 /* d10v.h -- Header file for D10V opcode table
-   Copyright 1996, 1997, 1998 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
    Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -78,6 +78,7 @@ struct d10v_opcode
 #define WF0     128	/* modifies f0 */
 #define WCAR    256	/* write Carry */
 #define BRANCH  512	/* branch, no link */
+#define ALONE  1024	/* short but pack with a NOP if on asm line alone */
 
   /* the opcode */
   long opcode;
diff --git a/gnu/usr.bin/binutils/include/opcode/d30v.h b/gnu/usr.bin/binutils/include/opcode/d30v.h
index f90b7a420ce..6cbc2576e01 100644
--- a/gnu/usr.bin/binutils/include/opcode/d30v.h
+++ b/gnu/usr.bin/binutils/include/opcode/d30v.h
@@ -1,5 +1,5 @@
 /* d30v.h -- Header file for D30V opcode table
-   Copyright (C) 1997, 2000 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
    Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
 
 This file is part of GDB, GAS, and the GNU binutils.
diff --git a/gnu/usr.bin/binutils/include/opcode/i370.h b/gnu/usr.bin/binutils/include/opcode/i370.h
index f2049e741d1..155a3cf866d 100644
--- a/gnu/usr.bin/binutils/include/opcode/i370.h
+++ b/gnu/usr.bin/binutils/include/opcode/i370.h
@@ -1,5 +1,5 @@
 /* i370.h -- Header file for S/390 opcode table
-   Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1998, 1999, 2000 Free Software Foundation, Inc.
    PowerPC version written by Ian Lance Taylor, Cygnus Support
    Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
 
diff --git a/gnu/usr.bin/binutils/include/opcode/ia64.h b/gnu/usr.bin/binutils/include/opcode/ia64.h
new file mode 100644
index 00000000000..642330cc118
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/opcode/ia64.h
@@ -0,0 +1,391 @@
+/* ia64.h -- Header file for ia64 opcode table
+   Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+
+   See the file HP-COPYRIGHT for additional information.  */
+
+#ifndef opcode_ia64_h
+#define opcode_ia64_h
+
+#include <sys/types.h>
+
+#include <bfd.h>
+
+
+typedef BFD_HOST_U_64_BIT ia64_insn;
+
+enum ia64_insn_type
+  {
+    IA64_TYPE_NIL = 0,	/* illegal type */
+    IA64_TYPE_A,	/* integer alu (I- or M-unit) */
+    IA64_TYPE_I,	/* non-alu integer (I-unit) */
+    IA64_TYPE_M,	/* memory (M-unit) */
+    IA64_TYPE_B,	/* branch (B-unit) */
+    IA64_TYPE_F,	/* floating-point (F-unit) */
+    IA64_TYPE_X,	/* long encoding (X-unit) */
+    IA64_TYPE_DYN,	/* Dynamic opcode */
+    IA64_NUM_TYPES
+  };
+
+enum ia64_unit
+  {
+    IA64_UNIT_NIL = 0,	/* illegal unit */
+    IA64_UNIT_I,	/* integer unit */
+    IA64_UNIT_M,	/* memory unit */
+    IA64_UNIT_B,	/* branching unit */
+    IA64_UNIT_F,	/* floating-point unit */
+    IA64_UNIT_L,	/* long "unit" */
+    IA64_UNIT_X,	/* may be integer or branch unit */
+    IA64_NUM_UNITS
+  };
+
+/* Changes to this enumeration must be propagated to the operand table in
+   bfd/cpu-ia64-opc.c 
+ */ 
+enum ia64_opnd
+  {
+    IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
+
+    /* constants */
+    IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */
+    IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */
+    IA64_OPND_C1,	/* the constant 1 */
+    IA64_OPND_C8,	/* the constant 8 */
+    IA64_OPND_C16,	/* the constant 16 */
+    IA64_OPND_GR0,	/* gr0 */
+    IA64_OPND_IP,	/* instruction pointer (ip) */
+    IA64_OPND_PR,	/* predicate register (pr) */
+    IA64_OPND_PR_ROT,	/* rotating predicate register (pr.rot) */
+    IA64_OPND_PSR,	/* processor status register (psr) */
+    IA64_OPND_PSR_L,	/* processor status register L (psr.l) */
+    IA64_OPND_PSR_UM,	/* processor status register UM (psr.um) */
+
+    /* register operands: */
+    IA64_OPND_AR3,	/* third application register # (bits 20-26) */
+    IA64_OPND_B1,	/* branch register # (bits 6-8) */
+    IA64_OPND_B2,	/* branch register # (bits 13-15) */
+    IA64_OPND_CR3,	/* third control register # (bits 20-26) */
+    IA64_OPND_F1,	/* first floating-point register # */
+    IA64_OPND_F2,	/* second floating-point register # */
+    IA64_OPND_F3,	/* third floating-point register # */
+    IA64_OPND_F4,	/* fourth floating-point register # */
+    IA64_OPND_P1,	/* first predicate # */
+    IA64_OPND_P2,	/* second predicate # */
+    IA64_OPND_R1,	/* first register # */
+    IA64_OPND_R2,	/* second register # */
+    IA64_OPND_R3,	/* third register # */
+    IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
+
+    /* indirect operands: */
+    IA64_OPND_CPUID_R3,	/* cpuid[reg] */
+    IA64_OPND_DBR_R3,	/* dbr[reg] */
+    IA64_OPND_DTR_R3,	/* dtr[reg] */
+    IA64_OPND_ITR_R3,	/* itr[reg] */
+    IA64_OPND_IBR_R3,	/* ibr[reg] */
+    IA64_OPND_MR3,	/* memory at addr of third register # */
+    IA64_OPND_MSR_R3,	/* msr[reg] */
+    IA64_OPND_PKR_R3,	/* pkr[reg] */
+    IA64_OPND_PMC_R3,	/* pmc[reg] */
+    IA64_OPND_PMD_R3,	/* pmd[reg] */
+    IA64_OPND_RR_R3,	/* rr[reg] */
+
+    /* immediate operands: */
+    IA64_OPND_CCNT5,	/* 5-bit count (31 - bits 20-24) */
+    IA64_OPND_CNT2a,	/* 2-bit count (1 + bits 27-28) */
+    IA64_OPND_CNT2b,	/* 2-bit count (bits 27-28): 1, 2, 3 */
+    IA64_OPND_CNT2c,	/* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
+    IA64_OPND_CNT5,	/* 5-bit count (bits 14-18) */
+    IA64_OPND_CNT6,	/* 6-bit count (bits 27-32) */
+    IA64_OPND_CPOS6a,	/* 6-bit count (63 - bits 20-25) */
+    IA64_OPND_CPOS6b,	/* 6-bit count (63 - bits 14-19) */
+    IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */
+    IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */
+    IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */
+    IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */
+    IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */
+    IA64_OPND_SOF,	/* 8-bit stack frame size */
+    IA64_OPND_SOL,	/* 8-bit size of locals */
+    IA64_OPND_SOR,	/* 6-bit number of rotating registers (scaled by 8) */
+    IA64_OPND_IMM8,	/* signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8U4,	/* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1,	/* signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1U4,	/* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
+    IA64_OPND_IMM8M1U8,	/* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMMU9,	/* unsigned 9-bit immediate (bits 33-34, 20-26) */
+    IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
+    IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
+    IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+    IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+    IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
+    IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
+    IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
+    IA64_OPND_IMM44,	/* signed 44-bit immediate (2^16*bits 6-32, 36) */
+    IA64_OPND_IMMU62,	/* unsigned 62-bit immediate */
+    IA64_OPND_IMMU64,	/* unsigned 64-bit immediate (lotsa bits...) */
+    IA64_OPND_INC3,	/* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
+    IA64_OPND_LEN4,	/* 4-bit count (bits 27-30 + 1) */
+    IA64_OPND_LEN6,	/* 6-bit count (bits 27-32 + 1) */
+    IA64_OPND_MBTYPE4,	/* 4-bit mux type (bits 20-23) */
+    IA64_OPND_MHTYPE8,	/* 8-bit mux type (bits 20-27) */
+    IA64_OPND_POS6,	/* 6-bit count (bits 14-19) */
+    IA64_OPND_TAG13,	/* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
+    IA64_OPND_TAG13b,	/* signed 13-bit tag (ip + 16*bits 24-32) */
+    IA64_OPND_TGT25,	/* signed 25-bit (ip + 16*bits 6-25, 36) */
+    IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
+    IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */
+    IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+
+    IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
+  };
+
+enum ia64_dependency_mode
+{
+  IA64_DV_RAW,
+  IA64_DV_WAW,
+  IA64_DV_WAR,
+};
+
+enum ia64_dependency_semantics
+{
+  IA64_DVS_NONE,
+  IA64_DVS_IMPLIED,
+  IA64_DVS_IMPLIEDF,
+  IA64_DVS_DATA,
+  IA64_DVS_INSTR,
+  IA64_DVS_SPECIFIC,
+  IA64_DVS_STOP,
+  IA64_DVS_OTHER,
+};
+
+enum ia64_resource_specifier
+{
+  IA64_RS_ANY,
+  IA64_RS_AR_K,
+  IA64_RS_AR_UNAT,
+  IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
+  IA64_RS_ARb, /* 48-63, 112-127 */
+  IA64_RS_BR,
+  IA64_RS_CFM,
+  IA64_RS_CPUID,
+  IA64_RS_CR_IRR,
+  IA64_RS_CR_LRR,
+  IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
+  IA64_RS_DBR,
+  IA64_RS_FR,
+  IA64_RS_FRb,
+  IA64_RS_GR0,
+  IA64_RS_GR,
+  IA64_RS_IBR,
+  IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
+  IA64_RS_MSR,
+  IA64_RS_PKR,
+  IA64_RS_PMC,
+  IA64_RS_PMD,
+  IA64_RS_PR,  /* non-rotating, 1-15 */
+  IA64_RS_PRr, /* rotating, 16-62 */
+  IA64_RS_PR63,
+  IA64_RS_RR,
+
+  IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
+  IA64_RS_CRX, /* CRs not in RS_CR */
+  IA64_RS_PSR, /* PSR bits */
+  IA64_RS_RSE, /* implementation-specific RSE resources */
+  IA64_RS_AR_FPSR,
+};
+
+enum ia64_rse_resource
+{
+  IA64_RSE_N_STACKED_PHYS,
+  IA64_RSE_BOF,
+  IA64_RSE_STORE_REG,
+  IA64_RSE_LOAD_REG,
+  IA64_RSE_BSPLOAD,
+  IA64_RSE_RNATBITINDEX,
+  IA64_RSE_CFLE,
+  IA64_RSE_NDIRTY,
+};
+
+/* Information about a given resource dependency */
+struct ia64_dependency
+{
+  /* Name of the resource */
+  const char *name;
+  /* Does this dependency need further specification? */
+  enum ia64_resource_specifier specifier;
+  /* Mode of dependency */
+  enum ia64_dependency_mode mode;
+  /* Dependency semantics */
+  enum ia64_dependency_semantics semantics;
+  /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
+#define REG_NONE (-1)
+  int regindex;
+  /* Special info on semantics */
+  const char *info;
+};
+
+/* Two arrays of indexes into the ia64_dependency table.
+   chks are dependencies to check for conflicts when an opcode is
+   encountered; regs are dependencies to register (mark as used) when an
+   opcode is used.  chks correspond to readers (RAW) or writers (WAW or
+   WAR) of a resource, while regs correspond to writers (RAW or WAW) and
+   readers (WAR) of a resource.  */
+struct ia64_opcode_dependency
+{
+  int nchks;
+  const unsigned short *chks;
+  int nregs;
+  const unsigned short *regs;
+};
+
+/* encode/extract the note/index for a dependency */
+#define RDEP(N,X) (((N)<<11)|(X))
+#define NOTE(X) (((X)>>11)&0x1F)
+#define DEP(X) ((X)&0x7FF)
+
+/* A template descriptor describes the execution units that are active
+   for each of the three slots.  It also specifies the location of
+   instruction group boundaries that may be present between two slots.  */
+struct ia64_templ_desc
+  {
+    int group_boundary;	/* 0=no boundary, 1=between slot 0 & 1, etc. */
+    enum ia64_unit exec_unit[3];
+    const char *name;
+  };
+
+/* The opcode table is an array of struct ia64_opcode.  */
+
+struct ia64_opcode
+  {
+    /* The opcode name.  */
+    const char *name;
+
+    /* The type of the instruction: */
+    enum ia64_insn_type type;
+
+    /* Number of output operands: */
+    int num_outputs;
+
+    /* The opcode itself.  Those bits which will be filled in with
+       operands are zeroes.  */
+    ia64_insn opcode;
+
+    /* The opcode mask.  This is used by the disassembler.  This is a
+       mask containing ones indicating those bits which must match the
+       opcode field, and zeroes indicating those bits which need not
+       match (and are presumably filled in by operands).  */
+    ia64_insn mask;
+
+    /* An array of operand codes.  Each code is an index into the
+       operand table.  They appear in the order which the operands must
+       appear in assembly code, and are terminated by a zero.  */
+    enum ia64_opnd operands[5];
+
+    /* One bit flags for the opcode.  These are primarily used to
+       indicate specific processors and environments support the
+       instructions.  The defined values are listed below. */
+    unsigned int flags;
+
+    /* Used by ia64_find_next_opcode (). */
+    short ent_index;
+
+    /* Opcode dependencies. */ 
+    const struct ia64_opcode_dependency *dependencies;
+  };
+
+/* Values defined for the flags field of a struct ia64_opcode.  */
+
+#define IA64_OPCODE_FIRST	(1<<0)	/* must be first in an insn group */
+#define IA64_OPCODE_X_IN_MLX	(1<<1)	/* insn is allowed in X slot of MLX */
+#define IA64_OPCODE_LAST	(1<<2)	/* must be last in an insn group */
+#define IA64_OPCODE_PRIV	(1<<3)	/* privileged instruct */
+#define IA64_OPCODE_SLOT2	(1<<4)	/* insn allowed in slot 2 only */
+#define IA64_OPCODE_NO_PRED	(1<<5)	/* insn cannot be predicated */
+#define IA64_OPCODE_PSEUDO	(1<<6)	/* insn is a pseudo-op */
+#define IA64_OPCODE_F2_EQ_F3	(1<<7)	/* constraint: F2 == F3 */
+#define IA64_OPCODE_LEN_EQ_64MCNT	(1<<8)	/* constraint: LEN == 64-CNT */
+#define IA64_OPCODE_MOD_RRBS    (1<<9)	/* modifies all rrbs in CFM */
+#define IA64_OPCODE_POSTINC	(1<<10)	/* postincrement MR3 operand */
+
+/* A macro to extract the major opcode from an instruction.  */
+#define IA64_OP(i)	(((i) >> 37) & 0xf)
+
+enum ia64_operand_class
+  {
+    IA64_OPND_CLASS_CST,	/* constant */
+    IA64_OPND_CLASS_REG,	/* register */
+    IA64_OPND_CLASS_IND,	/* indirect register */
+    IA64_OPND_CLASS_ABS,	/* absolute value */
+    IA64_OPND_CLASS_REL,	/* IP-relative value */
+  };
+
+/* The operands table is an array of struct ia64_operand.  */
+
+struct ia64_operand
+{
+  enum ia64_operand_class class;
+
+  /* Set VALUE as the operand bits for the operand of type SELF in the
+     instruction pointed to by CODE.  If an error occurs, *CODE is not
+     modified and the returned string describes the cause of the
+     error.  If no error occurs, NULL is returned.  */
+  const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
+			 ia64_insn *code);
+
+  /* Extract the operand bits for an operand of type SELF from
+     instruction CODE store them in *VALUE.  If an error occurs, the
+     cause of the error is described by the string returned.  If no
+     error occurs, NULL is returned.  */
+  const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
+			  ia64_insn *value);
+
+  /* A string whose meaning depends on the operand class.  */
+
+  const char *str;
+
+  struct bit_field
+    {
+      /* The number of bits in the operand.  */
+      int bits;
+
+      /* How far the operand is left shifted in the instruction.  */
+      int shift;
+    }
+  field[4];		/* no operand has more than this many bit-fields */
+
+  unsigned int flags;
+
+  const char *desc;	/* brief description */
+};
+
+/* Values defined for the flags field of a struct ia64_operand.  */
+
+/* Disassemble as signed decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_SIGNED	(1<<0)
+/* Disassemble as unsigned decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_UNSIGNED	(1<<1)
+
+extern const struct ia64_templ_desc ia64_templ_desc[16];
+
+/* The tables are sorted by major opcode number and are otherwise in
+   the order in which the disassembler should consider instructions.  */
+extern struct ia64_opcode ia64_opcodes_a[];
+extern struct ia64_opcode ia64_opcodes_i[];
+extern struct ia64_opcode ia64_opcodes_m[];
+extern struct ia64_opcode ia64_opcodes_b[];
+extern struct ia64_opcode ia64_opcodes_f[];
+extern struct ia64_opcode ia64_opcodes_d[];
+
+
+extern struct ia64_opcode *ia64_find_opcode (const char *name);
+extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
+
+extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
+					    enum ia64_insn_type type);
+
+extern void ia64_free_opcode (struct ia64_opcode *ent);
+extern const struct ia64_dependency *ia64_find_dependency (int index);
+
+/* To avoid circular library dependencies, this array is implemented
+   in bfd/cpu-ia64-opc.c: */
+extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
+
+#endif /* opcode_ia64_h */
diff --git a/gnu/usr.bin/binutils/include/opcode/m68hc11.h b/gnu/usr.bin/binutils/include/opcode/m68hc11.h
new file mode 100644
index 00000000000..52a24613078
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/opcode/m68hc11.h
@@ -0,0 +1,418 @@
+/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
+   Copyright 1999, 2000 Free Software Foundation, Inc.
+   Written by Stephane Carrez (stcarrez@worldnet.fr)
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _OPCODE_M68HC11_H
+#define _OPCODE_M68HC11_H
+
+/* Flags for the definition of the 68HC11 & 68HC12 CCR.  */
+#define M6811_S_BIT     0x80	/* Stop disable */
+#define M6811_X_BIT     0x40	/* X-interrupt mask */
+#define M6811_H_BIT     0x20	/* Half carry flag */
+#define M6811_I_BIT     0x10	/* I-interrupt mask */
+#define M6811_N_BIT     0x08	/* Negative */
+#define M6811_Z_BIT     0x04	/* Zero */
+#define M6811_V_BIT     0x02	/* Overflow */
+#define M6811_C_BIT     0x01	/* Carry */
+
+/* 68HC11 register address offsets (range 0..0x3F or 0..64).
+   The absolute address of the I/O register depends on the setting
+   of the M6811_INIT register.  At init time, the I/O registers are
+   mapped at 0x1000.  Address of registers is then:
+
+   0x1000 + M6811_xxx
+*/
+#define M6811_PORTA     0x00	/* Port A register */
+#define M6811__RES1	0x01	/* Unused/Reserved */
+#define M6811_PIOC	0x02	/* Parallel I/O Control register */
+#define M6811_PORTC	0x03	/* Port C register */
+#define M6811_PORTB	0x04	/* Port B register */
+#define M6811_PORTCL	0x05	/* Alternate latched port C */
+#define M6811__RES6	0x06	/* Unused/Reserved */
+#define M6811_DDRC	0x07	/* Data direction register for port C */
+#define M6811_PORTD	0x08	/* Port D register */
+#define M6811_DDRD	0x09	/* Data direction register for port D */
+#define M6811_PORTE	0x0A	/* Port E input register */
+#define M6811_CFORC	0x0B	/* Compare Force Register */
+#define M6811_OC1M	0x0C	/* OC1 Action Mask register */
+#define M6811_OC1D	0x0D	/* OC1 Action Data register */
+#define M6811_TCTN	0x0E	/* Timer Counter Register */
+#define M6811_TCTN_H	0x0E	/* "	 "	 " High part */
+#define M6811_TCTN_L	0x0F	/* "	 "	 " Low part */
+#define M6811_TIC1	0x10	/* Input capture 1 register */
+#define M6811_TIC1_H	0x10	/* "	 "	 " High part */
+#define M6811_TIC1_L	0x11	/* "	 "	 " Low part */
+#define M6811_TIC2	0x12	/* Input capture 2 register */
+#define M6811_TIC2_H	0x12	/* "	 "	 " High part */
+#define M6811_TIC2_L	0x13	/* "	 "	 " Low part */
+#define M6811_TIC3	0x14	/* Input capture 3 register */
+#define M6811_TIC3_H	0x14	/* "	 "	 " High part */
+#define M6811_TIC3_L	0x15	/* "	 "	 " Low part */
+#define M6811_TOC1	0x16	/* Output Compare 1 register */
+#define M6811_TOC1_H	0x16	/* "	 "	 " High part */
+#define M6811_TOC1_L	0x17	/* "	 "	 " Low part */
+#define M6811_TOC2	0x18	/* Output Compare 2 register */
+#define M6811_TOC2_H	0x18	/* "	 "	 " High part */
+#define M6811_TOC2_L	0x19	/* "	 "	 " Low part */
+#define M6811_TOC3	0x1A	/* Output Compare 3 register */
+#define M6811_TOC3_H	0x1A	/* "	 "	 " High part */
+#define M6811_TOC3_L	0x1B	/* "	 "	 " Low part */
+#define M6811_TOC4	0x1C	/* Output Compare 4 register */
+#define M6811_TOC4_H	0x1C	/* "	 "	 " High part */
+#define M6811_TOC4_L	0x1D	/* "	 "	 " Low part */
+#define M6811_TOC5	0x1E	/* Output Compare 5 register */
+#define M6811_TOC5_H	0x1E	/* "	 "	 " High part */
+#define M6811_TOC5_L	0x1F	/* "	 "	 " Low part */
+#define M6811_TCTL1	0x20	/* Timer Control register 1 */
+#define M6811_TCTL2	0x21	/* Timer Control register 2 */
+#define M6811_TMSK1	0x22	/* Timer Interrupt Mask Register 1 */
+#define M6811_TFLG1	0x23	/* Timer Interrupt Flag Register 1 */
+#define M6811_TMSK2	0x24	/* Timer Interrupt Mask Register 2 */
+#define M6811_TFLG2	0x25	/* Timer Interrupt Flag Register 2 */
+#define M6811_PACTL	0x26	/* Pulse Accumulator Control Register */
+#define M6811_PACNT	0x27	/* Pulse Accumulator Count Register */
+#define M6811_SPCR	0x28	/* SPI Control register */
+#define M6811_SPSR	0x29	/* SPI Status register */
+#define M6811_SPDR	0x2A	/* SPI Data register */
+#define M6811_BAUD	0x2B	/* SCI Baud register */
+#define M6811_SCCR1	0x2C	/* SCI Control register 1 */
+#define M6811_SCCR2	0x2D	/* SCI Control register 2 */
+#define M6811_SCSR	0x2E	/* SCI Status register */
+#define M6811_SCDR	0x2F	/* SCI Data (Read => RDR, Write => TDR) */
+#define M6811_ADCTL	0x30	/* A/D Control register */
+#define M6811_ADR1	0x31	/* A/D, Analog Result register 1 */
+#define M6811_ADR2	0x32	/* A/D, Analog Result register 2 */
+#define M6811_ADR3	0x33	/* A/D, Analog Result register 3 */
+#define M6811_ADR4	0x34	/* A/D, Analog Result register 4 */
+#define M6811__RES35	0x35
+#define M6811__RES36	0x36
+#define M6811__RES37	0x37
+#define M6811__RES38	0x38
+#define M6811_OPTION	0x39	/* System Configuration Options */
+#define M6811_COPRST	0x3A	/* Arm/Reset COP Timer Circuitry */
+#define M6811_PPROG	0x3B	/* EEPROM Programming Control Register */
+#define M6811_HPRIO	0x3C	/* Highest priority I-Bit int and misc */
+#define M6811_INIT	0x3D	/* Ram and I/O mapping register */
+#define M6811_TEST1	0x3E	/* Factory test control register */
+#define M6811_CONFIG	0x3F	/* COP, ROM and EEPROM enables */
+
+
+/* Flags of the CONFIG register (in EEPROM).  */
+#define M6811_NOSEC     0x08    /* Security mode disable */
+#define M6811_NOCOP     0x04    /* COP system disable */
+#define M6811_ROMON     0x02    /* Enable on-chip rom */
+#define M6811_EEON      0x01    /* Enable on-chip eeprom */
+
+/* Flags of the PPROG register.  */
+#define M6811_BYTE	0x10	/* Byte mode */
+#define M6811_ROW       0x08	/* Row mode */
+#define M6811_ERASE	0x04	/* Erase mode select (1 = erase, 0 = read) */
+#define M6811_EELAT     0x02	/* EEPROM Latch Control */
+#define M6811_EEPGM     0x01	/* EEPROM Programming Voltage Enable */
+
+/* Flags of the PIOC register.  */
+#define M6811_STAF	0x80	/* Strobe A Interrupt Status Flag */
+#define M6811_STAI	0x40	/* Strobe A Interrupt Enable Mask */
+#define M6811_CWOM	0x20	/* Port C Wire OR mode */
+#define M6811_HNDS	0x10	/* Handshake mode */
+#define M6811_OIN	0x08	/* Output or Input handshaking */
+#define M6811_PLS	0x04	/* Pulse/Interlocked Handshake Operation */
+#define M6811_EGA	0x02	/* Active Edge for Strobe A */
+#define M6811_INVB	0x01	/* Invert Strobe B */
+
+/* Flags of the SCCR1 register.  */
+#define M6811_R8	0x80	/* Receive Data bit 8 */
+#define M6811_T8	0x40	/* Transmit data bit 8 */
+#define M6811__SCCR1_5  0x20	/* Unused */
+#define M6811_M		0x10	/* SCI Character length */
+#define M6811_WAKE	0x08	/* Wake up method select (0=idle, 1=addr mark) */
+
+/* Flags of the SCCR2 register.  */
+#define M6811_TIE	0x80	/* Transmit Interrupt enable */
+#define M6811_TCIE	0x40	/* Transmit Complete Interrupt Enable */
+#define M6811_RIE	0x20	/* Receive Interrupt Enable */
+#define M6811_ILIE	0x10	/* Idle Line Interrupt Enable */
+#define M6811_TE	0x08	/* Transmit Enable */
+#define M6811_RE	0x04	/* Receive Enable */
+#define M6811_RWU	0x02	/* Receiver Wake Up */
+#define M6811_SBK	0x01	/* Send Break */
+
+/* Flags of the SCSR register.  */
+#define M6811_TDRE	0x80	/* Transmit Data Register Empty */
+#define M6811_TC	0x40	/* Transmit Complete */
+#define M6811_RDRF	0x20	/* Receive Data Register Full */
+#define M6811_IDLE	0x10	/* Idle Line Detect */
+#define M6811_OR	0x08	/* Overrun Error */
+#define M6811_NF	0x04	/* Noise Flag */
+#define M6811_FE	0x02	/* Framing Error */
+#define M6811__SCSR_0	0x01	/* Unused */
+
+/* Flags of the BAUD register.  */
+#define M6811_TCLR	0x80	/* Clear Baud Rate (TEST mode) */
+#define M6811__BAUD_6	0x40	/* Not used */
+#define M6811_SCP1	0x20	/* SCI Baud rate prescaler select */
+#define M6811_SCP0	0x10
+#define M6811_RCKB	0x08	/* Baud Rate Clock Check (TEST mode) */
+#define M6811_SCR2	0x04	/* SCI Baud rate select */
+#define M6811_SCR1	0x02
+#define M6811_SCR0	0x01
+
+#define M6811_BAUD_DIV_1	(0)
+#define M6811_BAUD_DIV_3	(M6811_SCP0)
+#define M6811_BAUD_DIV_4	(M6811_SCP1)
+#define M6811_BAUD_DIV_13	(M6811_SCP1|M6811_SCP0)
+
+/* Flags of the SPCR register.  */
+#define M6811_SPIE	0x80	/* Serial Peripheral Interrupt Enable */
+#define M6811_SPE	0x40	/* Serial Peripheral System Enable */
+#define M6811_DWOM	0x20	/* Port D Wire-OR mode option */
+#define M6811_MSTR	0x10	/* Master Mode Select */
+#define M6811_CPOL	0x08	/* Clock Polarity */
+#define M6811_CPHA	0x04	/* Clock Phase */
+#define M6811_SPR1	0x02	/* SPI Clock Rate Select */
+#define M6811_SPR0	0x01
+
+/* Flags of the SPSR register.  */
+#define M6811_SPIF	0x80	/* SPI Transfer Complete flag */
+#define M6811_WCOL	0x40	/* Write Collision */
+#define M6811_MODF	0x20	/* Mode Fault */
+
+/* Flags of the ADCTL register.  */
+#define M6811_CCF	0x80	/* Conversions Complete Flag */
+#define M6811_SCAN	0x20	/* Continuous Scan Control */
+#define M6811_MULT	0x10	/* Multiple Channel/Single Channel Control */
+#define M6811_CD	0x08	/* Channel Select D */
+#define M6811_CC	0x04	/*                C */
+#define M6811_CB	0x02	/*                B */
+#define M6811_CA	0x01	/*                A */
+
+/* Flags of the CFORC register.  */
+#define M6811_FOC1	0x80	/* Force Output Compare 1 */
+#define M6811_FOC2	0x40	/*			2 */
+#define M6811_FOC3	0x20	/*			3 */
+#define M6811_FOC4	0x10	/*			4 */
+#define M6811_FOC5	0x08	/*			5 */
+
+/* Flags of the OC1M register.  */
+#define M6811_OC1M7	0x80	/* Output Compare 7 */
+#define M6811_OC1M6	0x40	/*                6 */
+#define M6811_OC1M5	0x40	/*                5 */
+#define M6811_OC1M4	0x40	/*                4 */
+#define M6811_OC1M3	0x08	/*                3 */
+
+/* Flags of the OC1D register.  */
+#define M6811_OC1D7	0x80
+#define M6811_OC1D6	0x40
+#define M6811_OC1D5	0x20
+#define M6811_OC1D4	0x10
+#define M6811_OC1D3	0x08
+
+/* Flags of the TCTL1 register.  */
+#define M6811_OM2	0x80	/* Output Mode 2 */
+#define M6811_OL2	0x40	/* Output Level 2 */
+#define M6811_OM3	0x20
+#define M6811_OL3	0x10
+#define M6811_OM4	0x08
+#define M6811_OL4	0x04
+#define M6811_OM5	0x02
+#define M6811_OL5	0x01
+
+/* Flags of the TCTL2 register.  */
+#define M6811_EDG1B	0x20	/* Input Edge Capture Control 1 */
+#define M6811_EDG1A	0x10
+#define M6811_EDG2B	0x08	/* Input 2 */
+#define M6811_EDG2A	0x04
+#define M6811_EDG3B	0x02	/* Input 3 */
+#define M6811_EDG3A	0x01
+
+/* Flags of the TMSK1 register.  */
+#define M6811_OC1I	0x80	/* Output Compare 1 Interrupt */
+#define M6811_OC2I	0x40	/*		  2	      */
+#define M6811_OC3I	0x20	/*		  3	      */
+#define M6811_OC4I	0x10	/*		  4	      */
+#define M6811_OC5I	0x08	/*		  5	      */
+#define M6811_IC1I	0x04	/* Input Capture  1 Interrupt */
+#define M6811_IC2I	0x02	/*		  2	      */
+#define M6811_IC3I	0x01	/*		  3	      */
+
+/* Flags of the TFLG1 register.  */
+#define M6811_OC1F	0x80	/* Output Compare 1 Flag */
+#define M6811_OC2F	0x40	/*		  2	 */
+#define M6811_OC3F	0x20	/*		  3	 */
+#define M6811_OC4F	0x10	/*		  4	 */
+#define M6811_OC5F	0x08	/*		  5	 */
+#define M6811_IC1F	0x04	/* Input Capture  1 Flag */
+#define M6811_IC2F	0x02	/*		  2	 */
+#define M6811_IC3F	0x01	/*		  3	 */
+
+/* Flags of Timer Interrupt Mask Register 2 (TMSK2).  */
+#define M6811_TOI       0x80    /* Timer Overflow Interrupt Enable */
+#define M6811_RTII      0x40    /* RTI Interrupt Enable */
+#define M6811_PAOVI     0x20    /* Pulse Accumulator Overflow Interrupt En. */
+#define M6811_PAII      0x10    /* Pulse Accumulator Interrupt Enable */
+#define M6811_PR1       0x02    /* Timer prescaler */
+#define M6811_PR0       0x01    /* Timer prescaler */
+#define M6811_TPR_1     0x00    /* " " prescale div 1 */
+#define M6811_TPR_4     0x01    /* " " prescale div 4 */
+#define M6811_TPR_8     0x02    /* " " prescale div 8 */
+#define M6811_TPR_16    0x03    /* " " prescale div 16 */
+
+/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2).  */
+#define M6811_TOF       0x80    /* Timer overflow bit */
+#define M6811_RTIF      0x40    /* Read time interrupt flag */
+#define M6811_PAOVF     0x20    /* Pulse accumulator overflow Interrupt flag */
+#define M6811_PAIF      0x10    /* Pulse accumulator Input Edge " " " */
+
+/* Flags of Pulse Accumulator Control Register (PACTL).  */
+#define M6811_DDRA7     0x80    /* Data direction for port A bit 7 */
+#define M6811_PAEN      0x40    /* Pulse accumulator system enable */
+#define M6811_PAMOD     0x20    /* Pulse accumulator mode */
+#define M6811_PEDGE     0x10    /* Pulse accumulator edge control */
+#define M6811_RTR1      0x02    /* RTI Interrupt rates select */
+#define M6811_RTR0      0x01    /* " " " " */
+
+/* Flags of the Options register.  */
+#define M6811_ADPU      0x80    /* A/D Powerup */
+#define M6811_CSEL      0x40    /* A/D/EE Charge pump clock source select */
+#define M6811_IRQE      0x20    /* IRQ Edge/Level sensitive */
+#define M6811_DLY       0x10    /* Stop exit turn on delay */
+#define M6811_CME       0x08    /* Clock Monitor enable */
+#define M6811_CR1       0x02    /* COP timer rate select */
+#define M6811_CR0       0x01    /* COP timer rate select */
+
+/* Flags of the HPRIO register.  */
+#define M6811_RBOOT	0x80	/* Read Bootstrap ROM */
+#define M6811_SMOD	0x40	/* Special Mode */
+#define M6811_MDA	0x20	/* Mode Select A */
+#define M6811_IRV	0x10	/* Internal Read Visibility */
+#define M6811_PSEL3	0x08	/* Priority Select */
+#define M6811_PSEL2	0x04
+#define M6811_PSEL1	0x02
+#define M6811_PSEL0	0x01
+
+/* Some insns used by gas to turn relative branches into absolute ones.  */
+#define M6811_BRA	0x20
+#define M6811_JMP	0x7e
+#define M6811_BSR	0x8d
+#define M6811_JSR	0xbd
+#define M6812_JMP       0x06
+#define M6812_BSR       0x07
+#define M6812_JSR       0x16
+
+/* Instruction code pages. Code page 1 is the default.  */
+/*#define	M6811_OPCODE_PAGE1	0x00*/
+#define	M6811_OPCODE_PAGE2	0x18
+#define	M6811_OPCODE_PAGE3	0x1A
+#define	M6811_OPCODE_PAGE4	0xCD
+
+
+/* 68HC11 operands formats as stored in the m6811_opcode table.  These
+   flags do not correspond to anything in the 68HC11 or 68HC12.
+   They are only used by GAS to recognize operands.  */
+#define M6811_OP_NONE         0        /* No operand */
+#define M6811_OP_DIRECT       0x0001   /* Page 0 addressing:   *<val-8bits>  */
+#define M6811_OP_IMM8         0x0002   /*  8 bits immediat:    #<val-8bits>  */
+#define M6811_OP_IMM16        0x0004   /* 16 bits immediat:    #<val-16bits> */
+#define M6811_OP_IND16        0x0008   /* Indirect abs:        <val-16>      */
+#define M6812_OP_IND16_P2     0x0010   /* Second parameter indirect abs.     */
+#define M6812_OP_REG          0x0020   /* Register operand 1                 */
+#define M6812_OP_REG_2        0x0040   /* Register operand 2                 */
+
+#define M6811_OP_IX           0x0080   /* Indirect IX:         <val-8>,x     */
+#define M6811_OP_IY           0x0100   /* Indirect IY:         <val-8>,y     */
+#define M6812_OP_IDX          0x0200   /* Indirect: N,r N,[+-]r[+-] N:5-bits */
+#define M6812_OP_IDX_1        0x0400   /* N,r N:9-bits  */
+#define M6812_OP_IDX_2        0x0800   /* N,r N:16-bits */
+#define M6812_OP_D_IDX        0x1000   /* Indirect indexed: [D,r] */
+#define M6812_OP_D_IDX_2      0x2000   /* [N,r] N:16-bits */
+#define M6811_OP_MASK         0x0FFFF
+#define M6811_OP_BITMASK      0x00010000 /* Bitmask:             #<val-8>    */
+#define M6811_OP_JUMP_REL     0x00020000 /* Pc-Relative:         <val-8>     */
+#define M6812_OP_JUMP_REL16   0x00040000 /* Pc-relative:         <val-16>    */
+#define M6811_OP_PAGE1        0x0000
+#define M6811_OP_PAGE2        0x00080000 /* Need a page2 opcode before       */
+#define M6811_OP_PAGE3        0x00100000 /* Need a page3 opcode before       */
+#define M6811_OP_PAGE4        0x00200000 /* Need a page4 opcode before       */
+#define M6811_MAX_OPERANDS    3     /* Max operands: brset <dst> <mask> <b> */
+
+#define M6812_ACC_OFFSET      0x00400000 /* A,r B,r D,r			    */
+#define M6812_ACC_IND         0x00800000 /* [D,r]			    */
+#define M6812_PRE_INC         0x01000000 /* n,+r   n = -8..8		    */
+#define M6812_PRE_DEC         0x02000000 /* n,-r			    */
+#define M6812_POST_INC        0x04000000 /* n,r+			    */
+#define M6812_POST_DEC        0x08000000 /* n,r-			    */
+#define M6812_INDEXED_IND     0x10000000 /* [n,r]  n = 16-bits		    */
+#define M6812_INDEXED         0x20000000 /* n,r    n = 5, 9 or 16-bits	    */
+#define M6812_OP_IDX_P2       0x40000000
+
+/* Markers to identify some instructions.  */
+#define M6812_OP_EXG_MARKER   0x01000000 /* exg r1,r2 */
+#define M6812_OP_TFR_MARKER   0x02000000 /* tfr r1,r2 */
+#define M6812_OP_SEX_MARKER   0x04000000 /* sex r1,r2 */
+
+#define M6812_OP_EQ_MARKER    0x80000000 /* dbeq/ibeq/tbeq */
+#define M6812_OP_DBCC_MARKER  0x04000000 /* dbeq/dbne */
+#define M6812_OP_IBCC_MARKER  0x02000000 /* ibeq/ibne */
+#define M6812_OP_TBCC_MARKER  0x01000000
+
+#define M6812_OP_TRAP_ID      0x80000000 /* trap #N */
+
+#define M6811_OP_HIGH_ADDR    0x01000000 /* Used internally by gas.  */
+#define M6811_OP_LOW_ADDR     0x02000000
+
+/* CPU identification.  */
+#define cpu6811 0x01
+#define cpu6812 0x02
+
+/* The opcode table is an array of struct m68hc11_opcode.  */
+struct m68hc11_opcode {
+  const char*    name;     /* Op-code name */
+  long           format;
+  unsigned char  size;
+  unsigned char  opcode;
+  unsigned char  cycles_low;
+  unsigned char  cycles_high;
+  unsigned char  set_flags_mask;
+  unsigned char  clr_flags_mask;
+  unsigned char  chg_flags_mask;
+  unsigned char  arch;
+};
+
+/* Alias definition for 68HC12.  */
+struct m68hc12_opcode_alias 
+{
+  const char*   name;
+  const char*   translation;
+  unsigned char size;
+  unsigned char code1;
+  unsigned char code2;
+};
+
+/* The opcode table.  The table contains all the opcodes (all pages).
+   You can't rely on the order.  */
+extern const struct m68hc11_opcode m68hc11_opcodes[];
+extern const int m68hc11_num_opcodes;
+
+/* Alias table for 68HC12.  It translates some 68HC11 insn which are not
+   implemented in 68HC12 but have equivalent translations.  */
+extern const struct m68hc12_opcode_alias m68hc12_alias[];
+extern const int m68hc12_num_alias;
+
+#endif /* _OPCODE_M68HC11_H */
+
diff --git a/gnu/usr.bin/binutils/include/opcode/pj.h b/gnu/usr.bin/binutils/include/opcode/pj.h
index 8759b627e3d..b768f11bdb9 100644
--- a/gnu/usr.bin/binutils/include/opcode/pj.h
+++ b/gnu/usr.bin/binutils/include/opcode/pj.h
@@ -1,5 +1,5 @@
 /* Definitions for decoding the picoJava opcode table.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright 1999 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
 
 This program is free software; you can redistribute it and/or modify
diff --git a/gnu/usr.bin/binutils/include/opcode/tic54x.h b/gnu/usr.bin/binutils/include/opcode/tic54x.h
new file mode 100644
index 00000000000..09ee8c90370
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/opcode/tic54x.h
@@ -0,0 +1,167 @@
+/* tic54x.h -- Header file for TI TMS320C54X opcode table
+   Copyright 1999, 2000 Free Software Foundation, Inc.
+   Written by Timothy Wall (twall@cygnus.com)
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
+
+#ifndef _TIC54X_H_
+#define _TIC54X_H_
+
+typedef struct _symbol
+{
+  const char *name;
+  unsigned short value;
+} symbol;
+
+enum optype {
+  OPT = 0x8000,
+  OP_None = 0x0,
+
+  OP_Xmem, /* AR3 or AR4, indirect */
+  OP_Ymem, /* AR3 or AR4, indirect */
+  OP_pmad, /* PROG mem, direct */
+  OP_dmad, /* DATA mem, direct */
+  OP_Smem,
+  OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
+  OP_MMR,
+  OP_PA,
+  OP_Sind,
+  OP_xpmad,
+  OP_xpmad_ms7,
+  OP_MMRX,
+  OP_MMRY,
+
+  OP_SRC1, /* src accumulator in bit 8 */
+  OP_SRC, /* src accumulator in bit 9 */
+  OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
+  OP_DST, /* dst accumulator in bit 8 */
+  OP_ARX, /* arX in bits 0-3 */
+  OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
+  OP_SHFT, /*   0 to 15 (SHIFT1 in summary), bits 0-3 */
+  OP_B, /* ACC B only */
+  OP_A, /* ACC A only */
+
+  OP_lk, /* 16-bit immediate, '#' optional */
+  OP_TS,
+  OP_k8, /* -128 <= k <= 128 */
+  OP_16, /* literal "16" */
+  OP_BITC, /* 0 to 16 */
+  OP_CC, /* condition code */
+  OP_CC2, /* 4-bit condition code */
+  OP_CC3, /* 2-bit condition code */
+  OP_123, /* 1, 2, or 3 */
+  OP_031, /* 0-31, numeric */
+  OP_k5, /* 0 to 31 */
+  OP_k8u, /* 0 to 255 */
+  OP_ASM, /* "ASM" */
+  OP_T, /* "T" */
+  OP_DP, /* "DP" */
+  OP_ARP, /* "ARP" */
+  OP_k3, /* 0-7 */
+  OP_lku, /* 0 to 65535 */
+  OP_N, /* 0/1 or ST0/ST1 */
+  OP_SBIT, /* status bit or 0-15 */
+  OP_12, /* one or two */
+  OP_k9, /* 9 bits of data page (DP) address */
+  OP_TRN, /* "TRN" */
+
+};
+
+typedef struct _template
+{
+  /* The opcode mnemonic */
+  const char *name;
+
+  unsigned int words; /* insn size in words */
+  int minops, maxops; /* min/max operand count */
+  /* The significant bits in the opcode.  Other bits are zero. 
+     Instructions with more than 16 bits of opcode store the rest in the upper
+     16 bits.
+   */
+  unsigned short opcode;
+#define INDIRECT(OP)    ((OP)&0x80)
+#define MOD(OP)         (((OP)>>3)&0xF)
+#define ARF(OP)         ((OP)&0x7)
+#define IS_LKADDR(OP)   (INDIRECT(OP) && MOD(OP)>=12)
+#define SRC(OP)         ((OP)&0x200)
+#define DST(OP)         ((OP)&0x100)
+#define SRC1(OP)        ((OP)&0x100)
+#define SHIFT(OP)       (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
+#define SHFT(OP)        ((OP)&0xF)
+#define ARX(OP)         ((OP)&0x7)
+#define XMEM(OP)        (((OP)&0x00F0)>>4)
+#define YMEM(OP)        ((OP)&0x000F)
+#define XMOD(C)        (((C)&0xC)>>2)
+#define XARX(C)        (((C)&0x3)+2)
+#define CC3(OP)         (((OP)>>8)&0x3)
+#define SBIT(OP)        ((OP)&0xF)
+#define MMR(OP)         ((OP)&0x7F)
+#define MMRX(OP)        ((((OP)>>4)&0xF)+16)
+#define MMRY(OP)        (((OP)&0xF)+16)
+
+#define OPTYPE(X)       ((X)&~OPT)
+
+  /* Ones in this mask indicate which bits must match the opcode field.
+     Zeroes indicate don't care bits (operands and/or opcode options) */
+  unsigned short mask;
+
+  /* An array of operand codes (at most 4 operands) */
+#define MAX_OPERANDS 4
+  enum optype operand_types[MAX_OPERANDS];
+
+  /* Special purpose flags (e.g. branch type, parallel, delay, etc) 
+   */
+  unsigned short flags;
+#define B_NEXT      0 /* normal execution, next insn is next address */
+#define B_BRANCH    1 /* next insn is in opcode */
+#define B_RET       2 /* next insn is on stack */
+#define B_BACC      3 /* next insn is in acc */
+#define B_REPEAT    4 /* next insn repeats */
+#define FL_BMASK    0x07
+
+#define FL_DELAY    0x10 /* instruction uses delay slots */
+#define FL_EXT      0x20 /* instruction takes two words */   
+#define FL_FAR      0x40 /* far mode addressing */
+#define FL_LP       0x80 /* LP-only instruction */
+#define FL_NR       0x100 /* no repeat allowed */
+#define FL_SMR      0x200 /* Smem read (for flagging write-only *+ARx */
+
+  unsigned short opcode2, mask2;   /* some insns have an extended opcode */
+
+} template;
+
+typedef struct _partemplate {
+  char *name;
+  char *parname;
+  unsigned int words; /* length in words */
+  int minops, maxops; /* min/max operand count for 2nd part of insn */
+  unsigned short opcode;
+  unsigned short mask;
+  enum optype operand_types[MAX_OPERANDS];
+  enum optype paroperand_types[MAX_OPERANDS];
+} partemplate;
+
+extern const template tic54x_unknown_opcode;
+extern const template tic54x_optab[];
+extern const partemplate tic54x_paroptab[];
+extern const symbol mmregs[], regs[];
+extern const symbol condition_codes[], cc2_codes[], status_bits[];
+extern const symbol cc3_codes[];
+extern const char *misc_symbols[];
+
+#endif /* TIC54X_H */
diff --git a/gnu/usr.bin/binutils/include/opcode/tic80.h b/gnu/usr.bin/binutils/include/opcode/tic80.h
index b99bc30b818..01159e46b1c 100644
--- a/gnu/usr.bin/binutils/include/opcode/tic80.h
+++ b/gnu/usr.bin/binutils/include/opcode/tic80.h
@@ -1,5 +1,5 @@
 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
-   Copyright 1996, 1997, 1999 Free Software Foundation, Inc.
+   Copyright 1996, 1997 Free Software Foundation, Inc.
    Written by Fred Fish (fnf@cygnus.com), Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
diff --git a/gnu/usr.bin/binutils/include/opcode/v850.h b/gnu/usr.bin/binutils/include/opcode/v850.h
index 88916f1b848..737faf88d0d 100644
--- a/gnu/usr.bin/binutils/include/opcode/v850.h
+++ b/gnu/usr.bin/binutils/include/opcode/v850.h
@@ -1,5 +1,5 @@
 /* v850.h -- Header file for NEC V850 opcode table
-   Copyright 1996 Free Software Foundation, Inc.
+   Copyright 1996, 1997 Free Software Foundation, Inc.
    Written by J.T. Conklin, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
diff --git a/gnu/usr.bin/binutils/include/partition.h b/gnu/usr.bin/binutils/include/partition.h
index f49d67a8cad..091655ac01d 100644
--- a/gnu/usr.bin/binutils/include/partition.h
+++ b/gnu/usr.bin/binutils/include/partition.h
@@ -1,5 +1,5 @@
-/* List implentation of a partition of consecutive integers.
-   Copyright (C) 2000 Free Software Foundation, Inc.
+/* List implementation of a partition of consecutive integers.
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
    Contributed by CodeSourcery, LLC.
 
    This file is part of GNU CC.
diff --git a/gnu/usr.bin/binutils/include/safe-ctype.h b/gnu/usr.bin/binutils/include/safe-ctype.h
new file mode 100644
index 00000000000..6d4d10a830a
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/safe-ctype.h
@@ -0,0 +1,100 @@
+/* <ctype.h> replacement macros.
+
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Zack Weinberg <zackw@stanford.edu>.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.  If
+not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This is a compatible replacement of the standard C library's <ctype.h>
+   with the following properties:
+
+   - Implements all isxxx() macros required by C99.
+   - Also implements some character classes useful when
+     parsing C-like languages.
+   - Does not change behavior depending on the current locale.
+   - Behaves properly for all values in the range of a signed or
+     unsigned char.
+
+   To avoid conflicts, this header defines the isxxx functions in upper
+   case, e.g. ISALPHA not isalpha.  */
+
+#ifndef SAFE_CTYPE_H
+#define SAFE_CTYPE_H
+
+#ifdef isalpha
+ #error "safe-ctype.h and ctype.h may not be used simultaneously"
+#else
+
+/* Categories.  */
+
+enum {
+  /* In C99 */
+  _sch_isblank  = 0x0001,	/* space \t */
+  _sch_iscntrl  = 0x0002,	/* nonprinting characters */
+  _sch_isdigit  = 0x0004,	/* 0-9 */
+  _sch_islower  = 0x0008,	/* a-z */
+  _sch_isprint  = 0x0010,	/* any printing character including ' ' */
+  _sch_ispunct  = 0x0020,	/* all punctuation */
+  _sch_isspace  = 0x0040,	/* space \t \n \r \f \v */
+  _sch_isupper  = 0x0080,	/* A-Z */
+  _sch_isxdigit = 0x0100,	/* 0-9A-Fa-f */
+
+  /* Extra categories useful to cpplib.  */
+  _sch_isidst	= 0x0200,	/* A-Za-z_ */
+  _sch_isvsp    = 0x0400,	/* \n \r */
+  _sch_isnvsp   = 0x0800,	/* space \t \f \v \0 */
+
+  /* Combinations of the above.  */
+  _sch_isalpha  = _sch_isupper|_sch_islower,	/* A-Za-z */
+  _sch_isalnum  = _sch_isalpha|_sch_isdigit,	/* A-Za-z0-9 */
+  _sch_isidnum  = _sch_isidst|_sch_isdigit,	/* A-Za-z0-9_ */
+  _sch_isgraph  = _sch_isalnum|_sch_ispunct,	/* isprint and not space */
+  _sch_iscppsp  = _sch_isvsp|_sch_isnvsp	/* isspace + \0 */
+};
+
+/* Character classification.  */
+extern const unsigned short _sch_istable[256];
+
+#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (bit))
+
+#define ISALPHA(c)  _sch_test(c, _sch_isalpha)
+#define ISALNUM(c)  _sch_test(c, _sch_isalnum)
+#define ISBLANK(c)  _sch_test(c, _sch_isblank)
+#define ISCNTRL(c)  _sch_test(c, _sch_iscntrl)
+#define ISDIGIT(c)  _sch_test(c, _sch_isdigit)
+#define ISGRAPH(c)  _sch_test(c, _sch_isgraph)
+#define ISLOWER(c)  _sch_test(c, _sch_islower)
+#define ISPRINT(c)  _sch_test(c, _sch_isprint)
+#define ISPUNCT(c)  _sch_test(c, _sch_ispunct)
+#define ISSPACE(c)  _sch_test(c, _sch_isspace)
+#define ISUPPER(c)  _sch_test(c, _sch_isupper)
+#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit)
+
+#define ISIDNUM(c)	_sch_test(c, _sch_isidnum)
+#define ISIDST(c)	_sch_test(c, _sch_isidst)
+#define IS_VSPACE(c)	_sch_test(c, _sch_isvsp)
+#define IS_NVSPACE(c)	_sch_test(c, _sch_isnvsp)
+#define IS_SPACE_OR_NUL(c)	_sch_test(c, _sch_iscppsp)
+
+/* Character transformation.  */
+extern const unsigned char  _sch_toupper[256];
+extern const unsigned char  _sch_tolower[256];
+#define TOUPPER(c) _sch_toupper[(c) & 0xff]
+#define TOLOWER(c) _sch_tolower[(c) & 0xff]
+
+#endif /* no ctype.h */
+#endif /* SAFE_CTYPE_H */
diff --git a/gnu/usr.bin/binutils/include/sort.h b/gnu/usr.bin/binutils/include/sort.h
new file mode 100644
index 00000000000..c8e1d5547d1
--- /dev/null
+++ b/gnu/usr.bin/binutils/include/sort.h
@@ -0,0 +1,48 @@
+/* Sorting algorithms.
+   Copyright (C) 2000 Free Software Foundation, Inc.
+   Contributed by Mark Mitchell <mark@codesourcery.com>.
+
+This file is part of GNU CC.
+   
+GNU CC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef SORT_H
+#define SORT_H
+
+#include <sys/types.h> /* For size_t */
+#ifdef __STDC__
+#include <stddef.h>
+#endif	/* __STDC__ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <ansidecl.h>
+
+/* Sort an array of pointers.  */
+
+extern void sort_pointers PARAMS ((size_t, void **, void **));
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SORT_H */
+
+
+   
+   
diff --git a/gnu/usr.bin/binutils/include/splay-tree.h b/gnu/usr.bin/binutils/include/splay-tree.h
index 6d70c8d9075..e43d4b62eaa 100644
--- a/gnu/usr.bin/binutils/include/splay-tree.h
+++ b/gnu/usr.bin/binutils/include/splay-tree.h
@@ -1,5 +1,5 @@
 /* A splay-tree datatype.  
-   Copyright (C) 1998 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
    Contributed by Mark Mitchell (mark@markmitchell.com).
 
 This file is part of GNU CC.
@@ -99,9 +99,17 @@ extern splay_tree_node splay_tree_insert
 		                        PARAMS((splay_tree,
 					        splay_tree_key,
 					        splay_tree_value));
+extern void splay_tree_remove		PARAMS((splay_tree,
+						splay_tree_key));
 extern splay_tree_node splay_tree_lookup   
                                         PARAMS((splay_tree,
 					        splay_tree_key));
+extern splay_tree_node splay_tree_predecessor
+                                        PARAMS((splay_tree,
+						splay_tree_key));
+extern splay_tree_node splay_tree_successor
+                                        PARAMS((splay_tree,
+						splay_tree_key));
 extern int splay_tree_foreach           PARAMS((splay_tree,
 					        splay_tree_foreach_fn,
 					        void*));
diff --git a/gnu/usr.bin/binutils/include/symcat.h b/gnu/usr.bin/binutils/include/symcat.h
index 3e27162b264..61ce1e9b341 100644
--- a/gnu/usr.bin/binutils/include/symcat.h
+++ b/gnu/usr.bin/binutils/include/symcat.h
@@ -19,12 +19,16 @@
 #ifndef SYM_CAT_H
 #define SYM_CAT_H
 
-#if defined (__STDC__) || defined (ALMOST_STDC)
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define CONCAT2(a,b)	 a##b
 #define CONCAT3(a,b,c)	 a##b##c
 #define CONCAT4(a,b,c,d) a##b##c##d
 #define STRINGX(s) #s
 #else
+/* Note one should never pass extra whitespace to the CONCATn macros,
+   e.g. CONCAT2(foo, bar) because traditonal C will keep the space between
+   the two labels instead of concatenating them.  Instead, make sure to
+   write CONCAT2(foo,bar).  */
 #define CONCAT2(a,b)	 a/**/b
 #define CONCAT3(a,b,c)	 a/**/b/**/c
 #define CONCAT4(a,b,c,d) a/**/b/**/c/**/d
@@ -35,6 +39,11 @@
 #define XCONCAT3(a,b,c)   CONCAT3(a,b,c)
 #define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d)
 
+/* Note the layer of indirection here is typically used to allow
+   stringification of the expansion of macros.  I.e. "#define foo
+   bar", "XSTRING(foo)", to yield "bar".  Be aware that this only
+   works for __STDC__, not for traditional C which will still resolve
+   to "foo".  */
 #define XSTRING(s) STRINGX(s) 
 
-#endif SYM_CAT_H
+#endif /* SYM_CAT_H */