Binutils 2.15, with testsuites removed, and without gdb and libiberty.

93 files changed, 16773 insertions, 3605 deletions

diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog-0001 b/gnu/usr.bin/binutils/opcodes/ChangeLog-0001
new file mode 100644
index 00000000000..085453a34e9
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/ChangeLog-0001
@@ -0,0 +1,2224 @@
+2001-12-31  Jeffrey A Law  (law@redhat.com)
+
+	* hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers,
+	'X', 'M', and 'A'.  No longer emit a space after 'x' or 's'.
+	Always emit a space after 'H'.
+
+2001-12-18  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY.
+
+2001-12-17  Richard Henderson  <rth@redhat.com>
+
+	* alpha-opc.c (unop): Encode with RB as $sp.
+
+2001-12-07  Geoffrey Keating  <geoffk@redhat.com>
+
+	* Makefile.am: Add support for xstormy16.
+	* Makefile.in: Regenerate.
+	* configure.in: Add support for xstormy16.
+	* configure: Regenerate.
+	* disassemble.c: Add support for xstormy16.
+	* xstormy16-asm.c: New generated file.
+	* xstormy16-desc.c: New generated file.
+	* xstormy16-desc.h: New generated file.
+	* xstormy16-dis.c: New generated file.
+	* xstormy16-ibld.c: New generated file.
+	* xstormy16-opc.c: New generated file.
+	* xstormy16-opc.h: New generated file.
+
+2001-12-06  Richard Henderson  <rth@redhat.com>
+
+	* alpha-opc.c (alpha_opcodes): Add wh64en.
+
+2001-12-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* d10v-opc.c (d10v_predefined_registers): Remove warnings
+	introduced in Nov 29's patch.
+
+	* d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of
+	unmatched register.
+
+	* d10v-dis.c (print_operand): Disregard OPERAND_SP in register
+	predefined value.
+
+	* d10v-opc.c (RSRC_NOSP): New macro.
+	(d10v_operands): Add it.
+	(d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w".
+
+2001-11-29  Alexandre Oliva  <aoliva@redhat.com>
+
+	* d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP.
+	(RSRC_SP): New macro.
+	(d10v_operands): Add it.
+	(d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP.
+
+2001-11-23  Lars Brinkhoff  <lars@nocrew.org>
+
+	* pdp11-dis.c (print_insn_pdp11): Handle illegal instructions.
+	Also, break out of the loop as soon as an instruction has been
+	printed.
+
+2001-11-17  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (mfvrsave, mtvrsave): New instructions.
+
+2001-11-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+
+	* ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC.
+	(insert_bat, extract_bat, insert_bba, extract_bba,
+	insert_bd, extract_bd, insert_bdm, extract_bdm,
+	insert_bdp, extract_bdp, valid_bo,
+	insert_bo, extract_bo, insert_boe, extract_boe,
+	insert_ds, extract_ds, insert_de, extract_de,
+	insert_des, extract_des, insert_li, extract_li,
+	insert_mbe, extract_mbe, insert_mb6, extract_mb6,
+	insert_nb, extract_nb, insert_nsi, extract_nsi,
+	insert_ral, insert_ram, insert_ras,
+	insert_rbs, extract_rbs, insert_sh6, extract_sh6,
+	insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param.
+	(extract_bd, extract_bdm, extract_bdp,
+	extract_ds, extract_des,
+	extract_li, extract_nsi): Implement sign extension without conditional.
+	(insert_bdm, extract_bdm,
+	insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints.
+	(extract_bdm, extract_bdp): Correct 32 bit validation.
+	(AT1_MASK, AT2_MASK): Define.
+	(BBOAT_MASK): Define.
+	(BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define.
+	(BOFM64, BOFP64, BOTM64, BOTP64): Define.
+	(BODNZM64, BODNZP64, BODZM64, BODZP64): Define.
+	(PPCCOM32, PPCCOM64): Define.
+	(powerpc_opcodes): Modify existing 32 bit insns with branch hints
+	and add new patterns to implement 64 bit branches with hints.  Move
+	booke instructions so they match before ppc64.
+
+	* ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for
+	64 bit default targets, and parse "32" and "64" in options.
+	Formatting fixes.
+	(print_insn_powerpc): Pass dialect to operand->extract.
+
+2001-11-14  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-dis.c (count_decodable_bits): New function.
+	(add_insn_to_hash_chain): New function.
+	(hash_insn_array): Call add_insn_to_hash_chain.
+	(hash_insn_list): Call add_insn_to_hash_chain.
+	* m32r-dis.c: Regenerated.
+	* fr30-dis.c: Regenerated.
+
+2001-11-14  Andreas Jaeger  <aj@suse.de>
+
+	* i386-dis.c (print_insn): Use x86-64 as option.
+
+2001-11-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* disassemble.c (disassembler): Call print_insn_i386.
+	* i386-dis.c (SUFFIX_ALWAYS): Define.
+	(struct dis_private): Add orig_sizeflag.
+	(print_insn_i386): Make it a wrapper, calling..
+	(print_insn): ..The old body of print_insn_i386.  Avoid longjmp
+	warning without using volatile by moving orig_sizeflag to priv,
+	and removing inbuf.  Parse disassembler_options.
+	(print_insn_i386_att, print_insn_i386_intel): Move initialisation
+	code to print_insn.
+	(putop): Remove #ifdef SUFFIX_ALWAYS.
+
+2001-11-11  Timothy Wall  <twall@alum.mit.edu>
+
+	* tic54x-dis.c: Use revised opcode structure.  Export opcode
+	template lookup.
+	(has_lkaddr): Don't forget about Lmem insns.
+	* tic54x-opc.c: Add emulation trap.  Parallel table now uses
+	standard opcode templates.
+
+2001-11-13  Zack Weinberg <zack@codesourcery.com>
+
+	* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
+	to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
+	category instead of Ew.
+
+2001-11-12  Niraj Gupta <ngupta@zumanetworks.com>
+
+	* m68k-opc.c: Fix definitions of wddata[bwl].
+
+2001-11-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen-asm.c (cgen_parse_keyword): If the keyword is too big to
+	fit in the buffer, try to match the empty keyword.
+
+2001-11-09  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* cgen-ibld.in (extract_1): Fix badly placed #if 0.
+	* fr30-ibld.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* openrisc-ibld.c: Regenerate.
+
+2001-11-04  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (print_insn_mips): Remove spaces at end of line.
+
+2001-11-02  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr".
+	* configure: Regernate.
+	* po/fr.po: New file.
+	* po/sv.po: New file.
+	* po/tr.po: New file.
+
+2001-11-01  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* m68hc11-dis.c (print_insn): Fix disassembly of movb with a
+	constant as source.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c.  Regenerate
+	dependencies.
+	* Makefile.in: Regenerate.
+	* mmix-dis.c, mmix-opc.c: New files.
+
+2001-10-29  Kazu Hirata  <kazu@hxi.com>
+
+	* d30v-dis.c: Fix a comment typo.
+
+2001-10-23  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and
+	"bltzall" as writing GPR 31 (since they do).
+
+	* mips-dis.c (print_insn_arg): Calculate info->target
+	where appropriate.
+	(print_insn_mips): Fill in instruction info.
+	(print_mips16_insn_arg): Remove unneded variable 'val'.
+	Removed duplicated instruction target calculations,
+	calculate once and print that result.  Use same idiom for
+	masking the jump segment bits as is used in print_insn_arg.
+
+2001-10-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c (CT): Make it an optional operand.
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_isa_type): Make the ISA used to disassemble
+	SB-1 binaries include instructions specific to the SB-1.
+	* mips-opc.c (SB1): New definition.
+	(mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
+	"recip.ps", "rsqrt.ps", and "sqrt.ps".
+
+2001-10-17  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (STRM): New AltiVec operand.
+	(XDSS): New AltiVec instruction form.
+	(mtvscr): Correct operand list.
+	(dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
+
+2001-10-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+
+2001-10-13  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (MO): New macro for MO field of mbar instruction.
+	(powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr,
+	mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions.
+
+2001-10-13  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* cgen-ibld.in: Include safe-ctype.h in preference to
+	ctype.h.
+	* cgen-asm.in: Include safe-ctype.h in preference to
+	ctype.h.  Fix formatting.  Use ISSPACE instead of isspace and
+	TOLOWER instead of tolower.
+	(@arch@_cgen_build_insn_regex): Remove duplication of syntax
+	string elements in constructed regular expression.
+	* fr30-asm.c: Regenerate.
+	* fr30-desc.c: Regenerate.
+	* fr30-ibld.c: Regenerate.
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* openrisc-asm.c: Regenerate.
+	* openrisc-desc.c: Regenerate.
+	* openrisc-ibld.c: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2001-10-12  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
+	instruction field instruction/extraction functions for new BookE
+	DE form instructions.
+	(CT): New macro for CT field in an X form instruction.
+	(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
+	instructions.
+	(PPC64): Don't include PPC_OPCODE_PPC.
+	(403): New opcode macro for PPC403 processors.
+	(BOOKE): New opcode macro for BookE processors.
+	(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
+	(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
+	(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
+	(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
+	(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
+	(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
+	(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
+	(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
+	(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
+	(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
+	(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
+	(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
+	(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
+	(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
+
+	* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
+	for a disassembler option of `booke', `booke32' or `booke64' to enable
+	BookE support in the disassembler.
+
+2001-10-12  John Healy  <jhealy@redhat.com>
+
+	* cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8)
+	for the length when extracting the base part of the insn.
+
+2001-10-09  Bruno Haible  <haible@clisp.cons.org>
+
+	* cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive
+	regular expression.  Fix some formatting problems.
+	* fr30-asm.c: Regenerate.
+	* openrisc-asm.c: Regenerate.
+	* m32r-asm.c: Regenerate.
+
+2001-10-09  Christian Groessler <cpg@aladdin.de>
+
+	* z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly
+	of indirect register memory accesses to be same format the
+	assembler accepts.
+
+2001-10-09  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* sh-opc.h: Fix encoding of least significant nibble of the
+	DSP single data transfer instructions.
+
+	* sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP
+	instructions.
+
+2001-10-08  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* cgen-asm.in: Fix compile time warning messages in generated
+	C files.
+	* cgen-dis.in: The same.
+	* cgen-ibld.in: The same.
+	* fr30-asm.c: Regenerate.
+	* fr30-desc.c: Regenerate.
+	* fr30-dis.c: Regenerate.
+	* fr30-ibld.c: Regenerate.
+	* fr30-opc.c: Regenerate.
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* m32r-opc.c: Regenerate.
+	* m32r-opinst.c Regenerate.
+	* openrisc-asm.c: Regenerate.
+	* openrisc-desc.c: Regenerate.
+	* openrisc-dis.c: Regenerate.
+	* openrisc-ibld.c: Regenerate.
+	* openrisc-opc.c: Regenerate.
+	* openrisc-opc.h: Regenerate.
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2001-10-08  Aldy Hernandez  <aldyh@redhat.com>
+
+	* arm-opc.h (arm_opcodes): Add cirrus insns.
+
+	* arm-dis.c (print_insn_arm): Add 'I' case.
+
+2001-10-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+	* configure: Regenerate.
+
+2001-10-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (Makefile): Depend on bfd/configure.in.
+	Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2001-09-30  John Healy  <jhealy@redhat.com>
+
+	* cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits
+	calls to cgen_get_insn_value and cgen_put_insn_value calls.
+	(extract_1): Switched bfd_get_bits call to cgen_get_insn_value call.
+
+2001-09-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* Makefile.am: Update dependencies with "make dep-am".
+	* Makefile.in: Regenerate.
+
+2001-09-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* arc-dis.c: Formatting fixes.
+	(my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE.
+
+2001-09-21  Bruno Haible  <haible@clisp.cons.org>
+
+	* arc-dis.c: Don't include <ctype.h>.
+	* openrisc-desc.c: Likewise.
+	* openrisc-ibld.c: Likewise.
+
+2001-09-20  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* fr30-opc.c: Fix compile time warning messages.
+	* i370-opc.c: Fix compile time warning messages.
+	* i960-dis.c: Fix compile time warning messages.
+	* m32r-asm.c: Fix compile time warning messages.
+	* m32r-desc.c: Fix compile time warning messages.
+	* m32r-dis.c: Fix compile time warning messages.
+	* m32r-ibld.c: Fix compile time warning messages.
+	* m32r-opc.c: Fix compile time warning messages.
+	* m32r-opinst.c: Fix compile time warning messages.
+	* ns32k-dis.c: Fix compile time warning messages.
+	* openrisc-asm.c: Fix compile time warning messages.
+	* openrisc-desc.c: Fix compile time warning messages.
+	* openrisc-dis.c: Fix compile time warning messages.
+	* openrisc-ibld.c: Fix compile time warning messages.
+	* openrisc-opc.c: Fix compile time warning messages.
+	* pdp11-dis.c: Fix compile time warning messages.
+	* tic54x-dis.c: Fix compile time warning messages.
+	* v850-opc.c: Fix compile time warning messages.
+	* vax-dis.c: Fix compile time warning messages.
+	* w65-opc.h: Fix compile time warning messages.
+	* z8k-opc.h: Fix compile time warning messages.
+	* z8kgen.c: Fix compile time warning messages.
+
+2001-09-19  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* arm-dis.c:   Fix compile time warning messages.
+	* cgen-asm.c:  Fix compile time warning messages.
+	* cgen-dis.c:  Fix compile time warning messages.
+	* cris-dis.c:  Fix compile time warning messages.
+	* d10v-dis.c:  Fix compile time warning messages.
+	* fr30-asm.c:  Fix compile time warning messages.
+	* fr30-desc.c: Fix compile time warning messages.
+	* fr30-dis.c:  Fix compile time warning messages.
+	* fr30-ibld.c: Fix compile time warning messages.
+
+2001-09-18  Bruno Haible  <haible@clisp.cons.org>
+
+	* cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(cgen_parse_keyword): Use ISALNUM instead of isalnum.
+	* cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of
+	isalpha/tolower.
+	(cgen_keyword_add): Use ISALNUM instead of isalnum.
+	(hash_keyword_name): Use TOLOWER instead of tolower.
+	* fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(parse_insn_normal): Use TOLOWER/ISSPACE instead of
+	tolower/isspace.
+	(fr30_cgen_assemble_insn): Use ISSPACE instead of isspace.
+	* fr30-desc.c: Don't include <ctype.h>.
+	* fr30-ibld.c: Likewise.
+	* ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(load_insn_classes, parse_resource_users, load_depfile): Use
+	ISSPACE instead of isspace.
+	* m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(parse_insn_normal): Use TOLOWER/ISSPACE instead of
+	tolower/isspace.
+	(m32r_cgen_assemble_insn): Use ISSPACE instead of isspace.
+	* m32r-desc.c: Don't include <ctype.h>.
+	* m32r-ibld.c: Likewise.
+	* openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>.
+	(parse_insn_normal): Use TOLOWER/ISSPACE instead of
+	tolower/isspace.
+	(openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace.
+
+2001-09-18  Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+	* Makefile.am: Add rules and dependencies to create the s/390 opcode
+	table out of s390-opc.txt automatically.
+	* configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used.
+	* s390-mkopc.c (dumpTable): Change output to create a complete file.
+	* s390-opc.c: New improved opcode format macros and remove the
+	pregenerated opcode table.
+	* s390-opc.txt: Adapt to new improved opcode format macros.
+
+2001-09-14  David Schleef <ds@schleef.org>
+
+	* ppc-opc.c (VXA, VXA_MASK): Fix mask bits.
+
+2001-09-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (grps): Don't print the implicit al/ax/eax register
+	for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns.
+
+2001-08-31  Eric Christopher  <echristo@redhat.com>
+	    Jason Eckhardt    <jle@redhat.com>
+
+	* mips-dis.c: Add support for bfd_mach_mipsisa32 and
+	bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k,
+	bfd_mach_mips64.
+
+2001-08-31  Andreas Jaeger  <aj@suse.de>
+
+	* tic54x-opc.c: Add default initializers to avoid warnings.
+
+	* arc-opc.c: Include "sysdep.h" to get stdio.h as include file.
+	* arc-ext.c: Likewise.
+
+2001-08-28  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (icbt): Order correctly.
+
+2001-08-27  David Edelsohn  <dje@watson.ibm.com>
+	    Torbjorn Granlund  <tege@swox.com>
+
+	* ppc-opc.c (DS): Add PPC_OPERAND_DS flag.
+	(LS): Define.
+	(insert_ds): Complain if not a multiple of 4.
+	(XSYNC): Define.
+	(XSYNC_MASK): Define.
+	(powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev",
+	"slbmfee".  Modify "sync" to use XSYNC_MASK and LS.
+
+2001-08-26  Andreas Jaeger  <aj@suse.de>
+
+	* h8500-opc.h: Add default initializers to h8500_table to shut up
+	GCC warnings.
+
+2001-08-25  Andreas Jaeger  <aj@suse.de>
+
+	* tic54x-dis.c: Add unused attributes where needed.
+
+	* z8k-dis.c (output_instr): Add unused attribute.
+
+	* h8300-dis.c: Add missing prototypes.
+	(bfd_h8_disassemble): Make static.
+
+	* cris-dis.c: Add missing prototype.
+	* h8500-dis.c: Likewise.
+	* m68hc11-dis.c: Likewise.
+	* pj-dis.c: Likewise.
+	* tic54x-dis.c: Likewise.
+	* v850-dis.c: Likewise.
+	* vax-dis.c: Likewise.
+	* w65-dis.c: Likewise.
+	* z8k-dis.c: Likewise.
+
+	* d10v-dis.c: Add missing prototype.
+	(dis_long): Remove unused variable.
+	(dis_2_short): Likewise.
+
+	* sh-dis.c: Add missing prototypes.
+	* v850-opc.c: Likewise.
+	Add unused attributes where needed.
+
+	* ns32k-dis.c: Add missing prototypes.
+	(bit_extract_simple): Remove unused variable.
+
+2001-08-23  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-opc.c: Add "low or high" and "not low or high"
+	branch instructions for gcc 3.0.
+	* s390-opc.txt: Likewise.
+
+2001-08-21  Andreas Jaeger  <aj@suse.de>
+
+	* i960-dis.c: Add parameters for prototypes
+	(ctrl): Add unused attributes.
+	(cobr): Likewise.
+	(put_abs): Likewise.
+
+	* mips-dis.c: Add missing prototypes.
+	* a29k-dis.c: Likewise.
+	* arc-dis.c: Likewise.
+	* ia64-opc.c: Likewise.
+
+	* s390-dis.c: Add missing prototypes.
+	(init_disasm): Remove unused attribute since the parameter is
+	used.
+
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-opc.c (M1): Define. Reformatted Code.
+	(mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
+	mtps, mtps. Typo.
+
+2001-08-16  Jonathan Larmour  <jlarmour@redhat.com>
+
+	* mips-opc.c: R3900s can support all branch likely INSN_MACROs where
+	the corresponding non-likely insn is in MIPS I.
+
+2001-08-13  Kazu Hirata  <kazu@hxi.com>
+
+	* mcore-dis.c: Fix formatting.
+	* mips-dis.c: Likewise.
+	* pj-dis.c: Likewise.
+	* z8k-dis.c: Likewise.
+
+2001-08-12  Richard Henderson  <rth@redhat.com>
+
+	* cgen-ibld.in (extract_normal): Match type of VALUE and MASK
+	to *VALUEP.  Regenerate all cgen files.
+
+2001-08-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
+	argument.
+	* mips-opc.c (G6): Undefine.
+	(mips_builtin_opcodes): Remove gp32 entry for "move".  Add macro
+	as the first "move" alternative.
+
+2001-08-10  Andreas Jaeger  <aj@suse.de>
+
+	* configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes
+	to build warnings.
+	* configure: Regenerate.
+
+2001-08-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Revert 2001-08-08.
+
+2001-08-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* dis-buf.c (generic_strcat_address): Add missing prototype.
+	#if 0 the functions as it is unused.
+
+2001-08-08  Alan Modra  <amodra@bigpond.net.au>
+
+	1999-10-25  Torbjorn Granlund  <tege@swox.com>
+	* ppc-opc.c: Include "bfd.h".
+	(powerpc_operands): Add new field for reloc type.
+
+2001-07-21  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (print_insn_arg): Don't use software integer registers
+	for coprocessor registers.
+	(get_mips_isa): Removed.
+	(is_newabi): New function, checks if NewABI is used.
+	(_print_insn_mips): Get distinction between old ABI and new ABI right.
+
+2001-08-01  Christian Groessler <cpg@aladdin.de>
+
+	* z8kgen.c: Fixed indentation of opt[] array.  Include stdio.h to
+	get stderr definition.
+	(internal, gas): Removed warnings.
+	(gas): Create a correct final entry for created array.
+	* z8k-opc.h: Recreated with new z8kgen.
+
+2001-07-28  Kazu Hirata  <kazu@hxi.com>
+
+	* i386-dis.c: Fix formatting.
+
+2001-07-28  Matthias Kramm <kramm@quiss.org>
+
+	* i386-dis.c: Change formatting conventions for architecture
+	i386:intel to better match the format of various intel i386
+	assemblers, like nasm, tasm or masm.
+
+2001-07-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Update dependencies with "make dep-am".
+	* Makefile.in: Regenerate
+
+2001-07-24  Kazu Hirata  <kazu@hxi.com>
+
+	* alpha-dis.c: Fix formatting.
+	* cris-dis.c: Likewise.
+	* d10v-dis.c: Likewise.
+	* d30v-dis.c: Likewise.
+	* m10300-dis.c: Likewise.
+	* tic54x-dis.c: Likewise.
+
+2001-07-23  Kazu Hirata  <kazu@hxi.com>
+
+	* m68k-dis.c: Fix formatting.
+	* pj-dis.c: Likewise.
+	* s390-dis.c: Likewise.
+	* z8k-dis.c: Likewise.
+
+2001-07-21  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s
+	into the rest of the surrounding definitions.
+
+2001-07-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (grps): Print l or w suffix, and require mem modrm
+	for lgdt, lidt, sgdt, sidt.
+
+2001-07-13  Philip Blundell  <philb@gnu.org>
+
+	* arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR.
+
+2001-07-12  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cgen-asm.in: Include "xregex.h" always to enable the libiberty
+	regex support.
+	(@arch@_cgen_build_insn_regex): New routine from Graydon.
+	(@arch@_cgen_assemble_insn): Add Graydon's code to use regex
+	to verify if it is worth parsing the insn as insn "x".  Also update
+	error message when insn is not a recognized format of the insn vs
+	when the insn is completely unrecognized.
+
+2001-07-11  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
+	bfd_get_bits.
+	* cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
+	non-zero CGEN_CPU_DESC->insn_chunk_bitsize.
+
+2001-07-09  Andreas Jaeger  <aj@suse.de>, Karsten Keil <kkeil@suse.de>
+
+	* i386-dis.c (set_op): Handle 64 bit and 32 bit mode.
+	(OP_J): Use bfd_vma for mask to work properly with 64 bits.
+	(op_address,op_riprel): Use bfd_vma to handle 64 bits.
+
+2001-07-05  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.am (CPUDIR): Define.
+	(stamp-m32r): Update dependencies.
+	(stamp-fr30): Ditto.
+	(stamp-openrisc): Ditto.
+	* Makefile.in: Regenerate.
+
+2001-07-03  Zoltan Hidvegi <hzoli@hzoli.2y.net>
+
+	* ppc-opc.c: Fix encoding of 'clf' instruction.
+
+2001-06-30  Geoffrey Keating  <geoffk@redhat.com>
+
+	* cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT.
+
+2001-06-28  Geoffrey Keating  <geoffk@redhat.com>
+
+	* cgen-asm.c (cgen_parse_keyword): Allow any first character.
+	* cgen-opc.c (cgen_keyword_add): Ignore special first
+	character when building nonalpha_chars field.
+
+2001-06-24  Ben Elliston  <bje@redhat.com>
+
+	* m88k-dis.c: Format to conform to GNU coding standards.
+
+2001-06-23  Andreas Jaeger  <aj@suse.de>
+
+	* disassemble.c (disassembler_usage): Add unused attribute.
+
+2001-06-22  Eric Christopher  <echristo@redhat.com>
+
+	* mips-opc.c: Move prefx to start of the table.
+
+2001-06-22  Stacey Sheldon <ssheldon@Catena.com>
+
+	* arc-opc.c (insert_st_syntax): Fix over-optimisation of ST
+	instruction.
+
+2001-06-22  Pauli <pauli@moreton.com.au>
+
+	* m68k-opc.c: Add wdebug instruction.
+
+2001-06-15  Aldy Hernandez  <aldyh@redhat.com>
+
+	* m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc.
+
+2001-06-14  Geoffrey Keating  <geoffk@redhat.com>
+
+	* cgen-asm.c (cgen_parse_keyword): When looking for the
+	boundaries of a keyword, allow any special characters
+	that are actually in one of the allowed keyword.
+	* cgen-opc.c (cgen_keyword_add): Add any special characters
+	to the nonalpha_chars field.
+
+2001-06-12  Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+	* s390-opc.c: Add lgh instruction.
+	* s390-opc.txt: Likewise.
+
+2001-06-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c: Group function prototypes in one place.
+	(FLOATCODE): Redefine as 1.
+	(USE_GROUPS): Redefine as 2.
+	(USE_PREFIX_USER_TABLE): Redefine as 3.
+	(X86_64_SPECIAL): Define as 4.
+	(GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2.
+	(PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE.
+	(dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete.
+	(dis386): New table combining above four tables.
+	(dis386_twobyte_att, dis386_twobyte_intel): Delete.
+	(dis386_twobyte): New table combining above two tables.
+	(x86_64_table): New table to handle x86_64.
+	(X86_64_0): Define.
+	(float_mem_att, float_mem_intel): Delet.
+	(float_mem): New table combining above two tables.
+	(print_insn_i386): Modify for above.
+	(dofloat): Likewise.
+	(putop): Handle '{', '|' and '}' to select alternative mnemonics.
+	Return 0 on success, 1 if no valid alternative.
+	(putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax.
+	(putop <case 'T'>): Move to case 'U', and share case 'Q' code.
+	(putop <case 'I'>): Move to case 'T', and share case 'P' code.
+	(OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg
+	if not 64-bit mode.
+	(OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode.
+	(OP_I64): If not 64-bit mode, call OP_I.
+	OP_OFF64): If not 64-bit mode, call OP_OFF.
+	(OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename
+	'ignore'/'ignored' to 'bytemode'.
+
+2001-06-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in: Sort 'ta' case statement.
+	* configure: Regenerate.
+
+	* i386-dis.c (dis386_att): Add 'H' to conditional branch and
+	loop,jcxz insns.
+	(disx86_64_att): Likewise.
+	(dis386_twobyte_att): Likewise.
+	(print_insn_i386): Don't print branch hints as a prefix.
+	(putop): 'H' macro prints branch hints.
+	(get64): Kill compile warnings.
+
+2001-06-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh-opc.h (sh_table): Don't use empty initializers.
+
+2001-06-06  Christian Groessler <cpg@aladdin.de>
+
+	* z8k-dis.c: Fix formatting.
+	(unpack_instr): Remove unused cases in switch statement. Add
+	safety abort() in default case.
+	(unparse_instr): Add safety abort() in default case.
+
+2001-06-06  Peter Jakubek <pjak@snafu.de>
+
+	* m68k-dis.c (print_insn_m68k): Fix typo.
+	* m68k-opc.c (m68k_opcodes): Correct allowed operands for
+	mcf (ColdFire) div, rem and moveb instructions.
+
+2001-06-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define.
+	(cond_jump_mode, loop_jcxz_mode): Define.
+	(dis386_att): Add cond_jump_flag and loop_jcxz_flag as
+	appropriate, and 'F' suffix to loop insns.
+	(disx86_64_att): Likewise.
+	(dis386_twobyte_att): Likewise.
+	(print_insn_i386): Don't output addr prefix for loop, jcxz insns.
+	Output data size prefix for long conditional jumps.  Output cs and
+	ds branch hints.
+	(putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'.
+	(OP_J): Don't make PREFIX_DATA used.
+
+2001-06-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh-opc.h (sh_table): Complete last element entry to avoid
+	compiler warning.
+
+2001-05-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (mips_isa_type): Add MIPS r12k support.
+
+2001-05-23  Alan Modra  <amodra@one.net.au>
+
+	* arc-opc.c: Whitespace changes.
+
+2001-05-18  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris-opc.c (cris_spec_regs): Add missing initializer field for
+	last element.
+
+2001-05-15  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-dis.in (extract_normal): Complete support for min<base case.
+
+2001-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (INSNLEN): Rename MAXLEN.
+	(std_reg_names): Replace by mips32_reg_names and mips64_reg_names.
+	(print_insn_arg): Remove $ prefix of register names.
+	(set_mips_isa_type): Remove.
+	(mips_isa_type): New function.
+	(get_mips_isa): New Function.
+	(print_insn_mips): Rename _print_insn_mips.
+	(_print_insn_mips): New function, contains code which was
+	duplicated in print_insn_big_mips and print_insn_little_mips.
+	(print_insn_big_mips): Moved code to _print_insn_mips.
+	(print_insn_little_mips): Likewise.
+	(print_mips16_insn_arg): Remove $ prefix of register names.
+	Print error message before abort.
+
+2001-05-14  J.T. Conklin  <jtc@redback.com>
+
+	* ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of
+	simplified mnemonics used for setting PPC750-specific special
+	purpose	registers.
+
+2001-05-12  H.J. Lu  <hjl@gnu.org>
+
+	* i386-dis.c (print_insn_i386): Always set `mod', `reg' and
+	`rm'.
+
+2001-05-12  Peter Targett  <peter.targett@arccores.com>
+
+	* arc-opc.c (arc_reg_names): Correct attribute for lp_count
+	register to r/w.  Formatting fixes throughout file.
+
+2001-05-12  Alan Modra  <amodra@one.net.au>
+
+	* i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and
+	movq operands.
+	(twobyte_has_modrm): Update table.
+	(need_modrm): Give it file scope.
+	(MODRM_CHECK): Define.
+	(dofloat): Use MODRM_CHECK.
+	(OP_E): Likewise.
+	(OP_EM): Likewise.
+	(OP_EX): Likewise.
+
+2001-05-07  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-dis.in (default_print_insn): Tolerate min<base instructions
+	even at end of a section.
+	* cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions
+	by ignoring precariously-unpacked insn_value in favor of raw buffer.
+
+2001-05-03  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* disassemble.c (disassembler_usage): Remove unused attribute.
+
+2001-05-04  Frank Ch. Eigler  <fche@redhat.com>
+
+	* m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes.
+
+2001-05-04  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-dis.in (print_insn): Remove call to read_insn.  Instead,
+	assume incoming buffer already has the base insn loaded.  Handle
+	smaller-than-base instructions for variable-length case.
+
+2001-05-04  Alan Modra  <amodra@one.net.au>
+
+	* i386-dis.c (Ev, Ed): Remove duplicate define.
+	(Gd): Define.
+	(XS): Define.
+	(OP_XS): New function.
+	(dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and
+	movmskp operands.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Use MS for maskmovq operand.
+
+2001-04-27  Johan Rydberg  <jrydberg@opencores.org>
+
+	* Makefile.am: Add OpenRISC target.
+	* Makefile.in: Regenerated.
+
+	* disassemble.c (disassembler): Recognize the OpenRISC disassembly.
+
+	* configure.in (bfd_openrisc_arch): Add target.
+	* configure: Regenerated.
+
+	* openrisc-asm.c: New file.
+	* openrisc-desc.c: Likewise.
+	* openrisc-desc.h: Likewise.
+	* openrisc-dis.c: Likewise.
+	* openrisc-ibld.c: Likewise.
+	* openrisc-opc.c: Likewise.
+	* openrisc-opc.h: Likewise.
+
+2001-04-24  Christian Groessler  <cpg@aladdin.de>
+
+	* z8k-dis.c: add names of control registers (ctrl_names);
+	(seg_length): provides instruction length fixup for segmented
+	mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12,
+	CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases;
+	(unparse_intr): handle CLASS_PR, print addresses without '#'
+	* z8k-opc.h: re-created with new z8kgen
+	* z8kgen.c: merged in fixes which were in existing z8k-opc.h; new
+	entries for ldctl/ldctlb instruction
+
+2001-04-06  Andreas Jaeger  <aj@suse.de>
+
+	* i386-dis.c: Add ffreep instruction.
+
+2001-03-30  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ppc-opc.c (insert_mbe): Shift mask initializer as long.
+
+2001-03-24  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386-dis.c (PREGRP25): Define.
+	(dis386_twobyte_att): Use here in place of "movntq" entry.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq".
+	(PREGRP26): Define.
+	(dis386_twobyte_att): Use here.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Add PREGRP26 entry for "punpcklqdq".
+	(prefix_user_table <maskmovdqu>): XM operand, not MX.
+	(prefix_user_table): Cosmetic changes to "bad" entries.
+
+2001-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* mips-opc.c: Remove extraneous whitespace.
+	* mips-dis.c: Remove extraneous whitespace.
+
+2001-03-22  Ben Elliston  <bje@redhat.com>
+
+	* cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg
+	declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional.
+	* cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused
+	to allay a compiler warning.
+
+2001-03-22  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq.
+	(dis386_twobyte_intel): Likewise.
+	(twobyte_has_modrm): Set entry for paddq, psubq.
+
+2001-03-20  Patrick Macdonald  <patrickm@redhat.com>
+
+	* cgen-dis.in (print_insn_@arch@): Add support for target machine
+	determination via CGEN_COMPUTE_MACH.
+	* fr30-desc.c: Regenerate.
+	* fr30-dis.c: Regenerate.
+	* fr30-opc.h: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* m32r-opc.h: Regenerate.
+	* m32r-opinst.c: Regenerate.
+
+2001-03-20  H.J. Lu  <hjl@gnu.org>
+
+	* configure.in: Remove the redundent AC_ARG_PROGRAM.
+	* configure: Rebuild.
+
+2001-03-19  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and
+	notestr if larger than xsect.
+	(in_class): Handle format M5.
+	* ia64-asmtab.c: Regnerate.
+
+2001-03-19  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer
+	has more than one byte left to read.
+
+2001-03-16  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-opc.c: Add new opcodes.  Smooth out formatting.
+	* s390-opc.txt: Add new opcodes.
+
+2001-03-06  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c (print_insn_thumb): Compute destination address
+	of BLX(1) instruction by taking bit 1 from PC and not from bit
+	0 of the offset.
+
+2001-03-06  Igor Shevlyakov  <igor@windriver.com>
+
+	* m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs
+	so command line switches will work.
+
+2001-03-05  Dave Brolley  <brolley@redhat.com>
+
+	* fr30-asm.c: Regenerate.
+	* fr30-desc.c: Regenerate.
+	* fr30-desc.h: Regenerate.
+	* fr30-dis.c: Regenerate.
+	* fr30-ibld.c: Regenerate.
+	* fr30-opc.c: Regenerate.
+	* fr30-opc.h: Regenerate.
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-desc.h: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* m32r-opc.c: Regenerate.
+	* m32r-opc.h: Regenerate.
+	* m32r-opinst.c: Regenerate.
+
+2001-02-28  Igor Shevlyakov  <igor@windriver.com>
+
+	* m68k-opc.c: fix cpushl according to Motorola. Enable
+	bunch of instructions for Coldfire 5407 and add all new.
+
+2001-02-27  Alan Modra  <alan@linuxcare.com.au>
+
+	* configure.in (BFD_VERSION): Do without grep.
+	* configure: Regenerate.
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2001-02-23  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4".
+	* ia64-asmtab.c: Regenerate.
+
+2001-02-21  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
+	separate variants: one for IMM22 and the other for IMM14.
+	* ia64-asmtab.c: Regenerate.
+
+2001-02-21  Greg McGary  <greg@mcgary.org>
+
+	* cgen-opc.c (cgen_get_insn_value): Add missing `return'.
+
+2001-02-20  H.J. Lu  <hjl@gnu.org>
+
+	* Makefile.am (ia64-ic.tbl): Remove the target.
+	(ia64-raw.tbl): Likewise.
+	(ia64-waw.tbl): Likewise.
+	(ia64-war.tbl): Likewise.
+	(ia64-asmtab.c): Generate it in the source directory.
+	* Makefile.in: Regenerated.
+
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* Makefile.am: Add PDP-11 target.
+	* configure.in: Likewise.
+	* disassemble.c: Likewise.
+	* pdp11-dis.c: New file.
+	* pdp11-opc.c: New file.
+
+2001-02-14  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-ic.tbl: Update from Intel.  Add setf to fr-writers.
+	* ia64-asmtab.c: Regenerate.
+
+2001-02-12  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
+	instructions.
+	(putop): Handle 'Y'
+
+2001-02-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* mips-dis.c (print_insn_arg): Use top four bits of the address of
+	the following instruction not of the jump itself for the jump
+	target.
+	(print_mips16_insn_arg): Likewise.
+
+2001-02-11  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
+
+	* Makefile.am (stamp-lib): ranlib the libopcodes.a in the build
+	directory.
+	* Makefile.in: Regenerate.
+
+2001-02-09  Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* Makefile.am: Add linux target for S/390.
+	* Makefile.in: Likewise.
+	* configure.in: Likewise.
+	* disassemble.c: Likewise.
+	* s390-dis.c: New file.
+	* s390-mkopc.c: New file.
+	* s390-opc.c: New file.
+	* s390-opc.txt: New file.
+
+2001-02-05  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-asmtab.c: Revert 2000-12-16 change.
+
+2001-02-02  Patrick Macdonald  <patrickm@redhat.com>
+
+	* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
+	* m32r-desc.h: Regenerate.
+
+2001-02-01  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (dis386_att, grps): Use 'T' for push/pop
+	(putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax
+
+2001-01-14  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types.
+
+2001-01-13  Nick Clifton  <nickc@redhat.com>
+
+	* disassemble.c: Remove spurious white space.
+
+2001-01-13  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
+	templates.
+
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+	* Makefile.am (C_FILES): Add arc-ext.c.
+	(ALL_MACHINES) Add arc-ext.lo.
+	(INCLUDES) Add opcode directory to list.
+	New dependency entry for arc-ext.lo.
+	* disassemble.c (disassembler): Correct call to
+	arc_get_disassembler.
+	* arc-opc.c: New update for ARC, including full base
+	instructions for ARC variants.
+	* arc-dis.h, arc-dis.c: New update for ARC, including
+	extensibility functionality.
+	* arc-ext.h, arc-ext.c: New files for handling extensibility.
+
+2001-01-10  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (PREGRP15 - PREGRP24): New.
+	(dis386_twobyt): Add SSE2 instructions.
+	(twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions.
+	(twobyte_uses_f3_prefix): ... this one.
+	(grps): Add SSE instructions.
+	(prefix_user_table): Add two new slots; add SSE2 instructions.
+	(print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix;
+	Handle the REPNZ and Data16 prefixes as well; do proper lookup
+	to prefix_user_table.
+	(OP_E): Accept mfence and lfence as well.
+	(OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions.
+	(OP_XMM): Support REX extensions.
+	(OP_EM): Likewise.
+	(OP_EX): Likewise.
+
+2001-01-09  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c (print_insn): Set pc to zero for instructions with
+	a reloc associated with them.
+
+2001-01-09  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cgen-asm.in (parse_insn_normal): Changed syn to be
+	CGEN_SYNTAX_CHAR_TYPE.  Changed all references to *syn
+	as character to use CGEN_SYNTAX_CHAR macro and all comparisons
+	to '\0' to use 0 instead.
+	* cgen-dis.in (print_insn_normal): Ditto.
+	* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
+
+2001-01-05  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c: Add x86_64 support.
+	(rex): New static variable.
+	(REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants.
+	(USED_REX): New macro.
+	(Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros.
+	(OP_I64, OP_OFF64, OP_IMREG): New functions.
+	(OP_REG, OP_OFF): Declare.
+	(get64, get32, get32s): New functions.
+	(r??_reg): New constants.
+	(dis386_att): Change templates of instruction implicitly promoted
+	to 64bit; change e?? to RMe?? for unwind RM byte instructions.
+	(grps): Likewise.
+	(dis386_intel): Likewise.
+	(dixx86_64_att): New table based on dis386_att.
+	(dixx86_64_intel): New table based on dis386_intel.
+	(names64, names8rex): New global variable.
+	(names32, names16): Add extended registers.
+	(prefix_user_t): Recognize rex prefixes.
+	(prefix_name): Print REX prefixes nicely.
+	(op_riprel): New global variable.
+	(start_pc): Set type to bfd_vma.
+	(print_insn_i386): Detect the 64bit mode and use proper table;
+	move ckprefix after initializing the buffer; output unused rex prefixes;
+	output information about target of RIP relative addresses.
+	(putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S';
+	(print_operand_value): New function.
+	(OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for
+	REX prefix and new modes.
+	(get64, get32s): New.
+	(get32): Return bfd_signed_vma type.
+	(set_op): Initialize the op_riprel.
+	* disassemble.c (disassembler): Recognize the x86-64 disassembly.
+
+2001-01-03  Richard Sandiford  <r.sandiford@redhat.com>
+
+	 cgen-dis.in (read_insn): Use bfd_get_bits()
+
+2001-01-02  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen-dis.c (hash_insn_array): Use bfd_put_bits().
+	(hash_insn_list): Likewise
+	* cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits().
+	(extract_1): Use bfd_get_bits().
+	(extract_normal): Apply sign extension to both extraction
+	methods.
+	* cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits()
+	(cgen_put_insn_value): Use bfd_put_bits()
+
+2000-12-28  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-asm.in (parse_insn_normal): Print better error message for
+	instructions with missing operands.
+
+2000-12-21  Santeri Paavolainen <santtu@ssh.com>
+
+	* cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined.
+
+2000-12-16  Nick Clifton  <nickc@redhat.com>
+
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
+	* configure.in: Add spacing.
+	* configure: Regenerate.
+	* ia64-asmtab.c: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2000-12-12  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time
+	error messages over later parse-time ones.
+
+2000-12-12  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
+	argument.
+	* ia64-gen.c (insert_deplist): Cast sizeof result to int.
+	(print_dependency_table): Print NULL if semantics field not set.
+	(insert_opcode_dependencies): Mark cmp parameter as unused.
+	(print_main_table): Use fprintf_vma to print long long fields.
+	(main): Mark argv paramter as unused.  Convert to old style definition.
+	* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
+	* ia64-asmtab.c: Regnerate.
+
+2000-12-09  Nick Clifton  <nickc@redhat.com>
+
+	* m32r-dis.c (print_insn): Prevent re-read of instruction from
+	wrong address.
+
+	* fr30-dis.c: Regenerate.
+
+2000-12-08  Peter Targett  <peter.targett@arccores.com>
+
+	* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+	* Makefile.am (C_FILES): Add arc-ext.c.
+	(ALL_MACHINES) Add arc-ext.lo.
+	(INCLUDES) Add opcode directory to list.
+	New dependency entry for arc-ext.lo.
+	* disassemble.c (disassembler): Correct call to
+	arc_get_disassembler.
+	* arc-opc.c: New update for ARC, including full base
+	instructions for ARC variants.
+	* arc-dis.h, arc-dis.c: New update for ARC, including
+	extensibility functionality.
+	* arc-ext.h, arc-ext.c: New files for handling extensibility.
+
+2000-12-03  Chris Demetriou   cgd@sibyte.com
+
+	* mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
+	MOD_HILO, and MOD_LO macros.
+
+	* mips-opc.c (M1, M2): Delete.
+	(mips_builtin_opcodes): Remove all uses of M1.
+
+	* mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
+	instructions take "G" format second operands and use the
+	correct flags.
+	There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
+	match.
+	Delete "sel" code operands from mfc1 and mtc1.
+	Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
+	for dm[ft]c[023].
+
+2000-12-03  Ed Satterthwaite  ehs@sibyte.com  and
+	    Chris Demetriou   cgd@sibyte.com
+
+	* mips-opc.c (mips_builtin_opcodes): Finish additions
+	for MIPS32 support, and clean up existing entries for
+	aesthetics, consistency with the MIPS32 ISA, and
+	with consistency the rest of the table.
+
+2000-12-01  Nick Clifton  <nickc@redhat.com>
+
+	* mips16-opc.c (mips16_opcodes): Add initialiser for membership
+	field.
+
+2000-12-01  Chris Demetriou <cgd@sibyte.com>
+
+	mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
+	specifiers.  Update 'B' for new constant names, and remove
+	'm'.
+	mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
+	near the top of the array, so they are disassembled properly.
+	Enable "ssnop" for MIPS32.  Add "break" variant with 20 bit
+	code for MIPS32.  Update "clo" and "clz" to use 'U' operand
+	specifier.  Add 'H' format specifier variants for "mfc1,"
+	"mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32.  Update
+	MIPS32 "sdbbp" to use 'B' operand specifier.  Add MIPS32
+	"wait" variant which uses 'J' operand specifier.
+
+	* mips-dis.c (set_mips_isa_type): Update to use
+	CPU_UNKNOWN and ISA_* constants.  Add bfd_mach_mips32 case.
+	Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
+	* mips-opc.c (I32): New constant for instructions added in
+	MIPS32.
+	(P4): Delete.
+	(mips_builtin_opcodes) Replace all uses of P4 with I32.
+
+	* mips-dis.c (set_mips_isa_type): Add cases for
+	bfd_mach_mips5 and bfd_mach_mips64.
+	* mips-opc.c (I64): New definitions.
+
+	* mips-dis.c (set_mips_isa_type): Add case for
+	bfd_mach_mips_sb1.
+
+2000-11-28  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
+	(print_insn_ppi): Make nib1, nib2, nib3 unsigned.
+	Initialize variable dc to NULL.
+	(print_insn_shx): Remove unused label d_reg_n.
+
+2000-11-24  Nick Clifton  <nickc@redhat.com>
+
+	* arm-opc.h: Add new opcode formatting parameter 'B'.
+	(arm_opcodes): Add XScale, v5, and v5te	instructions.
+	(thumb_opcodes): Add v5t instructions.
+
+	* arm-dis.c (print_insn_arm): Handle new 'B' format
+	parameter.
+	(print_insn_thumb): Decode BLX(1) instruction.
+
+2000-11-21  Chris Demetriou  <cgd@sibyte.com>
+
+	* mips-opc.c: Fix file header comment.
+
+2000-11-14  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris-dis.c (cris_get_disassembler): If abfd is NULL, return
+	print_insn_cris_with_register_prefix.
+
+2000-11-11  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.
+
+2000-11-07  Matthew Green  <mrg@redhat.com>
+
+	* cgen-dis.in (print_insn): All insns which can fit into insn_value
+	must be loaded there in their entirety.
+
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
+	(compute_arch_mask): Add v8plusb and v9b machines.
+	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
+	* sparc-opc.c: Support for Cheetah instruction set.
+	(prefetch_table): Add #invalidate.
+
+2000-10-16  Nick Clifton  <nickc@redhat.com>
+
+	* mcore-dis.c (imsk): Change mask for OC to 0xFE00.
+
+2000-10-06  Dave Brolley  <brolley@redhat.com>
+
+	* fr30-desc.h: Regenerate.
+	* m32r-desc.h: Regenerate.
+	* m32r-ibld.c: Regenerate.
+
+2000-10-05  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-ic.tbl: Update from Intel.
+	* ia64-asmtab.c: Regenerate.
+
+2000-10-04  Kazu Hirata  <kazu@hxi.com>
+
+	* ia64-gen.c: Convert C++-style comments to C-style comments.
+	* tic54x-dis.c: Likewise.
+
+2000-09-29  Hans-Peter Nilsson  <hp@axis.com>
+
+	Changes to add dollar prefix to registers for files where user symbols
+	don't have a leading underscore.  Fix formatting.
+	* cris-dis.c (REGISTER_PREFIX_CHAR): New.
+	(format_reg): Add parameter with_reg_prefix.  All callers changed.
+	(print_with_operands): Ditto.
+	(print_insn_cris_generic): Renamed from print_insn_cris, add
+	parameter with_reg_prefix.
+	(print_insn_cris_with_register_prefix,
+	print_insn_cris_without_register_prefix, cris_get_disassembler):
+	New.
+	* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
+
+2000-09-22  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
+	gt, ge, ngt, and nge.
+	* ia64-asmtab.c: Regenerate.
+
+	* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
+	* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
+	(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
+	* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
+	* ia64-asmtab.c: Regnerate.
+
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+
+	* mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
+	Add mfc0 and mtc0 with sub-selection values.
+	Add clo and clz opcodes.
+	Add msub and msubu instructions for MIPS32.
+	Add madd/maddu aliases for mad/madu for MIPS32.
+	Support wait, deret, eret, movn, pref for MIPS32.
+	Support tlbp, tlbr, tlbwi, tlbwr.
+	(P4): New define.
+
+	* mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
+	(print_insn_arg): Handle 'H' args.
+	(set_mips_isa_type): Recognize 4K.
+	Use CPU_* defines instead of hardcoded numbers.
+
+2000-09-11  Catherine Moore <clm@redhat.com>
+
+	* d30v-opc.c (d30v_operand_t): New operand type Rb2.
+	(d30v_format_tab): Use Rb2 for modinc and moddec.
+
+2000-09-07  Catherine Moore  <clm@redhat.com>
+
+	* d30v-opc.c (d30v_format_tab): Use format Ra for
+	modinc and moddec.
+
+2000-09-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	* configure: Rebuilt with new libtool.m4.
+
+2000-09-05  Nick Clifton  <nickc@redhat.com>
+
+	* configure: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2000-08-31  Alexandre Oliva  <aoliva@redhat.com>
+
+	* acinclude.m4: Include libtool and gettext macros from the
+	top level.
+	* aclocal.m4, configure: Rebuilt.
+
+2000-08-30  Kazu Hirata  <kazu@hxi.com>
+
+	* tic80-dis.c: Fix formatting.
+
+2000-08-29  Kazu Hirata  <kazu@hxi.com>
+
+	* w65-dis.c: Fix formatting.
+
+2000-08-28  Mark Hatle  <mhatle@mvista.com>
+
+	* ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
+	(powerpc_opcodes): Add table entries for PPC 405 instructions.
+	Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
+	instructions.  Added extended mnemonic mftbl as defined in the
+	405GP manual for all PPCs.
+
+2000-08-28  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
+	call.  Change last goto to use failed instead of done.
+
+2000-08-28  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-ibld.in (cgen_put_insn_int_value): New function.
+	(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+	(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
+	(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+	* cgen-dis.in (read_insn): New static function.
+	(print_insn): Use read_insn to read the insn into the buffer and set
+	up for disassembly.
+	(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
+	in the buffer.
+	* fr30-asm.c: Regenerated.
+	* fr30-desc.c: Regenerated.
+	* fr30-desc.h: Regenerated.
+	* fr30-dis.c: Regenerated.
+	* fr30-ibld.c: Regenerated.
+	* fr30-opc.c: Regenerated.
+	* fr30-opc.h: Regenerated.
+	* m32r-asm.c: Regenerated.
+	* m32r-desc.c: Regenerated.
+	* m32r-desc.h: Regenerated.
+	* m32r-dis.c: Regenerated.
+	* m32r-ibld.c: Regenerated.
+	* m32r-opc.c: Regenerated.
+
+2000-08-28  Kazu Hirata  <kazu@hxi.com>
+
+	* tic30-dis.c: Fix formatting.
+
+2000-08-27  Kazu Hirata  <kazu@hxi.com>
+
+	* sh-dis.c: Fix formatting.
+
+2000-08-24  David Edelsohn  <dje@watson.ibm.com>
+
+	* ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
+
+2000-08-24  Kazu Hirata  <kazu@hxi.com>
+
+	* z8k-dis.c: Fix formatting.
+
+2000-08-16  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
+	break, mov-immediate, nop.
+	* ia64-opc-f.c: Delete fpsub instructions.
+	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
+	address operand.  Rewrite using macros to avoid long lines.
+	* ia64-opc.h (POSTINC): Define.
+	* ia64-asmtab.c: Regenerate.
+
+2000-08-15  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-ic.tbl: Add missing entries.
+
+2000-08-08  Jason Eckhardt  <jle@redhat.com>
+
+	* i860-dis.c (print_br_address): Change third argument from int
+	to long.
+
+2000-08-07  Richard Henderson  <rth@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Get byte skip count correct
+	for MLI templates.  Handle IA64_OPND_TGT64.
+
+2000-08-04  Ben Elliston  <bje@redhat.com>
+
+	* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
+	* cgen.sh: Likewise.
+
+2000-08-02  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
+
+2000-07-29  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+	* avr-dis.c (avr_operand): Use PARAMS macro in declaration.
+	Change return type from void to int.  Check the combination
+	of operands, return 1 if valid.  Fix to avoid BUF overflow.
+	Report undefined combinations of operands in COMMENT.
+	Report internal errors to stderr.  Output the adiw/sbiw
+	constant operand in both decimal and hex.
+	(print_insn_avr): Disassemble ldd/std with displacement of 0
+	as ld/st.  Check avr_operand () return value, handle invalid
+	combinations of operands like unknown opcodes.
+
+2000-07-28  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
+	(run-cgen, stamp-m32r, stamp-fr30): New targets.
+	* Makefile.in: Regenerate.
+	* configure.in: Add --enable-cgen-maint option.
+	* configure: Regenerate.
+
+2000-07-26  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned.
+	(cgen_hw_lookup_by_num): Ditto.
+	(cgen_operand_lookup_by_name): Ditto.
+	(print_address): Ditto.
+	(print_keyword): Ditto.
+	* cgen-dis.c (hash_insn_array): Mark unused parameters with
+	ATTRIBUTE_UNUSED.
+	* cgen-asm.c (hash_insn_array): Mark unused parameters with
+	ATTRIBUTE_UNUSED.
+	(cgen_parse_keyword): Ditto.
+
+2000-07-22  Jason Eckhardt  <jle@redhat.com>
+
+	* i860-dis.c: New file.
+	(print_insn_i860): New function.
+	(print_br_address): New function.
+	(sign_extend): New function.
+	(BITWISE_OP): New macro.
+	(I860_REG_PREFIX): New macro.
+	(grnames, frnames, crnames): New structures.
+
+	* disassemble.c (ARCH_i860): Define.
+	(disassembler): Add check for bfd_arch_i860 to set disassemble
+	function to print_insn_i860.
+
+	* Makefile.in (CFILES): Added i860-dis.c.
+	(ALL_MACHINES): Added i860-dis.lo.
+	(i860-dis.lo): New dependences.
+
+	* configure.in: New bits for bfd_i860_arch.
+
+	* configure: Regenerated.
+
+2000-07-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	* Makefile.am (CFILES): Add cris-dis.c and cris-opc.c.
+	(ALL_MACHINES): Add cris-dis.lo and cris-opc.lo.
+	(cris-dis.lo, cris-opc.lo): New rules.
+	* Makefile.in: Rebuild.
+	* configure.in (bfd_cris_arch): New target.
+	* configure: Rebuild.
+	* disassemble.c (ARCH_cris): Define.
+	(disassembler): Support ARCH_cris.
+	* cris-dis.c, cris-opc.c: New files.
+	* po/POTFILES.in, po/opcodes.pot: Regenerate.
+
+2000-07-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
+	Reported by Bill Clarke <llib@computer.org>.
+
+2000-07-09  Geoffrey Keating  <geoffk@redhat.com>
+
+	* ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
+	Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
+
+2000-07-09  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg,
+	fput_const, extract_3, extract_5_load, extract_5_store,
+	extract_5r_store, extract_5R_store, extract_10U_store,
+	extract_5Q_store, extract_11, extract_14, extract_16, extract_21,
+	extract_12, extract_17, extract_22): Prototype.
+	(print_insn_hppa): Rename inner block opcode -> opc to avoid
+	shadowing outer block.
+	(GET_BIT): Define.
+
+2000-07-05  DJ Delorie  <dj@redhat.com>
+
+	* MAINTAINERS: new
+
+2000-07-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* arm-dis.c (print_insn_arm): Output combinations of PSR flags.
+
+2000-07-03  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+	* avr-dis.c (avr_operand): Change _ () to _() around all strings
+	marked for translation (exception from the usual coding style).
+	(print_insn_avr): Initialize insn2 to avoid warnings.
+
+2000-07-03  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300-dis.c (bfd_h8_disassemble): Improve readability.
+	* h8500-dis.c: Fix formatting.
+
+2000-07-01  Alan Modra  <alan@linuxcare.com.au>
+
+	* Makefile.am (DEP): Fix 2000-06-22.  grep after running dep.sed
+	(CLEANFILES): Add DEPA.
+	* Makefile.in: Regenerate.
+
+2000-06-26  Scott Bambrough  <scottb@netwinder.org>
+
+	* arm-dis.c (regnames): Add an additional register set to match
+	the set used by GCC.  Make it the default.
+
+2000-06-22  Alan Modra  <alan@linuxcare.com.au>
+
+	* Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we
+	find one.
+	* Makefile.in: Regenerate.
+
+2000-06-20  H.J. Lu  <hjl@gnu.org>
+
+	* Makefile.am: Rebuild dependency.
+	* Makefile.in: Rebuild.
+
+2000-06-18  Stephane Carrez  <stcarrez@worldnet.fr>
+
+	* Makefile.in, configure: regenerate
+	* disassemble.c (disassembler): Recognize ARCH_m68hc12,
+	ARCH_m68hc11.
+	* m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12):
+	New functions.
+	* configure.in: Recognize m68hc12 and m68hc11.
+	* m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x
+	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
+	and opcode generation for m68hc11 and m68hc12.
+
+2000-06-16  Nick Duffek  <nsd@redhat.com>
+
+	* disassemble.c (disassembler): Refer to the PowerPC 620 using
+	bfd_mach_ppc_620 instead of 620.
+
+2000-06-12  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300-dis.c: Fix formatting.
+	(bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
+	correctly.
+
+2000-06-09  Denis Chertykov  <denisc@overta.ru>
+
+	* avr-dis.c (avr_operand): Bugfix for jmp/call address.
+
+2000-06-07  Denis Chertykov  <denisc@overta.ru>
+
+	* avr-dis.c: completely rewritten.
+
+2000-06-02  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300-dis.c: Follow the GNU coding style.
+	(bfd_h8_disassemble) Fix a typo.
+
+2000-06-01  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300-dis.c (bfd_h8_disassemble_init): Fix a typo.
+	(bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
+	correctly.  Fix a typo.
+
+2000-05-31  Nick Clifton  <nickc@redhat.com>
+
+	* opintl.h (_(String)): Explain why dgettext is used instead of
+	gettext.
+
+2000-05-30  Nick Clifton  <nickc@redhat.com>
+
+	* opintl.h (gettext, dgettext, dcgettext, textdomain,
+	bindtextdomain): Replace defines with those from intl/libgettext.h
+	to quieten gcc warnings.
+
+2000-05-26  Alan Modra  <alan@linuxcare.com.au>
+
+	* Makefile.am: Update dependencies with "make dep-am"
+	* Makefile.in: Regenerate.
+
+2000-05-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	* m10300-dis.c (disassemble): Don't assume 32-bit longs when
+	sign-extending operands.
+
+2000-05-15  Donald Lindsay  <dlindsay@redhat.com>
+
+	* d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
+	except brf's.
+
+2000-05-21  Nick Clifton  <nickc@redhat.com>
+
+	* Makefile.am (LIBIBERTY): Define.
+
+2000-05-19 Diego Novillo <dnovillo@redhat.com>
+
+	* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
+	(STD_REGISTER_NAMES): New name for REGISTER_NAMES.
+	(reg_names): Rename to std_reg_names. Change it to a char **
+	static variable.
+	(std_reg_names): New name for reg_names.
+	(set_mips_isa_type): Set reg_names to point to std_reg_names by
+	default.
+
+2000-05-16  Frank Ch. Eigler  <fche@redhat.com>
+
+	* fr30-desc.h: Partially regenerated to account for changed
+	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
+	* m32r-desc.h: Ditto.
+
+2000-05-15  Nick Clifton  <nickc@redhat.com>
+
+	* arm-opc.h: Use upper case for flasg in MSR and MRS
+	instructions.  Allow any bit to be set in the field_mask of
+	the MSR instruction.
+
+	* arm-dis.c (print_insn_arm): Decode _x and _s bits of the
+	field_mask of an MSR instruction.
+
+2000-05-11  Thomas de Lellis  <tdel@windriver.com>
+
+	* arm-opc.h: Disassembly of thumb ldsb/ldsh
+	instructions changed to ldrsb/ldrsh.
+
+2000-05-11  Ulf Carlsson  <ulfc@engr.sgi.com>
+
+	* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
+	target addresses for 'jal' and 'j'.
+
+2000-05-10  Geoff Keating  <geoffk@redhat.com>
+
+	* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
+	also available in common mode when powerpc syntax is being used.
+
+2000-05-08  Alan Modra  <alan@linuxcare.com.au>
+
+	* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
+	(dummy_print_address): Ditto.
+
+2000-05-04  Timothy Wall  <twall@redhat.com>
+
+	* tic54x-opc.c: New.
+	* tic54x-dis.c: New.
+	* disassemble.c (disassembler): Add ARCH_tic54x.
+	* configure.in: Added tic54x target.
+	* configure: Ditto.
+	* Makefile.am: Add tic54x dependencies.
+	* Makefile.in: Ditto.
+
+2000-05-03  J.T. Conklin  <jtc@redback.com>
+
+	* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
+	vector unit operands.
+	(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
+	unit instruction formats.
+	(PPCVEC): New macro, mask for vector instructions.
+	(powerpc_operands): Add table entries for above operand types.
+	(powerpc_opcodes): Add table entries for vector instructions.
+
+	* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
+	(print_insn_little_powerpc): Likewise.
+	(print_insn_powerpc): Prepend 'v' when printing vector registers.
+
+2000-04-24  Clinton Popetz  <cpopetz@redhat.com>
+
+	* configure.in: Add bfd_powerpc_64_arch.
+	* disassemble.c (disassembler): Use print_insn_big_powerpc for
+	64 bit code.
+
+2000-04-24  Nick Clifton  <nickc@redhat.com>
+
+	* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
+	field.
+
+2000-04-23  Denis Chertykov  <denisc@overta.ru>
+
+	* avr-dis.c (reg_fmul_d): New. Extract destination register from
+	FMUL instruction.
+	(reg_fmul_r): New. Extract source register from FMUL instruction.
+	(reg_muls_d): New. Extract destination register from MULS instruction.
+	(reg_muls_r): New. Extract source register from MULS instruction.
+	(reg_movw_d): New. Extract destination register from MOVW instruction.
+	(reg_movw_r): New. Extract source register from MOVW instruction.
+	(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
+	EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
+
+2000-04-22  Timothy Wall  <twall@redhat.com>
+
+	* ia64-gen.c (general): Add an ordered table of primary
+	opcode names, as well as priority fields to disassembly data
+	structures to enforce a preferred disassembly format based on the
+	ordering of the opcode tables.
+	(load_insn_classes): Show a useful message if IC tables are missing.
+	(load_depfile): Ditto.
+	* ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
+	distinguish preferred disassembly.
+	* ia64-opc-f.c: Reorder some insn for preferred disassembly
+	format.  Fix incorrect flag on fma.s/fma.s.s0.
+	* ia64-opc.c: Scan *all* disassembly matches and use the one with
+	the highest priority.
+	* ia64-opc-b.c: Use more abbreviations.
+	* ia64-asmtab.c: Regenerate.
+
+2000-04-21  Jason Eckhardt  <jle@redhat.com>
+
+	* hppa-dis.c (extract_16): New function.
+	(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
+	new operand types l,y,&,fe,fE,fx.
+
+2000-04-21  Richard Henderson  <rth@redhat.com>
+	    David Mosberger  <davidm@hpl.hp.com>
+	    Timothy Wall <twall@redhat.com>
+	    Bob Manson  <manson@charmed.cygnus.com>
+	    Jim Wilson  <wilson@redhat.com>
+
+	* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
+	(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
+	ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
+	ia64-asmtab.c.
+	(ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
+	(ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
+	ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
+	* Makefile.in: Rebuild.
+	* configure Rebuild.
+	* configure.in (bfd_ia64_arch): New target.
+	* disassemble.c (ARCH_ia64): Define.
+	(disassembler): Support ARCH_ia64.
+	* ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
+	ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
+	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
+	ia64-war.tbl, ia64-waw.tbl: New files.
+
+2000-04-20  Alexandre Oliva  <aoliva@redhat.com>
+
+	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
+	(disassemble): Use them.
+
+2000-04-14  Alan Modra  <alan@linuxcare.com.au>
+
+	* sysdep.h: Include "ansidecl.h" not <ansidecl.h>
+	* Makefile.am: Update dependencies.
+	* Makefile.in: Regenerate.
+
+2000-04-14  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
+
+	* a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
+	avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
+	disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
+	i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
+	m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
+	mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
+	ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
+	tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
+	w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h.  Remove
+	ansidecl.h as sysdep.h includes it.
+
+2000-04-7  Andrew Cagney  <cagney@b1.redhat.com>
+
+	* configure.in (WARN_CFLAGS): Set to -W -Wall by default.  Add
+	--enable-build-warnings option.
+	* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
+	* Makefile.in, configure: Re-generate.
+
+2000-04-05  J"orn Rennecke <amylaar@redhat.com>
+
+	* sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
+	stc GBR,@-<REG_N> is available for arch_sh1_up.
+	Group parallel processing insn with identical mnemonics together.
+	Make three-operand psha / pshl come first.
+
+2000-04-05  J"orn Rennecke <amylaar@redhat.co.uk>
+
+	* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
+	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
+	(sh_arg_type): Add A_PC.
+	(sh_table): Update entries using immediates.  Add repeat.
+	* sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
+	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
+
+2000-04-04  Alan Modra  <alan@linuxcare.com.au>
+
+	* po/opcodes.pot: Regenerate.
+
+	* Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
+	(DEP): Quote when passing vars to sub-make.  Add warning message
+	to end.
+	(DEP1): Rewrite for "gcc -MM".
+	(CLEANFILES): Add DEP2.
+	Update dependencies.
+	* Makefile.in: Regenerate.
+
+2000-04-03  Denis Chertykov  <denisc@overta.ru>
+
+	* avr-dis.c: Syntax cleanup.
+	(add0fff): Print the pc relative address as a signed number.
+	(add03f8): Likewise.
+
+2000-04-01  Ian Lance Taylor  <ian@zembu.com>
+
+	* disassemble.c (disassembler_usage): Don't use a prototype.  Mark
+	the parameter ATTRIBUTE_UNUSED.
+	* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
+
+2000-04-01  Alexandre Oliva  <aoliva@redhat.com>
+
+	* m10300-opc.c: SP-based offsets are always unsigned.
+
+2000-03-29  Thomas de Lellis  <tdel@windriver.com>
+
+	* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
+	[branch always] instead of "undefined".
+
+2000-03-27  Nick Clifton  <nickc@redhat.com>
+
+	* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
+	short instructions, from end of list of long instructions.
+
+2000-03-27  Ian Lance Taylor  <ian@zembu.com>
+
+	* Makefile.am (CFILES): Add avr-dis.c.
+	(ALL_MACHINES): Add avr-dis.lo.
+
+2000-03-27  Alan Modra  <alan@linuxcare.com>
+
+	* avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
+	truncate integers.
+	(print_insn_avr): Call function via pointer in K&R compatible way.
+	(dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
+	add0fff, add03f8): Convert to old style function declaration and
+	add prototype.
+	(avrdis_opcode): Add prototype.
+
+2000-03-27  Denis Chertykov  <denisc@overta.ru>
+
+	* avr-dis.c: New file.  AVR disassembler.
+	* configure.in (bfd_avr_arch): New architecture support.
+	* disassemble.c: Likewise.
+	* configure: Regenerate.
+
+2000-03-06  J"oern Rennecke <amylaar@redhat.com>
+
+	* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
+
+2000-03-02  J"orn Rennecke <amylaar@redhat.co.uk>
+
+	* d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
+	flag to determine if operand is pc-relative.
+	* d30v-opc.c:
+	(d30v_format_table):
+	(REL6S3): Renamed from IMM6S3.
+	Added flag OPERAND_PCREL.
+	(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
+	added flag OPERAND_PCREL.
+	(IMM12S3U): Replaced with REL12S3.
+	(SHORT_D2, LONG_D): Delay target is pc-relative.
+	(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
+	Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
+	using the REL* operands.
+	(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
+	(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
+	LONG_Db, using REL* operands.
+	(SHORT_U, SHORT_A5S): Removed stray alternatives.
+	(d30v_opcode_table): Use new *r formats.
+
+2000-02-28  Nick Clifton  <nickc@redhat.com>
+
+	* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
+	'signed_overflow_ok_p'.
+
+2000-02-27  Eli Zaretskii  <eliz@is.elta.co.il>
+
+	* Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
+	name of the libtool directory.
+	* Makefile.in: Rebuild.
+
+2000-02-24  Nick Clifton  <nickc@redhat.com>
+
+	* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
+	(cgen_clear_signed_overflow_ok): New function.
+	(cgen_signed_overflow_ok_p): New function.
+
+2000-02-23  Andrew Haley  <aph@redhat.com>
+
+	* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+	m32r-ibld.c, m32r-opc.h: Rebuild.
+
+2000-02-23  Linas Vepstas <linas@linas.org>
+
+	* i370-dis.c, i370-opc.c: New.
+
+	* disassemble.c (ARCH_i370): Define.
+	(disassembler): Handle it.
+
+	* Makefile.am: Add support for Linux/IBM 370.
+	* configure.in: Likewise.
+
+	* Makefile.in: Regenerate.
+	* configure: Likewise.
+
+2000-02-22  Chandra Chavva   <cchavva@redhat.com>
+
+	* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
+	ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
+	procedure.
+
+2000-02-22  Andrew Haley  <aph@redhat.com>
+
+	* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
+	force gp32 to zero.
+	* mips-opc.c (G6): New define.
+	(mips_builtin_op): Add "move" definition for -gp32.
+
+2000-02-22  Ian Lance Taylor  <ian@zembu.com>
+
+	From Grant Erickson <gerickso@Brocade.COM>:
+	* ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
+
+2000-02-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* dis-buf.c (buffer_read_memory): Change `length' param and all int
+	vars to unsigned.
+
+2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk>
+
+	* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
+	(print_insn_ppi): Likewise.
+	(print_insn_shx): Use info->mach to select appropriate insn set.
+	Add support for sh-dsp.  Remove FD_REG_N support.
+	* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
+	(sh_arg_type): Likewise.  Remove FD_REG_N.
+	(sh_dsp_reg_nums): New enum.
+	(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
+	(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
+	(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
+	(arch_sh3_dsp_up): Likewise.
+	(sh_opcode_info): New field: arch.
+	(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
+	D_REG_N.  Fill in arch field.  Add sh-dsp insns.
+
+2000-02-14  Fernando Nasser  <fnasser@totem.to.redhat.com>
+
+	* arm-dis.c: Change flavor name from atpcs-special to
+	special-atpcs to prevent name conflict in gdb.
+	(get_arm_regname_num_options, set_arm_regname_option,
+	get_arm_regnames): New functions.  API to access the several
+	flavor of register names.  Note: Used by gdb.
+	(print_insn_thumb): Use the register name entry from the currently
+	selected flavor for LR and PC.
+
+2000-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
+	classes.
+	(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
+	"mulsh.h" instructions.
+	* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
+	classes.
+	(print_insn_mcore): Add support for little endian targets.
+	Add support for MULSH and OPSR classes.
+
+2000-02-07  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c (parse_arm_diassembler_option): Rename again.
+	Previous delat did not take.
+
+2000-02-03  Timothy Wall  <twall@redhat.com>
+
+	* dis-buf.c (buffer_read_memory):  Use octets_per_byte field
+	to adjust target address bounds checking and calculate the
+	appropriate octet offset into data.
+
+2000-01-27  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c: (parse_disassembler_option): Rename to
+	parse_arm_disassembler_option and allow to be exported.
+
+	* disassemble.c (disassembler_usage): New function: Print out any
+	target specific disassembler options.
+	Call arm_disassembler_options() if the ARM architecture is being
+	supported.
+
+	* arm-dis.c (NUM_ELEM): Define this macro if not already
+	defined.
+	(arm_regname): New struct type for ARM register names.
+	(arm_toggle_regnames): Delete.
+	(parse_disassembler_option): Use register name structure.
+	(print_insn): New function: Combines duplicate code found in
+	print_insn_big_arm and print_insn_little_arm.
+	(print_insn_big_arm): Call print_insn.
+	(print_insn_little_arm): Call print_insn.
+	(print_arm_disassembler_options): Display list of supported,
+	ARM specific disassembler options.
+
+2000-01-27  Thomas de Lellis  <tdel@windriver.com>
+
+	* arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
+	ARM_STT_16BIT flag as Thumb code symbols.
+
+	* arm-dis.c (printf_insn_little_arm): Ditto.
+
+2000-01-25  Thomas de Lellis  <tdel@windriver.com>
+
+	* arm-dis.c (printf_insn_thumb): Prevent double dumping
+	of raw thumb instructions.
+
+2000-01-20  Nick Clifton  <nickc@redhat.com>
+
+	* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
+
+2000-01-03  Nick Clifton  <nickc@cygnus.com>
+
+	* arm-dis.c (streq): New macro.
+	(strneq): New macro.
+	(force_thumb): ew local variable.
+	(parse_disassembler_option): New function: Parse a single, ARM
+	specific disassembler command line switch.
+	(parse_disassembler_option): Call parse_disassembler_option to
+	parse individual command line switches.
+	(print_insn_big_arm): Check force_thumb.
+	(print_insn_little_arm): Check force_thumb.
+
+For older changes see ChangeLog-9899
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog-0203 b/gnu/usr.bin/binutils/opcodes/ChangeLog-0203
new file mode 100644
index 00000000000..25ed8b55868
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/ChangeLog-0203
@@ -0,0 +1,2110 @@
+2003-12-15  Christian Groessler  <chris@groessler.org>
+
+	* z8k-dis.c (intr_names): Removed.
+	(print_intr, print_flags): New functions.
+	(unparse_instr): Use new functions.
+
+2003-12-15  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r-opc.c: Regenerate.
+
+2003-12-14  Mark Mitchell  <mark@codesourcery.com>
+
+	* arm-opc.h (arm_opcodes): Put V6 instructions before XScale
+	instructions.
+
+2003-12-13  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE,
+	SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE
+	and SWYM_INSN_BYTE instead of raw numbers.
+
+2003-12-10  Zack Weinberg  <zack@codesourcery.com>
+
+	* ppc-opc.c (MO): Make optional.
+	(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
+	(tlbwe): Accept for both PPC403 and BOOKE.  Make all operands optional.
+
+2003-12-05  Ricardo Anguiano <anguiano@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+	    Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-dis.c (print_arm_insn): Add 'W' macro.
+	* arm-opc.h (arm_opcodes): Add V6 instructions.
+	(thumb_opcodes): Likewise.
+
+2003-12-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* openrisc-asm.c: Regenerate.
+	* pj-opc.c: Update copyright date.
+
+2003-12-03  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-desc.h: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* m32r-opc.c: Regenerate.
+	* m32r-opc.h: Regenerate.
+	* m32r-opinst.c: Regenerate.
+
+2003-12-02  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh-opc.h: Add support for sh4a and no-fpu variants.
+	* sh-dis.c: Ditto.
+
+2003-12-02  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* alpha-opc.c: Remove ARGSUSED.
+	* i370-opc.c: Likewise.
+	* ppc-opc.c: Likewise.
+
+2003-12-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2003-11-28  Christian Groessler  <chris@groessler.org>
+
+	* z8k-dis.c: Convert to ISO C90.
+	* z8kgen.c: Convert to ISO C90.
+	(opt): Move long opcode for "ldb rdb,imm8" after short one, now
+	the short one is created when assembling.
+	* z8k-opc.h: Regenerate with new z8kgen.c.
+
+2003-11-19  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* h8300-dis.c (print_colon_thingie): Remove.
+
+2003-11-18  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and
+	"dlca".
+
+2003-11-14  Nick Clifton  <nickc@redhat.com>
+
+	* dis-init.c (init_disassemble_info): Initialise
+	symbol_is_valid field.
+	* dis-buf.c (generic_symbol_is_valid): New function.  Always
+	returns TRUE.
+	* arm-dis.c (arm_symbol_is_valid): New function.  Return FALSE
+	for ARM ELF mapping symbols.
+	* disassemble.c (disassemble_init_for_target): Set
+	symbol_is_valid field to arm_symbol_is_valid of the target is
+	an ARM.
+
+2003-11-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* m68k-opc.c (m68k_opcodes): Reorder "fmovel".
+
+2003-11-03  Daniel Jacobowitz  <drow@mvista.com>
+
+	* arm-dis.c (print_arm_insn): Print "-" after "#".
+
+2003-10-30  Falk Hueffner  <falk.hueffner@student.uni-tuebingen.de>
+
+	* alpha-opc.c: Add support for a second argument to RPCC.
+
+2003-10-27  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-dis.c: Convert to ISO C90 prototypes.
+
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+	    Bernardo Innocenti  <bernie@develer.com>
+
+	* m68k-dis.c: Add MCFv4/MCF5528x support.
+	* m68k-opc.c: Likewise.
+
+2003-10-10  Dave Brolley  <brolley@redhat.com>
+
+	* frv-asm.c,frv-desc.c,frv-opc.c: Regenerated.
+
+2003-10-08  Dave Brolley  <brolley@redhat.com>
+
+	* frv-desc.[ch], frv-opc.[ch]: Regenerated.
+
+2003-09-30  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-dis.c (fetch_data): Remove numBytes parameter.
+	(print_insn_xtensa): Fix call to fetch_data.
+
+2003-09-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
+	(print_insn_args): Add handing for +E, +F, +G, and +H.
+	* mips-opc.c (I65): New define for MIPS64r2.
+	(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
+	"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
+	and "dshd" for MIPS64r2.  Adjust "dror", "dror32", and "drorv" to
+	be supported on MIPS64r2.
+
+2003-09-24  Dave Brolley  <brolley@redhat.com>
+
+	* frv-desc.c, frv-opc.c, frv-opc.h: Regenerated.
+
+2003-09-14  Andreas Jaeger  <aj@suse.de>
+
+	* i386-dis.c: Convert to ISO C90 prototypes.
+	* i370-dis.c: Likewise.
+	* i370-opc.c: Likewiwse.
+	* i960-dis.c: Likewise.
+	* ia64-opc.c: Likewise.
+
+2003-09-09  Dave Brolley  <brolley@redhat.com>
+
+	* frv-desc.c: Regenerated.
+
+2003-09-08  Dave Brolley  <brolley@redhat.com>
+
+	On behalf of Doug Evans <dje@sebabeach.org>
+	* Makefile.am (run-cgen): Pass new args archfile and opcfile
+	to cgen.sh.
+	(stamp-ip2k,stamp-m32r,stamp-fr30,stamp-frv,stamp-openrisc,
+	stamp-iq2000,stamp-xstormy16): Pass paths of .cpu and .opc files
+	to cgen.sh.
+	(stamp-frv): Delete hardcoded path spec workaround.
+	* Makefile.in: Regenerate.
+	* cgen.sh: New args archfile and opcfile.  Pass on to cgen.
+
+2003-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* v850-dis.c (disassemble): Accept bfd_mach_v850e1.
+	* v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions.
+
+2003-09-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-dis.c (struct dis_private): New.
+	(powerpc_dialect): Make static.  Accept -Many in addition to existing
+	options.  Save dialect in dis_private.
+	(print_insn_big_powerpc): Retrieve dialect from dis_private.
+	(print_insn_little_powerpc): Likewise.
+	(print_insn_powerpc): Call powpc_dialect here.  Remove unnecessary
+	efs/altivec check.  Try harder to disassemble if given -Many.
+	* ppc-opc.c (insert_fxm): Expand comment.
+	(PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY.
+	(POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise.
+	(POWER4): Remove PPCCOM.
+	(PPCONLY): Don't define.  Update all occurrences to PPC.
+
+2003-09-03  Andrew Cagney  <cagney@redhat.com>
+
+	* dis-init.c (init_disassemble_info): New file and function.
+	* Makefile.am (CFILES): Add "dis-init.c".
+	(libopcodes_la_SOURCES): Add "dis-init.c".
+	(dis-init.lo): Specify dependencies.
+	* Makefile.in: Regenerate.
+
+2003-09-03  Dave Brolley  <brolley@redhat.com>
+
+	* frv-*: Regenerated.
+
+2003-09-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries.
+	Move duplicate mnemonic entries together.  Use RS instead of RT on
+	all mt*.
+	* ppc-dis.c: Convert to ISO C.
+
+2003-08-29  Dave Brolley  <brolley@redhat.com>
+
+	* Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from
+	$(srcdir)/../cpu temporarily when regenerating source files.
+	* Makefile.in: Regenerated.
+
+2003-08-19  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c (print_insn_arm: case 'A'): Add code to
+	disassemble unindexed form of Addressing Mode 5.
+
+2003-08-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c (PPC440): Define.
+	(powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
+	icread instructions when PPC440.  Add dlmzb instruction.
+
+2003-08-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* dep-in.sed: Remove libintl.h.
+	* Makefile.am (POTFILES.in): Unset LC_COLLATE.
+	Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2003-08-07  Michael Meissner  <gnu@the-meissners.org>
+
+	* cgen-asm.c (hash_insn_array): Remove PARAMS macro.
+	(hash_insn_list): Ditto.
+	(build_asm_hash_table): Ditto.
+	(cgen_set_parse_operand_fn): Prototype definition.
+	(cgen_init_parse_operand): Ditto.
+	(hash_insn_array): Ditto.
+	(hash_insn_list): Ditto.
+	(build_asm_hash_table): Ditto.
+	(cgen_asm_lookup_insn): Ditto.
+	(cgen_parse_keyword): Ditto.
+	(cgen_parse_signed_integer): Ditto.
+	(cgen_parse_unsigned_integer): Ditto.
+	(cgen_parse_address): Ditto.
+	(cgen_validate_signed_integer): Ditto.
+	(cgen_validate_unsigned_integer): Ditto.
+
+	* cgen-opc.c (hash_keyword_name): Remove PARAMS macro.
+	(hash_keyword_value): Ditto.
+	(build_keyword_hash_tables): Ditto.
+	(cgen_keyword_lookup_name): Prototype definition.
+	(cgen_keyword_lookup_value): Ditto.
+	(cgen_keyword_add): Ditto.
+	(cgen_keyword_search_init): Ditto.
+	(cgen_keyword_search_next): Ditto.
+	(hash_keyword_name): Ditto.
+	(hash_keyword_value): Ditto.
+	(build_keyword_hash_tables): Ditto.
+	(cgen_hw_lookup_by_name): Ditto.
+	(cgen_hw_lookup_by_num): Ditto.
+	(cgen_operand_lookup_by_name): Ditto.
+	(cgen_operand_lookup_by_num): Ditto.
+	(cgen_insn_count): Ditto.
+	(cgen_macro_insn_count): Ditto.
+	(cgen_get_insn_value): Ditto.
+	(cgen_put_insn_value): Ditto.
+	(cgen_lookup_insn): Ditto.
+	(cgen_get_insn_operands): Ditto.
+	(cgen_lookup_get_insn_operands): Ditto.
+	(cgen_set_signed_overflow_ok): Ditto.
+	(cgen_clear_signed_overflow_ok): Ditto.
+	(cgen_signed_overflow_ok_p): Ditto.
+
+	* cgen-dis.c (hash_insn_array): Remove PARAMS macro.
+	(hash_insn_list): Ditto.
+	(build_dis_hash_table): Ditto.
+	(count_decodable_bits): Ditto.
+	(add_insn_to_hash_chain): Ditto.
+	(count_decodable_bits): Prototype definition.
+	(add_insn_to_hash_chain): Ditto.
+	(hash_insn_array): Ditto.
+	(hash_insn_list): Ditto.
+	(build_dis_hash_table): Ditto.
+	(cgen_dis_lookup_insn): Ditto.
+
+	* cgen-asm.in (parse_insn_normal): Remove PARAMS macro.
+	(@arch@_cgen_build_insn_regex): Prototype definition.
+	(parse_insn_normal): Ditto.
+	(@arch@_cgen_assemble_insn): Ditto.
+	(@arch@_cgen_asm_hash_keywords): Ditto.
+
+	* cgen-dis.in (print_normal): Remove PARAMS macro.  Use void *
+	instead of PTR.
+	(print_address): Ditto.
+	(print_keyword): Ditto.
+	(print_insn_normal): Ditto.
+	(print_insn): Ditto.
+	(default_print_insn): Ditto.
+	(read_insn): Ditto.
+	(print_normal): Prototype definition.  Use void * instead of PTR.
+	(print_address): Ditto.
+	(print_keyword): Ditto.
+	(print_insn_normal): Ditto.
+	(read_insn): Ditto.
+	(print_insn): Ditto.
+	(default_print_insn): Ditto.
+	(print_insn_@arch@): Ditto.
+
+	* cgen-ibld.in (insert_normal): Remove PARAMS macro.
+	(insn_insn_normal): Ditto.
+	(extract_normal): Ditto.
+	(extract_insn_normal): Ditto.
+	(put_insn_int_value): Ditto.
+	(insert_1): Ditto.
+	(fill_cache): Ditto.
+	(extract_1): Ditto.
+	(insert_1): Prototype definition.
+	(insert_normal): Ditto.
+	(insert_insn_normal): Ditto.
+	(put_insn_int_value): Ditto.
+	(fill_cache): Ditto.
+	(extract_1): Ditto.
+	(extract_normal): Ditto.
+	(extract_insn_normal): Ditto.
+
+	* fr30-asm.c: Regenerate.
+	* fr30-dis.c: Ditto.
+	* fr30-ibld.c: Ditto.
+	* frv-asm.c: Ditto.
+	* frv-dis.c: Ditto.
+	* frv-ibld.c: Ditto.
+	* ip2k-asm.c: Ditto.
+	* ip2k-dis.c: Ditto.
+	* ip2k-ibld.c: Ditto.
+	* iq2000-asm.c: Ditto.
+	* iq2000-dis.c: Ditto.
+	* iq2000-ibld.c: Ditto.
+	* m32r-asm.c: Ditto.
+	* m32r-dis.c: Ditto.
+	* m32r-ibld.c: Ditto.
+	* openrisc-asm.c: Ditto.
+	* openrisc-dis.c: Ditto.
+	* openrisc-ibld.c: Ditto.
+	* xstormy16-asm.c: Ditto.
+	* xstormy16-dis.c: Ditto.
+	* xstormy16-ibld.c: Ditto.
+
+2003-08-06  Nick Clifton  <nickc@redhat.com>
+
+	* po/fr.po: Updated French translation.
+
+2003-08-05  Nick Clifton  <nickc@redhat.com>
+
+	* configure.in (ALL_LINGUAS): Add nl.
+	* configure: Regenerate.
+	* po/nl.po: New Dutch translation.
+
+2003-07-30  Jason Eckhardt  <jle@rice.edu>
+
+	* i860-dis.c: Convert to ISO C90.  Remove superflous prototypes.
+
+2003-07-30  Nick Clifton  <nickc@redhat.com>
+
+	* po/ro.po: Updated Romanian translation.
+
+2003-07-29  Jakub Jelinek  <jakub@redhat.com>
+
+	* ppc-opc.c (insert_mbe, extract_mbe): Shift 1L instead of 1 up.
+
+2003-07-24  Nick Clifton  <nickc@redhat.com>
+
+	* po/fr.po: Updated French translation.
+
+2003-07-18  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c (parse_arm_disassembler_option): Do not expect
+	option string to be NUL terminated.
+	(parse_disassembler_options): Allow options to be space or
+	comma separated.
+
+2003-07-17  Nick Clifton  <nickc@redhat.com>
+
+	* po/es.po: New Spanish translation.
+	* po/sv.po: New Swedish translation.
+	* po/opcodes.pot: Regenerate.
+
+2003-07-15  Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries.
+
+2003-07-14  Nick Clifton  <nickc@redhat.com>
+
+	* po/tr.po: Update with latest version.
+	* po/POTFILES.in: Regenerate.
+	* Makefile.in: Regenerate.
+
+2003-07-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/opcodes.pot: Regenerate.
+
+2003-07-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	2000-05-25  Alexandre Oliva  <aoliva@cygnus.com>
+	* m10300-dis.c (disassemble): Negate negative accumulator's shift.
+	2000-05-24  Alexandre Oliva  <aoliva@cygnus.com>
+	* m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume
+	32-bit longs when sign-extending operands.
+	2000-04-20  Alexandre Oliva  <aoliva@cygnus.com>
+	* m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs.
+	* m10300-dis.c (HAVE_AM33_2): Define.
+	(disassemble): Use it.
+	(HAVE_AM33): Redefine.
+	(print_insn_mn10300): Fix mask for 5-byte extended insns.
+	2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
+	* m10300-opc.c: Renamed AM332 to AM33_2.
+	2000-03-31  Alexandre Oliva  <aoliva@cygnus.com>
+	* m10300-opc.c: Defined AM33 2.0 register operands.  Added support
+	for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and
+	bclr.  Implemented `fbCC', `flCC', `dcpf' and all FP insns.
+	* m10300-dis.c (print_insn_mn10300): Recognize 5byte extended
+	insn code of AM33 2.0.
+	(disassemble): Recognize FMT_D3.  Print out FP register names.
+
+2003-07-09  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (set_default_mips_dis_options): Get BFD from
+	the disassembler_info's section, rather than from the
+	disassembler_info's symbols pointer.
+
+2003-07-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Remove NULL pointer checks.  Formatting.  Remove
+	extraneous ATTRIBUTE_UNUSED.
+	* ppc-dis.c (print_insn_powerpc): Always pass a valid address to
+	operand->extract.
+
+2003-07-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Convert to C90, removing unnecessary prototypes and
+	casts.  Formatting.
+
+	* ppc-opc.c: Remove PARAMS from prototypes.
+	(FXM4): Define.
+	(insert_fxm): New function, used by both FXM and FXM4.
+	(extract_fxm): Likewise.
+	(XFXFXM_MASK): Remove 1 << 20 term.
+	(powerpc_opcodes): Add Power4 version of "mfcr".  Simplify "mtcr" mask.
+
+2003-07-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-dis.c (s390_extract_operand): Add support for long displacements.
+	* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z990.
+	* s390-opc.c (D20_20): Add define for 20 bit displacements.
+	(INSTR_RRF_R0RR, INSTR_RSL_R0RD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
+	INSTR_RSY_AARD, INSTR_RXY_RRRD, INSTR_RXY_FRRD, INSTR_SIY_URD): Add
+	new instruction formats.
+	(MASK_RRF_R0RR, MASK_RSL_R0RD, MASK_RSY_RRRD, MASK_RSY_RURD,
+	MASK_RSY_AARD, MASK_RXY_RRRD, MASK_RXY_FRRD, MASK_SIY_URD): Likewise.
+	(s390_opformats): Likewise.
+	* s390-opc.txt: Add new instructions for cpu type z990. Add missing
+	hfp instructions. Add missing instructions pgin, pgout and xsch.
+
+2003-06-23  H.J. Lu <hongjiu.lu@intel.com>
+
+	* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
+	Intel Precott New Instructions.
+	(PREGRP27): New. Added for "addsubpd" and "addsubps".
+	(PREGRP28): New. Added for "haddpd" and "haddps".
+	(PREGRP29): New. Added for "hsubpd" and "hsubps".
+	(PREGRP30): New. Added for "movsldup" and "movddup".
+	(PREGRP31): New. Added for "movshdup" and "movhpd".
+	(PREGRP32): New. Added for "lddqu".
+	(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
+	Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
+	entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
+	entry 0xd0. Use PREGRP32 for entry 0xf0.
+	(twobyte_has_modrm): Updated.
+	(twobyte_uses_SSE_prefix): Likewise.
+	(grps): Use PNI_Fixup in the "sidtQ" entry.
+	(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
+	PREGRP31 and PREGRP32.
+	(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
+	Use "fisttpll" in entry 1 in opcode 0xdd.
+	Use "fisttp" in entry 1 in opcode 0xdf.
+
+2003-06-19  Christian Groessler  <chris@groessler.org>
+
+	* z8k-dis.c (instr_data_s): Change tabl_index from long to int.
+	(print_insn_z8k): Correctly check return value from
+	z8k_lookup_instr call.
+	(unparse_instr): Handle CLASS_IRO case.
+	* z8kgen.c: Fix function definitions.  Fix formatting.
+	(opt): Add brk opcode alias for non-simulator breakpoint.  Add
+	missing and fix existing in/out and sin/sout opcode definitions.
+	(args): "@ri", "@ro" - add CLASS_IRO register usage for in/out
+	opcodes.
+	(internal): Check p->flags for non-zero before dereferencing it.
+	(gas): Add CLASS_IRO line.  Insert new OPC_xxx lines for the added
+	opcodes and renumber the remaining lines repectively.
+	(main): Remove "-d" command line switch.
+	* z8k-opc.h: Regenerate with new z8kgen.c.
+
+2003-06-11  H.J. Lu <hongjiu.lu@intel.com>
+
+	* po/Make-in (DESTDIR): New.
+	(install-data-yes): Support $(DESTDIR).
+	(uninstall): Likewise.
+
+2003-06-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2003-06-10  Doug Evans  <dje@sebabeach.org>
+
+	* cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to
+	CGEN_INSN_RELAXED.
+	* fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate.
+	* frv-asm.c,frv-desc.c,frv-desc.h: Regenerate.
+	* ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate.
+	* iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate.
+	* m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate.
+	* openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate.
+	* xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate.
+
+2003-06-10  Gary Hade <garyhade@us.ibm.com>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define.
+	(insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New.
+	(powerpc_opcodes): Add "attn", "lq" and "stq".
+
+2003-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300-dis.c (bfd_h8_disassemble): Don't print brackets round
+	rts/l and rte/l register lists.
+
+2003-06-03  Nick Clifton  <nickc@redhat.com>
+
+	* frv-desc.c: Regenerate.
+	* frv-opc.c: Regenerate.
+	* frv-asm.c: Regenerate.
+	* frv-desc.h: Regenerate.
+	* frv-dis.c: Regenerate.
+	* frv-ibld.c: Regenerate.
+	* frv-opc.h: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2003-06-03  Michael Snyder  <msnyder@redhat.com>
+	and Bernd Schmidt   <bernds@redhat.com>
+	and Alexandre Oliva <aoliva@redhat.com>
+
+	* disassemble.c (disassembler): Add support for h8300sx.
+	* h8300-dis.c: Ditto.
+
+2003-06-03  Nick Clifton  <nickc@redhat.com>
+
+	* frv-desc.c: Regenerate.
+	* frv-opc.c: Regenerate.
+
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* iq2000-asm.c: Regenerate.
+	* iq2000-desc.c: Regenerate.
+	* iq2000-desc.h: Regenerate.
+	* iq2000-dis.c: Regenerate.
+	* iq2000-ibld.c: Regenerate.
+	* iq2000-opc.c: Regenerate.
+	* iq2000-opc.h: Regenerate.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
+	(print_insn_i860): Grab 4 bits of the control register field
+	instead of 3.
+
+2003-05-18  Jason Eckhardt  <jle@rice.edu>
+
+	* i860-dis.c (print_insn_i860): Instruction shrd has a dual bit,
+	print it.
+
+2003-05-17  Andreas Jaeger  <aj@suse.de>
+
+	* Makefile.am (libopcodes_la_LIBADD): Add libbfd.la.
+	(libopcodes_la_DEPENDENCIES): Add libbfd.la.
+	* Makefile.in: Regenerated.
+
+2003-05-16  Nick Clifton  <nickc@redhat.com>
+
+	* configure.in (ALL_LINGUAS): Add Romanian translation.
+	* configure: Regenerate.
+	* po/ro.po: New file: Romanian translation.
+
+2003-05-12  Dhananjay Deshpande  <dhananjayd@kpitcummins.com>
+
+	* disassemble.c (disassembler): Add support for h8300hn and h8300sn.
+
+2003-05-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386-dis.c (print_insn): Test intel_syntax against (char) -1 in
+	case char is unsigned.
+
+2003-05-01  Christian Groessler <chris@groessler.org>
+
+	* z8k-dis.c (z8k_lookup_instr): Optimize FETCH_DATA calls.
+	(unpack_instr): Fix representation of segmented addresses.
+	(intr_name): Added, contains names of the parameters to the EI/DI
+	instructions.
+	(unparse_instr): Fix display of EI/DI parameters.
+
+2003-04-22  Doug Evans  <dje@sebabeach.org>
+
+	* fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate.
+	* frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate.
+	* ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate.
+	* m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate.
+	* m32r-opinst.c: Regenerate.
+	* openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate.
+	* xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate.
+
+2003-04-15  Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+	* h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'.
+
+2003-04-07  James E Wilson  <wilson@tuliptree.org>
+
+	* ia64-ic.tbl (fr-readers): Add mem-writers-fp.
+	* ia64-asmtab.c: Regenerate.
+
+2003-04-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	* mips-dis.c (mips_gpr_names_newabi): Reverted previous patch.
+
+2003-04-07  Alexandre Oliva  <aoliva@redhat.com>
+
+	* mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7.
+
+2003-04-04  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
+	s/c3x/tic3x/
+
+2003-04-01  Nick Clifton  <nickc@redhat.com>
+
+	* arm-dis.c: Remove presence of (r) and (tm) symbols.
+	* arm-opc.h: Remove presence of (r) and (tm) symbols.
+
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm-dis.c (regnames): Add iWMMXt register names.
+	(set_iwmmxt_regnames): New function.
+	(print_insn_arm): Handle iWMMXt formatters.
+	* arm-opc.h: Document iWMMXt formatters.
+	(arm_opcod): Add iWMMXt instructions.
+
+2003-03-22  Doug Evans  <dje@sebabeach.org>
+
+	* i386-dis.c (dis386): Recognize icebp (0xf1).
+
+2003-03-21  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to
+	S390_OPCODE_ZARCH.
+	(print_insn_s390): Use new modes field of s390_opcodes.
+	* s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove.
+	(s390_opcode_mode_val, s390_opcode_cpu_val): New enums.
+	(struct op_struct): Remove archbits. Add mode_bits and min_cpu.
+	(insertOpcode): Replace archbits by min_cpu and mode_bits.
+	(dumpTable): Write mode_bits and min_cpu instead of archbits.
+	(main): Adapt to new format in s390-opcode.txt.
+	* s390-opc.c (s390_opformats): Replace archbits by min_cpu and
+	mode_bits.
+	* s390-opc.txt: Replace archbits by min_cpu and mode_bits.
+
+2003-03-17  Nick Clifton  <nickc@redhat.com>
+
+	* ppc-opc.c: Fix formatting.  Update copyright date.
+
+2003-03-14  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403.
+
+2003-02-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* hppa-dis.c: Formatting.
+
+2003-02-25  Matthew Wilcox  <willy@debian.org>
+
+	* hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers.
+
+	* hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print
+	the space register when the value is zero.
+
+2003-02-23  Elias Athanasopoulos  <elathan@phys.uoa.gr>
+
+	* mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned,
+	use ARRAY_SIZE in loops.
+
+2003-02-12  Dave Brolley  <brolley@redhat.com>
+
+	* fr30-desc.c: Regenerate.
+
+2003-02-06  Gwenole Beauchesne  <gbeauchesne@mandrakesoft.com>
+
+	* i386-dis.c (dq_mode, Edq): Define.
+	(dis386_twobyte): Correct movd operands.
+	(OP_E): Handle dq_mode case.
+
+2003-01-29  Henric Jungheim <henric@attbi.com>
+
+	* sparc-dis.c (print_insn_sparc): When examining values added in
+	to rs1, make sure that there are previous instructions.
+
+2003-01-23  Nick Clifton  <nickc@redhat.com>
+
+	* Add sh2e support:
+
+	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>
+
+		* sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e.
+		* sh-opc.h (arch_sh2e, arch_sh2e_up): New.
+		(arch_sh2_up): Added sh2e.
+		(sh_table): Replaced all occurrences of arch_sh3e_up with
+		arch_sh2e_up, except in fsqrt.
+
+2003-01-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* sh64-dis.c: Include elf32-sh64.h.
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2003-01-17  Richard Henderson  <rth@redhat.com>
+
+	* alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap
+	PAL entry points.
+
+2003-01-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2003-01-08  Klee Dienes  <kdienes@apple.com>
+
+	* Makefile.am (ALL_MACHINES): Add msp430-dis.lo.
+	* Makefile.in: Regenerate.
+
+2003-01-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c (powerpc_macros <extrwi>): Accept a shift of 32.
+
+2002-01-02  Ben Elliston  <bje@redhat.com>
+	    Jeff Johnston  <jjohnstn@redhat.com>
+
+	* iq2000-asm.c: New file.
+	* iq2000-desc.c: Likewise.
+	* iq2000-desc.h: Likewise.
+	* iq2000-dis.c: Likewise.
+	* iq2000-ibld.c: Likewise.
+	* iq2000-opc.c: Likewise.
+	* iq2000-opc.h: Likewise.
+	* Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
+	(CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
+	iq2000-ibld.c, iq2000-opc.c.
+	(ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
+	iq2000-ibld.lo, iq2000-opc.lo.
+	(CLEANFILES): Add stamp-iq2000.
+	(IQ2000_DEPS): New macro.
+	(stamp-iq2000): New target.
+	* Makefile.in: Regenerate.
+	* configure.in: Handle bfd_iq2000_arch.
+	* configure: Regenerate.
+
+2003-01-02  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (print_insn_args): Use position extracted by "+A"
+	to calculate size for "+B".  Redo code for "+C" so it shares
+	the same style as "+A" and "+B" now do.
+
+2003-01-02  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c: Update copyright years.
+	(print_insn_arg): Rename to...
+	(print_insn_args): This, returning void.  Process the whole
+	string of args rather than a single one.  Reindent.
+	(print_insn_mips): Update to match the above.
+
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Move "di" into the
+	right order alphabetically, and make all hex constants use
+	lower-case letters.
+
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_cp0sel_name): New structure.
+	(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
+	(mips_cp0sel_names_sb1): New arrays.
+	(mips_arch_choice): New structure members "cp0sel_names" and
+	"cp0sel_names_len".
+	(mips_arch_choices): Add references to new cp0sel_names arrays
+	as appropriate, and make all existing entries reference
+	appropriate mips_XXX_names_numeric arrays rather than simply
+	using NULL.
+	(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
+	(lookup_mips_cp0sel_name): New function.
+	(set_default_mips_dis_options): Set mips_cp0sel_names and
+	mips_cp0sel_names_len as appropriate.  Remove now-unnecessary
+	checks for NULL register name arrays.
+	(parse_mips_dis_option): Likewise.
+	(print_insn_arg): Handle "+D" operand type.
+	* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
+	of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
+	names symbolically.
+
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
+	(mips_hwr_names_mips3264r2): New arrays.
+	(mips_arch_choice): New "hwr_names" member.
+	(mips_arch_choices): Adjust for structure change, and add a new
+	entry for "mips32r2" ISA.
+	(mips_hwr_names): New variable.
+	(set_default_mips_dis_options): Set mips_hwr_names.
+	(parse_mips_dis_option): New "hwr-names" option which sets
+	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
+	(print_insn_arg): Change return type to "int"
+	and use that to indicate number of characters consumed.
+	Add support for "+" operand extension character, "+A", "+B",
+	"+C", and "K" operands.
+	(print_insn_mips): Adjust for changes to print_insn_arg.
+	(print_mips_disassembler_options): Adjust for "hwr-names"
+	addition and "reg-names" change.
+	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
+	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
+	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
+	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
+	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
+	Note that hardware rotate instructions (ror, rorv) can be
+	used on MIPS32 Release 2, and add the official mnemonics
+	for them (rotr, rotrv) and the similar "rotl" mnemonic for
+	left-rotate.
+
+2002-12-30    Dmitry Diky <diwil@mail.ru>
+
+	* configure.in: Add msp430 target.
+	* configure: Regenerate.
+	* disassemble.c: Add entry for msp430 disassembly.
+	* msp430-dis.c: New file: msp430 disassembler.
+
+2002-12-27  Chris Demetriou  <cgd@broadcom.com>
+
+	* disassemble.c (disassembler_usage): Add invocation of
+	print_mips_disassembler_options.
+	* mips-dis.c: Include libiberty.h.
+	(print_mips_disassembler_options, set_default_mips_dis_options)
+	(parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name)
+	(choose_arch_by_name, choose_arch_by_number): New functions.
+	(mips_abi_choice, mips_arch_choice): New structures.
+	(mips32_reg_names, mips64_reg_names, reg_names): Remove.
+	(mips_gpr_names_numeric, mips_gpr_names_oldabi)
+	(mips_gpr_names_newabi, mips_fpr_names_numeric)
+	(mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
+	(mips_cp0_names_numeric, mips_cp0_names_mips3264)
+	(mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
+	(mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
+	(mips_cp0_names): New variables.
+	(print_insn_args): Use new variables to print GPR, FPR, and CP0
+	register names.
+	(mips_isa_type): Remove.
+	(print_insn_mips): Remove ISA and CPU setup since it is now done...
+	(_print_insn_mips): Here.  Remove register setup code, and
+	call set_default_mips_dis_options and parse_mips_dis_options
+	instead.
+	(print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
+
+2002-12-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.in: Regenerate.
+
+2002-12-19  Nick Kelsey  <nickk@ubicom.com>
+
+	* cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character
+	check to fix false keyword trigger with names such as <keyword>_foo.
+
+2002-12-19  Doug Evans  <dje@sebabeach.org>
+
+	* Makefile.am (CGEN_CPUS): New variable.
+	(run-cgen-all): New rule.
+	* Makefile.in: Regenerate.
+
+2002-12-18  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
+	"dror" entries, and reorder the remaining "dror" and "ror" entries.
+
+2002-12-16  DJ Delorie  <dj@delorie.com>
+
+	* xstormy16-asm.c (parse_immediate16): Add prototype.
+
+2002-12-16  Andrew MacLeod  <amacleod@redhat.com>
+
+	* xstormy16-asm.c: Regenerate.
+
+2002-12-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ns32k-dis.c (print_insn_ns32k): Constify "d", remove register
+	keyword.
+
+2002-12-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* h8500-opc.h (h8500_table): Add missing initializers to quiet
+	warnings.
+	* pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.
+	* pj-opc.c (pj_opc_info): Add braces around union initializer.
+	* z8kgen.c: Include "libiberty.h".
+	(opt, args, toks): Fix initializer warnings.
+	(chewname): Make "name" a char **.  Return mnemonic trimmed of
+	operands.
+	(gas): Improve emitted "DO NOT EDIT" warning.  Format emitted
+	opcode_entry_type, and make "nicename" and "name" const.  Make
+	z8k_table const too.  Formatting.  Generate idx as gas needs it.
+	* z8k-opc.h: Regenerate.
+
+2002-12-08  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-dis.c (print_indexed_operand): Fix PC-relative address
+	for 9 and 16-bit PC-relative addressing mode.
+
+2002-12-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
+	evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
+	evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
+	evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
+	evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
+	evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
+	evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
+	evmwhgsmian, evmwhgumian.
+	(mftb): Add to opcode table.
+	(mtspefscr): Change RT to RS in opcode table.
+
+2002-12-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c: Move mbar and msync up.  Change mask for mbar and
+	msync.
+
+2002-12-04  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
+	* ia64-opc-b.c: Add "hint.b" instruction.
+	* ia64-opc-f.c: Add "hint.f" instruction.
+	* ia64-opc-i.c: Add "hint.i" instruction.
+	* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
+	"cmp8xchg16" instructions.
+	* ia64-opc-x.c: Add "hint.x" instruction.
+
+	* ia64-opc.h (AR_CSD): New macro.
+
+	* ia64-ic.tbl: Update according to SDM2.1.
+	* ia64-raw.tbl: Ditto.
+	* ia64-waw.tbl: Ditto.
+
+	* ia64-gen.c (in_iclass): Handle "hint" like "nop".
+	(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
+	AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
+	* ia64-asmtab.c: Regenerate.
+
+2002-11-25  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,
+	evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw.
+
+2002-12-04  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c (PMRN): Remove.
+	(RA): Set to NB + 1.
+	(powerpc_opcodes): Change PMRN to SPR.
+	Change all RD to RS.
+	Change mftb to look like mftbl.
+	Move mftb before mftbl.
+	Add mfbbtar.
+	Add mtbbtar.
+	Change mfpmr to use PMR.
+	Change mtpmr to use PMR.
+	(RD): Remove.
+	(insert_ev2): Fix mask and shift.
+	(extract_ev2): Same.
+	(insert_ev4): Same.
+	(extract_ev4): Same.
+	(PMR): Define.
+	(extract_pmrn): Remove.
+	(insert_pmrn): Remove.
+
+2002-12-03  Richard Henderson  <rth@redhat.com>
+
+	* ia64-opc-m.c: Add ld8.mov.
+	* ia64-asmtab.c: Regenerate.
+
+2002-12-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* arm-dis.c (print_insn_arm): Constify "insn".  Formatting.
+	(print_insn_thumb): Likewise.
+	* h8500-dis.c (print_insn_h8500): Constify "opcode".
+	* mcore-dis.c (print_insn_mcore): Constify "op".  Formatting.
+	* ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid
+	type-punned pointer warnings.
+	<case 'L'>: Likewise.  Fix error message too.
+	* pdp11-dis.c (print_reg): Warning fix.
+	* sh-dis.c (print_movxy): Constify "op" param.
+	(print_insn_ddt): Constify sh_opcode_info vars.
+	(print_insn_ppi): Likewise.
+	(print_insn_sh): Likewise.
+	* tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid
+	type-punned pointer warnings.
+	* w65-dis.c (print_insn_w65): Constify "op".
+
+2002-12-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-dis.c (PC_REGNUM): Define.
+	(print_indexed_operand): Need an adjustment for some PC-relative
+	operand modes; print the final address of PC-relative modes.
+	(print_insn): Take into account movw/movb to adjust the PC-relative
+	operand addresses.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	*arm-dis.c, cris-dis.c, h8300-dis.c, mips-dis.c, mmix-dis.c, sh-dis.c,
+	sh64-dis.c, v850-dis.c: Replace boolean with bfd_boolean, true with
+	TRUE, false with FALSE.  Simplify comparisons of bfd_boolean vars
+	with TRUE/FALSE.  Formatting.
+
+2002-11-25  DJ Delorie  <dj@redhat.com>
+
+	* xstormy16-opc.c: Regenerate.
+
+2002-11-25  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64.
+
+2002-11-15  DJ Delorie  <dj@redhat.com>
+
+	* xstormy16-desc.c: Regenerate.
+	* xstormy16-opc.c: Regenerate.
+	* xstormy16-opc.h: Regenerate.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* avr-dis.c: Include libiberty.h (for xmalloc).
+	(struct avr_opcodes_s): Remove 'bin_mask' field (it's
+	automatically computed in the init routine).
+	(AVR_INSN): No longer provide bin_mask field in initializer.
+	(avr_opcodes_s): Declare as const.
+	(print_insn_avr): Store the bin_mask field in a separate table
+	(allocated with xmalloc); iterate through it at the same time as
+	we iterate through the opcodes.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* h8300-dis.c: Include libiberty.h (for xmalloc).
+	(struct h8_instruction): New type, used to wrap h8_opcodes with a
+	length field (computed at run-time).
+	(h8_instructions): New variable.
+	(bfd_h8_disassemble_init): Allocate the storage for
+	h8_instructions.  Fill h8_instructions with pointers to the
+	appropriate opcode and the correct value for the length field.
+	(bfd_h8_disassemble): Iterate through h8_instructions instead of
+	h8_opcodes.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* arc-opc.c (arc_ext_opcodes): Define.
+	(arc_ext_operands): Define.
+	* i386-dis.c (Suffix3DNow): Declare as const.
+	* arm-opc.h (arm_opcodes): Declare as const.
+	(thumb_opcodes): Declare as const.
+	* h8500-opc.h (h8500_table): Declare as const.
+	(h8500_table): Use a NULL for the opcode in the terminator, so
+	that code testing (opcode->name) behaves correctly.
+	* mcore-opc.h (mcore_table): Declare as const.
+	* sh-opc.h (sh_table): Declare as const.
+	* w65-opc.h (optable): Declare as const.
+	* z8k-opc.h (z8k_table): Declare as const.
+
+2002-11-18  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x-dis.c: Added support for enhanced and special insn.
+	(c4x_print_op): Added insn class 'i' and 'j'
+	(c4x_hash_opcode_special): Add to support special insn
+	(c4x_hash_opcode): Update to support the new opcode-list
+	format. Add support for the new special insns.
+	(c4x_disassemble): New opcode-list support.
+
+2002-11-16  Klee Dienes  <kdienes@apple.com>
+
+	* m88k-dis.c: Include libiberty.h (for xmalloc).
+	(HASHTAB): New type, used to build instruction hash tables.
+	Contains a pointer to an INSTAB and a pointer to the next hash
+	chain entry.
+	(instructions): Move definition from m88k.h; remove initialization
+	of 'next' field.
+	(hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB.
+	(printop): Mark pointer to OPSPEC as const.
+	(install): Remove; fold into init_disasm.
+	(m88kdis): Update to ihashtab_initialized to 1 after calling
+	init_disasm.  entry_ptr now iterates through HASHTABs, not
+	INSTABs.
+	(init_disasm): Iterate through the instructions and add to
+	hashtable[].
+
+2002-11-16  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x-dis.c: (c4x_print_op): Add support for the new argument
+	  format. Fix bug in 'N' register printer.
+
+2002-11-12  Segher Boessenkool  <segher@koffie.nl>
+
+	* ppc-dis.c (print_insn_powerpc): Correct condition register display.
+
+2002-11-07  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c (EVUIMM_4): Change bit size to 32.
+	(EVUIMM_2): Same.
+	(EVUIMM_8): Same.
+
+2002-11-07  Klee Dienes  <kdienes@apple.com>
+
+	 * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir'
+	 argument to ia64-gen.
+	 Regenerate dependencies for ia64-len.lo.
+	 * Makefile.in: Regenerate.
+	 * ia64-gen.c: Convert to use getopt().  Add the standard GNU
+	 options, as well as '--srcdir', which controls the directory in
+	 which ia64-gen looks for the sources it uses to generate the
+	 output table.  Add a 'const' to the declaration of the final
+	 output table.  Call xmalloc_set_program_name to set the program
+	 name.
+	 * ia64-asmtab.c: Regenerate.
+
+2002-11-07  Nick Clifton  <nickc@redhat.com>
+
+	* ia64-gen.c: Fix comment formatting and compile time warnings.
+	* ia64-opc-a.c: Fix compile time warnings.
+	* ia64-opc-b.c: Likewise.
+	* ia64-opc-d.c: Likewise.
+	* ia64-opc-f.c: Likewise.
+	* ia64-opc-i.c: Likewise.
+	* ia64-opc-m.c: Likewise.
+	* ia64-opc-x.c: Likewise.
+
+2002-11-06  Aldy Hernandez  <aldyh@redhat.com>
+
+	* ppc-opc.c: Change RD to RS for evmerge*.
+
+2002-10-07  Nathan Tallent  <eraxxon@alumni.rice.edu>
+
+	* sparc-opc.c (sparc_opcodes) <fb, fba, fbe, fbz, fbg, fbge,
+	fbl, fble, fblg, fbn, fbne, fbnz, fbo, fbu, fbue, fbug, fbuge,
+	fbul, fbule>: Add conditional/unconditional branch
+	classification.
+
+2002-10-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-dis.c (print_insn): Treat bitmask and branch operands
+	at the end.
+
+2002-09-30  Gavin Romig-Koch  <gavin@redhat.com>
+	    Ken Raeburn  <raeburn@cygnus.com>
+	    Aldy Hernandez  <aldyh@redhat.com>
+	    Eric Christopher  <echristo@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
+	(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
+	and bfd_mach_mips5500.
+	* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
+	(N411, N412, N5, N54, N55): New convenience defines.
+	(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
+	Change dmadd16 and madd16 from V1 to N411.
+
+2002-09-26  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (print_insn_mips): Always allow disassembly of
+	32-bit jalx opcode.
+
+2002-09-24  Nick Clifton  <nickc@redhat.com>
+
+	* po/de.po: Updated German translation.
+
+2002-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2002-09-20  Nick Clifton  <nickc@redhat.com>
+
+	* ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr
+	register names are accepted.
+
+2002-09-17  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED.
+	Convert functions to K&R format.
+
+2002-09-13  Nick Clifton  <nickc@redhat.com>
+
+	* ppc-opc.c (MFDEC2): Include Book-E.
+	(PPCCHLK64): New opcode mask.
+	(evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid,
+	mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl,
+	mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1,
+	mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr,
+	mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5,
+	mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11,
+	mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0,
+	mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear,
+	mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7,
+	mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3,
+	mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0,
+	mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7,
+	mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13,
+	mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New
+	Book-E instructions.
+	(evfsneg): Fix opcode value.
+	(dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64
+	mask.
+	(mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit
+	Book-E.
+	(extsw): Restrict to 64-bit PPC instruction sets.
+	(extsw.): Does not exist in 64-bit Book-E.
+	(powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as
+	they are no longer needed.
+
+2002-09-12  Gary Hade  <garyhade@us.ibm.com>
+
+	* ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC.
+
+2002-09-11  Nick Clifton  <nickc@redhat.com>
+
+	* po/da.po: Updated Danish translation file.
+
+2002-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* ppc-opc.c (extsw, extsw.): Do not allow for the BookE32.
+
+2002-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* disassemble.c (disassembler_usage): Add invocation of
+	print_ppc_disassembler_options.
+	* ppc-dis.c (print_ppc_disassembler_options): New function.
+
+2002-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* ppc-opc.c: The BookE implementations of the TLBWE and TLBRE
+	instructions do not take any arguments.
+
+2002-09-02  Nick Clifton  <nickc@redhat.com>
+
+	* v850-opc.c: Remove redundant references to V850EA architecture.
+
+2002-09-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* arc-opc.c: Include bfd.h.
+	(arc_get_opcode_mach): Subtract off base bfd_mach value.
+
+2002-08-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* v850-dis.c (disassemble): Remove bfd_mach_v850ea case.
+
+	* mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.
+
+2002-08-28  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* configure.in: Added bfd_tic4x_arch.
+	* configure: Regenerate.
+	* Makefile.am: Added tic4x-dis.o target.
+	* Makefile.in: Regenerate.
+
+2002-08-28  Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
+	* disassemble.c: Added tic4x target and c4x
+	disassembler routine.
+	* tic4x-dis.c: New file.
+
+2002-08-16  Christian Groessler <chris@groessler.org>
+
+	* z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex
+	values as those.
+	* z8kgen.c (opt): Fix definition of "in rd,imm16" opcode.
+	* z8k-opc.h: Regenerated with new z8kgen.c.
+
+2002-08-19  Elena Zannoni  <ezannoni@redhat.com>
+
+	From  matthew green  <mrg@redhat.com>
+
+	* ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
+	`-mefs'. Turn off AltiVec for E500 and efs.
+	(print_insn_powerpc): Don't print an AltiVec instruction if the
+	dialect is not efs.
+
+	* ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2,
+	insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions
+	for extracting pmrn/evld/evstd/etc operands.
+	(CRB, CRFD, CRFS, DC, RD): New instruction fields.
+	(CT): Make this equal to RD + 1.
+	(PMRN): New operand.
+	(RA): Update.
+	(EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands.
+	(WS): Update.
+	(EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL.
+	(ISEL, ISEL_MASK): New instruction form and mask for ISEL.
+	(XISEL, XISEL_MASK): New instruction form and mask for ISEL.
+	(CTX, CTX_MASK): New instruction form and mask for context cache
+	instructions.
+	(UCTX, UCTX_MASK): New instruction form and mask for user context
+	cache instructions.
+	(XC, XC_MASK, XUC, XUC_MASK): New instruction forms.
+	(CLASSIC): New define.
+	(PPCESPE): New define.
+	(PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New
+	defines for integer select, cache control, branch
+	locking, power management, cache locking and machine check
+	APU instructions, respectively.
+	(efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
+	efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
+	efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
+	efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
+	evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
+	evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
+	evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
+	evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi,
+	evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts,
+	evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh,
+	evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx,
+	evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat,
+	evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx,
+	evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe,
+	evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox,
+	evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv,
+	evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq,
+	evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui,
+	evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg,
+	evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq,
+	evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf,
+	evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf,
+	evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi,
+	evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi,
+	evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw,
+	evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw,
+	evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw,
+	evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw,
+	evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw,
+	evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa,
+	evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian,
+	evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf,
+	evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa,
+	evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan,
+	evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa,
+	evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian,
+	evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi,
+	evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi,
+	evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw,
+	evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw,
+	evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa,
+	evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia,
+	evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan,
+	evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw,
+	evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw,
+	evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex
+	instructions.
+	(rfmci): New machine check APU instruction.
+	(isel): New integer select APU instructino.
+	(icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls,
+	dcbtstlse, dcblc, dcblce): New cache control APU instructions.
+	(mtspefscr, mfspefscr): New instructions.
+	(mfpmr, mtpmr): New performance monitor APU instructions.
+	(savecontext): New context cache APU instructions.
+	(bblels, bbelr): New branch locking APU instructions.
+	(bblels, bbelr): New instructions.
+	(mftbl, mftbu, mftb): Set as CLASSIC instructions.  Add BOOKE alias.
+
+2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-opc.c: Update call operand to accept the page definition.
+	Identify instructions that are branches and calls to generate a
+	RL_JUMP relocation.
+
+2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11-dis.c (print_insn): Take into account 68HC12 memory
+	banks and fix disassembling of call instruction.
+	(print_indexed_operand): New param to tell whether
+	it was an indirect addressing operand (for disassembling call).
+
+2002-08-09  Nick Clifton  <nickc@redhat.com>
+
+	* po/sv.po: Updated Swedish translation.
+
+2002-08-08  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as
+	aliases to "daddiu" and "addiu".
+
+2002-07-30  Nick Clifton  <nickc@redhat.com>
+
+	* po/sv.po: Updated Swedish translation.
+
+2002-07-25  Nick Clifton  <nickc@redhat.com>
+
+	* po/sv.po: Updated Swedish translation.
+	* po/es.po: Updated Spanish translation.
+	* po/pr_BR.po: Updated Brazilian Portuguese translation.
+	* po/tr.po: Updated Turkish translation.
+	* po/fr.po: Updated French translation.
+
+2002-07-24  Nick Clifton  <nickc@redhat.com>
+
+	* po/sv.po: Updated Swedish translation.
+	* po/es.po: Updated Spanish translation.
+	* po/pr_BR.po: Updated Brazilian Portuguese translation.
+
+2002-07-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2002-07-23  Nick Clifton  <nickc@redhat.com>
+
+	* po/fr.po: Updated French translation.
+	* po/pr_BR.po: New Brazilian Portuguese translation.
+	* po/id.po: Updated Indonesian translation.
+	* configure.in (LINGUAS): Add pr_BR.
+	* configure: Regenerate.
+
+2002-07-18  Denis Chertykov  <denisc@overta.ru>
+	    Frank Ch. Eigler  <fche@redhat.com>
+	    Alan Lehotsky <alehotsky@cygnus.com>
+	    matthew green  <mrg@redhat.com>
+
+	* configure.in: Add support for ip2k.
+	* configure: Regenerate.
+	* Makefile.am: Add support for ip2k.
+	* Makefile.in: Regenerate.
+	* disassemble.c: Add support for ip2k.
+	* ip2k-asm.c: New generated file.
+	* ip2k-desc.c: New generated file.
+	* ip2k-desc.h: New generated file.
+	* ip2k-dis.c: New generated file.
+	* ip2k-ibld.c: New generated file.
+	* ip2k-opc.c: New generated file.
+	* ip2k-opc.h: New generated file.
+
+2002-07-17  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64-opc-b.c (bWhc): New macro.
+	(mWhc): Ditto.
+	(OpPaWhcD): Ditto.
+	(ia64_opcodes_b): Correct patterns for indirect call
+	instructions to use 3-bit "wh" field.
+	* ia64-asmtab.c: Regnerate.
+
+2002-07-09  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (mips_isa_type): Add MIPS16 insn handling.
+	* mips-opc.c (I16): New define.
+	(mips_builtin_opcodes): Make jalx an I16 insn.
+
+2002-06-18  Dave Brolley  <brolley@redhat.com>
+
+	* po/POTFILES.in: Add frv-*.[ch].
+	* disassemble.c (ARCH_frv): New macro.
+	(disassembler): Handle bfd_arch_frv.
+	* configure.in: Support frv_bfd_arch.
+	* Makefile.am (HFILES): Add frv-*.h.
+	(CFILES): Add frv-*.c
+	(ALL_MACHINES): Add frv-*.lo.
+	(CLEANFILES): Add stamp-frv.
+	(FRV_DEPS): New variable.
+	(stamp-frv): New target.
+	(frv-asm.lo): New target.
+	(frv-desc.lo): New target.
+	(frv-dis.lo): New target.
+	(frv-ibld.lo): New target.
+	(frv-opc.lo): New target.
+	(frv-*.[ch]): New files.
+
+2002-06-18  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen.
+	* Makefile.in: Regenerate.
+
+2002-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* a29k-dis.c: Replace CONST with const.
+	* h8300-dis.c: Likewise.
+	* m68k-dis.c: Likewise.
+	* or32-dis.c: Likewise.
+	* sparc-dis.c: Likewise.
+
+2002-06-04  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* configure.in: Add "sh5*-*" to list of targets which include
+	sh64 support.
+	* configure: Regenerate.
+
+2002-05-31  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c: Clean up a few whitespace issues, and sort a
+	few entries understanding that 'x' follows 'w' in the alphabet.
+
+2002-05-31  Chris G. Demetriou  <cgd@broadcom.com>
+	    Ed Satterthwaite  <ehs@broadcom.com>
+
+	* mips-opc.c: Add support for SB-1 MDMX subset and extensions.
+
+2002-05-31  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
+	    Ed Satterthwaite  <ehs@broadcom.com>
+
+	* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
+	and 'Z' formats, for MDMX.
+	(mips_isa_type): Add MDMX instructions to the ISA
+	bit mask for bfd_mach_mipsisa64.
+	* mips-opc.c: Add support for MDMX instructions.
+	(MX): New definition.
+
+	* mips-dis.c: Update copyright years to include 2002.
+
+2002-05-30  Diego Novillo  <dnovillo@redhat.com>
+
+	* d10v-opc.c (d10v_opcodes): `btsti' does not modify its
+	arguments.
+
+2002-05-28  Kuang Hwa Lin <kuang@sbcglobal.net>
+
+	* configure.in: Add DLX configuraton support.
+	* configure: Regenerate.
+	* Makefile.am: Add DLX configuraton support.
+	* Makefile.in: Regenerate.
+	* disassemble.c: Add DLX support.
+	* dlx-dis.c: New file.
+
+2002-05-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (sh-dis.lo): Don't put make commands in deps.
+	* Makefile.in: Regenerate.
+	* arc-dis.c: Use #include "" instead of <> for local header files.
+	* m68k-dis.c: Likewise.
+
+2002-05-22  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* Makefile.am (sh-dis.lo): Compile with @archdefs@.
+	* Makefile.in: regenerate.
+
+	* sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4
+	for disassembly.
+
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-opc.c (mips_builtin_opcodes): Add drol, dror macros.
+
+2002-05-17  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
+	* sh-dis.c (LITTLE_BIT): Delete.
+	(print_insn_sh, print_insn_shl): Deleted.
+	(print_insn_shx): Renamed to
+	(print_insn_sh).  No longer static.  Handle SHmedia instructions.
+	Use info->endian to determine endianness.
+	* sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete.
+	(print_insn_sh64x): No longer static.  Renamed to
+	(print_insn_sh64).  Removed pfun_compact and endian arguments.
+	If we got an uneven address to indicate SHmedia, adjust it.
+	Return -2 for SHcompact instructions.
+
+2002-05-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools.
+	* configure.in: Invoke AM_INSTALL_LIBBFD.
+	* Makefile.am (install-data-local): Move to..
+	(install_libopcodes): .. New target.
+	(uninstall_libopcodes): Likewise.
+	(install-bfdlibLTLIBRARIES): Likewise.
+	(uninstall-bfdlibLTLIBRARIES): Likewise.
+	(bfdlibdir): New.
+	(bfdincludedir): New.
+	(lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES.
+	* aclocal.m4: Regenerate.
+	* configure: Regenerate.
+	* Makefile.in: Regenerate.
+
+2002-05-15  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* fr30-asm.c: Regenerate.
+	* fr30-desc.c: Regenerate.
+	* fr30-dis.c: Regenerate.
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* openrisc-asm.c: Regenerate.
+	* openrisc-desc.c: Regenerate.
+	* openrisc-dis.c: Regenerate.
+	* xstormy16-asm.c: Regenerate.
+	* xstormy16-desc.c: Regenerate.
+	* xstormy16-dis.c: Regenerate.
+
+2002-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips-dis.c (is_newabi): EABI is not a NewABI.
+
+2002-05-13  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* configure.in (shle-*-*elf*): Include sh64 support.
+	* configure: Regenerate.
+
+2002-04-28  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode.
+	(print_insn_mode): Print some basic info about floating point values.
+
+2002-05-09  Anton Blanchard  <anton@samba.org>
+
+	* ppc-opc.c: Add "tlbiel" for POWER4.
+
+2002-05-07  Graydon Hoare  <graydon@redhat.com>
+
+	* cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather
+	than just most-recently-opened.
+
+2002-05-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke.
+
+2002-04-24  Christian Groessler <chris@groessler.org>
+
+	* z8k-dis.c (print_insn_z8k): Set disassemble_info to 2
+	bytes_per_chunk, 6 bytes_per_line for nicer display of the hex
+	codes.
+	(z8k_lookup_instr): CLASS_IGNORE case added.
+	(output_instr): Don't print hex codes, they are already
+	printed.
+	(unpack_instr): ARG_NIM4 case added.  ARG_NIM8 case
+	fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases.
+	(unparse_instr): Fix base and indexed addressing disassembly:
+	The index is inside the brackets.
+	* z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines.
+	(opt): Fix shift left/right arithmetic/logical byte defines:
+	The high byte of the immediate word is ignored by the
+	processor.
+	Fix n parameter of ldm opcodes: The opcode contains (n-1).
+	(args): Fix "n" entry.
+	(toks): Add "nim4" and "iiii" entries.
+	* z8k-opc.h: Regenerated with new z8kgen.c.
+
+2002-04-24  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/id.po: New Indonesian translation.
+	* configure.in (ALL_LIGUAS): Add id.po
+	* configure: Regenerate.
+
+2002-04-17  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (powerpc_opcode): Fix dssall operand list.
+
+2002-04-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* dep-in.sed: Cope with absolute paths.
+	* Makefile.am (dep.sed): Subst TOPDIR.
+	Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* ppc-opc.c: Whitespace.
+	* s390-dis.c: Fix copyright date.
+
+2002-03-23  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (vmaddfp): Fix operand order.
+
+2002-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2002-03-21  Anton Blanchard  <anton@samba.org>
+
+	* ppc-opc.c: Add optional field to mtmsrd.
+	(MTMSRD_L, XRLARB_MASK): Define.
+
+2002-03-18  Jan Hubicka  <jh@suse.cz>
+
+	* i386-dis.c (prefix_name): Fix handling of 32bit address prefix
+	in 64bit mode.
+	(print_insn) Likewise.
+	(putop): Fix handling of 'E'
+	(OP_E, OP_OFF): handle 32bit addressing mode in 64bit.
+	(ptr_reg): Likewise.
+
+2002-03-18  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/fr.po: Updated version.
+
+2002-03-16  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (M3D): Tweak comment.
+	(mips_builtin_op): Add comment indicating that opcodes of the
+	same name must be placed together in the table, and sort
+	the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt",
+	"rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name.
+
+2002-03-16  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* Makefile.am: Tidy up sh64 rules.
+	* Makefile.in: Regenerate.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c: Update copyright years.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA
+	bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64.  Add
+	comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that
+	indicate that they should dissassemble all applicable
+	MIPS-specified ASEs.
+	* mips-opc.c: Add support for MIPS-3D instructions.
+	(M3D): New definition.
+
+	* mips-opc.c: Update copyright years.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name.
+
+2002-03-15  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (is_newabi): Fix ABI decoding.
+
+2002-03-14  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32
+	and bfd_mach_mipsisa64 cases to match the rest.
+
+2002-03-13  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/fr.po: Updated version.
+
+2002-03-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-opc.c: Add optional `L' field to tlbie.
+	(XRTLRA_MASK): Define.
+
+2002-03-06  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Mark "pref" as being
+	present on I4.
+
+	* mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps".
+
+2002-03-05  Paul Koning  <pkoning@equallogic.com>
+
+	* pdp11-opc.c: Fix "mark" operand type.  Fix operand types
+	for float opcodes that take float operands.  Add alternate
+	names (xxxD vs. xxxF) for float opcodes.
+	* pdp11-dis.c (print_operand): Clean up formatting for mode 67.
+	(print_foperand): New function to handle float opcode operands.
+	(print_insn_pdp11): Use print_foperand to disassemble float ops.
+
+2002-02-27  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/de.po: Updated.
+
+2002-02-26  Brian Gaeke  <brg@dgate.org>
+
+	* Makefile.am (install-data-local): Install dis-asm.h.
+
+2002-02-26  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* configure.in (LINGUAS): Add de.po.
+	* configure: Regenerate.
+	* po/de.po: New file.
+
+2002-02-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc-dis.c (powerpc_dialect): Handle power4 option.
+	* ppc-opc.c (insert_bdm): Correct description of "at" branch
+	hints.  Test PPC_OPCODE_POWER4 to determine branch hint flavour.
+	(extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise.
+	(BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc.
+	(BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise.
+	(PPCCOM32, PPCCOM64): Delete.
+	(NOPOWER4, POWER4): Define.
+	(powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4,
+	and PPCCOM4 with POWER4 so that "at" style branch hint opcodes
+	are enabled for power4 rather than ppc64.
+
+2002-02-20  Tom Rix  <trix@redhat.com>
+
+	* ppc-opc.c (powerpc_operands): Add WS field.  Use for tlbre, tlbwe.
+
+2002-02-19  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-dis.c (init_disasm): Use renamed architecture defines.
+
+2002-02-19  matthew green  <mrg@redhat.com>
+
+	* ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola
+	specific.
+
+2002-02-18  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/tr.po: Updated translation.
+
+2002-02-15  Richard Henderson  <rth@redhat.com>
+
+	* alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo
+	disassembly mask.
+
+2002-02-15  Richard Henderson  <rth@redhat.com>
+
+	* alpha-opc.c (alpha_opcodes): Add simple pseudos for
+	lda, ldah, jmp, ret.
+
+2002-02-14  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/da.po: Updated translation.
+
+2002-02-12  Graydon Hoare  <graydon@redhat.com>
+
+	* cgen-asm.in (parse_insn_normal): Change call from
+	@arch@_cgen_parse_operand to cd->parse_operand, to
+	facilitate CGEN_ASM_INIT_HOOK doing useful work.
+
+2002-02-11  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not
+	sign-extended.
+
+2002-02-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: "make dep-am".
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+
+2002-02-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* configure.in <bfd_sh_arc>: For sh-* and shl-*, enable sh64
+	support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and
+	shl-*-linux*.
+	* configure: Regenerate.
+
+2002-02-10  Daniel Jacobowitz  <drow@mvista.com>
+
+	* cgen-dis.c: Add prototypes for count_decodable_bits
+	and add_insn_to_hash_chain.
+
+2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	* configure.in <bfd_sh_arc>: Enable sh64 support on sh-*.
+	* configure: Rebuilt.
+
+2002-02-08  Ivan Guzvinec <ivang@opencores.org>
+
+	* or32-opc.c: Fix compile time warning messages.
+	* or32-dis.c: Fix compile time warning messages.
+
+2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	Contribute sh64-elf.
+	2001-10-08  Nick Clifton  <nickc@cambridge.redhat.com>
+	* sh64-opc.c: Regenerate.
+	2001-03-13  DJ Delorie  <dj@redhat.com>
+	* sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its
+	purpose is more obvious.
+	* sh64-opc.c (shmedia_table): Ditto.
+	* sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto.
+	(print_insn_shmedia): Ditto.
+	2001-03-12  DJ Delorie  <dj@redhat.com>
+	* sh64-opc.c: Adjust comments to reflect reality: replace bits
+	3:0 with zeros (not "reserved"), replace "rrrrrr" with
+	"gggggg" for two-operand floating point opcodes.  Remove
+	"fsina".
+	2001-01-08  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-dis.c (print_insn_shmedia) <failing read_memory_func>:
+	Correct printing of .byte:s.  Return number of printed bytes or
+	-1; never 0.
+	(print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto.  Print as .byte:s
+	to next four-byte-alignment if insn or data is not aligned.
+	2001-01-06  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-dis.c: Update comments and fix comment formatting.
+	(initialize_shmedia_opcode_mask_table) <case A_IMMM>:
+	Abort instead of setting length to 0.
+	(crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb,
+	crange_bsearch_cmpl, sh64_get_contents_type,
+	sh64_address_in_cranges): Move to bfd/elf32-sh64.c.
+	2001-01-05  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-opc.c: Remove #if 0:d entries for instructions not found in
+	SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo.
+	2000-12-30  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed
+	address with same prefix as SHcompact.
+	In the disassembler, use a .cranges section for linked executables.
+	* sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file
+	and update for using structure in info->private_data.
+	(struct sh64_disassemble_info): New.
+	(is_shmedia_p): Delete.
+	(crange_qsort_cmpb): New function.
+	(crange_qsort_cmpl, crange_bsearch_cmpb): New functions.
+	(crange_bsearch_cmpl, sh64_address_in_cranges): New functions.
+	(init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions.
+	(sh64_get_contents_type, sh64_address_is_shmedia): New functions.
+	(print_insn_shmedia): Correct displaying of address after MOVI/SHORI
+	pair.  Display addresses for linked executables only.
+	(print_insn_sh64x_media): Initialize info->private_data by calling
+	init_sh64_disasm_info.
+	(print_insn_sh64x): Ditto.  Find out type of contents by calling
+	sh64_contents_type_disasm.  Display data regions using ".long" and
+	".byte" similar to unrecognized opcodes.
+	2000-12-19  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-dis.c (is_shmedia_p): Check info->section and look for ISA
+	information in section flags before considering symbols.  Don't
+	assume an info->mach setting of bfd_mach_sh5 means SHmedia code.
+	* configure.in (bfd_sh_arch): Check presence of sh64 insns by
+	matching $target $canon_targets instead of looking at the
+	now-removed -DINCLUDE_SHMEDIA in $targ_cflags.
+	* configure: Regenerate.
+	2000-11-25  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-opc.c (shmedia_creg_table): New.
+	* sh64-opc.h (shmedia_creg_info): New type.
+	(shmedia_creg_table): Declare.
+	* sh64-dis.c (creg_name): New function.
+	(print_insn_shmedia): Use it.
+	* disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map
+	bfd_mach_sh5 to print_insn_sh64 if big-endian and to
+	print_insn_sh64l if little-endian.
+	* sh64-dis.c (print_insn_shmedia): Make r unsigned.
+	(print_insn_sh64l): New.
+	(print_insn_sh64x): New.
+	(print_insn_sh64x_media): New.
+	(print_insn_sh64): Break out code to print_insn_sh64x and
+	print_insn_sh64x_media.
+	2000-11-24  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh64-opc.h: New file
+	* sh64-opc.c: New file
+	* sh64-dis.c: New file
+	* Makefile.am: Add sh64 targets.
+	(HFILES): Add sh64-opc.h.
+	(CFILES): Add sh64-opc.c and sh64-dis.c.
+	(ALL_MACHINES): Add sh64 files.
+	* Makefile.in: Regenerate.
+	* configure.in: Add support for sh64 to bfd_sh_arch.
+	* configure: Regenerate.
+	* disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define.
+	(disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to
+	print_insn_sh64.
+	* sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2002-02-04  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets.
+
+2002-02-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS.
+
+2002-02-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am"
+	* Makefile.in: Regenerate.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+	* or32-dis.c: New file.
+	* or32-opc.c: New file.
+	* configure.in: Add support for or32.
+	* configure: Regenerate.
+	* Makefile.am: Add support for or32.
+	* Makefile.in: Regenerate.
+	* disassemble.c: Add support for or32.
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2002-01-27  Daniel Jacobowitz  <drow@mvista.com>
+
+	* configure: Regenerated.
+
+2002-01-26  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/fr.po: Updated version.
+
+2002-01-25  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/es.po: Updated version.
+
+2002-01-24  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/da.po: New version.
+
+2002-01-23  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/da.po: New file: Spanish translation.
+	* configure.in (ALL_LINGUAS): Add da.
+	* configure: Regenerate.
+
+2002-01-22  Graydon Hoare  <graydon@redhat.com>
+
+	* fr30-asm.c: Regenerate.
+	* fr30-desc.c: Likewise.
+	* fr30-desc.h: Likewise.
+	* fr30-dis.c: Likewise.
+	* fr30-ibld.c: Likewise.
+	* fr30-opc.c: Likewise.
+	* fr30-opc.h: Likewise.
+	* m32r-asm.c: Likewise.
+	* m32r-desc.c: Likewise.
+	* m32r-desc.h: Likewise.
+	* m32r-dis.c: Likewise.
+	* m32r-ibld.c: Likewise.
+	* m32r-opc.c: Likewise.
+	* m32r-opc.h: Likewise.
+	* m32r-opinst.c: Likewise.
+	* openrisc-asm.c: Likewise.
+	* openrisc-desc.c: Likewise.
+	* openrisc-desc.h: Likewise.
+	* openrisc-dis.c: Likewise.
+	* openrisc-ibld.c: Likewise.
+	* openrisc-opc.c: Likewise.
+	* openrisc-opc.h: Likewise.
+	* xstormy16-desc.c: Likewise.
+
+2002-01-22  Richard Henderson  <rth@redhat.com>
+
+	* alpha-dis.c (print_insn_alpha): Also mask the base opcode for
+	comparison.
+
+2002-01-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2002-01-19  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h.
+	* arm-dis.c (print_insn_arm): Don't handle 'h' case.
+
+2002-01-18  Keith Walker  <keith.walker@arm.com>
+
+	* arm-opc.h (arm_opcodes): Add bxj instruction.
+
+2002-01-17  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/opcodes.pot: Regenerate.
+	* po/fr.po: Regenerate.
+	* po/sv.po: Regenerate.
+	* po/tr.po: Regenerate.
+
+2002-01-16  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/tr.po: Import new version.
+
+2002-01-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm-opc.h (arm_opcodes): Add patterns for VFP instructions.
+	* arm-dis.c (print_insn_arm): Support new disassembly qualifiers for
+	VFP bitfields.
+
+2002-01-10  matthew green  <mrg@redhat.com>
+
+	* xstormy16-asm.c: Regenerate.
+	* xstormy16-desc.c: Likewise.
+	* xstormy16-desc.h: Likewise.
+	* xstormy16-dis.c: Likewise.
+	* xstormy16-opc.c: Likewise.
+	* xstormy16-opc.h: Likewise.
+
+2002-01-07  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* po/es.po: New file: Spanish translation.
+	* configure.in (ALL_LINGUAS): Add es.
+	* configure: Regenerate.
+
+For older changes see ChangeLog-0001
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gnu/usr.bin/binutils/opcodes/alpha-opc.c b/gnu/usr.bin/binutils/opcodes/alpha-opc.c
index 8dc10e4a55b..53715975721 100644
--- a/gnu/usr.bin/binutils/opcodes/alpha-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/alpha-opc.c
@@ -1,5 +1,5 @@
 /* alpha-opc.c -- Alpha AXP opcode list
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
    Contributed by Richard Henderson <rth@cygnus.com>,
    patterned after the PPC opcode handling written by Ian Lance Taylor.
 
@@ -214,7 +214,6 @@ const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operand
    the RA field into the RB field, and the extraction function just
    checks that the fields are the same. */
 
-/*ARGSUSED*/
 static unsigned
 insert_rba(insn, value, errmsg)
      unsigned insn;
@@ -238,7 +237,6 @@ extract_rba(insn, invalid)
 
 /* The same for the RC field */
 
-/*ARGSUSED*/
 static unsigned
 insert_rca(insn, value, errmsg)
      unsigned insn;
@@ -262,7 +260,6 @@ extract_rca(insn, invalid)
 
 /* Fake arguments in which the registers must be set to ZERO */
 
-/*ARGSUSED*/
 static unsigned
 insert_za(insn, value, errmsg)
      unsigned insn;
@@ -282,7 +279,6 @@ extract_za(insn, invalid)
   return 0;
 }
 
-/*ARGSUSED*/
 static unsigned
 insert_zb(insn, value, errmsg)
      unsigned insn;
@@ -302,7 +298,6 @@ extract_zb(insn, invalid)
   return 0;
 }
 
-/*ARGSUSED*/
 static unsigned
 insert_zc(insn, value, errmsg)
      unsigned insn;
@@ -336,7 +331,6 @@ insert_bdisp(insn, value, errmsg)
   return insn | ((value / 4) & 0x1FFFFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_bdisp(insn, invalid)
      unsigned insn;
@@ -359,7 +353,6 @@ insert_jhint(insn, value, errmsg)
   return insn | ((value / 4) & 0x3FFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_jhint(insn, invalid)
      unsigned insn;
@@ -381,7 +374,6 @@ insert_ev6hwjhint(insn, value, errmsg)
   return insn | ((value / 4) & 0x1FFF);
 }
 
-/*ARGSUSED*/
 static int
 extract_ev6hwjhint(insn, invalid)
      unsigned insn;
@@ -1105,7 +1097,8 @@ const struct alpha_opcode alpha_opcodes[] = {
   { "wmb",		MFC(0x18,0x4400), BASE, ARG_NONE },
   { "fetch",		MFC(0x18,0x8000), BASE, { ZA, PRB } },
   { "fetch_m",		MFC(0x18,0xA000), BASE, { ZA, PRB } },
-  { "rpcc",		MFC(0x18,0xC000), BASE, { RA } },
+  { "rpcc",		MFC(0x18,0xC000), BASE, { RA, ZB } },
+  { "rpcc",		MFC(0x18,0xC000), BASE, { RA, RB } },	/* ev6 una */
   { "rc",		MFC(0x18,0xE000), BASE, { RA } },
   { "ecb",		MFC(0x18,0xE800), BASE, { ZA, PRB } },	/* ev56 una */
   { "rs",		MFC(0x18,0xF000), BASE, { RA } },
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-asm.c b/gnu/usr.bin/binutils/opcodes/cgen-asm.c
index c71c70de08e..7231e2d7aed 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/cgen-asm.c
@@ -28,16 +28,14 @@
 #include "opcode/cgen.h"
 #include "opintl.h"
 
-static CGEN_INSN_LIST *  hash_insn_array      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *));
-static CGEN_INSN_LIST *  hash_insn_list       PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *));
-static void              build_asm_hash_table PARAMS ((CGEN_CPU_DESC));
+static CGEN_INSN_LIST *  hash_insn_array      (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *);
+static CGEN_INSN_LIST *  hash_insn_list       (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *);
+static void              build_asm_hash_table (CGEN_CPU_DESC);
 
 /* Set the cgen_parse_operand_fn callback.  */
 
 void
-cgen_set_parse_operand_fn (cd, fn)
-     CGEN_CPU_DESC cd;
-     cgen_parse_operand_fn fn;
+cgen_set_parse_operand_fn (CGEN_CPU_DESC cd, cgen_parse_operand_fn fn)
 {
   cd->parse_operand_fn = fn;
 }
@@ -45,8 +43,7 @@ cgen_set_parse_operand_fn (cd, fn)
 /* Called whenever starting to parse an insn.  */
 
 void
-cgen_init_parse_operand (cd)
-     CGEN_CPU_DESC cd;
+cgen_init_parse_operand (CGEN_CPU_DESC cd)
 {
   /* This tells the callback to re-initialize.  */
   (void) (* cd->parse_operand_fn)
@@ -66,13 +63,12 @@ cgen_init_parse_operand (cd)
    list and we want earlier ones to be prefered.  */
 
 static CGEN_INSN_LIST *
-hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insns;
-     int count;
-     int entsize ATTRIBUTE_UNUSED;
-     CGEN_INSN_LIST **htable;
-     CGEN_INSN_LIST *hentbuf;
+hash_insn_array (CGEN_CPU_DESC cd,
+		 const CGEN_INSN *insns,
+		 int count,
+		 int entsize ATTRIBUTE_UNUSED,
+		 CGEN_INSN_LIST **htable,
+		 CGEN_INSN_LIST *hentbuf)
 {
   int i;
 
@@ -97,11 +93,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
    in a list.  */
 
 static CGEN_INSN_LIST *
-hash_insn_list (cd, insns, htable, hentbuf)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN_LIST *insns;
-     CGEN_INSN_LIST **htable;
-     CGEN_INSN_LIST *hentbuf;
+hash_insn_list (CGEN_CPU_DESC cd,
+		const CGEN_INSN_LIST *insns,
+		CGEN_INSN_LIST **htable,
+		CGEN_INSN_LIST *hentbuf)
 {
   const CGEN_INSN_LIST *ilist;
 
@@ -123,8 +118,7 @@ hash_insn_list (cd, insns, htable, hentbuf)
 /* Build the assembler instruction hash table.  */
 
 static void
-build_asm_hash_table (cd)
-     CGEN_CPU_DESC cd;
+build_asm_hash_table (CGEN_CPU_DESC cd)
 {
   int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd);
   CGEN_INSN_TABLE *insn_table = &cd->insn_table;
@@ -179,9 +173,7 @@ build_asm_hash_table (cd)
 /* Return the first entry in the hash list for INSN.  */
 
 CGEN_INSN_LIST *
-cgen_asm_lookup_insn (cd, insn)
-     CGEN_CPU_DESC cd;
-     const char *insn;
+cgen_asm_lookup_insn (CGEN_CPU_DESC cd, const char *insn)
 {
   unsigned int hash;
 
@@ -201,11 +193,10 @@ cgen_asm_lookup_insn (cd, insn)
    recording something in the keyword table].  */
 
 const char *
-cgen_parse_keyword (cd, strp, keyword_table, valuep)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     const char **strp;
-     CGEN_KEYWORD *keyword_table;
-     long *valuep;
+cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    const char **strp,
+		    CGEN_KEYWORD *keyword_table,
+		    long *valuep)
 {
   const CGEN_KEYWORD_ENTRY *ke;
   char buf[256];
@@ -262,11 +253,10 @@ cgen_parse_keyword (cd, strp, keyword_table, valuep)
    cgen_parse_address.  */
 
 const char *
-cgen_parse_signed_integer (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     long *valuep;
+cgen_parse_signed_integer (CGEN_CPU_DESC cd,
+			   const char **strp,
+			   int opindex,
+			   long *valuep)
 {
   bfd_vma value;
   enum cgen_parse_operand_result result;
@@ -287,11 +277,10 @@ cgen_parse_signed_integer (cd, strp, opindex, valuep)
    cgen_parse_address.  */
 
 const char *
-cgen_parse_unsigned_integer (cd, strp, opindex, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     unsigned long *valuep;
+cgen_parse_unsigned_integer (CGEN_CPU_DESC cd,
+			     const char **strp,
+			     int opindex,
+			     unsigned long *valuep)
 {
   bfd_vma value;
   enum cgen_parse_operand_result result;
@@ -309,13 +298,12 @@ cgen_parse_unsigned_integer (cd, strp, opindex, valuep)
 /* Address parser.  */
 
 const char *
-cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep)
-     CGEN_CPU_DESC cd;
-     const char **strp;
-     int opindex;
-     int opinfo;
-     enum cgen_parse_operand_result *resultp;
-     bfd_vma *valuep;
+cgen_parse_address (CGEN_CPU_DESC cd,
+		    const char **strp,
+		    int opindex,
+		    int opinfo,
+		    enum cgen_parse_operand_result *resultp,
+		    bfd_vma *valuep)
 {
   bfd_vma value;
   enum cgen_parse_operand_result result_type;
@@ -337,8 +325,7 @@ cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep)
 /* Signed integer validation routine.  */
 
 const char *
-cgen_validate_signed_integer (value, min, max)
-     long value, min, max;
+cgen_validate_signed_integer (long value, long min, long max)
 {
   if (value < min || value > max)
     {
@@ -358,8 +345,9 @@ cgen_validate_signed_integer (value, min, max)
    cases where min != 0 (and max > LONG_MAX).  */
 
 const char *
-cgen_validate_unsigned_integer (value, min, max)
-     unsigned long value, min, max;
+cgen_validate_unsigned_integer (unsigned long value,
+				unsigned long min,
+				unsigned long max)
 {
   if (value < min || value > max)
     {
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-asm.in b/gnu/usr.bin/binutils/opcodes/cgen-asm.in
index 525177c79d0..420f640ec3b 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-asm.in
+++ b/gnu/usr.bin/binutils/opcodes/cgen-asm.in
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -60,8 +60,7 @@ static const char * parse_insn_normal
    Returns NULL for success, an error message for failure.  */
 
 char * 
-@arch@_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+@arch@_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -184,11 +183,10 @@ char *
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -326,12 +324,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -361,10 +358,10 @@ const CGEN_INSN *
       if (! @arch@_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -435,9 +432,7 @@ const CGEN_INSN *
    FIXME: Not currently used.  */
 
 void
-@arch@_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-dis.c b/gnu/usr.bin/binutils/opcodes/cgen-dis.c
index 881ee1470f3..ca621dec2d3 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/cgen-dis.c
@@ -27,19 +27,18 @@
 #include "symcat.h"
 #include "opcode/cgen.h"
 
-static CGEN_INSN_LIST *  hash_insn_array      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *));
-static CGEN_INSN_LIST *  hash_insn_list       PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *));
-static void              build_dis_hash_table PARAMS ((CGEN_CPU_DESC));
-static int		 count_decodable_bits PARAMS ((const CGEN_INSN *));
-static void		 add_insn_to_hash_chain PARAMS ((CGEN_INSN_LIST *,
-							 const CGEN_INSN *,
-							 CGEN_INSN_LIST **,
-							 unsigned int));
+static CGEN_INSN_LIST *  hash_insn_array        (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *);
+static CGEN_INSN_LIST *  hash_insn_list         (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *);
+static void              build_dis_hash_table   (CGEN_CPU_DESC);
+static int		 count_decodable_bits   (const CGEN_INSN *);
+static void		 add_insn_to_hash_chain (CGEN_INSN_LIST *,
+						 const CGEN_INSN *,
+						 CGEN_INSN_LIST **,
+						 unsigned int);
 
 /* Return the number of decodable bits in this insn.  */
 static int
-count_decodable_bits (insn)
-  const CGEN_INSN *insn;
+count_decodable_bits (const CGEN_INSN *insn)
 {
   unsigned mask = CGEN_INSN_BASE_MASK (insn);
   int bits = 0;
@@ -54,11 +53,10 @@ count_decodable_bits (insn)
 
 /* Add an instruction to the hash chain.  */     
 static void
-add_insn_to_hash_chain (hentbuf, insn, htable, hash)
-     CGEN_INSN_LIST *hentbuf;
-     const CGEN_INSN *insn;
-     CGEN_INSN_LIST **htable;
-     unsigned int hash;
+add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf,
+			const CGEN_INSN *insn,
+			CGEN_INSN_LIST **htable,
+			unsigned int hash)
 {
   CGEN_INSN_LIST *current_buf;
   CGEN_INSN_LIST *previous_buf;
@@ -100,13 +98,12 @@ add_insn_to_hash_chain (hentbuf, insn, htable, hash)
    list and we want earlier ones to be prefered.  */
 
 static CGEN_INSN_LIST *
-hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insns;
-     int count;
-     int entsize ATTRIBUTE_UNUSED;
-     CGEN_INSN_LIST ** htable;
-     CGEN_INSN_LIST * hentbuf;
+hash_insn_array (CGEN_CPU_DESC cd,
+		 const CGEN_INSN * insns,
+		 int count,
+		 int entsize ATTRIBUTE_UNUSED,
+		 CGEN_INSN_LIST ** htable,
+		 CGEN_INSN_LIST * hentbuf)
 {
   int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG;
   int i;
@@ -141,11 +138,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
    in a list.  */
 
 static CGEN_INSN_LIST *
-hash_insn_list (cd, insns, htable, hentbuf)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN_LIST *insns;
-     CGEN_INSN_LIST **htable;
-     CGEN_INSN_LIST *hentbuf;
+hash_insn_list (CGEN_CPU_DESC cd,
+		const CGEN_INSN_LIST *insns,
+		CGEN_INSN_LIST **htable,
+		CGEN_INSN_LIST *hentbuf)
 {
   int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG;
   const CGEN_INSN_LIST *ilist;
@@ -177,8 +173,7 @@ hash_insn_list (cd, insns, htable, hentbuf)
 /* Build the disassembler instruction hash table.  */
 
 static void
-build_dis_hash_table (cd)
-     CGEN_CPU_DESC cd;
+build_dis_hash_table (CGEN_CPU_DESC cd)
 {
   int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd);
   CGEN_INSN_TABLE *insn_table = & cd->insn_table;
@@ -233,10 +228,7 @@ build_dis_hash_table (cd)
 /* Return the first entry in the hash list for INSN.  */
 
 CGEN_INSN_LIST *
-cgen_dis_lookup_insn (cd, buf, value)
-     CGEN_CPU_DESC cd;
-     const char * buf;
-     CGEN_INSN_INT value;
+cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value)
 {
   unsigned int hash;
 
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-dis.in b/gnu/usr.bin/binutils/opcodes/cgen-dis.in
index 9203b71d027..1a3c0fa59d6 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-dis.in
+++ b/gnu/usr.bin/binutils/opcodes/cgen-dis.in
@@ -41,34 +41,32 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -88,13 +86,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -118,12 +115,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -137,17 +133,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -179,14 +174,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -210,12 +204,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -320,10 +313,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -362,9 +352,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_@arch@ (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-ibld.in b/gnu/usr.bin/binutils/opcodes/cgen-ibld.in
index d2bfd02a91f..316f183c41e 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-ibld.in
+++ b/gnu/usr.bin/binutils/opcodes/cgen-ibld.in
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
diff --git a/gnu/usr.bin/binutils/opcodes/cgen-opc.c b/gnu/usr.bin/binutils/opcodes/cgen-opc.c
index 06544ca057d..882b34898be 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/cgen-opc.c
@@ -33,11 +33,11 @@
 #endif
 
 static unsigned int hash_keyword_name
-  PARAMS ((const CGEN_KEYWORD *, const char *, int));
+  (const CGEN_KEYWORD *, const char *, int);
 static unsigned int hash_keyword_value
-  PARAMS ((const CGEN_KEYWORD *, unsigned int));
+  (const CGEN_KEYWORD *, unsigned int);
 static void build_keyword_hash_tables
-  PARAMS ((CGEN_KEYWORD *));
+  (CGEN_KEYWORD *);
 
 /* Return number of hash table entries to use for N elements.  */
 #define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31)
@@ -46,9 +46,7 @@ static void build_keyword_hash_tables
    The result is the keyword entry or NULL if not found.  */
 
 const CGEN_KEYWORD_ENTRY *
-cgen_keyword_lookup_name (kt, name)
-     CGEN_KEYWORD *kt;
-     const char *name;
+cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name)
 {
   const CGEN_KEYWORD_ENTRY *ke;
   const char *p,*n;
@@ -87,9 +85,7 @@ cgen_keyword_lookup_name (kt, name)
    The result is the keyword entry or NULL if not found.  */
 
 const CGEN_KEYWORD_ENTRY *
-cgen_keyword_lookup_value (kt, value)
-     CGEN_KEYWORD *kt;
-     int value;
+cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value)
 {
   const CGEN_KEYWORD_ENTRY *ke;
 
@@ -111,9 +107,7 @@ cgen_keyword_lookup_value (kt, value)
 /* Add an entry to a keyword table.  */
 
 void
-cgen_keyword_add (kt, ke)
-     CGEN_KEYWORD *kt;
-     CGEN_KEYWORD_ENTRY *ke;
+cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke)
 {
   unsigned int hash;
   size_t i;
@@ -159,9 +153,7 @@ cgen_keyword_add (kt, ke)
    It is passed to each call to cgen_keyword_search_next.  */
 
 CGEN_KEYWORD_SEARCH
-cgen_keyword_search_init (kt, spec)
-     CGEN_KEYWORD *kt;
-     const char *spec;
+cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec)
 {
   CGEN_KEYWORD_SEARCH search;
 
@@ -183,8 +175,7 @@ cgen_keyword_search_init (kt, spec)
    The result is the next entry or NULL if there are no more.  */
 
 const CGEN_KEYWORD_ENTRY *
-cgen_keyword_search_next (search)
-     CGEN_KEYWORD_SEARCH *search;
+cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search)
 {
   /* Has search finished?  */
   if (search->current_hash == search->table->hash_table_size)
@@ -218,10 +209,9 @@ cgen_keyword_search_next (search)
    If CASE_SENSITIVE_P is non-zero, return a case sensitive hash.  */
 
 static unsigned int
-hash_keyword_name (kt, name, case_sensitive_p)
-     const CGEN_KEYWORD *kt;
-     const char *name;
-     int case_sensitive_p;
+hash_keyword_name (const CGEN_KEYWORD *kt,
+		   const char *name,
+		   int case_sensitive_p)
 {
   unsigned int hash;
 
@@ -237,9 +227,7 @@ hash_keyword_name (kt, name, case_sensitive_p)
 /* Return first entry in hash chain for VALUE.  */
 
 static unsigned int
-hash_keyword_value (kt, value)
-     const CGEN_KEYWORD *kt;
-     unsigned int value;
+hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value)
 {
   return value % kt->hash_table_size;
 }
@@ -249,8 +237,7 @@ hash_keyword_value (kt, value)
    we're using the disassembler, but we keep things simple.  */
 
 static void
-build_keyword_hash_tables (kt)
-     CGEN_KEYWORD *kt;
+build_keyword_hash_tables (CGEN_KEYWORD *kt)
 {
   int i;
   /* Use the number of compiled in entries as an estimate for the
@@ -278,9 +265,7 @@ build_keyword_hash_tables (kt)
    mach/isa.  */
 
 const CGEN_HW_ENTRY *
-cgen_hw_lookup_by_name (cd, name)
-     CGEN_CPU_DESC cd;
-     const char *name;
+cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name)
 {
   unsigned int i;
   const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
@@ -298,9 +283,7 @@ cgen_hw_lookup_by_name (cd, name)
    Returns NULL if HWNUM is not supported by the currently selected mach.  */
 
 const CGEN_HW_ENTRY *
-cgen_hw_lookup_by_num (cd, hwnum)
-     CGEN_CPU_DESC cd;
-     unsigned int hwnum;
+cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum)
 {
   unsigned int i;
   const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
@@ -320,9 +303,7 @@ cgen_hw_lookup_by_num (cd, hwnum)
    mach/isa.  */
 
 const CGEN_OPERAND *
-cgen_operand_lookup_by_name (cd, name)
-     CGEN_CPU_DESC cd;
-     const char *name;
+cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name)
 {
   unsigned int i;
   const CGEN_OPERAND **op = cd->operand_table.entries;
@@ -341,9 +322,7 @@ cgen_operand_lookup_by_name (cd, name)
    mach/isa.  */
 
 const CGEN_OPERAND *
-cgen_operand_lookup_by_num (cd, opnum)
-     CGEN_CPU_DESC cd;
-     int opnum;
+cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum)
 {
   return cd->operand_table.entries[opnum];
 }
@@ -353,8 +332,7 @@ cgen_operand_lookup_by_num (cd, opnum)
 /* Return number of instructions.  This includes any added at runtime.  */
 
 int
-cgen_insn_count (cd)
-     CGEN_CPU_DESC cd;
+cgen_insn_count (CGEN_CPU_DESC cd)
 {
   int count = cd->insn_table.num_init_entries;
   CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries;
@@ -369,8 +347,7 @@ cgen_insn_count (cd)
    This includes any added at runtime.  */
 
 int
-cgen_macro_insn_count (cd)
-     CGEN_CPU_DESC cd;
+cgen_macro_insn_count (CGEN_CPU_DESC cd)
 {
   int count = cd->macro_insn_table.num_init_entries;
   CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries;
@@ -384,10 +361,7 @@ cgen_macro_insn_count (cd)
 /* Cover function to read and properly byteswap an insn value.  */
 
 CGEN_INSN_INT
-cgen_get_insn_value (cd, buf, length)
-     CGEN_CPU_DESC cd;
-     unsigned char *buf;
-     int length;
+cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
 {
   int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
   int insn_chunk_bitsize = cd->insn_chunk_bitsize;
@@ -423,11 +397,10 @@ cgen_get_insn_value (cd, buf, length)
 /* Cover function to store an insn value properly byteswapped.  */
 
 void
-cgen_put_insn_value (cd, buf, length, value)
-     CGEN_CPU_DESC cd;
-     unsigned char *buf;
-     int length;
-     CGEN_INSN_INT value;
+cgen_put_insn_value (CGEN_CPU_DESC cd,
+		     unsigned char *buf,
+		     int length,
+		     CGEN_INSN_INT value)
 {
   int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
   int insn_chunk_bitsize = cd->insn_chunk_bitsize;
@@ -472,16 +445,14 @@ cgen_put_insn_value (cd, buf, length, value)
 /* ??? Will need to be revisited for VLIW architectures.  */
 
 const CGEN_INSN *
-cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields,
-		  alias_p)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_INSN_INT insn_int_value;
-     /* ??? CGEN_INSN_BYTES would be a nice type name to use here.  */
-     unsigned char *insn_bytes_value;
-     int length;
-     CGEN_FIELDS *fields;
-     int alias_p;
+cgen_lookup_insn (CGEN_CPU_DESC cd,
+		  const CGEN_INSN *insn,
+		  CGEN_INSN_INT insn_int_value,
+		  /* ??? CGEN_INSN_BYTES would be a nice type name to use here.  */
+		  unsigned char *insn_bytes_value,
+		  int length,
+		  CGEN_FIELDS *fields,
+		  int alias_p)
 {
   unsigned char *buf;
   CGEN_INSN_INT base_insn;
@@ -571,11 +542,10 @@ cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields,
    in.  */
 
 void
-cgen_get_insn_operands (cd, insn, fields, indices)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const CGEN_FIELDS *fields;
-     int *indices;
+cgen_get_insn_operands (CGEN_CPU_DESC cd,
+			const CGEN_INSN *insn,
+			const CGEN_FIELDS *fields,
+			int *indices)
 {
   const CGEN_OPINST *opinst;
   int i;
@@ -603,16 +573,14 @@ cgen_get_insn_operands (cd, insn, fields, indices)
    recognized.  */
 
 const CGEN_INSN *
-cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value,
-			       length, indices, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_INSN_INT insn_int_value;
-     /* ??? CGEN_INSN_BYTES would be a nice type name to use here.  */
-     unsigned char *insn_bytes_value;
-     int length;
-     int *indices;
-     CGEN_FIELDS *fields;
+cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd,
+			       const CGEN_INSN *insn,
+			       CGEN_INSN_INT insn_int_value,
+			       /* ??? CGEN_INSN_BYTES would be a nice type name to use here.  */
+			       unsigned char *insn_bytes_value,
+			       int length,
+			       int *indices,
+			       CGEN_FIELDS *fields)
 {
   /* Pass non-zero for ALIAS_P only if INSN != NULL.
      If INSN == NULL, we want a real insn.  */
@@ -627,24 +595,21 @@ cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value,
 
 /* Allow signed overflow of instruction fields.  */
 void
-cgen_set_signed_overflow_ok (cd)
-     CGEN_CPU_DESC cd;
+cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd)
 {
   cd->signed_overflow_ok_p = 1;
 }
 
 /* Generate an error message if a signed field in an instruction overflows.  */
 void
-cgen_clear_signed_overflow_ok (cd)
-     CGEN_CPU_DESC cd;
+cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd)
 {
   cd->signed_overflow_ok_p = 0;
 }
 
 /* Will an error message be generated if a signed field in an instruction overflows ? */
 unsigned int
-cgen_signed_overflow_ok_p (cd)
-     CGEN_CPU_DESC cd;
+cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd)
 {
   return cd->signed_overflow_ok_p;
 }
diff --git a/gnu/usr.bin/binutils/opcodes/cgen.sh b/gnu/usr.bin/binutils/opcodes/cgen.sh
index a9483bdb972..5a340b6e527 100644
--- a/gnu/usr.bin/binutils/opcodes/cgen.sh
+++ b/gnu/usr.bin/binutils/opcodes/cgen.sh
@@ -23,11 +23,19 @@
 # arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch].
 #
 # Usage:
-# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options
+# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \
+#         arch-file opc-file options [extrafiles]
 #
 # ACTION is currently always "opcodes". It exists to be consistent with the 
 # simulator.
-# OPTIONS is comma separated list of options:
+# ARCH is the name of the architecture.
+# It is substituted into @arch@ and @ARCH@ in the generated files.
+# PREFIX is both the generated file prefix and is substituted into
+# @prefix@ in the generated files.
+# ARCH-FILE is the name of the .cpu file (including path).
+# OPC-FILE is the name of the .opc file (including path).
+# OPTIONS is comma separated list of options (???).
+# EXTRAFILES is a space separated list (1 arg still) of extra files to build:
 #	- opinst - arch-opinst.c is being made, causes semantic analysis
 #
 # We store the generated files in the source directory until we decide to
@@ -44,11 +52,13 @@ cgendir=$4
 cgenflags=$5
 arch=$6
 prefix=$7
-options=$8
+archfile=$8
+opcfile=$9
+shift ; options=$9
 
 # List of extra files to build.
 # Values: opinst (only 1 extra file at present)
-extrafiles=$9
+shift ; extrafiles=$9
 
 rootdir=${srcdir}/..
 
@@ -88,7 +98,8 @@ opcodes)
 		${cgenflags} \
 		-f "${options}" \
 		-m all \
-		-a ${arch} \
+		-a ${archfile} \
+	        -OPC ${opcfile} \
 		-H tmp-desc.h1 \
 		-C tmp-desc.c1 \
 		-O tmp-opc.h1 \
diff --git a/gnu/usr.bin/binutils/opcodes/dep-in.sed b/gnu/usr.bin/binutils/opcodes/dep-in.sed
index e373d4ca84e..94da2adc340 100644
--- a/gnu/usr.bin/binutils/opcodes/dep-in.sed
+++ b/gnu/usr.bin/binutils/opcodes/dep-in.sed
@@ -10,6 +10,7 @@ s!@TOPDIR@/include!$(INCDIR)!g
 s!@BFDDIR@!$(BFDDIR)!g
 s!@TOPDIR@/bfd!$(BFDDIR)!g
 s!@SRCDIR@/!!g
+s! \.\./intl/libintl\.h!!g
 
 s/\\\n */ /g
 
diff --git a/gnu/usr.bin/binutils/opcodes/fr30-asm.c b/gnu/usr.bin/binutils/opcodes/fr30-asm.c
index be9c36c947c..f1c18a16bd5 100644
--- a/gnu/usr.bin/binutils/opcodes/fr30-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/fr30-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -356,8 +356,7 @@ fr30_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-fr30_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+fr30_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -480,11 +479,10 @@ fr30_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -622,12 +620,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -657,10 +654,10 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! fr30_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -731,9 +728,7 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-fr30_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+fr30_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/fr30-desc.c b/gnu/usr.bin/binutils/opcodes/fr30-desc.c
index 01d896f28ea..3309d54cf03 100644
--- a/gnu/usr.bin/binutils/opcodes/fr30-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/fr30-desc.c
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
diff --git a/gnu/usr.bin/binutils/opcodes/fr30-desc.h b/gnu/usr.bin/binutils/opcodes/fr30-desc.h
index 6be96d933ab..35d0de70820 100644
--- a/gnu/usr.bin/binutils/opcodes/fr30-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/fr30-desc.h
@@ -240,7 +240,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/gnu/usr.bin/binutils/opcodes/fr30-dis.c b/gnu/usr.bin/binutils/opcodes/fr30-dis.c
index ef7b37a5a24..0b99a4af395 100644
--- a/gnu/usr.bin/binutils/opcodes/fr30-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/fr30-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -343,13 +342,12 @@ fr30_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -369,13 +367,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -399,12 +396,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -418,17 +414,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -460,14 +455,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -491,12 +485,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -601,10 +594,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -643,9 +633,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_fr30 (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_fr30 (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/fr30-ibld.c b/gnu/usr.bin/binutils/opcodes/fr30-ibld.c
index 96374619e6c..b01e483e323 100644
--- a/gnu/usr.bin/binutils/opcodes/fr30-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/fr30-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
diff --git a/gnu/usr.bin/binutils/opcodes/frv-asm.c b/gnu/usr.bin/binutils/opcodes/frv-asm.c
index 538ed2dc8f1..145b56a2a79 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/frv-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -64,6 +64,14 @@ static const char * parse_s12
   PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
 static const char * parse_u12
   PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_even_register
+  PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
+static const char * parse_A0
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_A1
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_A
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *, long));
 
 static const char *
 parse_ulo16 (cd, strp, opindex, valuep)
@@ -102,7 +110,66 @@ parse_ulo16 (cd, strp, opindex, valuep)
 	  ++*strp;
 	  if (errmsg == NULL
 	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	    value >>= 16;
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0)
+	{
+	  *strp += 7;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0)
+	{
+	  *strp += 15;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0)
+	{
+	  *strp += 10;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_GOTOFFLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0)
+	{
+	  *strp += 18;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
 	  *valuep = value;
 	  return errmsg;
 	}
@@ -151,6 +218,65 @@ parse_uslo16 (cd, strp, opindex, valuep)
 	  *valuep = value;
 	  return errmsg;
 	}
+      else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0)
+	{
+	  *strp += 7;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0)
+	{
+	  *strp += 15;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0)
+	{
+	  *strp += 10;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_GOTOFFLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0)
+	{
+	  *strp += 18;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
     }
   return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
 }
@@ -196,6 +322,65 @@ parse_uhi16 (cd, strp, opindex, valuep)
 	  *valuep = value;
 	  return errmsg;
 	}
+      else if (strncasecmp (*strp + 1, "gothi(", 6) == 0)
+	{
+	  *strp += 7;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOTHI,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotfuncdeschi(", 14) == 0)
+	{
+	  *strp += 15;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTHI,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotoffhi(", 9) == 0)
+	{
+	  *strp += 10;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_GOTOFFHI,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofffuncdeschi(", 17) == 0)
+	{
+	  *strp += 18;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTOFFHI,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
     }
   return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
 }
@@ -278,6 +463,53 @@ parse_d12 (cd, strp, opindex, valuep)
           *valuep = value;
           return errmsg;
         }
+      else if (strncasecmp (*strp + 1, "got12(", 6) == 0)
+	{
+	  *strp += 7;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0)
+	{
+	  *strp += 15;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOT12,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0)
+	{
+	  *strp += 10;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_GOTOFF12,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0)
+	{
+	  *strp += 18;
+	  errmsg = cgen_parse_address (cd, strp, opindex,
+				       BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  *valuep = value;
+	  return errmsg;
+	}
     }
   return cgen_parse_signed_integer (cd, strp, opindex, valuep);
 }
@@ -306,6 +538,56 @@ parse_s12 (cd, strp, opindex, valuep)
       *valuep = value;
       return errmsg;
     }
+  else if ((**strp == '#' || **strp == '%')
+	   && strncasecmp (*strp + 1, "got12(", 6) == 0)
+    {
+      *strp += 7;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12,
+				   &result_type, &value);
+      if (**strp != ')')
+	return "missing ')'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else if ((**strp == '#' || **strp == '%')
+	   && strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0)
+    {
+      *strp += 15;
+      errmsg = cgen_parse_address (cd, strp, opindex,
+				   BFD_RELOC_FRV_FUNCDESC_GOT12,
+				   &result_type, &value);
+      if (**strp != ')')
+	return "missing ')'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else if ((**strp == '#' || **strp == '%')
+	   && strncasecmp (*strp + 1, "gotoff12(", 9) == 0)
+    {
+      *strp += 10;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFF12,
+				   &result_type, &value);
+      if (**strp != ')')
+	return "missing ')'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else if ((**strp == '#' || **strp == '%')
+	   && strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0)
+    {
+      *strp += 18;
+      errmsg = cgen_parse_address (cd, strp, opindex,
+				   BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
+				   &result_type, &value);
+      if (**strp != ')')
+	return "missing ')'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
   else
     {
       if (**strp == '#')
@@ -346,6 +628,69 @@ parse_u12 (cd, strp, opindex, valuep)
     }
 }
 
+static const char *
+parse_A (cd, strp, opindex, valuep, A)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+     long A;
+{
+  const char *errmsg;
+ 
+  if (**strp == '#')
+    ++*strp;
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+  if (errmsg)
+    return errmsg;
+
+  if (*valuep != A)
+    return "Value of A operand must be 0 or 1";
+
+  return NULL;
+}
+
+static const char *
+parse_A0 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  return parse_A (cd, strp, opindex, valuep, 0);
+}
+
+static const char *
+parse_A1 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  return parse_A (cd, strp, opindex, valuep, 1);
+}
+
+static const char *
+parse_even_register (cd, strP, tableP, valueP)
+     CGEN_CPU_DESC  cd;
+     const char **  strP;
+     CGEN_KEYWORD * tableP;
+     long *         valueP;
+{
+  const char * errmsg;
+  const char * saved_star_strP = * strP;
+
+  errmsg = cgen_parse_keyword (cd, strP, tableP, valueP);
+
+  if (errmsg == NULL && ((* valueP) & 1))
+    {
+      errmsg = _("register number must be even");
+      * strP = saved_star_strP;
+    }
+
+  return errmsg;
+}
 /* -- */
 
 const char * frv_cgen_parse_operand
@@ -377,8 +722,11 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
-      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A);
+    case FRV_OPERAND_A0 :
+      errmsg = parse_A0 (cd, strp, FRV_OPERAND_A0, &fields->f_A);
+      break;
+    case FRV_OPERAND_A1 :
+      errmsg = parse_A1 (cd, strp, FRV_OPERAND_A1, &fields->f_A);
       break;
     case FRV_OPERAND_ACC40SI :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si);
@@ -402,7 +750,7 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CCi);
       break;
     case FRV_OPERAND_CPRDOUBLEK :
-      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk);
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk);
       break;
     case FRV_OPERAND_CPRI :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRi);
@@ -441,13 +789,13 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCk);
       break;
     case FRV_OPERAND_FRDOUBLEI :
-      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
       break;
     case FRV_OPERAND_FRDOUBLEJ :
-      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
       break;
     case FRV_OPERAND_FRDOUBLEK :
-      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
       break;
     case FRV_OPERAND_FRI :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
@@ -455,12 +803,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
     case FRV_OPERAND_FRINTI :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
+      break;
     case FRV_OPERAND_FRINTJ :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
+      break;
     case FRV_OPERAND_FRINTK :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
     case FRV_OPERAND_FRJ :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
       break;
@@ -474,7 +831,7 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
       break;
     case FRV_OPERAND_GRDOUBLEK :
-      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
+      errmsg = parse_even_register (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
       break;
     case FRV_OPERAND_GRI :
       errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRi);
@@ -628,8 +985,7 @@ frv_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-frv_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+frv_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -752,11 +1108,10 @@ frv_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -894,12 +1249,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-frv_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -929,10 +1283,10 @@ frv_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! frv_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -1003,9 +1357,7 @@ frv_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-frv_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+frv_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/frv-desc.c b/gnu/usr.bin/binutils/opcodes/frv-desc.c
index 5fac77a0dd7..35659c7b420 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/frv-desc.c
@@ -47,6 +47,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
 {
   { "base", MACH_BASE },
   { "frv", MACH_FRV },
+  { "fr550", MACH_FR550 },
   { "fr500", MACH_FR500 },
   { "fr400", MACH_FR400 },
   { "tomcat", MACH_TOMCAT },
@@ -68,15 +69,28 @@ static const CGEN_ATTR_ENTRY UNIT_attr[] =
   { "I0", UNIT_I0 },
   { "I1", UNIT_I1 },
   { "I01", UNIT_I01 },
+  { "I2", UNIT_I2 },
+  { "I3", UNIT_I3 },
+  { "IALL", UNIT_IALL },
   { "FM0", UNIT_FM0 },
   { "FM1", UNIT_FM1 },
   { "FM01", UNIT_FM01 },
+  { "FM2", UNIT_FM2 },
+  { "FM3", UNIT_FM3 },
+  { "FMALL", UNIT_FMALL },
+  { "FMLOW", UNIT_FMLOW },
   { "B0", UNIT_B0 },
   { "B1", UNIT_B1 },
   { "B01", UNIT_B01 },
   { "C", UNIT_C },
   { "MULT_DIV", UNIT_MULT_DIV },
+  { "IACC", UNIT_IACC },
   { "LOAD", UNIT_LOAD },
+  { "STORE", UNIT_STORE },
+  { "SCAN", UNIT_SCAN },
+  { "DCPL", UNIT_DCPL },
+  { "MDUALACC", UNIT_MDUALACC },
+  { "MCLRACC_1", UNIT_MCLRACC_1 },
   { "NUM_UNITS", UNIT_NUM_UNITS },
   { 0, 0 }
 };
@@ -138,6 +152,37 @@ static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
   { 0, 0 }
 };
 
+static const CGEN_ATTR_ENTRY FR550_MAJOR_attr[] =
+{
+  { "NONE", FR550_MAJOR_NONE },
+  { "I_1", FR550_MAJOR_I_1 },
+  { "I_2", FR550_MAJOR_I_2 },
+  { "I_3", FR550_MAJOR_I_3 },
+  { "I_4", FR550_MAJOR_I_4 },
+  { "I_5", FR550_MAJOR_I_5 },
+  { "I_6", FR550_MAJOR_I_6 },
+  { "I_7", FR550_MAJOR_I_7 },
+  { "I_8", FR550_MAJOR_I_8 },
+  { "B_1", FR550_MAJOR_B_1 },
+  { "B_2", FR550_MAJOR_B_2 },
+  { "B_3", FR550_MAJOR_B_3 },
+  { "B_4", FR550_MAJOR_B_4 },
+  { "B_5", FR550_MAJOR_B_5 },
+  { "B_6", FR550_MAJOR_B_6 },
+  { "C_1", FR550_MAJOR_C_1 },
+  { "C_2", FR550_MAJOR_C_2 },
+  { "F_1", FR550_MAJOR_F_1 },
+  { "F_2", FR550_MAJOR_F_2 },
+  { "F_3", FR550_MAJOR_F_3 },
+  { "F_4", FR550_MAJOR_F_4 },
+  { "M_1", FR550_MAJOR_M_1 },
+  { "M_2", FR550_MAJOR_M_2 },
+  { "M_3", FR550_MAJOR_M_3 },
+  { "M_4", FR550_MAJOR_M_4 },
+  { "M_5", FR550_MAJOR_M_5 },
+  { 0, 0 }
+};
+
 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
 {
   { "MACH", & MACH_attr[0], & MACH_attr[0] },
@@ -181,6 +226,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
+  { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] },
   { "ALIAS", &bool_attr[0], &bool_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
@@ -188,7 +234,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
@@ -210,6 +256,7 @@ static const CGEN_ISA frv_cgen_isa_table[] = {
 
 static const CGEN_MACH frv_cgen_mach_table[] = {
   { "frv", "frv", MACH_FRV, 0 },
+  { "fr550", "fr550", MACH_FR550, 0 },
   { "fr500", "fr500", MACH_FR500, 0 },
   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
   { "fr400", "fr400", MACH_FR400, 0 },
@@ -519,6 +566,8 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
   { "cccr", 263, {0, {0}}, 0, 0 },
   { "lr", 272, {0, {0}}, 0, 0 },
   { "lcr", 273, {0, {0}}, 0, 0 },
+  { "iacc0h", 280, {0, {0}}, 0, 0 },
+  { "iacc0l", 281, {0, {0}}, 0, 0 },
   { "isr", 288, {0, {0}}, 0, 0 },
   { "neear0", 352, {0, {0}}, 0, 0 },
   { "neear1", 353, {0, {0}}, 0, 0 },
@@ -1456,7 +1505,7 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 CGEN_KEYWORD frv_cgen_opval_spr_names =
 {
   & frv_cgen_opval_spr_names_entries[0],
-  1005,
+  1007,
   0, 0, 0, 0, ""
 };
 
@@ -1610,6 +1659,18 @@ CGEN_KEYWORD frv_cgen_opval_acc_names =
   0, 0, 0, 0, ""
 };
 
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] =
+{
+  { "iacc0", 0, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_iacc0_names =
+{
+  & frv_cgen_opval_iacc0_names_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
 {
   { "icc0", 0, {0, {0}}, 0, 0 },
@@ -1756,6 +1817,7 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] =
   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400) } } },
   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
@@ -2157,10 +2219,6 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
-/* A: all accumulator indicator */
-  { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
-    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* ae: all entries indicator */
   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, 
@@ -2173,6 +2231,26 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, 
     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+/* A0: A==0 operand of mclracc */
+  { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* A1: A==1 operand of mclracc */
+  { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRintieven: (even) source register 1 */
+  { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRintjeven: (even) source register 2 */
+  { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRintkeven: (even) target register */
+  { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
+    { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
+    { 0, { (1<<MACH_BASE) } }  },
 /* d12: 12 bit signed immediate */
   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, 
@@ -2260,3692 +2338,3732 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
 /* add$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_ADD, "add", "add", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sub$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SUB, "sub", "sub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* and$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_AND, "and", "and", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* or$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_OR, "or", "or", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xor$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_XOR, "xor", "xor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* not$pack $GRj,$GRk */
   {
     FRV_INSN_NOT, "not", "not", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nsdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* udiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_UDIV, "udiv", "udiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nudiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* smul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_SMUL, "smul", "smul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_UMUL, "umul", "umul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+  },
+/* smu$pack $GRi,$GRj */
+  {
+    FRV_INSN_SMU, "smu", "smu", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* smass$pack $GRi,$GRj */
+  {
+    FRV_INSN_SMASS, "smass", "smass", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* smsss$pack $GRi,$GRj */
+  {
+    FRV_INSN_SMSSS, "smsss", "smsss", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* sll$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SLL, "sll", "sll", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srl$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRL, "srl", "srl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sra$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRA, "sra", "sra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+  },
+/* slass$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SLASS, "slass", "slass", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* scutss$pack $GRj,$GRk */
+  {
+    FRV_INSN_SCUTSS, "scutss", "scutss", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* scan$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SCAN, "scan", "scan", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADD, "cadd", "cadd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUB, "csub", "csub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CAND, "cand", "cand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_COR, "cor", "cor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXOR, "cxor", "cxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cnot$pack $GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CNOT, "cnot", "cnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMUL, "csmul", "csmul", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLL, "csll", "csll", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRL, "csrl", "csrl", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRA, "csra", "csra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSCAN, "cscan", "cscan", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDCC, "addcc", "addcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBCC, "subcc", "subcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDCC, "andcc", "andcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORCC, "orcc", "orcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRACC, "sracc", "sracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CANDCC, "candcc", "candcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CORCC, "corcc", "corcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRACC, "csracc", "csracc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDX, "addx", "addx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBX, "subx", "subx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+  },
+/* addss$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_ADDSS, "addss", "addss", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+  },
+/* subss$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SUBSS, "subss", "subss", 32,
+    { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
   },
 /* addi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ADDI, "addi", "addi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SUBI, "subi", "subi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ANDI, "andi", "andi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* ori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ORI, "ori", "ori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_XORI, "xori", "xori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nsdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* udivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_UDIVI, "udivi", "udivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* nudivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* smuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_SMULI, "smuli", "smuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_UMULI, "umuli", "umuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* slli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SLLI, "slli", "slli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRLI, "srli", "srli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srai$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRAI, "srai", "srai", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* scani$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SCANI, "scani", "scani", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDICC, "addicc", "addicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBICC, "subicc", "subicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDICC, "andicc", "andicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORICC, "oricc", "oricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
   },
 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXI, "addxi", "addxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXI, "subxi", "subxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
-    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
   },
 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
-    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
   },
 /* setlo$pack $ulo16,$GRklo */
   {
     FRV_INSN_SETLO, "setlo", "setlo", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* sethi$pack $uhi16,$GRkhi */
   {
     FRV_INSN_SETHI, "sethi", "sethi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* setlos$pack $slo16,$GRk */
   {
     FRV_INSN_SETLOS, "setlos", "setlos", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
   },
 /* ldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUB, "ldub", "ldub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUH, "lduh", "lduh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ld$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LD, "ld", "ld", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDF, "ldf", "ldf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDC, "ldc", "ldc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUB, "nldub", "nldub", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nld$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLD, "nld", "nld", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDF, "nldf", "nldf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldd$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDD, "ldd", "ldd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDF, "lddf", "lddf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDC, "lddc", "lddc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldd$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDD, "nldd", "nldd", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQ, "ldq", "ldq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQ, "nldq", "nldq", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDU, "ldu", "ldu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDU, "nldu", "nldu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDDU, "lddu", "lddu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDI, "ldi", "ldi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDI, "nldi", "nldi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_LDDI, "lddi", "lddi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* lddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* ldqi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* ldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
-  },
-/* nldqi$pack @($GRi,$d12),$GRk */
-  {
-    FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* nldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* stb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STB, "stb", "stb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sth$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STH, "sth", "sth", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* st$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_ST, "st", "st", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBF, "stbf", "stbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHF, "sthf", "sthf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STF, "stf", "stf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STC, "stc", "stc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* rstb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTB, "rstb", "rstb", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rsth$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTH, "rsth", "rsth", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rst$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_RST, "rst", "rst", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rstbf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rsthf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rstf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTF, "rstf", "rstf", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
-/* std$pack $GRk,@($GRi,$GRj) */
+/* std$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STD, "std", "std", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdf$pack $FRk,@($GRi,$GRj) */
+/* stdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDF, "stdf", "stdf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdc$pack $CPRk,@($GRi,$GRj) */
+/* stdc$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDC, "stdc", "stdc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* rstd$pack $GRk,@($GRi,$GRj) */
+/* rstd$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_RSTD, "rstd", "rstd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
-/* rstdf$pack $FRk,@($GRi,$GRj) */
+/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stq$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQ, "stq", "stq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQF, "stqf", "stqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQC, "stqc", "stqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rstq$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTQ, "rstq", "rstq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* rstqf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stbu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STBU, "stbu", "stbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STHU, "sthu", "sthu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STU, "stu", "stu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STFU, "stfu", "stfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STCU, "stcu", "stcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdu$pack $GRk,@($GRi,$GRj) */
+/* stdu$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDU, "stdu", "stdu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdfu$pack $FRk,@($GRi,$GRj) */
+/* stdfu$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdcu$pack $CPRk,@($GRi,$GRj) */
+/* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stqu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQU, "stqu", "stqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUB, "cldub", "cldub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUH, "clduh", "clduh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLD, "cld", "cld", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDF, "cldf", "cldf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDD, "cldd", "cldd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDF, "clddf", "clddf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQ, "cldq", "cldq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDU, "cldu", "cldu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDU, "clddu", "clddu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
   },
 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
   },
 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTB, "cstb", "cstb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTH, "csth", "csth", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CST, "cst", "cst", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHF, "csthf", "csthf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTF, "cstf", "cstf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+/* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTD, "cstd", "cstd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTQ, "cstq", "cstq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHU, "csthu", "csthu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTU, "cstu", "cstu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STBI, "stbi", "stbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STHI, "sthi", "sthi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sti$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STI, "sti", "sti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stbfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* sthfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STFI, "stfi", "stfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdi$pack $GRk,@($GRi,$d12) */
+/* stdi$pack $GRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDI, "stdi", "stdi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
-/* stdfi$pack $FRk,@($GRi,$d12) */
+/* stdfi$pack $FRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
   },
 /* stqi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STQI, "stqi", "stqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* stqfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
   },
 /* swap$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_SWAP, "swap", "swap", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* swapi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_SWAPI, "swapi", "swapi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CSWAP, "cswap", "cswap", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* movgf$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGF, "movgf", "movgf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movfg$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFG, "movfg", "movfg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgfd$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movfgd$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgfq$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
   },
 /* movfgq$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
   },
 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
   },
 /* movgs$pack $GRj,$spr */
   {
     FRV_INSN_MOVGS, "movgs", "movgs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* movsg$pack $spr,$GRj */
   {
     FRV_INSN_MOVSG, "movsg", "movsg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* bra$pack $hint_taken$label16 */
   {
     FRV_INSN_BRA, "bra", "bra", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bno$pack$hint_not_taken */
   {
     FRV_INSN_BNO, "bno", "bno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* beq$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bne$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* ble$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLE, "ble", "ble", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bgt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGT, "bgt", "bgt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* blt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLT, "blt", "blt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bge$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGE, "bge", "bge", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bls$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLS, "bls", "bls", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bhi$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BHI, "bhi", "bhi", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BC, "bc", "bc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bnc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNC, "bnc", "bnc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bn$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BN, "bn", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bp$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BP, "bp", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BV, "bv", "bv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bnv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNV, "bnv", "bnv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbra$pack $hint_taken$label16 */
   {
     FRV_INSN_FBRA, "fbra", "fbra", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbno$pack$hint_not_taken */
   {
     FRV_INSN_FBNO, "fbno", "fbno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbne$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBNE, "fbne", "fbne", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbeq$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fblg$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLG, "fblg", "fblg", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbue$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUE, "fbue", "fbue", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbul$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUL, "fbul", "fbul", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGE, "fbge", "fbge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fblt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLT, "fblt", "fblt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbuge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbug$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUG, "fbug", "fbug", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fble$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLE, "fble", "fble", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbgt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbule$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBULE, "fbule", "fbule", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbu$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBU, "fbu", "fbu", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* fbo$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBO, "fbo", "fbo", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
   },
 /* bctrlr$pack $ccond,$hint */
   {
     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bralr$pack$hint_taken */
   {
     FRV_INSN_BRALR, "bralr", "bralr", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnolr$pack$hint_not_taken */
   {
     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* beqlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* blelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLELR, "blelr", "blelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bgtlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bltlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bgelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* blslr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLSLR, "blslr", "blslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bhilr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BCLR, "bclr", "bclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bplr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BPLR, "bplr", "bplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bnvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbralr$pack$hint_taken */
   {
     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbeqlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbnelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fblglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbuelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbullr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbgelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbltlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbugelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbuglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fblelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbgtlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbulelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbulr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* fbolr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
   },
 /* bcralr$pack $ccond$hint_taken */
   {
     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnolr$pack$hint_not_taken */
   {
     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bceqlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bclelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcltlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcgelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bclslr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bchilr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcplr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbralr$pack $ccond$hint_taken */
   {
     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcblglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbullr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcblelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbulr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* fcbolr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
   },
 /* jmpl$pack @($GRi,$GRj) */
   {
     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* calll$pack @($GRi,$GRj) */
   {
     FRV_INSN_CALLL, "calll", "calll", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
   },
 /* jmpil$pack @($GRi,$s12) */
   {
     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* callil$pack @($GRi,$s12) */
   {
     FRV_INSN_CALLIL, "callil", "callil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
   },
 /* call$pack $label24 */
   {
     FRV_INSN_CALL, "call", "call", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
   },
 /* rett$pack $debug */
   {
     FRV_INSN_RETT, "rett", "rett", 32,
-    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* rei$pack $eir */
   {
     FRV_INSN_REI, "rei", "rei", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
   },
 /* tra$pack $GRi,$GRj */
   {
     FRV_INSN_TRA, "tra", "tra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tno$pack */
   {
     FRV_INSN_TNO, "tno", "tno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* teq$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TEQ, "teq", "teq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tne$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNE, "tne", "tne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tle$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLE, "tle", "tle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tgt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGT, "tgt", "tgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tlt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLT, "tlt", "tlt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tge$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGE, "tge", "tge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tls$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLS, "tls", "tls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* thi$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_THI, "thi", "thi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TC, "tc", "tc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tnc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNC, "tnc", "tnc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tn$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TN, "tn", "tn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tp$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TP, "tp", "tp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TV, "tv", "tv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tnv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNV, "tnv", "tnv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftra$pack $GRi,$GRj */
   {
     FRV_INSN_FTRA, "ftra", "ftra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftno$pack */
   {
     FRV_INSN_FTNO, "ftno", "ftno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftne$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTNE, "ftne", "ftne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* fteq$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTEQ, "fteq", "fteq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftlg$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftue$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUE, "ftue", "ftue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftul$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUL, "ftul", "ftul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGE, "ftge", "ftge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftlt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftuge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftug$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUG, "ftug", "ftug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftle$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLE, "ftle", "ftle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftgt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftule$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTULE, "ftule", "ftule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftu$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTU, "ftu", "ftu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* fto$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTO, "fto", "fto", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tira$pack $GRi,$s12 */
   {
     FRV_INSN_TIRA, "tira", "tira", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tino$pack */
   {
     FRV_INSN_TINO, "tino", "tino", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tieq$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIEQ, "tieq", "tieq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tine$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINE, "tine", "tine", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tile$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILE, "tile", "tile", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tigt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGT, "tigt", "tigt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tilt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILT, "tilt", "tilt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tige$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGE, "tige", "tige", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tils$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILS, "tils", "tils", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tihi$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIHI, "tihi", "tihi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tic$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIC, "tic", "tic", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tinc$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINC, "tinc", "tinc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tin$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIN, "tin", "tin", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tip$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIP, "tip", "tip", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tiv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIV, "tiv", "tiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* tinv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINV, "tinv", "tinv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftira$pack $GRi,$s12 */
   {
     FRV_INSN_FTIRA, "ftira", "ftira", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftino$pack */
   {
     FRV_INSN_FTINO, "ftino", "ftino", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftine$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTINE, "ftine", "ftine", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftieq$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftilg$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiue$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiul$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftige$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGE, "ftige", "ftige", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftilt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiug$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftile$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILE, "ftile", "ftile", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftigt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiule$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftiu$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* ftio$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIO, "ftio", "ftio", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* break$pack */
   {
     FRV_INSN_BREAK, "break", "break", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* mtrap$pack */
   {
     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
   },
 /* andcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDCR, "andcr", "andcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* orcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORCR, "orcr", "orcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* xorcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* nandcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* norcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORCR, "norcr", "norcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* andncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* orncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORNCR, "orncr", "orncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* nandncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* norncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORNCR, "norncr", "norncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* notcr$pack $CRj,$CRk */
   {
     FRV_INSN_NOTCR, "notcr", "notcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
   },
 /* ckra$pack $CRj_int */
   {
     FRV_INSN_CKRA, "ckra", "ckra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckno$pack $CRj_int */
   {
     FRV_INSN_CKNO, "ckno", "ckno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckeq$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckne$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNE, "ckne", "ckne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckle$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLE, "ckle", "ckle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckgt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cklt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLT, "cklt", "cklt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckge$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGE, "ckge", "ckge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckls$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLS, "ckls", "ckls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckhi$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKC, "ckc", "ckc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cknc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNC, "cknc", "cknc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckn$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKN, "ckn", "ckn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckp$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKP, "ckp", "ckp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ckv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKV, "ckv", "ckv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cknv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNV, "cknv", "cknv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckra$pack $CRj_float */
   {
     FRV_INSN_FCKRA, "fckra", "fckra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckno$pack $CRj_float */
   {
     FRV_INSN_FCKNO, "fckno", "fckno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckne$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKNE, "fckne", "fckne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckeq$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcklg$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckue$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUE, "fckue", "fckue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckul$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUL, "fckul", "fckul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGE, "fckge", "fckge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcklt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckuge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckug$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUG, "fckug", "fckug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckle$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLE, "fckle", "fckle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckgt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fckule$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKULE, "fckule", "fckule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcku$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKU, "fcku", "fcku", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* fcko$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKO, "fcko", "fcko", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckra$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKRA, "cckra", "cckra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckno$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNO, "cckno", "cckno", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNE, "cckne", "cckne", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLE, "cckle", "cckle", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGE, "cckge", "cckge", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLS, "cckls", "cckls", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKC, "cckc", "cckc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKN, "cckn", "cckn", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKP, "cckp", "cckp", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKV, "cckv", "cckv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckra$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckno$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
   },
 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
   },
 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
   },
 /* ici$pack @($GRi,$GRj) */
   {
     FRV_INSN_ICI, "ici", "ici", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dci$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCI, "dci", "dci", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* icei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_ICEI, "icei", "icei", 32,
-    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* dcei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEI, "dcei", "dcei", 32,
-    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* dcf$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCF, "dcf", "dcf", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcef$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEF, "dcef", "dcef", 32,
-    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
   },
 /* witlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WITLB, "witlb", "witlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* wdtlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* itlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* dtlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* icpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_ICPL, "icpl", "icpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
   },
 /* icul$pack $GRi */
   {
     FRV_INSN_ICUL, "icul", "icul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* dcul$pack $GRi */
   {
     FRV_INSN_DCUL, "dcul", "dcul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* bar$pack */
   {
     FRV_INSN_BAR, "bar", "bar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* membar$pack */
   {
     FRV_INSN_MEMBAR, "membar", "membar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
   },
 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP1, "cop1", "cop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP2, "cop2", "cop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
   },
 /* clrgr$pack $GRk */
   {
     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrfr$pack $FRk */
   {
     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrga$pack */
   {
     FRV_INSN_CLRGA, "clrga", "clrga", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* clrfa$pack */
   {
     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitgr$pack $GRk */
   {
     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitfr$pack $FRk */
   {
     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitga$pack */
   {
     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* commitfa$pack */
   {
     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
   },
 /* fitos$pack $FRintj,$FRk */
   {
     FRV_INSN_FITOS, "fitos", "fitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fitod$pack $FRintj,$FRdoublek */
   {
     FRV_INSN_FITOD, "fitod", "fitod", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdtoi$pack $FRdoublej,$FRintk */
   {
     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fditos$pack $FRintj,$FRk */
   {
     FRV_INSN_FDITOS, "fditos", "fditos", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* nfditos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* nfdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* nfitos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* nfstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fmovd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fnegd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fabss$pack $FRj,$FRk */
   {
     FRV_INSN_FABSS, "fabss", "fabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fabsd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* fdabss$pack $FRj,$FRk */
   {
     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
   },
 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
   },
 /* fsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* nfdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* fsqrtd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* nfsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FADDS, "fadds", "fadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* fdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FADDD, "faddd", "faddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
   },
 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
   },
 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* nfadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* nfsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* nfmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
   },
 /* nfdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
   },
 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
   {
     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
   },
 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
   {
     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
   },
 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAS, "fmas", "fmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSS, "fmss", "fmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fmad$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAD, "fmad", "fmad", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* fmsd$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
   },
 /* nfmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* nfmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
   },
 /* fdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* fddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
   },
 /* fdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* fdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
   },
 /* nfddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
   },
 /* nfdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
   },
 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
   },
 /* mhsetlos$pack $u12,$FRklo */
   {
     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsethis$pack $u12,$FRkhi */
   {
     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhdsets$pack $u12,$FRintk */
   {
     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsetloh$pack $s5,$FRklo */
   {
     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhsethih$pack $s5,$FRkhi */
   {
     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mhdseth$pack $s5,$FRintk */
   {
     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
   },
 /* mand$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAND, "mand", "mand", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MOR, "mor", "mor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mxor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MXOR, "mxor", "mxor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMAND, "cmand", "cmand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOR, "cmor", "cmor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mnot$pack $FRintj,$FRintk */
   {
     FRV_INSN_MNOT, "mnot", "mnot", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mrotli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mrotri$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwcut$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwcuti$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUT, "mcut", "mcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcuti$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mdcutssi$pack $ACC40Si,$s6,$FRintk */
+/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
   {
     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* maveh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAVEH, "maveh", "maveh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msllhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* msrlhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* msrahi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mdrotli$pack $FRinti,$u6,$FRintk */
+/* mdrotli$pack $FRintieven,$s6,$FRintkeven */
   {
     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* mcplhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* mcpli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
   },
 /* msaths$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHS, "msaths", "msaths", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* mqsaths$pack $FRinti,$FRintj,$FRintk */
+/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
   },
 /* msathu$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHU, "msathu", "msathu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* mabshs$pack $FRintj,$FRintk */
   {
     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
   },
 /* maddhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* maddhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msubhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* msubhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* mqaddhss$pack $FRinti,$FRintj,$FRintk */
+/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* mqaddhus$pack $FRinti,$FRintj,$FRintk */
+/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* mqsubhss$pack $FRinti,$FRintj,$FRintk */
+/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* mqsubhus$pack $FRinti,$FRintj,$FRintk */
+/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
-/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
   },
 /* maddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* msubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* masaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
+/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
   {
     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
+/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
-/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
-/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
-    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+    { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
   },
 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
-/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
   },
 /* mexpdhw$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mexpdhd$pack $FRinti,$u6,$FRintk */
+/* mexpdhd$pack $FRinti,$u6,$FRintkeven */
   {
     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
+/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mpackh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mdpackh$pack $FRinti,$FRintj,$FRintk */
+/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
   },
-/* munpackh$pack $FRinti,$FRintk */
+/* munpackh$pack $FRinti,$FRintkeven */
   {
     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mdunpackh$pack $FRinti,$FRintk */
+/* mdunpackh$pack $FRintieven,$FRintk */
   {
     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
   },
-/* mbtoh$pack $FRintj,$FRintk */
+/* mbtoh$pack $FRintj,$FRintkeven */
   {
     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
+/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* mhtob$pack $FRintj,$FRintk */
+/* mhtob$pack $FRintjeven,$FRintk */
   {
     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
-/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
+/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mbtohe$pack $FRintj,$FRintk */
   {
     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
   },
 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+  },
+/* mnop$pack */
+  {
+    FRV_INSN_MNOP, "mnop", "mnop", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
+  },
+/* mclracc$pack $ACC40Sk,$A0 */
+  {
+    FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
-/* mclracc$pack $ACC40Sk,$A */
+/* mclracc$pack $ACC40Sk,$A1 */
   {
-    FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
+    FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
   },
 /* mrdacc$pack $ACC40Si,$FRintk */
   {
     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mrdaccg$pack $ACCGi,$FRintk */
   {
     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
   },
 /* mwtacc$pack $FRinti,$ACC40Sk */
   {
     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
 /* mwtaccg$pack $FRinti,$ACCGk */
   {
     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
   },
 /* mcop1$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
   },
 /* mcop2$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
   },
 /* fnop$pack */
   {
     FRV_INSN_FNOP, "fnop", "fnop", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
   },
 };
 
diff --git a/gnu/usr.bin/binutils/opcodes/frv-desc.h b/gnu/usr.bin/binutils/opcodes/frv-desc.h
index 53cad79079c..f46c3f957c1 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/frv-desc.h
@@ -233,240 +233,240 @@ typedef enum spr_names {
  , H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74
  , H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78
  , H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272
- , H_SPR_LCR = 273, H_SPR_ISR = 288, H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353
- , H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355, H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357
- , H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359, H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361
- , H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363, H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365
- , H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367, H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369
- , H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371, H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373
- , H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375, H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377
- , H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379, H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381
- , H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383, H_SPR_NESR0 = 384, H_SPR_NESR1 = 385
- , H_SPR_NESR2 = 386, H_SPR_NESR3 = 387, H_SPR_NESR4 = 388, H_SPR_NESR5 = 389
- , H_SPR_NESR6 = 390, H_SPR_NESR7 = 391, H_SPR_NESR8 = 392, H_SPR_NESR9 = 393
- , H_SPR_NESR10 = 394, H_SPR_NESR11 = 395, H_SPR_NESR12 = 396, H_SPR_NESR13 = 397
- , H_SPR_NESR14 = 398, H_SPR_NESR15 = 399, H_SPR_NESR16 = 400, H_SPR_NESR17 = 401
- , H_SPR_NESR18 = 402, H_SPR_NESR19 = 403, H_SPR_NESR20 = 404, H_SPR_NESR21 = 405
- , H_SPR_NESR22 = 406, H_SPR_NESR23 = 407, H_SPR_NESR24 = 408, H_SPR_NESR25 = 409
- , H_SPR_NESR26 = 410, H_SPR_NESR27 = 411, H_SPR_NESR28 = 412, H_SPR_NESR29 = 413
- , H_SPR_NESR30 = 414, H_SPR_NESR31 = 415, H_SPR_NECR = 416, H_SPR_GNER0 = 432
- , H_SPR_GNER1 = 433, H_SPR_FNER0 = 434, H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512
- , H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514, H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516
- , H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518, H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520
- , H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522, H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524
- , H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526, H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528
- , H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530, H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532
- , H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534, H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536
- , H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538, H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540
- , H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542, H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544
- , H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546, H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548
- , H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550, H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552
- , H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554, H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556
- , H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558, H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560
- , H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562, H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564
- , H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566, H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568
- , H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570, H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572
- , H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574, H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576
- , H_SPR_ESR1 = 577, H_SPR_ESR2 = 578, H_SPR_ESR3 = 579, H_SPR_ESR4 = 580
- , H_SPR_ESR5 = 581, H_SPR_ESR6 = 582, H_SPR_ESR7 = 583, H_SPR_ESR8 = 584
- , H_SPR_ESR9 = 585, H_SPR_ESR10 = 586, H_SPR_ESR11 = 587, H_SPR_ESR12 = 588
- , H_SPR_ESR13 = 589, H_SPR_ESR14 = 590, H_SPR_ESR15 = 591, H_SPR_ESR16 = 592
- , H_SPR_ESR17 = 593, H_SPR_ESR18 = 594, H_SPR_ESR19 = 595, H_SPR_ESR20 = 596
- , H_SPR_ESR21 = 597, H_SPR_ESR22 = 598, H_SPR_ESR23 = 599, H_SPR_ESR24 = 600
- , H_SPR_ESR25 = 601, H_SPR_ESR26 = 602, H_SPR_ESR27 = 603, H_SPR_ESR28 = 604
- , H_SPR_ESR29 = 605, H_SPR_ESR30 = 606, H_SPR_ESR31 = 607, H_SPR_ESR32 = 608
- , H_SPR_ESR33 = 609, H_SPR_ESR34 = 610, H_SPR_ESR35 = 611, H_SPR_ESR36 = 612
- , H_SPR_ESR37 = 613, H_SPR_ESR38 = 614, H_SPR_ESR39 = 615, H_SPR_ESR40 = 616
- , H_SPR_ESR41 = 617, H_SPR_ESR42 = 618, H_SPR_ESR43 = 619, H_SPR_ESR44 = 620
- , H_SPR_ESR45 = 621, H_SPR_ESR46 = 622, H_SPR_ESR47 = 623, H_SPR_ESR48 = 624
- , H_SPR_ESR49 = 625, H_SPR_ESR50 = 626, H_SPR_ESR51 = 627, H_SPR_ESR52 = 628
- , H_SPR_ESR53 = 629, H_SPR_ESR54 = 630, H_SPR_ESR55 = 631, H_SPR_ESR56 = 632
- , H_SPR_ESR57 = 633, H_SPR_ESR58 = 634, H_SPR_ESR59 = 635, H_SPR_ESR60 = 636
- , H_SPR_ESR61 = 637, H_SPR_ESR62 = 638, H_SPR_ESR63 = 639, H_SPR_EIR0 = 640
- , H_SPR_EIR1 = 641, H_SPR_EIR2 = 642, H_SPR_EIR3 = 643, H_SPR_EIR4 = 644
- , H_SPR_EIR5 = 645, H_SPR_EIR6 = 646, H_SPR_EIR7 = 647, H_SPR_EIR8 = 648
- , H_SPR_EIR9 = 649, H_SPR_EIR10 = 650, H_SPR_EIR11 = 651, H_SPR_EIR12 = 652
- , H_SPR_EIR13 = 653, H_SPR_EIR14 = 654, H_SPR_EIR15 = 655, H_SPR_EIR16 = 656
- , H_SPR_EIR17 = 657, H_SPR_EIR18 = 658, H_SPR_EIR19 = 659, H_SPR_EIR20 = 660
- , H_SPR_EIR21 = 661, H_SPR_EIR22 = 662, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664
- , H_SPR_EIR25 = 665, H_SPR_EIR26 = 666, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668
- , H_SPR_EIR29 = 669, H_SPR_EIR30 = 670, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672
- , H_SPR_ESFR1 = 673, H_SPR_SR0 = 768, H_SPR_SR1 = 769, H_SPR_SR2 = 770
- , H_SPR_SR3 = 771, H_SPR_FSR0 = 1024, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026
- , H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030
- , H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034
- , H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036, H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038
- , H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040, H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042
- , H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044, H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046
- , H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048, H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050
- , H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052, H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054
- , H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056, H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058
- , H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060, H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062
- , H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064, H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066
- , H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068, H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070
- , H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072, H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074
- , H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076, H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078
- , H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080, H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082
- , H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084, H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086
- , H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088, H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092
- , H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096, H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100
- , H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104, H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108
- , H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112, H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116
- , H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120, H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124
- , H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128, H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132
- , H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136, H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140
- , H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144, H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148
- , H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089, H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093
- , H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097, H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101
- , H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105, H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109
- , H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113, H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117
- , H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121, H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125
- , H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129, H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133
- , H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137, H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141
- , H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145, H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149
- , H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272, H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280
- , H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282, H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284
- , H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286, H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288
- , H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290, H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292
- , H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294, H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296
- , H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298, H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300
- , H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302, H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304
- , H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306, H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308
- , H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310, H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312
- , H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314, H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316
- , H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318, H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320
- , H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322, H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324
- , H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326, H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328
- , H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330, H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332
- , H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334, H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336
- , H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338, H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340
- , H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342, H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344
- , H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348, H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352
- , H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356, H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360
- , H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364, H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368
- , H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372, H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376
- , H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380, H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384
- , H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388, H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392
- , H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396, H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400
- , H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404, H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345
- , H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349, H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353
- , H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357, H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361
- , H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365, H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369
- , H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373, H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377
- , H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381, H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385
- , H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389, H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393
- , H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397, H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401
- , H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405, H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536
- , H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538, H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540
- , H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542, H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544
- , H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546, H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548
- , H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550, H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552
- , H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554, H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556
- , H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558, H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560
- , H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562, H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564
- , H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566, H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568
- , H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570, H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572
- , H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574, H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576
- , H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578, H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580
- , H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582, H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584
- , H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586, H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588
- , H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590, H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592
- , H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594, H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596
- , H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598, H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600
- , H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602, H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604
- , H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606, H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608
- , H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610, H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612
- , H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614, H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616
- , H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618, H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620
- , H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622, H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624
- , H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626, H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628
- , H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630, H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632
- , H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634, H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636
- , H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638, H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640
- , H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642, H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644
- , H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646, H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648
- , H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650, H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652
- , H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654, H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656
- , H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658, H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660
- , H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662, H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664
- , H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666, H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668
- , H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670, H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672
- , H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674, H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676
- , H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678, H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680
- , H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682, H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684
- , H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686, H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688
- , H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690, H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692
- , H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694, H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696
- , H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698, H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700
- , H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702, H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704
- , H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706, H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708
- , H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710, H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712
- , H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714, H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716
- , H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718, H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720
- , H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722, H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724
- , H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726, H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728
- , H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730, H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732
- , H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734, H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736
- , H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738, H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740
- , H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742, H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744
- , H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746, H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748
- , H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750, H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752
- , H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754, H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756
- , H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758, H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760
- , H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762, H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764
- , H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766, H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768
- , H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770, H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772
- , H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774, H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776
- , H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778, H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780
- , H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782, H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784
- , H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786, H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788
- , H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790, H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792
- , H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794, H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796
- , H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798, H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800
- , H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802, H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804
- , H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806, H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808
- , H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810, H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812
- , H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814, H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816
- , H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818, H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820
- , H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822, H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824
- , H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826, H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828
- , H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830, H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832
- , H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834, H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836
- , H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838, H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840
- , H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842, H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844
- , H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846, H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848
- , H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850, H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852
- , H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854, H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856
- , H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858, H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860
- , H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862, H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864
- , H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866, H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868
- , H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870, H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872
- , H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874, H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876
- , H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878, H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880
- , H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882, H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884
- , H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886, H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888
- , H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890, H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892
- , H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894, H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896
- , H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898, H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900
- , H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902, H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904
- , H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906, H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908
- , H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912
- , H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916
- , H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920
- , H_SPR_STBAR = 1921, H_SPR_MMCR = 1922, H_SPR_DCR = 2048, H_SPR_BRR = 2049
- , H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054
- , H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058
- , H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062
- , H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066
- , H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070
- , H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074
- , H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078
- , H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082
- , H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086
- , H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090
- , H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093, H_SPR_CPSR = 2094
- , H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099
- , H_SPR_IHSR8 = 3848
+ , H_SPR_LCR = 273, H_SPR_IACC0H = 280, H_SPR_IACC0L = 281, H_SPR_ISR = 288
+ , H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353, H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355
+ , H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357, H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359
+ , H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361, H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363
+ , H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365, H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367
+ , H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369, H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371
+ , H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373, H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375
+ , H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377, H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379
+ , H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381, H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383
+ , H_SPR_NESR0 = 384, H_SPR_NESR1 = 385, H_SPR_NESR2 = 386, H_SPR_NESR3 = 387
+ , H_SPR_NESR4 = 388, H_SPR_NESR5 = 389, H_SPR_NESR6 = 390, H_SPR_NESR7 = 391
+ , H_SPR_NESR8 = 392, H_SPR_NESR9 = 393, H_SPR_NESR10 = 394, H_SPR_NESR11 = 395
+ , H_SPR_NESR12 = 396, H_SPR_NESR13 = 397, H_SPR_NESR14 = 398, H_SPR_NESR15 = 399
+ , H_SPR_NESR16 = 400, H_SPR_NESR17 = 401, H_SPR_NESR18 = 402, H_SPR_NESR19 = 403
+ , H_SPR_NESR20 = 404, H_SPR_NESR21 = 405, H_SPR_NESR22 = 406, H_SPR_NESR23 = 407
+ , H_SPR_NESR24 = 408, H_SPR_NESR25 = 409, H_SPR_NESR26 = 410, H_SPR_NESR27 = 411
+ , H_SPR_NESR28 = 412, H_SPR_NESR29 = 413, H_SPR_NESR30 = 414, H_SPR_NESR31 = 415
+ , H_SPR_NECR = 416, H_SPR_GNER0 = 432, H_SPR_GNER1 = 433, H_SPR_FNER0 = 434
+ , H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512, H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514
+ , H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516, H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518
+ , H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520, H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522
+ , H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524, H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526
+ , H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528, H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530
+ , H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532, H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534
+ , H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536, H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538
+ , H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540, H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542
+ , H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544, H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546
+ , H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548, H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550
+ , H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552, H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554
+ , H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556, H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558
+ , H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560, H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562
+ , H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564, H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566
+ , H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568, H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570
+ , H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572, H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574
+ , H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576, H_SPR_ESR1 = 577, H_SPR_ESR2 = 578
+ , H_SPR_ESR3 = 579, H_SPR_ESR4 = 580, H_SPR_ESR5 = 581, H_SPR_ESR6 = 582
+ , H_SPR_ESR7 = 583, H_SPR_ESR8 = 584, H_SPR_ESR9 = 585, H_SPR_ESR10 = 586
+ , H_SPR_ESR11 = 587, H_SPR_ESR12 = 588, H_SPR_ESR13 = 589, H_SPR_ESR14 = 590
+ , H_SPR_ESR15 = 591, H_SPR_ESR16 = 592, H_SPR_ESR17 = 593, H_SPR_ESR18 = 594
+ , H_SPR_ESR19 = 595, H_SPR_ESR20 = 596, H_SPR_ESR21 = 597, H_SPR_ESR22 = 598
+ , H_SPR_ESR23 = 599, H_SPR_ESR24 = 600, H_SPR_ESR25 = 601, H_SPR_ESR26 = 602
+ , H_SPR_ESR27 = 603, H_SPR_ESR28 = 604, H_SPR_ESR29 = 605, H_SPR_ESR30 = 606
+ , H_SPR_ESR31 = 607, H_SPR_ESR32 = 608, H_SPR_ESR33 = 609, H_SPR_ESR34 = 610
+ , H_SPR_ESR35 = 611, H_SPR_ESR36 = 612, H_SPR_ESR37 = 613, H_SPR_ESR38 = 614
+ , H_SPR_ESR39 = 615, H_SPR_ESR40 = 616, H_SPR_ESR41 = 617, H_SPR_ESR42 = 618
+ , H_SPR_ESR43 = 619, H_SPR_ESR44 = 620, H_SPR_ESR45 = 621, H_SPR_ESR46 = 622
+ , H_SPR_ESR47 = 623, H_SPR_ESR48 = 624, H_SPR_ESR49 = 625, H_SPR_ESR50 = 626
+ , H_SPR_ESR51 = 627, H_SPR_ESR52 = 628, H_SPR_ESR53 = 629, H_SPR_ESR54 = 630
+ , H_SPR_ESR55 = 631, H_SPR_ESR56 = 632, H_SPR_ESR57 = 633, H_SPR_ESR58 = 634
+ , H_SPR_ESR59 = 635, H_SPR_ESR60 = 636, H_SPR_ESR61 = 637, H_SPR_ESR62 = 638
+ , H_SPR_ESR63 = 639, H_SPR_EIR0 = 640, H_SPR_EIR1 = 641, H_SPR_EIR2 = 642
+ , H_SPR_EIR3 = 643, H_SPR_EIR4 = 644, H_SPR_EIR5 = 645, H_SPR_EIR6 = 646
+ , H_SPR_EIR7 = 647, H_SPR_EIR8 = 648, H_SPR_EIR9 = 649, H_SPR_EIR10 = 650
+ , H_SPR_EIR11 = 651, H_SPR_EIR12 = 652, H_SPR_EIR13 = 653, H_SPR_EIR14 = 654
+ , H_SPR_EIR15 = 655, H_SPR_EIR16 = 656, H_SPR_EIR17 = 657, H_SPR_EIR18 = 658
+ , H_SPR_EIR19 = 659, H_SPR_EIR20 = 660, H_SPR_EIR21 = 661, H_SPR_EIR22 = 662
+ , H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666
+ , H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670
+ , H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768
+ , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_FSR0 = 1024
+ , H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028
+ , H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032
+ , H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036
+ , H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038, H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040
+ , H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042, H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044
+ , H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046, H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048
+ , H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050, H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052
+ , H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054, H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056
+ , H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058, H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060
+ , H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062, H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064
+ , H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066, H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068
+ , H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070, H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072
+ , H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074, H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076
+ , H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078, H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080
+ , H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082, H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084
+ , H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086, H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088
+ , H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092, H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096
+ , H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100, H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104
+ , H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108, H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112
+ , H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116, H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120
+ , H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124, H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128
+ , H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132, H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136
+ , H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140, H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144
+ , H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148, H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089
+ , H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093, H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097
+ , H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101, H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105
+ , H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109, H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113
+ , H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117, H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121
+ , H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125, H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129
+ , H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133, H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137
+ , H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141, H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145
+ , H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149, H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272
+ , H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280, H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282
+ , H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284, H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286
+ , H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288, H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290
+ , H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292, H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294
+ , H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296, H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298
+ , H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300, H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302
+ , H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304, H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306
+ , H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308, H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310
+ , H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312, H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314
+ , H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316, H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318
+ , H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320, H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322
+ , H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324, H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326
+ , H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328, H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330
+ , H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332, H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334
+ , H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336, H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338
+ , H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340, H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342
+ , H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344, H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348
+ , H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352, H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356
+ , H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360, H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364
+ , H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368, H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372
+ , H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376, H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380
+ , H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384, H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388
+ , H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392, H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396
+ , H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400, H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404
+ , H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345, H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349
+ , H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353, H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357
+ , H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361, H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365
+ , H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369, H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373
+ , H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377, H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381
+ , H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385, H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389
+ , H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393, H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397
+ , H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401, H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405
+ , H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536, H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538
+ , H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540, H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542
+ , H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544, H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546
+ , H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548, H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550
+ , H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552, H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554
+ , H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556, H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558
+ , H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560, H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562
+ , H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564, H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566
+ , H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568, H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570
+ , H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572, H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574
+ , H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576, H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578
+ , H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580, H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582
+ , H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584, H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586
+ , H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588, H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590
+ , H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592, H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594
+ , H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596, H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598
+ , H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600, H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602
+ , H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604, H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606
+ , H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608, H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610
+ , H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612, H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614
+ , H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616, H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618
+ , H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620, H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622
+ , H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624, H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626
+ , H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628, H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630
+ , H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632, H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634
+ , H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636, H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638
+ , H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640, H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642
+ , H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644, H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646
+ , H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648, H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650
+ , H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652, H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654
+ , H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656, H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658
+ , H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660, H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662
+ , H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664, H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666
+ , H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668, H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670
+ , H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672, H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674
+ , H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676, H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678
+ , H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680, H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682
+ , H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684, H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686
+ , H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688, H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690
+ , H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692, H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694
+ , H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696, H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698
+ , H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700, H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702
+ , H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704, H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706
+ , H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708, H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710
+ , H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712, H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714
+ , H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716, H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718
+ , H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720, H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722
+ , H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724, H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726
+ , H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728, H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730
+ , H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732, H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734
+ , H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736, H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738
+ , H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740, H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742
+ , H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744, H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746
+ , H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748, H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750
+ , H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752, H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754
+ , H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756, H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758
+ , H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760, H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762
+ , H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764, H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766
+ , H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768, H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770
+ , H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772, H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774
+ , H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776, H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778
+ , H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780, H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782
+ , H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784, H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786
+ , H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788, H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790
+ , H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792, H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794
+ , H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796, H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798
+ , H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800, H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802
+ , H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804, H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806
+ , H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808, H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810
+ , H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812, H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814
+ , H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816, H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818
+ , H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820, H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822
+ , H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824, H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826
+ , H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828, H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830
+ , H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832, H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834
+ , H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836, H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838
+ , H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840, H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842
+ , H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844, H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846
+ , H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848, H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850
+ , H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852, H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854
+ , H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856, H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858
+ , H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860, H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862
+ , H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864, H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866
+ , H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868, H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870
+ , H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872, H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874
+ , H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876, H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878
+ , H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880, H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882
+ , H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884, H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886
+ , H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888, H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890
+ , H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892, H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894
+ , H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896, H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898
+ , H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900, H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902
+ , H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904, H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906
+ , H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908, H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910
+ , H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914
+ , H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918
+ , H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922
+ , H_SPR_DCR = 2048, H_SPR_BRR = 2049, H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052
+ , H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056
+ , H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060
+ , H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064
+ , H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068
+ , H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072
+ , H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076
+ , H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080
+ , H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084
+ , H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088
+ , H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092
+ , H_SPR_CPCR = 2093, H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097
+ , H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
 } SPR_NAMES;
 
 /* Enum declaration for .  */
@@ -510,6 +510,11 @@ typedef enum acc_names {
 } ACC_NAMES;
 
 /* Enum declaration for .  */
+typedef enum iacc0_names {
+  H_IACC0_IACC0
+} IACC0_NAMES;
+
+/* Enum declaration for .  */
 typedef enum iccr_names {
   H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3
 } ICCR_NAMES;
@@ -529,8 +534,8 @@ typedef enum cccr_names {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_FRV, MACH_FR500, MACH_FR400
- , MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
+  MACH_BASE, MACH_FRV, MACH_FR550, MACH_FR500
+ , MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -541,9 +546,12 @@ typedef enum isa_attr {
 /* Enum declaration for parallel execution pipeline selection.  */
 typedef enum unit_attr {
   UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01
- , UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0
- , UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV
- , UNIT_LOAD, UNIT_NUM_UNITS
+ , UNIT_I2, UNIT_I3, UNIT_IALL, UNIT_FM0
+ , UNIT_FM1, UNIT_FM01, UNIT_FM2, UNIT_FM3
+ , UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
+ , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC
+ , UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL
+ , UNIT_MDUALACC, UNIT_MCLRACC_1, UNIT_NUM_UNITS
 } UNIT_ATTR;
 
 /* Enum declaration for fr400 major insn categories.  */
@@ -566,6 +574,17 @@ typedef enum fr500_major_attr {
  , FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8
 } FR500_MAJOR_ATTR;
 
+/* Enum declaration for fr550 major insn categories.  */
+typedef enum fr550_major_attr {
+  FR550_MAJOR_NONE, FR550_MAJOR_I_1, FR550_MAJOR_I_2, FR550_MAJOR_I_3
+ , FR550_MAJOR_I_4, FR550_MAJOR_I_5, FR550_MAJOR_I_6, FR550_MAJOR_I_7
+ , FR550_MAJOR_I_8, FR550_MAJOR_B_1, FR550_MAJOR_B_2, FR550_MAJOR_B_3
+ , FR550_MAJOR_B_4, FR550_MAJOR_B_5, FR550_MAJOR_B_6, FR550_MAJOR_C_1
+ , FR550_MAJOR_C_2, FR550_MAJOR_F_1, FR550_MAJOR_F_2, FR550_MAJOR_F_3
+ , FR550_MAJOR_F_4, FR550_MAJOR_M_1, FR550_MAJOR_M_2, FR550_MAJOR_M_3
+ , FR550_MAJOR_M_4, FR550_MAJOR_M_5
+} FR550_MAJOR_ATTR;
+
 /* Number of architecture variants.  */
 #define MAX_ISAS  1
 #define MAX_MACHS ((int) MACH_MAX)
@@ -640,9 +659,9 @@ typedef enum cgen_hw_type {
  , HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO
  , HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3
  , HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG
- , HW_H_ACC40S, HW_H_ACC40U, HW_H_ICCR, HW_H_FCCR
- , HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN, HW_H_HINT_NOT_TAKEN
- , HW_MAX
+ , HW_H_ACC40S, HW_H_ACC40U, HW_H_IACC0, HW_H_ICCR
+ , HW_H_FCCR, HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN
+ , HW_H_HINT_NOT_TAKEN, HW_MAX
 } CGEN_HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
@@ -676,8 +695,9 @@ typedef enum cgen_operand_type {
  , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1
  , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
  , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
- , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE
- , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12
+ , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16
+ , FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN
+ , FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12
  , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
  , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
  , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
@@ -685,7 +705,7 @@ typedef enum cgen_operand_type {
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 77
+#define MAX_OPERANDS 81
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
@@ -695,11 +715,11 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
  , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
- , CGEN_INSN_FR500_MAJOR, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
@@ -735,6 +755,7 @@ extern CGEN_KEYWORD frv_cgen_opval_spr_names;
 extern CGEN_KEYWORD frv_cgen_opval_accg_names;
 extern CGEN_KEYWORD frv_cgen_opval_acc_names;
 extern CGEN_KEYWORD frv_cgen_opval_acc_names;
+extern CGEN_KEYWORD frv_cgen_opval_iacc0_names;
 extern CGEN_KEYWORD frv_cgen_opval_iccr_names;
 extern CGEN_KEYWORD frv_cgen_opval_fccr_names;
 extern CGEN_KEYWORD frv_cgen_opval_cccr_names;
@@ -742,6 +763,7 @@ extern CGEN_KEYWORD frv_cgen_opval_h_pack;
 extern CGEN_KEYWORD frv_cgen_opval_h_hint_taken;
 extern CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken;
 
+extern const CGEN_HW_ENTRY frv_cgen_hw_table[];
 
 
 
diff --git a/gnu/usr.bin/binutils/opcodes/frv-dis.c b/gnu/usr.bin/binutils/opcodes/frv-dis.c
index f71e1c5c83f..b0f51bce0ab 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/frv-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -152,8 +151,11 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
-      print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+    case FRV_OPERAND_A0 :
+      print_normal (cd, info, fields->f_A, 0, pc, length);
+      break;
+    case FRV_OPERAND_A1 :
+      print_normal (cd, info, fields->f_A, 0, pc, length);
       break;
     case FRV_OPERAND_ACC40SI :
       print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
@@ -230,12 +232,21 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case FRV_OPERAND_FRINTI :
       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
+      break;
     case FRV_OPERAND_FRINTJ :
       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
+      break;
     case FRV_OPERAND_FRINTK :
       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
     case FRV_OPERAND_FRJ :
       print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
       break;
@@ -385,13 +396,12 @@ frv_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -411,13 +421,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -441,12 +450,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -460,17 +468,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -502,14 +509,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -533,12 +539,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -643,10 +648,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -685,9 +687,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_frv (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_frv (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/frv-ibld.c b/gnu/usr.bin/binutils/opcodes/frv-ibld.c
index 316b2cc1bdb..565f4f49a0e 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/frv-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
@@ -569,7 +571,10 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_A1 :
       errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer);
       break;
     case FRV_OPERAND_ACC40SI :
@@ -651,12 +656,21 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case FRV_OPERAND_FRINTI :
       errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer);
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
     case FRV_OPERAND_FRINTJ :
       errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
     case FRV_OPERAND_FRINTK :
       errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
     case FRV_OPERAND_FRJ :
       errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
       break;
@@ -859,7 +873,10 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A);
+      break;
+    case FRV_OPERAND_A1 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A);
       break;
     case FRV_OPERAND_ACC40SI :
@@ -942,12 +959,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case FRV_OPERAND_FRINTI :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi);
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi);
+      break;
     case FRV_OPERAND_FRINTJ :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
+      break;
     case FRV_OPERAND_FRINTK :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
     case FRV_OPERAND_FRJ :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
       break;
@@ -1138,7 +1164,10 @@ frv_cgen_get_int_operand (cd, opindex, fields)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      value = fields->f_A;
+      break;
+    case FRV_OPERAND_A1 :
       value = fields->f_A;
       break;
     case FRV_OPERAND_ACC40SI :
@@ -1216,12 +1245,21 @@ frv_cgen_get_int_operand (cd, opindex, fields)
     case FRV_OPERAND_FRINTI :
       value = fields->f_FRi;
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      value = fields->f_FRi;
+      break;
     case FRV_OPERAND_FRINTJ :
       value = fields->f_FRj;
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      value = fields->f_FRj;
+      break;
     case FRV_OPERAND_FRINTK :
       value = fields->f_FRk;
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      value = fields->f_FRk;
+      break;
     case FRV_OPERAND_FRJ :
       value = fields->f_FRj;
       break;
@@ -1363,7 +1401,10 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
 
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      value = fields->f_A;
+      break;
+    case FRV_OPERAND_A1 :
       value = fields->f_A;
       break;
     case FRV_OPERAND_ACC40SI :
@@ -1441,12 +1482,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
     case FRV_OPERAND_FRINTI :
       value = fields->f_FRi;
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      value = fields->f_FRi;
+      break;
     case FRV_OPERAND_FRINTJ :
       value = fields->f_FRj;
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      value = fields->f_FRj;
+      break;
     case FRV_OPERAND_FRINTK :
       value = fields->f_FRk;
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      value = fields->f_FRk;
+      break;
     case FRV_OPERAND_FRJ :
       value = fields->f_FRj;
       break;
@@ -1597,7 +1647,10 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      fields->f_A = value;
+      break;
+    case FRV_OPERAND_A1 :
       fields->f_A = value;
       break;
     case FRV_OPERAND_ACC40SI :
@@ -1675,12 +1728,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
     case FRV_OPERAND_FRINTI :
       fields->f_FRi = value;
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      fields->f_FRi = value;
+      break;
     case FRV_OPERAND_FRINTJ :
       fields->f_FRj = value;
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      fields->f_FRj = value;
+      break;
     case FRV_OPERAND_FRINTK :
       fields->f_FRk = value;
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      fields->f_FRk = value;
+      break;
     case FRV_OPERAND_FRJ :
       fields->f_FRj = value;
       break;
@@ -1819,7 +1881,10 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
 {
   switch (opindex)
     {
-    case FRV_OPERAND_A :
+    case FRV_OPERAND_A0 :
+      fields->f_A = value;
+      break;
+    case FRV_OPERAND_A1 :
       fields->f_A = value;
       break;
     case FRV_OPERAND_ACC40SI :
@@ -1897,12 +1962,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
     case FRV_OPERAND_FRINTI :
       fields->f_FRi = value;
       break;
+    case FRV_OPERAND_FRINTIEVEN :
+      fields->f_FRi = value;
+      break;
     case FRV_OPERAND_FRINTJ :
       fields->f_FRj = value;
       break;
+    case FRV_OPERAND_FRINTJEVEN :
+      fields->f_FRj = value;
+      break;
     case FRV_OPERAND_FRINTK :
       fields->f_FRk = value;
       break;
+    case FRV_OPERAND_FRINTKEVEN :
+      fields->f_FRk = value;
+      break;
     case FRV_OPERAND_FRJ :
       fields->f_FRj = value;
       break;
diff --git a/gnu/usr.bin/binutils/opcodes/frv-opc.c b/gnu/usr.bin/binutils/opcodes/frv-opc.c
index 5e56e357645..1560d207dce 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/frv-opc.c
@@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* -- opc.c */
 #include "elf/frv.h"
+#include <stdio.h>
 
 static int match_unit
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE));
@@ -45,8 +46,10 @@ static int fr400_check_insn_major_constraints
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
 static int fr500_check_insn_major_constraints
   PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr550_check_insn_major_constraints
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
 static int check_insn_major_constraints
-  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
 
 int
 frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
@@ -141,37 +144,74 @@ frv_is_media_insn (const CGEN_INSN *insn)
 
 /* This table represents the allowable packing for vliw insns for the fr400.
    The fr400 has only 2 vliw slots. Represent this by not allowing any insns
-   in slots 2 and 3.
+   in the extra slots.
    Subsets of any given row are also allowed.  */
 static VLIW_COMBO fr400_allowed_vliw[] =
 {
   /*  slot0       slot1       slot2       slot3    */
-  {  UNIT_I0,    UNIT_I1,    UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_I0,    UNIT_FM0,   UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_I0,    UNIT_B0,    UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_FM0,   UNIT_FM1,   UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_FM0,   UNIT_B0,    UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_B0,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  }
+  {  UNIT_I0,    UNIT_I1,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_B0,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_B0,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO }
 };
 
 /* This table represents the allowable packing for vliw insns for the fr500.
+   The fr500 has only 4 vliw slots. Represent this by not allowing any insns
+   in the extra slots.
    Subsets of any given row are also allowed.  */
 static VLIW_COMBO fr500_allowed_vliw[] =
 {
   /*  slot0       slot1       slot2       slot3    */
-  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1  },
-  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0   },
-  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0   },
-  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1   },
-  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1   },
-  {  UNIT_I0,    UNIT_B0,    UNIT_B1,    UNIT_NIL  },
-  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1   },
-  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL  },
-  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
-  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  }
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1  PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_I0,    UNIT_B0,    UNIT_B1,    UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1   PAD_VLIW_COMBO },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  PAD_VLIW_COMBO }
+};
+
+/* This table represents the allowable packing for vliw insns for the fr550.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr550_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3       slot4       slot5       slot6       slot7   */
+  {  UNIT_I0,    UNIT_I1,    UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_I1,    UNIT_I2,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_B0,    UNIT_B1 ,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_I3,    UNIT_FM3 },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_I3,    UNIT_B0  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_FM3,   UNIT_B0  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_FM2,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_I2,    UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_I2,    UNIT_I3,    UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_I2,    UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1,    UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_FM3,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_FM2,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL }
 };
 
 /* Some insns are assigned specialized implementation units which map to
@@ -184,15 +224,28 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
 /* I0       */     UNIT_I0,
 /* I1       */     UNIT_I1,
 /* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
 /* FM0      */     UNIT_FM0,
 /* FM1      */     UNIT_FM1,
 /* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M3 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
 /* B0       */     UNIT_B0,  /* branches only in B0 unit.  */
 /* B1       */     UNIT_B0,
 /* B01      */     UNIT_B0,
 /* C        */     UNIT_C,
-/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0 unit.  */
-/* LOAD     */     UNIT_I0   /* load                only in I0 unit.  */
+/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0  unit.  */
+/* IACC     */     UNIT_I01, /* iacc multiply       in I0 or I1 unit.  */
+/* LOAD     */     UNIT_I0,  /* load                only in I0  unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0  unit.  */
+/* SCAN     */     UNIT_I0,  /* scan                only in I0  unit.  */
+/* DCPL     */     UNIT_C,   /* dcpl                only in C   unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
 };
 
 static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
@@ -202,15 +255,59 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
 /* I0       */     UNIT_I0,
 /* I1       */     UNIT_I1,
 /* I01      */     UNIT_I01, 
+/* I2       */     UNIT_NIL, /* no I2 or I3 unit */
+/* I3       */     UNIT_NIL,
+/* IALL     */     UNIT_I01, /* only I0 and I1 units */
 /* FM0      */     UNIT_FM0,
 /* FM1      */     UNIT_FM1,
 /* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_NIL, /* no F2 or M2 units */
+/* FM3      */     UNIT_NIL, /* no F3 or M2 units */
+/* FMALL    */     UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW    */     UNIT_FM0, /* Only F0,M0 units */
 /* B0       */     UNIT_B0,
 /* B1       */     UNIT_B1,
 /* B01      */     UNIT_B01,
 /* C        */     UNIT_C,
 /* MULT-DIV */     UNIT_I01, /* multiply and divide in I0 or I1 unit.  */
-/* LOAD     */     UNIT_I01  /* load                in I0 or I1 unit.  */
+/* IACC     */     UNIT_NIL, /* iacc multiply       not implemented */
+/* LOAD     */     UNIT_I01, /* load                in I0 or I1 unit.  */
+/* STORE    */     UNIT_I0,  /* store               only in I0 unit.  */
+/* SCAN     */     UNIT_I01, /* scan                in I0 or I1 unit.  */
+/* DCPL     */     UNIT_C,   /* dcpl                only in C unit.  */
+/* MDUALACC */     UNIT_FM0, /* media dual acc insn only in FM0 unit.  */
+/* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
+};
+
+static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* I2       */     UNIT_I2,
+/* I3       */     UNIT_I3,
+/* IALL     */     UNIT_IALL, 
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* FM2      */     UNIT_FM2,
+/* FM3      */     UNIT_FM3,
+/* FMALL    */     UNIT_FMALL,
+/* FMLOW    */     UNIT_FM01, /* Only F0,F1,M0,M1 units */
+/* B0       */     UNIT_B0,
+/* B1       */     UNIT_B1,
+/* B01      */     UNIT_B01,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I01,  /* multiply and divide in I0 or I1 unit.    */
+/* IACC     */     UNIT_NIL,  /* iacc multiply       not implemented.     */
+/* LOAD     */     UNIT_I01,  /* load                in I0 or I1 unit.    */
+/* STORE    */     UNIT_I01,  /* store               in I0 or I1 unit.    */
+/* SCAN     */     UNIT_IALL, /* scan                in any integer unit. */
+/* DCPL     */     UNIT_I0,   /* dcpl                only in I0 unit.     */
+/* MDUALACC */     UNIT_FMALL,/* media dual acc insn in all media units   */
+/* MCLRACC-1*/     UNIT_FM01  /* mclracc,A==1 in FM0 or FM1 unit.         */
 };
 
 void
@@ -227,6 +324,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
       vliw->current_vliw = fr400_allowed_vliw;
       vliw->unit_mapping = fr400_unit_mapping;
       break;
+    case bfd_mach_fr550:
+      vliw->current_vliw = fr550_allowed_vliw;
+      vliw->unit_mapping = fr550_unit_mapping;
+      break;
     default:
       vliw->current_vliw = fr500_allowed_vliw;
       vliw->unit_mapping = fr500_unit_mapping;
@@ -259,6 +360,13 @@ match_unit (FRV_VLIW *vliw,
       if (unit1 - unit2 <= 2)
 	return 1;
       break;
+    case UNIT_IALL:
+    case UNIT_FMALL:
+      /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
+	 versions.  */
+      if (unit1 - unit2 <= 5)
+	return 1;
+      break;
     default:
       break;
     }
@@ -293,7 +401,11 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
   VLIW_COMBO    *potential;
 
   if (next <= 0)
-    abort (); /* Should never happen */
+    {
+      fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n",
+	       __LINE__);
+      abort (); /* Should never happen */
+    }
 
   /* The table is sorted by units allowed within slots, so vliws with
      identical starting sequences are together.  */
@@ -348,6 +460,123 @@ fr400_check_insn_major_constraints (
 }
 
 static int
+find_unit_in_vliw (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
+)
+{
+  int i;
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
+      return 1;
+
+  return 0; /* not found */
+}
+
+static int
+find_major_in_slot (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot
+)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
+      return 1;
+
+  return 0;
+}
+
+static int
+fr550_find_media_in_vliw (FRV_VLIW *vliw)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    {
+      if (vliw->major[i] < FR550_MAJOR_M_1 || vliw->major[i] > FR550_MAJOR_M_5)
+	continue;
+
+      /* Found a media insn, however, MNOP and MCLRACC don't count.  */
+      if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MNOP
+	  || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_0
+	  || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
+	continue;
+
+      return 1; /* found one */
+    }
+
+  return 0;
+}
+
+static int
+fr550_find_float_in_vliw (FRV_VLIW *vliw)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    {
+      if (vliw->major[i] < FR550_MAJOR_F_1 || vliw->major[i] > FR550_MAJOR_F_4)
+	continue;
+
+      /* Found a floating point insn, however, FNOP doesn't count.  */
+      if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
+	continue;
+
+      return 1; /* found one */
+    }
+
+  return 0;
+}
+
+static int
+fr550_check_insn_major_constraints (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
+)
+{
+  CGEN_ATTR_VALUE_TYPE unit;
+  CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
+  switch (slot)
+    {
+    case UNIT_I2:
+      /* If it's a store, then there must be another store in I1 */
+      unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
+      if (unit == UNIT_STORE)
+	return find_unit_in_vliw (vliw, UNIT_STORE);
+      break;
+    case UNIT_FM2:
+    case UNIT_FM3:
+      /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with
+	 media insns.  */
+      if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4
+	  && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP)
+	return ! fr550_find_media_in_vliw (vliw);
+      /* Media insns other than MNOP in slot m2 or m3 cannot coexist with
+	 floating point insns.  */
+      if (major >= FR550_MAJOR_M_1 && major <= FR550_MAJOR_M_5
+	  && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP)
+	return ! fr550_find_float_in_vliw (vliw);
+      /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2
+	 respectively.
+       */
+      if (major == FR550_MAJOR_F_2)
+	return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0))
+	  &&   ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0));
+      /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2
+	 respectively.  */
+      if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5)
+	return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0));
+      /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2
+	 respectively.  */
+      if (major == FR550_MAJOR_M_4)
+	return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0));
+      break;
+    default:
+      break;
+    }
+  return 1; /* all ok */
+}
+
+static int
 fr500_check_insn_major_constraints (
   FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
 )
@@ -448,6 +677,8 @@ fr500_check_insn_major_constraints (
 	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
 	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7);
     default:
+      fprintf (stderr, "frv-opc.c, line %d: bad major code, aborting.\n",
+	       __LINE__);
       abort ();
       break;
     }
@@ -456,7 +687,7 @@ fr500_check_insn_major_constraints (
 
 static int
 check_insn_major_constraints (
-  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
 )
 {
   int rc;
@@ -465,6 +696,9 @@ check_insn_major_constraints (
     case bfd_mach_fr400:
       rc = fr400_check_insn_major_constraints (vliw, major);
       break;
+    case bfd_mach_fr550:
+      rc = fr550_check_insn_major_constraints (vliw, major, insn);
+      break;
     default:
       rc = fr500_check_insn_major_constraints (vliw, major);
       break;
@@ -491,12 +725,24 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 
   unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
   if (unit == UNIT_NIL)
-    abort (); /* no UNIT specified for this insn in frv.cpu  */
+    {
+      fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n",
+	       __LINE__);
+      abort (); /* no UNIT specified for this insn in frv.cpu  */
+    }
 
-  if (vliw->mach == bfd_mach_fr400)
-    major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
-  else
-    major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
+  switch (vliw->mach)
+    {
+    case bfd_mach_fr400:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
+      break;
+    case bfd_mach_fr550:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
+      break;
+    default:
+      major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
+      break;
+    }
 
   if (index <= 0)
     {
@@ -504,6 +750,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
       while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))
 	++vliw->current_vliw;
       vliw->major[0] = major;
+      vliw->insn[0] = insn;
       vliw->next_slot = 1;
       return 0;
     }
@@ -514,10 +761,11 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
   if (! (vliw->elf_flags & EF_FRV_NOPACK))
     {
       new_vliw = add_next_to_vliw (vliw, unit);
-      if (new_vliw && check_insn_major_constraints (vliw, major))
+      if (new_vliw && check_insn_major_constraints (vliw, major, insn))
 	{
 	  vliw->current_vliw = new_vliw;
 	  vliw->major[index] = major;
+	  vliw->insn[index] = insn;
 	  vliw->next_slot++;
 	  return 0;
 	}
@@ -573,6 +821,18 @@ static const CGEN_IFMT ifmt_smul = {
   32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_smu = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_slass = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_scutss = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_cadd = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
 };
@@ -625,10 +885,6 @@ static const CGEN_IFMT ifmt_setlos = {
   32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_S16) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ldsb = {
-  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_ldbf = {
   32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
 };
@@ -665,10 +921,6 @@ static const CGEN_IFMT ifmt_lddfi = {
   32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_stdf = {
-  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_cldbf = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
 };
@@ -677,14 +929,6 @@ static const CGEN_IFMT ifmt_clddf = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_cstdf = {
-  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_stdfi = {
-  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_movgf = {
   32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
 };
@@ -889,10 +1133,6 @@ static const CGEN_IFMT ifmt_ccalll = {
   32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ici = {
-  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_icei = {
   32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_AE) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
 };
@@ -1033,6 +1273,18 @@ static const CGEN_IFMT ifmt_mcuti = {
   32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mdcutssi = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mdrotli = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mqsaths = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_mcmpsh = {
   32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
 };
@@ -1041,6 +1293,10 @@ static const CGEN_IFMT ifmt_mabshs = {
   32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_cmqaddhss = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_maddaccs = {
   32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } }
 };
@@ -1053,6 +1309,14 @@ static const CGEN_IFMT ifmt_cmmulhs = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mqmulhs = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmqmulhs = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_mmachu = {
   32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
 };
@@ -1061,20 +1325,60 @@ static const CGEN_IFMT ifmt_cmmachu = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mqmachu = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmqmachu = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_cmexpdhw = {
   32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mexpdhd = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmexpdhd = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_munpackh = {
   32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_mdunpackh = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mbtoh = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_cmbtoh = {
   32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_mclracc = {
-  32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+static const CGEN_IFMT ifmt_mhtob = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmhtob = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmbtohe = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mnop = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mclracc_0 = {
+  32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mrdacc = {
@@ -1192,6 +1496,24 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } },
     & ifmt_smul, { 0x280 }
   },
+/* smu$pack $GRi,$GRj */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } },
+    & ifmt_smu, { 0x1180140 }
+  },
+/* smass$pack $GRi,$GRj */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } },
+    & ifmt_smu, { 0x1180180 }
+  },
+/* smsss$pack $GRi,$GRj */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } },
+    & ifmt_smu, { 0x11801c0 }
+  },
 /* sll$pack $GRi,$GRj,$GRk */
   {
     { 0, 0, 0, 0 },
@@ -1210,6 +1532,18 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
     & ifmt_add, { 0x40300 }
   },
+/* slass$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_slass, { 0x1180080 }
+  },
+/* scutss$pack $GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_scutss, { 0x1180100 }
+  },
 /* scan$pack $GRi,$GRj,$GRk */
   {
     { 0, 0, 0, 0 },
@@ -1432,6 +1766,18 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
     & ifmt_addcc, { 0x1c0 }
   },
+/* addss$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_slass, { 0x1180000 }
+  },
+/* subss$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_slass, { 0x1180040 }
+  },
 /* addi$pack $GRi,$s12,$GRk */
   {
     { 0, 0, 0, 0 },
@@ -1640,31 +1986,31 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80000 }
+    & ifmt_slass, { 0x80000 }
   },
 /* ldub$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80040 }
+    & ifmt_slass, { 0x80040 }
   },
 /* ldsh$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80080 }
+    & ifmt_slass, { 0x80080 }
   },
 /* lduh$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x800c0 }
+    & ifmt_slass, { 0x800c0 }
   },
 /* ld$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80100 }
+    & ifmt_slass, { 0x80100 }
   },
 /* ldbf$pack @($GRi,$GRj),$FRintk */
   {
@@ -1694,31 +2040,31 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80800 }
+    & ifmt_slass, { 0x80800 }
   },
 /* nldub$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80840 }
+    & ifmt_slass, { 0x80840 }
   },
 /* nldsh$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80880 }
+    & ifmt_slass, { 0x80880 }
   },
 /* nlduh$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x808c0 }
+    & ifmt_slass, { 0x808c0 }
   },
 /* nld$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80900 }
+    & ifmt_slass, { 0x80900 }
   },
 /* nldbf$pack @($GRi,$GRj),$FRintk */
   {
@@ -1772,7 +2118,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80180 }
+    & ifmt_slass, { 0x80180 }
   },
 /* ldqf$pack @($GRi,$GRj),$FRintk */
   {
@@ -1790,7 +2136,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80980 }
+    & ifmt_slass, { 0x80980 }
   },
 /* nldqf$pack @($GRi,$GRj),$FRintk */
   {
@@ -1802,61 +2148,61 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80400 }
+    & ifmt_slass, { 0x80400 }
   },
 /* ldubu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80440 }
+    & ifmt_slass, { 0x80440 }
   },
 /* ldshu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80480 }
+    & ifmt_slass, { 0x80480 }
   },
 /* lduhu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x804c0 }
+    & ifmt_slass, { 0x804c0 }
   },
 /* ldu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80500 }
+    & ifmt_slass, { 0x80500 }
   },
 /* nldsbu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80c00 }
+    & ifmt_slass, { 0x80c00 }
   },
 /* nldubu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80c40 }
+    & ifmt_slass, { 0x80c40 }
   },
 /* nldshu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80c80 }
+    & ifmt_slass, { 0x80c80 }
   },
 /* nlduhu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80cc0 }
+    & ifmt_slass, { 0x80cc0 }
   },
 /* nldu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80d00 }
+    & ifmt_slass, { 0x80d00 }
   },
 /* ldbfu$pack @($GRi,$GRj),$FRintk */
   {
@@ -1934,13 +2280,13 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80580 }
+    & ifmt_slass, { 0x80580 }
   },
 /* nldqu$pack @($GRi,$GRj),$GRk */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0x80d80 }
+    & ifmt_slass, { 0x80d80 }
   },
 /* ldqfu$pack @($GRi,$GRj),$FRintk */
   {
@@ -2092,12 +2438,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
     & ifmt_ldbfi, { 0xf00000 }
   },
-/* nldqi$pack @($GRi,$d12),$GRk */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsbi, { 0x1180000 }
-  },
 /* nldqfi$pack @($GRi,$d12),$FRintk */
   {
     { 0, 0, 0, 0 },
@@ -2108,19 +2448,19 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0000 }
+    & ifmt_slass, { 0xc0000 }
   },
 /* sth$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0040 }
+    & ifmt_slass, { 0xc0040 }
   },
 /* st$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0080 }
+    & ifmt_slass, { 0xc0080 }
   },
 /* stbf$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2150,19 +2490,19 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0800 }
+    & ifmt_slass, { 0xc0800 }
   },
 /* rsth$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0840 }
+    & ifmt_slass, { 0xc0840 }
   },
 /* rst$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0880 }
+    & ifmt_slass, { 0xc0880 }
   },
 /* rstbf$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2182,41 +2522,41 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
     & ifmt_ldbf, { 0xc0a80 }
   },
-/* std$pack $GRk,@($GRi,$GRj) */
+/* std$pack $GRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc00c0 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldd, { 0xc00c0 }
   },
-/* stdf$pack $FRk,@($GRi,$GRj) */
+/* stdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_stdf, { 0xc02c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_lddf, { 0xc02c0 }
   },
-/* stdc$pack $CPRk,@($GRi,$GRj) */
+/* stdc$pack $CPRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldc, { 0xc0980 }
+    { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_lddc, { 0xc0980 }
   },
-/* rstd$pack $GRk,@($GRi,$GRj) */
+/* rstd$pack $GRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc08c0 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldd, { 0xc08c0 }
   },
-/* rstdf$pack $FRk,@($GRi,$GRj) */
+/* rstdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_stdf, { 0xc0ac0 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_lddf, { 0xc0ac0 }
   },
 /* stq$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0100 }
+    & ifmt_slass, { 0xc0100 }
   },
 /* stqf$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2234,7 +2574,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0900 }
+    & ifmt_slass, { 0xc0900 }
   },
 /* rstqf$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2246,19 +2586,19 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0400 }
+    & ifmt_slass, { 0xc0400 }
   },
 /* sthu$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0440 }
+    & ifmt_slass, { 0xc0440 }
   },
 /* stu$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0480 }
+    & ifmt_slass, { 0xc0480 }
   },
 /* stbfu$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2284,29 +2624,29 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
     & ifmt_ldc, { 0xc0b40 }
   },
-/* stdu$pack $GRk,@($GRi,$GRj) */
+/* stdu$pack $GRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc04c0 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldd, { 0xc04c0 }
   },
-/* stdfu$pack $FRk,@($GRi,$GRj) */
+/* stdfu$pack $FRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_stdf, { 0xc06c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_lddf, { 0xc06c0 }
   },
-/* stdcu$pack $CPRk,@($GRi,$GRj) */
+/* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldc, { 0xc0b80 }
+    { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_lddc, { 0xc0b80 }
   },
 /* stqu$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0500 }
+    & ifmt_slass, { 0xc0500 }
   },
 /* stqfu$pack $FRintk,@($GRi,$GRj) */
   {
@@ -2488,17 +2828,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cldbf, { 0x1980080 }
   },
-/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+/* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cadd, { 0x19000c0 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_csmul, { 0x19000c0 }
   },
-/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cstdf, { 0x19800c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_clddf, { 0x19800c0 }
   },
 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
@@ -2542,17 +2882,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cldbf, { 0x1a00080 }
   },
-/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cadd, { 0x19c00c0 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_csmul, { 0x19c00c0 }
   },
-/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+/* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cstdf, { 0x1a000c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_clddf, { 0x1a000c0 }
   },
 /* stbi$pack $GRk,@($GRi,$d12) */
   {
@@ -2590,17 +2930,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } },
     & ifmt_ldbfi, { 0x1540000 }
   },
-/* stdi$pack $GRk,@($GRi,$d12) */
+/* stdi$pack $GRdoublek,@($GRi,$d12) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } },
-    & ifmt_ldsbi, { 0x14c0000 }
+    { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } },
+    & ifmt_lddi, { 0x14c0000 }
   },
-/* stdfi$pack $FRk,@($GRi,$d12) */
+/* stdfi$pack $FRdoublek,@($GRi,$d12) */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } },
-    & ifmt_stdfi, { 0x1580000 }
+    { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } },
+    & ifmt_lddfi, { 0x1580000 }
   },
 /* stqi$pack $GRk,@($GRi,$d12) */
   {
@@ -2618,7 +2958,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
-    & ifmt_ldsb, { 0xc0140 }
+    & ifmt_slass, { 0xc0140 }
   },
 /* swapi$pack @($GRi,$d12),$GRk */
   {
@@ -4184,13 +4524,13 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ici, { 0xc0e00 }
+    & ifmt_smu, { 0xc0e00 }
   },
 /* dci$pack @($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ici, { 0xc0f00 }
+    & ifmt_smu, { 0xc0f00 }
   },
 /* icei$pack @($GRi,$GRj),$ae */
   {
@@ -4208,7 +4548,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ici, { 0xc0f40 }
+    & ifmt_smu, { 0xc0f40 }
   },
 /* dcef$pack @($GRi,$GRj),$ae */
   {
@@ -4220,25 +4560,25 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0c80 }
+    & ifmt_slass, { 0xc0c80 }
   },
 /* wdtlb$pack $GRk,@($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ldsb, { 0xc0d80 }
+    & ifmt_slass, { 0xc0d80 }
   },
 /* itlbi$pack @($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ici, { 0xc0cc0 }
+    & ifmt_smu, { 0xc0cc0 }
   },
 /* dtlbi$pack @($GRi,$GRj) */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
-    & ifmt_ici, { 0xc0dc0 }
+    & ifmt_smu, { 0xc0dc0 }
   },
 /* icpl$pack $GRi,$GRj,$lock */
   {
@@ -4978,11 +5318,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } },
     & ifmt_mcuti, { 0x1ec0bc0 }
   },
-/* mdcutssi$pack $ACC40Si,$s6,$FRintk */
+/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } },
-    & ifmt_mcuti, { 0x1e00380 }
+    { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mdcutssi, { 0x1e00380 }
   },
 /* maveh$pack $FRinti,$FRintj,$FRintk */
   {
@@ -5008,11 +5348,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } },
     & ifmt_mrotli, { 0x1ec02c0 }
   },
-/* mdrotli$pack $FRinti,$u6,$FRintk */
+/* mdrotli$pack $FRintieven,$s6,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } },
-    & ifmt_mrotli, { 0x1e002c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mdrotli, { 0x1e002c0 }
   },
 /* mcplhi$pack $FRinti,$u6,$FRintk */
   {
@@ -5032,11 +5372,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
     & ifmt_mand, { 0x1ec0300 }
   },
-/* mqsaths$pack $FRinti,$FRintj,$FRintk */
+/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1e003c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1e003c0 }
   },
 /* msathu$pack $FRinti,$FRintj,$FRintk */
   {
@@ -5110,53 +5450,53 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmand, { 0x1c400c0 }
   },
-/* mqaddhss$pack $FRinti,$FRintj,$FRintk */
+/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1ec0600 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1ec0600 }
   },
-/* mqaddhus$pack $FRinti,$FRintj,$FRintk */
+/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1ec0640 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1ec0640 }
   },
-/* mqsubhss$pack $FRinti,$FRintj,$FRintk */
+/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1ec0680 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1ec0680 }
   },
-/* mqsubhus$pack $FRinti,$FRintj,$FRintk */
+/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1ec06c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1ec06c0 }
   },
-/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmand, { 0x1cc0000 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqaddhss, { 0x1cc0000 }
   },
-/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmand, { 0x1cc0040 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqaddhss, { 0x1cc0040 }
   },
-/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmand, { 0x1cc0080 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqaddhss, { 0x1cc0080 }
   },
-/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmand, { 0x1cc00c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqaddhss, { 0x1cc00c0 }
   },
 /* maddaccs$pack $ACC40Si,$ACC40Sk */
   {
@@ -5230,41 +5570,41 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmmulhs, { 0x1c80040 }
   },
-/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0700 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0700 }
   },
-/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0740 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0740 }
   },
-/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0a80 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0a80 }
   },
-/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0ac0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0ac0 }
   },
-/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmmulhs, { 0x1d00000 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqmulhs, { 0x1d00000 }
   },
-/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmmulhs, { 0x1d00040 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqmulhs, { 0x1d00040 }
   },
 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
   {
@@ -5302,47 +5642,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmmachu, { 0x1c800c0 }
   },
-/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0780 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0780 }
   },
-/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
+/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } },
-    & ifmt_mmachu, { 0x1ec07c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), 0 } },
+    & ifmt_mqmachu, { 0x1ec07c0 }
   },
-/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmmulhs, { 0x1d00080 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqmulhs, { 0x1d00080 }
   },
-/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
+/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmmachu, { 0x1d000c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmqmachu, { 0x1d000c0 }
   },
-/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1e00000 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1e00000 }
   },
-/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1e00040 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1e00040 }
   },
-/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1e00080 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1e00080 }
   },
 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
   {
@@ -5392,29 +5732,29 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmmulhs, { 0x1d400c0 }
   },
-/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0900 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0900 }
   },
-/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0940 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0940 }
   },
-/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec0980 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec0980 }
   },
-/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
+/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } },
-    & ifmt_mmulhs, { 0x1ec09c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } },
+    & ifmt_mqmulhs, { 0x1ec09c0 }
   },
 /* mexpdhw$pack $FRinti,$u6,$FRintk */
   {
@@ -5428,17 +5768,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmexpdhw, { 0x1d80080 }
   },
-/* mexpdhd$pack $FRinti,$u6,$FRintk */
+/* mexpdhd$pack $FRinti,$u6,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } },
-    & ifmt_mrotli, { 0x1ec0cc0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mexpdhd, { 0x1ec0cc0 }
   },
-/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
+/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmexpdhw, { 0x1d800c0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmexpdhd, { 0x1d800c0 }
   },
 /* mpackh$pack $FRinti,$FRintj,$FRintk */
   {
@@ -5446,47 +5786,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
     & ifmt_mand, { 0x1ec0d00 }
   },
-/* mdpackh$pack $FRinti,$FRintj,$FRintk */
+/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mand, { 0x1ec0d80 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mqsaths, { 0x1ec0d80 }
   },
-/* munpackh$pack $FRinti,$FRintk */
+/* munpackh$pack $FRinti,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } },
+    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTKEVEN), 0 } },
     & ifmt_munpackh, { 0x1ec0d40 }
   },
-/* mdunpackh$pack $FRinti,$FRintk */
+/* mdunpackh$pack $FRintieven,$FRintk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } },
-    & ifmt_munpackh, { 0x1ec0dc0 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTK), 0 } },
+    & ifmt_mdunpackh, { 0x1ec0dc0 }
   },
-/* mbtoh$pack $FRintj,$FRintk */
+/* mbtoh$pack $FRintj,$FRintkeven */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mabshs, { 0x1ec0e00 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), 0 } },
+    & ifmt_mbtoh, { 0x1ec0e00 }
   },
-/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
+/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
+    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
     & ifmt_cmbtoh, { 0x1dc0000 }
   },
-/* mhtob$pack $FRintj,$FRintk */
+/* mhtob$pack $FRintjeven,$FRintk */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } },
-    & ifmt_mabshs, { 0x1ec0e40 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), 0 } },
+    & ifmt_mhtob, { 0x1ec0e40 }
   },
-/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
+/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmbtoh, { 0x1dc0040 }
+    { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cmhtob, { 0x1dc0040 }
   },
 /* mbtohe$pack $FRintj,$FRintk */
   {
@@ -5498,13 +5838,25 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } },
-    & ifmt_cmbtoh, { 0x1dc0080 }
+    & ifmt_cmbtohe, { 0x1dc0080 }
+  },
+/* mnop$pack */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), 0 } },
+    & ifmt_mnop, { 0x7fee0ec0 }
   },
-/* mclracc$pack $ACC40Sk,$A */
+/* mclracc$pack $ACC40Sk,$A0 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } },
-    & ifmt_mclracc, { 0x1ec0ec0 }
+    { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A0), 0 } },
+    & ifmt_mclracc_0, { 0x1ec0ec0 }
+  },
+/* mclracc$pack $ACC40Sk,$A1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A1), 0 } },
+    & ifmt_mclracc_0, { 0x1ee0ec0 }
   },
 /* mrdacc$pack $ACC40Si,$FRintk */
   {
@@ -5566,10 +5918,6 @@ static const CGEN_IFMT ifmt_nop = {
   32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_mnop = {
-  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_ret = {
   32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
 };
@@ -5618,42 +5966,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
 /* nop$pack */
   {
     -1, "nop", "nop", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
-  },
-/* mnop$pack */
-  {
-    -1, "mnop", "mnop", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* ret$pack */
   {
     -1, "ret", "ret", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
   },
 /* cmp$pack $GRi,$GRj,$ICCi_1 */
   {
     -1, "cmp", "cmp", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* cmpi$pack $GRi,$s10,$ICCi_1 */
   {
     -1, "cmpi", "cmpi", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* ccmp$pack $GRi,$GRj,$CCi,$cond */
   {
     -1, "ccmp", "ccmp", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* mov$pack $GRi,$GRk */
   {
     -1, "mov", "mov", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 /* cmov$pack $GRi,$GRk,$CCi,$cond */
   {
     -1, "cmov", "cmov", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
   },
 };
 
@@ -5667,12 +6010,6 @@ static const CGEN_OPCODE frv_cgen_macro_insn_opcode_table[] =
     { { MNEM, OP (PACK), 0 } },
     & ifmt_nop, { 0x880000 }
   },
-/* mnop$pack */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, OP (PACK), 0 } },
-    & ifmt_mnop, { 0x7fee0ec0 }
-  },
 /* ret$pack */
   {
     { 0, 0, 0, 0 },
diff --git a/gnu/usr.bin/binutils/opcodes/frv-opc.h b/gnu/usr.bin/binutils/opcodes/frv-opc.h
index 018a64378d7..e166fa25615 100644
--- a/gnu/usr.bin/binutils/opcodes/frv-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/frv-opc.h
@@ -27,13 +27,17 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* -- opc.h */
 
-#undef CGEN_DIS_HASH_SIZE
+#undef  CGEN_DIS_HASH_SIZE
 #define CGEN_DIS_HASH_SIZE 128
-#undef CGEN_DIS_HASH
+#undef  CGEN_DIS_HASH
 #define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127)
 
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
 /* Vliw support.  */
-#define FRV_VLIW_SIZE 4 /* fr500 has largest vliw size of 4.  */
+#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
+#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
 typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
 typedef struct
@@ -45,6 +49,7 @@ typedef struct
   CGEN_ATTR_VALUE_TYPE *unit_mapping;
   VLIW_COMBO           *current_vliw;
   CGEN_ATTR_VALUE_TYPE  major[FRV_VLIW_SIZE];
+  const CGEN_INSN*      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
 int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
@@ -62,186 +67,188 @@ typedef enum cgen_insn_type {
   FRV_INSN_INVALID, FRV_INSN_ADD, FRV_INSN_SUB, FRV_INSN_AND
  , FRV_INSN_OR, FRV_INSN_XOR, FRV_INSN_NOT, FRV_INSN_SDIV
  , FRV_INSN_NSDIV, FRV_INSN_UDIV, FRV_INSN_NUDIV, FRV_INSN_SMUL
- , FRV_INSN_UMUL, FRV_INSN_SLL, FRV_INSN_SRL, FRV_INSN_SRA
- , FRV_INSN_SCAN, FRV_INSN_CADD, FRV_INSN_CSUB, FRV_INSN_CAND
- , FRV_INSN_COR, FRV_INSN_CXOR, FRV_INSN_CNOT, FRV_INSN_CSMUL
- , FRV_INSN_CSDIV, FRV_INSN_CUDIV, FRV_INSN_CSLL, FRV_INSN_CSRL
- , FRV_INSN_CSRA, FRV_INSN_CSCAN, FRV_INSN_ADDCC, FRV_INSN_SUBCC
- , FRV_INSN_ANDCC, FRV_INSN_ORCC, FRV_INSN_XORCC, FRV_INSN_SLLCC
- , FRV_INSN_SRLCC, FRV_INSN_SRACC, FRV_INSN_SMULCC, FRV_INSN_UMULCC
- , FRV_INSN_CADDCC, FRV_INSN_CSUBCC, FRV_INSN_CSMULCC, FRV_INSN_CANDCC
- , FRV_INSN_CORCC, FRV_INSN_CXORCC, FRV_INSN_CSLLCC, FRV_INSN_CSRLCC
- , FRV_INSN_CSRACC, FRV_INSN_ADDX, FRV_INSN_SUBX, FRV_INSN_ADDXCC
- , FRV_INSN_SUBXCC, FRV_INSN_ADDI, FRV_INSN_SUBI, FRV_INSN_ANDI
- , FRV_INSN_ORI, FRV_INSN_XORI, FRV_INSN_SDIVI, FRV_INSN_NSDIVI
- , FRV_INSN_UDIVI, FRV_INSN_NUDIVI, FRV_INSN_SMULI, FRV_INSN_UMULI
- , FRV_INSN_SLLI, FRV_INSN_SRLI, FRV_INSN_SRAI, FRV_INSN_SCANI
- , FRV_INSN_ADDICC, FRV_INSN_SUBICC, FRV_INSN_ANDICC, FRV_INSN_ORICC
- , FRV_INSN_XORICC, FRV_INSN_SMULICC, FRV_INSN_UMULICC, FRV_INSN_SLLICC
- , FRV_INSN_SRLICC, FRV_INSN_SRAICC, FRV_INSN_ADDXI, FRV_INSN_SUBXI
- , FRV_INSN_ADDXICC, FRV_INSN_SUBXICC, FRV_INSN_CMPB, FRV_INSN_CMPBA
- , FRV_INSN_SETLO, FRV_INSN_SETHI, FRV_INSN_SETLOS, FRV_INSN_LDSB
- , FRV_INSN_LDUB, FRV_INSN_LDSH, FRV_INSN_LDUH, FRV_INSN_LD
- , FRV_INSN_LDBF, FRV_INSN_LDHF, FRV_INSN_LDF, FRV_INSN_LDC
- , FRV_INSN_NLDSB, FRV_INSN_NLDUB, FRV_INSN_NLDSH, FRV_INSN_NLDUH
- , FRV_INSN_NLD, FRV_INSN_NLDBF, FRV_INSN_NLDHF, FRV_INSN_NLDF
- , FRV_INSN_LDD, FRV_INSN_LDDF, FRV_INSN_LDDC, FRV_INSN_NLDD
- , FRV_INSN_NLDDF, FRV_INSN_LDQ, FRV_INSN_LDQF, FRV_INSN_LDQC
- , FRV_INSN_NLDQ, FRV_INSN_NLDQF, FRV_INSN_LDSBU, FRV_INSN_LDUBU
- , FRV_INSN_LDSHU, FRV_INSN_LDUHU, FRV_INSN_LDU, FRV_INSN_NLDSBU
- , FRV_INSN_NLDUBU, FRV_INSN_NLDSHU, FRV_INSN_NLDUHU, FRV_INSN_NLDU
- , FRV_INSN_LDBFU, FRV_INSN_LDHFU, FRV_INSN_LDFU, FRV_INSN_LDCU
- , FRV_INSN_NLDBFU, FRV_INSN_NLDHFU, FRV_INSN_NLDFU, FRV_INSN_LDDU
- , FRV_INSN_NLDDU, FRV_INSN_LDDFU, FRV_INSN_LDDCU, FRV_INSN_NLDDFU
- , FRV_INSN_LDQU, FRV_INSN_NLDQU, FRV_INSN_LDQFU, FRV_INSN_LDQCU
- , FRV_INSN_NLDQFU, FRV_INSN_LDSBI, FRV_INSN_LDSHI, FRV_INSN_LDI
- , FRV_INSN_LDUBI, FRV_INSN_LDUHI, FRV_INSN_LDBFI, FRV_INSN_LDHFI
- , FRV_INSN_LDFI, FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI
- , FRV_INSN_NLDUHI, FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI
- , FRV_INSN_NLDFI, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI
- , FRV_INSN_NLDDFI, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQI
- , FRV_INSN_NLDQFI, FRV_INSN_STB, FRV_INSN_STH, FRV_INSN_ST
- , FRV_INSN_STBF, FRV_INSN_STHF, FRV_INSN_STF, FRV_INSN_STC
- , FRV_INSN_RSTB, FRV_INSN_RSTH, FRV_INSN_RST, FRV_INSN_RSTBF
- , FRV_INSN_RSTHF, FRV_INSN_RSTF, FRV_INSN_STD, FRV_INSN_STDF
- , FRV_INSN_STDC, FRV_INSN_RSTD, FRV_INSN_RSTDF, FRV_INSN_STQ
- , FRV_INSN_STQF, FRV_INSN_STQC, FRV_INSN_RSTQ, FRV_INSN_RSTQF
- , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU
- , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU
- , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU
- , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH
- , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF
- , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ
- , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU
- , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU
- , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB
- , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF
- , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ
- , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU
- , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU
- , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI
- , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI
- , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI
- , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD
- , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF
- , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS
- , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ
- , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT
- , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC
- , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV
- , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE
- , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL
- , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG
- , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU
- , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR
- , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR
- , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR
- , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR
- , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR
- , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR
- , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR
- , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR
- , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR
- , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR
- , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR
- , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR
- , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR
- , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR
- , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR
- , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR
- , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL
- , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT
- , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ
- , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT
- , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC
- , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV
- , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE
- , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL
- , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG
- , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU
- , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ
- , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT
- , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC
- , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV
- , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE
- , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL
- , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG
- , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU
- , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR
- , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR
- , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR
- , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ
- , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT
- , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC
- , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV
- , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE
- , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL
- , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG
- , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU
- , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ
- , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT
- , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC
- , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV
- , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE
- , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL
- , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG
- , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU
- , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI
- , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
- , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
- , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
- , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1
- , FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA
- , FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA
- , FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD
- , FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS
- , FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS
- , FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS
- , FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS
- , FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS
- , FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS
- , FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS
- , FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD
- , FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS
- , FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS
- , FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS
- , FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS
- , FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS
- , FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS
- , FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS
- , FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS
- , FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS
- , FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS
- , FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS
- , FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS
- , FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS
- , FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH
- , FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND
- , FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT
- , FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI
- , FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI
- , FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI
- , FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI
- , FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH
- , FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS
- , FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS
- , FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS
- , FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS
- , FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS
- , FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS
- , FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU
- , FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU
- , FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU
- , FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU
- , FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU
- , FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS
- , FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS
- , FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS
- , FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS
- , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
- , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
- , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
- , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MCLRACC
+ , FRV_INSN_UMUL, FRV_INSN_SMU, FRV_INSN_SMASS, FRV_INSN_SMSSS
+ , FRV_INSN_SLL, FRV_INSN_SRL, FRV_INSN_SRA, FRV_INSN_SLASS
+ , FRV_INSN_SCUTSS, FRV_INSN_SCAN, FRV_INSN_CADD, FRV_INSN_CSUB
+ , FRV_INSN_CAND, FRV_INSN_COR, FRV_INSN_CXOR, FRV_INSN_CNOT
+ , FRV_INSN_CSMUL, FRV_INSN_CSDIV, FRV_INSN_CUDIV, FRV_INSN_CSLL
+ , FRV_INSN_CSRL, FRV_INSN_CSRA, FRV_INSN_CSCAN, FRV_INSN_ADDCC
+ , FRV_INSN_SUBCC, FRV_INSN_ANDCC, FRV_INSN_ORCC, FRV_INSN_XORCC
+ , FRV_INSN_SLLCC, FRV_INSN_SRLCC, FRV_INSN_SRACC, FRV_INSN_SMULCC
+ , FRV_INSN_UMULCC, FRV_INSN_CADDCC, FRV_INSN_CSUBCC, FRV_INSN_CSMULCC
+ , FRV_INSN_CANDCC, FRV_INSN_CORCC, FRV_INSN_CXORCC, FRV_INSN_CSLLCC
+ , FRV_INSN_CSRLCC, FRV_INSN_CSRACC, FRV_INSN_ADDX, FRV_INSN_SUBX
+ , FRV_INSN_ADDXCC, FRV_INSN_SUBXCC, FRV_INSN_ADDSS, FRV_INSN_SUBSS
+ , FRV_INSN_ADDI, FRV_INSN_SUBI, FRV_INSN_ANDI, FRV_INSN_ORI
+ , FRV_INSN_XORI, FRV_INSN_SDIVI, FRV_INSN_NSDIVI, FRV_INSN_UDIVI
+ , FRV_INSN_NUDIVI, FRV_INSN_SMULI, FRV_INSN_UMULI, FRV_INSN_SLLI
+ , FRV_INSN_SRLI, FRV_INSN_SRAI, FRV_INSN_SCANI, FRV_INSN_ADDICC
+ , FRV_INSN_SUBICC, FRV_INSN_ANDICC, FRV_INSN_ORICC, FRV_INSN_XORICC
+ , FRV_INSN_SMULICC, FRV_INSN_UMULICC, FRV_INSN_SLLICC, FRV_INSN_SRLICC
+ , FRV_INSN_SRAICC, FRV_INSN_ADDXI, FRV_INSN_SUBXI, FRV_INSN_ADDXICC
+ , FRV_INSN_SUBXICC, FRV_INSN_CMPB, FRV_INSN_CMPBA, FRV_INSN_SETLO
+ , FRV_INSN_SETHI, FRV_INSN_SETLOS, FRV_INSN_LDSB, FRV_INSN_LDUB
+ , FRV_INSN_LDSH, FRV_INSN_LDUH, FRV_INSN_LD, FRV_INSN_LDBF
+ , FRV_INSN_LDHF, FRV_INSN_LDF, FRV_INSN_LDC, FRV_INSN_NLDSB
+ , FRV_INSN_NLDUB, FRV_INSN_NLDSH, FRV_INSN_NLDUH, FRV_INSN_NLD
+ , FRV_INSN_NLDBF, FRV_INSN_NLDHF, FRV_INSN_NLDF, FRV_INSN_LDD
+ , FRV_INSN_LDDF, FRV_INSN_LDDC, FRV_INSN_NLDD, FRV_INSN_NLDDF
+ , FRV_INSN_LDQ, FRV_INSN_LDQF, FRV_INSN_LDQC, FRV_INSN_NLDQ
+ , FRV_INSN_NLDQF, FRV_INSN_LDSBU, FRV_INSN_LDUBU, FRV_INSN_LDSHU
+ , FRV_INSN_LDUHU, FRV_INSN_LDU, FRV_INSN_NLDSBU, FRV_INSN_NLDUBU
+ , FRV_INSN_NLDSHU, FRV_INSN_NLDUHU, FRV_INSN_NLDU, FRV_INSN_LDBFU
+ , FRV_INSN_LDHFU, FRV_INSN_LDFU, FRV_INSN_LDCU, FRV_INSN_NLDBFU
+ , FRV_INSN_NLDHFU, FRV_INSN_NLDFU, FRV_INSN_LDDU, FRV_INSN_NLDDU
+ , FRV_INSN_LDDFU, FRV_INSN_LDDCU, FRV_INSN_NLDDFU, FRV_INSN_LDQU
+ , FRV_INSN_NLDQU, FRV_INSN_LDQFU, FRV_INSN_LDQCU, FRV_INSN_NLDQFU
+ , FRV_INSN_LDSBI, FRV_INSN_LDSHI, FRV_INSN_LDI, FRV_INSN_LDUBI
+ , FRV_INSN_LDUHI, FRV_INSN_LDBFI, FRV_INSN_LDHFI, FRV_INSN_LDFI
+ , FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI, FRV_INSN_NLDUHI
+ , FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI, FRV_INSN_NLDFI
+ , FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI, FRV_INSN_NLDDFI
+ , FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQFI, FRV_INSN_STB
+ , FRV_INSN_STH, FRV_INSN_ST, FRV_INSN_STBF, FRV_INSN_STHF
+ , FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_RSTB, FRV_INSN_RSTH
+ , FRV_INSN_RST, FRV_INSN_RSTBF, FRV_INSN_RSTHF, FRV_INSN_RSTF
+ , FRV_INSN_STD, FRV_INSN_STDF, FRV_INSN_STDC, FRV_INSN_RSTD
+ , FRV_INSN_RSTDF, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC
+ , FRV_INSN_RSTQ, FRV_INSN_RSTQF, FRV_INSN_STBU, FRV_INSN_STHU
+ , FRV_INSN_STU, FRV_INSN_STBFU, FRV_INSN_STHFU, FRV_INSN_STFU
+ , FRV_INSN_STCU, FRV_INSN_STDU, FRV_INSN_STDFU, FRV_INSN_STDCU
+ , FRV_INSN_STQU, FRV_INSN_STQFU, FRV_INSN_STQCU, FRV_INSN_CLDSB
+ , FRV_INSN_CLDUB, FRV_INSN_CLDSH, FRV_INSN_CLDUH, FRV_INSN_CLD
+ , FRV_INSN_CLDBF, FRV_INSN_CLDHF, FRV_INSN_CLDF, FRV_INSN_CLDD
+ , FRV_INSN_CLDDF, FRV_INSN_CLDQ, FRV_INSN_CLDSBU, FRV_INSN_CLDUBU
+ , FRV_INSN_CLDSHU, FRV_INSN_CLDUHU, FRV_INSN_CLDU, FRV_INSN_CLDBFU
+ , FRV_INSN_CLDHFU, FRV_INSN_CLDFU, FRV_INSN_CLDDU, FRV_INSN_CLDDFU
+ , FRV_INSN_CLDQU, FRV_INSN_CSTB, FRV_INSN_CSTH, FRV_INSN_CST
+ , FRV_INSN_CSTBF, FRV_INSN_CSTHF, FRV_INSN_CSTF, FRV_INSN_CSTD
+ , FRV_INSN_CSTDF, FRV_INSN_CSTQ, FRV_INSN_CSTBU, FRV_INSN_CSTHU
+ , FRV_INSN_CSTU, FRV_INSN_CSTBFU, FRV_INSN_CSTHFU, FRV_INSN_CSTFU
+ , FRV_INSN_CSTDU, FRV_INSN_CSTDFU, FRV_INSN_STBI, FRV_INSN_STHI
+ , FRV_INSN_STI, FRV_INSN_STBFI, FRV_INSN_STHFI, FRV_INSN_STFI
+ , FRV_INSN_STDI, FRV_INSN_STDFI, FRV_INSN_STQI, FRV_INSN_STQFI
+ , FRV_INSN_SWAP, FRV_INSN_SWAPI, FRV_INSN_CSWAP, FRV_INSN_MOVGF
+ , FRV_INSN_MOVFG, FRV_INSN_MOVGFD, FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ
+ , FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF, FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD
+ , FRV_INSN_CMOVFGD, FRV_INSN_MOVGS, FRV_INSN_MOVSG, FRV_INSN_BRA
+ , FRV_INSN_BNO, FRV_INSN_BEQ, FRV_INSN_BNE, FRV_INSN_BLE
+ , FRV_INSN_BGT, FRV_INSN_BLT, FRV_INSN_BGE, FRV_INSN_BLS
+ , FRV_INSN_BHI, FRV_INSN_BC, FRV_INSN_BNC, FRV_INSN_BN
+ , FRV_INSN_BP, FRV_INSN_BV, FRV_INSN_BNV, FRV_INSN_FBRA
+ , FRV_INSN_FBNO, FRV_INSN_FBNE, FRV_INSN_FBEQ, FRV_INSN_FBLG
+ , FRV_INSN_FBUE, FRV_INSN_FBUL, FRV_INSN_FBGE, FRV_INSN_FBLT
+ , FRV_INSN_FBUGE, FRV_INSN_FBUG, FRV_INSN_FBLE, FRV_INSN_FBGT
+ , FRV_INSN_FBULE, FRV_INSN_FBU, FRV_INSN_FBO, FRV_INSN_BCTRLR
+ , FRV_INSN_BRALR, FRV_INSN_BNOLR, FRV_INSN_BEQLR, FRV_INSN_BNELR
+ , FRV_INSN_BLELR, FRV_INSN_BGTLR, FRV_INSN_BLTLR, FRV_INSN_BGELR
+ , FRV_INSN_BLSLR, FRV_INSN_BHILR, FRV_INSN_BCLR, FRV_INSN_BNCLR
+ , FRV_INSN_BNLR, FRV_INSN_BPLR, FRV_INSN_BVLR, FRV_INSN_BNVLR
+ , FRV_INSN_FBRALR, FRV_INSN_FBNOLR, FRV_INSN_FBEQLR, FRV_INSN_FBNELR
+ , FRV_INSN_FBLGLR, FRV_INSN_FBUELR, FRV_INSN_FBULLR, FRV_INSN_FBGELR
+ , FRV_INSN_FBLTLR, FRV_INSN_FBUGELR, FRV_INSN_FBUGLR, FRV_INSN_FBLELR
+ , FRV_INSN_FBGTLR, FRV_INSN_FBULELR, FRV_INSN_FBULR, FRV_INSN_FBOLR
+ , FRV_INSN_BCRALR, FRV_INSN_BCNOLR, FRV_INSN_BCEQLR, FRV_INSN_BCNELR
+ , FRV_INSN_BCLELR, FRV_INSN_BCGTLR, FRV_INSN_BCLTLR, FRV_INSN_BCGELR
+ , FRV_INSN_BCLSLR, FRV_INSN_BCHILR, FRV_INSN_BCCLR, FRV_INSN_BCNCLR
+ , FRV_INSN_BCNLR, FRV_INSN_BCPLR, FRV_INSN_BCVLR, FRV_INSN_BCNVLR
+ , FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR, FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR
+ , FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR, FRV_INSN_FCBULLR, FRV_INSN_FCBGELR
+ , FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR, FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR
+ , FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR, FRV_INSN_FCBULR, FRV_INSN_FCBOLR
+ , FRV_INSN_JMPL, FRV_INSN_CALLL, FRV_INSN_JMPIL, FRV_INSN_CALLIL
+ , FRV_INSN_CALL, FRV_INSN_RETT, FRV_INSN_REI, FRV_INSN_TRA
+ , FRV_INSN_TNO, FRV_INSN_TEQ, FRV_INSN_TNE, FRV_INSN_TLE
+ , FRV_INSN_TGT, FRV_INSN_TLT, FRV_INSN_TGE, FRV_INSN_TLS
+ , FRV_INSN_THI, FRV_INSN_TC, FRV_INSN_TNC, FRV_INSN_TN
+ , FRV_INSN_TP, FRV_INSN_TV, FRV_INSN_TNV, FRV_INSN_FTRA
+ , FRV_INSN_FTNO, FRV_INSN_FTNE, FRV_INSN_FTEQ, FRV_INSN_FTLG
+ , FRV_INSN_FTUE, FRV_INSN_FTUL, FRV_INSN_FTGE, FRV_INSN_FTLT
+ , FRV_INSN_FTUGE, FRV_INSN_FTUG, FRV_INSN_FTLE, FRV_INSN_FTGT
+ , FRV_INSN_FTULE, FRV_INSN_FTU, FRV_INSN_FTO, FRV_INSN_TIRA
+ , FRV_INSN_TINO, FRV_INSN_TIEQ, FRV_INSN_TINE, FRV_INSN_TILE
+ , FRV_INSN_TIGT, FRV_INSN_TILT, FRV_INSN_TIGE, FRV_INSN_TILS
+ , FRV_INSN_TIHI, FRV_INSN_TIC, FRV_INSN_TINC, FRV_INSN_TIN
+ , FRV_INSN_TIP, FRV_INSN_TIV, FRV_INSN_TINV, FRV_INSN_FTIRA
+ , FRV_INSN_FTINO, FRV_INSN_FTINE, FRV_INSN_FTIEQ, FRV_INSN_FTILG
+ , FRV_INSN_FTIUE, FRV_INSN_FTIUL, FRV_INSN_FTIGE, FRV_INSN_FTILT
+ , FRV_INSN_FTIUGE, FRV_INSN_FTIUG, FRV_INSN_FTILE, FRV_INSN_FTIGT
+ , FRV_INSN_FTIULE, FRV_INSN_FTIU, FRV_INSN_FTIO, FRV_INSN_BREAK
+ , FRV_INSN_MTRAP, FRV_INSN_ANDCR, FRV_INSN_ORCR, FRV_INSN_XORCR
+ , FRV_INSN_NANDCR, FRV_INSN_NORCR, FRV_INSN_ANDNCR, FRV_INSN_ORNCR
+ , FRV_INSN_NANDNCR, FRV_INSN_NORNCR, FRV_INSN_NOTCR, FRV_INSN_CKRA
+ , FRV_INSN_CKNO, FRV_INSN_CKEQ, FRV_INSN_CKNE, FRV_INSN_CKLE
+ , FRV_INSN_CKGT, FRV_INSN_CKLT, FRV_INSN_CKGE, FRV_INSN_CKLS
+ , FRV_INSN_CKHI, FRV_INSN_CKC, FRV_INSN_CKNC, FRV_INSN_CKN
+ , FRV_INSN_CKP, FRV_INSN_CKV, FRV_INSN_CKNV, FRV_INSN_FCKRA
+ , FRV_INSN_FCKNO, FRV_INSN_FCKNE, FRV_INSN_FCKEQ, FRV_INSN_FCKLG
+ , FRV_INSN_FCKUE, FRV_INSN_FCKUL, FRV_INSN_FCKGE, FRV_INSN_FCKLT
+ , FRV_INSN_FCKUGE, FRV_INSN_FCKUG, FRV_INSN_FCKLE, FRV_INSN_FCKGT
+ , FRV_INSN_FCKULE, FRV_INSN_FCKU, FRV_INSN_FCKO, FRV_INSN_CCKRA
+ , FRV_INSN_CCKNO, FRV_INSN_CCKEQ, FRV_INSN_CCKNE, FRV_INSN_CCKLE
+ , FRV_INSN_CCKGT, FRV_INSN_CCKLT, FRV_INSN_CCKGE, FRV_INSN_CCKLS
+ , FRV_INSN_CCKHI, FRV_INSN_CCKC, FRV_INSN_CCKNC, FRV_INSN_CCKN
+ , FRV_INSN_CCKP, FRV_INSN_CCKV, FRV_INSN_CCKNV, FRV_INSN_CFCKRA
+ , FRV_INSN_CFCKNO, FRV_INSN_CFCKNE, FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG
+ , FRV_INSN_CFCKUE, FRV_INSN_CFCKUL, FRV_INSN_CFCKGE, FRV_INSN_CFCKLT
+ , FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG, FRV_INSN_CFCKLE, FRV_INSN_CFCKGT
+ , FRV_INSN_CFCKULE, FRV_INSN_CFCKU, FRV_INSN_CFCKO, FRV_INSN_CJMPL
+ , FRV_INSN_CCALLL, FRV_INSN_ICI, FRV_INSN_DCI, FRV_INSN_ICEI
+ , FRV_INSN_DCEI, FRV_INSN_DCF, FRV_INSN_DCEF, FRV_INSN_WITLB
+ , FRV_INSN_WDTLB, FRV_INSN_ITLBI, FRV_INSN_DTLBI, FRV_INSN_ICPL
+ , FRV_INSN_DCPL, FRV_INSN_ICUL, FRV_INSN_DCUL, FRV_INSN_BAR
+ , FRV_INSN_MEMBAR, FRV_INSN_COP1, FRV_INSN_COP2, FRV_INSN_CLRGR
+ , FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA, FRV_INSN_COMMITGR
+ , FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA, FRV_INSN_FITOS
+ , FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI, FRV_INSN_FDITOS
+ , FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI, FRV_INSN_CFITOS
+ , FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI, FRV_INSN_FMOVS
+ , FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS, FRV_INSN_FNEGS
+ , FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS, FRV_INSN_FABSS
+ , FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS, FRV_INSN_FSQRTS
+ , FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS
+ , FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS, FRV_INSN_FMULS
+ , FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD, FRV_INSN_FMULD
+ , FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS, FRV_INSN_CFMULS
+ , FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS, FRV_INSN_NFMULS
+ , FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD, FRV_INSN_CFCMPS
+ , FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS, FRV_INSN_FMADDD
+ , FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS
+ , FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS, FRV_INSN_FMAS
+ , FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS, FRV_INSN_NFDMAS
+ , FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS, FRV_INSN_FMAD
+ , FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS, FRV_INSN_FDADDS
+ , FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS, FRV_INSN_FDSADS
+ , FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS
+ , FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS
+ , FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH
+ , FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND, FRV_INSN_MOR
+ , FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR, FRV_INSN_CMXOR
+ , FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI, FRV_INSN_MROTRI
+ , FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT, FRV_INSN_MCUTI
+ , FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH
+ , FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI, FRV_INSN_MDROTLI
+ , FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS, FRV_INSN_MQSATHS
+ , FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH, FRV_INSN_MABSHS
+ , FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS
+ , FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS
+ , FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS
+ , FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS
+ , FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS
+ , FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS, FRV_INSN_MMULHU
+ , FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS, FRV_INSN_CMMULHU
+ , FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU
+ , FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS, FRV_INSN_MMACHU
+ , FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS, FRV_INSN_CMMACHU
+ , FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU
+ , FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS
+ , FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS
+ , FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS
+ , FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW
+ , FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH
+ , FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH
+ , FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE
+ , FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1
  , FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG
  , FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
 } CGEN_INSN_TYPE;
diff --git a/gnu/usr.bin/binutils/opcodes/i370-dis.c b/gnu/usr.bin/binutils/opcodes/i370-dis.c
index 51c0ff1dd3e..0f04f27f6bb 100644
--- a/gnu/usr.bin/binutils/opcodes/i370-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/i370-dis.c
@@ -1,6 +1,5 @@
-
 /* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions
-   Copyright 1994, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 2000, 2003 Free Software Foundation, Inc.
    PowerPC version written by Ian Lance Taylor, Cygnus Support
    Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org>
 
@@ -30,9 +29,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 */
 
 int
-print_insn_i370 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
 {
   bfd_byte buffer[8];
   int status;
diff --git a/gnu/usr.bin/binutils/opcodes/i370-opc.c b/gnu/usr.bin/binutils/opcodes/i370-opc.c
index 376dd0eaac9..a045f727597 100644
--- a/gnu/usr.bin/binutils/opcodes/i370-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/i370-opc.c
@@ -1,5 +1,5 @@
 /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
-   Copyright 1994, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1994, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
    PowerPC version written by Ian Lance Taylor, Cygnus Support
    Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
 
@@ -36,12 +36,12 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
    file.  */
 
 /* Local insertion and extraction functions.  */
-static i370_insn_t insert_ss_b2  PARAMS (( i370_insn_t, long, const char **));
-static i370_insn_t insert_ss_d2  PARAMS (( i370_insn_t, long, const char **));
-static i370_insn_t insert_rxf_r3  PARAMS (( i370_insn_t, long, const char **));
-static long extract_ss_b2 PARAMS (( i370_insn_t, int *));
-static long extract_ss_d2 PARAMS (( i370_insn_t, int *));
-static long extract_rxf_r3 PARAMS (( i370_insn_t, int *));
+static i370_insn_t insert_ss_b2 (i370_insn_t, long, const char **);
+static i370_insn_t insert_ss_d2 (i370_insn_t, long, const char **);
+static i370_insn_t insert_rxf_r3 (i370_insn_t, long, const char **);
+static long extract_ss_b2 (i370_insn_t, int *);
+static long extract_ss_d2 (i370_insn_t, int *);
+static long extract_rxf_r3 (i370_insn_t, int *);
 
 
 /* The operands table.
@@ -229,57 +229,44 @@ const struct i370_operand i370_operands[] =
 
 /* The functions used to insert and extract complicated operands.  */
 
-/*ARGSUSED*/
 static i370_insn_t
-insert_ss_b2 (insn, value, errmsg)
-     i370_insn_t insn;
-     long value;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_ss_b2 (i370_insn_t insn, long value,
+	      const char **errmsg ATTRIBUTE_UNUSED)
 {
   insn.i[1] |= (value & 0xf) << 28;
   return insn;
 }
 
 static i370_insn_t
-insert_ss_d2 (insn, value, errmsg)
-     i370_insn_t insn;
-     long value;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_ss_d2 (i370_insn_t insn, long value,
+	      const char **errmsg ATTRIBUTE_UNUSED)
 {
   insn.i[1] |= (value & 0xfff) << 16;
   return insn;
 }
 
 static i370_insn_t
-insert_rxf_r3 (insn, value, errmsg)
-     i370_insn_t insn;
-     long value;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_rxf_r3 (i370_insn_t insn, long value,
+	       const char **errmsg ATTRIBUTE_UNUSED)
 {
   insn.i[1] |= (value & 0xf) << 28;
   return insn;
 }
 
 static long
-extract_ss_b2 (insn, invalid)
-     i370_insn_t insn;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
 {
   return (insn.i[1] >>28) & 0xf;
 }
 
 static long
-extract_ss_d2 (insn, invalid)
-     i370_insn_t insn;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
 {
   return (insn.i[1] >>16) & 0xfff;
 }
 
 static long
-extract_rxf_r3 (insn, invalid)
-     i370_insn_t insn;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
 {
   return (insn.i[1] >>28) & 0xf;
 }
@@ -831,45 +818,45 @@ const struct i370_opcode i370_opcodes[] = {
 { "xi",     4, {{SI(0x97,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
 
 /* S form instructions */
-{ "cfc",    4, {{S(0xb21a,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "csch",   4, {{S(0xb230,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "hsch",   4, {{S(0xb231,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "ipk",    4, {{S(0xb20b,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "lfpc",   4, {{S(0xb29d,0,0),    0}}, {{S_MASK, 	 0}}, IBF,  {S_D2, S_B2} },
-{ "lpsw",   4, {{S(0x8200,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "msch",   4, {{S(0xb232,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "pc",     4, {{S(0xb218,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "pcf",    4, {{S(0xb218,0,0),    0}}, {{S_MASK, 	 0}}, IPC,  {S_D2, S_B2} },
-{ "ptlb",   4, {{S(0xb20d,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "rchp",   4, {{S(0xb23b,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "rp",     4, {{S(0xb277,0,0),    0}}, {{S_MASK, 	 0}}, IRP,  {0} },
-{ "rsch",   4, {{S(0xb238,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "sac",    4, {{S(0xb219,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "sacf",   4, {{S(0xb279,0,0),    0}}, {{S_MASK, 	 0}}, ISA,  {S_D2, S_B2} },
-{ "sal",    4, {{S(0xb237,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "schm",   4, {{S(0xb23c,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {0} },
-{ "sck",    4, {{S(0xb204,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "sckc",   4, {{S(0xb206,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "spka",   4, {{S(0xb20a,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "spt",    4, {{S(0xb208,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "spx",    4, {{S(0xb210,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "srnm",   4, {{S(0xb299,0,0),    0}}, {{S_MASK, 	 0}}, IBF,  {S_D2, S_B2} },
-{ "ssch",   4, {{S(0xb233,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "ssm",    4, {{S(0x8000,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "stap",   4, {{S(0xb212,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stck",   4, {{S(0xb205,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stckc",  4, {{S(0xb207,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "stcps",  4, {{S(0xb23a,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stcrw",  4, {{S(0xb239,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stfpc",  4, {{S(0xb29c,0,0),    0}}, {{S_MASK, 	 0}}, IBF,  {S_D2, S_B2} },
-{ "stidp",  4, {{S(0xb202,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "stpt",   4, {{S(0xb209,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stpx",   4, {{S(0xb211,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "stsch",  4, {{S(0xb234,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "tpi",    4, {{S(0xb236,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
-{ "trap4",  4, {{S(0xb2ff,0,0),    0}}, {{S_MASK, 	 0}}, ITR,  {S_D2, S_B2} },
-{ "ts",     4, {{S(0x9300,0,0),    0}}, {{S_MASK, 	 0}}, I370, {S_D2, S_B2} },
-{ "tsch",   4, {{S(0xb235,0,0),    0}}, {{S_MASK, 	 0}}, IXA,  {S_D2, S_B2} },
+{ "cfc",    4, {{S(0xb21a,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "csch",   4, {{S(0xb230,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "hsch",   4, {{S(0xb231,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "ipk",    4, {{S(0xb20b,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "lfpc",   4, {{S(0xb29d,0,0),    0}}, {{S_MASK,	 0}}, IBF,  {S_D2, S_B2} },
+{ "lpsw",   4, {{S(0x8200,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "msch",   4, {{S(0xb232,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "pc",     4, {{S(0xb218,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "pcf",    4, {{S(0xb218,0,0),    0}}, {{S_MASK,	 0}}, IPC,  {S_D2, S_B2} },
+{ "ptlb",   4, {{S(0xb20d,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "rchp",   4, {{S(0xb23b,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "rp",     4, {{S(0xb277,0,0),    0}}, {{S_MASK,	 0}}, IRP,  {0} },
+{ "rsch",   4, {{S(0xb238,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "sac",    4, {{S(0xb219,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "sacf",   4, {{S(0xb279,0,0),    0}}, {{S_MASK,	 0}}, ISA,  {S_D2, S_B2} },
+{ "sal",    4, {{S(0xb237,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "schm",   4, {{S(0xb23c,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {0} },
+{ "sck",    4, {{S(0xb204,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "sckc",   4, {{S(0xb206,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "spka",   4, {{S(0xb20a,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "spt",    4, {{S(0xb208,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "spx",    4, {{S(0xb210,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "srnm",   4, {{S(0xb299,0,0),    0}}, {{S_MASK,	 0}}, IBF,  {S_D2, S_B2} },
+{ "ssch",   4, {{S(0xb233,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "ssm",    4, {{S(0x8000,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "stap",   4, {{S(0xb212,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stck",   4, {{S(0xb205,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stckc",  4, {{S(0xb207,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "stcps",  4, {{S(0xb23a,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stcrw",  4, {{S(0xb239,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stfpc",  4, {{S(0xb29c,0,0),    0}}, {{S_MASK,	 0}}, IBF,  {S_D2, S_B2} },
+{ "stidp",  4, {{S(0xb202,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "stpt",   4, {{S(0xb209,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stpx",   4, {{S(0xb211,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "stsch",  4, {{S(0xb234,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "tpi",    4, {{S(0xb236,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
+{ "trap4",  4, {{S(0xb2ff,0,0),    0}}, {{S_MASK,	 0}}, ITR,  {S_D2, S_B2} },
+{ "ts",     4, {{S(0x9300,0,0),    0}}, {{S_MASK,	 0}}, I370, {S_D2, S_B2} },
+{ "tsch",   4, {{S(0xb235,0,0),    0}}, {{S_MASK,	 0}}, IXA,  {S_D2, S_B2} },
 
 /* SS form instructions */
 { "ap",     6, {{SSH(0xfa,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
diff --git a/gnu/usr.bin/binutils/opcodes/i860-dis.c b/gnu/usr.bin/binutils/opcodes/i860-dis.c
index ba183ab3f70..d95c7e96f09 100644
--- a/gnu/usr.bin/binutils/opcodes/i860-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/i860-dis.c
@@ -1,5 +1,5 @@
 /* Disassembler for the i860.
-   Copyright 2000 Free Software Foundation, Inc.
+   Copyright 2000, 2003 Free Software Foundation, Inc.
 
    Contributed by Jason Eckhardt <jle@cygnus.com>.
 
@@ -37,15 +37,13 @@ static const char *const frnames[] =
   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
 
-/* Control/status register names (encoded as 0..5 in the instruction).  */
+/* Control/status register names (encoded as 0..11 in the instruction).
+   Registers bear, ccr, p0, p1, p2 and p3 are XP only.  */
 static const char *const crnames[] = 
- {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
+ {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
+  "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
 
 
-/* Prototypes.  */
-static int sign_ext		PARAMS((unsigned int, int)); 
-static void print_br_address	PARAMS((disassemble_info *, bfd_vma, long));
-
 
 /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth.  */
 #define BITWISE_OP(op)  ((op) == 0x30 || (op) == 0x31		\
@@ -58,9 +56,7 @@ static void print_br_address	PARAMS((disassemble_info *, bfd_vma, long));
 
 /* Sign extend N-bit number.  */
 static int
-sign_ext (x, n)
-     unsigned int x;
-     int n;
+sign_ext (unsigned int x, int n)
 {
   int t;
   t = x >> (n - 1);
@@ -72,10 +68,7 @@ sign_ext (x, n)
 /* Print a PC-relative branch offset.  VAL is the sign extended value
    from the branch instruction.  */
 static void
-print_br_address (info, memaddr, val)
-     disassemble_info *info;
-     bfd_vma memaddr;
-     long val;
+print_br_address (disassemble_info *info, bfd_vma memaddr, long val)
 {
 
   long adj = (long)memaddr + 4 + (val << 2);
@@ -94,9 +87,7 @@ print_br_address (info, memaddr, val)
 
 /* Print one instruction.  */
 int
-print_insn_i860 (memaddr, info)
-     bfd_vma memaddr;
-     disassemble_info *info;
+print_insn_i860 (bfd_vma memaddr, disassemble_info *info)
 {
   bfd_byte buff[4];
   unsigned int insn, i;
@@ -138,8 +129,11 @@ print_insn_i860 (memaddr, info)
       const char *s;
       int val;
 
-      /* If this a flop and its dual bit is set, prefix with 'd.'.  */ 	
-      if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200))
+      /* If this a flop (or a shrd) and its dual bit is set,
+         prefix with 'd.'.  */ 	
+      if (((insn & 0xfc000000) == 0x48000000
+           || (insn & 0xfc000000) == 0xb0000000)
+          && (insn & 0x200))
 	(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
       else
 	(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
@@ -187,7 +181,7 @@ print_insn_i860 (memaddr, info)
 	    /* Control register.  */
 	    case 'c':
 	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
-				     crnames[(insn >> 21) & 0x7]);
+				     crnames[(insn >> 21) & 0xf]);
 	      break;
 
 	    /* 16-bit immediate (sign extend, except for bitwise ops).  */
diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc.c b/gnu/usr.bin/binutils/opcodes/ia64-opc.c
index 9726381dd6a..fc90213a6b5 100644
--- a/gnu/usr.bin/binutils/opcodes/ia64-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/ia64-opc.c
@@ -1,5 +1,5 @@
 /* ia64-opc.c -- Functions to access the compacted opcode table
-   Copyright 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2003 Free Software Foundation, Inc.
    Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
 
    This file is part of GDB, GAS, and the GNU binutils.
@@ -25,19 +25,19 @@
 #include "ia64-asmtab.h"
 #include "ia64-asmtab.c"
 
-static void get_opc_prefix PARAMS ((const char **, char *));
-static short int find_string_ent PARAMS ((const char *));
-static short int find_main_ent PARAMS ((short int));
-static short int find_completer PARAMS ((short int, short int, const char *));
-static ia64_insn apply_completer PARAMS ((ia64_insn, int));
-static int extract_op_bits PARAMS ((int, int, int));
-static int extract_op PARAMS ((int, int *, unsigned int *));
-static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type));
-static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type));
+static void get_opc_prefix (const char **, char *);
+static short int find_string_ent (const char *);
+static short int find_main_ent (short int);
+static short int find_completer (short int, short int, const char *);
+static ia64_insn apply_completer (ia64_insn, int);
+static int extract_op_bits (int, int, int);
+static int extract_op (int, int *, unsigned int *);
+static int opcode_verify (ia64_insn, int, enum ia64_insn_type);
+static int locate_opcode_ent (ia64_insn, enum ia64_insn_type);
 static struct ia64_opcode *make_ia64_opcode
-  PARAMS ((ia64_insn, const char *, int, int));
+  (ia64_insn, const char *, int, int);
 static struct ia64_opcode *ia64_find_matching_opcode
-  PARAMS ((const char *, short int));
+  (const char *, short int);
 
 const struct ia64_templ_desc ia64_templ_desc[16] =
   {
@@ -65,9 +65,7 @@ const struct ia64_templ_desc ia64_templ_desc[16] =
    of the opcode, or at the NUL character. */
 
 static void
-get_opc_prefix (ptr, dest)
-     const char **ptr;
-     char *dest;
+get_opc_prefix (const char **ptr, char *dest)
 {
   char *c = strchr (*ptr, '.');
   if (c != NULL)
@@ -89,8 +87,7 @@ get_opc_prefix (ptr, dest)
    STR; return -1 if one does not exist. */
 
 static short
-find_string_ent (str)
-     const char *str;
+find_string_ent (const char *str)
 {
   short start = 0;
   short end = sizeof (ia64_strings) / sizeof (const char *);
@@ -124,8 +121,7 @@ find_string_ent (str)
    return -1 if one does not exist. */
 
 static short
-find_main_ent (nameindex)
-     short nameindex;
+find_main_ent (short nameindex)
 {
   short start = 0;
   short end = sizeof (main_table) / sizeof (struct ia64_main_table);
@@ -164,10 +160,7 @@ find_main_ent (nameindex)
    return -1 if one does not exist. */
 
 static short
-find_completer (main_ent, prev_completer, name)
-     short main_ent;
-     short prev_completer;
-     const char *name;
+find_completer (short main_ent, short prev_completer, const char *name)
 {
   short name_index = find_string_ent (name);
 
@@ -200,9 +193,7 @@ find_completer (main_ent, prev_completer, name)
    return the result. */
 
 static ia64_insn
-apply_completer (opcode, completer_index)
-     ia64_insn opcode;
-     int completer_index;
+apply_completer (ia64_insn opcode, int completer_index)
 {
   ia64_insn mask = completer_table[completer_index].mask;
   ia64_insn bits = completer_table[completer_index].bits;
@@ -220,10 +211,7 @@ apply_completer (opcode, completer_index)
    first byte in OP_POINTER.) */
 
 static int
-extract_op_bits (op_pointer, bitoffset, bits)
-     int op_pointer;
-     int bitoffset;
-     int bits;
+extract_op_bits (int op_pointer, int bitoffset, int bits)
 {
   int res = 0;
 
@@ -259,10 +247,7 @@ extract_op_bits (op_pointer, bitoffset, bits)
    state entry in bits is returned. */
 
 static int
-extract_op (op_pointer, opval, op)
-     int op_pointer;
-     int *opval;
-     unsigned int *op;
+extract_op (int op_pointer, int *opval, unsigned int *op)
 {
   int oplen = 5;
 
@@ -317,10 +302,7 @@ extract_op (op_pointer, opval, op)
    PLACE matches OPCODE and is of type TYPE. */
 
 static int
-opcode_verify (opcode, place, type)
-     ia64_insn opcode;
-     int place;
-     enum ia64_insn_type type;
+opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type)
 {
   if (main_table[place].opcode_type != type)
     {
@@ -364,9 +346,7 @@ opcode_verify (opcode, place, type)
    priority. */
 
 static int
-locate_opcode_ent (opcode, type)
-     ia64_insn opcode;
-     enum ia64_insn_type type;
+locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type)
 {
   int currtest[41];
   int bitpos[41];
@@ -545,11 +525,7 @@ locate_opcode_ent (opcode, type)
 /* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
 
 static struct ia64_opcode *
-make_ia64_opcode (opcode, name, place, depind)
-     ia64_insn opcode;
-     const char *name;
-     int place;
-     int depind;
+make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind)
 {
   struct ia64_opcode *res =
     (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode));
@@ -572,9 +548,7 @@ make_ia64_opcode (opcode, name, place, depind)
 /* Determine the ia64_opcode entry for the opcode specified by INSN
    and TYPE.  If a valid entry is not found, return NULL. */
 struct ia64_opcode *
-ia64_dis_opcode (insn, type)
-     ia64_insn insn;
-     enum ia64_insn_type type;
+ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type)
 {
   int disent = locate_opcode_ent (insn, type);
 
@@ -633,9 +607,7 @@ ia64_dis_opcode (insn, type)
    matches NAME.  Return NULL if one is not found. */
 
 static struct ia64_opcode *
-ia64_find_matching_opcode (name, place)
-     const char *name;
-     short place;
+ia64_find_matching_opcode (const char *name, short place)
 {
   char op[129];
   const char *suffix;
@@ -696,8 +668,7 @@ ia64_find_matching_opcode (name, place)
    release any resources used by the returned entry. */
 
 struct ia64_opcode *
-ia64_find_next_opcode (prev_ent)
-     struct ia64_opcode *prev_ent;
+ia64_find_next_opcode (struct ia64_opcode *prev_ent)
 {
   return ia64_find_matching_opcode (prev_ent->name,
 				    prev_ent->ent_index + 1);
@@ -710,8 +681,7 @@ ia64_find_next_opcode (prev_ent)
    release any resources used by the returned entry. */
 
 struct ia64_opcode *
-ia64_find_opcode (name)
-     const char *name;
+ia64_find_opcode (const char *name)
 {
   char op[129];
   const char *suffix;
@@ -741,16 +711,14 @@ ia64_find_opcode (name)
 
 /* Free any resources used by ENT. */
 void
-ia64_free_opcode (ent)
-     struct ia64_opcode *ent;
+ia64_free_opcode (struct ia64_opcode *ent)
 {
   free ((void *)ent->name);
   free (ent);
 }
 
 const struct ia64_dependency *
-ia64_find_dependency (index)
-  int index;
+ia64_find_dependency (int index)
 {
   index = DEP(index);
 
diff --git a/gnu/usr.bin/binutils/opcodes/ip2k-asm.c b/gnu/usr.bin/binutils/opcodes/ip2k-asm.c
index 6a1653b014b..593db9db03d 100644
--- a/gnu/usr.bin/binutils/opcodes/ip2k-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/ip2k-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -607,8 +607,7 @@ ip2k_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-ip2k_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -731,11 +730,10 @@ ip2k_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -873,12 +871,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -908,10 +905,10 @@ ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! ip2k_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -982,9 +979,7 @@ ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-ip2k_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+ip2k_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/ip2k-desc.c b/gnu/usr.bin/binutils/opcodes/ip2k-desc.c
index f8e493289fb..0ab2cc5fa44 100644
--- a/gnu/usr.bin/binutils/opcodes/ip2k-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/ip2k-desc.c
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] },
diff --git a/gnu/usr.bin/binutils/opcodes/ip2k-desc.h b/gnu/usr.bin/binutils/opcodes/ip2k-desc.h
index 84db7fb1cb0..11220263b5c 100644
--- a/gnu/usr.bin/binutils/opcodes/ip2k-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/ip2k-desc.h
@@ -225,7 +225,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/gnu/usr.bin/binutils/opcodes/ip2k-dis.c b/gnu/usr.bin/binutils/opcodes/ip2k-dis.c
index f33fcc05ff6..00e764ccced 100644
--- a/gnu/usr.bin/binutils/opcodes/ip2k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/ip2k-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -352,13 +351,12 @@ ip2k_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -378,13 +376,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -408,12 +405,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -427,17 +423,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -469,14 +464,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -500,12 +494,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -610,10 +603,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -652,9 +642,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_ip2k (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_ip2k (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/ip2k-ibld.c b/gnu/usr.bin/binutils/opcodes/ip2k-ibld.c
index 22e2d8dea6b..e0c53090517 100644
--- a/gnu/usr.bin/binutils/opcodes/ip2k-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/ip2k-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-asm.c b/gnu/usr.bin/binutils/opcodes/iq2000-asm.c
index 17b93eb2f40..62d03f857a6 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -385,15 +385,15 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
     case IQ2000_OPERAND_EXECODE :
       errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode);
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_F_INDEX, &fields->f_index);
+      break;
     case IQ2000_OPERAND_HI16 :
       errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm);
       break;
     case IQ2000_OPERAND_IMM :
       errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, &fields->f_imm);
       break;
-    case IQ2000_OPERAND_INDEX :
-      errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_INDEX, &fields->f_index);
-      break;
     case IQ2000_OPERAND_JMPTARG :
       {
         bfd_vma value;
@@ -477,9 +477,6 @@ iq2000_cgen_init_asm (cd)
   iq2000_cgen_init_ibld_table (cd);
   cd->parse_handlers = & iq2000_cgen_parse_handlers[0];
   cd->parse_operand = iq2000_cgen_parse_operand;
-#ifdef CGEN_ASM_INIT_HOOK
-CGEN_ASM_INIT_HOOK
-#endif
 }
 
 
@@ -496,8 +493,7 @@ CGEN_ASM_INIT_HOOK
    Returns NULL for success, an error message for failure.  */
 
 char * 
-iq2000_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -620,11 +616,10 @@ iq2000_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -762,12 +757,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -797,10 +791,10 @@ iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! iq2000_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -871,9 +865,7 @@ iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-iq2000_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-desc.c b/gnu/usr.bin/binutils/opcodes/iq2000-desc.c
index a30bf56b8bf..6c7f3b06b79 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-desc.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -23,7 +23,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #include "sysdep.h"
-#include <ctype.h>
 #include <stdio.h>
 #include <stdarg.h>
 #include "ansidecl.h"
@@ -33,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "iq2000-opc.h"
 #include "opintl.h"
 #include "libiberty.h"
+#include "xregex.h"
 
 /* Attributes.  */
 
@@ -105,7 +105,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
@@ -122,7 +122,7 @@ const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
 /* Instruction set variants.  */
 
 static const CGEN_ISA iq2000_cgen_isa_table[] = {
-  { "iq2000", 32, 32, 32, 32 },
+  { "iq2000", 32, 32, 23, 32 },
   { 0, 0, 0, 0, 0 }
 };
 
@@ -255,6 +255,9 @@ const CGEN_IFLD iq2000_cgen_ifld_table[] =
   { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
   { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
   { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
+  { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+  { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+  { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
   { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
   { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
   { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
@@ -295,21 +298,21 @@ const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
 
 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
 {
-    { 0, { (void *) &(iq2000_cgen_ifld_table[5])} },
-    { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
-    {0,{0}}
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
+    { 0, { (const PTR) 0 } }
 };
 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
 {
-    { 0, { (void *) &(iq2000_cgen_ifld_table[5])} },
-    { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
-    {0,{0}}
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
+    { 0, { (const PTR) 0 } }
 };
 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
 {
-    { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
-    { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
-    {0,{0}}
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
+    { 0, { (const PTR) 0 } }
 };
 
 /* The operand table.  */
@@ -329,133 +332,136 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
 {
 /* pc: program counter */
   { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[0])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } }, 
     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 /* rs: register Rs */
   { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* rt: register Rt */
   { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* rd: register Rd */
   { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[5])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* rd-rs: register Rd from Rs */
   { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
-    { 2, { (void *) &(IQ2000_F_RD_RS_MULTI_IFIELD[0])} }, 
+    { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 /* rd-rt: register Rd from Rt */
   { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
-    { 2, { (void *) &(IQ2000_F_RD_RT_MULTI_IFIELD[0])} }, 
+    { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 /* rt-rs: register Rt from Rs */
   { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
-    { 2, { (void *) &(IQ2000_F_RT_RS_MULTI_IFIELD[0])} }, 
+    { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } }, 
     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
 /* shamt: shift amount */
   { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[6])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* imm: immediate */
   { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* offset: pc-relative offset */
   { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[14])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } }, 
     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 /* baseoff: base register offset */
   { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* jmptarg: jump target */
   { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[12])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } }, 
     { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 /* mask: mask */
   { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[18])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* maskq10: iq10 mask */
   { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[19])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* maskl: mask left */
   { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[20])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* count: count */
   { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[15])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } }, 
     { 0, { (1<<MACH_BASE) } }  },
-/* index: index */
-  { "index", IQ2000_OPERAND_INDEX, HW_H_UINT, 8, 9,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[17])} }, 
+/* f-index: index */
+  { "f-index", IQ2000_OPERAND_F_INDEX, HW_H_UINT, 8, 9,
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* execode: execcode */
   { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[21])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* bytecount: byte count */
   { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[16])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cam-y: cam global opn y */
   { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[29])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cam-z: cam global mask z */
   { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[28])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cm-3func: CM 3 bit fn field */
   { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[30])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cm-4func: CM 4 bit fn field */
   { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[31])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cm-3z: CM 3 bit Z field */
   { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[32])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* cm-4z: CM 4 bit Z field */
   { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[33])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* base: base register */
   { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* maskr: mask right */
   { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[3])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* bitnum: bit number */
   { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[4])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* hi16: high 16 bit immediate */
   { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* lo16: 16 bit signed immediate, for low */
   { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* mlo16: negated 16 bit signed immediate */
   { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[11])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* jmptargq10: iq10 21-bit jump offset */
   { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
-    { 0, { (void *) &(iq2000_cgen_ifld_table[13])} }, 
+    { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } }, 
     { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, {0, {0}}, {0, {0}} }
+/* sentinel */
+  { 0, 0, 0, 0, 0,
+    { 0, { (const PTR) 0 } },
+    { 0, { 0 } } }
 };
 
 #undef A
@@ -1161,14 +1167,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
     IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
   },
-/* pkrlr1 $rt,$index,$count */
+/* pkrlr1 $rt,$count */
   {
-    IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
+    IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* pkrlr30 $rt,$index,$count */
+/* pkrlr30 $rt,$count */
   {
-    IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
+    IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
 /* rb $rd,$rt */
@@ -1176,14 +1182,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
     IQ2000_INSN_RB, "rb", "rb", 32,
     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
   },
-/* rbr1 $rt,$index,$count */
+/* rbr1 $rt,$count */
   {
-    IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
+    IQ2000_INSN_RBR1, "rbr1", "rbr1", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* rbr30 $rt,$index,$count */
+/* rbr30 $rt,$count */
   {
-    IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
+    IQ2000_INSN_RBR30, "rbr30", "rbr30", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
 /* rfe */
@@ -1196,14 +1202,14 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
     IQ2000_INSN_RX, "rx", "rx", 32,
     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
   },
-/* rxr1 $rt,$index,$count */
+/* rxr1 $rt,$count */
   {
-    IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
+    IQ2000_INSN_RXR1, "rxr1", "rxr1", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* rxr30 $rt,$index,$count */
+/* rxr30 $rt,$count */
   {
-    IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
+    IQ2000_INSN_RXR30, "rxr30", "rxr30", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
 /* sleep */
@@ -1261,24 +1267,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
     IQ2000_INSN_WBU, "wbu", "wbu", 32,
     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
   },
-/* wbr1 $rt,$index,$count */
+/* wbr1 $rt,$count */
   {
-    IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
+    IQ2000_INSN_WBR1, "wbr1", "wbr1", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wbr1u $rt,$index,$count */
+/* wbr1u $rt,$count */
   {
-    IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
+    IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wbr30 $rt,$index,$count */
+/* wbr30 $rt,$count */
   {
-    IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
+    IQ2000_INSN_WBR30, "wbr30", "wbr30", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wbr30u $rt,$index,$count */
+/* wbr30u $rt,$count */
   {
-    IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
+    IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
 /* wx $rd,$rt */
@@ -1291,24 +1297,24 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
     IQ2000_INSN_WXU, "wxu", "wxu", 32,
     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
   },
-/* wxr1 $rt,$index,$count */
+/* wxr1 $rt,$count */
   {
-    IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
+    IQ2000_INSN_WXR1, "wxr1", "wxr1", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wxr1u $rt,$index,$count */
+/* wxr1u $rt,$count */
   {
-    IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
+    IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wxr30 $rt,$index,$count */
+/* wxr30 $rt,$count */
   {
-    IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
+    IQ2000_INSN_WXR30, "wxr30", "wxr30", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
-/* wxr30u $rt,$index,$count */
+/* wxr30u $rt,$count */
   {
-    IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
+    IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 23,
     { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
   },
 /* ldw $rt,$lo16($base) */
@@ -2181,7 +2187,7 @@ iq2000_cgen_cpu_close (cd)
      CGEN_CPU_DESC cd;
 {
   unsigned int i;
-  CGEN_INSN *insns;
+  const CGEN_INSN *insns;
 
   if (cd->macro_insn_table.init_entries)
     {
@@ -2189,7 +2195,7 @@ iq2000_cgen_cpu_close (cd)
       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
 	{
 	  if (CGEN_INSN_RX ((insns)))
-	    regfree(CGEN_INSN_RX (insns));
+	    regfree (CGEN_INSN_RX (insns));
 	}
     }
 
@@ -2199,7 +2205,7 @@ iq2000_cgen_cpu_close (cd)
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
 	{
 	  if (CGEN_INSN_RX (insns))
-	    regfree(CGEN_INSN_RX (insns));
+	    regfree (CGEN_INSN_RX (insns));
 	}
     }
 
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-desc.h b/gnu/usr.bin/binutils/opcodes/iq2000-desc.h
index 584c3ded755..13b4f56a80b 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-desc.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -42,7 +42,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_INSN_LSB0_P 1
 
 /* Minimum size of any insn (in bytes).  */
-#define CGEN_MIN_INSN_SIZE 4
+#define CGEN_MIN_INSN_SIZE 3
 
 /* Maximum size of any insn (in bytes).  */
 #define CGEN_MAX_INSN_SIZE 4
@@ -255,7 +255,7 @@ typedef enum cgen_operand_type {
  , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
  , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
  , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
- , IQ2000_OPERAND_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
+ , IQ2000_OPERAND_F_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
  , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
  , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
  , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
@@ -273,7 +273,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
  , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
  , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-dis.c b/gnu/usr.bin/binutils/opcodes/iq2000-dis.c
index 49e01201dc6..c20e9788517 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-dis.c
@@ -4,7 +4,8 @@
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 - the resultant file is machine generated, cgen-dis.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
+Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and GDB, the GNU debugger.
 
@@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "dis-asm.h"
 #include "bfd.h"
 #include "symcat.h"
+#include "libiberty.h"
 #include "iq2000-desc.h"
 #include "iq2000-opc.h"
 #include "opintl.h"
@@ -39,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -127,15 +128,15 @@ iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case IQ2000_OPERAND_EXECODE :
       print_normal (cd, info, fields->f_excode, 0, pc, length);
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      print_normal (cd, info, fields->f_index, 0, pc, length);
+      break;
     case IQ2000_OPERAND_HI16 :
       print_normal (cd, info, fields->f_imm, 0, pc, length);
       break;
     case IQ2000_OPERAND_IMM :
       print_normal (cd, info, fields->f_imm, 0, pc, length);
       break;
-    case IQ2000_OPERAND_INDEX :
-      print_normal (cd, info, fields->f_index, 0, pc, length);
-      break;
     case IQ2000_OPERAND_JMPTARG :
       print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
       break;
@@ -213,13 +214,12 @@ iq2000_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -239,13 +239,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -269,12 +268,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -288,17 +286,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -330,14 +327,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -361,12 +357,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -471,10 +466,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -513,9 +505,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_iq2000 (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-ibld.c b/gnu/usr.bin/binutils/opcodes/iq2000-ibld.c
index 5a29228c08b..f0640f0774f 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-ibld.c
@@ -35,39 +35,38 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #include "opintl.h"
 #include "safe-ctype.h"
 
-#undef  min
+#undef min
 #define min(a,b) ((a) < (b) ? (a) : (b))
-#undef  max
+#undef max
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 /* Used by the ifield rtx function.  */
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
@@ -605,15 +607,15 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case IQ2000_OPERAND_EXECODE :
       errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer);
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer);
+      break;
     case IQ2000_OPERAND_HI16 :
       errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
       break;
     case IQ2000_OPERAND_IMM :
       errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer);
       break;
-    case IQ2000_OPERAND_INDEX :
-      errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer);
-      break;
     case IQ2000_OPERAND_JMPTARG :
       {
         long value = fields->f_jtarg;
@@ -788,15 +790,15 @@ iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case IQ2000_OPERAND_EXECODE :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode);
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index);
+      break;
     case IQ2000_OPERAND_HI16 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
       break;
     case IQ2000_OPERAND_IMM :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm);
       break;
-    case IQ2000_OPERAND_INDEX :
-      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index);
-      break;
     case IQ2000_OPERAND_JMPTARG :
       {
         long value;
@@ -961,15 +963,15 @@ iq2000_cgen_get_int_operand (cd, opindex, fields)
     case IQ2000_OPERAND_EXECODE :
       value = fields->f_excode;
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      value = fields->f_index;
+      break;
     case IQ2000_OPERAND_HI16 :
       value = fields->f_imm;
       break;
     case IQ2000_OPERAND_IMM :
       value = fields->f_imm;
       break;
-    case IQ2000_OPERAND_INDEX :
-      value = fields->f_index;
-      break;
     case IQ2000_OPERAND_JMPTARG :
       value = fields->f_jtarg;
       break;
@@ -1075,15 +1077,15 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields)
     case IQ2000_OPERAND_EXECODE :
       value = fields->f_excode;
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      value = fields->f_index;
+      break;
     case IQ2000_OPERAND_HI16 :
       value = fields->f_imm;
       break;
     case IQ2000_OPERAND_IMM :
       value = fields->f_imm;
       break;
-    case IQ2000_OPERAND_INDEX :
-      value = fields->f_index;
-      break;
     case IQ2000_OPERAND_JMPTARG :
       value = fields->f_jtarg;
       break;
@@ -1198,15 +1200,15 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value)
     case IQ2000_OPERAND_EXECODE :
       fields->f_excode = value;
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      fields->f_index = value;
+      break;
     case IQ2000_OPERAND_HI16 :
       fields->f_imm = value;
       break;
     case IQ2000_OPERAND_IMM :
       fields->f_imm = value;
       break;
-    case IQ2000_OPERAND_INDEX :
-      fields->f_index = value;
-      break;
     case IQ2000_OPERAND_JMPTARG :
       fields->f_jtarg = value;
       break;
@@ -1309,15 +1311,15 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
     case IQ2000_OPERAND_EXECODE :
       fields->f_excode = value;
       break;
+    case IQ2000_OPERAND_F_INDEX :
+      fields->f_index = value;
+      break;
     case IQ2000_OPERAND_HI16 :
       fields->f_imm = value;
       break;
     case IQ2000_OPERAND_IMM :
       fields->f_imm = value;
       break;
-    case IQ2000_OPERAND_INDEX :
-      fields->f_index = value;
-      break;
     case IQ2000_OPERAND_JMPTARG :
       fields->f_jtarg = value;
       break;
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-opc.c b/gnu/usr.bin/binutils/opcodes/iq2000-opc.c
index fe8cf641502..35ffdf0a213 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-opc.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -166,7 +166,7 @@ static const CGEN_IFMT ifmt_lulck = {
 };
 
 static const CGEN_IFMT ifmt_pkrlr1 = {
-  32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { F (F_INDEX) }, { 0 } }
+  23, 23, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_rfe = {
@@ -1070,16 +1070,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
     & ifmt_chkhdr, { 0x4c200007 }
   },
-/* pkrlr1 $rt,$index,$count */
+/* pkrlr1 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4fa00000 }
   },
-/* pkrlr30 $rt,$index,$count */
+/* pkrlr30 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4fe00000 }
   },
 /* rb $rd,$rt */
@@ -1088,16 +1088,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
     & ifmt_chkhdr, { 0x4c200004 }
   },
-/* rbr1 $rt,$index,$count */
+/* rbr1 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4f000000 }
   },
-/* rbr30 $rt,$index,$count */
+/* rbr30 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4f400000 }
   },
 /* rfe */
@@ -1112,16 +1112,16 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
     & ifmt_chkhdr, { 0x4c200006 }
   },
-/* rxr1 $rt,$index,$count */
+/* rxr1 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4f800000 }
   },
-/* rxr30 $rt,$index,$count */
+/* rxr30 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4fc00000 }
   },
 /* sleep */
@@ -1190,28 +1190,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
     & ifmt_chkhdr, { 0x4c200001 }
   },
-/* wbr1 $rt,$index,$count */
+/* wbr1 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4e000000 }
   },
-/* wbr1u $rt,$index,$count */
+/* wbr1u $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4e200000 }
   },
-/* wbr30 $rt,$index,$count */
+/* wbr30 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4e400000 }
   },
-/* wbr30u $rt,$index,$count */
+/* wbr30u $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4e600000 }
   },
 /* wx $rd,$rt */
@@ -1226,28 +1226,28 @@ static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } },
     & ifmt_chkhdr, { 0x4c200003 }
   },
-/* wxr1 $rt,$index,$count */
+/* wxr1 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4e800000 }
   },
-/* wxr1u $rt,$index,$count */
+/* wxr1u $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4ea00000 }
   },
-/* wxr30 $rt,$index,$count */
+/* wxr30 $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4ec00000 }
   },
-/* wxr30u $rt,$index,$count */
+/* wxr30u $rt,$count */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } },
+    { { MNEM, ' ', OP (RT), ',', OP (COUNT), 0 } },
     & ifmt_pkrlr1, { 0x4ee00000 }
   },
 /* ldw $rt,$lo16($base) */
diff --git a/gnu/usr.bin/binutils/opcodes/iq2000-opc.h b/gnu/usr.bin/binutils/opcodes/iq2000-opc.h
index 4dca525ffe1..1242cea67a0 100644
--- a/gnu/usr.bin/binutils/opcodes/iq2000-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/iq2000-opc.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
diff --git a/gnu/usr.bin/binutils/opcodes/m10300-dis.c b/gnu/usr.bin/binutils/opcodes/m10300-dis.c
index a8d4b510dcd..1d3637c704d 100644
--- a/gnu/usr.bin/binutils/opcodes/m10300-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/m10300-dis.c
@@ -26,7 +26,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
 				 unsigned long insn, unsigned int));
 
-#define HAVE_AM33 (info->mach == AM33)
+#define HAVE_AM33_2 (info->mach == AM33_2)
+#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2)
 #define HAVE_AM30 (info->mach == AM30)
 
 int
@@ -200,6 +201,9 @@ print_insn_mn10300 (memaddr, info)
 
       insn = bfd_getb32 (buffer);
       consume = 7;
+      /* Handle the 5-byte extended instruction codes.  */
+      if ((insn & 0xfff80000) == 0xfe800000)
+	consume = 5;
     }
 
   disassemble (memaddr, info, insn, consume);
@@ -237,6 +241,8 @@ disassemble (memaddr, info, insn, size)
 	mysize = 5;
       else if (op->format == FMT_D2)
 	mysize = 4;
+      else if (op->format == FMT_D3)
+	mysize = 5;
       else if (op->format == FMT_D4)
 	mysize = 6;
       else if (op->format == FMT_D6)
@@ -253,6 +259,7 @@ disassemble (memaddr, info, insn, size)
       if ((op->mask & insn) == op->opcode
 	  && size == (unsigned int) mysize
 	  && (op->machine == 0
+	      || (op->machine == AM33_2 && HAVE_AM33_2)
 	      || (op->machine == AM33 && HAVE_AM33)
 	      || (op->machine == AM30 && HAVE_AM30)))
 	{
@@ -343,6 +350,25 @@ disassemble (memaddr, info, insn, size)
 	      insn |= (temp & 0xffffff00) >> 8;
 	      extension = temp & 0xff;
 	    }
+	  else if (size == 5 && op->format == FMT_D3)
+	    {
+	      status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
+	      if (status != 0)
+		{
+		  (*info->memory_error_func) (status, memaddr, info);
+		  return;
+		}
+	      insn &= 0xffff0000;
+	      insn |= bfd_getl16 (buffer);
+
+	      status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
+	      if (status != 0)
+		{
+		  (*info->memory_error_func) (status, memaddr, info);
+		  return;
+		}
+	      extension = *(unsigned char *) buffer;
+	    }
 	  else if (size == 5)
 	    {
 	      unsigned long temp = 0;
@@ -498,6 +524,52 @@ disassemble (memaddr, info, insn, size)
 		  if ((operand->flags & MN10300_OPERAND_SIGNED) != 0)
 		    value = ((value & 0xffffff) ^ 0x800000) - 0x800000;
 		}
+	      else if ((operand->flags & (MN10300_OPERAND_FSREG
+					  | MN10300_OPERAND_FDREG)))
+		{
+		  /* See m10300-opc.c just before #define FSM0 for an
+		     explanation of these variables.  Note that
+		     FMT-implied shifts are not taken into account for
+		     FP registers.  */
+		  unsigned long mask_low, mask_high;
+		  int shl_low, shr_high, shl_high;
+
+		  switch (operand->bits)
+		    {
+		    case 5:
+		      /* Handle regular FP registers.  */
+		      if (operand->shift >= 0)
+			{
+			  /* This is an `m' register.  */
+			  shl_low = operand->shift;
+			  shl_high = 8 + (8 & shl_low) + (shl_low & 4) / 4;
+			}
+		      else
+			{
+			  /* This is an `n' register.  */
+			  shl_low = -operand->shift;
+			  shl_high = shl_low / 4;
+			}
+		      mask_low = 0x0f;
+		      mask_high = 0x10;
+		      shr_high = 4;
+		      break;
+
+		    case 3:
+		      /* Handle accumulators.  */
+		      shl_low = -operand->shift;
+		      shl_high = 0;
+		      mask_low = 0x03;
+		      mask_high = 0x04;
+		      shr_high = 2;
+		      break;
+
+		    default:
+		      abort ();
+		    }
+		  value = ((((insn >> shl_high) << shr_high) & mask_high)
+			   | ((insn >> shl_low) & mask_low));
+		}
 	      else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
 		{
 		  value = ((extension >> (operand->shift))
@@ -567,6 +639,15 @@ disassemble (memaddr, info, insn, size)
 		    (*info->fprintf_func) (info->stream, "xr%d", (int) value);
 		}
 
+	      else if ((operand->flags & MN10300_OPERAND_FSREG) != 0)
+		(*info->fprintf_func) (info->stream, "fs%d", (int) value);
+
+	      else if ((operand->flags & MN10300_OPERAND_FDREG) != 0)
+		(*info->fprintf_func) (info->stream, "fd%d", (int) value);
+
+	      else if ((operand->flags & MN10300_OPERAND_FPCR) != 0)
+		(*info->fprintf_func) (info->stream, "fpcr");
+
 	      else if ((operand->flags & MN10300_OPERAND_USP) != 0)
 		(*info->fprintf_func) (info->stream, "usp");
 
diff --git a/gnu/usr.bin/binutils/opcodes/m10300-opc.c b/gnu/usr.bin/binutils/opcodes/m10300-opc.c
index 84014e127c8..4082b29e051 100644
--- a/gnu/usr.bin/binutils/opcodes/m10300-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/m10300-opc.c
@@ -1,5 +1,5 @@
 /* Assemble Matsushita MN10300 instructions.
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2004 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -338,6 +338,85 @@ const struct mn10300_operand mn10300_operands[] = {
 #define SIMM4_6    (SIMM4_2+1)
   {4, 12, MN10300_OPERAND_SIGNED},
 
+#define FPCR      (SIMM4_6+1)
+  {0, 0, MN10300_OPERAND_FPCR},
+
+/* We call f[sd]m registers those whose most significant bit is stored
+ * within the opcode half-word, i.e., in a bit on the left of the 4
+ * least significant bits, and f[sd]n registers those whose most
+ * significant bit is stored at the end of the full word, after the 4
+ * least significant bits.  They're not numbered after their position
+ * in the mnemonic asm instruction, but after their position in the
+ * opcode word, i.e., depending on the amount of shift they need.
+ *
+ * The additional bit is shifted as follows: for `n' registers, it
+ * will be shifted by (|shift|/4); for `m' registers, it will be
+ * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
+ * specifications are only 3-bits long, the two least-significant bits
+ * are shifted by 16, and the most-significant bit is shifted by -2
+ * (i.e., it's stored in the least significant bit of the full
+ * word).  */
+
+/* fsm register in the first register operand position.  */
+#define FSM0      (FPCR+1)
+  {5, 0, MN10300_OPERAND_FSREG },
+
+/* fsm register in the second register operand position.  */
+#define FSM1      (FSM0+1)
+  {5, 4, MN10300_OPERAND_FSREG },
+
+/* fsm register in the third register operand position.  */
+#define FSM2      (FSM1+1)
+  {5, 8, MN10300_OPERAND_FSREG },
+
+/* fsm register in the fourth register operand position.  */
+#define FSM3      (FSM2+1)
+  {5, 12, MN10300_OPERAND_FSREG },
+
+/* fsn register in the first register operand position.  */
+#define FSN1      (FSM3+1)
+  {5, -4, MN10300_OPERAND_FSREG },
+
+/* fsn register in the second register operand position.  */
+#define FSN2      (FSN1+1)
+  {5, -8, MN10300_OPERAND_FSREG },
+
+/* fsm register in the third register operand position.  */
+#define FSN3      (FSN2+1)
+  {5, -12, MN10300_OPERAND_FSREG },
+
+/* fsm accumulator, in the fourth register operand position.  */
+#define FSACC     (FSN3+1)
+  {3, -16, MN10300_OPERAND_FSREG },
+
+/* fdm register in the first register operand position.  */
+#define FDM0      (FSACC+1)
+  {5, 0, MN10300_OPERAND_FDREG },
+
+/* fdm register in the second register operand position.  */
+#define FDM1      (FDM0+1)
+  {5, 4, MN10300_OPERAND_FDREG },
+
+/* fdm register in the third register operand position.  */
+#define FDM2      (FDM1+1)
+  {5, 8, MN10300_OPERAND_FDREG },
+
+/* fdm register in the fourth register operand position.  */
+#define FDM3      (FDM2+1)
+  {5, 12, MN10300_OPERAND_FDREG },
+
+/* fdn register in the first register operand position.  */
+#define FDN1      (FDM3+1)
+  {5, -4, MN10300_OPERAND_FDREG },
+
+/* fdn register in the second register operand position.  */
+#define FDN2      (FDN1+1)
+  {5, -8, MN10300_OPERAND_FDREG },
+
+/* fdn register in the third register operand position.  */
+#define FDN3      (FDN2+1)
+  {5, -12, MN10300_OPERAND_FDREG },
+
 } ; 
 
 #define MEM(ADDR) PAREN, ADDR, PAREN 
@@ -482,8 +561,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "mov",	0xfb080000,  0xffff0000,  0,    FMT_D7, AM33,	{SIMM8, RN02}},
 { "mov",	0xfd080000,  0xffff0000,  0,    FMT_D8, AM33,	{SIMM24, RN02}},
 { "mov",	0xfe080000,  0xffff0000,  0,    FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
-{ "mov",	0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,	{SIMM8, XRN02}},
-{ "mov",	0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,	{SIMM24, XRN02}},
+{ "mov",	0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,	{IMM8, XRN02}},
+{ "mov",	0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,	{IMM24, XRN02}},
 { "mov",	0xfef80000,  0xffff0000,  0,    FMT_D9, AM33,	{IMM32_HIGH8, XRN02}},
 { "mov",	0xfe0e0000,  0xffff0f00,  0,    FMT_D9, AM33,	{MEM(IMM32_HIGH8_MEM), RN2}},
 { "mov",	0xfe1e0000,  0xffff0f00,  0,    FMT_D9, AM33,	{RM2, MEM(IMM32_HIGH8_MEM)}},
@@ -810,14 +889,17 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "btst",	0xfbe90000,  0xffff0000,  0,    FMT_D7, AM33,	{IMM8, RN02}},
 { "btst",	0xfde90000,  0xffff0000,  0,    FMT_D8, AM33,	{IMM24, RN02}},
 { "btst",	0xfee90000,  0xffff0000,  0,    FMT_D9, AM33,	{IMM32_HIGH8, RN02}},
+{ "btst",	0xfe820000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
 { "btst",	0xfe020000,  0xffff0000,  0,    FMT_D5, 0,	{IMM8E, MEM(IMM32_LOWSHIFT8)}},
 { "btst",	0xfaf80000,  0xfffc0000,  0,    FMT_D2, 0, 	{IMM8, MEM2(SD8N_SHIFT8, AN0)}},
 
 { "bset",	0xf080,	     0xfff0,	  0,    FMT_D0, 0,	{DM1, MEM(AN0)}},
+{ "bset",	0xfe800000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
 { "bset",	0xfe000000,  0xffff0000,  0,    FMT_D5, 0,	{IMM8E, MEM(IMM32_LOWSHIFT8)}},
 { "bset",	0xfaf00000,  0xfffc0000,  0,    FMT_D2, 0,	{IMM8, MEM2(SD8N_SHIFT8, AN0)}},
 
 { "bclr",	0xf090,	     0xfff0,	  0,    FMT_D0, 0,	{DM1, MEM(AN0)}},
+{ "bclr",	0xfe810000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
 { "bclr",	0xfe010000,  0xffff0000,  0,    FMT_D5, 0,	{IMM8E, MEM(IMM32_LOWSHIFT8)}},
 { "bclr",	0xfaf40000,  0xfffc0000,  0,    FMT_D2, 0,	{IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 
@@ -889,6 +971,36 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "lra",	0xda,	     0xff,	  0,    FMT_S0, 0,	{UNUSED}},
 { "setlb",	0xdb,	     0xff,	  0,    FMT_S0, 0,	{UNUSED}},
 
+{ "fbeq",	0xf8d000,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbne",	0xf8d100,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbgt",	0xf8d200,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbge",	0xf8d300,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fblt",	0xf8d400,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fble",	0xf8d500,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbuo",	0xf8d600,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fblg",	0xf8d700,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbleg",	0xf8d800,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbug",	0xf8d900,    0xffff00,	  0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbuge",	0xf8da00,    0xffff00,    0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbul",	0xf8db00,    0xffff00,    0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbule",	0xf8dc00,    0xffff00,    0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+{ "fbue",	0xf8dd00,    0xffff00,    0,    FMT_D1, AM33_2,	{SD8N_PCREL}},
+
+{ "fleq",	0xf0d0,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flne",	0xf0d1,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flgt",	0xf0d2,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flge",	0xf0d3,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "fllt",	0xf0d4,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flle",	0xf0d5,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "fluo",	0xf0d6,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "fllg",	0xf0d7,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flleg",	0xf0d8,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flug",	0xf0d9,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "fluge",	0xf0da,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flul",	0xf0db,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flule",	0xf0dc,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+{ "flue",	0xf0dd,	     0xffff,	  0,    FMT_D0, AM33_2,	{UNUSED}},
+
 { "jmp",	0xf0f4,	     0xfffc,	  0,    FMT_D0, 0,	{PAREN,AN0,PAREN}},
 { "jmp",	0xcc0000,    0xff0000,    0,    FMT_S2, 0,	{IMM16_PCREL}},
 { "jmp",	0xdc000000,  0xff000000,  0,    FMT_S4, 0,	{IMM32_HIGH24}},
@@ -906,6 +1018,141 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "rtm",	0xf0ff,	     0xffff,	  0,    FMT_D0, 0,	{UNUSED}},
 { "nop",	0xcb,	     0xff,	  0,    FMT_S0, 0,	{UNUSED}},
 
+{ "dcpf",	0xf9a600,    0xffff0f,    0,	FMT_D6, AM33_2,  {MEM (RM2)}},
+{ "dcpf",	0xf9a700,    0xffffff,    0,	FMT_D6, AM33_2,  {MEM (SP)}},
+{ "dcpf",	0xfba60000,  0xffff00ff,  0,	FMT_D7, AM33_2,  {MEM2 (RI,RM0)}},
+{ "dcpf",	0xfba70000,  0xffff0f00,  0,	FMT_D7, AM33_2,  {MEM2 (SD8,RM2)}},
+{ "dcpf",	0xfda70000,  0xffff0f00,  0,    FMT_D8, AM33_2,  {MEM2 (SD24,RM2)}},
+{ "dcpf",	0xfe460000,  0xffff0f00,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8,RM2)}},
+
+{ "fmov",	0xf92000,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEM (RM2), FSM0}},
+{ "fmov",	0xf92200,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FSM0}},
+{ "fmov",	0xf92400,    0xfffef0,    0,    FMT_D6, AM33_2,  {MEM (SP), FSM0}},
+{ "fmov",	0xf92600,    0xfffe00,    0,    FMT_D6, AM33_2,  {RM2, FSM0}},
+{ "fmov",	0xf93000,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEM (RM0)}},
+{ "fmov",	0xf93100,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEMINC (RM0)}},
+{ "fmov",	0xf93400,    0xfffd0f,    0,    FMT_D6, AM33_2,  {FSM1, MEM (SP)}},
+{ "fmov",	0xf93500,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, RM0}},
+{ "fmov",	0xf94000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fmov",	0xf9a000,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEM (RM2), FDM0}},
+{ "fmov",	0xf9a200,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FDM0}},
+{ "fmov",	0xf9a400,    0xfffef1,    0,    FMT_D6, AM33_2,  {MEM (SP), FDM0}},
+{ "fmov",	0xf9b000,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEM (RM0)}},
+{ "fmov",	0xf9b100,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEMINC (RM0)}},
+{ "fmov",	0xf9b400,    0xfffd1f,    0,    FMT_D6, AM33_2,  {FDM1, MEM (SP)}},
+{ "fmov",	0xf9b500,    0xffff0f,    0,    FMT_D6, AM33_2,  {RM2, FPCR}},
+{ "fmov",	0xf9b700,    0xfffff0,    0,    FMT_D6, AM33_2,  {FPCR, RM0}},
+{ "fmov",	0xf9c000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fmov",	0xfb200000,  0xfffe0000,  0,    FMT_D7, AM33_2,	{MEM2 (SD8, RM2), FSM2}},
+{ "fmov",	0xfb220000,  0xfffe0000,  0,    FMT_D7, AM33_2,	{MEMINC2 (RM2, SIMM8), FSM2}},
+{ "fmov",	0xfb240000,  0xfffef000,  0,    FMT_D7, AM33_2,	{MEM2 (IMM8, SP), FSM2}},
+{ "fmov",	0xfb270000,  0xffff000d,  0,    FMT_D7, AM33_2,	{MEM2 (RI, RM0), FSN1}},
+{ "fmov",	0xfb300000,  0xfffd0000,  0,    FMT_D7, AM33_2,	{FSM3, MEM2 (SD8, RM0)}},
+{ "fmov",	0xfb310000,  0xfffd0000,  0,    FMT_D7, AM33_2,	{FSM3, MEMINC2 (RM0, SIMM8)}},
+{ "fmov",	0xfb340000,  0xfffd0f00,  0,    FMT_D7, AM33_2,	{FSM3, MEM2 (IMM8, SP)}},
+{ "fmov",	0xfb370000,  0xffff000d,  0,    FMT_D7, AM33_2,	{FSN1, MEM2(RI, RM0)}},
+  /* FIXME: the spec doesn't say the fd register must be even for the
+   * next two insns.  Assuming it was a mistake in the spec.  */
+{ "fmov",	0xfb470000,  0xffff001d,  0,    FMT_D7, AM33_2,	{MEM2 (RI, RM0), FDN1}},
+{ "fmov",	0xfb570000,  0xffff001d,  0,    FMT_D7, AM33_2,	{FDN1, MEM2(RI, RM0)}},
+  /* END of FIXME */
+{ "fmov",	0xfba00000,  0xfffe0100,  0,    FMT_D7, AM33_2,	{MEM2 (SD8, RM2), FDM2}},
+{ "fmov",	0xfba20000,  0xfffe0100,  0,    FMT_D7, AM33_2,	{MEMINC2 (RM2, SIMM8), FDM2}},
+{ "fmov",	0xfba40000,  0xfffef100,  0,    FMT_D7, AM33_2,	{MEM2 (IMM8, SP), FDM2}},
+{ "fmov",	0xfbb00000,  0xfffd1000,  0,    FMT_D7, AM33_2,	{FDM3, MEM2 (SD8, RM0)}},
+{ "fmov",	0xfbb10000,  0xfffd1000,  0,    FMT_D7, AM33_2,	{FDM3, MEMINC2 (RM0, SIMM8)}},
+{ "fmov",	0xfbb40000,  0xfffd1f00,  0,    FMT_D7, AM33_2,	{FDM3, MEM2 (IMM8, SP)}},
+{ "fmov",	0xfd200000,  0xfffe0000,  0,    FMT_D8, AM33_2,	{MEM2 (SIMM24, RM2), FSM2}},
+{ "fmov",	0xfd220000,  0xfffe0000,  0,    FMT_D8, AM33_2,	{MEMINC2 (RM2, SIMM24), FSM2}},
+{ "fmov",	0xfd240000,  0xfffef000,  0,    FMT_D8, AM33_2,	{MEM2 (IMM24, SP), FSM2}},
+{ "fmov",	0xfd300000,  0xfffd0000,  0,    FMT_D8, AM33_2,	{FSM3, MEM2 (SIMM24, RM0)}},
+{ "fmov",	0xfd310000,  0xfffd0000,  0,    FMT_D8, AM33_2,	{FSM3, MEMINC2 (RM0, SIMM24)}},
+{ "fmov",	0xfd340000,  0xfffd0f00,  0,    FMT_D8, AM33_2,	{FSM3, MEM2 (IMM24, SP)}},
+{ "fmov",	0xfda00000,  0xfffe0100,  0,    FMT_D8, AM33_2,	{MEM2 (SIMM24, RM2), FDM2}},
+{ "fmov",	0xfda20000,  0xfffe0100,  0,    FMT_D8, AM33_2,	{MEMINC2 (RM2, SIMM24), FDM2}},
+{ "fmov",	0xfda40000,  0xfffef100,  0,    FMT_D8, AM33_2,	{MEM2 (IMM24, SP), FDM2}},
+{ "fmov",	0xfdb00000,  0xfffd1000,  0,    FMT_D8, AM33_2,	{FDM3, MEM2 (SIMM24, RM0)}},
+{ "fmov",	0xfdb10000,  0xfffd1000,  0,    FMT_D8, AM33_2,	{FDM3, MEMINC2 (RM0, SIMM24)}},
+{ "fmov",	0xfdb40000,  0xfffd1f00,  0,    FMT_D8, AM33_2,	{FDM3, MEM2 (IMM24, SP)}},
+{ "fmov",	0xfdb50000,  0xffff0000,  0,    FMT_D4, AM33_2,	{IMM32, FPCR}},
+{ "fmov",	0xfe200000,  0xfffe0000,  0,    FMT_D9, AM33_2,	{MEM2 (IMM32_HIGH8, RM2), FSM2}},
+{ "fmov",	0xfe220000,  0xfffe0000,  0,    FMT_D9, AM33_2,	{MEMINC2 (RM2, IMM32_HIGH8), FSM2}},
+{ "fmov",	0xfe240000,  0xfffef000,  0,    FMT_D9, AM33_2,	{MEM2 (IMM32_HIGH8, SP), FSM2}},
+{ "fmov",	0xfe260000,  0xfffef000,  0,    FMT_D9, AM33_2,	{IMM32_HIGH8, FSM2}},
+{ "fmov",	0xfe300000,  0xfffd0000,  0,    FMT_D9, AM33_2,	{FSM3, MEM2 (IMM32_HIGH8, RM0)}},
+{ "fmov",	0xfe310000,  0xfffd0000,  0,    FMT_D9, AM33_2,	{FSM3, MEMINC2 (RM0, IMM32_HIGH8)}},
+{ "fmov",	0xfe340000,  0xfffd0f00,  0,    FMT_D9, AM33_2,	{FSM3, MEM2 (IMM32_HIGH8, SP)}},
+{ "fmov",	0xfe400000,  0xfffe0100,  0,    FMT_D9, AM33_2,	{MEM2 (IMM32_HIGH8, RM2), FDM2}},
+{ "fmov",	0xfe420000,  0xfffe0100,  0,    FMT_D9, AM33_2,	{MEMINC2 (RM2, IMM32_HIGH8), FDM2}},
+{ "fmov",	0xfe440000,  0xfffef100,  0,    FMT_D9, AM33_2,	{MEM2 (IMM32_HIGH8, SP), FDM2}},
+{ "fmov",	0xfe500000,  0xfffd1000,  0,    FMT_D9, AM33_2,	{FDM3, MEM2 (IMM32_HIGH8, RM0)}},
+{ "fmov",	0xfe510000,  0xfffd1000,  0,    FMT_D9, AM33_2,	{FDM3, MEMINC2 (RM0, IMM32_HIGH8)}},
+{ "fmov",	0xfe540000,  0xfffd1f00,  0,    FMT_D9, AM33_2,	{FDM3, MEM2 (IMM32_HIGH8, SP)}},
+
+  /* FIXME: these are documented in the instruction bitmap, but not in
+   * the instruction manual.  */
+{ "ftoi",	0xfb400000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "itof",	0xfb420000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "ftod",	0xfb520000,  0xffff0f15,  0,    FMT_D10,AM33_2,  {FSN3, FDN1}},
+{ "dtof",	0xfb560000,  0xffff1f05,  0,    FMT_D10,AM33_2,  {FDN3, FSN1}},
+  /* END of FIXME */
+
+{ "fabs",	0xfb440000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "fabs",	0xfbc40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
+{ "fabs",	0xf94400,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
+{ "fabs",	0xf9c400,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
+
+{ "fneg",	0xfb460000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "fneg",	0xfbc60000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
+{ "fneg",	0xf94600,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
+{ "fneg",	0xf9c600,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
+
+{ "frsqrt",	0xfb500000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "frsqrt",	0xfbd00000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
+{ "frsqrt",	0xf95000,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
+{ "frsqrt",	0xf9d000,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
+
+  /* FIXME: this is documented in the instruction bitmap, but not in
+   * the instruction manual.  */
+{ "fsqrt",	0xfb540000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
+{ "fsqrt",	0xfbd40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
+{ "fsqrt",	0xf95200,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
+{ "fsqrt",	0xf9d200,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
+  /* END of FIXME */
+
+{ "fcmp",	0xf95400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fcmp",	0xf9d400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fcmp",	0xfe350000,  0xfffd0f00,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3}},
+
+{ "fadd",	0xfb600000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
+{ "fadd",	0xfbe00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
+{ "fadd",	0xf96000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fadd",	0xf9e000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fadd",	0xfe600000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
+
+{ "fsub",	0xfb640000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
+{ "fsub",	0xfbe40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
+{ "fsub",	0xf96400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fsub",	0xf9e400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fsub",	0xfe640000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
+
+{ "fmul",	0xfb700000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
+{ "fmul",	0xfbf00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
+{ "fmul",	0xf97000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fmul",	0xf9f000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fmul",	0xfe700000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
+
+{ "fdiv",	0xfb740000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
+{ "fdiv",	0xfbf40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
+{ "fdiv",	0xf97400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
+{ "fdiv",	0xf9f400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
+{ "fdiv",	0xfe740000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
+
+{ "fmadd",	0xfb800000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
+{ "fmsub",	0xfb840000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
+{ "fnmadd",	0xfb900000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
+{ "fnmsub",	0xfb940000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
+
 /* UDF instructions.  */
 { "udf00",	0xf600,	     0xfff0,	  0,    FMT_D0, 0,	{DM1, DN0}},
 { "udf00",	0xf90000,    0xfffc00,    0,    FMT_D1, 0,	{SIMM8, DN0}},
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-asm.c b/gnu/usr.bin/binutils/opcodes/m32r-asm.c
index 4abe187b81f..87c33f04cd3 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-asm.c
@@ -4,7 +4,7 @@
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 - the resultant file is machine generated, cgen-asm.in isn't
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2004 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and GDB, the GNU debugger.
 
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -111,7 +111,10 @@ parse_hi16 (cd, strp, opindex, valuep)
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	value = (value >> 16) + (value & 0x8000 ? 1 : 0);
+        {
+          value = value + (value & 0x8000 ? 0x10000 : 0);
+          value >>= 16;
+        }
       *valuep = value;
       return errmsg;
     }
@@ -147,7 +150,11 @@ parse_slo16 (cd, strp, opindex, valuep)
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	value &= 0xffff;
+        {
+	  value &= 0xffff;
+          if (value & 0x8000)
+             value |= 0xffff0000;
+        }
       *valuep = value;
       return errmsg;
     }
@@ -310,12 +317,18 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
         fields->f_uimm24 = value;
       }
       break;
+    case M32R_OPERAND_UIMM3 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, &fields->f_uimm3);
+      break;
     case M32R_OPERAND_UIMM4 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
       break;
     case M32R_OPERAND_UIMM5 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
       break;
+    case M32R_OPERAND_UIMM8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, &fields->f_uimm8);
+      break;
     case M32R_OPERAND_ULO16 :
       errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
       break;
@@ -358,8 +371,7 @@ m32r_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-m32r_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+m32r_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -482,11 +494,10 @@ m32r_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -624,12 +635,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -659,10 +669,10 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! m32r_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -733,9 +743,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-m32r_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+m32r_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-desc.c b/gnu/usr.bin/binutils/opcodes/m32r-desc.c
index 30a071985bd..711aff03bb0 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
   { "base", MACH_BASE },
   { "m32r", MACH_M32R },
   { "m32rx", MACH_M32RX },
+  { "m32r2", MACH_M32R2 },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -65,6 +66,7 @@ static const CGEN_ATTR_ENTRY PIPE_attr[] =
   { "O", PIPE_O },
   { "S", PIPE_S },
   { "OS", PIPE_OS },
+  { "O_OS", PIPE_O_OS },
   { 0, 0 }
 };
 
@@ -118,11 +120,13 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
 };
 
@@ -138,6 +142,7 @@ static const CGEN_ISA m32r_cgen_isa_table[] = {
 static const CGEN_MACH m32r_cgen_mach_table[] = {
   { "m32r", "m32r", MACH_M32R, 0 },
   { "m32rx", "m32rx", MACH_M32RX, 0 },
+  { "m32r2", "m32r2", MACH_M32R2, 0 },
   { 0, 0, 0, 0 }
 };
 
@@ -180,6 +185,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
   { "bpc", 6, {0, {0}}, 0, 0 },
   { "bbpsw", 8, {0, {0}}, 0, 0 },
   { "bbpc", 14, {0, {0}}, 0, 0 },
+  { "evb", 5, {0, {0}}, 0, 0 },
   { "cr0", 0, {0, {0}}, 0, 0 },
   { "cr1", 1, {0, {0}}, 0, 0 },
   { "cr2", 2, {0, {0}}, 0, 0 },
@@ -201,7 +207,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 {
   & m32r_cgen_opval_cr_names_entries[0],
-  23,
+  24,
   0, 0, 0, 0, ""
 };
 
@@ -241,7 +247,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
+  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
@@ -273,8 +279,10 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
@@ -287,6 +295,7 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
   { 0, 0, 0, 0, 0, 0, {0, {0}} }
@@ -354,6 +363,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* uimm3: 3 bit unsigned number */
+  { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm4: 4 bit trap number */
   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 
@@ -362,6 +375,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* uimm8: 8 bit unsigned immediate */
+  { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
+    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
@@ -369,19 +386,19 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
 /* imm1: 1 bit immediate */
   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
+    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* accd: accumulator destination register */
   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* accs: accumulator source register */
   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* acc: accumulator reg (d) */
   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* hash: # prefix */
   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
@@ -564,12 +581,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* bcl.s $disp8 */
   {
     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bcl.l $disp24 */
   {
     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* bnc.s $disp8 */
   {
@@ -599,12 +616,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* bncl.s $disp8 */
   {
     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bncl.l $disp24 */
   {
     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* cmp $src1,$src2 */
   {
@@ -629,12 +646,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* cmpeq $src1,$src2 */
   {
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* cmpz $src2 */
   {
     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* div $dr,$sr */
   {
@@ -656,20 +673,55 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
     M32R_INSN_REMU, "remu", "remu", 32,
     { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
+/* remh $dr,$sr */
+  {
+    M32R_INSN_REMH, "remh", "remh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remuh $dr,$sr */
+  {
+    M32R_INSN_REMUH, "remuh", "remuh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remb $dr,$sr */
+  {
+    M32R_INSN_REMB, "remb", "remb", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remub $dr,$sr */
+  {
+    M32R_INSN_REMUB, "remub", "remub", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divuh $dr,$sr */
+  {
+    M32R_INSN_DIVUH, "divuh", "divuh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divb $dr,$sr */
+  {
+    M32R_INSN_DIVB, "divb", "divb", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divub $dr,$sr */
+  {
+    M32R_INSN_DIVUB, "divub", "divub", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
 /* divh $dr,$sr */
   {
     M32R_INSN_DIVH, "divh", "divh", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* jc $sr */
   {
     M32R_INSN_JC, "jc", "jc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* jnc $sr */
   {
     M32R_INSN_JNC, "jnc", "jnc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* jl $sr */
   {
@@ -764,7 +816,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* machi $src1,$src2,$acc */
   {
     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* maclo $src1,$src2 */
   {
@@ -774,7 +826,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* maclo $src1,$src2,$acc */
   {
     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwhi $src1,$src2 */
   {
@@ -784,7 +836,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* macwhi $src1,$src2,$acc */
   {
     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
@@ -794,7 +846,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* macwlo $src1,$src2,$acc */
   {
     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
@@ -809,7 +861,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulhi $src1,$src2,$acc */
   {
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mullo $src1,$src2 */
   {
@@ -819,7 +871,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mullo $src1,$src2,$acc */
   {
     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwhi $src1,$src2 */
   {
@@ -829,7 +881,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulwhi $src1,$src2,$acc */
   {
     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
@@ -839,7 +891,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulwlo $src1,$src2,$acc */
   {
     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
@@ -854,7 +906,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfachi $dr,$accs */
   {
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfaclo $dr */
   {
@@ -864,7 +916,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfaclo $dr,$accs */
   {
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfacmi $dr */
   {
@@ -874,7 +926,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfacmi $dr,$accs */
   {
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfc $dr,$scr */
   {
@@ -889,7 +941,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvtachi $src1,$accs */
   {
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvtaclo $src1 */
   {
@@ -899,7 +951,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvtaclo $src1,$accs */
   {
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvtc $sr,$dcr */
   {
@@ -929,7 +981,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* rac $accd,$accs,$imm1 */
   {
     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach */
   {
@@ -939,7 +991,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* rach $accd,$accs,$imm1 */
   {
     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rte */
   {
@@ -954,7 +1006,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* sll $dr,$sr */
   {
     M32R_INSN_SLL, "sll", "sll", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
@@ -964,12 +1016,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* slli $dr,$uimm5 */
   {
     M32R_INSN_SLLI, "slli", "slli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sra $dr,$sr */
   {
     M32R_INSN_SRA, "sra", "sra", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
@@ -979,12 +1031,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* srai $dr,$uimm5 */
   {
     M32R_INSN_SRAI, "srai", "srai", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* srl $dr,$sr */
   {
     M32R_INSN_SRL, "srl", "srl", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
@@ -994,7 +1046,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* srli $dr,$uimm5 */
   {
     M32R_INSN_SRLI, "srli", "srli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* st $src1,@$src2 */
   {
@@ -1031,6 +1083,16 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
     { 0, { (1<<MACH_BASE), PIPE_O } }
   },
+/* sth $src1,@$src2+ */
+  {
+    M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
+/* stb $src1,@$src2+ */
+  {
+    M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
 /* st $src1,@-$src2 */
   {
     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
@@ -1064,57 +1126,82 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* satb $dr,$sr */
   {
     M32R_INSN_SATB, "satb", "satb", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* sath $dr,$sr */
   {
     M32R_INSN_SATH, "sath", "sath", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* sat $dr,$sr */
   {
     M32R_INSN_SAT, "sat", "sat", 32,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* pcmpbz $src2 */
   {
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* sadd */
   {
     M32R_INSN_SADD, "sadd", "sadd", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwu1 $src1,$src2 */
   {
     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* msblo $src1,$src2 */
   {
     M32R_INSN_MSBLO, "msblo", "msblo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwu1 $src1,$src2 */
   {
     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* maclh1 $src1,$src2 */
   {
     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* sc */
   {
     M32R_INSN_SC, "sc", "sc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* snc */
   {
     M32R_INSN_SNC, "snc", "snc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
+/* clrpsw $uimm8 */
+  {
+    M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+  },
+/* setpsw $uimm8 */
+  {
+    M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+  },
+/* bset $uimm3,@($slo16,$sr) */
+  {
+    M32R_INSN_BSET, "bset", "bset", 32,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bclr $uimm3,@($slo16,$sr) */
+  {
+    M32R_INSN_BCLR, "bclr", "bclr", 32,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* btst $uimm3,$sr */
+  {
+    M32R_INSN_BTST, "btst", "btst", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
   },
 };
 
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-desc.h b/gnu/usr.bin/binutils/opcodes/m32r-desc.h
index 85e22ee4dcd..ef61b696950 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/m32r-desc.h
@@ -38,6 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Selected cpu families.  */
 #define HAVE_CPU_M32RBF
 #define HAVE_CPU_M32RXF
+#define HAVE_CPU_M32R2F
 
 #define CGEN_INSN_LSB0_P 0
 
@@ -90,18 +91,19 @@ typedef enum gr_names {
 /* Enum declaration for .  */
 typedef enum cr_names {
   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
- , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
- , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
- , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
- , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
+ , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
+ , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
+ , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
+ , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
+ , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
 } CR_NAMES;
 
 /* Attributes.  */
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
+  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -112,6 +114,7 @@ typedef enum isa_attr {
 /* Enum declaration for parallel execution pipeline selection.  */
 typedef enum pipe_attr {
   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+ , PIPE_O_OS
 } PIPE_ATTR;
 
 /* Number of architecture variants.  */
@@ -138,11 +141,12 @@ typedef enum cgen_ifld_attr {
 typedef enum ifield_type {
   M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
  , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
- , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
- , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
- , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
- , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
- , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
+ , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
+ , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
+ , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
+ , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
+ , M32R_F_IMM1, M32R_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) M32R_F_MAX)
@@ -186,15 +190,16 @@ typedef enum cgen_operand_attr {
 typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
- , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
+ , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
+ , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
+ , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
+ , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
+ , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
+ , M32R_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 26
+#define MAX_OPERANDS 28
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 11
@@ -204,10 +209,10 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
- , CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
@@ -228,6 +233,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 
+extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
 
 
 
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-dis.c b/gnu/usr.bin/binutils/opcodes/m32r-dis.c
index 5688049ef16..46224626080 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -101,10 +100,13 @@ my_print_insn (cd, pc, info)
   char *buf = buffer;
   int status;
   int buflen = (pc & 3) == 0 ? 4 : 2;
+  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+  char *x;
 
   /* Read the base part of the insn.  */
 
-  status = (*info->read_memory_func) (pc, buf, buflen, info);
+  status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
+                                      buf, buflen, info);
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
@@ -112,22 +114,25 @@ my_print_insn (cd, pc, info)
     }
 
   /* 32 bit insn?  */
-  if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+  x = (big_p ? &buf[0] : &buf[3]);
+  if ((pc & 3) == 0 && (*x & 0x80) != 0)
     return print_insn (cd, pc, info, buf, buflen);
 
   /* Print the first insn.  */
   if ((pc & 3) == 0)
     {
+      buf += (big_p ? 0 : 2);
       if (print_insn (cd, pc, info, buf, 2) == 0)
 	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
-      buf += 2;
+      buf += (big_p ? 2 : -2);
     }
 
-  if (buf[0] & 0x80)
+  x = (big_p ? &buf[0] : &buf[1]);
+  if (*x & 0x80)
     {
       /* Parallel.  */
       (*info->fprintf_func) (info->stream, " || ");
-      buf[0] &= 0x7f;
+      *x &= 0x7f;
     }
   else
     (*info->fprintf_func) (info->stream, " -> ");
@@ -236,12 +241,18 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case M32R_OPERAND_UIMM24 :
       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
       break;
+    case M32R_OPERAND_UIMM3 :
+      print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
     case M32R_OPERAND_UIMM4 :
       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
       break;
     case M32R_OPERAND_UIMM5 :
       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
       break;
+    case M32R_OPERAND_UIMM8 :
+      print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
     case M32R_OPERAND_ULO16 :
       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
       break;
@@ -274,13 +285,12 @@ m32r_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -300,13 +310,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -330,12 +339,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -349,17 +357,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -391,14 +398,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -422,12 +428,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -532,10 +537,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -574,9 +576,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_m32r (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_m32r (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-ibld.c b/gnu/usr.bin/binutils/opcodes/m32r-ibld.c
index ef1ee0e0126..32224da6887 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
@@ -644,12 +646,18 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case M32R_OPERAND_UIMM24 :
       errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_UIMM3 :
+      errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_UIMM4 :
       errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
       break;
     case M32R_OPERAND_UIMM5 :
       errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_UIMM8 :
+      errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_ULO16 :
       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
       break;
@@ -777,12 +785,18 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case M32R_OPERAND_UIMM24 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
       break;
+    case M32R_OPERAND_UIMM3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
+      break;
     case M32R_OPERAND_UIMM4 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
       break;
     case M32R_OPERAND_UIMM5 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
       break;
+    case M32R_OPERAND_UIMM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
+      break;
     case M32R_OPERAND_ULO16 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
       break;
@@ -887,12 +901,18 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
     case M32R_OPERAND_UIMM24 :
       value = fields->f_uimm24;
       break;
+    case M32R_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
     case M32R_OPERAND_UIMM4 :
       value = fields->f_uimm4;
       break;
     case M32R_OPERAND_UIMM5 :
       value = fields->f_uimm5;
       break;
+    case M32R_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
     case M32R_OPERAND_ULO16 :
       value = fields->f_uimm16;
       break;
@@ -977,12 +997,18 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
     case M32R_OPERAND_UIMM24 :
       value = fields->f_uimm24;
       break;
+    case M32R_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
     case M32R_OPERAND_UIMM4 :
       value = fields->f_uimm4;
       break;
     case M32R_OPERAND_UIMM5 :
       value = fields->f_uimm5;
       break;
+    case M32R_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
     case M32R_OPERAND_ULO16 :
       value = fields->f_uimm16;
       break;
@@ -1075,12 +1101,18 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
     case M32R_OPERAND_UIMM24 :
       fields->f_uimm24 = value;
       break;
+    case M32R_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
     case M32R_OPERAND_UIMM4 :
       fields->f_uimm4 = value;
       break;
     case M32R_OPERAND_UIMM5 :
       fields->f_uimm5 = value;
       break;
+    case M32R_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
     case M32R_OPERAND_ULO16 :
       fields->f_uimm16 = value;
       break;
@@ -1161,12 +1193,18 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
     case M32R_OPERAND_UIMM24 :
       fields->f_uimm24 = value;
       break;
+    case M32R_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
     case M32R_OPERAND_UIMM4 :
       fields->f_uimm4 = value;
       break;
     case M32R_OPERAND_UIMM5 :
       fields->f_uimm5 = value;
       break;
+    case M32R_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
     case M32R_OPERAND_ULO16 :
       fields->f_uimm16 = value;
       break;
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opc.c b/gnu/usr.bin/binutils/opcodes/m32r-opc.c
index b60c1bf36e0..a18d5ccefa8 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-opc.c
@@ -30,6 +30,31 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "m32r-opc.h"
 #include "libiberty.h"
 
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (buf, value)
+     const char * buf ATTRIBUTE_UNUSED;
+     CGEN_INSN_INT value;
+{
+  unsigned int x;
+                                                                                
+  if (value & 0xffff0000) /* 32bit instructions */
+    value = (value >> 16) & 0xffff;
+                                                                                
+  x = (value>>8) & 0xf0;
+  if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+    return x;
+                                                                                
+  if (x == 0x70 || x == 0xf0)
+    return x | ((value>>8) & 0x0f);
+                                                                                
+  if (x == 0x30)
+    return x | ((value & 0x70) >> 4);
+  else
+    return x | ((value & 0xf0) >> 4);
+}
+                                                                                
+/* -- */
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
@@ -173,6 +198,18 @@ static const CGEN_IFMT ifmt_satb = {
   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_clrpsw = {
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bset = {
+  32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_btst = {
+  16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
+};
+
 #undef F
 
 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@@ -448,6 +485,48 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     & ifmt_div, { 0x90300000 }
   },
+/* remh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90200010 }
+  },
+/* remuh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90300010 }
+  },
+/* remb $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90200018 }
+  },
+/* remub $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90300018 }
+  },
+/* divuh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90100010 }
+  },
+/* divb $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90000018 }
+  },
+/* divub $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90100018 }
+  },
 /* divh $dr,$sr */
   {
     { 0, 0, 0, 0 },
@@ -898,6 +977,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x2060 }
   },
+/* sth $src1,@$src2+ */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+    & ifmt_cmp, { 0x2030 }
+  },
+/* stb $src1,@$src2+ */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+    & ifmt_cmp, { 0x2010 }
+  },
 /* st $src1,@-$src2 */
   {
     { 0, 0, 0, 0 },
@@ -1000,6 +1091,36 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, 0 } },
     & ifmt_nop, { 0x7501 }
   },
+/* clrpsw $uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM8), 0 } },
+    & ifmt_clrpsw, { 0x7200 }
+  },
+/* setpsw $uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM8), 0 } },
+    & ifmt_clrpsw, { 0x7100 }
+  },
+/* bset $uimm3,@($slo16,$sr) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+    & ifmt_bset, { 0xa0600000 }
+  },
+/* bclr $uimm3,@($slo16,$sr) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+    & ifmt_bset, { 0xa0700000 }
+  },
+/* btst $uimm3,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
+    & ifmt_btst, { 0xf0 }
+  },
 };
 
 #undef A
@@ -1187,7 +1308,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bc $disp24 */
   {
     -1, "bc24r", "bc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bl $disp8 */
   {
@@ -1197,17 +1318,17 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bl $disp24 */
   {
     -1, "bl24r", "bl", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bcl $disp8 */
   {
     -1, "bcl8r", "bcl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bcl $disp24 */
   {
     -1, "bcl24r", "bcl", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* bnc $disp8 */
   {
@@ -1217,7 +1338,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bnc $disp24 */
   {
     -1, "bnc24r", "bnc", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bra $disp8 */
   {
@@ -1227,17 +1348,17 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bra $disp24 */
   {
     -1, "bra24r", "bra", 32,
-    { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bncl $disp8 */
   {
     -1, "bncl8r", "bncl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bncl $disp24 */
   {
     -1, "bncl24r", "bncl", 32,
-    { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* ld $dr,@($sr) */
   {
@@ -1292,7 +1413,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* pop $dr */
   {
     -1, "pop", "pop", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldi $dr,$simm8 */
   {
@@ -1307,22 +1428,22 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* rac $accd */
   {
     -1, "rac-d", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rac $accd,$accs */
   {
     -1, "rac-ds", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach $accd */
   {
     -1, "rach-d", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach $accd,$accs */
   {
     -1, "rach-ds", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* st $src1,@($src2) */
   {
@@ -1357,7 +1478,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* push $src1 */
   {
     -1, "push", "push", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 };
 
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opc.h b/gnu/usr.bin/binutils/opcodes/m32r-opc.h
index 22e6924b060..5fe7106528b 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/m32r-opc.h
@@ -30,6 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #undef  CGEN_DIS_HASH_SIZE
 #define CGEN_DIS_HASH_SIZE 256
 #undef  CGEN_DIS_HASH
+#if 0
 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 #define CGEN_DIS_HASH(buffer, value) \
 (X (buffer) | \
@@ -37,6 +38,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#endif
 
 /* -- */
 /* Enum declaration for m32r instruction types.  */
@@ -51,37 +56,41 @@ typedef enum cgen_insn_type {
  , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
  , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
  , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
- , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
- , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
- , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
- , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
- , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
- , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
- , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
- , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
- , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
- , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
- , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
- , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
- , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
- , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
- , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
- , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
- , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
- , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
- , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
- , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
- , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
+ , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
+ , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
+ , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
+ , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
+ , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
+ , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
+ , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
+ , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
+ , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
+ , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
+ , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
+ , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
+ , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
+ , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
+ , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
+ , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
+ , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
+ , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
+ , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
+ , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
+ , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
+ , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
+ , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
+ , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
+ , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
+ , M32R_INSN_BTST
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
 #define CGEN_INSN_INVALID M32R_INSN_INVALID
 
 /* Total number of insns in table.  */
-#define MAX_INSNS ((int) M32R_INSN_SNC + 1)
+#define MAX_INSNS ((int) M32R_INSN_BTST + 1)
 
 /* This struct records data prior to insertion or after extraction.  */
 struct cgen_fields
@@ -97,8 +106,10 @@ struct cgen_fields
   long f_simm8;
   long f_simm16;
   long f_shift_op2;
+  long f_uimm3;
   long f_uimm4;
   long f_uimm5;
+  long f_uimm8;
   long f_uimm16;
   long f_uimm24;
   long f_hi16;
@@ -111,6 +122,7 @@ struct cgen_fields
   long f_accs;
   long f_accd;
   long f_bits67;
+  long f_bit4;
   long f_bit14;
   long f_imm1;
 };
diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opinst.c b/gnu/usr.bin/binutils/opcodes/m32r-opinst.c
index 5365d15a734..370aa7c0a8e 100644
--- a/gnu/usr.bin/binutils/opcodes/m32r-opinst.c
+++ b/gnu/usr.bin/binutils/opcodes/m32r-opinst.c
@@ -42,42 +42,42 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define COND_REF CGEN_OPINST_COND_REF
 
 static const CGEN_OPINST sfmt_empty_ops[] = {
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_add_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_add3_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_and3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_or3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addi_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addv_ops[] = {
@@ -85,7 +85,7 @@ static const CGEN_OPINST sfmt_addv_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addv3_ops[] = {
@@ -93,7 +93,7 @@ static const CGEN_OPINST sfmt_addv3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addx_ops[] = {
@@ -102,21 +102,21 @@ static const CGEN_OPINST sfmt_addx_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bc8_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bc24_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_beq_ops[] = {
@@ -124,14 +124,14 @@ static const CGEN_OPINST sfmt_beq_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_beqz_ops[] = {
   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bl8_ops[] = {
@@ -139,7 +139,7 @@ static const CGEN_OPINST sfmt_bl8_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bl24_ops[] = {
@@ -147,7 +147,7 @@ static const CGEN_OPINST sfmt_bl24_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bcl8_ops[] = {
@@ -156,7 +156,7 @@ static const CGEN_OPINST sfmt_bcl8_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bcl24_ops[] = {
@@ -165,53 +165,53 @@ static const CGEN_OPINST sfmt_bcl24_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bra8_ops[] = {
   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bra24_ops[] = {
   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmp_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmpi_ops[] = {
   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmpz_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_div_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jc_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jl_ops[] = {
@@ -219,20 +219,20 @@ static const CGEN_OPINST sfmt_jl_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jmp_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_ops[] = {
   { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_d_ops[] = {
@@ -240,14 +240,14 @@ static const CGEN_OPINST sfmt_ld_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldb_ops[] = {
   { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldb_d_ops[] = {
@@ -255,14 +255,14 @@ static const CGEN_OPINST sfmt_ldb_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldh_ops[] = {
   { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldh_d_ops[] = {
@@ -270,7 +270,7 @@ static const CGEN_OPINST sfmt_ldh_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_plus_ops[] = {
@@ -278,25 +278,25 @@ static const CGEN_OPINST sfmt_ld_plus_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld24_ops[] = {
   { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldi8_ops[] = {
   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldi16_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_lock_ops[] = {
@@ -304,7 +304,7 @@ static const CGEN_OPINST sfmt_lock_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_machi_ops[] = {
@@ -312,7 +312,7 @@ static const CGEN_OPINST sfmt_machi_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_machi_a_ops[] = {
@@ -320,82 +320,82 @@ static const CGEN_OPINST sfmt_machi_a_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulhi_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mv_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfachi_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfc_ops[] = {
   { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtachi_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtc_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_nop_ops[] = {
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rac_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
   { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rte_ops[] = {
@@ -407,34 +407,34 @@ static const CGEN_OPINST sfmt_rte_ops[] = {
   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_seth_ops[] = {
   { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sll3_ops[] = {
   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_slli_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_d_ops[] = {
@@ -442,14 +442,14 @@ static const CGEN_OPINST sfmt_st_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_stb_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_stb_d_ops[] = {
@@ -457,14 +457,14 @@ static const CGEN_OPINST sfmt_stb_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sth_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sth_d_ops[] = {
@@ -472,7 +472,7 @@ static const CGEN_OPINST sfmt_sth_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_plus_ops[] = {
@@ -480,7 +480,23 @@ static const CGEN_OPINST sfmt_st_plus_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sth_plus_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_plus_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_trap_ops[] = {
@@ -495,7 +511,7 @@ static const CGEN_OPINST sfmt_trap_ops[] = {
   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_unlock_ops[] = {
@@ -504,27 +520,27 @@ static const CGEN_OPINST sfmt_unlock_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_satb_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sat_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sadd_ops[] = {
   { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
   { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
   { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_macwu1_ops[] = {
@@ -532,19 +548,48 @@ static const CGEN_OPINST sfmt_macwu1_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulwu1_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sc_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_clrpsw_ops[] = {
+  { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
+  { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_setpsw_ops[] = {
+  { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
+  { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bset_ops[] = {
+  { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
+  { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+  { OUTPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_btst_ops[] = {
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
+  { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 #undef OP_ENT
@@ -600,6 +645,13 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
   & sfmt_jc_ops[0],
   & sfmt_jc_ops[0],
   & sfmt_jl_ops[0],
@@ -674,6 +726,8 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_sth_ops[0],
   & sfmt_sth_d_ops[0],
   & sfmt_st_plus_ops[0],
+  & sfmt_sth_plus_ops[0],
+  & sfmt_stb_plus_ops[0],
   & sfmt_st_plus_ops[0],
   & sfmt_add_ops[0],
   & sfmt_addv_ops[0],
@@ -691,6 +745,11 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_macwu1_ops[0],
   & sfmt_sc_ops[0],
   & sfmt_sc_ops[0],
+  & sfmt_clrpsw_ops[0],
+  & sfmt_setpsw_ops[0],
+  & sfmt_bset_ops[0],
+  & sfmt_bset_ops[0],
+  & sfmt_btst_ops[0],
 };
 
 /* Function to call before using the operand instance table.  */
diff --git a/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c b/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c
index cf42b6468c2..e2373cfd14b 100644
--- a/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c
@@ -1,5 +1,5 @@
 /* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@nerim.fr)
 
 This program is free software; you can redistribute it and/or modify
@@ -39,19 +39,14 @@ static const char *const reg_dst_table[] = {
 #define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4)
 
 /* Prototypes for local functions.  */
-static int read_memory
-  PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *));
-static int print_indexed_operand
-  PARAMS ((bfd_vma, struct disassemble_info *, int*, int, int, bfd_vma));
-static int print_insn
-  PARAMS ((bfd_vma, struct disassemble_info *, int));
+static int read_memory (bfd_vma, bfd_byte *, int, struct disassemble_info *);
+static int print_indexed_operand (bfd_vma, struct disassemble_info *,
+                                  int*, int, int, bfd_vma);
+static int print_insn (bfd_vma, struct disassemble_info *, int);
 
 static int
-read_memory (memaddr, buffer, size, info)
-     bfd_vma memaddr;
-     bfd_byte *buffer;
-     int size;
-     struct disassemble_info *info;
+read_memory (bfd_vma memaddr, bfd_byte* buffer, int size,
+             struct disassemble_info* info)
 {
   int status;
 
@@ -70,13 +65,9 @@ read_memory (memaddr, buffer, size, info)
 /* Read the 68HC12 indexed operand byte and print the corresponding mode.
    Returns the number of bytes read or -1 if failure.  */
 static int
-print_indexed_operand (memaddr, info, indirect, mov_insn, pc_offset, endaddr)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     int *indirect;
-     int mov_insn;
-     int pc_offset;
-     bfd_vma endaddr;
+print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info,
+                       int* indirect, int mov_insn, int pc_offset,
+                       bfd_vma endaddr)
 {
   bfd_byte buffer[4];
   int reg;
@@ -231,10 +222,7 @@ print_indexed_operand (memaddr, info, indirect, mov_insn, pc_offset, endaddr)
 /* Disassemble one instruction at address 'memaddr'.  Returns the number
    of bytes used by that instruction.  */
 static int
-print_insn (memaddr, info, arch)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
-     int arch;
+print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
 {
   int status;
   bfd_byte buffer[4];
@@ -324,7 +312,7 @@ print_insn (memaddr, info, arch)
     {
       int offset;
       int pc_src_offset;
-      int pc_dst_offset;
+      int pc_dst_offset = 0;
 
       if ((opcode->arch & arch) == 0)
 	continue;
@@ -717,7 +705,7 @@ print_insn (memaddr, info, arch)
 
   /* Opcode not recognized.  */
   if (format == M6811_OP_PAGE2 && arch & cpu6812
-      && ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff)))
+      && ((code >= 0x30 && code <= 0x39) || (code >= 0x40)))
     (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff);
 
   else if (format == M6811_OP_PAGE2)
@@ -738,17 +726,13 @@ print_insn (memaddr, info, arch)
 /* Disassemble one instruction at address 'memaddr'.  Returns the number
    of bytes used by that instruction.  */
 int
-print_insn_m68hc11 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_m68hc11 (bfd_vma memaddr, struct disassemble_info* info)
 {
   return print_insn (memaddr, info, cpu6811);
 }
 
 int
-print_insn_m68hc12 (memaddr, info)
-     bfd_vma memaddr;
-     struct disassemble_info *info;
+print_insn_m68hc12 (bfd_vma memaddr, struct disassemble_info* info)
 {
   return print_insn (memaddr, info, cpu6812);
 }
diff --git a/gnu/usr.bin/binutils/opcodes/mmix-opc.c b/gnu/usr.bin/binutils/opcodes/mmix-opc.c
index 76dc5d8745e..8d553e2299c 100644
--- a/gnu/usr.bin/binutils/opcodes/mmix-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/mmix-opc.c
@@ -1,5 +1,5 @@
 /* mmix-opc.c -- MMIX opcode table
-   Copyright (C) 2001 Free Software Foundation, Inc.
+   Copyright (C) 2001, 2003 Free Software Foundation, Inc.
    Written by Hans-Peter Nilsson (hp@bitrange.com)
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -227,7 +227,8 @@ const struct mmix_opcode mmix_opcodes[] =
    {"prego",	Z (0x9c),	OP (x_regs_z),		N},
 
    {"ldunc",	Z (0x96),	OP (regs_z_opt),	MO},
-   {"go",	Z (0x9e),	OP (regs_z_opt),	B},
+   {"go",	Z (GO_INSN_BYTE),
+				OP (regs_z_opt),	B},
 
    {"stb",	Z (0xa0),	OP (regs_z_opt),	MB},
    {"stt",	Z (0xa8),	OP (regs_z_opt),	MT},
@@ -251,7 +252,8 @@ const struct mmix_opcode mmix_opcodes[] =
    {"syncid",	Z (0xbc),	OP (x_regs_z),		M},
 
    {"stunc",	Z (0xb6),	OP (regs_z_opt),	MO},
-   {"pushgo",	Z (0xbe),	OP (pushgo),		J},
+   {"pushgo",	Z (PUSHGO_INSN_BYTE),
+				OP (pushgo),		J},
 
    /* Synonym for OR with a zero Z.  */
    {"set",	O (0xc1)
@@ -287,16 +289,20 @@ const struct mmix_opcode mmix_opcodes[] =
    {"ormh",	O (0xe9),	OP (reg_yz),		N},
 
    {"setml",	O (0xe2),	OP (reg_yz),		N},
-   {"setl",	O (0xe3),	OP (reg_yz),		N},
+   {"setl",	O (SETL_INSN_BYTE),
+				OP (reg_yz),		N},
    {"orml",	O (0xea),	OP (reg_yz),		N},
    {"orl",	O (0xeb),	OP (reg_yz),		N},
 
-   {"inch",	O (0xe4),	OP (reg_yz),		N},
-   {"incmh",	O (0xe5),	OP (reg_yz),		N},
+   {"inch",	O (INCH_INSN_BYTE),
+				OP (reg_yz),		N},
+   {"incmh",	O (INCMH_INSN_BYTE),
+				OP (reg_yz),		N},
    {"andnh",	O (0xec),	OP (reg_yz),		N},
    {"andnmh",	O (0xed),	OP (reg_yz),		N},
 
-   {"incml",	O (0xe6),	OP (reg_yz),		N},
+   {"incml",	O (INCML_INSN_BYTE),
+				OP (reg_yz),		N},
    {"incl",	O (0xe7),	OP (reg_yz),		N},
    {"andnml",	O (0xee),	OP (reg_yz),		N},
    {"andnl",	O (0xef),	OP (reg_yz),		N},
@@ -314,7 +320,8 @@ const struct mmix_opcode mmix_opcodes[] =
 
    {"geta",	Z (0xf4),	OP (regaddr),		N},
    {"sync",	O (0xfc),	OP (sync),		N},
-   {"swym",	O (0xfd),	OP (xyz_opt),		N},
+   {"swym",	O (SWYM_INSN_BYTE),
+				OP (xyz_opt),		N},
 
    {"put", Z (0xf6) | 0xff00,	OP (put),		N},
    {"get", O (0xfe) | 0xffe0,	OP (get),		N},
diff --git a/gnu/usr.bin/binutils/opcodes/msp430-dis.c b/gnu/usr.bin/binutils/opcodes/msp430-dis.c
index 767ffa472c1..1b5ffb1ec12 100644
--- a/gnu/usr.bin/binutils/opcodes/msp430-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/msp430-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble MSP430 instructions.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2004 Free Software Foundation, Inc.
    
    Contributed by Dmitry Diky <diwil@mail.ru>
         
@@ -491,6 +491,10 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
 	    {
 	      /* Absolute.  */
 	      dst = msp430dis_opcode (addr + 2, info);
+	      /* If the 'src' field is not the same as the dst
+		 then this is not an rla instruction.  */
+	      if (dst != msp430dis_opcode (addr + 4, info))
+		return 0;
 	      cmd_len += 4;
 	      *cycles = 6;
 	      sprintf (op1, "&0x%04x", PS (dst));
diff --git a/gnu/usr.bin/binutils/opcodes/openrisc-asm.c b/gnu/usr.bin/binutils/opcodes/openrisc-asm.c
index d47659b8c8f..ad977907d9a 100644
--- a/gnu/usr.bin/binutils/opcodes/openrisc-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/openrisc-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -60,7 +60,7 @@ long
 openrisc_sign_extend_16bit (value)
      long value;
 {
-  return (long) (short) value;
+  return ((value & 0xffff) ^ 0x8000) - 0x8000;
 }
 
 /* Handle hi().  */
@@ -74,15 +74,16 @@ parse_hi16 (cd, strp, opindex, valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
-  bfd_vma value;
+  unsigned long ret;
 
   if (**strp == '#')
     ++*strp;
 
   if (strncasecmp (*strp, "hi(", 3) == 0)
     {
-      *strp += 3;
+      bfd_vma value;
 
+      *strp += 3;
 #if 0
       errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
       if (errmsg != NULL)
@@ -92,23 +93,31 @@ parse_hi16 (cd, strp, opindex, valuep)
         errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
                                      &result_type, &value);
       if (**strp != ')')
-        return "missing `)'";
+        return _("missing `)'");
+
       ++*strp;
       if (errmsg == NULL
           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
         value >>= 16;
-      *valuep = (long) (short) value;
-
-      return errmsg;
+      ret = value;
     }
   else
     {
       if (**strp == '-')
-        errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value);
+	{
+	  long value;
+	  errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
+	  ret = value;
+	}
       else
-        errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value);
+	{
+	  unsigned long value;
+	  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
+	  ret = value;
+	}
     }
-  *valuep = (long) (short) (value & 0xffff);
+
+  *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
   return errmsg;
 }
 
@@ -123,15 +132,16 @@ parse_lo16 (cd, strp, opindex, valuep)
 {
   const char *errmsg;
   enum cgen_parse_operand_result result_type;
-  bfd_vma value;
+  unsigned long ret;
 
   if (**strp == '#')
     ++*strp;
 
   if (strncasecmp (*strp, "lo(", 3) == 0)
     {
-      *strp += 3;
+      bfd_vma value;
 
+      *strp += 3;
 #if 0 
       errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
       if (errmsg != NULL)
@@ -142,21 +152,28 @@ parse_lo16 (cd, strp, opindex, valuep)
         errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
                                      &result_type, &value);
       if (**strp != ')')
-        return "missing `)'";
-      ++*strp;
-      if (errmsg == NULL
-          && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-        value &= 0xffff;
-      *valuep = (long) (short) value;
+        return _("missing `)'");
 
-      return errmsg;
+      ++*strp;
+      ret = value;
     }
-
-  if (**strp == '-')
-    errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value);
   else
-    errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value);
-  *valuep = (long) (short) (value & 0xffff);
+    {
+      if (**strp == '-')
+	{
+	  long value;
+	  errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
+	  ret = value;
+	}
+      else
+	{
+	  unsigned long value;
+	  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
+	  ret = value;
+	}
+    }
+
+  *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
   return errmsg;
 }
 
@@ -277,8 +294,7 @@ openrisc_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-openrisc_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+openrisc_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -401,11 +417,10 @@ openrisc_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -543,12 +558,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -578,10 +592,10 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! openrisc_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -652,9 +666,7 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-openrisc_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+openrisc_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/openrisc-desc.c b/gnu/usr.bin/binutils/opcodes/openrisc-desc.c
index 6de9107f77b..989b1958648 100644
--- a/gnu/usr.bin/binutils/opcodes/openrisc-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/openrisc-desc.c
@@ -112,7 +112,7 @@ const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
diff --git a/gnu/usr.bin/binutils/opcodes/openrisc-desc.h b/gnu/usr.bin/binutils/opcodes/openrisc-desc.h
index d1edee2f51c..0c7df17b886 100644
--- a/gnu/usr.bin/binutils/opcodes/openrisc-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/openrisc-desc.h
@@ -223,7 +223,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/gnu/usr.bin/binutils/opcodes/openrisc-dis.c b/gnu/usr.bin/binutils/opcodes/openrisc-dis.c
index 5c4da5f3e94..6b721e213fb 100644
--- a/gnu/usr.bin/binutils/opcodes/openrisc-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/openrisc-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -161,13 +160,12 @@ openrisc_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -187,13 +185,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -217,12 +214,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -236,17 +232,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -278,14 +273,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -309,12 +303,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -419,10 +412,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -461,9 +451,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_openrisc (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_openrisc (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/openrisc-ibld.c b/gnu/usr.bin/binutils/opcodes/openrisc-ibld.c
index c2e5156e8d2..751ac07c3cf 100644
--- a/gnu/usr.bin/binutils/opcodes/openrisc-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/openrisc-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
diff --git a/gnu/usr.bin/binutils/opcodes/pj-opc.c b/gnu/usr.bin/binutils/opcodes/pj-opc.c
index 68ca05e20f5..218496ddbb0 100644
--- a/gnu/usr.bin/binutils/opcodes/pj-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/pj-opc.c
@@ -1,5 +1,5 @@
 /* pj-opc.c -- Definitions for picoJava opcodes.
-   Copyright 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2002 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
 
 This program is free software; you can redistribute it and/or modify
diff --git a/gnu/usr.bin/binutils/opcodes/po/Make-in b/gnu/usr.bin/binutils/opcodes/po/Make-in
index 0552db1feef..6176dbf78c3 100644
--- a/gnu/usr.bin/binutils/opcodes/po/Make-in
+++ b/gnu/usr.bin/binutils/opcodes/po/Make-in
@@ -24,6 +24,8 @@ gnulocaledir = $(prefix)/share/locale
 gettextsrcdir = $(prefix)/share/gettext/po
 subdir = po
 
+DESTDIR =
+
 INSTALL = @INSTALL@
 INSTALL_DATA = @INSTALL_DATA@
 MKINSTALLDIRS = @MKINSTALLDIRS@
@@ -111,9 +113,9 @@ install-data: install-data-@USE_NLS@
 install-data-no: all
 install-data-yes: all
 	if test -r $(MKINSTALLDIRS); then \
-	  $(MKINSTALLDIRS) $(datadir); \
+	  $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \
 	else \
-	  $(top_srcdir)/mkinstalldirs $(datadir); \
+	  $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \
 	fi
 	@catalogs='$(CATALOGS)'; \
 	for cat in $$catalogs; do \
@@ -123,7 +125,7 @@ install-data-yes: all
 	    *)     destdir=$(localedir);; \
 	  esac; \
 	  lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \
-	  dir=$$destdir/$$lang/LC_MESSAGES; \
+	  dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \
 	  if test -r $(MKINSTALLDIRS); then \
 	    $(MKINSTALLDIRS) $$dir; \
 	  else \
@@ -153,12 +155,12 @@ install-data-yes: all
 	done
 	if test "$(PACKAGE)" = "gettext"; then \
 	  if test -r $(MKINSTALLDIRS); then \
-	    $(MKINSTALLDIRS) $(gettextsrcdir); \
+	    $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \
 	  else \
-	    $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \
+	    $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \
 	  fi; \
 	  $(INSTALL_DATA) $(srcdir)/Makefile.in.in \
-			  $(gettextsrcdir)/Makefile.in.in; \
+			  $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \
 	else \
 	  : ; \
 	fi
@@ -171,12 +173,12 @@ uninstall:
 	for cat in $$catalogs; do \
 	  cat=`basename $$cat`; \
 	  lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \
-	  rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \
-	  rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \
-	  rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \
-	  rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \
+	  rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \
+	  rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \
+	  rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \
+	  rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \
 	done
-	rm -f $(gettextsrcdir)/po-Makefile.in.in
+	rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in
 
 check: all
 
diff --git a/gnu/usr.bin/binutils/opcodes/po/POTFILES.in b/gnu/usr.bin/binutils/opcodes/po/POTFILES.in
index 9a14a1daeb9..333c612130b 100644
--- a/gnu/usr.bin/binutils/opcodes/po/POTFILES.in
+++ b/gnu/usr.bin/binutils/opcodes/po/POTFILES.in
@@ -16,8 +16,9 @@ d10v-dis.c
 d10v-opc.c
 d30v-dis.c
 d30v-opc.c
-dis-buf.c
 disassemble.c
+dis-buf.c
+dis-init.c
 dlx-dis.c
 fr30-asm.c
 fr30-desc.c
@@ -48,12 +49,12 @@ ia64-dis.c
 ia64-gen.c
 ia64-opc-a.c
 ia64-opc-b.c
+ia64-opc.c
 ia64-opc-d.c
 ia64-opc-f.c
+ia64-opc.h
 ia64-opc-i.c
 ia64-opc-m.c
-ia64-opc.c
-ia64-opc.h
 ip2k-asm.c
 ip2k-desc.c
 ip2k-desc.h
@@ -87,9 +88,9 @@ m68k-opc.c
 m88k-dis.c
 mcore-dis.c
 mcore-opc.h
+mips16-opc.c
 mips-dis.c
 mips-opc.c
-mips16-opc.c
 mmix-dis.c
 mmix-opc.c
 ns32k-dis.c
@@ -111,11 +112,11 @@ ppc-opc.c
 s390-dis.c
 s390-mkopc.c
 s390-opc.c
-sh-dis.c
-sh-opc.h
 sh64-dis.c
 sh64-opc.c
 sh64-opc.h
+sh-dis.c
+sh-opc.h
 sparc-dis.c
 sparc-opc.c
 sysdep.h
@@ -137,6 +138,7 @@ xstormy16-dis.c
 xstormy16-ibld.c
 xstormy16-opc.c
 xstormy16-opc.h
+xtensa-dis.c
 z8k-dis.c
-z8k-opc.h
 z8kgen.c
+z8k-opc.h
diff --git a/gnu/usr.bin/binutils/opcodes/po/da.gmo b/gnu/usr.bin/binutils/opcodes/po/da.gmo
new file mode 100644
index 00000000000..42d668d1827
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/da.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/da.po b/gnu/usr.bin/binutils/opcodes/po/da.po
new file mode 100644
index 00000000000..36227adf2f7
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/da.po
@@ -0,0 +1,449 @@
+# Danish messages for opcodes.
+# Copyright (C) 2001 Free Software Foundation, Inc.
+# Keld Simonsen <keld@dkuug.dk>, 2002.
+# Christian Rose <menthos@menthos.com>, 2001.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.12.91\n"
+"POT-Creation-Date: 2002-07-23 15:55-0400\n"
+"PO-Revision-Date: 2002-09-07 19:35+0200\n"
+"Last-Translator: Keld Simonsen <keld@dkuug.dk>\n"
+"Language-Team: Danish <dansk@klid.dk>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=iso-8859-1\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "operanden for betinget hop ligger på skæv adresse"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "hopperådet ligger på skæv adresse"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Ugyldig limm-reference i sidste instruktion!\n"
+
+#: arm-dis.c:507
+msgid "<illegal precision>"
+msgstr "<ugyldig præcision>"
+
+#: arm-dis.c:1010
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Ukendt registernavn er angivet: %s\n"
+
+#: arm-dis.c:1017
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Ukendt disassembleralternativ: %s\n"
+
+#: arm-dis.c:1191
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n"
+"sammen med flaget -M:\n"
+
+#: avr-dis.c:118 avr-dis.c:128
+msgid "undefined"
+msgstr "udefineret"
+
+#: avr-dis.c:180
+msgid "Internal disassembler error"
+msgstr "Intern fejl i disassembleren"
+
+#: avr-dis.c:228
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "ukendt begrænsning \"%c\""
+
+#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195
+#: openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %ld)"
+
+#: cgen-asm.c:367
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operanden er uden for intervallet (%lu er ikke mellem %lu og %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<ukendt register %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Ukendt fejl %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adressen 0x%x ligger uden for tilladte grænser.\n"
+
+#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244
+#: xstormy16-asm.c:231
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Ukendt felt %d ved tolkning.\n"
+
+#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294
+#: xstormy16-asm.c:281
+msgid "missing mnemonic in syntax string"
+msgstr "Mangler mnemonic i syntaksstreng"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781
+#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434
+#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417
+#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610
+msgid "unrecognized instruction"
+msgstr "ukendt instruktion"
+
+#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477
+#: xstormy16-asm.c:464
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt \"%c\")"
+
+#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487
+#: xstormy16-asm.c:474
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt slut på instruktion)"
+
+#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515
+#: xstormy16-asm.c:502
+msgid "junk at end of line"
+msgstr "snavs ved slutning på linjen"
+
+#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622
+#: xstormy16-asm.c:609
+msgid "unrecognized form of instruction"
+msgstr "ukendt form af instruktion"
+
+#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634
+#: xstormy16-asm.c:621
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "fejlagtig instruktion \"%.50s...\""
+
+#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637
+#: xstormy16-asm.c:624
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "fejlagtig instruktion \"%.50s\""
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
+#: xstormy16-dis.c:39
+msgid "*unknown*"
+msgstr "*ukendt*"
+
+#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136
+#: xstormy16-dis.c:169
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Ukendt felt %d ved udskrift af instruktion.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166
+#: xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179
+#: xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operanden uden for intervallet (%lu ikke mellem 0 og %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633
+#: xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Ukendt felt %d ved konstruktion af instruktion.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735
+#: xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Ukendt felt %d ved afkodning af instruktion.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815
+#: xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Ukendt felt %d ved hentning af heltalsoperand.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875
+#: xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Ukendt felt %d ved hentning af vma-operand.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944
+#: xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Ukendt felt %d ved indstilling af heltalsoperand.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001
+#: xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Ukendt felt %d ved indstilling af vma-operand.\n"
+
+#: h8300-dis.c:385
+#, c-format
+msgid "Hmmmm %x"
+msgstr "Hmmmm %x"
+
+#: h8300-dis.c:396
+#, c-format
+msgid "Don't understand %x \n"
+msgstr "Forstår ikke %x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "kan ikke indsætte %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*ukendt*"
+
+#: i386-dis.c:1649
+msgid "<internal disassembler error>"
+msgstr "<intern fejl i disassembleren>"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "ukendt\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "ukendt\t0x%04lx"
+
+#: m10300-dis.c:685
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "ukendt\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<intern fejl i instruktionstabellen: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<funktionskode %d>"
+
+#: m88k-dis.c:255
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <disassemblerfejl: %08x>"
+
+#: mips-dis.c:337
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# intern fejl, ukendt modifikator(%c)"
+
+#: mips-dis.c:1209
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# intern disassembler-fejl, ukendt modifikator (%c)"
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Fejlagtig 'case' %d (%s) i %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Internt: ikke-fejltestet kode (test-tilfælde mangler): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(ukendt)"
+
+#: mmix-dis.c:517
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*ukendt operandstype: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:628
+msgid "$<undefined>"
+msgstr "$<udefineret>"
+
+#: ppc-opc.c:777 ppc-opc.c:810
+msgid "invalid conditional option"
+msgstr "ugyldigt betinget flag"
+
+#: ppc-opc.c:812
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "forsøg på at sætte y-bitten når modifikatoren + eller - blev brugt"
+
+#: ppc-opc.c:844 ppc-opc.c:896
+msgid "offset not a multiple of 4"
+msgstr "afsæt ikke et produkt af 4"
+
+#: ppc-opc.c:869
+msgid "offset not between -2048 and 2047"
+msgstr "afsæt ikke mellem -2048 og 2047"
+
+#: ppc-opc.c:894
+msgid "offset not between -8192 and 8191"
+msgstr "afsæt ikke mellem -8192 og 8191"
+
+#: ppc-opc.c:922
+msgid "ignoring least significant bits in branch offset"
+msgstr "ignorerer mindste betydende bit i afsæt for betinget hop"
+
+#: ppc-opc.c:956 ppc-opc.c:993
+msgid "illegal bitmask"
+msgstr "ugyldig bitmaske"
+
+#: ppc-opc.c:1066
+msgid "value out of range"
+msgstr "værdien er uden for intervallet"
+
+#: ppc-opc.c:1142
+msgid "index register in load range"
+msgstr "indeksregistret er i indlæsningsintervallet"
+
+#: ppc-opc.c:1158
+msgid "invalid register operand when updating"
+msgstr "ugyldig registeroperand ved opdatering"
+
+#. Mark as non-valid instruction
+#: sparc-dis.c:750
+msgid "unknown"
+msgstr "ukendt"
+
+#: sparc-dis.c:825
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Intern fejl:  dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:836
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:885
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:224
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "ukendt operandskiftning: %x\n"
+
+#: v850-dis.c:236
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "ukendt pop-register: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "forskydningsværdien er ikke indenfor intervallet og ligger ikke på lige adresse"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "forskydningsværdien er uden for intervallet"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "forskydningsværdien ligger ikke på lige adresse"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "umiddelbar værdi er uden for intervallet"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "værdien for betinget hop er ikke inden for intervallet og til et ulige afsæt"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "værdien for betinget hop er uden for intervallet"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "betinget hop til ulige afsæt"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "værdien for betinget hop er ikke indenfor intervallet og til et ulige afsæt"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "ugyldigt register for stakjustering"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "umiddelbar værdi er ikke indenfor intervallet og ikke lige"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "umiddelbar værdi skal være lige"
+
+#: xstormy16-asm.c:74
+msgid "Bad register in preincrement"
+msgstr "Forkert register i præinkrement"
+
+#: xstormy16-asm.c:79
+msgid "Bad register in postincrement"
+msgstr "Forkert register i postinkrement"
+
+#: xstormy16-asm.c:81
+msgid "Bad register name"
+msgstr "Forkert registernavn"
+
+#: xstormy16-asm.c:85
+msgid "Label conflicts with register name"
+msgstr "Etikette konflikter med registernavn"
+
+#: xstormy16-asm.c:89
+msgid "Label conflicts with `Rx'"
+msgstr "Etikette konflikter med 'Rx'"
+
+#: xstormy16-asm.c:91
+msgid "Bad immediate expression"
+msgstr "Forkert umiddelbart udtryk"
+
+#: xstormy16-asm.c:120
+msgid "Small operand was not an immediate number"
+msgstr "Lille operand var ikke et umiddelbart tal"
+
+#~ msgid "unrecognized keyword/register name"
+#~ msgstr "ukendt navn på nøgleord/register"
diff --git a/gnu/usr.bin/binutils/opcodes/po/de.gmo b/gnu/usr.bin/binutils/opcodes/po/de.gmo
new file mode 100644
index 00000000000..acd983f25e6
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/de.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/de.po b/gnu/usr.bin/binutils/opcodes/po/de.po
new file mode 100644
index 00000000000..e8028230f5a
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/de.po
@@ -0,0 +1,813 @@
+# Katalog für opcodes.
+# Copyright (C) 2002 Free Software Foundation, Inc.
+# Martin v. Löwis <martin@v.loewis.de>, 2002.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2004-02-28 12:30+0100\n"
+"Last-Translator: Roland Illig <roland.illig@gmx.de>\n"
+"Language-Team: German <de@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "Sprung-Operand ist nicht ausgerichtet (unaligned)."
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "Sprunghinweis ist nicht ausgerichtet (unaligned)."
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Ungültige limm-Referenz in der letzten Anweisung!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<ungültige Genauigkeit>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Unbekannte Registernamensmenge: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Unbekannte Disassembler-Option: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Die folgenden ARM-spezifischen Disassembleroptionen werden in Kombination\n"
+"mit dem Schalter »-M« unterstützt:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "undefiniert"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Interner Disassemblerfehler."
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "Unbekannte Einschränkung »%c«"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen %lu und %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<unbekanntes Register %d>"
+
+#  Can't happen.
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Unbekannter Fehler %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adresse 0x%x ist außerhalb des gültigen Bereichs.\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Unbekanntes Feld %d beim Parsen entdeckt.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "Fehlender Mnemonic im Syntaxstring"
+
+#  We couldn't parse it.
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "Unbekannter Befehl"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "Syntaxfehler (erwartetes Zeichen »%c«, gefunden »%c«)"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "Syntaxfehler (Zeichen »%c« erwartet, Befehlsende bekommen)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "Müll am Ende der Zeile"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "Unbekannte Befehlsform"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "Falscher Befehl »%.50s...«"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "Falscher Befehl »%.50s«"
+
+#  Default text to print if an instruction isn't recognized.
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*unbekannt*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Unbekanntes Feld %d beim Schreiben des Befehls.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen 0 und %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Unbekanntes Feld %d beim Erzeugen des Befehls.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Unbekannted Feld %d beim Decodieren des Befehls.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Unbekanntes Feld %d beim Holen des int-Operanden.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Unbekanntes Feld %d beim Setzen des int-Operanden.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "Die Registernummer muss gerade sein."
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "Ich verstehe »0x%x« nicht.\n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "Kann nicht mit »inserv %d« umgehen.\n"
+
+#  Couldn't understand anything.
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*unbekannt*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<interner Disassemblerfehler>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Fehler:"
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Warnung:"
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "Mehrfache Bemerkung »%s« nicht verarbeitet.\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "Kann »ia64-ic.tbl« nicht zum Lesen finden\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "Kann »%s« nicht zum Lesen finden\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr "Das letzte Format »%s« scheint strenger zu sein als »%s«.\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "Überlappendes Feld »%s->%s«.\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "Ãœberschreibe Bemerkung %d mit Bemerkung %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "Keine Ahnung, wie ich die Abhängigkeit »%% %s« angeben soll.\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "Keine Ahnung, wie ich die Abhängigkeit »# %s« angeben soll.\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] hat weder Terminale noch Unterklassen\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s hat weder Terminale noch Unterklassen\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "Kein Befehl ist dem Terminal-IC »%s [%s]« direkt zugeordnet"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "Kein Befehl ist dem Terminal-IC »%s« direkt zugeordnet.\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "Die Klasse »%s« wurde definiert, aber nicht benutzt.\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Warnung: Die Ressource »%s (%s)« hat keine »chks%s«.\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "Die Ressource »%s (%s)« hat keine Register\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC Bemerkung %d in Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC Bemerkung %d für Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "Opcode %s hat keine Klasse (Operanden %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "Kann nicht in das Verzeichnis »%s« wechseln, errno = %s\n"
+
+#  We've been passed a w.  Return with an error message so that
+#  cgen will try the next parsing option.
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "Schlüsselwort »W« ist im Operandenplatz »FR« ungültig."
+
+#  Invalid offset present.
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "»offset(IP)« ist keine gültige Form."
+
+#  Found something there in front of (DP) but it's out
+#  of range.
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) Offset außerhalb des gültigen Bereichs."
+
+#  Found something there in front of (SP) but it's out
+#  of range.
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) Offset außerhalb des gültigen Bereichs."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "Unerlaubte Benutzung von Klammern."
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "Operand außerhalb des gültigen Bereichs (1 bis 255)."
+
+#  Something is very wrong. opindex has to be one of the above.
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: Ungültiger Operatorindex."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Byteadresse benötigt -- muss gerade sein."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address: Gebe Symbol zurück. Sollte eigentlich ein Literal sein."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "Der Operand %operator muss ein Symbol sein."
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Versuch, ein gesetztes Bit von 0 zu bestimmen"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "Ein Direktoperand kann kein Register sein."
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "Direktoperand außerhalb des gültigen Bereichs."
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "21-Bit-Offset außerhalb des gültigen Bereichs"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "Fehlende »)«."
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "unbekannt\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "unbekannt\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "unbekannt\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<interner Fehler in der Opcode-Tabelle: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<Funktionscode %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <Disassemblierungsfehler: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# Interner Fehler, unvollständige Erweiterungsfolge (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# Interner Fehler, undefinierte Erweiterungsfolge (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# Interner Fehler, undefinierter Modifikator (%c)"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# Interner Fehler im Disassembler: unerkannter Modifikator (%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Die folgenden MIPS-spezifischen Disassembleroptionen werden zusammen\n"
+"mit dem Schalter »-M« unterstützt (mehrere Optionen sollten durch\n"
+"Kommata getrennt werden):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Gib GPR-Namen entsprechend des angegebenen ABI aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           disassembliert wird.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Gib FPR-Namen entsprechend des angegebenen ABI aus.\n"
+"                           Standard: numerisch.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Gib CP0-Registernamen entsprechend der angegebenen\n"
+"                           Architektur aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           disassembliert wird.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Gib HWR-Namen entsprechend der angegebenen\n"
+"                           Architektur aus.\n"
+"                           Standard: abhängig von der Binärdatei, die\n"
+"                           verarbeitet wird.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Gib GPR- und FPR-Namen entsprechend des\n"
+"                           angegebenen ABI aus.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Gib CP0-Register und HWR-Namen entsprechend der\n"
+"                           angegebenen Architektur aus.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Für die obigen Optionen werden die folgenden Werte für »ABI« unterstützt:\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Für die obigen Optionen werden die folgenden Werte für »ARCH« unterstützt:\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Interner Fehler: case %d (%s) in %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Intern: Nicht gedebuggter Code (Testfall fehlt): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(unbekannt)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "Unbekannter Operandentyp: %d*"
+
+#  I and Z are output operands and can`t be immediate
+#  * A is an address and we can`t have the address of
+#  * an immediate either. We don't know how much to increase
+#  * aoffsetp by since whatever generated this is broken
+#  * anyway!
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<undefiniert>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "Ungültige bedingte Option"
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "Versuch, das y-Bit zusammen mit dem Modifikator »+« oder »-« zu setzen."
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "Offset muss ein Vielfaches von 16 sein"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "Offset muss ein Vielfaches von 2 sein"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "Offset darf nicht größer als 62 sein"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "Offset muss ein Vielfaches von 4 sein"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "Offset darf nicht größer als 124 sein"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "Offset muss ein Vielfaches von 8 sein"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "Offset darf nicht größer als 248 sein"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "Offset muss im Bereich von -2048 bis 2047 liegen"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "Offset muss im Bereich von -8192 bis 8191 liegen"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "Ignoriere ungültige mfcr-Maske."
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "Ignoriere niedrigste Bits im Verzweigungsoffset"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "Ungültige Bitmaske"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "Wert außerhalb des gültigen Bereichs"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "Indexregister im Ladebereich (load range)"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "Die Operanden für das Quell- und Zielregister müssen verschieden sein"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "Ungültiger Registeroperand beim Aktualisieren"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "Der Zielregisteroperand muss gerade sein"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "Der Quellregisteroperand muss gerade sein"
+
+#  Mark as non-valid instruction.
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "unbekannt"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "Unbekannte Operandenverschiebung: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "Unbekanntes pop-Register: %d\n"
+
+#  The functions used to insert and extract complicated operands.
+#  Note: There is a conspiracy between these functions and
+#  v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#  containing the string 'out of range' will be ignored unless a
+#  specific command line option is given to GAS.
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "Der Abstandswert ist außerhalb des gültigen Bereichs und nicht ausgerichtet"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "Der Abstandswert ist außerhalb des fültigen Bereichs."
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "Der Abstandswert ist nicht ausgerichtet."
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "Direktwert außerhalb des gültigen Bereichs"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset."
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs."
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "Verzweigung auf ungeraden Offset"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset."
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "Ungültiges Register für Stackanpassung."
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "Direktwert außerhalb des gültigen Bereichs und nicht gerade"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "Der Direktoperand muss gerade sein."
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Ungültiges Register beim Pre-Increment"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Ungültiges Register beim Post-Increment"
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Falscher Registername."
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Sprungmarke verträgt sich nicht mit dem Registername"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Sprungmarke verträgt sich nicht mit »Rx«"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Ungültiger Direktausdruck"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Keine Verlagerung für kleine Direktwerte"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Kleiner Operand war keine Direktzahl."
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Operand muss ein Symbol sein"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Syntaxfehler: Kein abschließendes »)«"
diff --git a/gnu/usr.bin/binutils/opcodes/po/es.gmo b/gnu/usr.bin/binutils/opcodes/po/es.gmo
new file mode 100644
index 00000000000..8382c264ea7
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/es.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/es.po b/gnu/usr.bin/binutils/opcodes/po/es.po
new file mode 100644
index 00000000000..f94b9673c37
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/es.po
@@ -0,0 +1,791 @@
+# Mensajes en español para opcodes-2.14rel030712.
+# Copyright (C) 2002, 2003 Free Software Foundation, Inc.
+# Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002, 2003.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2003-07-14 18:57-0500\n"
+"Last-Translator: Cristian Othón Martínez Vera <cfuga@itam.mx>\n"
+"Language-Team: Spanish <es@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=ISO-8859-1\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "operando de ramificación sin alinear"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "pista de salto sin alinear"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "¡Referencia limm ilegal en la última instrucción!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<precisión ilegal>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Conjunto de nombres de registro no reconocido: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Opción de desensamblador no reconocida: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Las siguientes opciones de desensamblador específicas de ARM tienen soporte\n"
+"para su uso con el interruptor -M:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "sin definir"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Error interno del desensamblador"
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "restricción `%c' desconocida"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operando fuera de rango (%ld no está entre %ld y %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operando fuera de rango (%lu no está entre %lu y %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<registro %d desconocido>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Error desconocido %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "La dirección 0x%x está fuera de los límites.\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "No se reconoció el campo %d durante la decodificación.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "falta el mnemónico en la cadena sintáctica"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "instrucción no reconocida"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "error sintáctico (se esperaba el carácter `%c', se encontró `%c')"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "error sintáctico (se esperaba el carácter `%c', se encontró el final de la instrucción)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "basura al final de la línea"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "forma de instrucción no reconocida"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instrucción errónea `%.50s...'"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instrucción errónea `%.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*desconocida*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "No se reconoció el campo %d al mostrar insn.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operando fuera de rango (%ld no está entre %ld y %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operando fuera de rango (%lu no está entre 0 y %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "No se reconoció el campo %d al construir insn.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "No se reconoció el campo %d al decodificar insn.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "No se reconoció el campo %d al obtener el operando int.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "No se reconoció el campo %d al obtener el operando vma.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "No se reconoció el campo %d al establecer el operando int.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "No se reconoció el campo %d al establecer el operando vma.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "el número de registro debe ser par"
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "No se entiende 0x%x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "no se puede lidiar con insert %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*desconocido*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<error interno del desensamblador>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Error: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Aviso: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "la nota múltiple %s no se maneja\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "no se puede encontrar ia64-ic.tbl para lectura\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "no se puede encontrar %s para lectura\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"el formato más reciente '%s'\n"
+"parece más restrictivo que '%s'\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "campo solapado %s->%s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "se sobreescribe la nota %d con la nota %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "no se sabe cómo especificar la dependencia %% %s\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "No se sabe cómo especificar la dependencia # %s\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] no tiene terminales o sub-clases\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s no tiene terminales o sub-clases\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "no hay insns mapeadas directamente al IC terminal %s [%s]"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "no hay insns mapeadas directamente al IC terminal %s\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "se define la clase %s pero no se utiliza\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Aviso: el rsrc %s (%s) no tiene chks%s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "el rsrc %s (%s) no tiene registros\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "la nota IC %d en el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "la nota IC %d para el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "el código de operación %s no tiene clase (ops %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "no se puede cambiar el directorio a \"%s\", errno = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "la palabra clave W es inválida en la ranura del operando FR."
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "el desplazamiento(IP) no es una forma válida"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "desplazamiento (DP) fuera de rango."
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "desplazamiento (SP) fuera de rango."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "uso ilegal de paréntesis"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "operando fuera de rango (no está entre 1 y 255)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: índice de operador inválido."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Se requiere una dirección de byte. - debe ser par."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address devolvió un símbolo. Se requiere una literal."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "el operando %operator no es un símbolo"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Se intentó encontrar un índice de bit de 0"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "el valor inmediato no puede ser un registro"
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "el valor inmediato está fuera de rango"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "desplazamiento de 21-bit fuera de rango"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "falta un `)'"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "desconocido\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "desconocido\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "desconocido\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<error interno en la tabla de códigos de operación: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<código de función %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <error de desensamblador: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# error interno, secuencia de extensión incompleta (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# error interno, secuencia de extensión sin definir (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# error interno, modificador(%c) sin definir"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# error interno del desensamblador, modificador (%c) no reconocido"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Las siguientes opciones de desensamblador específicas de MIPS tienen soporte\n"
+"para su uso con el interruptor -M (las opciones múltiples se deben separar con comas):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Muestra los nombres GPR de acuerdo a la ABI especificada.\n"
+"                           Por omisión: basado en el binario a desensamblar.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Muestra los nombres FPR de acuerdo a la ABI especificada.\n"
+"                           Por omisión: numérico.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Muestra los nombres de registro CP0 de acuerdo a\n"
+"                           la arquitectura especificada.\n"
+"                           Por omisión: basado en el binario a desensamblar.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Muestra los nombres HWR de acuerdo a la arquitectura \n"
+"                           especificada.\n"
+"                           Por omisión: basado en el binario a desensamblar.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Muestra los nombres GPR y FPR de acuerdo a\n"
+"                           la ABI especificada.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Muestra el registro CP0 y los nombres HWR de acuerdo a\n"
+"                           la arquitectura especificada.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Para las opciones anteriores, se da soporte a los siguientes valores de \"ABI\":\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Para las opciones anteriores, se da soporte a los siguientes valores de \"ARCH\":\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Case %d erróneo (%s) en %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Interno: Código no depurado (falta el caso de prueba): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(desconocido)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*tipo de operandos operandos desconocido: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<sin definir>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "opción condicional inválida"
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "intento de establecer el bit y cuando se usaba el modificador + ó -"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "el desplazamiento no es un múltiplo de 16"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "el desplazamiento no es un múltiplo de 2"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "el desplazamiento es mayor que 62"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "el desplazamiento no es un múltiplo de 4"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "el desplazamiento es mayor que 124"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "el desplazamiento no es un múltiplo de 8"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "el desplazamiento es mayor que 248"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "el desplazamiento no está entre -2048 y 2047"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "el desplazamiento no está entre -8192 y 8191"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "se ignora la máscara mfcr inválida"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "ignorando los bits menos significativos en el desplazamiento de la rama"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "máscara de bits ilegal"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "valor fuera de rango"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "registro índice en el rango de carga"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "los operandos de registros fuente y objetivo deben ser diferentes"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "operando de registro inválido mientras se actualizaba"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "el operando de registro objetivo debe ser par"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "el operando de registro fuente debe ser par"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "desconocida"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Error interno:  sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Error interno: sparc-opcode.h erróneo: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "operando de desplazamiento desconocido: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "registro pop desconocido: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "el valor de desubicación no está en el rango y no está alineado"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "el valor de desubicación está fuera de rango"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "el valor de desubicación no está alineado"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "el valor inmediato está fuera de rango"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "el valor de ramificación está fuera de rango"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "ramificación a un desplazamiento impar"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "registro inválido para el ajuste de la pila"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "el valor inmediato no está en rango y no es par"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "el valor inmediato debe ser par"
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Registro erróneo en el preincremento"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Registro erróneo en el postincremento"
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Nombre de registro erróneo"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "La etiqueta tiene conflictos con el nombre de registro"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "La etiqueta tiene conflictos con `Rx'"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Expresión inmediata errónea"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "No hay reubicaciones para inmediatos small"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "El operando small no era un número inmediato"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "El operando no es un símbolo"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Error sintáctico: No hay ')' al final"
+
+#~ msgid "unrecognized keyword/register name"
+#~ msgstr "nombre clave/de registro no reconocido"
diff --git a/gnu/usr.bin/binutils/opcodes/po/fr.gmo b/gnu/usr.bin/binutils/opcodes/po/fr.gmo
new file mode 100644
index 00000000000..20c70127178
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/fr.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/fr.po b/gnu/usr.bin/binutils/opcodes/po/fr.po
new file mode 100644
index 00000000000..ac645226b82
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/fr.po
@@ -0,0 +1,793 @@
+# Messages français pour opcodes.
+# Copyright © 2004 Free Software Foundation, Inc.
+# Michel Robitaille <robitail@IRO.UMontreal.CA>, traducteur depuis/since 1996.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2004-05-10 08:00-0500\n"
+"Last-Translator: Michel Robitaille <robitail@IRO.UMontreal.CA>\n"
+"Language-Team: French <traduc@traduc.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=ISO-8859-1\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Plural-Forms: nplurals=2; plural=(n > 1);\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "opérande de branchement non alignée"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "saut indicé non aligné"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Référence limite illégale dans la dernière instruction!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<précision illégale>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Nom de jeu de registres inconnu: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Option du désassembleur non reconnue: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Les options spécifiques ARM suivantes sont supportées avec l'utilisation de\n"
+"l'option -M:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "non défini"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Erreur interne du désassembleur"
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "contrainte inconnue « %c »"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "opérande hors limite (%ld n'est pas entre %ld et %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "opérande hors limite (%lu n'est pas entre %lu et %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<registre inconnu %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Erreur inconnue %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adresse 0x%x est hors limite.\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Champ non reconnu %d lors de l'analyse.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "mnémonique manquante dans la syntaxe de la chaîne"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "instruction non reconnue"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "erreur de syntaxe (caractère « %c » attendu,  « %c » obtenu)"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "erreur de syntaxe (caractère « %c » attendu, fin de l'instruction obtenue)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "rebut à la fin de la ligne"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "forme d'instruction non reconnue"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instruction erronée « %.50s... »"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instruction erronée « %.50s »"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*inconnu*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Champ non reconnu %d lors de l'impression insn.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "opérande hors limite (%ld n'est pas entre %ld et %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "opérande hors limite (%lu n'est pas entre 0 et %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Champ non reconnu %d lors de la construction de insn.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Champ non reconnu %d lors du décodage de insn.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Champ non reconnu %d lors de la prise d'une opérande int.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Champ non reconnu %d lors de la prise d'une opérande vma.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande int.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande vma.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "numéro de registre doit être pair"
+
+# h8300-dis.c:380Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hummmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "Ne comprend pas 0x%x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "Ne peut gérer l'insertion %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*inconnu*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<erreur interne du désassembleur>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: ERREUR: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: AVERTISSEMENT: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "note multiple %s n'est pas traitée\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "ne peut trouver ia64-ic.tbl pour la lecture\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "ne peut trouver %s pour la lecture\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"le plus récent format '%s'\n"
+"apparaît plus restrictif que '%s'\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "chevauchement de champ %s->%s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "sur-écriture de la note %d avec la note %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "ne sait comment spécifier %% pour la dépendance %s\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "Ne sait comment spécifier # pour la dépendence %s\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] n'a pas de terminals ou de sous-classes\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s n'a pas de terminals ou de sous-classes\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "aucun insns mappé directement au terminal IC %s [%s]"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "aucun insns mappé directement au terminal IC %s\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "classe %s défini mais non utilisée\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "AVERTISSEMENT: rsrc %s (%s) n'a pas de chks%s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "rsrc %s (%s) n'a pas de registres\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC note %d dans l'opcode %s (IC:%s) entre en conflit avec la ressource %s note %d\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC note %d pour l'opcode %s (IC:%s) entre en conflit avec la ressource %s note %d\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "opcode %s n'a pas de classe (ops %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "incapable de changer de répertoire vers \"%s\", errno = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "W mot clé invalide dans la slot de l'opérance FR."
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "décalage(IP) n'a pas un format valide"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "décalage (DP) est hors limite."
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "décalage (SP) est hors limite."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "usage illégal des parenthèses"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "opérande hors limite (n'est pas entre 1 et 255)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: opindex invalide."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "adresse d'octet requise - doit être paire."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address a retourné un symbole. Litéral requis."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "opérande de l'%opérateur n'est pas un symbole"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Tentative de repérage d'un index de bit de 0"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "valeur immédiate doit être un registre"
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "valeur immédiate est hors limite"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "décalage de 21 bits est hors limite"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "`)' manquante"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "inconnu\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "inconnu\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "inconnu\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<erreur interne dans la table des codes-op: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<code de fonction %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <erreur du désassembleur: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# erreur interne, séquence d'extension incomplète (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# erreur interne, séquence d'extension indéfinie (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# erreur interne, modificateur non défini(%c)"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# erreur interne du déssassembleur, modificateur non reconnu(%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Les options spécifiques MIPS du désassembleur sont supportées avec l'utilisation de\n"
+"l'option -M (les options multiples doivent être séparées par des virgules):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Afficher les noms GPR selon l'ABI spécifié.\n"
+"                           Par défaut: basé sur le binaire déassemblé.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Afficher les noms FPR selon l'ABI spécifié.\n"
+"                           Par défaut: numérique.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Afficher les noms des registres CP0 selon\n"
+"                           l'architecture spécifiée.\n"
+"                           Par défaut: basé sur le binaire déassemblé.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Afficher les noms HWR selon  \n"
+"\t\t\t   l'architecture spécifiée.\n"
+"                           Par défaut: basé sur le binaire déassemblé.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Afficher les noms GPR et FPR selon l'ABI\n"
+"                           spécifié.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Afficher les noms des registres CP0 et HWR selon\n"
+"                           l'architecture spécifiée.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Pour les options ci-haut, les valeurs suivantes sont supportés pour l'\"ABI\":\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Pour les options ci-haut, les valeurs suivantes sont supportées pour \"ARCH\":\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Case erroné %d (%s) dans %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Interne: code qui n'est pas au point (case de test manquant): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(inconnu)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*type d'opérande inconnue: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<non défini>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "option conditionnelle invalide"
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "tentative d'initialisation du bit y lorsque le modificateur + ou - a été utilisé"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "décalage n'est pas un multiple de 16"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "décalage n'est pas un multiple de 2"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "décalage plus grand que 62"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "décalage n'est pas un multiple de 4"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "décalage plus grand que 124"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "décalage n'est pas un multiple de 8"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "décalage plus grand que 248"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "décalage n'est pas entre -2048 et 2047"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "décalage n'est pas entre -8192 et 8191"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "masque mfcr invalide est ignoré"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "Les derniers bits les moins significatifs sont ignorés dans le décalage de branchement"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "masque de bits illégal"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "valeur hors limite"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "registre index n'est pas dans la plage de chargement"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "les opérandes des registres source et cible doivent être diffrents"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "opérande registre invalide lors de la mise à jour"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "opérande du registre cible doit être pair"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "opérande du registre source doit être pair"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "inconnu"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erreur interne:  sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erreur interne: sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Erreur interne: sparc-opcode.h erroné: « %s » == « %s »\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "décalage d'opérande inconnu: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "registre de pile inconnu: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "La valeur de déplacement est hors limite et n'est pas alignée."
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "valeur de déplacement est hors limite"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "valeur de déplacement n'est pas alignée"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "valeur immédiate est hors limite"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "valeur de branchement est hors limite et a un décalage impair"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "valeur de branchement hors limite"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "Branchement avec un décalage impair"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "valeur de branchement est hors limite et a un décalage impair"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "registre invalide pour un ajustement de la pile"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "valeur immédiate est hors limite et est impaire"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "valeur immédiate doit être paire"
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Registre erroné dans un préincrément"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Registre erroné dans un postincrément"
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Nom erroné de registre"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Conflits d'étiquette avec le nom de registre"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Conflit d'étiquette avec « Rx »"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Expression immédiate erronée"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "aucune relocalisation pour un petit immédiat"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Petite opérande n'était pas un nombre immédiat"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "opérande n'est pas un symbol"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Erreur de syntaxe: pas de ')' en suffixe"
+
+#~ msgid "unrecognized keyword/register name"
+#~ msgstr "nom de mot clé ou de registre non reconnu"
diff --git a/gnu/usr.bin/binutils/opcodes/po/id.gmo b/gnu/usr.bin/binutils/opcodes/po/id.gmo
new file mode 100644
index 00000000000..5d6dcd45e5e
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/id.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/id.po b/gnu/usr.bin/binutils/opcodes/po/id.po
new file mode 100644
index 00000000000..3edf2949926
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/id.po
@@ -0,0 +1,423 @@
+# opcodes 2.12.1 (Indonesian)
+# Copyright (C) 2002 Free Software Foundation, Inc.
+# Tedi Heriyanto <tedi_h@gmx.net>, 2002.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.12.1\n"
+"POT-Creation-Date: 2002-02-08 03:24-0200\n"
+"PO-Revision-Date: 2002-07-23 12:35GMT+0700\n"
+"Last-Translator: Tedi Heriyanto <tedi_h@gmx.net>\n"
+"Language-Team: Indonesian <translation-team-id@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"X-Generator: KBabel 0.9.5\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "operand cabang tidak rata"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "petunjuk lompat tidak rata"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "referensi limm ilegal dalam instruksi terakhir!\n"
+
+#: arm-dis.c:502
+msgid "<illegal precision>"
+msgstr "<presisi ilegal>"
+
+#: arm-dis.c:1012
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Set nama register tidak dikenal: %s\n"
+
+#: arm-dis.c:1019
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Option disasembler tidak dikenal: %s\n"
+
+#: arm-dis.c:1191
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Option disablembler khusus ARM berikut ini didukung untuk digunakan dengan\n"
+"switch -M:\n"
+
+#: avr-dis.c:118 avr-dis.c:128
+msgid "undefined"
+msgstr "tidak didefinisikan"
+
+#: avr-dis.c:180
+msgid "Internal disassembler error"
+msgstr "Kesalahan disasembler internal"
+
+#: avr-dis.c:228
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "konstrain tidak dikenal `%c'"
+
+#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operand keluar batas (%ld tidak antara %ld dan %ld)"
+
+#: cgen-asm.c:367
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operand keluar batas (%lu tidak antara %lu dan %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<register tidak dikenal %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Kesalahan tidak dikenal %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Alamat 0x%x di luar batas.\n"
+
+#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Field tidak dikenal %d saat parsing.\n"
+
+#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281
+msgid "missing mnemonic in syntax string"
+msgstr "mnemonik hilang dalam string sintaks"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610
+msgid "unrecognized instruction"
+msgstr "instruksti tidak dikenal"
+
+#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan `%c')"
+
+#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan akhir instruksi)"
+
+#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502
+msgid "junk at end of line"
+msgstr "sampah di akhir baris"
+
+#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609
+msgid "unrecognized form of instruction"
+msgstr "bentuk instruksi tidak dikenal"
+
+#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instruksi buruk `%.50s...'"
+
+#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instruksi buruk `%.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 xstormy16-dis.c:39
+msgid "*unknown*"
+msgstr "*tidak dikenal*"
+
+#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Field tidak dikenal %d saat mencetak insn.\n"
+
+#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operand di luar batas (%ld tidak antara %ld dan %lu)"
+
+#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operand di luar batas (%lu tidak antara 0 dan %lu)"
+
+#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Field tidak dikenal %d saat membuild insn.\n"
+
+#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Field tidak dikenal %d saat mendekode insn.\n"
+
+#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Field tidak dikenal %d saat memperoleh operand int.\n"
+
+#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Field tidak dikenal %d saat memperoleh operand vma.\n"
+
+#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Field tidak dikenal %d saat menset operand int.\n"
+
+#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Field tidak dikenal %d saat menset operand vma.\n"
+
+#: h8300-dis.c:384
+#, c-format
+msgid "Hmmmm %x"
+msgstr "Hmmmm %x"
+
+#: h8300-dis.c:395
+#, c-format
+msgid "Don't understand %x \n"
+msgstr "Tidak mengerti %x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "tidak dapat menangani insert %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*tidak dikenal*"
+
+#: i386-dis.c:1649
+msgid "<internal disassembler error>"
+msgstr "<kesalahan asembler internal>"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "tidak dikenal\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "tidak dikenal\t0x%04lx"
+
+#: m10300-dis.c:685
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "tidak dikenal\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<kesalahan internal dalam tabel opcode: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<kode fungsi %d>"
+
+#: m88k-dis.c:255
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <kesalahan dis: %08x>"
+
+#: mips-dis.c:290
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# kesalahan internal, modifier tidak didefinisikan(%c)"
+
+#: mips-dis.c:1154
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# kesalahan internal disasembler, modifier tidak dikenal (%c)"
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Case buruk %d (%s) dalam %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Internal: Kode belum didebug (tidak ada test-case): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(tidak dikenal)"
+
+#: mmix-dis.c:517
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*tipe operand tidak dikenal: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:628
+msgid "$<undefined>"
+msgstr "$<tidak didefinisikan>"
+
+#: ppc-opc.c:765 ppc-opc.c:798
+msgid "invalid conditional option"
+msgstr "option kondisional tidak valid"
+
+#: ppc-opc.c:800
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "berusaha menset bit y saat menggunakan modifier + atau -"
+
+#: ppc-opc.c:832 ppc-opc.c:884
+msgid "offset not a multiple of 4"
+msgstr "offset bukan kelipatan 4"
+
+#: ppc-opc.c:857
+msgid "offset not between -2048 and 2047"
+msgstr "offset tidak berada antara -2048 dan 2047"
+
+#: ppc-opc.c:882
+msgid "offset not between -8192 and 8191"
+msgstr "offset tidak berada antara -8192 dan 8191"
+
+#: ppc-opc.c:910
+msgid "ignoring least significant bits in branch offset"
+msgstr "mengabaikan least significant bit dalam offset cabang"
+
+#: ppc-opc.c:944 ppc-opc.c:981
+msgid "illegal bitmask"
+msgstr "bitmask ilegal"
+
+#: ppc-opc.c:1054
+msgid "value out of range"
+msgstr "nilai di luar batas"
+
+#: ppc-opc.c:1130
+msgid "index register in load range"
+msgstr "register indeks dalam daerah pemuatan"
+
+#: ppc-opc.c:1146
+msgid "invalid register operand when updating"
+msgstr "operand register tidak valid saat mengupdate"
+
+#. Mark as non-valid instruction
+#: sparc-dis.c:750
+msgid "unknown"
+msgstr "tidak dikenal"
+
+#: sparc-dis.c:825
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Kesalahan internal:  sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:836
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:885
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:224
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "shift operand tidak dikenal: %x\n"
+
+#: v850-dis.c:236
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "reg pop tidak dikenal: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "nilai displacement tidak dalam jangkauan dan tidak rata"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "nilai displacement di luar batas"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "nilai displacement tidak rata"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "nilai langsung di luar batas"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "nilai cabang tidak dalam jangkauan"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "nilai cabang di luar jangkauan"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "cabang offset ganjil"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "nilai cabang di luar jangkauan dan offset ganjil"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "register tidak valid untuk penyesuaian stack"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "nilai langsung tidak dalam jangkauan dan tidak genap"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "nilai langsung harus genap"
+
+#: xstormy16-asm.c:74
+msgid "Bad register in preincrement"
+msgstr "register buruk dalam preinkremen"
+
+#: xstormy16-asm.c:79
+msgid "Bad register in postincrement"
+msgstr "Register buruk dalam pascainkremen"
+
+#: xstormy16-asm.c:81
+msgid "Bad register name"
+msgstr "Nama register buruk"
+
+#: xstormy16-asm.c:85
+msgid "Label conflicts with register name"
+msgstr "Label konflik dengan nama register"
+
+#: xstormy16-asm.c:89
+msgid "Label conflicts with `Rx'"
+msgstr "Label konflik dengan `Rx'"
+
+#: xstormy16-asm.c:91
+msgid "Bad immediate expression"
+msgstr "Ekspresi langsung yang buruk"
+
+#: xstormy16-asm.c:120
+msgid "Small operand was not an immediate number"
+msgstr "Operand kecil bukan sebuah angka immediate"
diff --git a/gnu/usr.bin/binutils/opcodes/po/nl.gmo b/gnu/usr.bin/binutils/opcodes/po/nl.gmo
new file mode 100644
index 00000000000..d90ae8d030b
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/nl.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/nl.po b/gnu/usr.bin/binutils/opcodes/po/nl.po
new file mode 100644
index 00000000000..d4247c11843
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/nl.po
@@ -0,0 +1,809 @@
+# Dutch messages for the Opcodes Library.
+# Copyright (C) 1999, 2002, 2003 Free Software Foundation, Inc.
+# This file is distributed under the same license as the Opcodes package.
+# Tim Van Holder <tim.van.holder@pandora.be>, 1999, 2002, 2003.
+# 
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2003-07-18 17:17+0200\n"
+"Last-Translator: Tim Van Holder <tim.van.holder@pandora.be>\n"
+"Language-Team: Dutch <vertaling@nl.linux.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=iso-8859-1\n"
+"Content-Transfer-Encoding: 8-bit\n"
+"Plural-Forms: nplurals=2; plural=(n != 1);\n"
+
+# misschien 'branch' vertalen (vertakking?)
+# en unaligned vertalen als 'niet uitgelijnd'?
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "branch-operand niet uitgelijnd"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "jump-hint niet uitgelijnd"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Ongeldige limm-verwijzing in de laatste instructie!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<ongeldige precisie>"
+
+# Hoort set bij 'name', of bij 'register name'?
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Registernaam-verzameling niet herkend: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Disassembler-optie niet herkend: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"De volgende ARM-specifieke disassembler-opties worden ondersteund voor gebruik\n"
+"via de -M optie:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "niet gedefinieerd"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Interne fout in de disassembler"
+
+# Vertaling voor constraint? 'begrenzing' misschien?
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "onbekende constraint `%c'"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operand buiten bereik (%ld niet tussen %ld en %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operand buiten bereik (%lu niet tussen %lu en %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<onbekend register %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Onbekende fout %d\n"
+
+# Slecht vertaald. Wat is de geijkte vertaling voor 'out of bounds'?
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adres 0x%x is buiten de perken.\n"
+
+# Betere vertaling voor 'parsing'?
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Veld %d niet herkend tijdens parsen.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "mnemonic ontbreekt in syntaxstring"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "instructie niet herkend"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "syntaxfout (verwachtte character `%c', maar vond `%c')"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "syntaxfout (verwachtte character `%c', maar vond het einde van de instructie)"
+
+# Betere (niet-Vlaamse) vertaling voor 'junk'?
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "brol aan einde van lijn"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "instructievorm niet herkend"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "slechte instructie `%s.50s...'"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "slechte instructie `%s.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*onbekend*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Veld %d niet herkend bij het afdrukken van een insn.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operand buiten bereik (%ld niet tussen %ld en %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operand buiten bereik (%lu niet tussen 0 en %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Veld %d niet herkend bij het opbouwen van een insn.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Veld %d niet herkend bij het decoderen van een insn.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Veld %d niet herkend bij het ophalen van een int-operand.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Veld %d niet herkend bij het ophalen van een vma-operand.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Veld %d niet herkend bij het instellen van een int-operand.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Veld %d niet herkend bij het instellen van een vma-operand.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "registernummer moet paar zijn"
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "Ik begrijp 0x%x niet\n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "kan niet omgaan met insert %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*onbekend*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<interne fout in de disassembler>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Fout: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Let Op: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "meervoudige noot %s wordt niet opgevangen\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "kan invoerbestand ia64-ic.tbl niet vinden\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "kan invoerbestand %s niet vinden\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"het meest recente formaat '%s'\n"
+"lijkt meer beperkend dan '%s'\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "overlappend veld %s->%s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "noot %d wordt overschreven door noot %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "ik weet niet hoe ik de %%-dependency %s moet opgeven\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "Ik weet niet hoe ik de #-dependency %s moet opgeven\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] heeft geen eindsymbolen of subklassen\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s heeft geen eindsymbolen of subklassen\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s [%s] vertaald worden"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s vertaald worden\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "klasse %s is gedefinieerd maar wordt niet gebruikt\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Let Op: rsrc %s (%s) heeft geen chks%s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "rsrc %s (%s) heeft geen regs\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC noot %d in opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "IC noot %d voor opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "opcode %s heeft geen klasse (ops %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "kan niet naar directory \"%s\" gaan, errno = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "keyword W is ongeldig in operand-slot FR"
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "offset(IP) is geen geldige vorm"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) offset buiten bereik"
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) offset buiten bereik"
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "ongeldig gebruik van haakjes"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "operand buiten bereik (niet tussen 1 en 255)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: ongeldige opindex."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Byte-adres vereist. - moet paar zijn."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address gaf een symbool terug terwijl een letterlijke waarde vereist is."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "operand van %operator is geen symbool"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Poging tot vinden van bit-index van 0"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "onmiddellijke waarde kan geen register zijn"
+
+# of moet 'immediate' behouden worden?
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "onmiddellijke waarde is buiten bereik"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "21-bit offset is buiten bereik"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "`)' ontbreekt"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "onbekend\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "onbekend\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "onbekend\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<interne fout in opcode-tabel: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<functie-code %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <dis fout: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# interne fout, onvolledige extension sequence  (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# interne fout, extension sequence (+%c) niet gedefinieerd"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# interne fout, modifier(%c) niet gedefinieerd"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# interne fout in disassembler, modifier(%c) niet herkend"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"De volgende MIPS-specifieke disassembler-opties worden ondersteund voor gebruik\n"
+"via de -M optie (meerdere opties moeten door komma's gescheiden worden):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Druk GPR-namen af volgens de opgegeven ABI.\n"
+"                           Standaard: gebaseerd op het binair bestand dat\n"
+"                           gedesassembleerd wordt.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Druk FPR-namen af volgens de opgegeven ABI.\n"
+"                           Standaard: numeriek.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Druk CP0 registernamen af volgens de opgegeven\n"
+"                           architectuur.\n"
+"                           Standaard: gebaseerd op het binair bestand dat\n"
+"                           gedesassembleerd wordt.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Druk HWR-namen af volgens de opgegeven architectuur.\n"
+"                           Standaard: gebaseerd op het binair bestand dat\n"
+"                           gedesassembleerd wordt.\n"
+"\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Druk GPR- en FPR-namen af volgens de opgegeven ABI.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Druk CP0 registernamen en HWR-namen af volgens de\n"
+"                           opgegeven architectuur.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ABI\":\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ARCH\":\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Ongeldige case %d (%s) in %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Intern: Code niet gedebugd (test-case ontbreekt): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(onbekend)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "onbekend type operanden: %d"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<niet gedefinieerd>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "ongeldige voorwaardelijke optie"
+
+# Dit kan waarschijnlijk beter
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "poging om y bit in te stellen wanneer + of - modifier gebruikt wordt"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "offset is geen veelvoud van 16"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "offset is geen veelvoud van 2"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "offset is groter dan 62"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "offset is geen veelvoud van 4"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "offset is groter dan 124"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "offset is geen veelvoud van 8"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "offset is groter dan 248"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "offset ligt niet tussen -2048 en 2047"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "offset ligt niet tussen -8192 en 8191"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "ongeldig mfcr-masker wordt genegeerd"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "minst significante bits worden genegeerd in branch offset"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "illegaal bitmasker"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "waarde buiten bereik"
+
+# of is laadbereik beter?
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "indexregister in load-bereik"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "bron- en doel-registeroperanden moeten verschillen"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "ongeldige register-operand bij update"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "doel-registeroperand moet paar zijn"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "bron-registeroperand moet paar zijn"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "onbekend"
+
+# Looks like this is a typo (two spaces after the ':')
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Interne fout: sparch-opcode.h is verkeerd: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "onbekende operand-shift: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "onbekend pop reg: %d\n"
+
+# Wat is een goede vertaling voor 'displacement'?
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "displacement-waarde is niet in bereik en is niet uitgelijnd"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "displacement-waarde is buiten bereik"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "displacement-waarde is niet uitgelijnd"
+
+# of moet 'immediate' behouden worden?
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "onmiddellijke waarde is buiten bereik"
+
+# Repeated message..., use 'to an odd...' to merge it
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "branch-waarde niet in bereik en naar onpare offset"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "branch-waarde buiten bereik"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "branch naar onpare offset"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "branch-waarde niet in bereik en naar een onpare offset"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "ongeldig register voor stack-aanpassing"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "onmiddellijke waarde niet in bereik en niet paar"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "onmiddellijke waarde moet paar zijn"
+
+# of is laadbereik beter?
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Ongeldig register in preincrement"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Ongeldig register in postincrement"
+
+# of is laadbereik beter?
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Ongeldige registernaam"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Label geeft conflict met registernaam"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Label geeft conflict met `Rx'"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Slechte onmiddelijke expressie"
+
+# immediate what? 'value' assumed
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Geen relocatie voor kleine onmiddelijke waarde"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Kleine operand was geen onmiddellijk getal"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Operand is geen symbool"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Syntaxfout: Geen sluithaakje"
diff --git a/gnu/usr.bin/binutils/opcodes/po/opcodes.pot b/gnu/usr.bin/binutils/opcodes/po/opcodes.pot
index fbc549dbda2..15fdff07f02 100644
--- a/gnu/usr.bin/binutils/opcodes/po/opcodes.pot
+++ b/gnu/usr.bin/binutils/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2002-02-08 03:24-0200\n"
+"POT-Creation-Date: 2003-07-17 14:54+0100\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -26,47 +26,47 @@ msgstr ""
 msgid "Illegal limm reference in last instruction!\n"
 msgstr ""
 
-#: arm-dis.c:502
+#: arm-dis.c:554
 msgid "<illegal precision>"
 msgstr ""
 
-#: arm-dis.c:1012
+#: arm-dis.c:1162
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
-#: arm-dis.c:1019
+#: arm-dis.c:1169
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:1191
+#: arm-dis.c:1343
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
 "the -M switch:\n"
 msgstr ""
 
-#: avr-dis.c:118 avr-dis.c:128
+#: avr-dis.c:117 avr-dis.c:127
 msgid "undefined"
 msgstr ""
 
-#: avr-dis.c:180
+#: avr-dis.c:179
 msgid "Internal disassembler error"
 msgstr ""
 
-#: avr-dis.c:228
+#: avr-dis.c:227
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195
-#: xstormy16-ibld.c:195
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
 msgstr ""
 
-#: cgen-asm.c:367
+#: cgen-asm.c:369
 #, c-format
 msgid "operand out of range (%lu not between %lu and %lu)"
 msgstr ""
@@ -87,112 +87,134 @@ msgstr ""
 msgid "Address 0x%x is out of bounds.\n"
 msgstr ""
 
-#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:244 xstormy16-asm.c:284
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr ""
 
-#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:294 xstormy16-asm.c:334
 msgid "missing mnemonic in syntax string"
 msgstr ""
 
 #. We couldn't parse it.
-#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511
-#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430
-#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623
-#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508
-#: xstormy16-asm.c:610
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434
+#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
 msgid "unrecognized instruction"
 msgstr ""
 
-#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:477 xstormy16-asm.c:517
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr ""
 
-#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:487 xstormy16-asm.c:527
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr ""
 
-#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:515 xstormy16-asm.c:555
 msgid "junk at end of line"
 msgstr ""
 
-#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662
 msgid "unrecognized form of instruction"
 msgstr ""
 
-#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr ""
 
-#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677
 #, c-format
 msgid "bad instruction `%.50s'"
 msgstr ""
 
 #. Default text to print if an instruction isn't recognized.
-#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
-#: xstormy16-dis.c:39
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
 msgid "*unknown*"
 msgstr ""
 
-#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr ""
 
-#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
 #, c-format
 msgid "operand out of range (%lu not between 0 and %lu)"
 msgstr ""
 
-#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr ""
 
-#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr ""
 
-#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001
-#: xstormy16-ibld.c:1224
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
 msgstr ""
 
-#: h8300-dis.c:384
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr ""
+
+#: h8300-dis.c:377
 #, c-format
-msgid "Hmmmm %x"
+msgid "Hmmmm 0x%x"
 msgstr ""
 
-#: h8300-dis.c:395
+#: h8300-dis.c:760
 #, c-format
-msgid "Don't understand %x \n"
+msgid "Don't understand 0x%x \n"
 msgstr ""
 
 #: h8500-dis.c:143
@@ -206,10 +228,185 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:1649
+#: i386-dis.c:1699
 msgid "<internal disassembler error>"
 msgstr ""
 
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr ""
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr ""
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr ""
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr ""
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr ""
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr ""
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr ""
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr ""
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr ""
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr ""
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr ""
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr ""
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr ""
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr ""
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr ""
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr ""
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr ""
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr ""
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr ""
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr ""
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr ""
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr ""
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr ""
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr ""
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr ""
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr ""
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr ""
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr ""
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr ""
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr ""
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr ""
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr ""
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr ""
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr ""
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+msgid "missing `)'"
+msgstr ""
+
 #: m10200-dis.c:199
 #, c-format
 msgid "unknown\t0x%02x"
@@ -220,7 +417,7 @@ msgstr ""
 msgid "unknown\t0x%04lx"
 msgstr ""
 
-#: m10300-dis.c:685
+#: m10300-dis.c:766
 #, c-format
 msgid "unknown\t0x%04x"
 msgstr ""
@@ -235,21 +432,99 @@ msgstr ""
 msgid "<function code %d>"
 msgstr ""
 
-#: m88k-dis.c:255
+#: m88k-dis.c:746
 #, c-format
 msgid "# <dis error: %08x>"
 msgstr ""
 
-#: mips-dis.c:290
+#: mips-dis.c:703
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr ""
+
+#: mips-dis.c:746
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr ""
+
+#: mips-dis.c:1004
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
 msgstr ""
 
-#: mips-dis.c:1154
+#: mips-dis.c:1755
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr ""
 
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+
+#: mips-dis.c:1779
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+
+#: mips-dis.c:1784
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+
+#: mips-dis.c:1797
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+
+#: mips-dis.c:1802 mips-dis.c:1810 mips-dis.c:1812
+msgid "\n"
+msgstr ""
+
+#: mips-dis.c:1804
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+
 #: mmix-dis.c:34
 #, c-format
 msgid "Bad case %d (%s) in %s:%d\n"
@@ -264,7 +539,7 @@ msgstr ""
 msgid "(unknown)"
 msgstr ""
 
-#: mmix-dis.c:517
+#: mmix-dis.c:519
 #, c-format
 msgid "*unknown operands type: %d*"
 msgstr ""
@@ -275,76 +550,116 @@ msgstr ""
 #. * aoffsetp by since whatever generated this is broken
 #. * anyway!
 #.
-#: ns32k-dis.c:628
+#: ns32k-dis.c:631
 msgid "$<undefined>"
 msgstr ""
 
-#: ppc-opc.c:765 ppc-opc.c:798
+#: ppc-opc.c:781 ppc-opc.c:809
 msgid "invalid conditional option"
 msgstr ""
 
-#: ppc-opc.c:800
+#: ppc-opc.c:811
 msgid "attempt to set y bit when using + or - modifier"
 msgstr ""
 
-#: ppc-opc.c:832 ppc-opc.c:884
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr ""
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr ""
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr ""
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
 msgid "offset not a multiple of 4"
 msgstr ""
 
-#: ppc-opc.c:857
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr ""
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr ""
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr ""
+
+#: ppc-opc.c:950
 msgid "offset not between -2048 and 2047"
 msgstr ""
 
-#: ppc-opc.c:882
+#: ppc-opc.c:973
 msgid "offset not between -8192 and 8191"
 msgstr ""
 
-#: ppc-opc.c:910
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr ""
+
+#: ppc-opc.c:1059
 msgid "ignoring least significant bits in branch offset"
 msgstr ""
 
-#: ppc-opc.c:944 ppc-opc.c:981
+#: ppc-opc.c:1090 ppc-opc.c:1125
 msgid "illegal bitmask"
 msgstr ""
 
-#: ppc-opc.c:1054
+#: ppc-opc.c:1192
 msgid "value out of range"
 msgstr ""
 
-#: ppc-opc.c:1130
+#: ppc-opc.c:1262
 msgid "index register in load range"
 msgstr ""
 
-#: ppc-opc.c:1146
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr ""
+
+#: ppc-opc.c:1294
 msgid "invalid register operand when updating"
 msgstr ""
 
-#. Mark as non-valid instruction
-#: sparc-dis.c:750
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr ""
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr ""
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
 msgid "unknown"
 msgstr ""
 
-#: sparc-dis.c:825
+#: sparc-dis.c:835
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:836
+#: sparc-dis.c:846
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:885
+#: sparc-dis.c:895
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr ""
 
-#: v850-dis.c:224
+#: v850-dis.c:221
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr ""
 
-#: v850-dis.c:236
+#: v850-dis.c:233
 #, c-format
 msgid "unknown pop reg: %d\n"
 msgstr ""
@@ -398,30 +713,42 @@ msgstr ""
 msgid "immediate value must be even"
 msgstr ""
 
-#: xstormy16-asm.c:74
+#: xstormy16-asm.c:76
 msgid "Bad register in preincrement"
 msgstr ""
 
-#: xstormy16-asm.c:79
+#: xstormy16-asm.c:81
 msgid "Bad register in postincrement"
 msgstr ""
 
-#: xstormy16-asm.c:81
+#: xstormy16-asm.c:83
 msgid "Bad register name"
 msgstr ""
 
-#: xstormy16-asm.c:85
+#: xstormy16-asm.c:87
 msgid "Label conflicts with register name"
 msgstr ""
 
-#: xstormy16-asm.c:89
+#: xstormy16-asm.c:91
 msgid "Label conflicts with `Rx'"
 msgstr ""
 
-#: xstormy16-asm.c:91
+#: xstormy16-asm.c:93
 msgid "Bad immediate expression"
 msgstr ""
 
-#: xstormy16-asm.c:120
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr ""
+
+#: xstormy16-asm.c:125
 msgid "Small operand was not an immediate number"
 msgstr ""
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr ""
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr ""
diff --git a/gnu/usr.bin/binutils/opcodes/po/pt_BR.gmo b/gnu/usr.bin/binutils/opcodes/po/pt_BR.gmo
new file mode 100644
index 00000000000..083e8f42199
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/pt_BR.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/pt_BR.po b/gnu/usr.bin/binutils/opcodes/po/pt_BR.po
new file mode 100644
index 00000000000..c2663d3da01
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/pt_BR.po
@@ -0,0 +1,445 @@
+# opcodes: translation to Brazilian Portuguese (pt_BR)
+# Copyright (C) 2002 Free Software Foundation, Inc.
+# Alexandre Folle de Menezes <afmenez@terra.com.br>, 2002.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.12.91\n"
+"POT-Creation-Date: 2002-07-23 15:55-0400\n"
+"PO-Revision-Date: 2002-07-24 04:00-0300\n"
+"Last-Translator: Alexandre Folle de Menezes <afmenez@terra.com.br>\n"
+"Language-Team: Brazilian Portuguese <ldp-br@bazar.conectiva.com.br>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=ISO-8859-1\n"
+"Content-Transfer-Encoding: 8-bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "operando de desvio desalinhado"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "dica de salto desalinhada"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Referência limm ilegal na última instrução!\n"
+
+#: arm-dis.c:507
+msgid "<illegal precision>"
+msgstr "<precisão ilegal>"
+
+#: arm-dis.c:1010
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Conjunto de nomes de registrador desconhecido: %s\n"
+
+#: arm-dis.c:1017
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Opção do desmontador desconhecida: %s\n"
+
+#: arm-dis.c:1191
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"As opções do desmontador espcíficas para ARM a seguir não são suportadas para\n"
+"uso com a opção -M:\n"
+
+#: avr-dis.c:118 avr-dis.c:128
+msgid "undefined"
+msgstr "indefinido"
+
+#: avr-dis.c:180
+msgid "Internal disassembler error"
+msgstr "Erro interno do desmontador"
+
+#: avr-dis.c:228
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "restrição `%c' desconhecida"
+
+#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195
+#: openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operando fora de faixa (%ld não está entre %ld e %ld)"
+
+#: cgen-asm.c:367
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operando fora de faixa (%lu não está entre %lu e %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<registrador %d desconhecido>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Erro %d desconhecido\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Endereço 0x%x está fora dos limites.\n"
+
+#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244
+#: xstormy16-asm.c:231
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Campo %d desconhecido durante análise.\n"
+
+#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294
+#: xstormy16-asm.c:281
+msgid "missing mnemonic in syntax string"
+msgstr "mnemônico faltando na string de sintaxe"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781
+#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434
+#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417
+#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610
+msgid "unrecognized instruction"
+msgstr "instrução não reconhecida"
+
+#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477
+#: xstormy16-asm.c:464
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "erro de sintaxe (esperado char `%c', encontrado `%c')"
+
+#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487
+#: xstormy16-asm.c:474
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "erro de sintaxe (esperado char `%c', encontrado fim de instrução)"
+
+#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515
+#: xstormy16-asm.c:502
+msgid "junk at end of line"
+msgstr "lixo no final do arquivo"
+
+#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622
+#: xstormy16-asm.c:609
+msgid "unrecognized form of instruction"
+msgstr "forma de instrução não reconhecida"
+
+#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634
+#: xstormy16-asm.c:621
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instrução `%.50s...' errada"
+
+#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637
+#: xstormy16-asm.c:624
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instrução `%.50s' errada"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39
+#: xstormy16-dis.c:39
+msgid "*unknown*"
+msgstr "*desconecida*"
+
+#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136
+#: xstormy16-dis.c:169
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Campo %d não reconhecido durante impressão de insn.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166
+#: xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operando fora de faixa (%ld não está entre %ld e %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179
+#: xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operando fora de faixa (%lu não está entre 0 e %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633
+#: xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Campo %d não reconhecido durante construção de insn.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735
+#: xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Campo %d não reconhecido durante decodificação de insn.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815
+#: xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Campo %d não reconhecido ao obter operando int.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875
+#: xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Campo %d não reconhecido ao obter operando vma.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944
+#: xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Campo %d não reconhecido ao definir operando int.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001
+#: xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Campo %d não reconhecido ao definir operando vma.\n"
+
+#: h8300-dis.c:385
+#, c-format
+msgid "Hmmmm %x"
+msgstr "Hmmmm %x"
+
+#: h8300-dis.c:396
+#, c-format
+msgid "Don't understand %x \n"
+msgstr "Não entendo %x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "impossível lidar com insert %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*desconhecido*"
+
+#: i386-dis.c:1649
+msgid "<internal disassembler error>"
+msgstr "<erro interno do desmontador>"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "desconhecido\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "desconhecido\t0x%04lx"
+
+#: m10300-dis.c:685
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "desconhecido\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<erro interno na tabela de códigos de operação: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<código de função %d>"
+
+#: m88k-dis.c:255
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <erro de desmontador: %08x>"
+
+#: mips-dis.c:337
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# erro interno, modificador (%c) indefinido"
+
+#: mips-dis.c:1209
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# erro interno do desmontador, modificador (%c) não reconhecido"
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Case %d errado (%s) em %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Interno: Código não depurado (test-case faltando): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(desconhecido)"
+
+#: mmix-dis.c:517
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*tipo de operandos desconhecidos: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:628
+msgid "$<undefined>"
+msgstr "$<indefinido>"
+
+#: ppc-opc.c:777 ppc-opc.c:810
+msgid "invalid conditional option"
+msgstr "opção condicional inválida"
+
+#: ppc-opc.c:812
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "tentativa de setar bit y ao usar modificador + ou -"
+
+#: ppc-opc.c:844 ppc-opc.c:896
+msgid "offset not a multiple of 4"
+msgstr "deslocamento não é um múltiplo de 4"
+
+#: ppc-opc.c:869
+msgid "offset not between -2048 and 2047"
+msgstr "deslocamento não está entre -2048 and 2047"
+
+#: ppc-opc.c:894
+msgid "offset not between -8192 and 8191"
+msgstr "deslocamento não está entre -8192 and 8191"
+
+#: ppc-opc.c:922
+msgid "ignoring least significant bits in branch offset"
+msgstr "ignorando os bits menos significatiovs no deslocamento do desvio"
+
+#: ppc-opc.c:956 ppc-opc.c:993
+msgid "illegal bitmask"
+msgstr "máscara de bits ilegal"
+
+#: ppc-opc.c:1066
+msgid "value out of range"
+msgstr "valor fora de faixa"
+
+#: ppc-opc.c:1142
+msgid "index register in load range"
+msgstr "registrador de índice na faixa de carregamento"
+
+#: ppc-opc.c:1158
+msgid "invalid register operand when updating"
+msgstr "operando de registro inválido durante atualização"
+
+#. Mark as non-valid instruction
+#: sparc-dis.c:750
+msgid "unknown"
+msgstr "desconhecido"
+
+#: sparc-dis.c:825
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erro interno:  sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:836
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Erro interno: sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:885
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Erro interno: sparc-opcode.h errado: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:224
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "deslocamento de operando desconhecido: %x\n"
+
+#: v850-dis.c:236
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "registrador pop desconhecido: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "valor do deslocamento está fora da faixa e não está alinhado"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "valor do deslocamento está fora da faixa"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "valor do deslocamento não está alinhado"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "valor imediato está fora da faixa"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "valor do desvio fora da faixa e para deslocamento ímpar"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "valor do desvio fora da faixa"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "desvio para um deslocamento ímpar"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "valor do desvio fora da faixa e para um deslocamento ímpar"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "registrador inválido para ajuste da pilha"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "valor imediato fora da faixa e não é par"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "o valor imediato deve ser par"
+
+#: xstormy16-asm.c:74
+msgid "Bad register in preincrement"
+msgstr "Registrador errado no pré-incremento"
+
+#: xstormy16-asm.c:79
+msgid "Bad register in postincrement"
+msgstr "Registrador errado no pós-incremento"
+
+#: xstormy16-asm.c:81
+msgid "Bad register name"
+msgstr "Nome de registrador errado"
+
+#: xstormy16-asm.c:85
+msgid "Label conflicts with register name"
+msgstr "O rótulo conflita com nome de registrador"
+
+#: xstormy16-asm.c:89
+msgid "Label conflicts with `Rx'"
+msgstr "O rótulo conflita com `Rx'"
+
+#: xstormy16-asm.c:91
+msgid "Bad immediate expression"
+msgstr "Expressão imediata errada"
+
+#: xstormy16-asm.c:120
+msgid "Small operand was not an immediate number"
+msgstr "O operando pequeno não era um número imediato"
diff --git a/gnu/usr.bin/binutils/opcodes/po/ro.gmo b/gnu/usr.bin/binutils/opcodes/po/ro.gmo
new file mode 100644
index 00000000000..6125448e623
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/ro.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/ro.po b/gnu/usr.bin/binutils/opcodes/po/ro.po
new file mode 100644
index 00000000000..ca0b870ee2e
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/ro.po
@@ -0,0 +1,788 @@
+# Mesajele în limba românã pentru pachetul opcodes
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# Eugen Hoanca <eugenh@urban-grafx.ro>, 2003
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2003-07-21 16:53+0300\n"
+"Last-Translator: Eugen Hoanca <eugenh@urban-grafx.ro>\n"
+"Language-Team: Romanian <translation-team-ro@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=ISO-8859-2\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "ramurã operand nealiniatã"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "sugestie salt(jump) nealiniat"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "referinþã limm ilegalã în ultima instrucþiune!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<precizie ilegalã>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Setare nume registru necunoscutã: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Opþiune dezasamblor necunsocutã: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Opþiunile ARM de dezasamblor specifice urmãtoare sunt permise cu folosirea\n"
+"switch-ului -M:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "nedefinit(ã)"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Eroare internã de dezasamblor"
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "constrângere necunoscutã `%c'"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operand în afara intervalului (%ld nu este între %ld ºi %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operand în afara intervalului (%lu nu este între %lu ºi %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<registru necunoscut %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Eroare necunoscutã %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adresa 0x%x este peste limite (out of bounds).\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Câmp necunoscut %d în analizã(parsing).\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "mnemonicã lipsã în sintaxã"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "instrucþiune necunoscutã"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "eroare de sintaxã ( se aºtepta %c', s-a primit `%c')"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "eroare de sintaxã (s-a aºteptat char `%c' s-a primit sfârºit de instrucþiune)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "resturi(junk) la sfârºit de linie"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "formã de instrucþiune necunoscutã"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "instrucþiune greºitã ``%.50s...'"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "instrucþiune greºitã `%.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*necunoscut(ã)*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Câmp necunoscut %d în tipãrire insn.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operand în afara limitelor (%ld nu este între %ld ºi %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operand în afara limitelor (%lu nu este între 0 ºi %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Câmp necunoscut %d în construire(building) insn.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Câmp necunoscut %d în decodare insn.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Câmp necunoscut %d în preluare operand int.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Câmp necunoscut %d în preluare operand vma.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Câmp necunoscut %d în setare operand int.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Câmp necunoscut %d în setare operand vma.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "numãrul registrului trebuie sã fie par"
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "Nu înþeleg 0x%x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "nu fac faþã la inserarea %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*necunoscut(ã)*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<eroare internã de dezasamblor>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Eroare: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Avertisment: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "notele multiple %s nerezolvabile(handled)\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "nu pot gãsi ia64-ic.tbl pentru citire\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "nu pot gãsi %s pentru citire\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"cel mai recent format %s \n"
+"pare mai restrictiv decât '%s'\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "câmp suprapus %s -> %s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "suprascriere nota %d cu nota %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "nu ºtiu cum se specificã dependinþele %% %s\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "nu ºtiu cum se specificã dependinþele # %s\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] nu are terminale sau sublclase\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s nu are terminale sau subclase\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "nici un insns mapat direct la terminalul IC %s [%s]"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "nici un insns mapat direct la terminalul IC %s\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "clasa %s este definitã dar nefolositã\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Avertisment: rsrc %s (%s) nu are chks%s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "rsrc %s (%s) nu areo regs\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "Nota IC %d din opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "Nota IC %d pentru opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "opcode %s nu are clasã (ops %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "nu am putut schimba directorul în \"%s\", errno = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "Cuvânt cheie W invalidv în slotul operand FR."
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "offsetul(IP) nu are formã validã"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) offset în afara intervalului"
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) offset în afara intervalului"
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "Folosire ilegalã de paranteze"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "operand în afara limitelor (nu este între 0 ºi 255)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: opindex invalid."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Se necesitã adresã byte. -trebuie sã fie parã (even)."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address a returnat un simbol. Se necesitã literal."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "%operator operandulk nu este un simbol"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Se încearcã gãsirea bitului index de 0"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "valoarea directã(immediate) nu poate fi înregistratã"
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "valoare directã(immediate) în afara intervalului"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "offsetul 21 bit în afara intervalului"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "`)' lipsã"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "necunoscut(ã)\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "necunoscut(ã)\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "necunoscut(ã)\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<eroare internã în tabel opcode: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<cod funcþie %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <eroare dez: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# eroare internã, secvenþã incompletã de extensie (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# eroare internã, secvenþã de extensie nedefinitã (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# eroare internã, modificator nedefinit(%c)"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# eroare internã de dezasamblor, modificator necunoscut (%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Opþiunile MIPS de dezasamblor specifice urmãtoare sunt permise cu folosirea\n"
+"switch-ului -M (opþiunile multiple trebuie separate prin virgulã:\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Afiºeazã numele GPR potrivit ABI specificat.\n"
+"                           Implicit: bazat pe binar ce este dezasamblat.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Afiºeazã numele FPR potrivit ABI specificat.\n"
+"                           Implicit: numeric.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARCH           Afiºeazã numele de regiºtri CP0 potrivit\n"
+"                           arhitecturii specifice.\n"
+"                           Implicit: bazat pe binar în dezasamblare.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARCH           Afiºeazã numele HWR potrivit arhitecturii \n"
+"\t\t\t   specifice.\n"
+"                           Implicit: bazat pe binar în dezasamblare.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Afiºeazã numele GPR ºi FPR potriviti\n"
+"                           ABI specificat.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARCH           Afiºeazã regiºtrii CP0 ºi numele HWR potrivit\n"
+"                           arhitecturii specifice.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ABI\":\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ARCH\":\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Caz greºit %d (%s) in %s: %d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Intern: cod non debugged (caz test lipsã) %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(necunoscut)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*tip necunoscut de operanzi: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<nedefinit>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "opþiune condiþionalã invalidã"
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "se încearcã setarea bitului y în folosirea modificatorilor + sau -"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "offsetul nu este multiplu de 16"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "offsetul nu este multiplu de 2"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "offset mai mare decât 62"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "offsetul nu este multiplu de 4"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "offset mai mare decât 124"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "offsetul nu este multiplu de 8"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "offset mai mare de 248"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "offsetul nu este între -2048 ºi 2047"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "offsetul nu este între -8192 ºi 8191"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "se ignorã mascã mfcr invalidã"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "se ignorã cei mai puþin semnificanþi biþi în offsetul ramurii(branch)"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "bitmask ilegal"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "valoare în afara intervalului"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "registru index în interval de încãrcare"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "operanzii regiºtri sursã ºi destinaþie trebuie sã fie diferiþi"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "registru de operand invalid în updatare"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "operandul registru destinaþie trebuie sã fie par"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "operandul registru sursã trebuie sã fie par"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "necunoscut(ã)"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Eroare internã:  opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Eroare internã: opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Eroare internã:  opcode.h sparc greºit: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "schimbare(shift) de oberand necunoscutã: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "pop reg necunoscut: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "valoarea deplasãrii în afara intervalului ºi nealiniatã"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "deplasare"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "valoarea deplasãrii nu este aliniatã"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "valoare directã(immediate) în afara intervalului"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "valoare ramurã(branch) în afara intervalului"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "ramurã(branch) la offset impar"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "registru invalid pentru modificare stivã"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "valoare directã(immediate) în afara intervalului ºi imparã"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "valoarea directã(immediate) trebuie sã fie parã"
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Registru greºit în preincrementare"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Registru greºit în postincrementare"
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Nume registru greºit"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Eticheta(label) se aflã în conflict cu numele de registru"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Eticheta(label) se aflã în conflict cu `Rx'"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Expresie directã(immediate) greºitã"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Nici o relocare pentru mai mic directã(immediate)"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Operandul redus nu a fost un numãr direct(immediate)"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Operandul nu este simbol"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Eroare de sintaxã:Nu existã ')'"
diff --git a/gnu/usr.bin/binutils/opcodes/po/sv.gmo b/gnu/usr.bin/binutils/opcodes/po/sv.gmo
new file mode 100644
index 00000000000..2bbaca69dd3
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/sv.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/sv.po b/gnu/usr.bin/binutils/opcodes/po/sv.po
new file mode 100644
index 00000000000..ae55351a284
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/sv.po
@@ -0,0 +1,808 @@
+# Swedish messages for opcodes.
+# Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
+# Christian Rose <menthos@menthos.com>, 2001, 2002, 2003.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2003-07-16 14:36+0200\n"
+"Last-Translator: Christian Rose <menthos@menthos.com>\n"
+"Language-Team: Swedish <sv@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=iso-8859-1\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "grenoperanden ligger inte på jämn gräns"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "hopptipset ligger inte på jämn gräns"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Otillåten limm-referens i sista instruktionen!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<otillåten precision>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Okänt registernamn är angivet: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Okänt disassembleralternativ: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Följande ARM-specifika disassembleralternativ stöds för användning\n"
+"tillsammans med flaggan -M:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "odefinierad"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "Internt fel i disassembleraren"
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "okänd begränsning \"%c\""
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)"
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "operanden är utanför intervallet (%lu är inte mellan %lu och %lu)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<okänt register %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Okänt fel %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "Adressen 0x%x ligger utanför tillåtna gränser.\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Okänt fält %d vid tolkning.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "instruktion saknas i syntaxsträng"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "okänd instruktion"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade slutet på instruktion)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "skräp vid slutet på raden"
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "okänd instruktionsform"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "felaktig instruktion \"%.50s...\""
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "felaktig instruktion \"%.50s\""
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*okänd*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "Okänt fält %d vid utskrift av instruktion.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %lu)"
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "operanden utanför intervallet (%lu inte mellan 0 och %lu)"
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Okänt fält %d vid konstruktion av instruktion.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Okänt fält %d vid avkodning av instruktion.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "Okänt fält %d vid hämtning av heltalsoperand.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "Okänt fält %d vid hämtning av vma-operand.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "Okänt fält %d vid inställning av heltalsoperand.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "Okänt fält %d vid inställning av vma-operand.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "registernumret måste vara jämnt"
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "Förstår inte 0x%x \n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "kan inte sätta in %d\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*okänd*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<internt fel i disassembleraren>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Fel: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Varning: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "multipel anteckning %s hanteras inte\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "kan inte hitta ia64-ic.tbl för läsning\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "kan inte hitta %s för läsning\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"allra senaste formatet \"%s\"\n"
+"verkar mer restriktivt än \"%s\"\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "överlappande fält %s->%s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "skriver över anteckning %d med anteckning %d (IC:%s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "vet inte hur %%-beroende %s ska anges\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "Vet inte hur #-beroende %s ska anges\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC:%s [%s] har inga terminaler eller underklasser\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC:%s har inga terminaler eller underklasser\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "inga instruktioner mappade direkt till terminal-IC %s [%s]"
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "inga instruktioner mappade direkt till terminal-IC %s\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "klassen %s är definierad men inte använd\n"
+
+# Misstänkt pluralhack!
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Varning: rsrc %s (%s) har inga kontroller%s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "rsrc %s (%s) har inga register\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr ""
+"IC-anteckning %d i instruktion %s (IC:%s) står i konflikt med resurs %s\n"
+"anteckning %d\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr ""
+"IC-anteckning %d för instruktion %s (IC:%s) står i konflikt med resurs %s\n"
+"anteckning %d\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "instruktion %s har ingen klass (operationer %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "kan inte byta katalog till \"%s\", felnummer = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "W-nyckelord ogiltigt i FR-operandlucka."
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "avståndet(IP) är inte en giltig form"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) avståndet är utanför intervallet."
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) avståndet är utanför intervallet."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "otillåten användning av parenteser"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "operanden utanför intervallet (inte mellan 1 och 255)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: ogiltigt opindex."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Byteadress krävs - måste vara jämn."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address returnerade en symbol. Literal krävs."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "%operator-operand är inte en symbol"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "Försök att hitta 0-bitindex"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "omedelbart värde kan inte vara register"
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "omedelbart värde är utanför intervallet"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "21-bitars avstånd utanför intervallet"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "\")\" saknas"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "okänd\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "okänd\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "okänd\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<internt fel i instruktionstabellen: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<funktionskod %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <disassemblerarfel: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# internt fel, ofullständig ändelsesekvens (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# internt fel, odefinierad ändelsesekvens (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "# internt fel, okänd modifierare(%c)"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "# internt disassemblerfel, okänd modifierare (%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Följande MIPS-specifika disassembleralternativ stöds för användning\n"
+"tillsammans med flaggan -M (flera alternativ kan skiljas åt med komman):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Skriv ut GPR-namn enligt det angivna ABI:t.\n"
+"                           Standard: baserat på den binärfil som\n"
+"                           disassembleras.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Skriv ut FPR-namn enligt det angivna ABI:t.\n"
+"                           Standard: numeriskt.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=ARK            Skriv ut CP0-registernamn enligt den angivna\n"
+"                           arkitekturen.\n"
+"                           Standard: baserat på den binärfil som\n"
+"                           disassembleras.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=ARK            Skriv ut HWR-namn enligt den angivna \n"
+"\t\t\t   arkitekturen.\n"
+"                           Standard: baserat på den binärfil som\n"
+"                           disassembleras.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Skriv ut GPR- och FPR-namn enligt det angivna\n"
+"                           ABI:t.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=ARK            Skriv ut CP0-register med HWR-namn enligt\n"
+"                           angiven arkitektur.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  För flaggorna ovan stöds följande värden på \"ABI\":\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  För flaggorna ovan stöds följande värden på \"ARK\":\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Felaktigt fall %d (%s) i %s:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "Internt: Ej felsökt kod (testfall saknas): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(okänd)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "*okänd operandtyp: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<odefinierad>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "ogiltig villkorlig flagga"
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "försök att ställa in y-biten då modifieraren + eller - användes"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "avståndet är inte en multipel av 16"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "avståndet är inte en multipel av 2"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "avståndet är större än 62"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "avståndet är inte en multipel av 4"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "avståndet är större än 124"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "avståndet är inte en multipel av 8"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "avståndet är större än 248"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "avståndet är inte mellan -2048 och 2047"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "avståndet är inte mellan -8192 och 8191"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "ignorerar ogiltig mfcr-mask"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "ignorerar minst signifikanta bitarna i grenavstånd"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "otillåten bitmask"
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "värdet är utanför intervallet"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "indexregistret är i inläsningsintervallet"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "käll- och målregisteroperander måste vara olika"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "ogiltig registeroperand vid uppdatering"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "målregisteroperand måste vara jämn"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "källregisteroperand måste vara jämn"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "okänd"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Internt fel:  felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "okänt operandskifte: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "okänt pop-register: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "förskjutningsvärdet är inte inom intervallet och ligger inte på jämn gräns"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "förskjutningsvärdet är utanför intervallet"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "förskjutningsvärdet ligger inte på jämn gräns"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "omedelbara värdet är utanför intervallet"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "grenvärdet är utanför intervallet"
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "grening till udda avstånd"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "ogiltigt register för stackjustering"
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "omedelbara värdet är inte inom intervallet och inte jämnt"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "omedelbara värdet måste vara jämnt"
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Felaktigt register i förhandsökning"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Felaktigt register i efterhandsökning"
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Felaktigt registernamn"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Etiketten står i konflikt med registernamn"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Etiketten står i konflikt med \"Rx\""
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Felaktigt omedelbart uttryck"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Ingen omlokalisering för litet omedelbart tal"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Liten operand var inte ett omedelbart tal"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Operanden är inte en symbol"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Syntaxfel: Inget eftersläpande \")\""
+
+#~ msgid "Hmmmm %x"
+#~ msgstr "Hmmmm %x"
+
+#~ msgid "Don't understand %x \n"
+#~ msgstr "Förstår inte %x \n"
+
+#~ msgid "No relocation for small immediate number"
+#~ msgstr "Ingen omlokalisering för litet omedelbart tal"
+
+#~ msgid "unrecognized keyword/register name"
+#~ msgstr "okänt namn på nyckelord/register"
diff --git a/gnu/usr.bin/binutils/opcodes/po/tr.gmo b/gnu/usr.bin/binutils/opcodes/po/tr.gmo
new file mode 100644
index 00000000000..98b9df15351
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/tr.gmo
diff --git a/gnu/usr.bin/binutils/opcodes/po/tr.po b/gnu/usr.bin/binutils/opcodes/po/tr.po
new file mode 100644
index 00000000000..f01f58dbf15
--- /dev/null
+++ b/gnu/usr.bin/binutils/opcodes/po/tr.po
@@ -0,0 +1,788 @@
+# translation of opcodes-2.14rel030712.tr.po to Turkish
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# Deniz Akkus Kanca <deniz@arayan.com>, 2001,2003.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: opcodes 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:56+0930\n"
+"PO-Revision-Date: 2003-07-13 22:58+0300\n"
+"Last-Translator: Deniz Akkus Kanca <deniz@arayan.com>\n"
+"Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"X-Generator: KBabel 1.0\n"
+
+#: alpha-opc.c:335
+msgid "branch operand unaligned"
+msgstr "dal işleneni hizalı değil"
+
+#: alpha-opc.c:358 alpha-opc.c:380
+msgid "jump hint unaligned"
+msgstr "atlama işareti hizalı değil"
+
+#: arc-dis.c:52
+msgid "Illegal limm reference in last instruction!\n"
+msgstr "Son işlemde geçersiz limm referansı!\n"
+
+#: arm-dis.c:554
+msgid "<illegal precision>"
+msgstr "<geçersiz kesinlik>"
+
+#: arm-dis.c:1162
+#, c-format
+msgid "Unrecognised register name set: %s\n"
+msgstr "Bilinmeyen yazmaç ad kümesi: %s\n"
+
+#: arm-dis.c:1169
+#, c-format
+msgid "Unrecognised disassembler option: %s\n"
+msgstr "Bilinmeyen karşıt-çevirici seçeneği: %s\n"
+
+#: arm-dis.c:1343
+msgid ""
+"\n"
+"The following ARM specific disassembler options are supported for use with\n"
+"the -M switch:\n"
+msgstr ""
+"\n"
+"Aşağıdaki ARM'a özgü karşıt-çevirici seçenekleri \n"
+"-M seçeneği ile kullanılabilir:\n"
+
+#: avr-dis.c:117 avr-dis.c:127
+msgid "undefined"
+msgstr "tanımlanmamış"
+
+#: avr-dis.c:179
+msgid "Internal disassembler error"
+msgstr "İç karşıt-çevirici hatası "
+
+#: avr-dis.c:227
+#, c-format
+msgid "unknown constraint `%c'"
+msgstr "`%c' bilinmeyen kısıtı"
+
+#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195
+#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195
+#, c-format
+msgid "operand out of range (%ld not between %ld and %ld)"
+msgstr "Kapsam dışı terim (%ld, %ld ve %ld arasında değil) "
+
+#: cgen-asm.c:369
+#, c-format
+msgid "operand out of range (%lu not between %lu and %lu)"
+msgstr "Kapsam dışı terim (%lu, %lu ve %lu arasında değil)"
+
+#: d30v-dis.c:312
+#, c-format
+msgid "<unknown register %d>"
+msgstr "<bilinmeyen yazmaç %d>"
+
+#. Can't happen.
+#: dis-buf.c:57
+#, c-format
+msgid "Unknown error %d\n"
+msgstr "Bilinmeyen hata %d\n"
+
+#: dis-buf.c:62
+#, c-format
+msgid "Address 0x%x is out of bounds.\n"
+msgstr "0x%x adresi sınırların dışında.\n"
+
+#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325
+#: openrisc-asm.c:261 xstormy16-asm.c:284
+#, c-format
+msgid "Unrecognized field %d while parsing.\n"
+msgstr "Ayrıştırma esnasında bilinmeyen alan %d bulundu.\n"
+
+#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375
+#: openrisc-asm.c:311 xstormy16-asm.c:334
+msgid "missing mnemonic in syntax string"
+msgstr "biçem dizgesinde ipucu eksik"
+
+#. We couldn't parse it.
+#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812
+#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764
+#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650
+#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515
+#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451
+#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470
+#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663
+msgid "unrecognized instruction"
+msgstr "bilinmeyen iÅŸlem"
+
+#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558
+#: openrisc-asm.c:494 xstormy16-asm.c:517
+#, c-format
+msgid "syntax error (expected char `%c', found `%c')"
+msgstr "biçem hatası (char `%c' beklenirken `%c' bulundu)"
+
+#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568
+#: openrisc-asm.c:504 xstormy16-asm.c:527
+#, c-format
+msgid "syntax error (expected char `%c', found end of instruction)"
+msgstr "biçem hatası (char `%c' beklenirken işlem sonu bulundu)"
+
+#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596
+#: openrisc-asm.c:532 xstormy16-asm.c:555
+msgid "junk at end of line"
+msgstr "Satır sonu bozuk "
+
+#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838
+#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662
+msgid "unrecognized form of instruction"
+msgstr "bilinmeyen işlem türü"
+
+#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850
+#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674
+#, c-format
+msgid "bad instruction `%.50s...'"
+msgstr "geçersiz işlem `%.50s...'"
+
+#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853
+#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677
+#, c-format
+msgid "bad instruction `%.50s'"
+msgstr "geçersiz işlem `%.50s'"
+
+#. Default text to print if an instruction isn't recognized.
+#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41
+#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41
+msgid "*unknown*"
+msgstr "*bilinmeyen*"
+
+#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251
+#: openrisc-dis.c:138 xstormy16-dis.c:171
+#, c-format
+msgid "Unrecognized field %d while printing insn.\n"
+msgstr "yönerge yazdırılırken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166
+#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166
+#, c-format
+msgid "operand out of range (%ld not between %ld and %lu)"
+msgstr "Kapsam dışı işlenen (%ld, %ld ve %lu arasında değil) "
+
+#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179
+#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179
+#, c-format
+msgid "operand out of range (%lu not between 0 and %lu)"
+msgstr "kapsam dışı terim (%lu 0 ve %lu arasında değil) "
+
+#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713
+#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678
+#, c-format
+msgid "Unrecognized field %d while building insn.\n"
+msgstr "Yönerge oluşturulurken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890
+#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826
+#, c-format
+msgid "Unrecognized field %d while decoding insn.\n"
+msgstr "Yönerge çözümlenirken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024
+#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939
+#, c-format
+msgid "Unrecognized field %d while getting int operand.\n"
+msgstr "`int' terimi alınırken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138
+#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032
+#, c-format
+msgid "Unrecognized field %d while getting vma operand.\n"
+msgstr "`vma' terimi alınırken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261
+#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134
+#, c-format
+msgid "Unrecognized field %d while setting int operand.\n"
+msgstr "`int' terimi atanırken bilinmeyen alan %d bulundu.\n"
+
+#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372
+#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224
+#, c-format
+msgid "Unrecognized field %d while setting vma operand.\n"
+msgstr "`vma' terimi atanırken bilinmeyen alan %d bulundu.\n"
+
+#: frv-asm.c:365
+msgid "register number must be even"
+msgstr "yazmaç çift sayı olmalı"
+
+#: h8300-dis.c:377
+#, c-format
+msgid "Hmmmm 0x%x"
+msgstr "Hmmmm 0x%x"
+
+#: h8300-dis.c:760
+#, c-format
+msgid "Don't understand 0x%x \n"
+msgstr "0x%x anlaşılamadı\n"
+
+#: h8500-dis.c:143
+#, c-format
+msgid "can't cope with insert %d\n"
+msgstr "insert %d yaptırılamıyor\n"
+
+#. Couldn't understand anything.
+#: h8500-dis.c:350
+#, c-format
+msgid "%02x\t\t*unknown*"
+msgstr "%02x\t\t*bilinmeyen*"
+
+#: i386-dis.c:1699
+msgid "<internal disassembler error>"
+msgstr "<iç karşıt-çevirici hatası>"
+
+#: ia64-gen.c:295
+#, c-format
+msgid "%s: Error: "
+msgstr "%s: Hata: "
+
+#: ia64-gen.c:308
+#, c-format
+msgid "%s: Warning: "
+msgstr "%s: Uyarı: "
+
+#: ia64-gen.c:494 ia64-gen.c:728
+#, c-format
+msgid "multiple note %s not handled\n"
+msgstr "çoklu not %s desteklenmiyor\n"
+
+#: ia64-gen.c:605
+msgid "can't find ia64-ic.tbl for reading\n"
+msgstr "ia64-ic.tbl okunmak için bulunamadı\n"
+
+#: ia64-gen.c:810
+#, c-format
+msgid "can't find %s for reading\n"
+msgstr "%s okunmak için bulunamadı\n"
+
+#: ia64-gen.c:1034
+#, c-format
+msgid ""
+"most recent format '%s'\n"
+"appears more restrictive than '%s'\n"
+msgstr ""
+"en son biçem '%s'\n"
+"'%s'dan daha kısıtlayıcı\n"
+
+#: ia64-gen.c:1045
+#, c-format
+msgid "overlapping field %s->%s\n"
+msgstr "üstüste binmiş alan %s->%s\n"
+
+#: ia64-gen.c:1236
+#, c-format
+msgid "overwriting note %d with note %d (IC:%s)\n"
+msgstr "%2$d notu %1$d notunun üstüne yazılıyor (IC:%3$s)\n"
+
+#: ia64-gen.c:1435
+#, c-format
+msgid "don't know how to specify %% dependency %s\n"
+msgstr "%% %s bağımlılığının nasıl tanımlanacağı bilinmiyor\n"
+
+#: ia64-gen.c:1457
+#, c-format
+msgid "Don't know how to specify # dependency %s\n"
+msgstr "# %s bağımlılığının nasıl tanımlanacağı bilinmiyor\n"
+
+#: ia64-gen.c:1496
+#, c-format
+msgid "IC:%s [%s] has no terminals or sub-classes\n"
+msgstr "IC: %s [%s]'nin değişmez simgeleri veya alt sınıfları yok\n"
+
+#: ia64-gen.c:1499
+#, c-format
+msgid "IC:%s has no terminals or sub-classes\n"
+msgstr "IC: %s'nin değişmez simgeleri veya alt sınıfları yok\n"
+
+#: ia64-gen.c:1508
+#, c-format
+msgid "no insns mapped directly to terminal IC %s [%s]"
+msgstr "deÄŸiÅŸmez simge IC %s [%s]'ye direkt eÅŸleÅŸen iÅŸlem yok "
+
+#: ia64-gen.c:1511
+#, c-format
+msgid "no insns mapped directly to terminal IC %s\n"
+msgstr "deÄŸiÅŸmez simge IC %s'ye direkt eÅŸleÅŸen iÅŸlem yok\n"
+
+#: ia64-gen.c:1522
+#, c-format
+msgid "class %s is defined but not used\n"
+msgstr "%s sınıfı tanımlanmış fakat kullanılmamış\n"
+
+#: ia64-gen.c:1533
+#, c-format
+msgid "Warning: rsrc %s (%s) has no chks%s\n"
+msgstr "Uyarı: rsrc %s (%s) içinde kontrol yok %s\n"
+
+#: ia64-gen.c:1537
+#, c-format
+msgid "rsrc %s (%s) has no regs\n"
+msgstr "rsrc %s (%s) içinde yazmaç yok\n"
+
+#: ia64-gen.c:2436
+#, c-format
+msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "(IC:%3$s) opkod %2$s içinde IC notu %1$d, %4$s kaynağı %5$d notuyla çelişiyor\n"
+
+#: ia64-gen.c:2464
+#, c-format
+msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"
+msgstr "(IC:%3$s) opkod %2$s için IC notu %1$d, %4$s kaynağı %5$d notuyla çelişiyor\n"
+
+#: ia64-gen.c:2478
+#, c-format
+msgid "opcode %s has no class (ops %d %d %d)\n"
+msgstr "%s opkodunun sınıfları yok (ops %d %d %d)\n"
+
+#: ia64-gen.c:2789
+#, c-format
+msgid "unable to change directory to \"%s\", errno = %s\n"
+msgstr "\"%s\" dizinine geçilemedi, hatano = %s\n"
+
+#. We've been passed a w.  Return with an error message so that
+#. cgen will try the next parsing option.
+#: ip2k-asm.c:92
+msgid "W keyword invalid in FR operand slot."
+msgstr "FR işlenen slotunda W anahtar kelimesi geçersiz."
+
+#. Invalid offset present.
+#: ip2k-asm.c:122
+msgid "offset(IP) is not a valid form"
+msgstr "görece(IP) geçerli biçimde değil"
+
+#. Found something there in front of (DP) but it's out
+#. of range.
+#: ip2k-asm.c:175
+msgid "(DP) offset out of range."
+msgstr "(DP) görecesi aralık dışı."
+
+#. Found something there in front of (SP) but it's out
+#. of range.
+#: ip2k-asm.c:221
+msgid "(SP) offset out of range."
+msgstr "(SP) görece aralık dışı."
+
+#: ip2k-asm.c:241
+msgid "illegal use of parentheses"
+msgstr "parantezlerin geçersiz kullanımı"
+
+#: ip2k-asm.c:248
+msgid "operand out of range (not between 1 and 255)"
+msgstr "kapsam dışı işlenen (1 ve 255 arasında değil)"
+
+#. Something is very wrong. opindex has to be one of the above.
+#: ip2k-asm.c:273
+msgid "parse_addr16: invalid opindex."
+msgstr "parse_addr16: geçersiz opindeks."
+
+#: ip2k-asm.c:353
+msgid "Byte address required. - must be even."
+msgstr "Bayt adresi gerekli. - çift sayı olmalı."
+
+#: ip2k-asm.c:362
+msgid "cgen_parse_address returned a symbol. Literal required."
+msgstr "cgen_parse_address bir sembol döndürdü. Sabit gerekli."
+
+#: ip2k-asm.c:420
+#, c-format
+msgid "%operator operand is not a symbol"
+msgstr "%operator iÅŸleneni sembol deÄŸil"
+
+#: ip2k-asm.c:474
+msgid "Attempt to find bit index of 0"
+msgstr "0'ın bit indeksini bulma denemesi"
+
+#: iq2000-asm.c:110 iq2000-asm.c:141
+msgid "immediate value cannot be register"
+msgstr "şimdiki değer yazmaç olamaz"
+
+#: iq2000-asm.c:120 iq2000-asm.c:151
+msgid "immediate value out of range"
+msgstr "şimdiki değer kapsam dışı"
+
+#: iq2000-asm.c:180
+msgid "21-bit offset out of range"
+msgstr "21 bit görece değer aralık dışı"
+
+#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305
+#: openrisc-asm.c:96 openrisc-asm.c:155
+msgid "missing `)'"
+msgstr "eksik `)'"
+
+#: m10200-dis.c:199
+#, c-format
+msgid "unknown\t0x%02x"
+msgstr "bilinmeyen\t0x%02x"
+
+#: m10200-dis.c:339
+#, c-format
+msgid "unknown\t0x%04lx"
+msgstr "bilinmeyen\t0x%04lx"
+
+#: m10300-dis.c:766
+#, c-format
+msgid "unknown\t0x%04x"
+msgstr "bilinmeyen\t0x%04x"
+
+#: m68k-dis.c:429
+#, c-format
+msgid "<internal error in opcode table: %s %s>\n"
+msgstr "<işlemci kod tablosunda iç hata: %s %s>\n"
+
+#: m68k-dis.c:1007
+#, c-format
+msgid "<function code %d>"
+msgstr "<iÅŸlev kodu %d>"
+
+#: m88k-dis.c:746
+#, c-format
+msgid "# <dis error: %08x>"
+msgstr "# <`dis' hatası: %08x>"
+
+#: mips-dis.c:699
+msgid "# internal error, incomplete extension sequence (+)"
+msgstr "# iç hata, eksik uzatma dizisi (+)"
+
+#: mips-dis.c:742
+#, c-format
+msgid "# internal error, undefined extension sequence (+%c)"
+msgstr "# iç hata, tanımlanmamış uzatma dizisi (+%c)"
+
+#: mips-dis.c:1000
+#, c-format
+msgid "# internal error, undefined modifier(%c)"
+msgstr "#iç hata, tanımlanmamış değiştirici (%c)"
+
+#: mips-dis.c:1751
+#, c-format
+msgid "# internal disassembler error, unrecognised modifier (%c)"
+msgstr "#iç karşıt-çevirici hatası, tanımlanmamış değiştirici (%c)"
+
+#: mips-dis.c:1763
+msgid ""
+"\n"
+"The following MIPS specific disassembler options are supported for use\n"
+"with the -M switch (multiple options should be separated by commas):\n"
+msgstr ""
+"\n"
+"Aşağıdaki MIPS'e özgü karşıt-çevirici seçenekleri \n"
+"-M seçeneği ile kullanılabilir (birden fazla seçenek virgülle ayrılmalıdır):\n"
+
+#: mips-dis.c:1767
+msgid ""
+"\n"
+"  gpr-names=ABI            Print GPR names according to  specified ABI.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  gpr-names=ABI            Belirtilen ABI'ye göre GPR isimlerini gösterir.\n"
+"                           Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n"
+
+#: mips-dis.c:1771
+msgid ""
+"\n"
+"  fpr-names=ABI            Print FPR names according to specified ABI.\n"
+"                           Default: numeric.\n"
+msgstr ""
+"\n"
+"  fpr-names=ABI            Belirtilen ABI'ye göre FPR isimlerini gösterir.\n"
+"                           Öntanımlı: sayısal.\n"
+
+#: mips-dis.c:1775
+msgid ""
+"\n"
+"  cp0-names=ARCH           Print CP0 register names according to\n"
+"                           specified architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  cp0-names=MİMARİ         Belirtilen mimariye göre CP0 yazmaç isimlerini\n"
+"                           gösterir.\n"
+"                           Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n"
+
+#: mips-dis.c:1780
+msgid ""
+"\n"
+"  hwr-names=ARCH           Print HWR names according to specified \n"
+"\t\t\t   architecture.\n"
+"                           Default: based on binary being disassembled.\n"
+msgstr ""
+"\n"
+"  hwr-names=MİMARİ         Belirtilen mimariye göre HWR isimlerini gösterir.\n"
+"                           Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n"
+
+#: mips-dis.c:1785
+msgid ""
+"\n"
+"  reg-names=ABI            Print GPR and FPR names according to\n"
+"                           specified ABI.\n"
+msgstr ""
+"\n"
+"  reg-names=ABI            Belirtilen ABI'ye göre GPR ve FPR isimlerini\n"
+"                           gösterir.\n"
+
+#: mips-dis.c:1789
+msgid ""
+"\n"
+"  reg-names=ARCH           Print CP0 register and HWR names according to\n"
+"                           specified architecture.\n"
+msgstr ""
+"\n"
+"  reg-names=MİMARİ         Belirtilen mimariye göre CP0 yazmaç ve HWR\n"
+"                           isimlerini gösterir.\n"
+
+#: mips-dis.c:1793
+msgid ""
+"\n"
+"  For the options above, the following values are supported for \"ABI\":\n"
+"   "
+msgstr ""
+"\n"
+"  Yukarıdaki seçeneklere göre \"ABI\" için aşağıdaki değerler desteklenir:\n"
+"   "
+
+#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808
+msgid "\n"
+msgstr "\n"
+
+#: mips-dis.c:1800
+msgid ""
+"\n"
+"  For the options above, The following values are supported for \"ARCH\":\n"
+"   "
+msgstr ""
+"\n"
+"  Yukarıdaki seçeneklere göre \"ARCH\" için aşağıdaki değerler desteklenir:\n"
+"   "
+
+#: mmix-dis.c:34
+#, c-format
+msgid "Bad case %d (%s) in %s:%d\n"
+msgstr "Hatalı durum %d (%s), %s içerisinde:%d\n"
+
+#: mmix-dis.c:44
+#, c-format
+msgid "Internal: Non-debugged code (test-case missing): %s:%d"
+msgstr "İç Hata: Hata ayıklanmamış kod (test eksik): %s:%d"
+
+#: mmix-dis.c:53
+msgid "(unknown)"
+msgstr "(bilinmeyen)"
+
+#: mmix-dis.c:519
+#, c-format
+msgid "*unknown operands type: %d*"
+msgstr "bilinmeyen işlenen türü: %d*"
+
+#. I and Z are output operands and can`t be immediate
+#. * A is an address and we can`t have the address of
+#. * an immediate either. We don't know how much to increase
+#. * aoffsetp by since whatever generated this is broken
+#. * anyway!
+#.
+#: ns32k-dis.c:631
+msgid "$<undefined>"
+msgstr "$<tanımlanmamış>"
+
+#: ppc-opc.c:781 ppc-opc.c:809
+msgid "invalid conditional option"
+msgstr "koşullu seçenek geçersiz "
+
+#: ppc-opc.c:811
+msgid "attempt to set y bit when using + or - modifier"
+msgstr "+ veya - değiştiricisini kullanırken y bitini atama denemesi"
+
+#: ppc-opc.c:840
+msgid "offset not a multiple of 16"
+msgstr "görece 16'nın katı değil"
+
+#: ppc-opc.c:860
+msgid "offset not a multiple of 2"
+msgstr "görece 2'nin katı değil"
+
+#: ppc-opc.c:862
+msgid "offset greater than 62"
+msgstr "görece 62'den büyük"
+
+#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975
+msgid "offset not a multiple of 4"
+msgstr "görece 4'ün katı değil"
+
+#: ppc-opc.c:883
+msgid "offset greater than 124"
+msgstr "görece 124'ten büyük"
+
+#: ppc-opc.c:902
+msgid "offset not a multiple of 8"
+msgstr "görece 8'in katı değil"
+
+#: ppc-opc.c:904
+msgid "offset greater than 248"
+msgstr "görece 248'den büyük"
+
+#: ppc-opc.c:950
+msgid "offset not between -2048 and 2047"
+msgstr "görece -2048 ve 2047 arasında değil"
+
+#: ppc-opc.c:973
+msgid "offset not between -8192 and 8191"
+msgstr "görece -8192 ve 8191 arasında değil"
+
+#: ppc-opc.c:1011
+msgid "ignoring invalid mfcr mask"
+msgstr "geçersiz mfcr maskesi yoksayıldı"
+
+#: ppc-opc.c:1059
+msgid "ignoring least significant bits in branch offset"
+msgstr "Dal göreli konumunda en önemsiz bitler atlanıyor"
+
+#: ppc-opc.c:1090 ppc-opc.c:1125
+msgid "illegal bitmask"
+msgstr "geçersiz bitmask "
+
+#: ppc-opc.c:1192
+msgid "value out of range"
+msgstr "değer aralık dışı"
+
+#: ppc-opc.c:1262
+msgid "index register in load range"
+msgstr "yükleme aralığında endeks yazmacı"
+
+#: ppc-opc.c:1279
+msgid "source and target register operands must be different"
+msgstr "kaynak ve hedef yazmaç işlenenleri farklı olmalı"
+
+#: ppc-opc.c:1294
+msgid "invalid register operand when updating"
+msgstr "güncelleme esnasında geçersiz yazmaç terimi bulundu"
+
+#: ppc-opc.c:1335
+msgid "target register operand must be even"
+msgstr "hedef yazmaç işleneni çift sayı olmalı"
+
+#: ppc-opc.c:1350
+msgid "source register operand must be even"
+msgstr "kaynak yazmaç işleneni çift sayı olmalı"
+
+#. Mark as non-valid instruction.
+#: sparc-dis.c:760
+msgid "unknown"
+msgstr "bilinmeyen"
+
+#: sparc-dis.c:835
+#, c-format
+msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:846
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
+
+#: sparc-dis.c:895
+#, c-format
+msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
+msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\" == \"%s\"\n"
+
+#: v850-dis.c:221
+#, c-format
+msgid "unknown operand shift: %x\n"
+msgstr "bilinmeyen terim kaydırması: %x\n"
+
+#: v850-dis.c:233
+#, c-format
+msgid "unknown pop reg: %d\n"
+msgstr "bilinmeyen çek yazmacı: %d\n"
+
+#. The functions used to insert and extract complicated operands.
+#. Note: There is a conspiracy between these functions and
+#. v850_insert_operand() in gas/config/tc-v850.c.  Error messages
+#. containing the string 'out of range' will be ignored unless a
+#. specific command line option is given to GAS.
+#: v850-opc.c:68
+msgid "displacement value is not in range and is not aligned"
+msgstr "yer değiştirme değeri kapsam dışında ve hizalanmamış"
+
+#: v850-opc.c:69
+msgid "displacement value is out of range"
+msgstr "yer değiştirme değeri kapsam dışında"
+
+#: v850-opc.c:70
+msgid "displacement value is not aligned"
+msgstr "yer değiştirme değeri hizalanmamış"
+
+#: v850-opc.c:72
+msgid "immediate value is out of range"
+msgstr "şimdiki değer kapsam dışı"
+
+#: v850-opc.c:83
+msgid "branch value not in range and to odd offset"
+msgstr "dal değeri kapsam dışında ve tek sayılı göreli konuma işaret ediyor"
+
+#: v850-opc.c:85 v850-opc.c:117
+msgid "branch value out of range"
+msgstr "dal değeri kapsam dışında "
+
+#: v850-opc.c:88 v850-opc.c:120
+msgid "branch to odd offset"
+msgstr "dallanma tek sayılı göreli konuma işaret ediyor"
+
+#: v850-opc.c:115
+msgid "branch value not in range and to an odd offset"
+msgstr "dal değeri kapsam dışında ve tek sayılı göreli konuma işaret ediyor"
+
+#: v850-opc.c:346
+msgid "invalid register for stack adjustment"
+msgstr "yığıt düzeltmesi için geçersiz yazmaç "
+
+#: v850-opc.c:370
+msgid "immediate value not in range and not even"
+msgstr "şimdiki değer kapsam dışı ve çift sayı değil"
+
+#: v850-opc.c:375
+msgid "immediate value must be even"
+msgstr "şimdiki değer çift sayı olmalı"
+
+#: xstormy16-asm.c:76
+msgid "Bad register in preincrement"
+msgstr "Arttırma öncesinde geçersiz yazmaç"
+
+#: xstormy16-asm.c:81
+msgid "Bad register in postincrement"
+msgstr "Arttırma sonrasında  geçersiz yazmaç "
+
+#: xstormy16-asm.c:83
+msgid "Bad register name"
+msgstr "Geçersiz yazmaç adı"
+
+#: xstormy16-asm.c:87
+msgid "Label conflicts with register name"
+msgstr "Etiket, yazmaç adıyla çakışıyor"
+
+#: xstormy16-asm.c:91
+msgid "Label conflicts with `Rx'"
+msgstr "Etiket, `Rx' ile çakışıyor"
+
+#: xstormy16-asm.c:93
+msgid "Bad immediate expression"
+msgstr "Hatalı şimdiki ifade"
+
+#: xstormy16-asm.c:115
+msgid "No relocation for small immediate"
+msgstr "Küçük şimdiki için yerdeğiştirme yok"
+
+#: xstormy16-asm.c:125
+msgid "Small operand was not an immediate number"
+msgstr "Küçük işlenen şimdiki sayı değil"
+
+#: xstormy16-asm.c:164
+msgid "Operand is not a symbol"
+msgstr "Ä°ÅŸlenen bir sembol deÄŸil"
+
+#: xstormy16-asm.c:172
+msgid "Syntax error: No trailing ')'"
+msgstr "Sözdizim hatası: Sonlandıran ')' yok"
diff --git a/gnu/usr.bin/binutils/opcodes/s390-dis.c b/gnu/usr.bin/binutils/opcodes/s390-dis.c
index 33121c78b70..42f5151d3f0 100644
--- a/gnu/usr.bin/binutils/opcodes/s390-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/s390-dis.c
@@ -89,6 +89,10 @@ s390_extract_operand (insn, operand)
   val >>= -bits;
   val &= ((1U << (operand->bits - 1)) << 1) - 1;
 
+  /* Check for special long displacement case.  */
+  if (operand->bits == 20 && operand->shift == 20)
+    val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
+
   /* Sign extend value if the operand is signed or pc relative.  */
   if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
       && (val & (1U << (operand->bits - 1))))
diff --git a/gnu/usr.bin/binutils/opcodes/s390-mkopc.c b/gnu/usr.bin/binutils/opcodes/s390-mkopc.c
index caa9993a881..34188e6216f 100644
--- a/gnu/usr.bin/binutils/opcodes/s390-mkopc.c
+++ b/gnu/usr.bin/binutils/opcodes/s390-mkopc.c
@@ -34,7 +34,8 @@ enum s390_opcode_cpu_val
   {
     S390_OPCODE_G5 = 0,
     S390_OPCODE_G6,
-    S390_OPCODE_Z900
+    S390_OPCODE_Z900,
+    S390_OPCODE_Z990
   };
 
 struct op_struct
@@ -192,6 +193,8 @@ main (void)
 	    min_cpu = S390_OPCODE_G6;
 	  else if (strcmp (cpu_string, "z900") == 0)
 	    min_cpu = S390_OPCODE_Z900;
+	  else if (strcmp (cpu_string, "z990") == 0)
+	    min_cpu = S390_OPCODE_Z990;
 	  else {
 	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
 	    exit (1);
diff --git a/gnu/usr.bin/binutils/opcodes/s390-opc.c b/gnu/usr.bin/binutils/opcodes/s390-opc.c
index a2837833d74..1a4b276a643 100644
--- a/gnu/usr.bin/binutils/opcodes/s390-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/s390-opc.c
@@ -98,33 +98,35 @@ const struct s390_operand s390_operands[] =
   { 12, 20, S390_OPERAND_DISP },
 #define D_36   25                 /* Displacement starting at position 36 */
   { 12, 36, S390_OPERAND_DISP },
+#define D20_20 26		  /* 20 bit displacement starting at 20 */
+  { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
 
-#define L4_8   26                 /* 4 bit length starting at position 8 */
+#define L4_8   27                 /* 4 bit length starting at position 8 */
   { 4, 8, S390_OPERAND_LENGTH },
-#define L4_12  27                 /* 4 bit length starting at position 12 */
+#define L4_12  28                 /* 4 bit length starting at position 12 */
   { 4, 12, S390_OPERAND_LENGTH },
-#define L8_8   28                 /* 8 bit length starting at position 8 */
+#define L8_8   29                 /* 8 bit length starting at position 8 */
   { 8, 8, S390_OPERAND_LENGTH },
 
-#define U4_8   29                 /* 4 bit unsigned value starting at 8 */
+#define U4_8   30                 /* 4 bit unsigned value starting at 8 */
   { 4, 8, 0 },
-#define U4_12  30                 /* 4 bit unsigned value starting at 12 */
+#define U4_12  31                 /* 4 bit unsigned value starting at 12 */
   { 4, 12, 0 },
-#define U4_16  31                 /* 4 bit unsigned value starting at 16 */
+#define U4_16  32                 /* 4 bit unsigned value starting at 16 */
   { 4, 16, 0 },
-#define U4_20  32                 /* 4 bit unsigned value starting at 20 */
+#define U4_20  33                 /* 4 bit unsigned value starting at 20 */
   { 4, 20, 0 },
-#define U8_8   33                 /* 8 bit unsigned value starting at 8 */
+#define U8_8   34                 /* 8 bit unsigned value starting at 8 */
   { 8, 8, 0 },
-#define U8_16  34                 /* 8 bit unsigned value starting at 16 */
+#define U8_16  35                 /* 8 bit unsigned value starting at 16 */
   { 8, 16, 0 },
-#define I16_16 35                 /* 16 bit signed value starting at 16 */
+#define I16_16 36                 /* 16 bit signed value starting at 16 */
   { 16, 16, S390_OPERAND_SIGNED },
-#define U16_16 36                 /* 16 bit unsigned value starting at 16 */
+#define U16_16 37                 /* 16 bit unsigned value starting at 16 */
   { 16, 16, 0 },
-#define J16_16 37                 /* PC relative jump offset at 16 */
+#define J16_16 38                 /* PC relative jump offset at 16 */
   { 16, 16, S390_OPERAND_PCREL },
-#define J32_16 38                 /* PC relative long offset at 16 */
+#define J32_16 39                 /* PC relative long offset at 16 */
   { 32, 16, S390_OPERAND_PCREL }
 };
 
@@ -194,6 +196,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
+#define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 }           /* e.g. idte  */
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. cfxbr */
 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfebr */
 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfxbr */
@@ -205,7 +208,11 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
+#define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 }            /* e.g. tp    */
 #define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
+#define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
+#define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
+#define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
@@ -215,11 +222,14 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
 #define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
 #define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
+#define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
+#define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
 #define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
 #define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
 #define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
 #define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
 #define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
+#define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
 #define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
 #define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
 #define INSTR_SS_LIRDRD  6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
@@ -253,6 +263,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
@@ -264,21 +275,28 @@ const struct s390_operand s390_operands[] =
 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -303,11 +321,14 @@ const struct s390_opcode s390_opformats[] =
   { "rs",	OP8(0x00LL),	MASK_RS_RRRD,	INSTR_RS_RRRD,	3, 0 },
   { "rse",	OP8(0x00LL),	MASK_RSE_RRRD,	INSTR_RSE_RRRD,	3, 0 },
   { "rsi",	OP8(0x00LL),	MASK_RSI_RRP,	INSTR_RSI_RRP,	3, 0 },
+  { "rsy",	OP8(0x00LL),	MASK_RSY_RRRD,	INSTR_RSY_RRRD,	3, 3 },
   { "rx",	OP8(0x00LL),	MASK_RX_RRRD,	INSTR_RX_RRRD,	3, 0 },
   { "rxe",	OP8(0x00LL),	MASK_RXE_RRRD,	INSTR_RXE_RRRD,	3, 0 },
   { "rxf",	OP8(0x00LL),	MASK_RXF_RRRDR,	INSTR_RXF_RRRDR,3, 0 },
+  { "rxy",	OP8(0x00LL),	MASK_RXY_RRRD,	INSTR_RXY_RRRD,	3, 3 },
   { "s",	OP8(0x00LL),	MASK_S_RD,	INSTR_S_RD,	3, 0 },
   { "si",	OP8(0x00LL),	MASK_SI_URD,	INSTR_SI_URD,	3, 0 },
+  { "siy",	OP8(0x00LL),	MASK_SIY_URD,	INSTR_SIY_URD,	3, 3 },
   { "ss",	OP8(0x00LL),	MASK_SS_RRRDRD,	INSTR_SS_RRRDRD,3, 0 },
   { "sse",	OP8(0x00LL),	MASK_SSE_RDRD,	INSTR_SSE_RDRD,	3, 0 },
 };
diff --git a/gnu/usr.bin/binutils/opcodes/s390-opc.txt b/gnu/usr.bin/binutils/opcodes/s390-opc.txt
index f0b7f83d251..be08c829dd7 100644
--- a/gnu/usr.bin/binutils/opcodes/s390-opc.txt
+++ b/gnu/usr.bin/binutils/opcodes/s390-opc.txt
@@ -109,6 +109,8 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch
 b1 lra RX_RRRD "load real address" g5 esa,zarch
 25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
 35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
+25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch
+35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch
 22 ltdr RR_FF "load and test (long)" g5 esa,zarch
 32 lter RR_FF "load and test (short)" g5 esa,zarch
 12 ltr RR_RR "load and test" g5 esa,zarch
@@ -118,7 +120,9 @@ af mc SI_URD "monitor call" g5 esa,zarch
 6c md RX_FRRD "multiply (long)" g5 esa,zarch
 2c mdr RR_FF "multiply (long)" g5 esa,zarch
 7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
+7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch
 3c mer RR_FF "multiply (short to long)" g5 esa,zarch
+3c mder RR_FF "multiply short to long hfp" g5 esa,zarch
 4c mh RX_RRRD "multiply halfword" g5 esa,zarch
 fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch
 1c mr RR_RR "multiply" g5 esa,zarch
@@ -623,3 +627,167 @@ e30000000090 llgc RXE_RRRD "load logical character" z900 zarch
 e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch
 eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch
 eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch
+b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch
+b3b6 cxfr RRE_RF "convert from fixed 32 to extended hfp" g5 esa,zarch
+b3b5 cdfr RRE_RF "convert from fixed 32 to long hfp" g5 esa,zarch
+b3b4 cefr RRE_RF "convert from fixed 32 to short hfp" g5 esa,zarch
+b3ba cfxr RRF_U0FR "convert to fixed extended hfp to 32" z900 zarch
+b3b9 cfdr RRF_U0FR "convert to fixed long hfp to 32" z900 zarch
+b3b8 cfer RRF_U0FR "convert to fixed short hfp to 32" z900 zarch
+b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch
+b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch
+b367 fixr RRF_U0FF "load fp integer extended hfp" g5 esa,zarch
+b37f fidr RRF_U0FF "load fp integer long hfp" g5 esa,zarch
+b377 fier RRF_U0FF "load fp integer short hfp" g5 esa,zarch
+b325 lxdr RRE_FF "load lengthened long to extended hfp" g5 esa,zarch
+ed0000000025 lxd RXE_FRRD "load lengthened long to extended hfp" g5 esa,zarch
+b326 lxer RRE_FF "load lengthened short to extended hfp" g5 esa,zarch
+ed0000000026 lxe RXE_FRRD "load lengthened short to extended hfp" g5 esa,zarch
+b324 lder RRE_FF "load lengthened short to long hfp" g5 esa,zarch
+ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch
+b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch
+b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch
+b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch
+35 ledr RR_FF "load rounded long to short hfp" g5 esa,zarch
+b337 meer RRE_FF "multiply short hfp" g5 esa,zarch
+ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch
+b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch
+ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch
+b263 cmpsc RRE_RR "compression call" g5 esa,zarch
+eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch
+b365 lxr RRE_RR "load extended hfp" g5 esa,zarch
+b22e pgin RRE_RR "page in" g5 esa,zarch
+b22f pgout RRE_RR "page out" g5 esa,zarch
+b276 xsch S_00 "cancel subchannel" g5 esa,zarch
+# New long displacement instructions on z990
+e3000000005a ay RXY_RRRD "add with long offset" z990 zarch
+e3000000007a ahy RXY_RRRD "add halfword with long offset" z990 zarch
+e3000000005e aly RXY_RRRD "add logical with long offset" z990 zarch
+eb0000000054 niy SIY_URD "and immediate with long offset" z990 zarch
+e30000000054 ny RXY_RRRD "and with long offset" z990 zarch
+e30000000059 cy RXY_RRRD "compare with long offset" z990 zarch
+eb0000000014 csy RSY_RRRD "compare and swap with long offset" z990 zarch
+eb0000000031 cdsy RSY_RRRD "compare double and swap with long offset" z990 zarch
+e30000000079 chy RXY_RRRD "compare halfword with long offset" z990 zarch
+e30000000055 cly RXY_RRRD "compare logical with long offset" z990 zarch
+eb0000000055 cliy SIY_URD "compare logical immediate with long offset" z990 zarch
+eb0000000021 clmy RSY_RURD "compare logical characters under mask with long offset" z990 zarch
+e30000000006 cvby RXY_RRRD "convert to binary with long offset" z990 zarch
+e30000000026 cvdy RXY_RRRD "convert to decimal with long offset" z990 zarch
+eb0000000057 xiy SIY_URD "exclusive or immediate with long offset" z990 zarch
+e30000000057 xy RXY_RRRD "exclusive or with long offset" z990 zarch
+e30000000073 icy RXY_RRRD "insert character with long offset" z990 zarch
+eb0000000081 icmy RSY_RURD "insert characters with long offset" z990 zarch
+ed0000000065 ldy RXY_FRRD "load (long) with long offset" z990 zarch
+ed0000000064 ley RXY_FRRD "load (short) with long offset" z990 zarch
+e30000000058 ly RXY_RRRD "load with long offset" z990 zarch
+eb000000009a lamy RSY_AARD "load access multiple" z990 zarch
+e30000000071 lay RXY_RRRD "load address with long offset" z990 zarch
+e30000000076 lb RXY_RRRD "load byte with long offset" z990 zarch
+e30000000077 lgb RXY_RRRD "load byte with long offset 64" z990 zarch
+e30000000078 lhy RXY_RRRD "load halfword with long offset" z990 zarch
+eb0000000098 lmy RSY_RRRD "load multiple with long offset" z990 zarch
+e30000000013 lray RXY_RRRD "load real address with long offset" z990 zarch
+eb0000000052 mviy SIY_URD "move immediate with long offset" z990 zarch
+e30000000051 msy RXY_RRRD "multiply single with long offset" z990 zarch
+eb0000000056 oiy SIY_URD "or immediate with long offset" z990 zarch
+e30000000056 oy RXY_RRRD "or with long offset" z990 zarch
+ed0000000067 stdy RXY_FRRD "load (long) with long offset" z990 zarch
+ed0000000066 stey RXY_FRRD "load (short) with long offset" z990 zarch
+e30000000050 sty RXY_RRRD "store with long offset" z990 zarch
+eb000000009b stamy RSY_AARD "store access multiple with long offset" z990 zarch
+e30000000072 stcy RXY_RRRD "store character with long offset" z990 zarch
+eb000000002d stcmy RSY_RURD "store characters under mask with long offset" z990 zarch
+e30000000070 sthy RXY_RRRD "store halfword with long offset" z990 zarch
+eb0000000090 stmy RSY_RRRD "store multiple with long offset" z990 zarch
+e3000000005b sy RXY_RRRD "subtract with long offset" z990 zarch
+e3000000007b shy RXY_RRRD "subtract halfword with long offset" z990 zarch
+e3000000005f sly RXY_RRRD "subtract logical with long offset" z990 zarch
+eb0000000051 tmy SIY_URD "test under mask with long offset" z990 zarch
+# 'old' instructions extended to long displacement
+# these instructions are entered into the opcode table twice.
+e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch
+e30000000004 lg RXY_RRRD "	 load 64" z990 zarch
+e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch
+e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch
+e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch
+e3000000000b slg RXY_RRRD "subtract logical with long offset 64" z990 zarch
+e3000000000c msg RXY_RRRD "multiply single with long offset 64" z990 zarch
+e3000000000d dsg RXY_RRRD "divide single 64" z990 zarch
+e3000000000e cvbg RXY_RRRD "convert to binary with long offset 64" z990 zarch
+e3000000000f lrvg RXY_RRRD "load reversed 64" z990 zarch
+e30000000014 lgf RXY_RRRD "load 64<32" z990 zarch
+e30000000015 lgh RXY_RRRD "load halfword 64" z990 zarch
+e30000000016 llgf RXY_RRRD "load logical 64<32" z990 zarch
+e30000000017 llgt RXY_RRRD "load logical thirty one bits" z990 zarch
+e30000000018 agf RXY_RRRD "add with long offset 64<32" z990 zarch
+e30000000019 sgf RXY_RRRD "subtract with long offset 64<32" z990 zarch
+e3000000001a algf RXY_RRRD "add logical with long offset 64<32" z990 zarch
+e3000000001b slgf RXY_RRRD "subtract logical with long offset 64<32" z990 zarch
+e3000000001c msgf RXY_RRRD "multiply single with long offset 64<32" z990 zarch
+e3000000001d dsgf RXY_RRRD "divide single 64<32" z990 zarch
+e3000000001e lrv RXY_RRRD "load reversed 32" z990 zarch
+e3000000001f lrvh RXY_RRRD "load reversed 16" z990 zarch
+e30000000020 cg RXY_RRRD "compare with long offset 64" z990 zarch
+e30000000021 clg RXY_RRRD "compare logical with long offset 64" z990 zarch
+e30000000024 stg RXY_RRRD "store with long offset 64" z990 zarch
+e3000000002e cvdg RXY_RRRD "convert to decimal with long offset 64" z990 zarch
+e3000000002f strvg RXY_RRRD "store reversed 64" z990 zarch
+e30000000030 cgf RXY_RRRD "compare with long offset 64<32" z990 zarch
+e30000000031 clgf RXY_RRRD "compare logical with long offset 64<32" z990 zarch
+e3000000003e strv RXY_RRRD "store reversed 32" z990 zarch
+e3000000003f strvh RXY_RRRD "store reversed 64" z990 zarch
+e30000000046 bctg RXY_RRRD "branch on count 64" z990 zarch
+e30000000080 ng RXY_RRRD "and with long offset 64" z990 zarch
+e30000000081 og RXY_RRRD "or with long offset 64" z990 zarch
+e30000000082 xg RXY_RRRD "exclusive or with long offset 64" z990 zarch
+e30000000086 mlg RXY_RRRD "multiply logical 64" z990 zarch
+e30000000087 dlg RXY_RRRD "divide logical 64" z990 zarch
+e30000000088 alcg RXY_RRRD "add logical with carry 64" z990 zarch
+e30000000089 slbg RXY_RRRD "subtract logical with borrow 64" z990 zarch
+e3000000008e stpq RXY_RRRD "store pair to quadword" z990 zarch
+e3000000008f lpq RXY_RRRD "load pair from quadword" z990 zarch
+e30000000090 llgc RXY_RRRD "load logical character" z990 zarch
+e30000000091 llgh RXY_RRRD "load logical halfword" z990 zarch
+e30000000096 ml RXY_RRRD "multiply logical 32" z990 zarch
+e30000000097 dl RXY_RRRD "divide logical 32" z990 zarch
+e30000000098 alc RXY_RRRD "add logical with carry 32" z990 zarch
+e30000000099 slb RXY_RRRD "subtract logical with borrow 32" z990 zarch
+eb0000000004 lmg RSY_RRRD "load multiple with long offset 64" z990 zarch
+eb000000000a srag RSY_RRRD "shift right single 64" z990 zarch
+eb000000000b slag RSY_RRRD "shift left single 64" z990 zarch
+eb000000000c srlg RSY_RRRD "shift right single logical 64" z990 zarch
+eb000000000d sllg RSY_RRRD "shift left single logical 64" z990 zarch
+eb000000000f tracg RSY_RRRD "trace 64" z990 zarch
+eb000000001c rllg RSY_RRRD "rotate left single logical 64" z990 zarch
+eb000000001d rll RSY_RRRD "rotate left single logical 32" z990 zarch
+eb0000000020 clmh RSY_RURD "compare logical characters under mask high with long offset" z990 zarch
+eb0000000024 stmg RSY_RRRD "store multiple with long offset 64" z990 zarch
+eb0000000025 stctg RSY_RRRD "store control 64" z990 zarch
+eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch
+eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch
+eb000000002f lctlg RSY_RRRD "load control 64" z990 zarch
+eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch
+eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch
+eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch
+eb0000000045 bxleg RSY_RRRD "branch on index low or equal 64" z990 zarch
+eb0000000080 icmh RSY_RURD "insert characters under mask high with long offset" z990 zarch
+eb000000008e mvclu RSY_RRRD "move long unicode" z990 zarch
+eb000000008f clclu RSY_RRRD "compare logical long unicode with long offset" z990 zarch
+eb0000000096 lmh RSY_RRRD "load multiple high" z990 zarch
+# new z990 instructions
+b98a cspg RRE_RR "compare and swap and purge" z990 zarch
+b98e idte RRF_R0RR "invalidate dat table entry" z990 zarch
+b33e madr RRF_F0FF "multiply and add long hfp" z990 esa,zarch
+ed000000003e mad RXF_FRRDF "multiply and add long hfp" z990 esa,zarch
+b32e maer RRF_F0FF "multiply and add short hfp" z990 esa,zarch
+ed000000002e mae RXF_FRRDF "multiply and add shoft hfp" z990 esa,zarch
+b33f msdr RRF_F0FF "multiply and subtract long hfp" z990 esa,zarch
+ed000000003f msd RXF_FRRDF "multiply and subtract long hfp" z990 esa,zarch
+b32f mser RRF_F0FF "mutliply and subtract short hfp" z990 esa,zarch
+ed000000002f mse RXF_FRRDF "multiply and subttract short hfp" z990 esa,zarch
+b92e km RRE_RR "cipher message" z990 esa,zarch
+b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch
+b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch
+b93f klmd RRE_RR "compute last message digest" z990 esa,zarch
+b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch
diff --git a/gnu/usr.bin/binutils/opcodes/v850-dis.c b/gnu/usr.bin/binutils/opcodes/v850-dis.c
index 7c449f67ad1..b5022cd42d0 100644
--- a/gnu/usr.bin/binutils/opcodes/v850-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/v850-dis.c
@@ -1,20 +1,20 @@
 /* Disassemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 
 #include <stdio.h>
@@ -78,6 +78,10 @@ disassemble (memaddr, info, insn)
     case bfd_mach_v850e:
       target_processor = PROCESSOR_V850E;
       break;
+
+    case bfd_mach_v850e1:
+      target_processor = PROCESSOR_V850E1;
+      break;
     }
   
   /* Find the opcode.  */
diff --git a/gnu/usr.bin/binutils/opcodes/v850-opc.c b/gnu/usr.bin/binutils/opcodes/v850-opc.c
index 94969ac48f2..2249d16803d 100644
--- a/gnu/usr.bin/binutils/opcodes/v850-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/v850-opc.c
@@ -1,37 +1,37 @@
 /* Assemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "opcode/v850.h"
 #include <stdio.h>
 #include "opintl.h"
 
-/* regular opcode */
+/* Regular opcodes.  */
 #define OP(x)		((x & 0x3f) << 5)
 #define OP_MASK		OP (0x3f)
 
-/* conditional branch opcode */
+/* Conditional branch opcodes.  */
 #define BOP(x)		((0x0b << 7) | (x & 0x0f))
 #define BOP_MASK	((0x0f << 7) | 0x0f)
 
-/* one-word opcodes */
+/* One-word opcodes.  */
 #define one(x)		((unsigned int) (x))
 
-/* two-word opcodes */
+/* Two-word opcodes.  */
 #define two(x,y)	((unsigned int) (x) | ((unsigned int) (y) << 16))
 
 static long unsigned insert_d9      PARAMS ((long unsigned, long, const char **));
@@ -402,15 +402,15 @@ const struct v850_operand v850_operands[] =
 #define UNUSED	0
   { 0, 0, NULL, NULL, 0 }, 
 
-/* The R1 field in a format 1, 6, 7, or 9 insn. */
+/* The R1 field in a format 1, 6, 7, or 9 insn.  */
 #define R1	(UNUSED + 1)
   { 5, 0, NULL, NULL, V850_OPERAND_REG }, 
 
 /* As above, but register 0 is not allowed.  */
 #define R1_NOTR0 (R1 + 1)
-  { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, 
+  { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 
-/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
+/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn.  */
 #define R2	(R1_NOTR0 + 1)
   { 5, 11, NULL, NULL, V850_OPERAND_REG },
 
@@ -418,23 +418,23 @@ const struct v850_operand v850_operands[] =
 #define R2_NOTR0 (R2 + 1)
   { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 
-/* The imm5 field in a format 2 insn. */
+/* The imm5 field in a format 2 insn.  */
 #define I5	(R2_NOTR0 + 1)
   { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, 
 
-/* The unsigned imm5 field in a format 2 insn. */
+/* The unsigned imm5 field in a format 2 insn.  */
 #define I5U	(I5 + 1)
   { 5, 0, NULL, NULL, 0 },
 
-/* The imm16 field in a format 6 insn. */
+/* The imm16 field in a format 6 insn.  */
 #define I16	(I5U + 1)
   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
 
-/* The signed disp7 field in a format 4 insn. */
+/* The signed disp7 field in a format 4 insn.  */
 #define D7	(I16 + 1)
   { 7, 0, NULL, NULL, 0},
 
-/* The disp16 field in a format 6 insn. */
+/* The disp16 field in a format 6 insn.  */
 #define D16_15	(D7 + 1)
   { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 
 
@@ -446,11 +446,11 @@ const struct v850_operand v850_operands[] =
 #define CCCC	(B3 + 1)
   { 4, 0, NULL, NULL, V850_OPERAND_CC },
 
-/* The unsigned DISP8 field in a format 4 insn. */
+/* The unsigned DISP8 field in a format 4 insn.  */
 #define D8_7	(CCCC + 1)
   { 7, 0, insert_d8_7, extract_d8_7, 0 },
 
-/* The unsigned DISP8 field in a format 4 insn. */
+/* The unsigned DISP8 field in a format 4 insn.  */
 #define D8_6	(D8_7 + 1)
   { 6, 1, insert_d8_6, extract_d8_6, 0 },
 
@@ -462,7 +462,7 @@ const struct v850_operand v850_operands[] =
 #define EP	(SR1 + 1)
   { 0, 0, NULL, NULL, V850_OPERAND_EP },
 
-/* The imm16 field (unsigned) in a format 6 insn. */
+/* The imm16 field (unsigned) in a format 6 insn.  */
 #define I16U	(EP + 1)
   { 16, 16, NULL, NULL, 0}, 
 
@@ -470,11 +470,11 @@ const struct v850_operand v850_operands[] =
 #define SR2	(I16U + 1)
   { 5, 11, NULL, NULL, V850_OPERAND_SRG },
 
-/* The disp16 field in a format 8 insn. */
+/* The disp16 field in a format 8 insn.  */
 #define D16	(SR2 + 1)
   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
 
-/* The DISP9 field in a format 3 insn, relaxable. */
+/* The DISP9 field in a format 3 insn, relaxable.  */
 #define D9_RELAX	(D16 + 1)
   { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
 
@@ -484,19 +484,19 @@ const struct v850_operand v850_operands[] =
 #define D22	(D9_RELAX + 1)
   { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
 
-/* The signed disp4 field in a format 4 insn. */
+/* The signed disp4 field in a format 4 insn.  */
 #define D4	(D22 + 1)
   { 4, 0, NULL, NULL, 0},
 
-/* The unsigned disp5 field in a format 4 insn. */
+/* The unsigned disp5 field in a format 4 insn.  */
 #define D5_4	(D4 + 1)
   { 4, 0, insert_d5_4, extract_d5_4, 0 },
 
-/* The disp16 field in an format 7 unsigned byte load insn. */
+/* The disp16 field in an format 7 unsigned byte load insn.  */
 #define D16_16	(D5_4 + 1)
   { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, 
 
-/* Third register in conditional moves. */
+/* Third register in conditional moves.  */
 #define R3	(D16_16 + 1)
   { 5, 27, NULL, NULL, V850_OPERAND_REG },
 
@@ -504,11 +504,11 @@ const struct v850_operand v850_operands[] =
 #define MOVCC	(R3 + 1)
   { 4, 17, NULL, NULL, V850_OPERAND_CC },
 
-/* The imm9 field in a multiply word. */
+/* The imm9 field in a multiply word.  */
 #define I9	(MOVCC + 1)
   { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, 
 
-/* The unsigned imm9 field in a multiply word. */
+/* The unsigned imm9 field in a multiply word.  */
 #define U9	(I9 + 1)
   { 9, 0, insert_u9, extract_u9, 0 }, 
 
@@ -516,7 +516,7 @@ const struct v850_operand v850_operands[] =
 #define LIST12	(U9 + 1)
   { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, 
 
-/* The IMM6 field in a call instruction. */
+/* The IMM6 field in a call instruction.  */
 #define I6	(LIST12 + 1)
   { 6, 0, NULL, NULL, 0 }, 
 
@@ -528,19 +528,19 @@ const struct v850_operand v850_operands[] =
 #define IMM32	(IMM16 + 1)
   { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, 
 
-/* The imm5 field in a push/pop instruction. */
+/* The imm5 field in a push/pop instruction.  */
 #define IMM5	(IMM32 + 1)
   { 5, 1, NULL, NULL, 0 }, 
 
-/* Reg2 in dispose instruction. */
+/* Reg2 in dispose instruction.  */
 #define R2DISPOSE	(IMM5 + 1)
   { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
 
-/* Stack pointer in prepare instruction. */
+/* Stack pointer in prepare instruction.  */
 #define SP	(R2DISPOSE + 1)
   { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
 
-/* The IMM5 field in a divide N step instruction. */
+/* The IMM5 field in a divide N step instruction.  */
 #define I5DIV	(SP + 1)
   { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, 
 
@@ -550,23 +550,24 @@ const struct v850_operand v850_operands[] =
 
   /* The list of registers in a PUSHML/POPML instruction.  */
 #define LIST18_L (LIST18_H + 1)
-  { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
+  /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c.  */
+  { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP },
 } ; 
 
 
-/* reg-reg instruction format (Format I) */
+/* Reg - Reg instruction format (Format I).  */
 #define IF1	{R1, R2}
 
-/* imm-reg instruction format (Format II) */
+/* Imm - Reg instruction format (Format II).  */
 #define IF2	{I5, R2}
 
-/* conditional branch instruction format (Format III) */
+/* Conditional branch instruction format (Format III).  */
 #define IF3	{D9_RELAX}
 
-/* 3 operand instruction (Format VI) */
+/* 3 operand instruction (Format VI).  */
 #define IF6	{I16, R1, R2}
 
-/* 3 operand instruction (Format VI) */
+/* 3 operand instruction (Format VI).  */
 #define IF6U	{I16U, R1, R2}
 
 
@@ -604,17 +605,22 @@ const struct v850_operand v850_operands[] =
 const struct v850_opcode v850_opcodes[] =
 {
 { "breakpoint",	0xffff,			0xffff,		      	{UNUSED},   		0, PROCESSOR_ALL },
+{ "dbtrap",	one (0xf840),		one (0xffff),		{UNUSED},   		0, PROCESSOR_V850E1 },
 
 { "jmp",	one (0x0060),		one (0xffe0),	      	{R1}, 			1, PROCESSOR_ALL },
   
-/* load/store instructions */
+/* Load/store instructions.  */
+{ "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E1 },
 { "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E },
 
+{ "sld.hu",     one (0x0070),		one (0x07f0),         	{D5_4, EP,   R2_NOTR0},	1, PROCESSOR_V850E1 },
 { "sld.hu",     one (0x0070),		one (0x07f0),         	{D5_4, EP,   R2_NOTR0},	1, PROCESSOR_V850E },
 
+{ "sld.b",	one (0x0300),		one (0x0780),	      	{D7,   EP,   R2},	1, PROCESSOR_V850E1 },
 { "sld.b",	one (0x0300),		one (0x0780),	      	{D7,   EP,   R2},	1, PROCESSOR_V850E },
 { "sld.b",	one (0x0300),		one (0x0780),	      	{D7,   EP,   R2},	1, PROCESSOR_V850 },
 
+{ "sld.h",	one (0x0400),		one (0x0780),	      	{D8_7, EP,   R2}, 	1, PROCESSOR_V850E1 },
 { "sld.h",	one (0x0400),		one (0x0780),	      	{D8_7, EP,   R2}, 	1, PROCESSOR_V850E },
 { "sld.h",	one (0x0400),		one (0x0780),	      	{D8_7, EP,   R2}, 	1, PROCESSOR_V850 },
 { "sld.w",	one (0x0500),		one (0x0781),	      	{D8_6, EP,   R2}, 	1, PROCESSOR_ALL },
@@ -639,7 +645,7 @@ const struct v850_opcode v850_opcodes[] =
 { "st.h",	two (0x0760, 0x0000),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
 { "st.w",	two (0x0760, 0x0001),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
 
-/* byte swap/extend instructions */
+/* Byte swap/extend instructions.  */
 { "zxb",	one (0x0080),		one (0xffe0), 	      	{R1_NOTR0},		0, PROCESSOR_NOT_V850 },
 { "zxh",	one (0x00c0),		one (0xffe0), 	      	{R1_NOTR0}, 		0, PROCESSOR_NOT_V850 },
 { "sxb",	one (0x00a0),		one (0xffe0), 	      	{R1_NOTR0},		0, PROCESSOR_NOT_V850 },
@@ -648,12 +654,12 @@ const struct v850_opcode v850_opcodes[] =
 { "bsw",	two (0x07e0, 0x0340),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_NOT_V850 },
 { "hsw",	two (0x07e0, 0x0344),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_NOT_V850 },
 
-/* jump table instructions */
+/* Jump table instructions.  */
 { "switch",	one (0x0040),		one (0xffe0), 	      	{R1}, 			1, PROCESSOR_NOT_V850 },
 { "callt",	one (0x0200),		one (0xffc0), 	      	{I6}, 			0, PROCESSOR_NOT_V850 },
 { "ctret", 	two (0x07e0, 0x0144),	two (0xffff, 0xffff), 	{0}, 			0, PROCESSOR_NOT_V850 },
 
-/* arithmetic operation instructions */
+/* Arithmetic operation instructions.  */
 { "setf",	two (0x07e0, 0x0000),	two (0x07f0, 0xffff), 	{CCCC, R2}, 		0, PROCESSOR_ALL },
 { "cmov",	two (0x07e0, 0x0320),	two (0x07e0, 0x07e1), 	{MOVCC, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 },
 { "cmov",	two (0x07e0, 0x0300),	two (0x07e0, 0x07e1), 	{MOVCC, I5, R2, R3}, 	0, PROCESSOR_NOT_V850 },
@@ -686,14 +692,14 @@ const struct v850_opcode v850_opcodes[] =
 { "cmp",	OP  (0x0f),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 { "cmp",	OP  (0x13),		OP_MASK,		IF2, 			0, PROCESSOR_ALL },
   
-/* saturated operation instructions */
+/* Saturated operation instructions.  */
 { "satadd",	OP (0x11),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satadd",	OP (0x06),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satsub",	OP (0x05),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satsubi",	OP (0x33),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
 { "satsubr",	OP (0x04),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 
-/* logical operation instructions */
+/* Logical operation instructions.  */
 { "tst",	OP (0x0b),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 { "or",		OP (0x08),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 { "ori",	OP (0x34),		OP_MASK,		IF6U, 			0, PROCESSOR_ALL },
@@ -710,21 +716,21 @@ const struct v850_opcode v850_opcodes[] =
 { "shr",	two (0x07e0, 0x0080),	two (0x07e0, 0xffff), 	{R1,  R2}, 		0, PROCESSOR_ALL },
 { "sasf",       two (0x07e0, 0x0200),	two (0x07f0, 0xffff), 	{CCCC, R2}, 		0, PROCESSOR_NOT_V850 },
 
-/* branch instructions */
-	/* signed integer */
+/* Branch instructions.  */
+	/* Signed integer.  */
 { "bgt",	BOP (0xf),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bge",	BOP (0xe),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "blt",	BOP (0x6),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "ble",	BOP (0x7),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* unsigned integer */
+	/* Unsigned integer.  */
 { "bh",		BOP (0xb),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bnh",	BOP (0x3),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bl",		BOP (0x1),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bnl",	BOP (0x9),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* common */
+	/* Common.  */
 { "be",		BOP (0x2),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bne",	BOP (0xa),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* others */
+	/* Others.  */
 { "bv",		BOP (0x0),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bnv",	BOP (0x8),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bn",		BOP (0x4),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
@@ -741,20 +747,20 @@ const struct v850_opcode v850_opcodes[] =
    We use the short form in the opcode/mask fields.  The assembler
    will twiddle bits as necessary if the long form is needed.  */
 
-	/* signed integer */
+	/* Signed integer.  */
 { "jgt",	BOP (0xf),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jge",	BOP (0xe),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jlt",	BOP (0x6),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jle",	BOP (0x7),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* unsigned integer */
+	/* Unsigned integer.  */
 { "jh",		BOP (0xb),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jnh",	BOP (0x3),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jl",		BOP (0x1),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jnl",	BOP (0x9),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* common */
+	/* Common.  */
 { "je",		BOP (0x2),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jne",	BOP (0xa),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-	/* others */
+	/* Others.  */
 { "jv",		BOP (0x0),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jnv",	BOP (0x8),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jn",		BOP (0x4),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
@@ -769,7 +775,7 @@ const struct v850_opcode v850_opcodes[] =
 { "jr",		one (0x0780),		two (0xffc0, 0x0001),	{D22}, 			0, PROCESSOR_ALL },
 { "jarl",	one (0x0780),		two (0x07c0, 0x0001),	{D22, R2}, 		0, PROCESSOR_ALL}, 
 
-/* bit manipulation instructions */
+/* Bit manipulation instructions.  */
 { "set1",	two (0x07c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		2, PROCESSOR_ALL },
 { "set1",	two (0x07e0, 0x00e0),	two (0x07e0, 0xffff),	{R2, R1},    		2, PROCESSOR_NOT_V850 },
 { "not1",	two (0x47c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		2, PROCESSOR_ALL },
@@ -779,7 +785,7 @@ const struct v850_opcode v850_opcodes[] =
 { "tst1",	two (0xc7c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		2, PROCESSOR_ALL },
 { "tst1",	two (0x07e0, 0x00e6),	two (0x07e0, 0xffff),	{R2, R1},    		2, PROCESSOR_NOT_V850 },
 
-/* special instructions */
+/* Special instructions.  */
 { "di",		two (0x07e0, 0x0160),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
 { "ei",		two (0x87e0, 0x0160),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
 { "halt",	two (0x07e0, 0x0120),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
@@ -787,10 +793,10 @@ const struct v850_opcode v850_opcodes[] =
 { "trap",	two (0x07e0, 0x0100),	two (0xffe0, 0xffff),	{I5U}, 			0, PROCESSOR_ALL },
 { "ldsr",	two (0x07e0, 0x0020),	two (0x07e0, 0xffff),	{R1, SR2}, 		0, PROCESSOR_ALL },
 { "stsr",	two (0x07e0, 0x0040),	two (0x07e0, 0xffff),	{SR1, R2}, 		0, PROCESSOR_ALL },
+{ "dbret",	two (0x07e0, 0x0146),	two (0xffff, 0xffff),	{UNUSED},   		0, PROCESSOR_V850E1 },
 { 0, 0, 0, {0}, 0, 0 },
 
 } ;
 
 const int v850_num_opcodes =
   sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
-
diff --git a/gnu/usr.bin/binutils/opcodes/xstormy16-asm.c b/gnu/usr.bin/binutils/opcodes/xstormy16-asm.c
index 324c091893e..618e33b2f07 100644
--- a/gnu/usr.bin/binutils/opcodes/xstormy16-asm.c
+++ b/gnu/usr.bin/binutils/opcodes/xstormy16-asm.c
@@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define max(a,b) ((a) > (b) ? (a) : (b))
 
 static const char * parse_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
 
 /* -- assembler routines inserted here.  */
 
@@ -317,8 +317,7 @@ xstormy16_cgen_init_asm (cd)
    Returns NULL for success, an error message for failure.  */
 
 char * 
-xstormy16_cgen_build_insn_regex (insn)
-     CGEN_INSN *insn;
+xstormy16_cgen_build_insn_regex (CGEN_INSN *insn)
 {  
   CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
   const char *mnem = CGEN_INSN_MNEMONIC (insn);
@@ -441,11 +440,10 @@ xstormy16_cgen_build_insn_regex (insn)
    Returns NULL for success, an error message for failure.  */
 
 static const char *
-parse_insn_normal (cd, insn, strp, fields)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
 {
   /* ??? Runtime added insns not handled yet.  */
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
@@ -583,12 +581,11 @@ parse_insn_normal (cd, insn, strp, fields)
    mind helps keep the design clean.  */
 
 const CGEN_INSN *
-xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg)
-     CGEN_CPU_DESC cd;
-     const char *str;
-     CGEN_FIELDS *fields;
-     CGEN_INSN_BYTES_PTR buf;
-     char **errmsg;
+xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
 {
   const char *start;
   CGEN_INSN_LIST *ilist;
@@ -618,10 +615,10 @@ xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg)
       if (! xstormy16_cgen_insn_supported (cd, insn))
 	continue;
 #endif
-      /* If the RELAX attribute is set, this is an insn that shouldn't be
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
 	 chosen immediately.  Instead, it is used during assembler/linker
 	 relaxation if possible.  */
-      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
 	continue;
 
       str = start;
@@ -692,9 +689,7 @@ xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg)
    FIXME: Not currently used.  */
 
 void
-xstormy16_cgen_asm_hash_keywords (cd, opvals)
-     CGEN_CPU_DESC cd;
-     CGEN_KEYWORD *opvals;
+xstormy16_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
   const CGEN_KEYWORD_ENTRY * ke;
diff --git a/gnu/usr.bin/binutils/opcodes/xstormy16-desc.c b/gnu/usr.bin/binutils/opcodes/xstormy16-desc.c
index 9c9f30bc582..1c94fd7d853 100644
--- a/gnu/usr.bin/binutils/opcodes/xstormy16-desc.c
+++ b/gnu/usr.bin/binutils/opcodes/xstormy16-desc.c
@@ -104,7 +104,7 @@ const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
diff --git a/gnu/usr.bin/binutils/opcodes/xstormy16-desc.h b/gnu/usr.bin/binutils/opcodes/xstormy16-desc.h
index a880321f759..e6135058083 100644
--- a/gnu/usr.bin/binutils/opcodes/xstormy16-desc.h
+++ b/gnu/usr.bin/binutils/opcodes/xstormy16-desc.h
@@ -261,7 +261,7 @@ typedef enum cgen_operand_type {
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
diff --git a/gnu/usr.bin/binutils/opcodes/xstormy16-dis.c b/gnu/usr.bin/binutils/opcodes/xstormy16-dis.c
index 17c54a68a15..54af2571ab5 100644
--- a/gnu/usr.bin/binutils/opcodes/xstormy16-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/xstormy16-dis.c
@@ -41,21 +41,20 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define UNKNOWN_INSN_MSG _("*unknown*")
 
 static void print_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
 static void print_address
-     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
 static void print_keyword
-     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
 static void print_insn_normal
-     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
-	      bfd_vma, int));
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
 static int print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
 static int default_print_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
 static int read_insn
-     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
-	      CGEN_EXTRACT_INFO *, unsigned long *));
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
 
 /* -- disassembler routines inserted here */
 
@@ -194,13 +193,12 @@ xstormy16_cgen_init_dis (cd)
 /* Default print handler.  */
 
 static void
-print_normal (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     long value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -220,13 +218,12 @@ print_normal (cd, dis_info, value, attrs, pc, length)
 /* Default address handler.  */
 
 static void
-print_address (cd, dis_info, value, attrs, pc, length)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     bfd_vma value;
-     unsigned int attrs;
-     bfd_vma pc ATTRIBUTE_UNUSED;
-     int length ATTRIBUTE_UNUSED;
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
 
@@ -250,12 +247,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
 /* Keyword print handler.  */
 
 static void
-print_keyword (cd, dis_info, keyword_table, value, attrs)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     PTR dis_info;
-     CGEN_KEYWORD *keyword_table;
-     long value;
-     unsigned int attrs ATTRIBUTE_UNUSED;
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
 {
   disassemble_info *info = (disassemble_info *) dis_info;
   const CGEN_KEYWORD_ENTRY *ke;
@@ -269,17 +265,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs)
 
 /* Default insn printer.
 
-   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
    about disassemble_info.  */
 
 static void
-print_insn_normal (cd, dis_info, insn, fields, pc, length)
-     CGEN_CPU_DESC cd;
-     PTR dis_info;
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
-     int length;
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   disassemble_info *info = (disassemble_info *) dis_info;
@@ -311,14 +306,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
    Returns 0 if all is well, non-zero otherwise.  */
 
 static int
-read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-     CGEN_EXTRACT_INFO *ex_info;
-     unsigned long *insn_value;
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   char *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
 {
   int status = (*info->read_memory_func) (pc, buf, buflen, info);
   if (status != 0)
@@ -342,12 +336,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
    been called).  */
 
 static int
-print_insn (cd, pc, info, buf, buflen)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     unsigned int buflen;
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    char *buf,
+	    unsigned int buflen)
 {
   CGEN_INSN_INT insn_value;
   const CGEN_INSN_LIST *insn_list;
@@ -452,10 +445,7 @@ print_insn (cd, pc, info, buf, buflen)
 #endif
 
 static int
-default_print_insn (cd, pc, info)
-     CGEN_CPU_DESC cd;
-     bfd_vma pc;
-     disassemble_info *info;
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 {
   char buf[CGEN_MAX_INSN_SIZE];
   int buflen;
@@ -494,9 +484,7 @@ typedef struct cpu_desc_list {
 } cpu_desc_list;
 
 int
-print_insn_xstormy16 (pc, info)
-     bfd_vma pc;
-     disassemble_info *info;
+print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
 {
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
diff --git a/gnu/usr.bin/binutils/opcodes/xstormy16-ibld.c b/gnu/usr.bin/binutils/opcodes/xstormy16-ibld.c
index 0e4876a6f48..13433e0ea63 100644
--- a/gnu/usr.bin/binutils/opcodes/xstormy16-ibld.c
+++ b/gnu/usr.bin/binutils/opcodes/xstormy16-ibld.c
@@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
 #define FLD(f) (fields->f)
 
 static const char * insert_normal
-     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
 static const char * insert_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
-	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 static int extract_normal
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
-	      unsigned int, unsigned int, unsigned int, unsigned int,
-	      unsigned int, unsigned int, bfd_vma, long *));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
 static int extract_insn_normal
-     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
-	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 #if CGEN_INT_INSN_P
 static void put_insn_int_value
-     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
 #endif
 #if ! CGEN_INT_INSN_P
 static CGEN_INLINE void insert_1
-     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
 static CGEN_INLINE int fill_cache
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
 static CGEN_INLINE long extract_1
-     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
-	      unsigned char *, bfd_vma));
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
 #endif
 
 /* Operand insertion.  */
@@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1
 /* Subroutine of insert_normal.  */
 
 static CGEN_INLINE void
-insert_1 (cd, value, start, length, word_length, bufp)
-     CGEN_CPU_DESC cd;
-     unsigned long value;
-     int start,length,word_length;
-     unsigned char *bufp;
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
 {
   unsigned long x,mask;
   int shift;
@@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp)
    necessary.  */
 
 static const char *
-insert_normal (cd, value, attrs, word_offset, start, length, word_length,
-	       total_length, buffer)
-     CGEN_CPU_DESC cd;
-     long value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
-     CGEN_INSN_BYTES_PTR buffer;
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
 {
   static char errbuf[100];
   /* Written this way to avoid undefined behaviour.  */
@@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
    The result is an error message or NULL if success.  */
 
 static const char *
-insert_insn_normal (cd, insn, fields, buffer, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN * insn;
-     CGEN_FIELDS * fields;
-     CGEN_INSN_BYTES_PTR buffer;
-     bfd_vma pc;
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   unsigned long value;
@@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
  because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 
 static void
-put_insn_int_value (cd, buf, length, insn_length, value)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_INSN_BYTES_PTR buf;
-     int length;
-     int insn_length;
-     CGEN_INSN_INT value;
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
 {
   /* For architectures with insns smaller than the base-insn-bitsize,
      length may be too big.  */
@@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value)
    Returns 1 for success, 0 for failure.  */
 
 static CGEN_INLINE int
-fill_cache (cd, ex_info, offset, bytes, pc)
-     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
-     CGEN_EXTRACT_INFO *ex_info;
-     int offset, bytes;
-     bfd_vma pc;
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
 {
   /* It's doubtful that the middle part has already been fetched so
      we don't optimize that case.  kiss.  */
@@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc)
 /* Subroutine of extract_normal.  */
 
 static CGEN_INLINE long
-extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
-     CGEN_CPU_DESC cd;
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
-     int start,length,word_length;
-     unsigned char *bufp;
-     bfd_vma pc ATTRIBUTE_UNUSED;
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
 {
   unsigned long x;
   int shift;
@@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
    necessary.  */
 
 static int
-extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
-		word_length, total_length, pc, valuep)
-     CGEN_CPU_DESC cd;
+extract_normal (CGEN_CPU_DESC cd,
 #if ! CGEN_INT_INSN_P
-     CGEN_EXTRACT_INFO *ex_info;
+		CGEN_EXTRACT_INFO *ex_info,
 #else
-     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 #endif
-     CGEN_INSN_INT insn_value;
-     unsigned int attrs;
-     unsigned int word_offset, start, length, word_length, total_length;
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
 #if ! CGEN_INT_INSN_P
-     bfd_vma pc;
+		bfd_vma pc,
 #else
-     bfd_vma pc ATTRIBUTE_UNUSED;
+		bfd_vma pc ATTRIBUTE_UNUSED,
 #endif
-     long *valuep;
+		long *valuep)
 {
   long value, mask;
 
@@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
    been called).  */
 
 static int
-extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
-     CGEN_CPU_DESC cd;
-     const CGEN_INSN *insn;
-     CGEN_EXTRACT_INFO *ex_info;
-     CGEN_INSN_INT insn_value;
-     CGEN_FIELDS *fields;
-     bfd_vma pc;
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
 {
   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
   const CGEN_SYNTAX_CHAR_TYPE *syn;
diff --git a/gnu/usr.bin/binutils/opcodes/xtensa-dis.c b/gnu/usr.bin/binutils/opcodes/xtensa-dis.c
index bf5f5bfa192..8c310854a8a 100644
--- a/gnu/usr.bin/binutils/opcodes/xtensa-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/xtensa-dis.c
@@ -337,7 +337,7 @@ static char* state_names[256] =
 int show_raw_fields;
 
 static int fetch_data
-  PARAMS ((struct disassemble_info *info, bfd_vma memaddr, int numBytes));
+  PARAMS ((struct disassemble_info *info, bfd_vma memaddr));
 static void print_xtensa_operand
   PARAMS ((bfd_vma, struct disassemble_info *, xtensa_operand,
 	   unsigned operand_val, int print_sr_name));
@@ -348,15 +348,13 @@ struct dis_private {
 };
 
 static int
-fetch_data (info, memaddr, numBytes)
+fetch_data (info, memaddr)
      struct disassemble_info *info;
      bfd_vma memaddr;
-     int numBytes;
 {
   int length, status = 0;
   struct dis_private *priv = (struct dis_private *) info->private_data;
-  int insn_size = (numBytes != 0 ? numBytes :
-		   xtensa_insn_maxlength (xtensa_default_isa));
+  int insn_size = xtensa_insn_maxlength (xtensa_default_isa);
 
   /* Read the maximum instruction size, padding with zeros if we go past
      the end of the text section.  This code will automatically adjust
@@ -475,7 +473,7 @@ print_insn_xtensa (memaddr, info)
   isa = xtensa_default_isa;
 
   /* Fetch the maximum size instruction.  */
-  bytes_fetched = fetch_data (info, memaddr, 0);
+  bytes_fetched = fetch_data (info, memaddr);
 
   /* Copy the bytes into the decode buffer.  */
   memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) *