resolve conflicts.

34 files changed, 6576 insertions, 8735 deletions

diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog b/gnu/usr.bin/binutils/opcodes/ChangeLog
index e329df2dd90..593bec9de1a 100644
--- a/gnu/usr.bin/binutils/opcodes/ChangeLog
+++ b/gnu/usr.bin/binutils/opcodes/ChangeLog
@@ -1,5731 +1,1274 @@
-2000-05-26  Scott Bambrough  <scottb@netwinder.org>
-
-	Port of patch to mainline by Nick Clifton <nickc@cygnus.com>:
-	* arm-opc.h: Use upper case for flags in MSR and MRS
-	instructions.  Allow any bit to be set in the field_mask of
-	the MSR instruction.
-
-	Port of patch to mainline by Nick Clifton <nickc@cygnus.com>:
-	* arm-dis.c (print_insn_arm): Decode _x and _s bits of
-	the field_mask of an MSR instruction.
-
-2000-05-26  Scott Bambrough  <scottb@netwinder.org>
-
-	Port of patch to mainline by Thomas de Lellis <tdel@windriver.com>:
-        * arm-opc.h: Disassembly of thumb ldsb/ldsh
-        instructions changed to ldrsb/ldrsh.
-
-2000-04-13  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
-
-	* a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
-	avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
-	disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
-	i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
-	m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
-	mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, ppc-dis.c,
-	ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, tic80-dis.c,
-	tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, z8k-dis.c,
-	z8kgen.c: Everyone includes sysdep.h. Remove ansidecl.h as sysdep.h
-	includes it.
-
-2000-04-20  Alexandre Oliva  <aoliva@cygnus.com>
-
-	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
-	(disassemble): Use them.
-
-2000-04-04  Alan Modra  <alan@linuxcare.com.au>
-
-	* po/opcodes.pot: Regenerate.
-
-	* Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
-	(DEP): Quote when passing vars to sub-make.  Add warning message
-	to end.
-	(DEP1): Rewrite for "gcc -MM".
-	(CLEANFILES): Add DEP2.
-	Update dependencies.
-	* Makefile.in: Regenerate.
-
-2000-04-03  Denis Chertykov  <denisc@overta.ru>
-
-	* avr-dis.c: Syntax cleanup.
-	(add0fff): Print the pc relative address as a signed number.
-	(add03f8): Likewise.
-
-2000-04-01  Ian Lance Taylor  <ian@zembu.com>
-
-	* disassemble.c (disassembler_usage): Don't use a prototype.  Mark
-	the parameter ATTRIBUTE_UNUSED.
-	* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
-
-2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
-
-	* m10300-opc.c: SP-based offsets are always unsigned.
-
-2000-03-29  Thomas de Lellis  <tdel@windriver.com>
-
-	* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
-	[branch always] instead of "undefined".
-
-2000-03-27  Nick Clifton  <nickc@cygnus.com>
+2001-06-11  Alan Modra  <amodra@bigpond.net.au>
+
+	Merge from mainline.
+	2001-06-06  Peter Jakubek <pjak@snafu.de>
+	* m68k-dis.c (print_insn_m68k): Fix typo.
+	* m68k-opc.c (m68k_opcodes): Correct allowed operands for
+	mcf (ColdFire) div, rem and moveb instructions.
+
+	2001-06-06  Alan Modra  <amodra@bigpond.net.au>
+	* i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define.
+	(cond_jump_mode, loop_jcxz_mode): Define.
+	(dis386_att): Add cond_jump_flag and loop_jcxz_flag as
+	appropriate, and 'F' suffix to loop insns.
+	(disx86_64_att): Likewise.
+	(dis386_twobyte_att): Likewise.
+	(print_insn_i386): Don't output addr prefix for loop, jcxz insns.
+	Output data size prefix for long conditional jumps.  Output cs and
+	ds branch hints.
+	(putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'.
+	(OP_J): Don't make PREFIX_DATA used.
+
+	2001-05-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+	* mips-dis.c (mips_isa_type): Add MIPS r12k support.
+
+	2001-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+	* mips-dis.c (INSNLEN): Rename MAXLEN.
+	(std_reg_names): Replace by mips32_reg_names and mips64_reg_names.
+	(print_insn_arg): Remove $ prefix of register names.
+	(set_mips_isa_type): Remove.
+	(mips_isa_type): New function.
+	(get_mips_isa): New Function.
+	(print_insn_mips): Rename _print_insn_mips.
+	(_print_insn_mips): New function, contains code which was
+	duplicated in print_insn_big_mips and print_insn_little_mips.
+	(print_insn_big_mips): Moved code to _print_insn_mips.
+	(print_insn_little_mips): Likewise.
+	(print_mips16_insn_arg): Remove $ prefix of register names.
+	Print error message before abort.
 
-	* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
-	short instructions, from end of list of long instructions.
+	2001-05-14  J.T. Conklin  <jtc@redback.com>
+	* ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of
+ 	simplified mnemonics used for setting PPC750-specific special
+	purpose	registers.
 
-2000-03-27  Ian Lance Taylor  <ian@zembu.com>
+	2001-03-23  Nick Clifton  <nickc@redhat.com>
+	* mips-opc.c: Remove extraneous whitespace.
+	* mips-dis.c: Remove extraneous whitespace.
 
-	* Makefile.am (CFILES): Add avr-dis.c.
-	(ALL_MACHINES): Add avr-dis.lo.
+	2001-03-06  Igor Shevlyakov  <igor@windriver.com>
+	* m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs
+	so command line switches will work.
 
-2000-03-27  Alan Modra  <alan@linuxcare.com>
+	2001-02-28  Igor Shevlyakov  <igor@windriver.com>
+	* m68k-opc.c: fix cpushl according to Motorola. Enable
+	bunch of instructions for Coldfire 5407 and add all new.
 
-	* avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
-	truncate integers.
-	(print_insn_avr): Call function via pointer in K&R compatible way.
-	(dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
-	add0fff, add03f8): Convert to old style function declaration and
-	add prototype.
-	(avrdis_opcode): Add prototype.
-
-2000-03-27  Denis Chertykov  <denisc@overta.ru>
-
-	* avr-dis.c: New file.  AVR disassembler.
-	* configure.in (bfd_avr_arch): New architecture support.
-	* disassemble.c: Likewise.
+	2001-02-27  Alan Modra  <alan@linuxcare.com.au>
+	* configure.in (BFD_VERSION): Do without grep.
 	* configure: Regenerate.
-
-Mon Mar  6 19:52:05 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
-
-	* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
-
-2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
-
-        * d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
-        flag to determine if operand is pc-relative.
-        * d30v-opc.c:
-        (d30v_format_table):
-        (REL6S3): Renamed from IMM6S3.
-        Added flag OPERAND_PCREL.
-        (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
-        added flag OPERAND_PCREL.
-        (IMM12S3U): Replaced with REL12S3.
-        (SHORT_D2, LONG_D): Delay target is pc-relative.
-        (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
-        Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
-        using the REL* operands.
-        (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
-        (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
-        LONG_Db, using REL* operands.
-        (SHORT_U, SHORT_A5S): Removed stray alternatives.
-        (d30v_opcode_table): Use new *r formats.
-
-2000-02-28  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
-	'signed_overflow_ok_p'.
-
-2000-02-27  Eli Zaretskii  <eliz@is.elta.co.il>
-
-	* Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
-	name of the libtool directory.
-	* Makefile.in: Rebuild.
-
-2000-02-24  Nick Clifton  <nickc@cygnus.com>
-
-	* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
-	(cgen_clear_signed_overflow_ok): New function.
-	(cgen_signed_overflow_ok_p): New function.
-
-2000-02-23  Andrew Haley  <aph@cygnus.com>
-
-        * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
-	m32r-ibld.c,m32r-opc.h: Rebuild.
-
-2000-02-23  Linas Vepstas <linas@linas.org>
-
-	* i370-dis.c, i370-opc.c: New.
-
-	* disassemble.c (ARCH_i370): Define.
-	(disassembler): Handle it.
-
-	* Makefile.am: Add support for Linux/IBM 370.
-	* configure.in: Likewise.
-
+	* Makefile.am: Run "make dep-am".
 	* Makefile.in: Regenerate.
-	* configure: Likewise.
-
-2000-02-22  Chandra Chavva   <cchavva@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
-	ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
-	procedure.
-
-1999-12-30  Andrew Haley  <aph@cygnus.com>
-
-	* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
-	force gp32 to zero.
-	* mips-opc.c (G6): New define.
-	(mips_builtin_op): Add "move" definition for -gp32.
 
-2000-02-22  Ian Lance Taylor  <ian@zembu.com>
-
-	From Grant Erickson <gerickso@Brocade.COM>:
-	* ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
-
-2000-02-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* dis-buf.c (buffer_read_memory): Change `length' param and all int
-	vars to unsigned.
-
-Thu Feb 17 00:18:12 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
-
-	* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
-	(print_insn_ppi): Likewise.
-	(print_insn_shx): Use info->mach to select appropriate insn set.
-	Add support for sh-dsp.  Remove FD_REG_N support.
-	* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
-	(sh_arg_type): Likewise.  Remove FD_REG_N.
-	(sh_dsp_reg_nums): New enum.
-	(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
-	(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
-	(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
-	(arch_sh3_dsp_up): Likewise.
-	(sh_opcode_info): New field: arch.
-	(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
-	D_REG_N.  Fill in arch field.  Add sh-dsp insns.
-
-2000-02-14  Fernando Nasser  <fnasser@totem.to.cygnus.com>
-
-	* arm-dis.c: Change flavor name from atpcs-special to
-	special-atpcs to prevent name conflict in gdb.
-	(get_arm_regname_num_options, set_arm_regname_option,
-	get_arm_regnames): New functions.  API to access the several
-	flavor of register names.  Note: Used by gdb.
-	(print_insn_thumb): Use the register name entry from the currently
-	selected flavor for LR and PC.
-
-2000-02-10  Nick Clifton  <nickc@cygnus.com>
-
-	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
-	classes.
-	(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
-	"mulsh.h" instructions.
-	* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
-	classes.
-	(print_insn_mcore): Add support for little endian targets.
-	Add support for MULSH and OPSR classes.
-
-2000-02-07  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (parse_arm_diassembler_option): Rename again.
-	Previous delat did not take.
-
-2000-02-03  Timothy Wall  <twall@redhat.com>	
-	
-	* dis-buf.c (buffer_read_memory):  Use octets_per_byte field
-	to adjust target address bounds checking and calculate the
-	appropriate octet offset into data.
-	
-2000-01-27  Nick Clifton  <nickc@redhat.com>
-
-	* arm-dis.c: (parse_disassembler_option): Rename to
-	parse_arm_disassembler_option and allow to be exported.
-
-	* disassemble.c (disassembler_usage): New function: Print out any
-	target specific disassembler options.
-	Call arm_disassembler_options() if the ARM architecture is being
-	supported.  
-
-	* arm-dis.c (NUM_ELEM): Define this macro if not already
-	defined.
-	(arm_regname): New struct type for ARM register names.
-	(arm_toggle_regnames): Delete.
-	(parse_disassembler_option): Use register name structure.
-	(print_insn): New function: Combines duplicate code found in
-	print_insn_big_arm and print_insn_little_arm.
-	(print_insn_big_arm): Call print_insn.
-	(print_insn_little_arm): Call print_insn.
-	(print_arm_disassembler_options): Display list of supported,
-	ARM specific disassembler options.
-	  
-2000-01-27  Thomas de Lellis  <tdel@windriver.com>
-
-        * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
-	ARM_STT_16BIT flag as Thumb code symbols.
-        
-        * arm-dis.c (printf_insn_little_arm): Ditto.
-
-2000-01-25  Thomas de Lellis  <tdel@windriver.com>
-
-	* arm-dis.c (printf_insn_thumb): Prevent double dumping
-        of raw thumb instructions.
-
-2000-01-20  Nick Clifton  <nickc@cygnus.com>
-
-	* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
-
-2000-01-03  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (streq): New macro.
-	(strneq): New macro.
-	(force_thumb): ew local variable.
-	(parse_disassembler_option): New function: Parse a single, ARM
-	specific disassembler command line switch.
-	(parse_disassembler_option): Call parse_disassembler_option to
-	parse individual command line switches.
-	(print_insn_big_arm): Check force_thumb.
-	(print_insn_little_arm): Check force_thumb.
-
-1999-12-27  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall".
-
-Wed Dec  1 03:34:53 1999  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-opc.c, m10300-dis.c: Add am33 support.
-
-Wed Nov 24 20:29:58 1999  Jeffrey A Law  (law@cygnus.com)
-
-	* hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names.
-	(print_insn_hppa): Handle 'B' operand.
-
-1999-11-22  Nick Clifton  <nickc@cygnus.com>
-
-	* d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction.
+	2001-02-20  H.J. Lu  <hjl@gnu.org>
+	* Makefile.am (ia64-ic.tbl): Remove the target.
+	(ia64-raw.tbl): Likewise.
+	(ia64-waw.tbl): Likewise.
+	(ia64-war.tbl): Likewise.
+	(ia64-asmtab.c): Generate it in the source directory.
+	* Makefile.in: Regenerated.
 
-1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
+	2001-02-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+        * mips-dis.c (print_insn_arg): Use top four bits of the address of
+	the following instruction not of the jump itself for the jump
+	target.
+	(print_mips16_insn_arg): Likewise.
 
-	* mips-opc.c (I5): New.
-	(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
-	madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
-	pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
+	2001-02-11  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
+	* Makefile.am (stamp-lib): ranlib the libopcodes.a in the build
+	directory.
+	* Makefile.in: Regenerate.
 
-Mon Nov 15 19:34:58 1999  Donald Lindsay  <dlindsay@cygnus.com>
+2001-06-07  Alan Modra  <amodra@bigpond.net.au>
 
-	* arm-dis.c (print_insn_arm): Added general purpose 'X' format.
-	* arm-opc.h (print_insn_arm): Added comment documenting
-	the 'X' format just added to arm-dis.c.
+	* Many files: Update copyright notices.
 
-1999-11-15  Gavin Romig-Koch  <gavin@cygnus.com>
+2001-05-23  Alan Modra  <amodra@one.net.au>
 
-	* mips-opc.c (la): Create a version that just uses addiu directly.
-	(dla): Expand to daddiu if possible.
+	* arc-opc.c: Whitespace changes.
 
-1999-11-11  Nick Clifton  <nickc@cygnus.com>
+	Merge from mainline
+	2001-05-12  Peter Targett  <peter.targett@arccores.com>
+	* arc-opc.c (arc_reg_names): Correct attribute for lp_count
+	register to r/w.  Formatting fixes throughout file.
 
-	* mips-opc.c: Add ssnop pattern.
+2001-05-12  Alan Modra  <amodra@one.net.au>
 
-1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com>
+	* i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and
+	movq operands.
+	(twobyte_has_modrm): Update table.
+	(need_modrm): Give it file scope.
+	(MODRM_CHECK): Define.
+	(dofloat): Use MODRM_CHECK.
+	(OP_E): Likewise.
+	(OP_EM): Likewise.
+	(OP_EX): Likewise.
 
-	* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
+2001-05-04  Alan Modra  <amodra@one.net.au>
 
-1999-10-29  Nick Clifton  <nickc@cygnus.com>
+	* i386-dis.c (Ev, Ed): Remove duplicate define.
+	(Gd): Define.
+	(XS): Define.
+	(OP_XS): New function.
+	(dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and
+	movmskp operands.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Use MS for maskmovq operand.
 
-	* d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA
-	(d30v_format_tab): Define the SHORT_AR format.
+	Merge mainline:  2001-04-06  Andreas Jaeger  <aj@suse.de>
+	* i386-dis.c: Add ffreep instruction.
 
-1999-10-28  Nick Clifton  <nickc@cygnus.com>
+2001-03-30  Alexandre Oliva  <aoliva@redhat.com>
 
-	* mcore-dis.c: Remove spurious code introduced in previous delta. 
+	* ppc-opc.c (insert_mbe): Shift mask initializer as long.
 
-1999-10-27  Scott Bambrough  <scottb@netwinder.org>
+2001-03-24  Alan Modra  <alan@linuxcare.com.au>
 
-	* arm-dis.c: Include sysdep.h to prevent compile time warnings.
+	* i386-dis.c (PREGRP25): Define.
+	(dis386_twobyte_att): Use here in place of "movntq" entry.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq".
+	(PREGRP26): Define.
+	(dis386_twobyte_att): Use here.
+	(dis386_twobyte_intel): Likewise.
+	(prefix_user_table): Add PREGRP26 entry for "punpcklqdq".
+	(prefix_user_table <maskmovdqu>): XM operand, not MX.
+	(prefix_user_table): Cosmetic changes to "bad" entries.
 
-1999-10-18  Michael Meissner  <meissner@cygnus.com>
+2001-03-22  Alan Modra  <alan@linuxcare.com.au>
 
-	* alpha-opc.c (alpha_operands): Fill in missing initializer.
-	(alpha_num_operands): Convert to unsigned.
-	(alpha_num_opcodes): Ditto.
-	(insert_rba): Declare unused arguments ATTRIBUTE_UNUSED.
-	(insert_rca): Ditto.
-	(insert_za): Ditto.
-	(insert_zb): Ditto.
-	(insert_zc): Ditto.
-	(extract_bdisp): Ditto.
-	(extract_jhint): Ditto.
-	(extract_ev6hwjhint): Ditto.
+	* i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq.
+	(dis386_twobyte_intel): Likewise.
+	(twobyte_has_modrm): Set entry for paddq, psubq.
 
-Sun Oct 10 01:48:01 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
+2001-03-19  Jim Wilson  <wilson@redhat.com>
 
-	* hppa-dis.c (print_insn_hppa):  Add new codes 'cc', 'cd', 'cC',
-	'co', '@'.
+	* ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and
+	notestr if larger than xsect.
+	(in_class): Handle format M5.
+	* ia64-asmtab.c: Regnerate.
 
-	* hppa-dis.c (print_insn_hppa): Removed unused args.  Fix '?W'.
+2001-03-19  John David Anglin  <dave@hiauly1.hia.nrc.ca>
 
-	* hppa-dis.c (print_insn_hppa):  Implement codes "?N", "?Q".
+	* vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer
+	has more than one byte left to read.
 
-Thu Oct  7 00:12:43 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
+2001-02-23  David Mosberger  <davidm@hpl.hp.com>
 
-	* d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for
-	rac/rachi instructions.
-	(d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi,
-	slae, st and st2w.
+	* ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4".
+	* ia64-asmtab.c: Regenerate.
 
-1999-10-04  Doug Evans  <devans@casey.cygnus.com>
+2001-02-21  David Mosberger  <davidm@hpl.hp.com>
 
-	* fr30-asm.c,fr30-desc.h: Rebuild.
-	* m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild.  Add m32rx support.
-	* m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto.
+	* ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
+	separate variants: one for IMM22 and the other for IMM14.
+	* ia64-asmtab.c: Regenerate.
+	
+2001-02-14  Jim Wilson  <wilson@redhat.com>
 
-1999-09-29  Nick Clifton  <nickc@cygnus.com>
+	* ia64-ic.tbl: Update from Intel.  Add setf to fr-writers.
+	* ia64-asmtab.c: Regenerate.
 
-	* sh-opc.h: Fix bit patterns for several load and store
-	instructions.  
+Mon Feb 12 17:38:59 CET 2001  Jan Hubicka  <jh@suse.cz>
 
-Thu Sep 23 08:27:20 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org
+	* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
+	instructions.
+	(putop): Handle 'Y'
 
-	* hppa-dis.c (print_insn_hppa): Replace 'B', 'M', 'g' and 'l' with
-	cleaner code using completer prefixes.  Add 'Y'.
+2001-02-05  Jim Wilson  <wilson@redhat.com>
 
-Sun Sep 19 10:41:27 1999  Jeffrey A Law  (law@cygnus.com)
+	* ia64-asmtab.c: Revert 2000-12-16 change.
 
-	* hppa-dis.c: (print_insn_hppa): Correct 'cJ', 'cc'.
+Thu Feb  1 16:41:58 MET 2001  Jan Hubicka  <jh@suse.cz>
 
-	* hppa-dis.c (extract_22): New function.
+	* i387-dis.c (dis386_att, grps): Use 'T' for push/pop
+	(putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax
 
-	* hppa-dis.c (print_insn_hppa): Handle 'J', 'K', and 'cc'.
+2001-01-14  Alan Modra  <alan@linuxcare.com.au>
 
-	* hppa-dis.c (print_insn_hppa): Handle 'fe' and 'cJ'.
+	* hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types.
 
-	* hppa-dis.c (print_insn_hppa): Handle '#', 'd', and 'cq'.
+2001-01-13  Nick Clifton  <nickc@redhat.com>
 
-	* hppa-dis.c (print_insn_hppa): Handle 'm', 'h', '='.
+	* disassemble.c: Remove spurious white space.
 
-	* hppa-dis.c (print_insn_hppa): Handle 'X' operand.
+Sat Jan 13 01:48:24 MET 2001  Jan Hubicka  <jh@suse.cz>
 
-	* hppa-dis.c (print_insn_hppa): Handle 'B' operand.
+	* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
+	templates.
 
-	* hppa-dis.c (print_insn_hppa): Handle 'M' and 'L' operands.
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
 
-	* hppa-dis.c (print_insn_hppa): Handle 'l' operand.
+	* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+	* Makefile.am (C_FILES): Add arc-ext.c.
+	(ALL_MACHINES) Add arc-ext.lo.
+	(INCLUDES) Add opcode directory to list.
+	New dependency entry for arc-ext.lo.
+	* disassemble.c (disassembler): Correct call to
+	arc_get_disassembler.
+	* arc-opc.c: New update for ARC, including full base
+	instructions for ARC variants.
+	* arc-dis.h, arc-dis.c: New update for ARC, including
+	extensibility functionality.
+	* arc-ext.h, arc-ext.c: New files for handling extensibility.
 
-	* hppa-dis.c (print_insn_hppa): Handle 'g' operand.
+2001-01-10  Jan Hubicka  <jh@suse.cz>
 
-Sat Sep 18 11:36:12 1999  Jeffrey A Law  (law@cygnus.com)
+	* i386-dis.c (PREGRP15 - PREGRP24): New.
+	(dis386_twobyt): Add SSE2 instructions.
+	(twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions.
+	(twobyte_uses_f3_prefix): ... this one.
+	(grps): Add SSE instructions.
+	(prefix_user_table): Add two new slots; add SSE2 instructions.
+	(print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix;
+	Handle the REPNZ and Data16 prefixes as well; do proper lookup
+	to prefix_user_table.
+	(OP_E): Accept mfence and lfence as well.
+	(OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions.
+	(OP_XMM): Support REX extensions.
+	(OP_EM): Likewise.
+	(OP_EX): Likewise.
 
-	* hppa-dis.c (print_insn_hppa): Output a space after 'X' completer.
+2001-01-09  Nick Clifton  <nickc@redhat.com>
 
-	* hppa-dis.c: (print_insn_hppa): Do output a space before a 'v'
-	operand.
+	* arm-dis.c (print_insn): Set pc to zero for instructions with
+	a reloc associated with them.
 
-	* hppa-dis.c: (print_insn_hppa): Handle 'fX'.
+2001-01-09  Jeff Johnston  <jjohnstn@redhat.com>
 
-	* hppa-dis.c: (print_insn_hppa): Add missing break after
-	FP register case.
+	* cgen-asm.in (parse_insn_normal): Changed syn to be
+	CGEN_SYNTAX_CHAR_TYPE.  Changed all references to *syn
+	as character to use CGEN_SYNTAX_CHAR macro and all comparisons
+	to '\0' to use 0 instead.
+	* cgen-dis.in (print_insn_normal): Ditto.
+	* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
 
-	* hppa-dis.c: Finish constifying various completers, register
-	names, etc etc.
+2001-01-05  Jan Hubicka  <jh@suse.cz>
 
-1999-09-14  Michael Meissner  <meissner@cygnus.com>
+	* i386-dis.c: Add x86_64 support.
+	(rex): New static variable.
+	(REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants.
+	(USED_REX): New macro.
+	(Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros.
+	(OP_I64, OP_OFF64, OP_IMREG): New functions.
+	(OP_REG, OP_OFF): Declare.
+	(get64, get32, get32s): New functions.
+	(r??_reg): New constants.
+	(dis386_att): Change templates of instruction implicitly promoted
+	to 64bit; change e?? to RMe?? for unwind RM byte instructions.
+	(grps): Likewise.
+	(dis386_intel): Likewise.
+	(dixx86_64_att): New table based on dis386_att.
+	(dixx86_64_intel): New table based on dis386_intel.
+	(names64, names8rex): New global variable.
+	(names32, names16): Add extended registers.
+	(prefix_user_t): Recognize rex prefixes.
+	(prefix_name): Print REX prefixes nicely.
+	(op_riprel): New global variable.
+	(start_pc): Set type to bfd_vma.
+	(print_insn_i386): Detect the 64bit mode and use proper table;
+	move ckprefix after initializing the buffer; output unused rex prefixes;
+	output information about target of RIP relative addresses.
+	(putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S';
+	(print_operand_value): New function.
+	(OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for
+	REX prefix and new modes.
+	(get64, get32s): New.
+	(get32): Return bfd_signed_vma type.
+	(set_op): Initialize the op_riprel.
+	* disassemble.c (disassembler): Recognize the x86-64 disassembly.
+
+2001-01-03  Richard Sandiford  <r.sandiford@redhat.com>
+
+	 cgen-dis.in (read_insn): Use bfd_get_bits()
+
+2001-01-02  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen-dis.c (hash_insn_array): Use bfd_put_bits().
+	(hash_insn_list): Likewise
+	* cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits().
+	(extract_1): Use bfd_get_bits().
+	(extract_normal): Apply sign extension to both extraction
+	methods.
+	* cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits()
+	(cgen_put_insn_value): Use bfd_put_bits()
+
+2000-12-28  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-asm.in (parse_insn_normal): Print better error message for
+	instructions with missing operands.
+
+2000-12-21  Santeri Paavolainen <santtu@ssh.com>
+
+	* cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined.
+
+2000-12-16  Nick Clifton  <nickc@redhat.com>
 
-	* configure.in (Canonicalization of target names): Remove adding
-	${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14
-	generates $ac_config_sub with a ${CONFIG_SHELL} already.
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
+	* configure.in: Add spacing.
 	* configure: Regenerate.
+	* ia64-asmtab.c: Regenerate.
+	* po/opcodes.pot: Regenerate.
 
-Tue Sep  7 13:50:32 1999  Jeffrey A Law  (law@cygnus.com)
-
-	* hppa-dis.c (print_insn_hppa): Escape '%' in output strings.
-
-	* hppa-dis.c (print_insn_hppa): Handle 'Z' argument.
-
-1999-09-07  Nick Clifton  <nickc@cygnus.com>
-
-	* sh-opc.h: Add mulu.w and muls.w patterns.  These are the correct
-	names for the mulu and muls patterns.
-
-1999-09-04  Steve Chamberlain  <sac@pobox.com>
-
-	* pj-opc.c: New file.
-	* pj-dis.c: New file.
-	* disassemble.c	(disassembler): Handle bfd_arch_pj.
-	* configure.in: Handle bfd_pj_arch.
-	* Makefile.am: Rebuild dependencies.
-	(CFILES): Add pj-dis.c and pj-opc.c.
-	(ALL_MACHINES): Add pj-dis.lo and pj-opc.lo.
-	* configure, Makefile.in: Rebuild.
-
-1999-09-04  H.J. Lu  <hjl@gnu.org>
-
-	* i386-dis.c (print_insn_i386): Set bytes_per_line to 7.
-
-Mon Aug 30 18:56:14 1999  Richard Henderson  <rth@cygnus.com>
-
-	* alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31.
+2000-12-12  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time
+	error messages over later parse-time ones.
+
+2000-12-12  Jim Wilson  <wilson@redhat.com>
+
+	* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
+	argument.
+	* ia64-gen.c (insert_deplist): Cast sizeof result to int.
+	(print_dependency_table): Print NULL if semantics field not set.
+	(insert_opcode_dependencies): Mark cmp parameter as unused.
+	(print_main_table): Use fprintf_vma to print long long fields.
+	(main): Mark argv paramter as unused.  Convert to old style definition.
+	* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
+	* ia64-asmtab.c: Regnerate.
 
-1999-08-04  Doug Evans  <devans@casey.cygnus.com>
+2000-12-09  Nick Clifton  <nickc@redhat.com>
 
-	* fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild.
-	* m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild.
-	* m32r-opinst.c: Rebuild.
+	* m32r-dis.c (print_insn): Prevent re-read of instruction from
+	wrong address.
 
-Sat Aug 28 00:27:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+	* fr30-dis.c: Regenerate.
 
-        * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'.  Prefix float
-	register args by 'f'.
+2000-12-08  Peter Targett  <peter.targett@arccores.com>
 
-	* hppa-dis.c (print_insn_hppa): Add args q, %, !, and |.
+	* configure.in: Add arc-ext.lo for bfd_arc_arch selection.
+	* Makefile.am (C_FILES): Add arc-ext.c.
+	(ALL_MACHINES) Add arc-ext.lo.
+	(INCLUDES) Add opcode directory to list.
+	New dependency entry for arc-ext.lo.
+	* disassemble.c (disassembler): Correct call to
+	arc_get_disassembler.
+	* arc-opc.c: New update for ARC, including full base
+	instructions for ARC variants.
+	* arc-dis.h, arc-dis.c: New update for ARC, including
+	extensibility functionality.
+	* arc-ext.h, arc-ext.c: New files for handling extensibility.
 
-	* hppa-dis.c (MASK_10, read_write_names, add_compl_names,
-	extract_10U_store):  New.
-	(print_insn_hppa):  Add new completers.
+2000-12-03  Chris Demetriou   cgd@sibyte.com
 
-	* hppa-dis.c (signed_unsigned_names,mix_half_names,
-	saturation_names):  New.
-	(print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'.
+        * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
+        MOD_HILO, and MOD_LO macros.
 
-	* hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. 
+        * mips-opc.c (M1, M2): Delete.
+        (mips_builtin_opcodes): Remove all uses of M1.
 
-	* hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!'
+        * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
+        instructions take "G" format second operands and use the
+        correct flags.
+        There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to
+	match.
+        Delete "sel" code operands from mfc1 and mtc1.
+        Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants
+	for dm[ft]c[023].
 
-	* hppa-dis.c (print_insn_hppa):  Look at next arg instead of bits
-	to decide to print a space.
+2000-12-03  Ed Satterthwaite  ehs@sibyte.com  and
+            Chris Demetriou   cgd@sibyte.com
 
-1999-08-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
+        * mips-opc.c (mips_builtin_opcodes): Finish additions
+        for MIPS32 support, and clean up existing entries for
+        aesthetics, consistency with the MIPS32 ISA, and
+        with consistency the rest of the table.
 
-	* i386-dis.c: Add AMD athlon instruction support.
+2000-12-01  Nick Clifton  <nickc@redhat.com>
 
-1999-08-10  Ian Lance Taylor  <ian@zembu.com>
+	* mips16-opc.c (mips16_opcodes): Add initialiser for membership
+	field.
 
-	From Wally Iimura <iimura@microunity.com>:
-	* dis-buf.c (buffer_read_memory): Rewrite expression to avoid
-	overflow at end of address space.
-	(generic_print_address): Use sprintf_vma.
+2000-12-01  Chris Demetriou <cgd@sibyte.com>
 
-1999-08-08  Ian Lance Taylor  <ian@zembu.com>
+        mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
+        specifiers.  Update 'B' for new constant names, and remove
+        'm'.
+        mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
+        near the top of the array, so they are disassembled properly.
+        Enable "ssnop" for MIPS32.  Add "break" variant with 20 bit
+        code for MIPS32.  Update "clo" and "clz" to use 'U' operand
+        specifier.  Add 'H' format specifier variants for "mfc1,"
+        "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32.  Update
+        MIPS32 "sdbbp" to use 'B' operand specifier.  Add MIPS32
+        "wait" variant which uses 'J' operand specifier.
 
-	* Makefile.am: Rename .dep* files to DEP*.  Change DEP variable to
-	MKDEP.  Rebuild dependencies.
-	* Makefile.in: Rebuild.
+        * mips-dis.c (set_mips_isa_type): Update to use
+        CPU_UNKNOWN and ISA_* constants.  Add bfd_mach_mips32 case.
+        Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
+        * mips-opc.c (I32): New constant for instructions added in
+        MIPS32.
+        (P4): Delete.
+        (mips_builtin_opcodes) Replace all uses of P4 with I32.
 
-Fri Aug  6 09:46:35 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+        * mips-dis.c (set_mips_isa_type): Add cases for
+        bfd_mach_mips5 and bfd_mach_mips64.
+        * mips-opc.c (I64): New definitions.
 
-	* hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names,
-	add_cond_64_names, wide_add_cond_names, logical_cond_64_names,
-	unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New.
-	(print_insn_hppa): Add 64 bit condition completers.
+        * mips-dis.c (set_mips_isa_type): Add case for
+        bfd_mach_mips_sb1.
 
-Thu Aug  5 16:59:58 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+2000-11-28  Hans-Peter Nilsson  <hp@bitrange.com>
 
-	* hppa-dis.c (print_insn_hppa): Change condition args to use
-	'?' prefix.
+	* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
+	(print_insn_ppi): Make nib1, nib2, nib3 unsigned.
+	Initialize variable dc to NULL.
+	(print_insn_shx): Remove unused label d_reg_n.
 
-Wed Jul 28 04:33:58 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+2000-11-24  Nick Clifton  <nickc@redhat.com>
 
-	* hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E'
-	code.
+	* arm-opc.h: Add new opcode formatting parameter 'B'.
+	(arm_opcodes): Add XScale, v5, and v5te	instructions.
+	(thumb_opcodes): Add v5t instructions.
 
-1999-07-21  Ian Lance Taylor  <ian@zembu.com>
+	* arm-dis.c (print_insn_arm): Handle new 'B' format
+	parameter.
+	(print_insn_thumb): Decode BLX(1) instruction.
 
-	From Mark Elbrecht:
-	* configure.bat: Remove; obsolete.
+2000-11-21  Chris Demetriou  <cgd@sibyte.com>
 
-1999-07-11  Ian Lance Taylor  <ian@zembu.com>
+	* mips-opc.c: Fix file header comment.
 
-	* dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate.
-	(generic_strcat_address): Add cast to avoid warning.
-	* i386-dis.c: Initialize all structure fields to avoid warnings.
-	Add ATTRIBUTE_UNUSED as appropriate.
+2000-11-14  Hans-Peter Nilsson  <hp@axis.com>
 
-1999-07-08  Jakub Jelinek  <jj@ultra.linux.cz>
+	* cris-dis.c (cris_get_disassembler): If abfd is NULL, return
+	print_insn_cris_with_register_prefix.
 
-	* sparc-dis.c (print_insn_sparc): Differentiate between
-	addition and oring when guessing symbol for comment.
+2000-11-11  Alexandre Oliva  <aoliva@redhat.com>
 
-1999-07-05  Nick Clifton  <nickc@cygnus.com>
+	* sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.
 
-	* arm-dis.c (print_insn_arm): Display hex equivalent of rotated
-	constant. 
+2000-11-07  Matthew Green  <mrg@redhat.com>
 
-1999-06-23  Alan Modra  <alan@spri.levels.unisa.edu.au>
+	* cgen-dis.in (print_insn): All insns which can fit into insn_value
+	must be loaded there in their entirety.
 
-	* i386-dis.c: Mention intel mode specials in macro char comment.
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
 
-1999-06-21  Ian Lance Taylor  <ian@zembu.com>
+	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
+	(compute_arch_mask): Add v8plusb and v9b machines.
+	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
+	* sparc-opc.c: Support for Cheetah instruction set.
+	(prefetch_table): Add #invalidate.
 
-	* alpha-dis.c: Don't include <stdlib.h>.
-	* arm-dis.c: Include "sysdep.h".
-	* tic30-dis.c: Don't include <stdlib.h> or <string.h>.  Include
-	"sysdep.h".
-	* Makefile.am: Rebuild dependencies.
-	* Makefile.in: Rebuild.
+2000-10-16  Nick Clifton  <nickc@redhat.com>
 
-1999-06-16  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange
-	SWIs. 
-
-1999-06-14  Nick Clifton  <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com>
-
-	* arm-dis.c (arm_regnames): Turn into a pointer to a register
-	name set.
-	(arm_regnames_standard): New variable: Array of ARM register
-	names according to ARM instruction set nomenclature. 
-	(arm_regnames_apcs): New variable: Array of ARM register names
-	according to ARM Procedure Call Standard.
-	(arm_regnames_raw): New variable: Array of ARM register names
-	using just 'r' and the register number.
-	(arm_toggle_regnames): New function: Toggle the chosen register set
-	naming scheme.
-	(parse_disassembler_options): New function: Parse any target
-	disassembler command line options.
-	(print_insn_big_arm): Call parse_disassembler_options if any
-	are defined.
-	(print_insn_little_arm): Call parse_disassembler_options if any
-	are defined.
-
-1999-06-13  Ian Lance Taylor  <ian@zembu.com>
-
-	* i386-dis.c (FWAIT_OPCODE): Define.
-	(used_prefixes): New static variable.
-	(fetch_data): Don't print an error message if we have already
-	fetched some bytes successfully.
-	(ckprefix): Clear used_prefixes.  Use FWAIT_OPCODE, not 0x9b.
-	(prefix_name): New static function.
-	(print_insn_i386): If setjmp fails, indicating a data error, but
-	we have managed to fetch some bytes, print the first one as a
-	prefix or a .byte pseudo-op.  If fwait is followed by a non
-	floating point instruction, print the first prefix.  Set
-	used_prefixes when prefixes are used.  If any prefixes were not
-	used after disassembling the instruction, print the first prefix
-	instead of printing the instruction.
-	(putop): Set used_prefixes when prefixes are used.
-	(append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise.
-	(OP_DIR, OP_SIMD_Suffix): Likewise.
-
-1999-06-07  Jakub Jelinek  <jj@ultra.linux.cz>
-
-	* sparc-opc.c: Fix up set, setsw, setuw operand kinds.
-	Support signx %reg, clruw %reg.
-
-1999-06-07  Jakub Jelinek  <jj@ultra.linux.cz>
-
-	* sparc-opc.c: Add aliases Solaris as supports.
-
-Mon Jun  7 12:04:52 1999  Andreas Schwab  <schwab@issan.cs.uni-dortmund.de>
-
-	* Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c.
-	* Makefile.in: Regenerated.
+	* mcore-dis.c (imsk): Change mask for OC to 0xFE00.
 
-1999-06-03  Philip Blundell  <philb@gnu.org>
-
-	* arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR
-	when target is PC-relative.
-
-1999-05-28  Linus Nordberg  <linus.nordberg@canit.se>
-
-	* m68k-opc.c: Rename MACL/MSACL to MAC/MSAC.  Add MACM/MSACM.  Add
-	MOVE MACSR,CCR.
-
-	* m68k-dis.c (fetch_arg): Add places `n', `o'.
-
-	* m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK.
-	Add mcf5206e to appropriate instructions.
-	Add alias for MAC, MSAC.
-
-	* m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place
-	`N'.
-
-	* m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl,
-	macw, remsl, remul for mcf5307.  Change mcf5200 --> mcf.
-
-	* m68k-dis.c: Add format `u' and places `h', `m', `M'.
-
-1999-05-18  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (Ed): Define.
-	(dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd.
-	(Rw): Remove.
-	(OP_rm): Rename to OP_Rd.
-	(ONE): Remove.
-	(OP_ONE): Remove.
-	(putop): Add const to template and p.
-	(print_insn_x86): Delete.
-	(print_insn_i386): Merge old function print_insn_x86.  Add const
-	to dp.
-	(struct dis386): Add const to name.
-	(dis386_att, dis386_intel): Add const.
-	(dis386_twobyte_att, dis386_twobyte_intel): Add const.
-	(names32, names16, names8, names_seg, index16): Add const.
-	(grps, prefix_user_table, float_reg): Add const.
-	(float_mem_att, float_mem_intel): Add const.
-	(oappend): Add const to s.
-	(OP_REG): Add const to s.
-	(ptr_reg): Add const to s.
-	(dofloat): Add const to dp.
-	(OP_C): Don't skip modrm, it's now done in OP_Rd.
-	(OP_D): Ditto.
-	(OP_T): Ditto.
-	(OP_Rd): Check for valid mod.  Call Op_E to print.
-	(OP_E): Handle d_mode arg.  Check for bad sfence,lea,lds etc.
-	(OP_MS): Check for valid mod.  Call Op_EM to print.
-	(OP_3DNowSuffix): Set obufp and use oappend rather than
-	strcat.  Call BadOp() for errors.
-	(OP_SIMD_Suffix): Likewise.
-	(BadOp): New function.
-
-1999-05-12  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (dis386_intel): Remove macro chars, except for
-	jEcxz.  Change cWtR and cRtd to cW and cR.
-	(dis386_twobyte_intel): Remove macro chars here too.
-	(putop): Handle R and W macros for intel mode.
-
-	* i386-dis.c (SIMD_Fixup): New function.
-	(dis386_twobyte_att): Use it on movlps and movhps, and change
-	Ev to EX on these insns.  Change movmskps Ev, XM to Gv, EX.
-	(dis386_twobyte_intel): Same here.
-
-	* i386-dis.c (Av): Remove.
-	(Ap): remove lptr.
-	(lptr): Remove.
-	(OPSIMD): Define.
-	(OP_SIMD_Suffix): New function.
-	(OP_DIR): Remove dead code.
-	(eAX_reg..eDI_reg): Renumber.
-	(onebyte_has_modrm): Table numbering comments.
-	(INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86.
-	(print_insn_x86): Move all prefix oappends to after uses_f3_prefix
-	checks.  Print error on invalid dp->bytemode2.  Remove simd_cmp,
-	and handle SIMD cmp insns in OP_SIMD_Suffix.
-	(info->bytes_per_line): Bump from 5 to 6.
-	(OP_None): Remove.
-	(OP_E): Use INTERNAL_DISASSEMBLER_ERROR.  Handle sfence.
-	(OP_3DNowSuffix): Ensure mnemonic index unsigned.
-
-	PIII SIMD support from Doug Ledford <dledford@redhat.com>
-	* i386-dis.c (XM, EX, None): Define.
-	(OP_XMM, OP_EX, OP_None): New functions.
-	(USE_GROUPS, USE_PREFIX_USER_TABLE): Define.
-	(GRP14): Rename to GRPAMD.
-	(GRP*): Add USE_GROUPS flag.
-	(PREGRP*): Define.
-	(dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns.
-	(twobyte_has_modrm): Add SIMD entries.
-	(twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New.
-	(grps): Add SIMD insns.
-	(print_insn_x86): New vars uses_f3_prefix and simd_cmp.  Don't
-	oappend repz if uses_f3_prefix.  Add code to handle new groups for
-	SIMD insns.
-
-	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>
-	* i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn
-	operand from Av to Jv.
-
-1999-05-07  Nick Clifton  <nickc@cygnus.com>
-
-	* mcore-dis.c (print_insn_mcore): Use .short to display
-	unidentified instructions, not .word.
-
-1999-04-26  Tom Tromey  <tromey@cygnus.com>
-
-	* aclocal.m4, configure: Updated for new version of libtool.
-
-1999-04-14  Doug Evans  <devans@casey.cygnus.com>
-
-	* fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild.
-	* m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild.
-
-Mon Apr 12 23:46:17 1999  Jeffrey A Law  (law@cygnus.com)
-
-	* hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0
-	instructions.
-
-1999-04-10  Doug Evans  <devans@casey.cygnus.com>
+2000-10-06  Dave Brolley  <brolley@redhat.com>
 
-	* fr30-desc.c,fr30-desc.h,fr30-ibld.c: Rebuild.
-	* m32r-desc.c,m32r-desc.h,m32r-opinst.c: Rebuild.
+	* fr30-desc.h: Regenerate.
+	* m32r-desc.h: Regenerate.
+	* m32r-ibld.c: Regenerate.
 
-1999-04-06  Ian Lance Taylor  <ian@zembu.com>
+2000-10-05  Jim Wilson  <wilson@redhat.com>
 
-	* opintl.h (LC_MESSAGES): Never define.
+	* ia64-ic.tbl: Update from Intel.
+	* ia64-asmtab.c: Regenerate.
 
-1999-04-04  Ian Lance Taylor  <ian@zembu.com>
+2000-10-04  Kazu Hirata  <kazu@hxi.com>
 
-	* i386-dis.c (intel_syntax, open_char, close_char): Make static.
-	(separator_char, scale_char): Likewise.
-	(print_insn_x86): Likewise.
-	(print_insn_i386): Likewise.  Add declaration.
+	* ia64-gen.c: Convert C++-style comments to C-style comments.
+	* tic54x-dis.c: Likewise.
 
-1999-03-26  Doug Evans  <devans@casey.cygnus.com>
+2000-09-29  Hans-Peter Nilsson  <hp@axis.com>
 
-	* fr30-dis.c: Rebuild.
-	* m32r-dis.c: Rebuild.
+	Changes to add dollar prefix to registers for files where user symbols
+	don't have a leading underscore.  Fix formatting.
+	* cris-dis.c (REGISTER_PREFIX_CHAR): New.
+	(format_reg): Add parameter with_reg_prefix.  All callers changed.
+	(print_with_operands): Ditto.
+	(print_insn_cris_generic): Renamed from print_insn_cris, add
+	parameter with_reg_prefix.
+	(print_insn_cris_with_register_prefix,
+	print_insn_cris_without_register_prefix, cris_get_disassembler):
+	New.
+	* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
 
-1999-03-23  Ian Lance Taylor  <ian@zembu.com>
+2000-09-22  Jim Wilson  <wilson@redhat.com>
 
-	* m68k-opc.c: Change compare instructions to use "@s" rather than
-	";s" when used with an immediate operand.
+	* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
+	gt, ge, ngt, and nge.
+	* ia64-asmtab.c: Regenerate.
 
-1999-03-22  Doug Evans  <devans@casey.cygnus.com>
+	* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
+	* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
+	(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
+	* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
+	* ia64-asmtab.c: Regnerate.
 
-	* cgen-opc.c (cgen_set_cpu): Delete.
-	(cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize.
-	* fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c,fr30-opc.h:
-	Rebuild.
-	* m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h:
-	Rebuild.
-	* po/opcodes.pot: Rebuild.
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
 
-1999-03-16  Martin Hunt  <hunt@cygnus.com>
+	* mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.
+	Add mfc0 and mtc0 with sub-selection values.
+	Add clo and clz opcodes.
+	Add msub and msubu instructions for MIPS32.
+	Add madd/maddu aliases for mad/madu for MIPS32.
+	Support wait, deret, eret, movn, pref for MIPS32.
+	Support tlbp, tlbr, tlbwi, tlbwr.
+	(P4): New define.
 
-	* d30v-opc.c (mvtsys): Remove FLAG_LKR.
+	* mips-dis.c (print_insn_arg): Print sdbbp 'm' args.
+	(print_insn_arg): Handle 'H' args.
+	(set_mips_isa_type): Recognize 4K.
+	Use CPU_* defines instead of hardcoded numbers.
 
-1999-03-11  Doug Evans  <devans@casey.cygnus.com>
+2000-09-11  Catherine Moore <clm@redhat.com>
 
-	* cgen-opc.c (cgen_set_cpu): New arg `isa'.  All callers updated.
-	(cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns.
-	(cgen_get_insn_operands): Rewrite test for hardcoded/operand index.
-	* fr30-asm.c,fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c: Rebuild.
-	* m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c: Rebuild.
-	* m32r-opinst.c: Rebuild.
+	* d30v-opc.c (d30v_operand_t): New operand type Rb2.
+	(d30v_format_tab): Use Rb2 for modinc and moddec.
 
-1999-02-25  Doug Evans  <devans@casey.cygnus.com>
+2000-09-07  Catherine Moore  <clm@redhat.com>
 
-	* cgen-opc.c (cgen_hw_lookup_by_name): Rewrite.
-	(cgen_hw_lookup_by_num): Rewrite.
-	* fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild.
-	* m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild.
-	* m32r-opinst.c: Rebuild.
+        * d30v-opc.c (d30v_format_tab): Use format Ra for
+        modinc and moddec.
 
-Sat Feb 13 14:06:19 1999  Richard Henderson  <rth@cygnus.com>
+2000-09-06  Alexandre Oliva  <aoliva@redhat.com>
 
-	* alpha-opc.c: Add sqrt+flags patterns.  Add EV6 PALcode insns.
-	(insert_jhint): Fix insertion mask.
-	* alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns.
+	* configure: Rebuilt with new libtool.m4.
 
-1999-02-10  Doug Evans  <devans@casey.cygnus.com>
+2000-09-05  Nick Clifton  <nickc@redhat.com>
 
-	* Makefile.in: Rebuild.
-
-1999-02-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* i960c-asm.c,i960c-dis.c,i960c-opc.c,i960c-opc.h: Delete.
-	* i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig.
-	* Makefile.am: Remove references to them.
-	(HFILES): Add fr30-desc.h,m32r-desc.h.
-	(CFILES): Add fr30-desc.c,fr30-ibld.c,m32r-desc.c,m32r-ibld.c,
-	m32r-opinst.c.
-	(ALL_MACHINES): Update.
-	* configure.in: Redo handling of cgen_files.
-	(bfd_i960_arch): Delete i960c-*.lo files.
 	* configure: Regenerate.
-	* cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
-	(hash_insn_array): Rewrite.
-	* cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
-	(hash_insn_array): Rewrite.
-	* cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
-	(cgen_lookup_insn,cgen_get_insn_operands): Define here.
-	(cgen_lookup_get_insn_operands): Ditto.
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate.
-	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
-	* po/POTFILES.in: Rebuild.
-	* po/opcodes.pot: Rebuild.
-
-Fri Feb  5 00:04:24 1999  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.am: Rebuild dependencies.
-	(HFILES): Add fr30-opc.h.
-	(CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c.
-	* Makefile.in: Rebuild.
-
-	* configure.in: Change AC_PREREQ to 2.13.  Remove AM_CYGWIN32.
-	Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to
-	AC_PROG_INSTALL.
-	* acconfig.h: Remove.
-	* configure: Rebuild with current autoconf/automake.
-	* aclocal.m4: Likewise.
-	* config.in: Likewise.
-	* Makefile.in: Likewise.
-
-Thu Feb  4 13:48:52 1999  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Correct move (not movew) to status word on 5200.
-
-Mon Feb  1 20:54:36 1999  Catherine Moore  <clm@cygnus.com>
-
-        * disassemble.c (disassembler):  Handle bfd_mach_i386_i386_intel_syntax.
-        * i386-dis.c (x_mode):  Define.
-        (dis386):  Remove.
-        (dis386_att):  New.
-        (dis386_intel):  New.
-        (dis386_twobyte):  Remove.
-        (dis386_twobyte_att):  New.
-        (dis386_twobyte_intel):  New.
-        (print_insn_x86):  Use new arrays.
-        (float_mem):  Remove.
-        (float_mem_intel):  New.
-        (float_mem_att):  New.
-        (dofloat):  Use new float_mem arrays.
-        (print_insn_i386_att):  New.
-        (print_insn_i386_intel):  New.
-        (print_insn_i386):  Handle bfd_mach_i386_i386_intel_syntax.
-        (putop):  Handle intel syntax.
-        (OP_indirE):  Handle intel syntax.
-        (OP_E):  Handle intel syntax.
-        (OP_I):  Handle intel syntax.
-        (OP_sI):  Handle intel syntax.
-        (OP_OFF):  Handle intel syntax.
-
-
-
-1999-01-27  Doug Evans  <devans@casey.cygnus.com>
-
-	* fr30-opc.h,fr30-opc.c: Rebuild.
-	* i960c-opc.h,i960c-opc.c: Rebuild.
-	* m32r-opc.c: Rebuild.
-
-Tue Jan 19 18:01:54 1999  David Taylor  <taylor@texas.cygnus.com>
-
-	* hppa-dis.c: revert HP merge changes until HP gives us
-	an updated file.
-	
-1999-01-19  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_arm): Display ARM syntax for PC relative
-	offsets as well as symbloic address.
-
-Tue Jan 19 10:51:01 1999  David Taylor  <taylor@texas.cygnus.com>
-
-	* hppa-dis.c: fix comments and some indentation.
-
-1999-01-12  Doug Evans  <devans@casey.cygnus.com>
-
-	* fr30-opc.c,i960c-opc.c: Regenerate.
-
-1999-01-11  Doug Evans  <devans@casey.cygnus.com>
-
-	* fr30-opc.c: Regenerate.
-
-1999-01-06  Doug Evans  <devans@casey.cygnus.com>
-
-	* m32r-dis.c: Regenerate.
-
-1999-01-05  Doug Evans  <devans@casey.cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate.
-	* i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate.
-	* m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
-
-1999-01-04  Jason Molenda  (jsm@bugshack.cygnus.com)
-
-	* configure.in: Require autoconf 2.12.1 or higher.
-
-1998-12-30  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH.
-
-Wed Dec 16 16:17:49 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c: Regenerated.
-
-1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111.
-
-1998-12-15  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c,fr30-opc.h: Regenerated.
-
-1998-12-14  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c,fr30-opc.h: Regenerated.
-
-Thu Dec 10 18:39:46 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c,fr30-opc.h: Regenerated.
-
-Thu Dec 10 12:49:24 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-
-Tue Dec  8 13:56:18 1998  David Taylor  <taylor@texas.cygnus.com>
-
-	* dis-buf.c (generic_strcat_address): reformat to GNU coding
-	conventions.  change sprintf call to an sprintf_vma call.
-
-Tue Dec  8 13:12:44 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
-
-Tue Dec  8 10:50:46 1998  David Taylor  <taylor@texas.cygnus.com>
-
-	The following changes were made by
-	Elena Zannoni <ezannoni@kwikemart.cygnus.com>,
-	David Taylor <taylor@texas.cygnus.com>, and
-	Edith Epstein <eepstein@sophia.cygnus.com> as part of a project to
-	merge in changes by HP; HP did not create ChangeLog entries.
-
-	* dis-buf.c (generic_strcat_address): new function.
-
-	* hppa-dis.c: Changes to improve hppa disassembly.
-	  Changed formatting in : reg_names, fp_reg_names,control_reg, 
-	  New variables : sign_extension_names, deposit_names, conversion_names
-	    float_test_names, compare_cond_names_double, add_cond_names_double,
-	    logical_cond_names_double, unit_cond_names_double, 
-	    branch_push_pop_names, saturation_names, shift_names, mix_names,
-	  New Macros :   GET_COMPL_O, GET_PUSH_POP,MERGED_REG 
-	  Move some definitions to libhppa.h: GET_FIELD, GET_BIT
-	  (fput_const): renamed as fput_hex_const
-	  (print_insn_hppa):
-	   - use the macros fputs_filtered and
-	     fput_decimal_const whenever possible; calls to sign_extend require
-	     2 params -- add a missing second param of 0.
-	   - Some new code ifdefed for LOCAL_ONLY, all related to figuring out
-	     architecture version number of current machine. HP folks are
-	     trying to handle situation where the target program was compiled
-	     for PA 1.x (32-bit), but is running on a PA 2.0 machine and 
-	     visa versa.
-	   - added new cases : 'g', 'B', 'm'
-	   - added cases specifically for PA 2.0
-	   - changed the following cases : '"', 'n', 'N', 'p', 'Z', 
-	   - calls to fput_const become calls to fput_hex_const
-
-1998-12-07  James E Wilson  <wilson@wilson-pc.cygnus.com>
-
-	* Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c.
-	(ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo.
-	(i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules.
-	* Makefile.in: Rebuilt.
-	* configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o,
-	i960-dis.c to ta.
-	* i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
-	* i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
-	
-Mon Dec  7 14:33:44 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
-
-Sun Dec  6 14:06:48 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2.
-
-	* ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions.
-	From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>.
-
-Fri Dec  4 17:45:51 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* fr30-opc.c: Regenerate.
-
-Fri Dec  4 17:08:08 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
-
-Thu Dec  3 14:26:20 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
-
-Thu Dec  3 00:09:17 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate.
+	* po/opcodes.pot: Regenerate.
 
-1998-11-30  Doug Evans  <devans@casey.cygnus.com>
+2000-08-31  Alexandre Oliva  <aoliva@redhat.com>
 
-	* cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE ->
-	CGEN_INSN_BASE_VALUE.
-	* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
-	* fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate.
+	* acinclude.m4: Include libtool and gettext macros from the
+	top level.
+	* aclocal.m4, configure: Rebuilt.
 
-Thu Nov 26 11:26:32 1998  Dave Brolley  <brolley@cygnus.com>
+2000-08-30  Kazu Hirata  <kazu@hxi.com>
 
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated.
+	* tic80-dis.c: Fix formatting.
 
-Tue Nov 24 11:20:54 1998  Dave Brolley  <brolley@cygnus.com>
+2000-08-29  Kazu Hirata  <kazu@hxi.com>
 
-	* fr30-asm.c,fr30-dis.c: Regenerated.
+	* w65-dis.c: Fix formatting.
 
-Mon Nov 23 18:28:48 1998  Dave Brolley  <brolley@cygnus.com>
+2000-08-28  Mark Hatle  <mhatle@mvista.com>
 
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
+	* ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
+	(powerpc_opcodes): Add table entries for PPC 405 instructions.
+	Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
+	instructions.  Added extended mnemonic mftbl as defined in the
+	405GP manual for all PPCs.
 
-1998-11-20  Doug Evans  <devans@tobor.to.cygnus.com>
+2000-08-28  Jim Wilson  <wilson@redhat.com>
 
-	* fr30-opc.c: Regenerated.
+	* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
+	call.  Change last goto to use failed instead of done.
 
-Thu Nov 19 16:02:46 1998  Dave Brolley  <brolley@cygnus.com>
+2000-08-28  Dave Brolley  <brolley@redhat.com>
 
-	* fr30-opc.c: Regenerated.
-	* fr30-opc.h: Regenerated.
-	* fr30-dis.c: Regenerated.
+	* cgen-ibld.in (cgen_put_insn_int_value): New function.
+	(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+	(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
+	(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
+	* cgen-dis.in (read_insn): New static function.
+	(print_insn): Use read_insn to read the insn into the buffer and set
+	up for disassembly.
+	(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
+	in the buffer.
 	* fr30-asm.c: Regenerated.
-
-Thu Nov 19 07:54:15 1998  Doug Evans  <devans@charmed.cygnus.com>
-
-	* mips-opc.c (sync.p,sync.l): Swap insn values.
-
-1998-11-19  Doug Evans  <devans@tobor.to.cygnus.com>
-
-	* fr30-opc.c: Regenerate.
-
-Wed Nov 18 21:36:37 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c: Regenerated.
-	* fr30-opc.h: Regenerated.
-
-1998-11-18  Doug Evans  <devans@casey.cygnus.com>
-
-	* m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild.
-	* fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild.
-
-Wed Nov 18 11:30:04 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* fr30-opc.c: Regenerated.
-
-Mon Nov 16 19:21:48 1998  Dave Brolley  <brolley@cygnus.com>
-	
-	* fr30-opc.c: Regenerated.
-	* fr30-opc.h: Regenerated.
+	* fr30-desc.c: Regenerated.
+	* fr30-desc.h: Regenerated.
 	* fr30-dis.c: Regenerated.
-	* fr30-asm.c: Regenerated.
-
-Thu Nov 12 19:24:18 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* po/opcodes.pot: Regenerated.
+	* fr30-ibld.c: Regenerated.
 	* fr30-opc.c: Regenerated.
 	* fr30-opc.h: Regenerated.
-	* fr30-dis.c: Regenerated.
-	* fr30-asm.c: Regenerated.
-
-Tue Nov 10 15:26:27 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* disassemble.c (disassembler): Add support for FR30 target.
-	
-Tue Nov 10 11:00:04 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild.
-	* fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild.
-
-Mon Nov  9 18:22:55 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* po/opcodes.pot: Regenerate.
-	* po/POTFILES.in: Regenerate.
-	* fr30-opc.c: Regenerate.
-	* fr30-opc.h: Regenerate.
-
-Fri Nov  6 17:21:38 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-asm.c: Regenerate.
-
-Wed Nov  4 18:46:47 1998  Dave Brolley  <brolley@cygnus.com>
-
-	* configure.in: Added case for bfd_fr30_arch.
-	* Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c.
-	(ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo.
-	(CLEANFILES): Added stamp-fr30.
-	(FR30_DEPS): Added.
-	* fr30-asm.c: New file.
-	* fr30-dis.c: New file.
-	* fr30-opc.c: New file.
-	* fr30-opc.h: New file.
-	* po/POTFILES.in: Regenerated
-	* po/opcodes.pot: Regenerated
-
-Mon Nov  2 15:05:33 1998  Geoffrey Noer  <noer@cygnus.com>
-
-        * configure.in: detect cygwin* instead of cygwin32*
-        * configure: regenerate
-
-Tue Oct 27 08:58:37 1998  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* mips-opc.c (IS_M): Added.
-
-Mon Oct 19 13:03:19 1998  Doug Evans  <devans@seba.cygnus.com>
+	* m32r-asm.c: Regenerated.
+	* m32r-desc.c: Regenerated.
+	* m32r-desc.h: Regenerated.
+	* m32r-dis.c: Regenerated.
+	* m32r-ibld.c: Regenerated.
+	* m32r-opc.c: Regenerated.
 
-	* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
+2000-08-28  Kazu Hirata  <kazu@hxi.com>
 
-Fri Oct  9 14:01:56 1998  Doug Evans  <devans@seba.cygnus.com>
+	* tic30-dis.c: Fix formatting.
 
-	* m32r-opc.h,m32r-opc.c: Regenerate.
+2000-08-27  Kazu Hirata  <kazu@hxi.com>
 
-Sun Oct  4 21:01:44 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+	* sh-dis.c: Fix formatting.
 
-	* i386-dis.c (OP_3DNowSuffix): New static function.
-	(OPSUF): Define.
-	(GRP14): Define.
-	(dis386_twobyte): Add GRP14, femms, and 3DNow entries.
-	(twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow.
-	(insn_codep): New static variable.
-	(print_insn_x86): Init insn_codep after prefixes.
-	(grps): Add GRP14 entries for prefetch, prefetchw.
-	(OP_REG): Reformat.
+2000-08-24  David Edelsohn  <dje@watson.ibm.com>
 
-	From Jeff B Epler <jepler@usgs.gov>
-	* i386-dis.c (Suffix3DNow): New table.
+	* ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
 
-Wed Sep 30 10:17:50 1998  Nick Clifton  <nickc@cygnus.com>
+2000-08-24  Kazu Hirata  <kazu@hxi.com>
 
-	* d10v-opc.c: Treat TRAP as if it were a branch type instruction.
+	* z8k-dis.c: Fix formatting.
 
-Mon Sep 28 14:35:43 1998  Martin M. Hunt  <hunt@cygnus.com>
+2000-08-16  Jim Wilson  <wilson@redhat.com>
 
-	* d10v-dis.c (print_operand): If num is nonzero, then
-	add OPERAND_ACC1, not OPERAND_ACC0.
+	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
+	break, mov-immediate, nop.
+	* ia64-opc-f.c: Delete fpsub instructions.
+	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
+	address operand.  Rewrite using macros to avoid long lines.
+	* ia64-opc.h (POSTINC): Define.
+	* ia64-asmtab.c: Regenerate.
 
-Thu Sep 24 09:20:03 1998  Nick Clifton  <nickc@cygnus.com>
+2000-08-15  Jim Wilson  <wilson@redhat.com>
 
-	* d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP
-	insns. 
+	* ia64-ic.tbl: Add missing entries.
 
-Tue Sep 22 17:55:14 1998  Nick Clifton  <nickc@cygnus.com>
+2000-08-08  Jason Eckhardt  <jle@redhat.com>
 
-	* d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit
-	class. 
+	* i860-dis.c (print_br_address): Change third argument from int
+	to long.
 
-Tue Sep 15 15:14:45 1998  Doug Evans  <devans@canuck.cygnus.com>
+2000-08-07  Richard Henderson  <rth@redhat.com>
 
-	* m32r-opc.h,m32r-opc.c: Add bbpc,bbpsw support.
+	* ia64-dis.c (print_insn_ia64): Get byte skip count correct
+	for MLI templates.  Handle IA64_OPND_TGT64.
 
-1998-09-09  Michael Meissner  <meissner@cygnus.com>
+2000-08-04  Ben Elliston  <bje@redhat.com>
 
-	* ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move
-	to/from SPRs.
+	* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
+	* cgen.sh: Likewise.
 
-Fri Sep  4 19:42:59 1998  Nick Clifton  <nickc@cygnus.com>
+2000-08-02  Jim Wilson  <wilson@redhat.com>
 
-	* arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf
-	object files.
-	(print_insn_little_arm): Detect Thumb symbols in elf object
-	files. 
+	* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
 
-Sat Aug 29 22:24:09 1998  Richard Henderson  <rth@cygnus.com>
+2000-07-29  Marek Michalkiewicz  <marekm@linux.org.pl>
 
-	* alpha-dis.c (print_insn_alpha): Use the machine type to
-	decide which PALcode set to include.
+	* avr-dis.c (avr_operand): Use PARAMS macro in declaration.
+	Change return type from void to int.  Check the combination
+	of operands, return 1 if valid.  Fix to avoid BUF overflow.
+	Report undefined combinations of operands in COMMENT.
+	Report internal errors to stderr.  Output the adiw/sbiw
+	constant operand in both decimal and hex.
+	(print_insn_avr): Disassemble ldd/std with displacement of 0
+	as ld/st.  Check avr_operand () return value, handle invalid
+	combinations of operands like unknown opcodes.
 
-Sun Aug 23 02:16:18 1998  Richard Henderson  <rth@cygnus.com>
+2000-07-28  Ben Elliston  <bje@redhat.com>
 
-	* sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case.
-
-Fri Aug 21 16:07:52 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS,
-	MSUB and MSUBS instructions.
-
-Thu Aug 13 16:23:04 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* ppc-opc.c (powerpc_operands): Omit parens around additions in
-	operand name macros.
-
-Wed Aug 12 14:00:38 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	From Peter Jeremy <peter.jeremy@auss2.alcatel.com.au>:
-	* m68k-opc.c: Correct mulsl and mulul to use q rather than D, a,
-	+, -, and d for ColdFire.
-
-	From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>:
-	* ppc-opc.c (insert_mbe): Handle wrapping bitmasks.
-	(extract_mbe): Likewise.
-
-Wed Aug 12 11:11:34 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes.
-
-	* m10300-opc.c: First cut at UDF instructions.
-
-Mon Aug 10 14:08:22 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate (remove semantic descriptions).
-
-Mon Aug 10 12:51:12 1998  Catherine Moore  <clm@cygnus.com>
-
-        * arm-dis.c (print_insn_big_arm):  Fix indentation.
-        (print_insn_little_arm): Likewise.
-
-Sun Aug  9 20:17:28 1998  Catherine Moore  <clm@cygnus.com>
-
-        * arm-dis.c (print_insn_big_arm):  Check for thumb symbol
-        attributes.
-        (print_insn_little_arm): Likewise.
-
-Mon Aug  3 12:43:16 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	Move all global state data into opcode table struct, and treat
-	opcode table as something that is "opened/closed".
-	* cgen-asm.c (all fns): New first arg of opcode table descriptor.
-	(cgen_asm_init): Delete.
-	(cgen_set_parse_operand_fn): New function.
-	* cgen-dis.c (all fns): New first arg of opcode table descriptor.
-	(cgen_dis_init): Delete.
-	* cgen-opc.c (all fns): New first arg of opcode table descriptor.
-	(cgen_current_{opcode_table_mach,endian}): Delete.
-	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
-
-Thu Jul 30 21:41:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some
-	instructions.
-
-Tue Jul 28 11:00:09 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-opc.c: Add entries for "no_match_operands" field in
-	the opcode table.
-
-Fri Jul 24 11:41:37 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups).
-
-Tue Jul 21 13:41:07 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
-
-Mon Jul 13 14:53:59 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (ckprefix): Handle fwait specially only when it isn't
-	the first prefix.
-	(dofloat): Correct test for fnstsw.  Print `fnstsw %ax' rather
-	than `fnstsw %eax'.
-	(OP_J): Remove unnecessary subtraction when 16-bit displacement
-	will be masked later.
-
-Thu Jul  2 17:11:27 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define.
-
-Wed Jul  1 16:11:16 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
-
-Fri Jun 26 11:08:55 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-dis.c: Only recognize instructions from the currently
-	selected machine.
-	* m10300-opc.c: Add field indicating the particular variant of
-	the mn10300 each instruction is available on.
-
-Fri Jun 26 12:04:21 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: For bfd_vax_arch, build vax-dis.lo.
-	* Makefile.am: Rebuild dependencies.
- 	(CFILES): Add vax-dis.c.
-	(ALL_MACHINES): Add vax-dis.lo.
-	* aclocal.m4: Rebuild with current libtool.
-	* configure, Makefile.in: Rebuild.
-
-Fri Jun 26 12:03:20 1998  Klaus Kaempf  <kkaempf@progis.de>
-
-	* vax-dis.c: New file, from work by Pauline Middelink
-	<middelin@polyware.iaf.nl>.
-	* disassemble.c (ARCH_vax): Define if ARCH_all.
-	(disassembler): Add case for ARCH_vax.
-	* makefile.vms: Support compilation on vms/vax.
-
-Tue Jun 23 19:42:18 1998  Mark Alexander  <marka@cygnus.com>
-
-	* m10200-dis.c (print_insn_mn10200): Fix various non-portabilities
-	related to sign extension and the size of ints.
-
-Tue Jun 23 10:59:26 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-opc.c: Support one operand "asr", "lsr" and "asl"
-	instructions.  Support (sp) addressing mode by expanding it into
-	(0,sp).
-
-Sat Jun 20 14:46:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* mips-dis.c (_print_insn_mips): Fix argument interchange typo.
-
-Fri Jun 19 09:16:42 1998  Mark Alexander  <marka@cygnus.com>
-
-	* m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op.
-
-1998-06-18  Ulrich Drepper  <drepper@cygnus.com>
-
-	* i386-dis.c: Add support for fxsave, fxrstor, sysenter and
-	sysexit.
-
-Thu Jun 18 10:22:24 1998  John Metzler  <jmetzler@cygnus.com>
-
-	* mips-dis.c (print_insn_little_mips): Previously, instruction
- 	printing references the symbol table to determine whether the
- 	instruction resides in a block regular instructions or mips16
- 	instructions. However, when the disassembler gets used in other
- 	environments where the symbol table is not present, we no longer
- 	rely in the symbol table, rather, use the low bit of the
- 	instructions address to guess. There should be no change for usage
- 	of the disassembler in host based programs, gdb, objdump.
-	(print_insn_big_mips): ditto.
-	(print_insn_mips): ditto
-
-Wed Jun 17 21:19:01 1998  Mark Alexander  <marka@cygnus.com>
-
-	* m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes.
-
-Wed Jun 17 17:49:23 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".
-
-Tue Jun 16 13:10:51 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (index16): Add '%' to register names.  Use ','
-	instead of '+'.
-
-Sat Jun 13 11:33:55 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c: Don't print opcode suffix when we can figure out the
-	size (and gas can!) by register operands, or from the default
-	size.
-	(putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros.  Rename 'C'
-	macro to 'E'.
-	(dis386, dis386_twobyte, grps): Use new suffix macros.
-	(dis386): Correct imul Ib to imul sIb.  Change jnl to jge to be
-	consistent.  Add suffix for call, jmp, lcall, ljmp, iret.  Reverse
-	order of cmps operands to agree with Intel docs.  Correct operand
-	of aad and aam (Ib -> sIb).  Change ud2b from 0fb8 to 0fb9 to
-	agree with Intel docs.
-	(print_insn_x86): Print orphan fwait before other prefixes.
-	Return correct byte count for orphan fwait with prefixes.  Don't
-	print `bound' operands in reverse order.
-	(ckprefix): Stop accumulating prefixes if we get fwait.
-	(OP_DIR): Print `$' before Ap operands of ljmp, lcall.
-
-Fri Jun 12 13:40:38 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* po/Make-in (all-yes): If maintainer mode, depend on .pot file.
-	($(PACKAGE).pot): Unconditionally depend on POTFILES.
-
-Fri Jun 12 11:04:06 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	Fix problems when bfd_vma is wider than long.
-	* i386-dis.c: Make op_address and start_pc unsigned.
-	(set_op): Make parameter unsigned.
-	(print_insn_x86): Cast to bfd_vma when passing a value to
-	print_address_func.
-	* ns32k-dis.c (CORE_ADDR): Don't define.
- 	(print_insn_ns32k): Change type of addr to bfd_vma.  Use
-	bfd_scan_vma to read back address.
-	(print_insn_arg): Change type of addr to bfd_vma.  Use sprintf_vma
-	to format it.
-	* m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow.
-	(NEXTULONG): New definition.
-	(print_insn_m68k): Avoid overflow when computing third argument of
-	print_insn_arg.
-	(print_insn_arg): Use NEXTULONG to fetch 32 bit address values.
-	Use disp instead of val to store offset values.
-	(print_indexed): Use base_disp instead of word to store base
-	displacement, to avoid overflow.
-	* m10300-dis.c (disassemble): Cast value to long when computing
-	pc-relative address, to get correct sign extension.
-
-Wed Jun 10 15:58:37 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-
-Tue Jun  9 14:27:57 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as
-	'mov rX, rY'.  Patch courtesy of Tony Thompson <Tony.Thompson@arm.com>
-
-Mon Jun  8 18:17:21 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn.
-
-Fri Jun  5 23:47:55 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c:  Combine aflag and dflag into sizeflag.  Change OP_*
-	functions to void.
-	(OP_DSreg): Rename from OP_DSSI.
-	(OP_ESreg): Rename from OP_ESDI.
-	(Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode.
-	(DSBX): Define.
-	(append_seg): Rename from append_prefix.
-	(ptr_reg): New function.
-	(dis386): Add S suffix to pushf, popf, ret, lret, enter, leave.
-	Add DSBX for xlat.
-	(PREFIX_ADDR): Rename from PREFIX_ADR.
-	(float_reg): Add non-broken opcodes for people who don't want
-	UNIXWARE_COMPAT.
-
-Fri Jun  5 19:15:04 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on
-	68000/68008/68010.
-
-Wed Jun  3 18:56:22 1998  H.J. Lu  <hjl@gnu.org>
-
-	* i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS".
-
-Tue Jun  2 15:06:46 1998  Geoff Keating  <geoffk@ozemail.com.au>
-
-	* ppc-opc.c (powerpc_macros): Support shifts and rotates of size
-	0; produce error message for shifts of size 32 (or 64 for 64-bit
-	shifts), because the hardware doesn't support them.
-
-Wed May 27 15:29:13 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* d30v-opc.c: Add new operand: Ra3.  Change SHORT_B3, SHORT_B3b,
-	LONG_2, LONG_2b formats to use this new operand.
-
-Tue May 26 20:47:48 1998  Stan Cox  <scox@cygnus.com>
-
-	* sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le.
-
-Tue May 26 20:45:33 1998  Mark Alexander  <marka@cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): big endian instruction / little
-	endian data support.
-
-Tue May 26 16:14:39 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
-	and SHORT_B3b formats to use Rb instead of Ra.
-
-	Add FLAG_MUL16 to MUL2XH opcode.
-
-	Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
-	to existing 1.1.1 parallelisation prohibition procedure.
-
-Fri May 22 16:00:00 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-asm.c,m32r-dis.c: Regenerate.
-
-Tue May 19 17:36:08 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly
-	with a shift count of 0.
-
-Fri May 15 14:58:31 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
-	(cgen_hw_lookup_by_num): New function.
-
-Wed May 13 17:03:59 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA).
-
-Wed May 13 14:34:31 1998  Mark Alexander  <marka@cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Always fetch instructions
-	as big-endian on SPARClite.
-
-Tue May 12 11:46:31 1998  Richard Henderson  <rth@cygnus.com>
-
-	* d30v-opc.c (pre_defined_register): Remove alias for r0.
-
-Sun May 10 22:37:22 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* po/Make-in (install-info): New target.
-
-Thu May  7 17:15:59 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in (WIN32LIBADD): Add -lintl on cygwin32.
-	* configure: Rebuild.
-
-Thu May  7 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
- 	variety of ISA2 instructions to set bottom ten bits of trap code.
-
-Thu May  7 11:54:25 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.am (config.status): Add explicit target so that
-	config.status depends upon bfd/configure.in.
-	* Makefile.in: Rebuild.
-
-Thu May  7 09:33:02 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* mips-opc.c (break, sdbbp): Added two-operand variety of ISA1
-	instructions to set bottom ten bits of break code.
-	* mips-dis.c (print_insn_arg): Implement 'q' operand format used
-	for above optional argument.
+	* Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
+	(run-cgen, stamp-m32r, stamp-fr30): New targets.
+	* Makefile.in: Regenerate.
+	* configure.in: Add --enable-cgen-maint option.
+	* configure: Regenerate.
 
-Wed May  6 15:30:06 1998  Klaus Kaempf  <kkaempf@progis.de>
+2000-07-26  Dave Brolley  <brolley@redhat.com>
 
-	* makefile.vms: Run dec c with /nodebug.
+	* cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned.
+	(cgen_hw_lookup_by_num): Ditto.
+	(cgen_operand_lookup_by_name): Ditto.
+	(print_address): Ditto.
+	(print_keyword): Ditto.
+	* cgen-dis.c (hash_insn_array): Mark unused parameters with
+	ATTRIBUTE_UNUSED.
+	* cgen-asm.c (hash_insn_array): Mark unused parameters with
+	ATTRIBUTE_UNUSED.
+	(cgen_parse_keyword): Ditto.
 
-Mon May  4 10:19:57 1998  Tom Tromey  <tromey@cygnus.com>
+2000-07-22  Jason Eckhardt  <jle@redhat.com>
 
-	* Makefile.in: Rebuilt.
-	* Makefile.am: Regenerated dependencies with mkdep.
+	* i860-dis.c: New file.
+	(print_insn_i860): New function.
+	(print_br_address): New function.
+	(sign_extend): New function.
+	(BITWISE_OP): New macro.
+	(I860_REG_PREFIX): New macro.
+	(grnames, frnames, crnames): New structures.
 
-	* opintl.h (_): Define as dgettext.
+	* disassemble.c (ARCH_i860): Define.
+	(disassembler): Add check for bfd_arch_i860 to set disassemble
+	function to print_insn_i860.
 
-Tue Apr 28 14:12:12 1998  Nick Clifton  <nickc@cygnus.com>
+	* Makefile.in (CFILES): Added i860-dis.c.
+	(ALL_MACHINES): Added i860-dis.lo.
+	(i860-dis.lo): New dependences.
 
-	* cgen-asm.c: Internationalised.
-	* m32r-asm.c: Internationalised.
-	* m32r-dis.c: Internationalised.
-	* m32r-opc.c: Internationalised.
+	* configure.in: New bits for bfd_i860_arch.
 
-	* aclocal.m4: Regenerated.
 	* configure: Regenerated.
-	* Makefile.am (POTFILES): Remove inclusion of BFD_H.
-	* Makefile.in: Rebuild.
-	* po/POTFILES.in: Rebuilt using rule in Makefile.in.
-	* po/opcodes.pot: Rebuilt after changing POTFILES.in.
-
-Tue Apr 28 13:13:13 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Call AC_ISC_POSIX near start.  Move CY_GNU_GETTEXT
-	after AC_PROG_CC.
-	* aclocal.m4, configure: Rebuild with current tools.
-
-Mon Apr 27 14:31:00 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* opintl.h: New file - contains internationalisation macros used
-	by source files in this directory.
-	* po/: New subdirectory - contains internationalisation files.
-	* po/Make-in: New file - Makefile constructor.
-	* po/POTFILES.in: New file - list of files in opcodes directory
-	that should be scan for internationalisation macros.
-	* po/opcodes.pot: New file - list of internationisation strings
-	found in files mentioned in po/POTFILES.in.
-	* Makefile.am: Add rule to build po/POTFILES.in.  Add SUBDIRS
-	entry.  Add intl directory to include paths.
-	* acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT,
-	HAVE_STRCPY, HAVE_LC_MESSAGES
-	* configure.in: Add rule to build Makefile in po subdirectory.
-	* Makefile.in: Rebuilt.
-	* aclocal.m4: Rebuilt.
-	* config.in: Rebuilt.
-	* configure: Rebuilt.
-	* alpha-opc.c: Internationalised.
-	* arc-dis.c: Internationalised.
-	* arc-opc.c: Internationalised.
-	* arm-dis.c: Internationalised.
-	* cgen-asm.c: Internationalised.
-	* d30v-dis.c: Internationalised.
-	* dis-buf.c: Internationalised.
-	* h8300-dis.c: Internationalised.
-	* h8500-dis.c: Internationalised.
-	* i386-dis.c: Internationalised.
-	* m10200-dis.c: Internationalised.
-	* m10300-dis.c: Internationalised.
-	* m68k-dis.c: Internationalised.
-	* m88k-dis.c: Internationalised.
-	* mips-dis.c: Internationalised.
-	* ns32k-dis.c: Internationalised.
-	* opintl.h: Internationalised.
-	* ppc-opc.c: Internationalised.
-	* sparc-dis.c: Internationalised.
-	* v850-dis.c: Internationalised.
-	* v850-opc.c: Internationalised.
-
-Mon Apr 27 10:33:56 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data.
-	(asm_hash_table_entries): New variable.
-	(cgen_asm_init): Free asm_hash_table_entries.
-	(hash_insn_array,hash_insn_list): New functions.
-	(build_asm_hash_table): Use them.  Hash macro insns as well.
-	(cgen_asm_lookup_insn): Update.
-	* cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data.
-	(dis_hash_table_entries): New variable.
-	(cgen_dis_init): Free dis_hash_table_entries.
-	(hash_insn_array,hash_insn_list): New functions.
-	(build_dis_hash_table): Use them.  Hash macro insns as well.
-	(cgen_dis_lookup_insn): Update.
-	* cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data.
-	(cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update.
-	(cgen_macro_insn_count): New function.
-	* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
-
-Fri Apr 24 16:07:57 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (OP_DSSI): Print segment override.
-
-Mon Apr 13 16:59:39 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_arm): Add "_all" extension to 'C'
-	operator.
-
-Mon Apr 13 16:50:27 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@.
-	(libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@.
-	* configure.in: Define and substitute WIN32LDFLAGS and
-	WIN32LIBADD.
-	* aclocal.m4: Rebuild with new libtool.
-	* configure, Makefile.in: Rebuild.
-
-Fri Apr 10 18:14:31 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-
-Sun Apr  5 16:04:39 1998  H.J. Lu  <hjl@gnu.org>
-
-	* Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists
-	before trying to copy it.
-	* Makefile.in: Rebuild.
-
-Thu Apr  2 17:25:49 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r-opc.c: Use signed immediate values for CMPUI instruction.
-
-Wed Apr  1 16:20:27 1998  Ian Dall  <Ian.Dall@dsto.defence.gov.au>
-
-        * ns32k-dis.c (bit_extract_simple): New function to extract bits
-        from an arbitrary valid buffer instead of fetching them on demand
-        using fetch_data().
-        (invalid_float): use bit_extract_simple() instead of bit_extract().
-
-Tue Mar 31 11:09:08 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	From H.J. Lu <hjl@gnu.org>:
-	* i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew
-	to Ev for both.
-
-Mon Mar 30 17:32:03 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Branched binutils 2.9.
-
-Mon Mar 30 15:18:00 1998  Ken Raeburn  <raeburn@cygnus.com>
-
-	* d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when
-	disassembling last 4 bytes of a section.
-
-Fri Mar 27 18:08:13 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	Fix some gcc -Wall warnings:
-	* arc-dis.c (print_insn): Add casts to avoid warnings.
-	* cgen-opc.c (cgen_keyword_lookup_name): Likewise.
-	* d10v-dis.c (dis_long, dis_2_short): Likewise.
-	* m10200-dis.c (disassemble): Likewise.
-	* m10300-dis.c (disassemble): Likewise.
-	* ns32k-dis.c (print_insn_ns32k): Likewise.
-	* ppc-opc.c (insert_ral, insert_ram): Likewise.
-	* cgen-dis.c (build_dis_hash_table): Remove used local variables.
-	* cgen-opc.c (cgen_keyword_search_next): Likewise.
-	* d10v-dis.c (dis_long, dis_2_short): Likewise.
-	* d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise.
-	* ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise.
-	* tic80-dis.c (print_one_instruction): Likewise.
-	* w65-dis.c (print_operand): Likewise.
-	* z8k-dis.c (fetch_data): Likewise.
-	* a29k-dis.c: Add return type for find_byte_func_type.
-	* arc-opc.c: Include <stdio.h>.  Remove declarations of
-	insert_multshift and extract_multshift.
-	* d30v-dis.c (lookup_opcode): Parenthesize assignments in
-	conditionals.
-	(extract_value): Fully parenthesize expression.
-	* h8500-dis.c (print_insn_h8500): Initialize local variables.
-	* h8500-opc.h (h8500_table): Fully bracket initializer.
-	* w65-opc.h (optable): Likewise.
-	* i386-dis.c (print_insn_x86): Declare aflag and flag parameters.
-	* i386-dis.c (OP_E): Initialize local variables.
-	* m10200-dis.c (print_insn_mn10200): Likewise.
-	* mips-dis.c (print_insn_mips16): Likewise.
-	* sh-dis.c (print_insn_shx): Likewise.
-	* v850-dis.c (print_insn_v850): Likewise.
-	* ns32k-dis.c (print_insn_arg): Declare.
-	(get_displacement, invalid_float): Declare.
-	(list_search, sign_extend, flip_bytes): Declare return type.
-	(get_displacement): Likewise.
-	(print_insn_arg): Likewise.  Make d int.  Fix sprintf format
-	string.
-	(print_insn_ns32k): Make i unsigned.
-	(invalid_float): Make static.  Declare type of val.
-	* tic30-dis.c (print_par_insn): Make i size_t.  Don't check strlen
-	on each for iteration.
-	* tic30-dis.c (get_indirect_operand): Likewise.
-	* z8k-dis.c (print_insn_z8001): Declare return type.
-	(print_insn_z8002): Likewise.
-	(unparse_instr): Fix sprintf format strings.
-
-Fri Mar 27 00:05:23 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* mips-opc.c: Add "sync.l" and "sync.p".
-
-Wed Mar 25 14:32:48 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c (print_insn_m68k): Use info->mach to select the
-	default m68k variant to recognize.
-
-	* i960-dis.c (pinsn): Change type of first argument to bfd_vma.
-	(ctrl, cobr, mem, ea): Likewise.
-	(print_addr): Likewise.  Remove cast.
-	(ea): Cast argument of print_addr to bfd_vma.
-
-	* cgen-asm.c (cgen_parse_signed_integer): Fix type of local
-	variable value.
-	(cgen_parse_unsigned_integer): Likewise.
-	(cgen_parse_address): Likewise.
-
-Wed Mar 25 14:31:31 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i960-dis.c (ctrl): Add full braces to structure initialization.
-	(cobr, mem, reg): Likewise.
-	(ea): Correct parenthesization in expression.
-
-	* cgen-asm.c: Include <ctype.h>.
-	(build_asm_hash_table): Remove unused local variable i.
-	(cgen_parse_keyword): Add casts to avoid warnings.
-
-	* arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF
-	symbol.  Fix indentation.
-	(print_insn_little_arm): Likewise.
-
-Fri Mar 20 18:55:18 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Use AM_DISABLE_SHARED.
-	* aclocal.m4, configure: Rebuild with libtool 1.2.
-
-Thu Mar 19 15:46:53 1998  Nick Clifton  <nickc@cygnus.com>
-
-	These patches are courtesy of Jonathan Walton and Tony Thompson
-	(athompso@cambridge.arm.com).
-
-	* arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC
-	relative addresses.
-
-	* arm-opc.h (thumb_opcodes): Annotate PC relative addresses with
-	both the offset and the label closest to the destination.
-
-Sat Mar 14 23:47:14 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-opc.h: Regenerate.
-
-Wed Mar  4 12:08:14 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
-
-Sat Feb 28 16:02:34 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not
-	assume that info->symbols is non-empty.
-
-Sat Feb 28 12:19:05 1998  Richard Henderson  <rth@cygnus.com>
-
-	* alpha-opc.c (cvtqs) There is no such thing.
-	(cvttq): Missing most of the /*d variants.
-
-Thu Feb 26 15:53:09 1998  Michael Meissner  <meissner@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_table): Indicate which instructions are
-	delayed branches or jumps.
 
-Tue Feb 24 10:46:44 1998  Doug Evans  <devans@canuck.cygnus.com>
+2000-07-20  Hans-Peter Nilsson  <hp@axis.com>
 
-	* arm-dis.c (print_insn_{big,little}_arm): info->symbol changed
-	to *info->symbols.
-	* mips-dis.c (print_insn_{big,little}_mips): Likewise.
-	* tic30-dis.c (print_branch): Likewise.
-
-Tue Feb 24 11:06:18 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove
-	saved_symbol code as it is no longer needed.
-
-Mon Feb 23 13:16:17 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-asm.c: Include symcat.h.
-	* cgen-dis.c,cgen-opc.c: Ditto.
-	* m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
-
-Mon Feb 23 10:34:58 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'.
-
-Thu Feb 19 16:51:13 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.[ch]: Regenerate.
-
-Tue Feb 17 17:14:50 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max
-	arguments.  Don't perform validation here.
-	* m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate.
-
-Fri Feb 13 14:26:06 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-
-Fri Feb 13 14:53:02 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.am (AUTOMAKE_OPTIONS): Define.
-	* configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e.
-
-Fri Feb 13 10:21:09 1998  Mark Alexander  <marka@cygnus.com>
-
-	* m10300-dis.c (print_insn_mn10300): Recognize break instruction.
-
-Fri Feb 13 13:12:14 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Get the version number from BFD.
-	* configure: Rebuild.
-
-	From H.J. Lu <hjl@gnu.org>:
-	* Makefile.am (libopcodes_la_LDFLAGS): Define.
+	* Makefile.am (CFILES): Add cris-dis.c and cris-opc.c.
+	(ALL_MACHINES): Add cris-dis.lo and cris-opc.lo.
+	(cris-dis.lo, cris-opc.lo): New rules.
 	* Makefile.in: Rebuild.
-
-Fri Feb 13 09:50:32 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-	* m32r-opc.h: Regenerate.
-
-Thu Feb 12 11:01:40 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.c: Regenerate.
-
-Thu Feb 12 03:41:00 1998  J"orn Rennecke  <amylaar@cygnus.co.uk>
-
-	Fix rac to accept only a0:
-	* d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes):
-	Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1.
-	Introduce OPERAND_GPR.
-	* d10v-dis.c (print_operand): Likewise.
-
-Wed Feb 11 18:58:34 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain.
-	(cgen_hw_lookup): Make result const.
-	* m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
-
-Sat Feb  7 15:30:27 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure, aclocal.m4: Rebuild with new libtool.
-
-Thu Feb  5 17:56:10 1998  Michael Meissner  <meissner@cygnus.com>
-
-	* d30v-opc.c (repeat{,i} instructions): Repeat/repeati
-	instructions use a PC relative branch, not absolute.
-
-Wed Feb  4 19:17:37 1998  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Set libtool_enable_shared rather than
-	libtool_shared.  Remove diversion hack.
-	* configure, Makefile.in, aclocal.m4: Rebuild with new libtool.
-
-Tue Feb  3 17:19:40 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-opc.c (cgen_set_cpu): Initialize hardware table.
-	* m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
-
-Mon Feb  2 19:22:15 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
-
-	* tic30-dis.c: New file.
-	* disassemble.c	(disassembler): Add bfd_arch_tic30 case.
-	* configure.in: Handle bfd_tic30_arch.
-	* Makefile.am: Rebuild dependencies.
-	(CFILES): Add tic30-dis.c
-	(ALL_MACHINES): Add tic30-dis.lo.
-	* configure, Makefile.in: Rebuild.
-
-Thu Jan 29 13:02:56 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-opc.h (HAVE_CPU_M32R): Define.
-
-Wed Jan 28 09:55:03 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (insertion routines): If both alignment and size is
-	wrong then report this.
-
-Tue Jan 27 21:52:59 1998  Jeffrey A Law  (law@cygnus.com)
-
-	* mips-dis.c (_print_insn_mips): Set target_processor as appropriate.
-	Only recognize instructions for the current target_processor.
-
-Thu Jan 22 16:20:17 1998  Fred Fish  <fnf@cygnus.com>
-
-	* d10v-dis.c (PC_MASK): Correct value.
-	(print_operand): If there's a reloc, don't calculate the
- 	address because they could be in different sections.
-
-Fri Jan 16 15:29:11 1998  Jim Blandy  <jimb@zwingli.cygnus.com>
-
-	* mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu"
- 	instruction after the 4650's "mul" instruction; nobody's using the
- 	4010 these days.  If object files someday indicate which processor
-	variant they're intended for, we can do a better job at this.
-
-Mon Jan 12 14:43:54 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cgen-asm.c (build_asm_hash_table): Traverse compiled in table using
-	table provided entry size.  Use CGEN_INSN_MNEMONIC.
-	(cgen_parse_keyword): Rewrite.
-	* cgen-dis.c (build_dis_hash_table): Traverse compiled in table using
-	table provided entry size.  Use CGEN_INSN_MASK_BITSIZE.
-	* cgen-opc.c: Clean up pass over `struct foo' usage.
-	(cgen_keyword_lookup_value): Handle "" entry.
-	(cgen_keyword_add): Likewise.
-
-Mon Dec 22 12:37:06 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-opc.c: Add FP_D to s.d instruction flags.
-
-Wed Dec 17 11:38:29 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (halt, pulse): Enable them on the 68060.
-
-Tue Dec 16 15:22:53 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
-	PC relative offset forms before the 15 bit forms.  An assembler command
-	line option now chooses the default.
-
-Tue Dec 16 15:22:51 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_table): Set new flags bits
-	FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions.
-
-1997-12-15  Brendan Kehoe  <brendan@lisa.cygnus.com>
-
-	* configure: Only build libopcodes shared if --enable-shared's value
-	was `yes', or was set to `*opcodes*'.
-	* aclocal.m4: Likewise.
-	* NOTE: this really needs to be fixed in libtool/libtool.m4, the
-	original source of this bit of code.  It's not clear what the best fix
-	would be, though.
-
-Fri Dec 12 11:57:04 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
-	(tic80_opcodes): Reorder table entries to put the 32 bit PC relative
- 	offset forms before the 15 bit forms, to default to the long forms.
-
-Fri Dec 12 01:32:30 1997  Richard Henderson  <rth@cygnus.com>
-
-	* alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
-
-Wed Dec 10 17:42:35 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c (print_insn_little_arm): Prevent examination of stored
-	symbol if none is present.
-	(print_insn_big_arm):  Prevent examination of stored symbol if
-	none is present.
-
-Thu Oct 23 21:13:37 1997  Fred Fish  <fnf@cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Correct entry for RTE.
-
-Mon Dec  8 11:21:07 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* disassemble.c: Remove disasm_symaddr() function.
-
-	* arm-dis.c: Use info->symbol instead of info->flags to determine
-	if disassmbly should be in Thumb or Arm mode.
-
-Tue Dec  2 09:54:27 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* arm-dis.c: Add support for disassembling Thumb opcodes.
-	(print_insn_thumb): New function.
-
-	* disassemble.c (disasm_symaddr): New function.
-
-	* arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
-	(thumb_opcodes): Table of Thumb opcodes.
-
-Mon Dec  1 12:25:57 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (btst): Change Dd@s to Dd;b.
-
-	* m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q',
-	and 'v' as operand types.
-
-Mon Dec  1 11:56:50 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Add argument for lpstop.  From Olivier Carmona
-	<olivier.carmona@di.epfl.ch>.
-	* m68k-dis.c (print_insn_m68k): Handle special case of lpstop,
-	which has a two word opcode with a one word argument.
-
-Sun Nov 23 22:25:21 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
-	unsigned, not signed.
-	(d30v_format_table): Add SHORT_CMPU cases for cmpu.
-
-Tue Nov 18 23:10:03 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
-
-	* d10v-dis.c (print_operand):
-	Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
-
-Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
-
-	* d10v-opc.c (OPERAND_FLAG): Split into:
-	(OPERAND_FFLAG, OPERAND_CFLAG) .
-	(FSRC): Split into:
-	(FFSRC, CFSRC).
-
-Thu Nov 13 11:05:33 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c: Move the INSN_MACRO ISA value to the membership
-	field for all INSN_MACRO's.
-	* mips16-opc.c: same
-
-Wed Nov 12 10:16:57 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c (sync,cache): These are 3900 insns.
-
-Tue Nov 11 23:53:41 1997  J"orn Rennecke <amylaar@cygnus.co.uk>
-
-	sh-opc.h (sh_table): Remove ftst/nan.
-
-Tue Oct 28 17:59:32 1997  Ken Raeburn  <raeburn@cygnus.com>
-
-	* mips-opc.c (ffc, ffs): Fix mask.
-
-Tue Oct 28 16:34:54 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
-	control registers.
-
-Mon Oct 27 22:34:03 1997  Ken Raeburn  <raeburn@cygnus.com>
-
-	* mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
-	(WR_HILO, RD_HILO, MOD_HILO): New macros.
-
-Mon Oct 27 22:34:03 1997  Ken Raeburn  <raeburn@cygnus.com>
-
-	* mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
-	(WR_HILO, RD_HILO, MOD_HILO): New macros.
-
-Thu Oct 23 14:57:58 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Replace // with /* ... */
-
-Wed Oct 22 17:33:21 1997  Richard Henderson  <rth@cygnus.com>
-
-	* sparc-opc.c: Add wr & rd for v9a asr's.
-	* sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's.
-	(v9a_asr_reg_names): New variable.
-	Patch from David Miller <davem@vger.rutgers.edu>.
-
-Wed Oct 22 17:18:02 1997  Richard Henderson  <rth@cygnus.com>
-
-	* sparc-opc.c (v9notv9a): New insn type.
-	(IMPDEP): Move to the end to not conflict with edge8 et al.
-	Patch from David Miller <davem@vger.rutgers.edu>.
-
-Fri Oct 17 13:18:53 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c (bnezl,beqzl): Mark these as also tx39.
-
-Thu Oct 16 11:55:20 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
-
-Tue Oct 14 16:10:31 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Use new symbol_at_address_func() field
-	of disassemble_info structure to determine if an overlay address
-	has a matching symbol in low memory.
-
-	* dis-buf.c (generic_symbol_at_address): New (dummy) function for
-	new symbol_at_address_func field in disassemble_info structure.
-
-Fri Oct 10 16:44:52 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (extract_d22): Use signed arithmatic.
-
-Tue Oct  7 23:40:43 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c: Three op mult is not an ISA insn.
-
-Tue Oct  7 23:37:21 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c: Fix formatting.
-
-Fri Oct  3 17:26:54 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather
- 	than assuming that char is signed.  Explicitly sign extend 16 bit
-	values, rather than assuming that short is 16 bits.
-	(OP_sI, OP_J, OP_DIR): Likewise.
-
-Thu Oct  2 13:36:45 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (v850_sreg_names): Use symbolic names for higher
-	system registers.
-
-Wed Oct  1 16:58:54 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c: Fix typo in comment.
-
-	* v850-dis.c (disassemble): Add test of processor type when
-	determining opcodes.
-
-Wed Oct  1 14:10:20 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Use a diversion to set enable_shared before the
-	arguments are parsed.
-	* configure: Rebuild.
-
-Thu Sep 25 13:04:59 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (TBL1): Use ! rather than `.
-	* m68k-dis.c (print_insn_arg): Remove ` operand specifier.
-
-Wed Sep 24 11:29:35 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire.
-
-	* m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32.
-
-	* m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
-	for mcf5200.
-
-	* configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL.
-	* aclocal.m4: Rebuild with new libtool.
+	* configure.in (bfd_cris_arch): New target.
 	* configure: Rebuild.
+	* disassemble.c (ARCH_cris): Define.
+	(disassembler): Support ARCH_cris.
+	* cris-dis.c, cris-opc.c: New files.
+	* po/POTFILES.in, po/opcodes.pot: Regenerate.
 
-Fri Sep 19 11:45:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
-
-Thu Sep 18 11:21:43 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
-
-Tue Sep 16 15:18:20 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (v850_opcodes): Further rearrangements.
+2000-07-11  Jakub Jelinek  <jakub@redhat.com>
 
-Tue Sep 16 16:12:11 1997  Ken Raeburn  <raeburn@cygnus.com>
+	* sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2.
+	Reported by Bill Clarke <llib@computer.org>.
 
-	* d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change.
+2000-07-09  Geoffrey Keating  <geoffk@redhat.com>
 
-Tue Sep 16 09:48:50 1997  Nick Clifton  <nickc@cygnus.com>
+	* ppc-opc.c (powerpc_opcodes): Correct suffix for vslw.
+	Patch by Randall J Fisher <rfisher@ecn.purdue.edu>.
 
-	* v850-opc.c (v850_opcodes): Fields reordered to allow assembler
-	parser to work.
+2000-07-09  Alan Modra  <alan@linuxcare.com.au>
 
-Tue Sep 16 10:01:00 1997  Gavin Koch  <gavin@cygnus.com>
+	* hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg,
+	fput_const, extract_3, extract_5_load, extract_5_store,
+	extract_5r_store, extract_5R_store, extract_10U_store,
+	extract_5Q_store, extract_11, extract_14, extract_16, extract_21,
+	extract_12, extract_17, extract_22): Prototype.
+	(print_insn_hppa): Rename inner block opcode -> opc to avoid
+	shadowing outer block.
+	(GET_BIT): Define.
 
-	* mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.
+2000-07-05  DJ Delorie  <dj@redhat.com>
 
-Mon Sep 15 18:31:52 1997  Nick Clifton  <nickc@cygnus.com>
+	* MAINTAINERS: new
 
-	* v850-opc.c: Initialise processors field of v850_opcode structure.
+2000-07-04  Alexandre Oliva  <aoliva@redhat.com>
 
-Wed Aug 27 21:42:39 1997  Ken Raeburn  <raeburn@cygnus.com>
+	* arm-dis.c (print_insn_arm): Output combinations of PSR flags.
 
-	Merge changes from Martin Hunt:
+2000-07-03  Marek Michalkiewicz  <marekm@linux.org.pl>
 
-	* d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
+	* avr-dis.c (avr_operand): Change _ () to _() around all strings
+	marked for translation (exception from the usual coding style).
+	(print_insn_avr): Initialize insn2 to avoid warnings.
 
-	* d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
-	(d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix
-	rot2h, sra2h, and srl2h to use new SHORT_A5S format.
+2000-07-03  Kazu Hirata  <kazu@hxi.com>
 
-	* d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes.
+	* h8300-dis.c (bfd_h8_disassemble): Improve readability.
+	* h8500-dis.c: Fix formatting.
 
-	* d30v-dis.c (print_insn): First operand of d*i (delayed
-	branch) instructions is relative.
+2000-07-01  Alan Modra  <alan@linuxcare.com.au>
 
-	* d30v-opc.c (d30v_opcode_table): Change form for repeati.
-	(d30v_operand_table): Add IMM6S3 type.
-	(d30v_format_table): Change SHORT_D2. Add LONG_Db.
-
-	* d30v-dis.c: Fix bug with ".s" and ".l" extensions
-	and cmp instructions.
-
-	* d30v-opc.c: Correct entries for repeat*, and sat*.
-	Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
-	types. Correct several formats.
-
-	* d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
-
-	* d30v-opc.c (pre_defined_registers): Change control registers.
-
-	* d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
-	SHORT_C2.  Manual was incorrect.
-
-	* d30v-dis.c (lookup_opcode):  Return value now indicates
-	if an opcode has a short and a long form.  Used for deciding
-	to append a ".s" or ".l".
-	(print_insn): Append a ".s" to an instruction if it is
- 	the short form and ".l" if it is a long form. Do not append
-	anything if the instruction has only one possible size.
-
-	* d30v-opc.c: Change mulx2h to require an even register.
-	New form: SHORT_A2; a SHORT_A form that needs an even
-	register as the first operand.
-
-	* d30v-dis.c (print_insn_d30v): Fix problem where the last
-	instruction was not being disassembled if there were an odd
-	number of instructions.
-
-	* d30v-opc.c (SHORT_M2, LONG_M2):  Two new forms.
-
-Fri Sep 12 11:43:54 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Improved display of register lists.
-
-Thu Sep 11 17:35:10 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Fix assembler args to
-	fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s,
-	fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s,
-	fandnot1s, fandnot2s.
-
-Tue Sep  9 10:03:49 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq.
-
-Mon Sep  8 14:06:59 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-asm.c (cgen_parse_address): New argument resultp.
-	All callers updated.
-	* m32r-asm.c (parse_h_hi16): Right shift numbers by 16.
-
-Tue Sep  2 18:39:08 1997  Jeffrey A Law  (law@cygnus.com)
-
-        * mn10200-dis.c (disassemble): PC relative instructions are
-        relative to the next instruction, not the current instruction.
-
-Tue Sep  2 15:41:55 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Only signed extend values that are not
-	returned by extract functions.
-	Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag.
-
-Tue Sep  2 15:39:40 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c: Update comments.  Remove use of
-	V850_OPERAND_ADJUST_SHORT_MEMORY.  Fix several operand patterns.
-
-Tue Aug 26 09:42:28 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (MOVHI): Immediate parameter is unsigned.
-
-Mon Aug 25 15:58:07 1997  Christopher Provenzano  <proven@cygnus.com>
-
-	* configure: Rebuilt with latest devo autoconf for NT support.
-
-Fri Aug 22 10:35:15 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Use curly brace syntax for register
-	lists.
-
-	* v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
-	where r0 is being used as a destination register.
-
-Thu Aug 21 11:09:09 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
-
-Tue Aug 19 10:59:59 1997  Richard Henderson  <rth@cygnus.com>
-
-	* alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage.
-
-Mon Aug 18 11:10:03 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-opc.c (v850_opcodes[]): Remove use of flag field.
-	* v850-opc.c (v850_opcodes[]): Add support for reversed short load
-	opcodes..
+	* Makefile.am (DEP): Fix 2000-06-22.  grep after running dep.sed
+	(CLEANFILES): Add DEPA.
+	* Makefile.in: Regenerate.
 
-Mon Aug 18 11:08:25 1997  Nick Clifton  <nickc@cygnus.com>
+2000-06-26  Scott Bambrough  <scottb@netwinder.org>
 
-	* configure (cgen_files): Add support for v850e target.
-	* configure.in (cgen_files):  Add support for v850e target.
+	* arm-dis.c (regnames): Add an additional register set to match
+	the set used by GCC.  Make it the default.
 
-Mon Aug 18 11:08:25 1997  Nick Clifton  <nickc@cygnus.com>
+2000-06-22  Alan Modra  <alan@linuxcare.com.au>
 
-	* configure (cgen_files): Add support for v850ea target.
-	* configure.in (cgen_files):  Add support for v850ea target.
+	* Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we
+	find one.
+	* Makefile.in: Regenerate.
 
-Fri Aug 15 05:17:48 1997  Doug Evans  <dje@canuck.cygnus.com>
+2000-06-20  H.J. Lu  <hjl@gnu.org>
 
-	* configure.in (bfd_arc_arch): Add.
-	* configure: Rebuild.
-	* Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo.
+	* Makefile.am: Rebuild dependency.
 	* Makefile.in: Rebuild.
-	* arc-dis.c, arc-opc.c: New files.
-	* disassemble.c (ARCH_all): Define ARCH_arc.
-	(disassembler): Add ARC support.
-
-Wed Aug 13 18:52:11 1997  Nick Clifton  <nickc@cygnus.com>
-
-	* v850-dis.c (disassemble): Add support for v850EA instructions.
-
-	* v850-opc.c (insert_i5div, extract_i5div): New Functions.
-	(v850_opcodes): Add v850EA instructions.
-
-	* v850-dis.c (disassemble): Add support for v850E instructions.
-
-	* v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
-	extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
-	insert_spe, extract_spe): New Functions.
-	(v850_opcodes): Add v850E instructions.
-
-	* v850-opc.c: Reorganised and re-layed out to improve readability
-	and portability.
-
-Tue Aug  5 23:09:31 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild with autoconf 2.12.1.
-
-Mon Aug  4 12:02:16 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* aclocal.m4, configure: Rebuild with new automake patches.
-
-Fri Aug  1 13:02:04 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Set enable_shared before AM_PROG_LIBTOOL.
-	* acinclude.m4: Just include acinclude.m4 from BFD.
-	* aclocal.m4, configure: Rebuild.
-
-Thu Jul 31 21:44:42 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.am: New file, based on old Makefile.in.
-	* acconfig.h: New file.
-	* acinclude.m4: New file.
-	* stamp-h.in: New file.
-	* configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL.
-	Removed shared library handling; now handled by libtool.  Replace
-	AC_CONFIG_HEADER with AM_CONFIG_HEADER.  Call AM_MAINTAINER_MODE,
-	AM_CYGWIN32, and AM_EXEEXT.  Replace AC_PROG_INSTALL with
-	AM_PROG_INSTALL.  Change all .o files to .lo.  Remove stamp-h
-	handling in AC_OUTPUT.
-	* dep-in.sed: Change .o to .lo.
-	* Makefile.in: Now built with automake.
-	* aclocal.m4: Now built with aclocal.
-	* config.in, configure: Rebuild.
-
-Mon Jul 28 21:52:24 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mips-opc.c: Fix typo/thinko in "eret" instruction.
-
-Thu Jul 24 13:03:26 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
-	Make array const.
-	* sparc-dis.c (sorted_opcodes): New static local.
-	(struct opcode_hash): `opcode' is pointer to const element.
-	(build_hash): First arg is now table of sorted pointers.
-	(print_insn_sparc): Sort opcodes by sorting table of pointers.
-	(compare_opcodes): Update.
-
-Tue Jul 15 12:05:23 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-opc.c: #include <ctype.h>.
-	(hash_keyword_name): New arg `case_sensitive_p'.  Callers updated.
-	Handle case insensitive hashing.
-	(hash_keyword_value): Change type of `value' to unsigned int.
-
-Thu Jul 10 12:56:10 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mips-opc.c (mips_builtin_opcodes): If an insn uses single
-	precision FP, mark it as such.  Likewise for double precision
-	FP.  Mark ISA1 insns.  Consolidate duplicate opcodes where
-	possible.
-
-Wed Jun 25 15:25:57 1997  Felix Lee  <flee@cirdan.cygnus.com>
-
-	* ppc-opc.c (extract_nsi): make unsigned expression signed before
- 	negating it.
-	(UNUSED): remove one level of parens, so MSVC doesn't choke on
- 	nesting depth when all the macros are expanded.
-
-Tue Jun 17 17:02:17 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sparc-opc.c: The fcmp v9a instructions take an integer register
-	as a destination, not a floating point register.  From Christian
-	Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>.
-
-Mon Jun 16 14:13:18 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@()
-	syntax.  From Roman Hodek
-	<rnhodek@faui22c.informatik.uni-erlangen.de>.
-
-	* i386-dis.c (twobyte_has_modrm): Fix pand.
-
-Mon Jun 16 14:08:38 1997  Michael Taylor  <mbt@mit.edu>
-
-	* i386-dis.c (dis386_twobyte): Fix pand and pandn.
-
-Tue Jun 10 11:26:47 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
-
-	* arm-dis.c: Add prototypes for arm_decode_shift and
-	print_insn_arm.
-
-Mon Jun  2 11:39:04 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c: Add r3900 insns.
-
-Tue May 27 15:55:44 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sh-dis.c (print_insn_shx): Change relmask to bfd_vma.  Don't
-	print delay slot instructions on the same line.  When using a PC
-	relative load, add a comment with the value being loaded if it can
-	be obtained.
-
-Tue May 27 11:02:08 1997  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl
-	to pushS/popS for segment regs and byte constant so that
-	pushw/popw printed when in 16 bit data mode.
-
-	* i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to
-	print cbtw, cwtd in 16 bit data mode.
-	* i386-dis.c (putop): extra case W to support above.
-
-	* i386-dis.c (print_insn_x86): print addr32 prefix when given
-	address size prefix in 16 bit address mode.
-
-Fri May 23 16:47:23 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sh-dis.c: Reindent.  Rename local variable fprintf to
-	fprintf_fn.
-
-Thu May 22 14:06:02 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2.
-
-Tue May 20 11:26:27 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
-	  field membership.
-	* mips16-opc.c (mip16_opcodes): same.
-
-Mon May 12 15:10:53 1997  Jim Wilson  <wilson@cygnus.com>
-
-	* m68k-opc.c (moveb): Change $d to %d.
-
-Mon May  5 14:28:41 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c: (dis386_twobyte): Add MMX instructions.
-	(twobyte_has_modrm): Likewise.
-	(grps): Likewise.
-	(OP_MMX, OP_EM, OP_MS): New static functions.
-
-	* i386-dis.c: Revert patch of April 4.  The output now matches
-	what gcc generates.
-
-Fri May  2 12:48:37 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead
-	of $simm16.
-
-Thu May  1 15:34:15 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU.
-
-Tue Apr 15 12:40:08 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (install): Depend upon installdirs.
-	(installdirs): New target.
-
-Mon Apr 14 12:13:51 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	From Thomas Graichen <graichen@rzpd.de>:
-	* configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub.
-	* configure: Rebuild.
-
-Sun Apr 13 17:50:41 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h.
-	Delete string{,s}.h support.
-
-Thu Apr 10 14:44:56 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-asm.c (cgen_parse_operand_fn): New global.
-	(cgen_parse_{{,un}signed_integer,address}): Update call to
-	cgen_parse_operand_fn.
-	(cgen_init_parse_operand): New function.
-	* m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed
-	from cgen_asm_init_parse.
-	(m32r_cgen_assemble_insn): New operand `errmsg'.
-	Delete call to as_bad, return error message to caller.
-	(m32r_cgen_asm_hash_keywords): #if 0 out.
-
-Wed Apr  9 12:05:25 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c (print_insn_arg) [case 'd']: Print as address register,
-	not data register.
-	[case 'J']: Fix typo in register name.
-
-Mon Apr  7 16:48:22 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Substitute SHLIB_LIBS.
-	* configure: Rebuild.
-	* Makefile.in (SHLIB_LIBS): New variable.
-	($(SHLIB)): Use $(SHLIB_LIBS).
-
-Mon Apr  7 11:45:44 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation.
-
-	* cgen-opc.c (hash_keyword_name): Improve algorithm.
-
-	* disassemble.c (disassembler): Handle m32r.
-
-Fri Apr  4 12:29:38 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files.
-	* cgen-asm.c, cgen-dis.c, cgen-opc.c: New files.
-	* Makefile.in (CFILES): Add them.
-	(ALL_MACHINES): Add them.
-	(dependencies): Regenerate.
-	* configure.in (cgen_files): New variable.
-	(bfd_m32r_arch): Add entry.
-	* configure: Regenerate.
-
-Fri Apr  4 14:04:16 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Correct file names for bfd_mn10[23]00_arch.
-	* configure: Rebuild.
-
-	* Makefile.in: Rebuild dependencies.
-
-	* d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h".
-
-	* i386-dis.c (float_reg): Swap fsubrp and fsubp.  Swap fdivrp and
-	fdivp.
-
-Thu Apr  3 13:22:45 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Branched binutils 2.8.
-
-Wed Apr  2 12:23:53 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m10200-dis.c: Rename from mn10200-dis.c.
-	* m10200-opc.c: Rename from mn10200-opc.c.
-	* m10300-dis.c: Rename from mn10300-dis.c
-	* m10300-opc.c: Rename from mn10300-opc.c.
-	* Makefile.in: Update accordingly.
-
-	* mips16-opc.c: Add mul and dmul macros.
-
-Tue Apr  1 16:27:45 1997  Klaus Kaempf  <kkaempf@progis.de>
-
-	* makefile.vms: Update CFLAGS, add clean target.
-
-Fri Mar 28 12:10:09 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-opc.c: Add "wait".  From Ralf Baechle
-	<ralf@gnu.ai.mit.edu>.
-
-	* configure.in: Add stdlib.h to AC_CHECK_HEADERS list.
-	* configure, config.in: Rebuild.
-	* sysdep.h: Include <stdlib.h> if it exists.
-	* sparc-dis.c: Include <stdio.h> and "sysdep.h".  Don't include
-	<string.h>.
-	* Makefile.in: Rebuild dependencies.
-
-Thu Mar 27 14:24:43 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* ppc-opc.c: Add PPC 403 instructions and extended opcodes.  From
-	Andrew Bray <andy@madhouse.demon.co.uk>.
-
-	* mips-opc.c: Add cast when setting mips_opcodes.
-
-Tue Mar 25 23:04:00 1997  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* v850-dis.c (disassemble):  Fix sign extension problem.
-	* v850-opc.c (extract_d*):  Fix sign extension problems to make
-	disassembly calculate branch offsets correctly.
-
-Mon Mar 24 13:22:13 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s.
-
-	* mips-opc.c: Add dctr and dctw.
-
-Sun Mar 23 18:08:10 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d30v-dis.c (print_insn): Change the way signed constants
-	are displayed.
-
-Fri Mar 21 14:37:52 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (BFD_H): New variable.
-	(HFILES): New variable.
-	(CFILES): Add all C files.
-	(.dep, .dep1, dep.sed, dep, dep-in): New targets.
-	Delete old dependencies, and build new ones.
-	* dep-in.sed: New file.
-
-Thu Mar 20 19:03:30 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
-
-	* m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}.
-
-Tue Mar 18 14:17:03 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-opc.c: Change "trap" to "syscall".
-	* mn10300-opc.c: Add new "syscall" instruction.
-
-Mon Mar 17 08:48:03 1997  J.T. Conklin  <jtc@beauty.cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
- 	mulul insns on the coldfire.
-
-Sat Mar 15 17:13:05 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* arm-dis.c (print_insn_arm): Don't print instruction bytes.
-	(print_insn_big_arm): Set bytes_per_chunk and display_endian.
-	(print_insn_little_arm): Likewise.
-
-Fri Mar 14 15:08:59 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	Based on patches from H.J. Lu <hjl@lucon.org>:
-	* i386-dis.c (fetch_data): Add prototype.
-	* m68k-dis.c (fetch_data): Add prototype.
-	(dummy_print_address): Add prototype.  Make static.
-	* ppc-opc.c (valid_bo): Add prototype.
-	* sparc-dis.c (build_hash_table): Add prototype.
-	(is_delayed_branch, compute_arch_mask): Add prototypes.
-	(print_insn_sparc): Make several local variables const.
-	(compare_opcodes): Change arguments to const PTR.  Add prototype.
-	* sparc-opc.c (arg): Change name field to be const.
-	(lookup_name, lookup_value): Add prototypes.  Change table and
-	name parameters to be const.
-	(sparc_encode_asi): Change name parameter to be const.
-	(sparc_encode_membar, sparc_encode_prefetch): Likewise.
-	(sparc_encode_sparclet_cpreg): Likewise.
-	(sparc_decode_asi): Change return type to be const.
-	(sparc_decode_membar, sparc_decode_prefetch): Likewise.
-	(sparc_decode_sparclet_cpreg): Likewise.
-
-Fri Mar  7 10:51:49 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since
-	Solaris doesn't like the combined options, and the -f is
-	unnecessary.
-	(stamp-tshlink, install): Likewise.
-
-Thu Mar  6 16:51:11 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these
-	as relaxable.
-
-Tue Mar  4 06:10:36 1997  J.T. Conklin  <jtc@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Fix last change for the mc68010.
-
-Mon Mar  3 07:45:20 1997  J.T. Conklin  <jtc@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
- 	the mc68000.
-
-Thu Feb 27 14:04:32 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
-
-	* m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
-
-Thu Feb 27 11:36:41 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8.
-
-Wed Feb 26 15:34:48 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* tic80-opc.c (tic80_predefined_symbols): Define r25 properly.
-
-Wed Feb 26 13:38:30 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
-	floatformat_to_double to make portable.
-	(print_insn_arg): Use NEXTEXTEND macro when extracting extended
-	precision float.
-
-Mon Feb 24 19:26:12 1997  Dawn Perchik  <dawn@cygnus.com>
-
-	* mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes,
-	and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes.
-
-Mon Feb 24 15:19:01 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
-	d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
-
-Mon Feb 24 14:33:26 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (LSI_SCALED): Renamed from this ...
-	(OFF_SL_BR_SCALED): ... to this, and added the flag
-	TIC80_OPERAND_BASEREL to the flags word.
-	(tic80_opcodes): Replace all occurances of LSI_SCALED with
-	OFF_SL_BR_SCALED.
-
-Sat Feb 22 21:25:00 1997  Dawn Perchik  <dawn@cygnus.com>
-
-	* mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
-	Change mips_opcodes from const array to a pointer,
-	and change bfd_mips_num_opcodes from const int to int,
-	so that we can increase the size of the mips opcodes table
-	dynamically.
-
-Sat Feb 22 21:03:47 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_predefined_symbols): Revert change to
-	store BITNUM values in the table in one's complement form
-	to match behavior when assembler is given a raw numeric
-	value for a BITNUM operand.
-	* tic80-dis.c (print_operand_bitnum): Ditto.
-
-Fri Feb 21 16:31:18 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d30v-opc.c: Removed references to FLAG_X.
-
-Wed Feb 19 14:51:20 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in: Add dependencies on ../bfd/bfd.h as required.
-
-Tue Feb 18 17:43:43 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* Makefile.in: Added d30v object files.
-	* configure: (bfd_d30v_arch) Rebuilt.
-	* configure.in: (bfd_d30v_arch) Added new case.
-	* d30v-dis.c: New file.
-	* d30v-opc.c: New file.
-	* disassemble.c (disassembler) Add entry for d30v.
-
-Tue Feb 18 16:32:08 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_predefined_symbols): Add symbolic
-	representations for the floating point BITNUM values.
-
-Fri Feb 14 12:14:05 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_predefined_symbols): Store BITNUM values
-	in the table in one's complement form, as they appear in the
-	actual instruction.
-	(tic80_symbol_to_value): Use macros to access predefined
-	symbol fields.
-	(tic80_value_to_symbol): Ditto.
-	(tic80_next_predefined_symbol): New function.
-	* tic80-dis.c (print_operand_bitnum): Remove code that did
-	one's complement for BITNUM values.
-
-Thu Feb 13 21:56:51 1997  Klaus Kaempf  <kkaempf@progis.de>
-
-	* makefile.vms: Remove 8 bit characters.  Update to latest
-	gcc release.
-
-Thu Feb 13 20:41:22 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
-
-	* m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
-
-Thu Feb 13 16:30:02 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-opc.c (IMM16_PCREL): This is a signed operand.
-	(IMM24_PCREL): Likewise.
-
-Thu Feb 13 13:28:43 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base
-	address for an extended PC relative instruction that is not a
-	branch.
-
-Wed Feb 12 12:27:40 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
-	bytes_per_line.
-
-Tue Feb 11 16:36:31 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
-	(tic80_opcodes): Sort entries so that long immediate forms
-	come after short immediate forms, making it easier for
-	assembler to select the right one for a given operand.
-
-Tue Feb 11 15:26:47 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (_print_insn_mips): Set bytes_per_chunk and
-	display_endian.
-	(print_insn_mips16): Likewise.
-
-Mon Feb 10 10:12:41 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_symbol_to_value): Changed to accept
-	a symbol class that restricts translation to just that
-	class (general register, condition code, etc).
-
-Thu Feb  6 17:34:09 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
-	and REG_DEST_E for register operands that have to be
-	an even numbered register.  Add REG_FPA for operands that
-	are one of the floating point accumulator registers.
-	Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
-	(tic80_opcodes): Change entries that need even numbered
-	register operands to use the new operand table entries.
-	Add "or" entries that are identical to "or.tt" entries.
-
-Wed Feb  5 11:12:44 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips16-opc.c: Add new cases of exit instruction for
-	disassembler.
-	* mips-dis.c (print_mips16_insn_arg): Display floating point
-	registers in operands of exit instruction.  Print `$' before
-	register names in operands of entry and exit instructions.
-
-Thu Jan 30 14:09:03 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_predefined_symbols): Table of name/value
-	pairs for all predefined symbols recognized by the assembler.
-	Also used by the disassembling routines.
-	(tic80_symbol_to_value): New function.
-	(tic80_value_to_symbol): New function.
-	* tic80-dis.c (print_operand_control_register,
- 	print_operand_condition_code, print_operand_bitnum):
-	Remove private tables and use tic80_value_to_symbol function.
-
-Thu Jan 30 11:30:45 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-dis.c (print_operand): Change address printing
-	to correctly handle PC wrapping.  Fixes PR11490.
-
-Wed Jan 29 09:39:17 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
-	branches relaxable.
-
-Tue Jan 28 15:57:34 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_insn_mips16): Set insn_info information.
-	(print_mips16_insn_arg): Likewise.
-
-	* mips-dis.c (print_insn_mips16): Better handling of an extend
- 	opcode followed by an instruction which can not be extended.
-
-Fri Jan 24 12:08:21 1997  J.T. Conklin  <jtc@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
- 	coldfire moveb instruction to not allow an address register as
- 	destination.  Although the documentation does not indicate that
-	this is invalid, experiments uncovered unexpected behavior.
-	Added a comment explaining the situation.  Thanks to Andreas
-	Schwab for pointing this out to me.
-
-Wed Jan 22 20:13:51 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_opcodes): Expand comment to note that the
- 	entries are presorted so that entries with the same mnemonic are
-	adjacent to each other in the table.  Sort the entries for each
-	instruction so that this is true.
-
-Mon Jan 20 12:48:57 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c: Include <libiberty.h>.
-	(print_insn_m68k): Sort the opcode table on the most significant
-	nibble of the opcode.
-
-Sat Jan 18 15:15:05 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
-	"vsub", "vst", "xnor", and "xor" instructions.
-	(V_a1): Renamed from V_a, msb of accumulator reg number.
-	(V_a0): Add macro, lsb of accumulator reg number.
-
-Fri Jan 17 18:24:31 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (print_insn_tic80): Broke excessively long
-	function up into several smaller ones and arranged for
-	the instruction printing function to be callable recursively
-	to print vector instructions that have both a load and a
-	math instruction packed into a single opcode.
-	* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
-	to explain why it comes after the other vector opcodes.
-
-Fri Jan 17 16:19:15 1997  J.T. Conklin  <jtc@beauty.cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
-	move insns to handle immediate operands.
-
-Thu Jan 17 16:19:00 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
-	fix operand mask in the "moveml" entries for the coldfire.
-
-Thu Jan 16 20:54:40 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):
-	New macros for building vector instruction opcodes.
-	(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
-	FMT_LI, which were unused.  The field is now a flags field.
-	Remove some opcodes that are possible, but illegal, such
-	as long immediate instructions with doubles for immediate
-	values.  Add "vadd" and "vld" instructions.
-
-Wed Jan 15 18:59:51 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (tic80_operands): Reorder some table entries to make
-	the order more logical.  Move the shift alias instructions ("rotl",
-	"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
- 	interspersed with the regular sr.x and sl.x instructions.  Add
-	and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
- 	"sub", "subu", "swcr", and "trap".
-
-Tue Jan 14 19:42:50 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS.
-	(OFF_SL_PC): Renamed from OFF_SL.
-	(OFF_SS_BR): New operand type for base relative operand.
-	(OFF_SL_BR): New operand type for base relative operand.
-	(REG_BASE): New operand type for base register operand.
-	(tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp",
-	"frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr",
-	"ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr"
-	instructions.
-	* tic80-dis.c (print_insn_tic80): Print opcode name with fixed width
- 	10 char field, padded with spaces on rhs, rather than a string
- 	followed by a tab.  Use renamed TIC80_OPERAND_PCREL flag bit rather
- 	than old TIC80_OPERAND_RELATIVE.  Add support for new
-	TIC80_OPERAND_BASEREL flag bit.
-
-Mon Jan 13 15:58:56 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (print_insn_tic80): Print floating point operands
-	as floats.
-	* tic80-opc.c (SPFI): Add single precision floating point
-	immediate operand type.
-	(ROTATE): Add rotate operand type for shifts.
-	(ENDMASK): Add for shifts.
-	(n): Macro for the 'n' bit.
-	(i): Macro for the 'i' bit.
-	(PD): Macro for the 'PD' field.
-	(P2): Macro for the 'P2' field.
-	(P1): Macro for the 'P1' field.
-	(tic80_opcodes): Add entries for "exts", "extu", "fadd",
-	"fcmp", and "fdiv".
-
-Mon Jan  6 15:06:55 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-dis.c (disassemble): Mask off unwanted bits after
-	adding in current address for pc-relative operands.
-
-Mon Jan  6 10:56:25 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit.
-	(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
-	* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
-	changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
-	(SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
-	REG_BASE_M_SI, REG_BASE_M_LI respectively.
-	(REG_SCALED, LSI_SCALED): New operand types.
-	(E): New macro for 'E' bit at bit 27.
-	(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
-	opcodes, including the various size flavors (b,h,w,d) for
-	the direct load and store instructions.
-
-Sun Jan  5 12:18:14 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
- 	in an instruction.
-	* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
-  	Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
-	* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
-	(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New	bit-twiddlers.
-	(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
-	masks with "MASK_* & ~M_*" to get the M bit reset.
-	(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
-
-Sat Jan  4 19:05:05 1997  Fred Fish  <fnf@cygnus.com>
-
-	* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
-	correctly.  Add support for printing TIC80_OPERAND_BITNUM and
-	TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
-	form.
-	* tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
-	CC, SICR, and LICR table entries.
-	(tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
-	"bcnd", and "brcr" opcodes.
-
-Fri Jan  3 18:32:11 1997  Fred Fish  <fnf@cygnus.com>
-
-	* ppc-opc.c (powerpc_operands): Make comment match the
-	actual fields (no shift field).
-	* sparc-opc.c (sparc_opcodes): Document why this cannot be "const".
-	* tic80-dis.c (print_insn_tic80): Replace abort stub with a
-	partial implementation, work in progress.
-	* tic80-opc.c (tic80_operands): Begin construction operands table.
-	(tic80_opcodes): Continue populating opcodes table and start
-	filling in the operand indices.
-	(tic80_num_opcodes): Add this.
-
-Fri Jan  3 12:13:52 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Add #B case for moveq.
-
-Thu Jan  2 12:14:29 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-dis.c (disassemble): Make sure all variables are initialized
-	before they are used.
-
-Tue Dec 31 12:20:38 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_opcodes): Put curly-braces around operands
-	for "breakpoint" instruction.
-
-Tue Dec 31 15:38:13 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
-	(dep): Use ALL_CFLAGS rather than CFLAGS.
-
-Tue Dec 31 15:09:16 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY
-	flag.
-
-Mon Dec 30 17:02:11 1996  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
-	(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
-
-Mon Dec 30 11:38:01 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips16-opc.c: Add "abs".
-
-Sun Dec 29 10:58:22 1996  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
-	* disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
-	(disassembler): Add bfd_arch_tic80 support to set disassemble
- 	to print_insn_tic80.
-	* tic80-dis.c (print_insn_tic80): Add stub.
-
-Fri Dec 27 22:30:57 1996  Fred Fish  <fnf@cygnus.com>
-
-	* configure.in (arch in $selarchs): Add bfd_tic80_arch entry.
-	* configure: Regenerate with autoconf.
-	* tic80-dis.c: Add file.
-	* tic80-opc.c: Add file.
-
-Fri Dec 20 14:30:19 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (pre_defined_registers):  Add cr[0-15], dpc, dpsw, link.
-
-Mon Dec 16 13:00:15 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-opc.c (mn10200_operands): Add SIMM16N.
-	(mn10200_opcodes): Use it for some logicals and btst insns.
-	Add "break" and "trap" instructions.
-
-	* mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
-
-	* mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".
-
-Sat Dec 14 22:36:20 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_mips16_insn_arg): The base address of a PC
-	relative load or add now depends upon whether the instruction is
-	in a delay slot.
-
-Wed Dec 11 09:23:46 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-dis.c: Finish writing disassembler.
-	* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
-	Fix mask for "jmp (an)".
-
-	* mn10300-dis.c (disassemble, print_insn_mn10300): Corrently
-	handle endianness issues for mn10300.
-
-	* mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".
 
-Tue Dec 10 12:08:05 1996  Jeffrey A Law  (law@cygnus.com)
+2000-06-18  Stephane Carrez  <stcarrez@worldnet.fr>
 
-	* mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
-	instruction.  Fix opcode field for "movb (imm24),dn".
+	* Makefile.in, configure: regenerate
+	* disassemble.c (disassembler): Recognize ARCH_m68hc12,
+	ARCH_m68hc11.
+	* m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12):
+	New functions.
+	* configure.in: Recognize m68hc12 and m68hc11.
+	* m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x
+	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
+	and opcode generation for m68hc11 and m68hc12.
 
-	* mn10200-opc.c (mn10200_operands): Fix insertion position
-	for DI operand.
+2000-06-16  Nick Duffek  <nsd@redhat.com>
 
-Mon Dec  9 16:42:43 1996  Jeffrey A Law  (law@cygnus.com)
+	* disassemble.c (disassembler): Refer to the PowerPC 620 using
+	bfd_mach_ppc_620 instead of 620.
 
-	* mn10200-opc.c: Create mn10200 opcode table.
-	* mn10200-dis.c: Flesh out mn10200 disassembler.  Not ready,
-	but moving along nicely.
+2000-06-12  Kazu Hirata  <kazu@hxi.com>
 
-Sun Dec  8 04:28:31 1996  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+	* h8300-dis.c: Fix formatting.
+	(bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl]
+	correctly.
 
-	* Makefile.in (ALL_MACHINES):  Add mips16-opc.o.
+2000-06-09  Denis Chertykov  <denisc@overta.ru>
 
-Fri Dec  6 16:47:40 1996  J.T. Conklin  <jtc@rhino.cygnus.com>
+	* avr-dis.c (avr_operand): Bugfix for jmp/call address.
 
-	* m68k-opc.c (m68k_opcodes): Revert change to use < and >
-	specifiers for fmovem* instructions.
+2000-06-07  Denis Chertykov  <denisc@overta.ru>
 
-Fri Dec  6 14:48:09 1996  Jeffrey A Law  (law@cygnus.com)
+	* avr-dis.c: completely rewritten.
 
-	* mn10300-dis.c (disassemble): Remove '$' register prefixing.
+2000-06-02  Kazu Hirata  <kazu@hxi.com>
 
-Fri Dec  6 17:34:39 1996  Ian Lance Taylor  <ian@cygnus.com>
+	* h8300-dis.c: Follow the GNU coding style.
+	(bfd_h8_disassemble) Fix a typo.
 
-	* mips16-opc.c: Change opcode for entry/exit to avoid conflicting
-	with dsrl.
+2000-06-01  Kazu Hirata  <kazu@hxi.com>
 
-Fri Dec  6 14:48:09 1996  Jeffrey A Law  (law@cygnus.com)
+	* h8300-dis.c (bfd_h8_disassemble_init): Fix a typo.
+	(bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl]
+	correctly.  Fix a typo.
 
-	* mn10300-opc.c: Add some comments explaining the various
- 	operands and such.
+2000-05-31  Nick Clifton  <nickc@redhat.com>
 
-	* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
+	* opintl.h (_(String)): Explain why dgettext is used instead of
+	gettext.
 
-Thu Dec  5 12:09:48 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+2000-05-30  Nick Clifton  <nickc@redhat.com>
 
-	* m68k-dis.c (print_insn_arg): Handle new < and > operand
-	specifiers.
+	* opintl.h (gettext, dgettext, dcgettext, textdomain,
+	bindtextdomain): Replace defines with those from intl/libgettext.h
+	to quieten gcc warnings.
 
-	* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
-	operand specifiers in fmovm* instructions.
+2000-05-26  Alan Modra  <alan@linuxcare.com.au>
 
-Wed Dec  4 14:52:18 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* ppc-opc.c (insert_li): Give an error if the offset has the two
-	least significant bits set.
-
-Wed Nov 27 13:09:01 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_insn_mips16): Separate the instruction from
-	the arguments with a tab, not a space.
-
-Tue Nov 26 13:24:17 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-dis.c (disasemble): Finish conversion to '$' as
-	register prefix.
-
-	* mn10300-opc.c (mn10300_opcodes): Fix mask field for
-	mov am,(imm32,sp).
-
-Tue Nov 26 10:53:21 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild with autoconf 2.12.
-
-	Add support for mips16 (16 bit MIPS implementation):
-	* mips16-opc.c: New file.
-	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
-	(mips16_reg_names): New static array.
-	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
-	after seeing a 16 bit symbol.
-	(print_insn_little_mips): Likewise.
-	(print_insn_mips16): New static function.
-	(print_mips16_insn_arg): New static function.
-	* mips-opc.c: Add jalx instruction.
-	* Makefile.in (mips16-opc.o): New target.
-	* configure.in: Use mips16-opc.o for bfd_mips_arch.
-	* configure: Rebuild.
-
-Mon Nov 25 16:15:17 1996  J.T. Conklin  <jtc@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
- 	operand specifiers in *save, *restore and movem* instructions.
-
-	* m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
- 	the coldfire.
-
-	* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
- 	register operands for immediate arithmetic, not, neg, negx, and
-	set according to condition instructions.
-
-	* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
- 	specifier of the effective-address operand in immediate forms of
- 	arithmetic instructions.  The specifier for the immediate operand
- 	notes how and where the constant will be stored.
-
-Mon Nov 25 11:17:01 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
-	opcode.
-
-	* mn10300-dis.c (disassemble): Use '$' instead of '%' for
-	register prefix.
-
-	* mn10300-dis.c (disassemble): Prefix registers with '%'.
-
-Wed Nov 20 10:37:13 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-dis.c (disassemble): Handle register lists.
-
-	* mn10300-opc.c: Fix handling of register list operand for
-	"call", "ret", and "rets" instructions.
-
-	* mn10300-dis.c (disassemble): Print PC-relative and memory
-	addresses symbolically if possible.
-	* mn10300-opc.c: Distinguish between absolute memory addresses,
-	pc-relative offsets & random immediates.
-
-	* mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte
-	in 7 byte insns.
-	(disassemble): Handle SPLIT and EXTENDED operands.
-
-Tue Nov 19 13:33:01 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-dis.c: Rough cut at printing some operands.
-
-	* mn10300-dis.c: Start working on disassembler support.
-	* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
-
-	* mn10300-opc.c (mn10300_operands): Add "REGS" for a register
-	list.
-	(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-
-Mon Nov 18 15:20:35 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
-
-Fri Nov 15 13:43:19 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Demand parens around
-	register argument is calls and jmp instructions.
-
-Thu Nov  7 00:26:05 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
-	getx operand.  Fix opcode for mulqu imm,dn.
-
-Wed Nov  6 13:42:32 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_operands): Hijack "bits" field
-	in MN10300_OPERAND_SPLIT operands for how many bits
-	appear in the basic insn word.  Add IMM32_HIGH24,
-	IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
-	(mn10300_opcodes): Use new operands as needed.
-
-	* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
-	for bset, bclr, btst instructions.
-	(mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
-
-	* mn10300-opc.c (mn10300_operands): Remove many redundant
-	operands.  Update opcode table as appropriate.
-	(IMM32): Add MN10300_OPERAND_SPLIT flag.
-	(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
-
-Tue Nov  5 13:26:58 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
-	operands (for indexed load/stores).  Fix bitpos for DI
-	operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
-	few instructions that insert immediates/displacements in the
-	middle of the instruction.  Add IMM8E for 8 bit immediate in
-	the extended part of an instruction.
-	(mn10300_operands): Use new opcodes as appropriate.
-
-Tue Nov  5 10:30:51 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Declare the trap instruction
- 	sequential so the assembler never parallelizes it with
-	other instructions.
-
-Mon Nov  4 12:50:40 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
-	a data/address register that appears in register field 0
-	and register field 1.
-	(mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
-
-Fri Nov  1 10:29:11 1996  Richard Henderson  <rth@tamu.edu>
-
-	* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
-	standard disassembly.
-
-	* alpha-opc.c (alpha_operands): Rearrange flags slot.
-	(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
-	Recategorize PALcode instructions.
-
-Wed Oct 30 16:46:58 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_opcodes): Add relaxing "jbr".
-
-Tue Oct 29 16:30:28 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (_print_insn_mips): Don't print a trailing tab if
-	there are no operand types.
-
-Tue Oct 29 12:22:21 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (D9_RELAX): Renamed from D9, all references
-	changed.
-	(v850_operands): Make sure D22 immediately follows D9_RELAX.
-
-Fri Oct 25 12:12:53 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5.
-
-Thu Oct 24 17:53:52 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
-	and sst.w instructions.
-
-	* v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
-	"bCC"instructions).
-
-Thu Oct 24 17:21:20 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (_print_insn_mips): Use a tab between the instruction
-	and the arguments.
-
-Tue Oct 22 23:32:56 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* ppc-opc.c (PPCPWR2): Define.
-	(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
-	it.
-
-Fri Oct 11 16:03:49 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
-	field for movhu instruction.
-
-	* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
-	cast value to "long" not "signed long" to keep hpux10
-	compiler quiet.
-
-Thu Oct 10 10:25:58 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
-	for mov (abs16),DN.
-
-	* mn10300-opc.c (FMT*): Remove definitions.
-
-	* mn10300-opc.c (mn10300_opcodes): Fix destination register
-	for shift-by-register opcodes.
-
-	* mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
-	into [AD][MN][01] for encoding the position of the register
-	in the opcode.
-
-Wed Oct  9 11:19:26 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
-	"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
-
-Tue Oct  8 11:55:35 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
-	Fix various typos.  Add "PAREN" operand.
-	(MEM, MEM2): Define.
-	(mn10300_opcodes): Surround all memory addresses with "PAREN"
-	operands.  Fix several typos.
-
-	* mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
-	changes.
-
-Mon Oct  7 16:48:45 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10300-opc.c (FMT_XX): Renumber starting at one.
-	(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
-	at this time.
-	(mn10300_opcodes): Break opcode format out into its own field.
-	Update many operand fields to deal with signed vs unsigned
-	issues.  Fix one or two typos in the "mov" instruction
-	opcode, mask and/or operand fields.
-
-Mon Oct  7 11:39:49 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
-	m68851 wasn't reset.
-
-Thu Oct  3 17:17:02 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
-	all opcodes.  Very rough cut at operands for all opcodes.
-
-	* mn10300-opc.c (mn10300_opcodes): Start fleshing out the
-	opcode table.
-
-Thu Oct  3 10:06:07 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10200-opc.c, mn10300-opc.c: New files.
-	* mn10200-dis.c, mn10300-dis.c: New files.
-	* mn10x00-opc.c, mn10x00-dis.c: Deleted.
-	* disassemble.c: Break mn10x00 support into 10200 and 10300
-	support.
-	* configure.in: Likewise.
-	* configure: Rebuilt.
-
-Thu Oct  3 15:59:12 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
-
-	* Makefile.in (MOSTLYCLEAN): Move config.log to distclean.
-
-Wed Oct  2 23:28:42 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita
-	MN10x00 processors.
-	* disassemble (ARCH_mn10x00): Define.
-	(disassembler): Handle bfd_arch_mn10x00.
-	* configure.in: Recognize bfd_mn10x00_arch.
-	* configure: Rebuilt.
-
-Tue Oct  1 10:49:11 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c (op_rtn): Change to be a pointer.  Adjust uses
-	accordingly.  Don't declare functions using op_rtn.
-
-Fri Sep 27 18:28:59 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* v850-dis.c (disassemble):  Add memaddr argument.  Re-arrange
-	params to be more standard.
-	* (disassemble):  Print absolute addresses and symbolic names for
-	branch and jump targets.
-	* v850-opc.c (v850_operand):  Add displacement flag to 9 and 22
-	bit operands.
-	* (v850_opcodes):  Add breakpoint insn.
-
-Mon Sep 23 12:32:26 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Move the fmovemx data register cases before the
- 	other cases, so that they get recognized before the data register
- 	does gets treated as a degenerate register list.
-
-Tue Sep 17 12:06:51 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-opc.c: Add a case for "div" and "divu" with two registers
-	and a destination of $0.
-
-Tue Sep 10 16:12:39 1996  Fred Fish  <fnf@rtl.cygnus.com>
-
-	* mips-dis.c (print_insn_arg): Add prototype.
-	(_print_insn_mips): Ditto.
-
-Mon Sep  9 14:26:26 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_insn_arg): Print condition code registers as
- 	$fccN.
-
-Tue Sep  3 12:09:46 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx.
-
-Tue Sep  3 12:05:25 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-dis.c (disassemble): Make static.  Provide prototype.
-
-Sun Sep  1 22:30:40 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (insert_d9, insert_d22): Fix boundary case
-	in range checks.
-
-Sat Aug 31 01:27:26 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-dis.c (disassemble): Handle insertion of ',', '[' and
-	']' characters into the output stream.
-	* v850-opc.c (v850_opcodes: Remove size field from all opcodes.
-	Add "memop" field to all opcodes (for the disassembler).
-	Reorder opcodes so that "nop" comes before "mov" and "jr"
-	comes before "jarl".
-
-	* v850-dis.c (print_insn_v850): Fix typo in last change.
-
-	* v850-dis.c (print_insn_v850): Properly handle disassembling
-	a two byte insn at the end of a memory region when the memory
-	region's size is only two byte aligned.
-
-	* v850-dis.c (v850_cc_names): Fix stupid thinkos.
-
-	* v850-dis.c (v850_reg_names): Define.
-	(v850_sreg_names, v850_cc_names): Likewise.
-	(disassemble): Very rough cut at printing operands (unformatted).
-
-	* v850-opc.c (BOP_MASK): Fix.
-	(v850_opcodes): Fix mask for jarl and jr.
-
-	* v850-dis.c: New file.  Skeleton for disassembler support.
-	* Makefile.in Remove v850 references, they're not needed here.
-	* configure.in: Add v850-dis.o when building v850 toolchains.
-	* configure: Rebuilt.
-	* disassemble.c (disassembler): Call v850 disassembler.
-
-	* v850-opc.c (insert_d8_7, extract_d8_7): New functions.
-	(insert_d8_6, extract_d8_6): New functions.
-	(v850_operands): Rename D7S to D7; operand for D7 is unsigned.
-	Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
-	Add D8_6.
-	(IF4A, IF4B): Use "D7" instead of "D7S".
-	(IF4C, IF4D): Use "D8_7" instead of "D8".
-	(IF4E, IF4F): New.  Use "D8_6".
-	(v850_opcodes): Use IF4A/IF4B for sld.b/sst.b.  Use IF4C/IF4D for
-	sld.h/sst.h.  Use IF4E/IF4F for sld.w/sst.w.
-
-	* v850-opc.c (insert_d16_15, extract_d16_15): New functions.
-	(v850_operands): Change D16 to D16_15, use special insert/extract
-	routines.  New new D16 that uses the generic insert/extract code.
-	(IF7A, IF7B): Use D16_15.
-	(IF7C, IF7D): New.  Use D16.
-	(v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
-
-	* v850-opc.c (insert_d9, insert_d22): Slightly improve error
-	message.  Issue an error if the branch offset is odd.
-
-	* v850-opc.c: Add notes about needing special insert/extract
-	for all the load/store insns, except "ld.b" and "st.b".
-
-	* v850-opc.c (insert_d22, extract_d22): New functions.
-	(v850_operands): Use insert_d22 and extract_d22 for
-	D22 operands.
-	(insert_d9): Fix range check.
-
-Fri Aug 30 18:01:02 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
-
-	* v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag
-	and set bits field to D9 and D22 operands.
-
-Thu Aug 29 11:10:46 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_operands): Define SR2 operand.
-	(v850_opcodes): "ldsr" uses R1,SR2.
-
-	* v850-opc.c (v850_opcodes): Fix opcode specs for
-	sld.w, sst.b, sst.h, sst.w, and nop.
-
-Wed Aug 28 15:55:43 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_opcodes): Add null opcode to mark the
-	end of the opcode table.
-
-Mon Aug 26 13:35:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (pre_defined_registers): Added register pairs,
-	"r0-r1", "r2-r3", etc.
-
-Fri Aug 23 00:27:01 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_operands): Make I16 be a signed operand.
-	Create I16U for an unsigned 16bit mmediate operand.
-	(v850_opcodes): Use I16U for "ori", "andi" and "xori".
-
-	* v850-opc.c (v850_operands): Define EP operand.
-	(IF4A, IF4B, IF4C, IF4D): Use EP.
-
-	* v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
-	with immediate operand, "movhi".  Tweak "ldsr".
-
-	* v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
-	correct.  Get sld.[bhw] and sst.[bhw] closer.
-
-	* v850-opc.c (v850_operands): "not" is a two byte insn
-
-	* v850-opc.c (v850_opcodes): Correct bit pattern for setf.
-
-	* v850-opc.c (v850_operands): D16 inserts at offset 16!
-
-	* v850-opc.c (two): Get order of words correct.
-
-	* v850-opc.c (v850_operands): I16 inserts at offset 16!
-
-	* v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
-	register source and destination operands.
-	(v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
-
-	* v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.  Fix
-	same thinko in "trap" opcode.
-
-	* v850-opc.c (v850_opcodes): Add initializer for size field
-	on all opcodes.
-
-	* v850-opc.c (v850_operands): D6 -> DS7.  References changed.
-	Add D8 for 8-bit unsigned field in short load/store insns.
-	(IF4A, IF4D): These both need two registers.
-	(IF4C, IF4D): Define.  Use 8-bit unsigned field.
-	(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
-	IF4C & IF4D.  For "trap" use I5U, not I5.  Add IF1 operand
-	for "ldsr" and "stsr".
-	* v850-opc.c (v850_operands): 3-bit immediate for bit insns
-	is unsigned.
-
-	* v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
-	short store word (sst.w).
-
-Thu Aug 22 16:57:27 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* v850-opc.c (v850_operands): Added insert and extract fields,
- 	pointers to functions that handle unusual operand encodings.
-
-Thu Aug 22 01:05:24 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_opcodes): Enable "trap".
-
-	* v850-opc.c (v850_opcodes): Fix order of displacement
-	and register for "set1", "clr1", "not1", and "tst1".
-
-Wed Aug 21 18:46:26 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* v850-opc.c (v850_operands): Add "B3" support.
-	(v850_opcodes): Fix and enable "set1", "clr1", "not1"
-	and "tst1".
-
-	* v850-opc.c (v850_opcodes): "jmp" has only an R1 operand.
-
-	* v850-opc.c: Close unterminated comment.
-
-Wed Aug 21 17:31:26 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
-
-	* v850-opc.c (v850_operands): Add flags field.
- 	(v850_opcodes): add move opcodes.
-
-Tue Aug 20 14:41:03 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
-
-	* Makefile.in (ALL_MACHINES): Add v850-opc.o.
-	* configure: (bfd_v850v_arch) Add new case.
-	* configure.in: (bfd_v850_arch) Add new case.
-	* v850-opc.c: New file.
-
-Mon Aug 19 15:21:38 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
-
-Thu Aug 15 13:14:43 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c: Add additional information to the opcode
-	table to help determinine which instructions can be done
-	in parallel.
-
-Thu Aug 15 13:11:13 1996  Stan Shebs  <shebs@andros.cygnus.com>
-
-	* mpw-make.sed: Update editing of include pathnames to be
-	more general.
-
-Thu Aug 15 16:28:41 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* arm-opc.h: Added "bx" instruction definition.
-
-Wed Aug 14 17:00:04 1996  Richard Henderson  <rth@tamu.edu>
-
-	* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
-
-Mon Aug 12 14:30:37 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
-
-Fri Aug  9 13:21:59 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
-
-Thu Aug  8 12:43:52 1996  Klaus Kaempf  <kkaempf@progis.de>
-
-	* makefile.vms: Update for alpha-opc changes.
-
-Wed Aug  7 11:55:10 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c (print_insn_i386): Actually return the correct value.
- 	(ONE, OP_ONE): #ifdef out; not used.
-
-Fri Aug  2 17:47:03 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
-	Changed subi operand type to treat 0 as 16.
-
-Wed Jul 31 16:21:41 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Add cpushl for the mcf5200.  From Ken Rose
-	<rose@netcom.com>.
-
-Wed Jul 31 14:39:27 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* arm-opc.h: (arm_opcodes): Added halfword and sign-extension
- 	memory transfer instructions. Add new format string entries %h and %s.
-	* arm-dis.c: (print_insn_arm): Provide decoding of the new
-	formats %h and %s.
-
-Fri Jul 26 11:45:04 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
- 	(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
-
-Fri Jul 26 14:01:43 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* alpha-dis.c (print_insn_alpha_osf): Remove.
-	(print_insn_alpha_vms): Remove.
-	(print_insn_alpha): Make globally visible.  Chose the register
-	names based on info->flavour.
-	* disassemble.c: Always return print_insn_alpha for the alpha.
-
-Thu Jul 25 15:24:17 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-dis.c (dis_long): Handle unknown opcodes.
-
-Thu Jul 25 12:08:09 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-opc.c: Changes to support signed and unsigned numbers.
-	All instructions with the same name that have long and short forms
-	now end in ".l" or ".s".  Divs added.
-	* d10v-dis.c: Changes to support signed and unsigned numbers.
-
-Tue Jul 23 11:02:53 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* d10v-dis.c: Change all functions to use info->print_address_func.
-
-Mon Jul 22 15:38:53 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
- 	move ccr/sr insns more strict so that the disassembler only
- 	selects them when the addressing mode is data register.
-
-Mon Jul 22 11:25:24 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-        * d10v-opc.c (pre_defined_registers):  Declare.
-        * d10v-dis.c (print_operand): Now uses pre_defined_registers
-        to pick a better name for the registers.
-
-Mon Jul 22 13:47:23 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sparc-opc.c: Fix opcode values for fpack16, and fpackfix.  Fix
-	operands for fexpand and fpmerge.  From Christian Kuehnke
-	<Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>.
-
-Mon Jul 22 13:17:06 1996  Richard Henderson  <rth@tamu.edu>
-
-	* alpha-dis.c (print_insn_alpha): No longer the user-visible
-	print routine.  Take new regnames and cpumask arguments.
-	Kill the environment variable nonsense.
-	(print_insn_alpha_osf): New function.  Do OSF/1 style regnames.
-	(print_insn_alpha_vms): New function.  Do VMS style regnames.
-	* disassemble.c (disassembler): Test bfd flavour to pick
-	between OSF and VMS routines.  Default to OSF.
-
-Thu Jul 18 17:19:34 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Call AC_SUBST (INSTALL_SHLIB).
-	* configure: Rebuild.
-	* Makefile.in (install): Use @INSTALL_SHLIB@.
-
-Wed Jul 17 14:39:05 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
-
-	* configure: (bfd_d10v_arch) Add new case.
-	* configure.in: (bfd_d10v_arch) Add new case.
-	* d10v-dis.c: New file.
-	* d10v-opc.c: New file.
-	* disassemble.c (disassembler) Add entry for d10v.
-
-Wed Jul 17 10:12:05 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
- 	to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab.
-
-Mon Jul 15 16:59:55 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* i386-dis.c:  Get rid of print_insn_i8086.  Use info.mach to
-	distinguish between variants of the instruction set.
-	* sparc-dis.c:  Get rid of print_insn_sparclite.  Use info.mach to
-	distinguish between variants of the instruction set.
-
-Fri Jul 12 10:12:01 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* i386-dis.c (print_insn_i8086):  New routine to disassemble using
-	the 8086 instruction set.
-	* i386-dis.c:  General cleanups.  Make most things static.  Add
-	prototypes.  Get rid of static variables aflags and dflags.  Pass
-	them as args (to almost everything).
-
-Thu Jul 11 11:58:44 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns.
-
-	* h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l".
-
-	* h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two
-	if the next arg is marked with SRC_IN_DST.  Gross.
-
-	* h8300-dis.c (bfd_h8_disassemble): Print "exr" when
-	we're looking for and find EXR.
-
-	* h8300-dis.c (bfd_h8_disassemble): We don't have a match
-	if we're looking for KBIT and we don't find it.
-
-	* h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits
-	for L_3 and L_2.
-
-	* h8300-dis.c (bfd_h8_disassemble): Don't set plen for
-	3bit immediate operands.
-
-Tue Jul  9 10:55:20 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Released binutils 2.7.
-
-	* alpha-opc.c: Add new case of "mov".  From Klaus Kaempf
-	<kkaempf@progis.ac-net.de>.
-
-Thu Jul  4 11:42:51 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* alpha-opc.c: Correct second case of "mov" to use OPRL.
-
-Wed Jul  3 16:03:47 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* sparc-dis.c (print_insn_sparclite):  New routine to print
-	sparclite instructions.
-
-Wed Jul  3 14:21:18 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Add coldfire support.
-
-Fri Jun 28 15:53:51 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS,
-	#ASI_NUCLEUS_LITTLE.  Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L
-	to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE.
-
-Tue Jun 25 22:58:31 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
-
-	* Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir):
-	Use autoconf-set values.
-	(docdir, oldincludedir): Removed.
-	* configure.in (AC_PREREQ): autoconf 2.5 or higher.
-
-Fri Jun 21 13:53:36 1996  Richard Henderson  <rth@tamu.edu>
-
-	* alpha-opc.c: New file.
-	* alpha-opc.h: Remove.
-	* alpha-dis.c: Complete rewrite to use new opcode table.
-	* configure.in: For bfd_alpha_arch, use alpha-opc.o.
-	* configure: Rebuild with autoconf 2.10.
-	* Makefile.in (ALL_MACHINES): Add alpha-opc.o.
-	(alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not
-	alpha-opc.h.
-	(alpha-opc.o): New target.
-
-Wed Jun 19 15:55:12 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Remove unused local variable i.
-	Set imm_added_to_rs1 even if the source and destination register
-	are not the same.
-
-	* sparc-opc.c: Add some two operand forms of the wr instruction.
-
-Tue Jun 18 15:58:27 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
-
-	* h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument
-	to just "mode".
-
-	* disassemble.c (disassembler): Handle H8/S.
-	* h8300-dis.c (print_insn_h8300s): New function for H8/S.
-
-Tue Jun 18 18:06:50 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sparc-opc.c: Add beq/teq as aliases for be/te.
-
-	* ppc-opc.c: Fix fcmpo opcode.  From Sergei Steshenko
-	<sergei@msil.sps.mot.com>.
-
-Tue Jun 18 15:08:54 1996  Klaus Kaempf  <kkaempf@progis.de>
-
-	* makefile.vms: New file.
-
-	* alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov.
-
-Mon Jun 10 18:50:38 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8,
-	regardless of plen.
-
-Tue Jun  4 09:15:53 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* i386-dis.c (OP_OFF): Call append_prefix.
-
-Thu May 23 15:18:23 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (instruction encoding macros): Add explicit casts to
-	unsigned long to silence a warning from the Solaris PowerPC
-	compiler.
-
-Thu Apr 25 19:33:32 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions.
-
-Mon Apr 22 17:12:35 1996  Doug Evans  <dje@blues.cygnus.com>
-
-	* sparc-dis.c (X_IMM,X_SIMM): New macros.
-	(X_IMM13): Delete.
-	(print_insn_sparc): Merge cases i,I,j together.  New cases X,Y.
-	* sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants,
-	Y for 6 bit shift constants.  Rewrite entries for crdcxt, cwrcxt,
-	cpush, cpusha, cpull sparclet insns.
-
-Wed Apr 17 14:20:22 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R.
-
-Thu Apr 11 17:30:02 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sparc-opc.c: Set F_FBR on floating point branch instructions.
-	Set F_FLOAT on other floating point instructions.
-
-Mon Apr  8 17:02:48 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (PPC860): Macro for 860/821 specific instructions and
-	registers.
- 	(powerpc_opcodes): Add 860/821 specific SPRs.
-
-Mon Apr  8 14:00:44 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Permit --enable-shared to specify a list of
-	directories.  Set and substitute BFD_PICLIST.
-	* configure: Rebuild.
-	* Makefile.in (BFD_PICLIST): Rename from BFD_LIST.  Change all
-	uses.  Set to @BFD_PICLIST@.
-
-Fri Apr  5 17:12:27 1996  Jeffrey A Law  (law@cygnus.com)
-
-	* h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates,
-	not "abs", which may be needed for the absolute in something
-	like btst #0,@10:8.  Print L_3 immediates separately from other
-	immediates.  Change ABSMOV reference to ABS8MEM.
-
-Wed Apr  3 10:40:45 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc.
-	(current_arch_mask): New static global.
-	(compute_arch_mask): New static function.
-	(print_insn_sparc): Delete sparc_v9_p.  New static local
-	current_mach.  Resort opcode table if current_mach changes.
-	Generalize "insn not supported" test.
-	(compare_opcodes): Prefer supported opcodes to nonsupported ones.
-	Delete test for v9/!v9.
-	* sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
-	(v6notlet): Define.
-	(brfc): Split into CBR and FBR for coprocessor/fp branches.
-	(brfcx): Renamed to FBRX.
-	(condfc): Renamed to CONDFC.  Pass v6notlet to CBR (standard
-	coprocessor mnemonics are not supported on the sparclet).
-	(condf): Renamed to CONDF.
-	(SLCBCC2): Delete F_ALIAS flag.
-
-Sat Mar 30 21:45:59 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): rd must be 0 for
-	mov foo,{%y,%psr,%wim,%tbr}.  Support mov foo,%asrX.
-
-Fri Mar 29 13:02:40 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (config.status): Depend upon BFD VERSION file, so
-	that the shared library version number is set correctly.
-
-Tue Mar 26 15:47:14 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Use AC_CHECK_TOOL to find ar and ranlib.  From
-	Miles Bader <miles@gnu.ai.mit.edu>.
-	* configure: Rebuild.
-
-Sat Mar 16 13:04:07 1996  Fred Fish  <fnf@cygnus.com>
-
-	* z8kgen.c (internal, gas): Call xmalloc rather than unchecked
-	malloc.
-
-Tue Mar 12 12:14:10 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild with autoconf 2.8.
-
-Thu Mar  7 15:11:10 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'.
-	* sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'.
-
-Tue Mar  5 15:51:57 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Don't set SHLIB or SHLINK to an empty string,
-	since they appear as targets in Makefile.in.
-	* configure: Rebuild.
-
-Mon Feb 26 13:03:40 1996  Stan Shebs  <shebs@andros.cygnus.com>
-
-	* mpw-make.sed: Edit out shared library support bits.
-
-Tue Feb 20 20:48:28 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET.
-	(sparc_opcode_archs): Add MASK_V8 to sparclet entry.
-	(sparc_opcodes): Add sparclet insns.
-	(sparclet_cpreg_table): New static local.
-	(sparc_{encode,decode}_sparclet_cpreg): New functions.
-	* sparc-dis.c (print_insn_sparc): Handle sparclet cpregs.
-
-Tue Feb 20 11:02:44 1996  Alan Modra  <alan@mullet.Levels.UniSA.Edu.Au>
-
-	* i386-dis.c (index16): New static variable.
-	(putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the
-	other way around.
-	(OP_indirE): Return result of OP_E.
-	(OP_E): Check for 16 bit addressing mode, and disassemble
-	correctly.  Optimised 32 bit case a little.  Don't print
-	"(base,index,scale)" when sib specifies only an offset.
-
-Mon Feb 19 12:32:17 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Set and substitute SHLIB_DEP.
-	* configure: Rebuild.
-	* Makefile.in (SHLIB_DEP): New variable.
-	(LIBIBERTY_LISTS, BFD_LIST): New variables.
-	(stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST.  If
-	COMMON_SHLIB, add them to piclist with appropriate modifications.
-	($(SHLIB)): Depend upon $(SHLIB_DEP).  Don't check COMMON_SHLIB
-	here: just use piclist.
-
-Mon Feb 19 02:03:50 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define.
-	(print_insn_sparc): Rewrite v9/not-v9 tests.
-	(compare_opcodes): Likewise.
-	* sparc-opc.c (MASK_<ARCH>): Define.
-	(v6,v7,v8,sparclite,v9,v9a): Redefine.
-	(sparclet,v6notv9): Define.
-	(sparc_opcode_archs): Delete member `conflicts'.  Add `supported'.
-	(sparc_opcodes): Delete F_NOTV9, use v6notv9 instead.
-
-Thu Feb 15 14:45:05 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Call AC_PROG_CC before configure.host.
-	* configure: Rebuild.
-
-	* Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB).
-
-Wed Feb 14 19:01:27 1996  Alan Modra  <alan@spri.levels.unisa.edu.au>
-
-	* i386-dis.c (onebyte_has_modrm): New static array.
-	(twobyte_has_modrm): New static array.
-	(print_insn_i386): Only fetch the mod/reg/rm byte if it is needed.
-
-Tue Feb 13 15:15:01 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not
-	$(SHLINK).
-
-Mon Feb 12 16:26:06 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (PPC): Undef, so default defination on Windows NT
-	doesn't conflict.
-
-Wed Feb  7 13:59:54 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on
-	m68010up, not just m68020up | cpu32.
-
-	* Makefile.in (SONAME): New variable.
-	($(SHLINK)): Make a link to the transformed name, as well.
-	(stamp-tshlink): New target.
-	(install): Skip stamp-tshlink during install.
-
-Tue Feb  6 12:28:54 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Call AC_ARG_PROGRAM.
-	* configure: Rebuild.
-	* Makefile.in (program_transform_name): New variable.
-	(install): Transform library name before installing it.
-
-Mon Feb  5 16:14:42 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i960-dis.c (mem): Add HX dcinva instruction.
-
-	Support for building as a shared library, based on patches from
-	Alan Modra <alan@spri.levels.unisa.edu.au>:
-	* configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib.
-	New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC,
-	SHLIB_CFLAGS, COMMON_SHLIB, SHLINK.
-	* configure: Rebuild.
-	* Makefile.in (ALLLIBS): New variable.
-	(PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables.
-	(COMMON_SHLIB, SHLINK): New variables.
-	(.c.o): If PICFLAG is set, compile twice, once PIC, once normal.
-	(STAGESTUFF): Remove variable.
-	(all): Depend upon $(ALLLIBS) rather than $(TARGETLIB).
-	(stamp-piclist, piclist): New targets.
-	($(SHLIB), $(SHLINK)): New targets.
-	($(OFILES)): Depend upon stamp-picdir.
-	(disassemble.o): Build twice if PICFLAG is set.
-	(MOSTLYCLEAN): Add pic/*.o.
-	(clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist.
-	(distclean): Remove pic and stamp-picdir.
-	(install): Install shared libraries.
-	(stamp-picdir): New target.
-
-Fri Feb  2 17:15:25 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support.
-	Print unknown instruction as "unknown", rather than in hex.
-
-Tue Jan 30 14:06:08 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* dis-buf.c: Include "sysdep.h" before "dis-asm.h".
-
-Thu Jan 25 20:24:07 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting.
-
-Thu Jan 25 11:56:49 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte
-	when necessary.  From Ulrich Drepper
-	<drepper@myware.rz.uni-karlsruhe.de>.
-
-Thu Jan 25 03:39:10 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with
-	sparc_num_opcodes.  Update architecture enum values.
-	* sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname.
-	(sparc_opcode_lookup_arch): New function.
-	(sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes.
-	(sparc_opcodes): Add v9a shutdown insn.
-
-Mon Jan 22 08:29:59 1996  Doug Evans  <dje@charmed.cygnus.com>
-
-	* sparc-dis.c (print_insn_sparc): Renamed from print_insn.
-	If DISASM_RAW_INSN, print insn in hex.  Handle v9a as opcode
-	architecture.
-	(print_insn_sparc64): Deleted.
-	* disassemble.c (disassembler, case bfd_arch_sparc): Always use
-	print_insn_sparc.
-
-	* sparc-opc.c (architecture_pname): Add v9a.
-
-Fri Jan 12 14:35:58 1996  David Mosberger-Tang  <davidm@AZStarNet.com>
-
-	* alpha-opc.h (alpha_insn_set): VAX floating point opcode was
- 	incorrectly defined as 0x16 when it should be 0x15.
-	(FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits!
-	(alpha_insn_set): added cvtst and cvttq float ops.  Also added
- 	excb (exception barrier) which is defined in the Alpha
- 	Architecture Handbook version 2.
-	* alpha-dis.c (print_insn_alpha): Fixed special-case decoding for
- 	OPERATE_FORMAT_CODE type instructions.  The bug caused mulq to be
- 	disassembled as or, for example.
-
-Wed Jan 10 12:37:22 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex.
-	(_print_insn_mips): Change i from int to unsigned int.
-
-Thu Jan  4 17:21:10 1996  David Edelsohn  <edelsohn@mhpcc.edu>
-
-	* ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different
-	from tlbie PowerPC opcode.  Add PPC603 tlbld and tlbli.
-
-Thu Dec 28 13:29:19 1995  John Hassey  <hassey@rtp.dg.com>
-
-	* i386-dis.c: Added Pentium Pro instructions.
-
-Tue Dec 19 22:56:35 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to
-	being for Power2.
-
-Fri Dec 15 14:14:15 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* sh-opc.h (sh_nibble_type): Added REG_B.
-	(sh_arg_type): Added A_REG_B.
-	(sh_table): Added pref and bank reg versions of ldc, ldc.l, stc
- 	and stc.l opcodes.
-	* sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B.
-
-Fri Dec 15 16:44:31 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* disassemble.c (disassembler): Use new bfd_big_endian macro.
-
-Tue Dec 12 12:22:24 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (distclean): Remove stamp-h.  From Ronald
-	F. Guilmette <rfg@monkeys.com>.
-
-Tue Dec  5 13:42:44 1995  Stan Shebs  <shebs@andros.cygnus.com>
-
-	From David Mosberger-Tang  <davidm@azstarnet.com>:
-	* alpha-dis.c (print_insn_alpha): fixed decoding of cpys
- 	instruction.
-
-Mon Dec  4 12:29:05 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* sh-opc.h (sh_arg_type): Added A_SSR and A_SPC.
-	(sh_table): Added many SH3 opcodes.
-	* sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC.
-
-Fri Dec  1 07:42:18 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC.
-	(subco,subco.): Mark this PPC, not PPCCOM.
-
-Mon Nov 27 13:09:52 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild with autoconf 2.7.
-
-Tue Nov 21 18:28:06 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild with autoconf 2.6.
-
-Wed Nov 15 19:02:53 1995  Ken Raeburn  <raeburn@cygnus.com>
-
-	* configure.in: Sort list of architectures.  Accept but do nothing
-	for alliant, convex, pyramid, romp, and tahoe.
-
-Wed Nov  8 20:18:59 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* a29k-dis.c (print_special): Change num to unsigned int.
-
-Wed Nov  8 20:10:35 1995  Eric Freudenthal <freudenthal@nyu.edu>
-
-	* a29k-dis.c (print_insn): Cast insn24 to unsigned long when
-	shifting it.
-
-Tue Nov  7 15:21:06 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Call AC_CHECK_PROG to find and cache AR.
-	* configure: Rebuilt.
-
-Mon Nov  6 17:39:47 1995  Harry Dolan  <dolan@ssd.intel.com>
-
-	* configure.in: Add case for bfd_i860_arch.
-	* configure: Rebuild.
-
-Fri Nov  3 12:45:31 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (m68k_opcodes): Correct fmoveml operands.
-	* m68k-dis.c (NEXTSINGLE): Change i to unsigned int.
-	(NEXTDOUBLE): Likewise.
-	(print_insn_m68k): Don't match fmoveml if there is more than one
-	register in the list.
-	(print_insn_arg): Handle a place of '8' for a type of 'L'.
-
-Thu Nov  2 23:06:33 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Use #W rather than #w.
-	* m68k-dis.c (print_insn_arg): Handle new 'W' place.
-
-Wed Nov  1 13:30:24 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf,
-	and likewise for all the dbxx opcodes.
-
-Mon Oct 30 20:50:40 1995  Fred Fish  <fnf@cygnus.com>
-
-	* arc-dis.c: Include elf-bfd.h rather than libelf.h.
-
-Mon Oct 23 11:11:34 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
-
-	* mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added
- 	the VR4100 specific instructions to the mips_opcodes structure.
-
-Thu Oct 19 11:05:23 1995  Stan Shebs  <shebs@andros.cygnus.com>
-
-	* mpw-config.in, mpw-make.sed: Remove ugly workaround for
-	ugly Metrowerks bug in CW6, is fixed in CW7.
-
-Mon Oct 16 12:59:01 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
-
-	* ppc-opc.c (whole file): Add flags for common/any support.
-
-Tue Oct 10 11:06:07 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (BISON): Remove macro.
-	(FLAGS_TO_PASS): Remove BISON.
-
-Fri Oct  6 16:26:45 1995  Ken Raeburn  <raeburn@cygnus.com>
-
-	Mon Sep 25 22:49:32 1995  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* m68k-dis.c (print_insn_m68k): Recognize all two-word
-	instructions that take no args by looking at the match mask.
-  	(print_insn_arg): Always print "%" before register names.
-	[case 'c']: Use "nc" for the no-cache case, as recognized by gas.
-	[case '_']: Don't print "@#" before address.
-	[case 'J']: Use "%s" as format string, not register name.
-	[case 'B']: Treat place == 'C' like 'l' and 'L'.
-
-Thu Oct  5 22:16:20 1995  Ken Raeburn  <raeburn@cygnus.com>
-
-	* i386-dis.c: Describe cmpxchg8b operand, and spell the opcode
-	name correctly.
-
-Tue Oct  3 08:30:20 1995  steve chamberlain  <sac@slash.cygnus.com>
-
-	From David Mosberger-Tang  <davidm@azstarnet.com>
-
-	* alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
-  	(alpha_insn_set): added definitions for VAX floating point
- 	instructions (Unix compilers don't generate these, but handcoded
- 	assembly might still use them).
-
-	* alpha-dis.c (print_insn_alpha): added support for disassembling
- 	the miscellaneous instructions in the Alpha instruction set.
-
-Tue Sep 26 18:47:20 1995  Stan Shebs  <shebs@andros.cygnus.com>
-
-	* mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k,
-	no longer create sysdep.h, sed ppc-opc.c to work around a
-	serious Metrowerks C bug.
-	* mpw-make.in: Remove.
-	* mpw-make.sed: New file, used by mpw-configure to edit
-	Makefile.in into an MPW makefile.
-
-Wed Sep 20 12:55:28 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (maintainer-clean): New synonym for realclean.
-
-Tue Sep 19 15:28:36 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: Split pmove patterns which use 'P' into patterns
-	which use '0', '1', and '2' instead.  Specify the proper size for
-	a pmove immediate operand.  Correct the pmovefd patterns to be
-	moves to a register, not from a register.
-	* m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'.
-
-Thu Sep 14 11:58:22 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Mark all insns that reference
-	%psr, %wim, %tbr as F_NOTV9.
-
-Fri Sep  8 01:07:38 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (Makefile): Just rebuild Makefile when running
-	config.status.
-	(config.h, stamp-h): New targets.
-	* configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM
-	earlier.  Don't bother to call AC_ARG_PROGRAM.  Touch stamp-h when
-	rebuilding config.h.
-	* configure: Rebuild.
-
-	* mips-opc.c: Change unaligned loads and stores with "t,A"
-	operands to use "t,A(b)".
-
-Thu Sep  7 19:02:46 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-dis.c (print_insn_shx): Add F_FR0 support.
-
-Thu Sep  7 19:02:46 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate
-	until 3 instead of until 2.
-
-Wed Sep  6 21:21:33 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (ALL_CFLAGS): Define.
-	(.c.o, disassemble.o): Use $(ALL_CFLAGS).
-	(MOSTLYCLEAN): Add config.log.
-	(distclean): Don't remove config.log.
-	* configure.in: Substitute HDEFINES.
-	* configure: Rebuild.
-
-Wed Sep  6 15:08:09 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-opc.h (sh_arg_type): Add F_FR0.
-	(sh_table, case fmac): Add F_FR0 as first argument.
-
-Wed Sep  6 15:08:09 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-opc.h (sh_opcode_info): Increase arg array size to 4.
-
-Tue Sep  5 18:28:10 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c: Remove all references to NO_V9.
-
-Tue Sep  5 20:03:26 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* aclocal.m4: Just include ../bfd/aclocal.m4.
-	* configure: Rebuild.
-
-Tue Sep  5 16:09:59 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c (X_DISP19): Define.
-	(print_insn, case 'G'): Use it.
-	(print_insn, case 'L'): Sign extend displacement.
-
-Mon Sep  4 14:28:46 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Run ../bfd/configure.host before AC_PROG_CC.
-	Subsitute CFLAGS and AR.  Call AC_PROG_INSTALL.  Don't substitute
-	host_makefile_frag or frags.
-	* aclocal.m4: New file.
-	* configure: Rebuild.
-	* Makefile.in (INSTALL): Set to @INSTALL@.
-	(INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@.
-	(INSTALL_DATA): Set to @INSTALL_DATA@.
-	(AR): Set to @AR@.
-	(AR_FLAGS): Set to rc rather than qc.
-	(CC): Define as @CC@.
-	(CFLAGS): Set to @CFLAGS@.
-	(@host_makefile_frag@): Remove.
-	(config.status): Remove dependency upon @frags@.
-
-	* configure.in: ../bfd/config.bfd now just sets shell variables.
-	Use them rather than looking through target Makefile fragments.
-	* configure: Rebuild.
-
-Thu Aug 31 12:35:32 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-opc.h (ftrc): Change FPUL_N to FPUL_M.
-
-Wed Aug 30 13:52:28 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn.
-	Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic
-	sparc64 insns.
-
-	* sparc-opc.c (sparc_opcodes): Fix prefetcha insn.
-	(lookup_{name,value}): New functions.
-	(prefetch_table): New static local.
-	(sparc_{encode,decode}_prefetch): New functions.
-	* sparc-dis.c (print_insn): Handle '*' arg (prefetch function).
-
-Wed Aug 30 11:11:58 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-opc.h: Add blank lines to improve readabililty of sh3e
-	instructions.
-
-Wed Aug 30 11:09:38 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
-
-	* sh-dis.c: Correct comment on first line of file.
-
-Tue Aug 29 15:37:18 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* disassemble.c (disassembler): Handle bfd_mach_sparc64.
-
-	* sparc-opc.c (asi, membar): New static locals.
-	(sparc_{encode,decode}_{asi,membar}): New functions.
-	(sparc_opcodes, membar insn): Fix.
-	* sparc-dis.c (print_insn): Call sparc_decode_asi.
-	Support decoding of membar masks.
-	(X_MEMBAR): Define.
-
-Sat Aug 26 21:22:48 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl.
-
-Mon Aug 21 17:33:36 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis,
-	and likewise for the other branches.  Add bhs as an alias for bcc,
-	and likewise for the size variants.  Add dbhs as an alias for
-	dbcc.
-
-Fri Aug 11 13:40:24 1995  Jeff Law  (law@snake.cs.utah.edu)
-
-	* sh-opc.h (FP sts instructions): Update to match reality.
-
-Mon Aug  7 16:12:58 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-dis.c: (fpcr_names): Add % before all register names.
-	(reg_names): Likewise.
-	(print_insn_arg): Don't explicitly print % before register names.
-	Add % before register names in static array names.  In case 'r',
-	print data registers as `@(Dn)', not `Dn@'.  When printing a
-	memory address, don't print @# before it.
-	(print_indexed): Change base_disp and outer_disp from int to
-	bfd_vma.  Print using MIT syntax, not mutant invalid Motorola
-	syntax.  Sign extend 8 byte displacement correctly.
-	(print_base): Print using MIT syntax.  Print zpc when appropriate.
-	Change parameter disp from int to bfd_vma.
-
-	* m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases
-	for jsr.
-
-Mon Aug  7 02:21:40 1995  Jeff Law  (law@snake.cs.utah.edu)
-
-	* sh-dis.c (print_insn_shx): Handle new operand types F_REG_N,
-	F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N.
-	* sh-opc.h (sh_arg_type): Add new operand types.
-	(sh_table): Add new opcodes from SH3E Floating Point ISA.
-
-Sat Aug  5 16:50:14 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (distclean): Remove generated file config.h.
-
-Sat Aug  5 16:50:14 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (distclean): Remove generated file config.h.
-
-Wed Aug  2 18:33:40 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* m68k-opc.c: New file, holding tables from include/opcode/m68k.h.
-	Clean up tables.
-	* m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff.
-	(opcode): Remove.
-	(print_insn_m68k): Change d to be const.  Use m68k_numopcodes
-	rather than numopcodes.  Use m68k_opcodes rather than removed
-	opcode function.  Don't check F_ALIAS.
-	(print_insn_arg): Change first parameter to be const char *.
-	* Makefile.in (ALL_MACHINES): Add m68k-opc.o.
-	(m68k-opc.o): New target.
-	* configure.in: Build m68k-opc.o for bfd_m68k_arch.
-	* configure: Rebuild.
-
-Wed Aug  2 08:23:38 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-dis.c (HASH_SIZE, HASH_INSN): Define.
-	(opcode_bits, opcode_hash_table): New variables.
-	(opcodes_initialized): Renamed from opcodes_sorted.
-	(build_hash_table): New function.
-	(is_delayed_branch): Use hash table.
-	(print_insn): Renamed from print_insn_sparc, made static.
-	Build and use hash table.  If !sparc64, ignore sparc64 insns,
-	and vice-versa if sparc64.
-	(print_insn_sparc, print_insn_sparc64): New functions.
-	(compare_opcodes): Move sparc64 opcodes to end.
-	Print commutative insns with constant second.
-	* sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
-
-Tue Aug  1 00:12:49 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* sh-dis.c (print_insn_shx): Remove unused local dslot.  Use
-	print_address_func for A_BDISP12 and A_BDISP8.  Correct test which
-	avoids printing a delay slot in a delay slot.
-	* sh-opc.h (sh_table): Fully bracket last entry.
-
-Mon Jul 31 12:04:47 1995  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sparc-opc.c (sllx, srax, srlx): Fix disassembly.
-
-Wed Jul 12 00:59:34 1995  Ken Raeburn  <raeburn@kr-pc.cygnus.com>
-
-	* configure.in: Get host_makefile_frag from ${srcdir}.
-
-	* configure.in: Autoconfiscated.  Check for string[s].h.  Create
-	config.h from config.in.  Don't set up sysdep.h link.
-	* sysdep.h: New file.
-	* configure, config.in: New files, generated from configure.in.
-	* Makefile.in: Updated to be processed autoconf-style.
-	(distclean): Keep sysdep.h.  Remove config.log and config.cache.
-	(Makefile): Depend on config.status.
-	(config.status): New rule.
-	* configure.bat: Update Makefile substitutions.
-
-Tue Jul 11 14:23:37 1995  Jeff Spiegel  <jeffs@lsil.com>
-
-	* mips-opc.c (L1): Define.
-	(mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
-	addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
-	and wb.
-
-Tue Jul 11 11:49:49 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
-	if ISA 3 and addu otherwise, replacing or, since some MIPS chips
-	have multiple add units but only a single logical unit.
-
-	* ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3,
-	shifted by 18, without any insertion or extraction function.
-	(insert_cr, extract_cr): Remove.
-
-Wed Jun 21 20:05:39 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
-
-	* m68k-dis.c (print_insn_arg, print_indexed): Print "%" before
-	register names.
+	* Makefile.am: Update dependencies with "make dep-am"
+	* Makefile.in: Regenerate.
 
-Thu Jun 15 17:23:31 1995  Stan Shebs  <shebs@andros.cygnus.com>
+2000-05-25  Alexandre Oliva  <aoliva@redhat.com>
 
-	* mpw-config.in: Add sh and i386 configs, remove sparc config.
-	* sh-opc.h: Add copyright.
+	* m10300-dis.c (disassemble): Don't assume 32-bit longs when
+	sign-extending operands.
 
-Mon Jun  5 03:30:43 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+2000-05-15  Donald Lindsay  <dlindsay@redhat.com>
 
-	* Makefile.in (crunch-m68k): Delete extra target accidentally
-	checked in a while ago.
+	* d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches
+	except brf's.
 
-Wed May 24 16:22:13 1995  Jim Wilson  <wilson@chestnut.cygnus.com>
+2000-05-21  Nick Clifton  <nickc@redhat.com>
 
-	* sh-opc.h (sh_table): Add SH3 support.
+	* Makefile.am (LIBIBERTY): Define.
 
-Wed May 24 14:16:08 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+2000-05-19 Diego Novillo <dnovillo@redhat.com>
 
-	* sh-opc.h: Added bsrf and braf.
+	* mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.
+	(STD_REGISTER_NAMES): New name for REGISTER_NAMES.
+	(reg_names): Rename to std_reg_names. Change it to a char **
+	static variable.
+	(std_reg_names): New name for reg_names.
+	(set_mips_isa_type): Set reg_names to point to std_reg_names by
+	default.
 
-Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+2000-05-16  Frank Ch. Eigler  <fche@redhat.com>
 
-	* arm-opc.h (arm_opcodes): Add 64-bit multiply patterns.  Delete
-	bogus [ls]fm{ea,fd} patterns.
+	* fr30-desc.h: Partially regenerated to account for changed
+	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
+	* m32r-desc.h: Ditto.
 
-	* arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc.
-	* arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and
-	initialize it from memory.  Make function static.
-	(print_insn_{big,little}_arm): New functions.
-	* disassemble.c (disassembler, case bfd_arch_arm): Disassemble for
-	the correct endianness.
+2000-05-15  Nick Clifton  <nickc@redhat.com>
 
-Mon Apr 24 14:18:05 1995  Jason Molenda   (crash@phydeaux.cygnus.com>
+	* arm-opc.h: Use upper case for flasg in MSR and MRS
+	instructions.  Allow any bit to be set in the field_mask of
+	the MSR instruction.
 
-	* sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from
-	enum list.
+	* arm-dis.c (print_insn_arm): Decode _x and _s bits of the
+	field_mask of an MSR instruction.
 
-Wed Apr 19 14:07:03 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+2000-05-11  Thomas de Lellis  <tdel@windriver.com>
 
-	* m68k-dis.c (opcode): Finish change made by Kung Hsu on April
-	17th, so that it builds again using GCC as the compiler.
+	* arm-opc.h: Disassembly of thumb ldsb/ldsh
+	instructions changed to ldrsb/ldrsh.
 
-Tue Apr 18 12:14:51 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+2000-05-11  Ulf Carlsson  <ulfc@engr.sgi.com>
 
-	* mips-dis.c (print_insn_little_mips): Cast return value from
-	bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips
-	expects an unsigned long, and that might be fewer words of
-	argument storage (e.g., if bfd_vma is long long on a 32-bit
-	machine).
-	(print_insn_big_mips): Likewise with bfd_getb32 value.
-	(_print_insn_mips): Now static.
+	* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
+	target addresses for 'jal' and 'j'.
 
-Mon Apr 17 12:23:28 1995  Kung Hsu  <kung@rtl.cygnus.com>
+2000-05-10  Geoff Keating  <geoffk@redhat.com>
 
-	* m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because
-	gcc memory hog problem with initializer is fixed.
+	* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
+	also available in common mode when powerpc syntax is being used.
 
-Mon Apr 10 15:55:01 1995  Stan Shebs  <shebs@andros.cygnus.com>
+2000-05-08  Alan Modra  <alan@linuxcare.com.au>
 
-	Merge in support for Mac MPW as a host.
-	(Old change descriptions retained for informational value.)
+	* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
+	(dummy_print_address): Ditto.
 
-	* mpw-config.in (archname): Compute from the config.
-	(BFD_MACHINES, ARCHDEFS): Put into mk.tmp.
+2000-05-04  Timothy Wall  <twall@redhat.com>
 
-	* mpw-config.in (target_arch): Compute from canonical target.
-	(m68k, mips, powerpc, sparc): Add architectures.
-	* mpw-make.in (disassemble.c.o): Add.
-	(ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
+	* tic54x-opc.c: New.
+	* tic54x-dis.c: New.
+	* disassemble.c (disassembler): Add ARCH_tic54x.
+	* configure.in: Added tic54x target.
+	* configure: Ditto.
+	* Makefile.am: Add tic54x dependencies.
+	* Makefile.in: Ditto.
 
-	* mpw-config.in (BFD_MACHINES): Set to a default value.
-	* mpw-make.in (BFD_MACHINES): Remove wired-in value.
+2000-05-03  J.T. Conklin  <jtc@redback.com>
 
-	* mpw-make.in (CSEARCH): Add extra-include to search path.
+	* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
+	vector unit operands.
+	(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
+	unit instruction formats.
+	(PPCVEC): New macro, mask for vector instructions.
+	(powerpc_operands): Add table entries for above operand types.
+	(powerpc_opcodes): Add table entries for vector instructions.
 
-	* mpw-config.in (varargs.h): Don't create.
-	(sysdep.h): Create using forward-include.
-	* mpw-make.in (CSEARCH): Add include/mpw to search path.
+	* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
+	(print_insn_little_powerpc): Likewise.
+	(print_insn_powerpc): Prepend 'v' when printing vector registers.
 
-	* mpw-config.in: New file, MPW version of configure.in.
-	* mpw-make.in: New file, MPW version of Makefile.in.
+2000-04-24  Clinton Popetz  <cpopetz@redhat.com>
 
-Fri Mar 31 14:23:38 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+	* configure.in: Add bfd_powerpc_64_arch.
+	* disassemble.c (disassembler): Use print_insn_big_powerpc for
+	64 bit code.
 
-	* alpha-dis.c (print_insn_alpha): Put empty statement after
-	default label.
+2000-04-24  Nick Clifton  <nickc@redhat.com>
 
-Tue Mar 21 10:51:40 1995  Jeff Law  (law@snake.cs.utah.edu)
+	* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
+	field.
 
-	* hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version.
-	(low_sign_extend): Likewise.
-	(get_field): Delete unused function.
-	(set_field, deposit_14, deposit_21): Likewise.
+2000-04-23  Denis Chertykov  <denisc@overta.ru>
 
-Fri Mar 17 15:55:53 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
+	* avr-dis.c (reg_fmul_d): New. Extract destination register from
+	FMUL instruction.
+	(reg_fmul_r): New. Extract source register from FMUL instruction.
+	(reg_muls_d): New. Extract destination register from MULS instruction.
+	(reg_muls_r): New. Extract source register from MULS instruction.
+	(reg_movw_d): New. Extract destination register from MOVW instruction.
+	(reg_movw_r): New. Extract source register from MOVW instruction.
+	(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
+	EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.
 
-	* i386-dis.c: Support for more pentium opcodes.  From Guy Harris
-	  (guy@netapp.com).
+2000-04-22  Timothy Wall  <twall@redhat.com>
 
-Tue Mar 14 00:52:57 1995  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+	* ia64-gen.c (general): Add an ordered table of primary
+	opcode names, as well as priority fields to disassembly data
+	structures to enforce a preferred disassembly format based on the
+	ordering of the opcode tables.
+	(load_insn_classes): Show a useful message if IC tables are missing.
+	(load_depfile): Ditto.
+	* ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
+	distinguish preferred disassembly.
+	* ia64-opc-f.c: Reorder some insn for preferred disassembly
+	format.  Fix incorrect flag on fma.s/fma.s.s0.
+	* ia64-opc.c: Scan *all* disassembly matches and use the one with
+	the highest priority.
+	* ia64-opc-b.c: Use more abbreviations.
+	* ia64-asmtab.c: Regenerate.
 
-	Sat Feb 11 17:22:41 1995  Klaus Kaempf  (kkaempf@didymus.rmi.de)
+2000-04-21  Jason Eckhardt  <jle@redhat.com>
 
-	* alpha-opc.h (OSF_ASMCODE): define
-	print pal-code names as defined in App C of the
-	Alpha Architecture Reference Manual
+	* hppa-dis.c (extract_16): New function.
+	(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
+	new operand types l,y,&,fe,fE,fx.
 
-	* alpha-dis.c: cleaned up output
-	print stylized code forms as defined in App A.4.3 of the
-	Alpha Architecture Reference Manual
+2000-04-21  Richard Henderson  <rth@redhat.com>
+	    David Mosberger  <davidm@hpl.hp.com>
+	    Timothy Wall <twall@redhat.com>
+	    Bob Manson  <manson@charmed.cygnus.com>
+	    Jim Wilson  <wilson@redhat.com>
 
-Wed Mar  8 15:21:14 1995  Ian Lance Taylor  <ian@cygnus.com>
+	* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
+	(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
+	ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
+	ia64-asmtab.c.
+	(ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
+	(ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
+	ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
+	* Makefile.in: Rebuild.
+	* configure Rebuild.
+	* configure.in (bfd_ia64_arch): New target.
+	* disassemble.c (ARCH_ia64): Define.
+	(disassembler): Support ARCH_ia64.
+	* ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
+	ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
+	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
+	ia64-war.tbl, ia64-waw.tbl: New files.
 
-	* mips-opc.c: Add new mips4 instructions.  Don't set INSN_RFE for
-	`rfe'.
-	* mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R',
-	'N', and 'M'.
+2000-04-20  Alexandre Oliva  <aoliva@redhat.com>
 
-Wed Mar  8 02:54:05 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
+	(disassemble): Use them.
 
-	* m68k-dis.c (opcode): New function.  Returns address of opcode
-	table entry given index, even if the opcode table was split to
-	work around gcc bugs.
-	(print_insn_m68k): Call opcode instead of referencing m68k_opcodes
-	directly.
-	(BREAK_UP_BIG_DECL): Make secondary array static and const.
-	(reg_names): Now const.
-	(print_insn_arg): Arrays cacheFieldName and names now const.
-	(print_indexed): Array scales now const.
+2000-04-14  Alan Modra  <alan@linuxcare.com.au>
 
-Tue Mar  7 16:41:21 1995  Ian Lance Taylor  <ian@cygnus.com>
+	* sysdep.h: Include "ansidecl.h" not <ansidecl.h>
+	* Makefile.am: Update dependencies.
+	* Makefile.in: Regenerate.
 
-	* ppc-opc.c: Sort recently added instructions by minor opcode
-	number within major opcode number.
+2000-04-14  Michael Sokolov  <msokolov@ivan.Harhan.ORG>
 
-Mon Mar  6 10:04:36 1995  Jeff Law  (law@snake.cs.utah.edu)
+	* a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
+	avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
+	disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
+	i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
+	m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
+	mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
+	ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
+	tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
+	w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h.  Remove
+	ansidecl.h as sysdep.h includes it.
 
-	* hppa-dis.c: Include libhppa.h.
+2000-04-7  Andrew Cagney  <cagney@b1.redhat.com>
 
-Fri Feb 24 19:15:36 1995  Ian Lance Taylor  <ian@cygnus.com>
+	* configure.in (WARN_CFLAGS): Set to -W -Wall by default.  Add
+	--enable-build-warnings option.
+	* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
+	* Makefile.in, configure: Re-generate.
 
-	* mips-opc.c: Change dli to use M_DLI, and add dla.
+2000-04-05  J"orn Rennecke <amylaar@redhat.com>
 
-Mon Feb 20 23:54:38 1995  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+	* sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
+	stc GBR,@-<REG_N> is available for arch_sh1_up.
+	Group parallel processing insn with identical mnemonics together.
+	Make three-operand psha / pshl come first.
 
-	* Makefile.in (ALL_MACHINES):  Add w65-dis.o.
+2000-04-05  J"orn Rennecke <amylaar@redhat.co.uk>
 
-Thu Feb 16 17:34:41 1995  Ian Lance Taylor  <ian@cygnus.com>
+	* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
+	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
+	(sh_arg_type): Add A_PC.
+	(sh_table): Update entries using immediates.  Add repeat.
+	* sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
+	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
 
-	* mips-opc.c: Add r4650 mul instruction.
+2000-04-04  Alan Modra  <alan@linuxcare.com.au>
 
-Wed Feb 15 15:45:20 1995  Ian Lance Taylor  <ian@cygnus.com>
+	* po/opcodes.pot: Regenerate.
 
-	* mips-opc.c: Add uld and usd macros for unaligned double load and
-        store.
+	* Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
+	(DEP): Quote when passing vars to sub-make.  Add warning message
+	to end.
+	(DEP1): Rewrite for "gcc -MM".
+	(CLEANFILES): Add DEP2.
+	Update dependencies.
+	* Makefile.in: Regenerate.
 
-Tue Feb 14 13:17:37 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+2000-04-03  Denis Chertykov  <denisc@overta.ru>
 
-	* ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
-	mfdcr, mtdcr, icbt, iccci.
+	* avr-dis.c: Syntax cleanup.
+	(add0fff): Print the pc relative address as a signed number.
+	(add03f8): Likewise.
 
-Thu Feb  9 12:28:13 1995  Stan Shebs  <shebs@andros.cygnus.com>
+2000-04-01  Ian Lance Taylor  <ian@zembu.com>
 
-	* i960-dis.c (struct tabent, struct sparse_tabent): Change the
-        signed char fields to shorts, more portable.
+	* disassemble.c (disassembler_usage): Don't use a prototype.  Mark
+	the parameter ATTRIBUTE_UNUSED.
+	* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.
 
-Wed Feb  8 17:29:29 1995  Stan Shebs  <shebs@andros.cygnus.com>
+2000-04-01  Alexandre Oliva  <aoliva@redhat.com>
 
-	* i960-dis.c (struct tabent, struct sparse_tabent): Declare the
-        char fields as signed chars, since they may have negative values.
+	* m10300-opc.c: SP-based offsets are always unsigned.
 
-Mon Feb  6 10:52:06 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
+2000-03-29  Thomas de Lellis  <tdel@windriver.com>
 
-	* i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum
-	  (mycroft@netbsd.org).
+	* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
+	[branch always] instead of "undefined".
 
-Mon Jan 30 12:38:00 1995  Ian Lance Taylor  <ian@cygnus.com>
+2000-03-27  Nick Clifton  <nickc@redhat.com>
 
-	From "Logg, Ed" <elogg@ea.com>:
-	* ppc-opc.c (extract_bdm): Correct parenthezisation.
-	* ppc-dis.c (print_insn_powerpc): Print .long before unrecognized
-	value.
+	* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
+	short instructions, from end of list of long instructions.
 
-Thu Jan 26 18:32:08 1995  Ian Lance Taylor  <ian@cygnus.com>
+2000-03-27  Ian Lance Taylor  <ian@zembu.com>
 
-	* ppc-opc.c: Changes based on patch from David Edelsohn
-	<edelsohn@mhpcc.edu>.
-	(powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of
-	SPR.
-	(FXM_MASK): Define.
-	(insert_tbr): New static function.
-	(extract_tbr): New static function.
-	(XFXFXM_MASK, XFXM): Define.
-	(XSPRBAT_MASK, XSPRG_MASK): Define.
-	(powerpc_opcodes): Add instructions to access special registers by
-	name.  Add mtcr and mftbu.
+	* Makefile.am (CFILES): Add avr-dis.c.
+	(ALL_MACHINES): Add avr-dis.lo.
 
-Tue Jan 17 10:56:43 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+2000-03-27  Alan Modra  <alan@linuxcare.com>
 
-	* mips-opc.c (P3): Define.
-	(mips_opcodes): Add mad and madu.
+	* avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
+	truncate integers.
+	(print_insn_avr): Call function via pointer in K&R compatible way.
+	(dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
+	add0fff, add03f8): Convert to old style function declaration and
+	add prototype.
+	(avrdis_opcode): Add prototype.
 
-Sun Jan 15 16:32:59 1995  Steve Chamberlain  <sac@splat>
+2000-03-27  Denis Chertykov  <denisc@overta.ru>
 
-	* configure.in: Add W65 support.
+	* avr-dis.c: New file.  AVR disassembler.
+	* configure.in (bfd_avr_arch): New architecture support.
 	* disassemble.c: Likewise.
-	* w65-opc.h, w65-dis.c: New files.
-
-Wed Dec 28 22:15:33 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
-
-	* h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit
-	immediates.
-
-Tue Dec 20 11:25:12 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* mips-opc.c: Add dli as a synonym for li.
-
-Thu Dec  8 18:23:31 1994  Ken Raeburn  <raeburn@cujo.cygnus.com>
-
-	* alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and
-	print something for reserved opcode values, even if it won't
-	assemble again.
-
-	* mips-dis.c (_print_insn_mips): When initializing, shift right
-	and mask, to avoid sign extension problems on the Alpha.
-
-	* m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr
-	control registers.
-
-Wed Nov 23 22:34:51 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
-
-	* sh-opc.h (mov.l gbr): Get direction right.
-	* sh-dis.c (print_insn_shx): New function.
-	(print_insn_shl, print_insn_sh): Call print_insn_shx to
-	print opcodes with right byte order.
-
-Thu Nov  3 19:32:22 1994  Ken Raeburn  <raeburn@cujo.cygnus.com>
-
-	* ns32k-dis.c (struct ns32k_option): Renamed from struct option,
-	to avoid conflicts with getopt.
-
-Mon Oct 31 18:48:10 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* hppa-dis.c (print_insn_hppa): Read the instruction using
-	bfd_getb32, so that it works on a little endian or 64 bit host.
-	Remove unused local variable op.
-
-Tue Oct 25 17:07:57 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* mips-opc.c: Use or instead of addu for pseudo-op move, since
-	addu does not work correctly if -mips3.
-
-Wed Oct 19 13:40:16 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* a29k-dis.c (print_special): Add special register names defined
-	on 29030, 29040 and 29050.
-	(print_insn): Handle new operand type 'I'.
-
-Wed Oct 12 11:59:55 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* Makefile.in (INSTALL): Use top level install.sh script.
-
-Wed Oct  5 19:16:29 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* sparc-dis.c: Rewrite to use bitfields, rather than a union, so
-	that it works on a little endian host.
-
-Tue Oct  4 12:14:21 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
-
-	* configure.in: Use ${config_shell} when running config.bfd.
-
-Wed Sep 21 18:49:12 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* mips-opc.c (mips_opcodes): "dabs" is only available with -mips3.
-
-Thu Sep 15 16:30:22 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* a29k-dis.c (print_insn): Print the opcode.
-
-Wed Sep 14 17:52:14 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* mips-opc.c (mips_opcodes): Set WR_t for sc and scd.
-
-Sun Sep 11 22:32:17 1994  Jeff Law  (law@snake.cs.utah.edu)
-
-	* hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3.
-
-Tue Sep  6 11:37:12 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions
-	which store a value into memory.
-
-Sun Sep 04 17:58:10 1994  Richard Earnshaw (rwe@pegasus.esprit.ec.org)
-
-	* configure.in, Makefile.in, disassemble.c: Add support for the ARM.
-	* arm-dis.c, arm-opc.h: New files.
-
-Fri Aug  5 14:00:05 1994  Stan Shebs  (shebs@andros.cygnus.com)
-
-	* Makefile.in (ns32k-dis.o): Add dependency.
-	* ns32k-dis.c (print_insn_arg): Declare initialized local as
-	string, not as array of chars.
-
-Thu Jul 28 18:14:16 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
-
-	* sparc-dis.c (print_insn_sparc): Handle new operand type 'x'.
-
-	* sparc-opc.c: Added sparclite extended FP operations, and
-	versions of v9 impdep* instructions permitting specification of
-	the OPF field.
-
-Tue Jul 26 16:36:03 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
-
-	* i960-dis.c (reg_names): Now const.
-	(struct sparse_tabent): New type, copied from array type in mem
-	function.
-	(ctrl): Local static array ctrl_tab now const.
-	(cobr): Local static array cobr_tab now const.
-	(mem): Local variables reg1, reg2, reg3 now point to const.  Local
-	static variable mem_tab no longer explicitly initialized.  Changed
-	mem_init to const array of struct sparse_tabent.
-	(reg): Local static variable reg_tab no longer explicitly
-	initialized.  Changed reg_init to const array of struct
-	sparse_tabent.
-	(ea): Local static array scale_tab now const.
-
-	* i960-dis.c (reg): Added i960JX instructions to reg_init table.
-	(REG_MAX): Updated.
-
-Tue Jul 19 21:00:00 1994  DJ Delorie (dj@ctron.com)
-
-	* configure.bat: the disassember needs to be enabled for
-	"objdump -d" to work in djgpp.
-
-Wed Jul 13 18:01:58 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
-
-	* ns32k-dis.c: Deleted all code in "#ifdef GDB".
-	(invalid_float): Enabled general version, doesn't require running
-	on ns32k host.  Changed to take char* argument, and test for
-	explicitly specified sizes, instead of using sizeof() on host CPU
-	types.
-	(INVALID_FLOAT): Cast first argument.
-	(opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532,
-	list_P032, list_M032): Now const.
-	(optlist, list_search): Made appropriate arguments now point to
-	const.
-	(print_insn_arg): Changed static array of one-character-string
-	pointers into a static const array of characters; fixed sprintf
-	statement accordingly.
-
-Sun Jul 10 00:27:47 1994  Ian Dall  (dall@hfrd.dsto.gov.au)
-
-	* opcodes/ns32k-dis.c: Semi-new file.  Had apparently been dropped
-	from distribution. A ns32k-dis.c from a previous distribution has
-	been brought up to date and supports the new interface.
-
-	* disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
-
-	* configure.in: add bfd_ns32k_arch target support.
-
-	* Makefile.in: add ns32k-dis.o to ALL_MACHINES.
-	Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
-
-Wed Jun 29 22:10:37 1994  Steve Chamberlain  (sac@cygnus.com)
-
-	* h8300-dis.c (bfd_h8_disassemble): Get 16bit branch
-	disassembly right.
-
-Tue Jun 28 13:22:06 1994  Stan Shebs  (shebs@andros.cygnus.com)
-
-	* h8300-dis.c, mips-dis.c: Don't use true and false.
-
-Thu Jun 23 12:53:19 1994  David J. Mackenzie  (djm@rtl.cygnus.com)
-
-	* configure.in: Change --with-targets to --enable-targets.
-
-Wed Jun 22 13:38:32 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* mips-dis.c (_print_insn_mips): Build a static hash table mapping
-	opcodes to the first instruction with that opcode, to speed
-	disassembly of large files.  From ralphc@pyramid.com (Ralph
-	Campbell).
-
-Tue Jun  7 12:49:44 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* Makefile.in (mostlyclean): Fix typo (was mostyclean).
-
-Wed May 11 22:32:00 1994  DJ Delorie (dj@ctron.com)
-
-	* configure.bat: update to latest makefile.in
-
-Sat May  7 17:13:21 1994  Steve Chamberlain  (sac@cygnus.com)
-
-	* a29k-dis.c (print_insn): Print 'x' type operand in hex.
-	* h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly.
-	* sh-dis.c (print_insn_sh): Don't recur endlessly if delay
-	slot insn is in a delay slot.
-	* z8k-opc.h: (resflg): Fix patterns.
-	* h8500-opc.h Fix CR insn patterns.
-
-Fri May  6 14:34:46 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and
-	"cmpl" before POWER versions, so that gas -many uses them.
-
-Thu Apr 28 18:32:36 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
-
-	* disassemble.c: New file.
-	* Makefile.in (OFILES): Add disassemble.o.
-	(disassemble.o): Provide dependencies; compile with $(ARCHDEFS).
-	* configure.in: Define ARCHDEFS in Makefile.  Code taken from
-	binutils/configure.in.
-
-	* m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the
-	opcode being examined.
-
-Thu Apr 21 17:08:40 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS.
-	(insert_ral, insert_ram, insert_ras): New functions.
-	(powerpc_opcodes): Use RAL for load with update, RAM for lmw, and
-	RAS for store with update.
-
-Sat Apr 16 23:41:44 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_opcodes): Correct fcir.  From David Edelsohn
-	(edelsohn@npac.syr.edu).
-
-Wed Apr  6 17:11:45 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c (mips_opcodes): Correct operands of "nor" with an
-	immediate argument.
-
-Mon Apr  4 16:30:46 1994  Doug Evans  (dje@canuck.cygnus.com)
-
-	* sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0".
-
-Mon Apr  4 13:22:00 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_operands): The signedp field has been
-	removed, so don't initialize it.  Set the PPC_OPERAND_SIGNED flag
-	instead.  Add new operand SISIGNOPT.
-	(powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT.
-	Based on patch from David Edelsohn (edelsohn@npac.syr.edu).
-	* ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather
-	than signedp field.
-
-Wed Mar 30 00:31:49 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* i386-dis.c (struct private):  Renamed to dis_private. `private'
-	is a reserved word for dynix cc.
-
-Mon Mar 28 13:00:15 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* configure.in: Change error message to refer to bfd/config.bfd
-	rather than bfd/configure.in.
-
-Mon Mar 28 12:28:30 1994  David Edelsohn  (edelsohn@npac.syr.edu)
-
-	* ppc-opc.c: Define POWER2 as short alias flag.
-	(powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and
-	fsqrt.
-
-Wed Mar 23 12:23:05 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* i960-dis.c (print_insn_i960): Don't read a second word for
-	opcodes 0, 1, 2 and 3.
-
-Wed Mar 16 15:37:58 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* configure.in: Don't build m68881-ext.o for bfd_m68k_arch.
-
-Mon Mar 14 14:53:50 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* m68881-ext.c: Removed; no longer used.
-	* Makefile.in: Changed accordingly.
-
-	* m68k-dis.c (ext_format_68881): Don't declare.
-	(print_insn_m68k): If an instruction uses place 'i', it uses at
-	least four fixed bytes.
-	(print_insn_arg): Don't bump p by 2 for case 'I', place 'i'.  For
-	extended float, convert to double using floatformat_to_double, not
-	ieee_extended_to_double, and fetch the data before converting it.
-
-Tue Mar  8 18:12:25 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: It's sqrt.s, not sqrt.w.  From
-	davidj@ICSI.Berkeley.EDU (David Johnson).
-
-Tue Feb  8 16:55:27 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the
-	PowerPC uses bdnz[l][a].
-
-Tue Feb  8 00:32:28 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* dis-buf.c, i386-dis.c:  Include sysdep.h.
-
-Mon Feb  7 19:22:23 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o.
-
-	* ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported
-	by Motorola PowerPC 601 with PPC_OPCODE_601.
-	* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc):
-	Disassemble Motorola PowerPC 601 instructions as well as normal
-	PowerPC instructions.
-
-Sun Feb  6 07:45:17 1994  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* i960-dis.c (reg, mem): Just use a static array instead of
-	calling xmalloc.
-
-Sat Feb  5 00:04:02 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
-
-	* hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the
-	condition name index if this is for a negated condition.
-
-	* hppa-dis.c (print_insn_hppa): No space before 'H' operand.
-	Floating point format for 'H' operand is backwards from normal
-	case (0 == double, 1 == single).  For '4', '6', '7', '9', and '8'
-	operands (fmpyadd and fmpysub), handle bizarre register
-	translation correctly for single precision format.
-
-	* hppa-dis.c (print_insn_hppa): Do not emit a space after 'F'
-	or 'I' operands if the next format specifier is 'M' (fcmp
-	condition completer).
-
-Feb  4 23:38:03 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c (powerpc_operands): New operand type MBE to handle a
-	single number giving a bitmask for the MB and ME fields of an M
-	form instruction.  Change NB to accept 32, and turn it into 0;
-	also turn 0 into 32 when disassembling.  Seperated SH from NB.
-	(insert_mbe, extract_mbe): New functions.
-	(insert_nb, extract_nb): New functions.
-	(SC_MASK): Mask out SA and LK bits.
-	(powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT,
-	RA, SI.  Change "liu" and "cau" to use UI rather than SI.  Mark
-	"bctr" and "bctrl" as accepted by POWER.  Change "rlwimi",
-	"rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.",
-	"rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to
-	use MBE rather than MB.  Add "mfmq" and "mtmq" POWER instructions.
-	(powerpc_macros): Define table of macro definitions.
-	(powerpc_num_macros): Define.
-
-	* ppc-dis.c (print_insn_powerpc): Don't skip optional operands
-	if PPC_OPERAND_NEXT is set.
-
-Sat Jan 22 23:10:07 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of
-	char.  Retrieve contents using bfd_getl32 instead of shifting.
-
-Fri Jan 21 19:01:39 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* ppc-opc.c: New file.  Opcode table for PowerPC, including
-	opcodes for POWER (RS/6000).
-	* ppc-dis.c: New file.  PowerPC and Power (RS/6000) disassembler.
-	* Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o.
-	(CFILES): Add ppc-dis.c.
-	(ppc-dis.o, ppc-opc.o): New targets.
-	* configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch.
-
-Mon Jan 17 20:05:49 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
-
-	* hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template.
-	No space before 'u', 'f', or 'N'.
-
-Sun Jan 16 14:20:16 1994  Jim Kingdon  (kingdon@deneb.cygnus.com)
-
-	* i386-dis.c (print_insn_i386): Add FIXME comment regarding reading
-	farther than we should.
-
-	* i386-dis.c (dis386): Use Yb and Yv for scasb and scasS.
-
-Thu Jan  6 12:38:05 1994  David J. Mackenzie  (djm@thepub.cygnus.com)
-
-	* sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments.
-
-Wed Jan  5 11:56:21 1994  David J. Mackenzie  (djm@thepub.cygnus.com)
-
-	* i960-dis.c (print_insn_i960): Only read word2 if the instruction
-	needs it, to prevent reading past the end of a section.
-
-Wed Nov 17 17:20:12 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.h: Use macro for j instruction, to support SVR4 PIC.
-	Removed t,A case for la; always use t,A(b) case.
-
-Mon Nov  8 12:37:36 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	From Ted Lemen <mellon@pepper.ncd.com>
-	* mips-dis.c (print_insn_arg): Handle 'k'.
-	* mips-opc.c: Make cache use k, not t.
-
-Sun Nov  7 23:52:34 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* alpha-opc.h, alpha-dis.c (print_insn_alpha):  Add
-	FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
-	FLOAT_FORMAT_CODE to put out floating point register names.
-
-Mon Nov  1 18:17:51 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Use macros for jal variants, to support SVR4 PIC.
-
-Thu Oct 28 17:42:23 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x.
-
-Wed Oct 27 11:48:01 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts
-	larger than 32.  Moved dsxx32 variants first for disassembler.
-
-Mon Oct 25 11:33:14 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
-
-	* z8kgen.c, z8k-opc.h: Add full lda information.
-
-Tue Oct 19 12:39:25 1993  Jeffrey A Law  (law@cs.utah.edu)
-
-	* hppa-dis.c (print_insn_hppa): Do not emit a space after
-	movb instructions.  Any necessary space will be emitted by
-	the code to handle nullification completers.
-
-Wed Oct 13 16:19:07 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Moved l.d down so that it disassembles as ldc1.
-
-Fri Oct  8 02:34:21 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* alpha-opc.h:  Add ldl_l, fix typo for ldq_u.
-	* alpha-dis.c (print_insn_alpha):  Add code for PAL_FORMAT_CODE.
-
-Tue Oct  5 17:47:53 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Correct lwu opcode value (book had it wrong).
-
-Thu Sep 30 11:26:18 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
-
-	* z8k-dis.c (FETCH_DATA): get just the right amount of data.
-	(unpack_instr): Cope with ARG_IMM4M1 type instructions.
-
-Wed Sep 29 16:24:49 1993  K. Richard Pixley  (rich@sendai.cygnus.com)
-
-	* m88k-dis.c (m88kdis): comment change.  Remove space after
-	  printing mnemonic.
-	  (printop): handle new arg types DEC and XREG for m88110.
-
-Tue Sep 28 19:20:16 1993  Jeffrey A Law (law@snake.cs.utah.edu)
-
-	* hppa-dis.c (print_insn_hppa): Handle 'z' operand
-	type for absolute branch addresses.  Delete special
-	"ble" and "be" code in 'W' operand code.
-
-Fri Sep 24 14:08:33 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Set hazard information correctly for branch
-	likely instructions.
-
-Fri Sep 17 04:41:17 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* alpha-dis.c (print_insn_alpha), alpha-opc.h:  Fix bugs, use
-	info->fprintf_func for printing and info->print_address_func for
-	address output.
-
-Wed Sep 15 12:12:07 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Set INSN_TRAP for tXX instructions.
-
-Thu Sep  9 10:11:27 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson):
-	Corrected second case of "b" for disassembler.
-
-Tue Sep  7 14:25:15 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-dis.c, m88k-dis.c: Don't include libbfd.h.  Changed calls
-	to BFD swapping routines to correspond to BFD name changes.
-
-Thu Sep  2 10:35:25 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Change div machine instruction to be z,s,t rather
-	than s,t.  Change div macro to be d,v,t rather than d,s,t.
-	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
-	rem and remu which generates only the corresponding div
-	instruction.  This is for compatibility with the MIPS assembler,
-	which only generates the simple machine instruction when an
-	explicit destination of $0 is used.
-	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
-
-Thu Aug 26 17:41:44 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set
-	WR_31 hazard for bal, bgezal, bltzal.
-
-Thu Aug 26 17:20:02 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* hppa-dis.c (print_insn_hppa): Use print function
-	from within the disassemble_info, not fprintf_filtered.
-
-Wed Aug 25 13:51:40 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
-
-	* hppa-dis.c (print_insn_hppa): Handle '|' like '>'.  (From Jeff
-	Law, law@cs.utah.edu.)
-
-Mon Aug 23 12:44:05 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c ("absu"): Removed.
-	("dabs"): Added.
-
-Fri Aug 20 10:52:52 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Added r6000 and r4000 instructions and macros.
-	Changed hazard information to distinguish between memory load
-	delays and coprocessor load delays.
-
-Wed Aug 18 15:39:23 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: li.d uses "T,L", not "S,F".  Added li.s.
-
-Tue Aug 17 09:44:42 1993  David J. Mackenzie  (djm@thepub.cygnus.com)
-
-	* configure.in: Don't pass cpu to config.bfd.
-
-Tue Aug 17 12:23:52 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* m88k-dis.c (m88kdis): Make class unsigned.
-
-Thu Aug 12 15:08:18 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* alpha-dis.c (print_insn_alpha): One branch format case was
-	missing the instruction name.
-
-Wed Aug 11 19:29:39 1993  David J. Mackenzie  (djm@thepub.cygnus.com)
-
-	* Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS.
-	Add the arch-specific auxiliary files.
-	(OFILES): Remove the arch-specific auxiliary files
-	and use BFD_MACHINES instead of DIS_LIBS.
-	* configure.in: Set BFD_MACHINES based on --with-targets option.
-
-Thu Aug 12 12:04:53 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b).  Similarly
-	for swc1.
-
-Sun Aug  8 15:09:30 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* sparc-opc.c: Change CONST to const to deal with gcc
-	-Dconst=__const -traditional.
-
-Fri Aug  6 10:58:55 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took
-	coprocessor instructions out of #if 0, and made them use new
-	argument type "C".
-
-Thu Aug  5 17:11:06 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* sparc-dis.c: Include ansidecl.h before opcodes/sparc.h.
-
-Fri Jul 30 18:48:15 1993  John Gilmore  (gnu@cygnus.com)
-
-	* sparc-opc.c:  Add F_JSR, F_UNBR, or F_CONDBR flags to each branch
-	instruction, for use by the disassembler.
-
-	* sparc-dis.c (SEX):  Add sign extension macro.  Replace many
-	hand-coded sign extensions that depended on 32-bit host ints.
-	FIXME, we still depend on big-endian host bitfield ordering.
-	(sparc_print_insn):  Set the insn_info_valid field, and the
-	other fields that describe the instruction being printed.
-
-Tue Jul 27 17:04:58 1993  Jim Wilson  (wilson@sphagnum.cygnus.com)
-
-	* sparc-opc.c (call): Accept all 6 addressing modes valid for
-	`jmp' instead of just one of them.
-
-Wed Jul 21 11:43:32 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
-
-	* hppa-dis.c: Move floating registers from reg_names to fp_reg_names.
-	(fput_fp_reg_r): Renamed from fput_reg_r.
-	(fput_fp_reg): New function.
-	(print_insn_hppa): Use fput_fp_reg{,_r} where appropriate.
-
-	* hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards.
-
-	* hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD.
-
-Mon Jul 19 13:52:21 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
-
-	* hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'.
-
-	* hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n',
-	don't output a space.
-
-	* hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad.
-
-Sun Jul 18 16:30:02 1993  Jim Kingdon  (kingdon@rtl.cygnus.com)
-
-	* mips-opc.c: New file, containing opcode table from
-	../include/opcode/mips.h.
-	* Makefile.in: Add it.
-
-Thu Jul 15 12:37:05 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* m88k-dis.c: New file, moved in from gdb and changed to use the
-	new dis-asm.h disassembler interface.
-	* Makefile.in (DIS_LIBS): Added m88k-dis.o.
-	(m88k-dis.o): New target.
-
-Tue Jul 13 10:04:16 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to
-	argument string const char * to correspond to opcode/mips.h.
-
-Tue Jul  6 15:18:37 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* mips-dis.c: Updated to account for name changes in new version
-	of opcode/mips.h.
-	* Makefile.in: Added header file dependencies.
-
-Sat Jul  3 23:47:56 1993  Doug Evans  (dje@canuck.cygnus.com)
-
-	* h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction.
-
-Thu Jul  1 12:23:38 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign
-	extend, rather than shifts.
-
-Sun Jun 20 20:56:56 1993  Ken Raeburn  (raeburn@poseidon.cygnus.com)
-
-	* Makefile.in: Undo 15 June change.
-
-Fri Jun 18 14:15:15 1993  Per Bothner  (bothner@deneb.cygnus.com)
-
-	* m68k-dis.c (print_insn_arg):  Change return value to byte count
-	or error code.
-	* m68k-dis.c:  Re-write to detect invalid operands before
-	printing anything, so we can handle this the same way we
-	handle invalid opcodes.
-
-Thu Jun 17 15:01:36 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
-
-	* sh-dis.c, sh-opc.h: Understand some more opcodes.
-
-Wed Jun 16 13:48:05 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* hppa-dis.c: Include <ansidecl.h> and sysdep.h before other
-	header files.
-
-Tue Jun 15 21:45:26 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
-
-	* sparc-dis.c: Don't declare qsort, since sysdep.h might.
-
-	* configure.in: Do make sysdep.h link.
-	* Makefile.in: Search ../include.  Don't search ../bfd.
-
-Tue Jun 15 13:36:10 1993  Stu Grossman  (grossman@cygnus.com)
-
-	Changes from Jeff Law, law@cs.utah.edu:
-	* hppa-dis.c: Fix typo.  'a' and 'd' were reversed.
-	Do not print a space before the completers specified by
-	'a' and 'd'.
-
-Fri Jun 11 18:40:21 1993  Ken Raeburn  (raeburn@cygnus.com)
-
-	* mips-dis.c: No longer need to bomb out if HOST_64_BIT is
-	defined, since gdb has been fixed.
-
-	Changes from Jeff Law, law@cs.utah.edu:
-	* hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
-	fput_reg_r, fput_creg, fput_const, and fputs_filtered should
-	be a *disassemble_info, not a *FILE.
-	* hppa-dis.c: Support 'd', '!', and 'a'.
-	* hppa-dis.c: Support 's' to extract a 2 bit space register.
-	* hppa-dis.c: Delete cases which are no longer needed.
-
-Fri Jun 11 07:53:48 1993  Jim Kingdon  (kingdon@cygnus.com)
-
-	* m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes.
-
-Tue Jun  8 12:25:01 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
-
-	* h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with
-	H8/300-H opcodes.
-
-Mon Jun  7 12:58:49 1993  Per Bothner  (bothner@rtl.cygnus.com)
-
-	* Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h.
-	* configure.in:  No longer need to configure to get sysdep.h.
-
-Thu Jun  3 15:56:49 1993  Stu Grossman  (grossman@cygnus.com)
-
-	* Patches from Jeffrey Law <law@cs.utah.edu>.
-	* hppa-dis.c: Support 'I', 'J', and 'K' in output
-	templates for 1.1 FP computational instructions.
-
-Tue May 25 13:05:48 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
-
-	* h8500-dis.c (print_insn_h8500): Address argument is type
-	bfd_vma.
-	* z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002):
-	Ditto.
-
-	* h8500-opc.h (addr_class_type): No comma at end of enumerator.
-	* sh-opc.h (sh_nibble_type, sh_arg_type): Ditto.
-
-	* sparc-dis.c (compare_opcodes): Move static declaration to
-	top-level.
-
-Fri May 21 14:17:37 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp
-	instruction, remove unimp hack from 'l' argument.
-
-Wed May 19 15:35:54 1993  Stu Grossman  (grossman@cygnus.com)
-
-	* z8k-dis.c (fetch_data):  Use unsigned char to make ancient gcc's
-	happy.
-
-Fri May 14 15:22:46 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson):
-	* mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor
-	instructions.
-
-Fri May 14 00:09:14 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
-
-	* hppa-dis.c: Include dis-asm.h before sysdep.h.  Changed some
-	arrays of string pointers to 2-d arrays of chars, to save
-	space.
-
-Thu May  6 20:51:17 1993  Fred Fish  (fnf@cygnus.com)
-
-	* a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c:
-	Cast second arg to read_memory_func to "bfd_byte *", as necessary.
-
-Tue May  4 20:31:10 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
-
-	* hppa-dis.c: New file from Utah, adapted to new disassembler
-	calling interface.
-	* Makefile.in: Include it.
-
-Mon Apr 26 18:17:42 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
-
-	* sh-dis.c, sh-opc.h: New files.
-
-Fri Apr 23 18:51:22 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
-
-	* alpha-dis.c, alpha-opc.h: New files.
-
-Tue Apr  6 12:54:08 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed
-	value.
-
-Mon Apr  5 17:37:37 1993  John Gilmore  (gnu@cygnus.com)
-
-	* sparc-dis.c: Make "ta" the default trap instruction, "t" the alias.
-
-Fri Apr  2 07:24:27 1993  Ian Lance Taylor  (ian@cygnus.com)
-
-	* a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than
-	const.
-
-Thu Apr  1 11:20:43 1993  Jim Kingdon  (kingdon@cygnus.com)
-
-	* sparc-dis.c: Use fprintf_func a few places where I forgot,
-	and double percent signs a few places.
-
-	* a29k-dis.c, i960-dis.c: New, merged from gdb and binutils.
-
-	* i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c:
-	Use info->print_address_func not print_address.
-
-	* dis-buf.c (generic_print_address): New function.
-
-Wed Mar 31 10:07:04 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* Makefile.in: Add sparc-dis.c.
-	sparc-dis.c: New file, merges binutils and gdb versions as follows:
-	From GDB:
-	    Add `add' instruction to the set that get checked
-	    for a preceding `sethi' in order to print an absolute address.
-	    * (print_insn):  Disassembly prefers real instructions.
-	    (is_delayed_branch):  Speed up.
-	    * sparc-opcode.h: Add ALIAS bit to aliases.  Fix up opcode tables.
-	    Still missing some float ops, and needs testing.
-	    * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by
-	    F_ALIAS.  Use printf, not fprintf, when not passing a file
-	    pointer...
-	    (compare_opcodes): Check that identical instructions have
-	    identical opcodes, complain otherwise.
-	From binutils:
-	    * New 'm' arg.
-	    * Include reg_names.
-	From neither:
-	    Use dis-asm.h/read_memory_func interface.
-
-Wed Mar 31 20:49:06 1993  K. Richard Pixley  (rich@rtl.cygnus.com)
-
-	* h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data):
-	  deliberately return non-zero to setjmp from longjmp.  Otherwise
-	  this code fails to compile.
-
-Wed Mar 31 17:04:31 1993  Stu Grossman  (grossman@cygnus.com)
-
-	* m68k-dis.c:  Fix prototype for fetch_arg().
-
-Wed Mar 31 10:07:04 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* dis-buf.c: New file, for new read_memory_func interface.
-	Makefile.in (OFILES): Include it.
-	m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c:
-	Use new read_memory_func interface.
-
-Mon Mar 29 14:02:17 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
-
-	* h8500-dis.c (print_insn_h8500): Get sign of fp offsets right.
-	* h8500-opc.h: Fix couple of opcodes.
-
-Wed Mar 24 02:03:36 1993  david d `zoo' zuhn  (zoo at poseidon.cygnus.com)
-
-	* Makefile.in: add dvi & installcheck targets
-
-Mon Mar 22 18:55:04 1993  John Gilmore  (gnu@cygnus.com)
-
-	* Makefile.in:  Update for h8500-dis.c.
-
-Fri Mar 19 14:27:17 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+	* configure: Regenerate.
 
-	* h8500-dis.c, h8500-opc.h: New files
+2000-03-06  J"oern Rennecke <amylaar@redhat.com>
 
-Thu Mar 18 14:12:37 1993  Per Bothner  (bothner@rtl.cygnus.com)
+	* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.
 
-	* mips-dis.c, z8k-dis.c:  Converted to use interface defined in
-	../include/dis-asm.h.
-	* m68k-dis.c:  New file (merge of ../binutils/m68k-pinsn.c
-	and ../gdb/m68k-pinsn.c).
-	* i386-dis.c:  New file (merge of ../binutils/i386-pinsn.c
-	and ../gdb/i386-pinsn.c).
-	* m68881-ext.c:  New file.  Moved definition of
-	ext_format ext_format_68881 from ../gdb/m68k-tdep.c.
-	* Makefile.in:  Adjust for new files.
-	* i386-dis.c:  Patches from John Hassey (hassey@dg-rtp.dg.com).
-	* m68k-dis.c:  Recognize '9' placement code, so (say) pflush
-	can be dis-assembled.
+2000-03-02  J"orn Rennecke <amylaar@redhat.co.uk>
+
+	* d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
+	flag to determine if operand is pc-relative.
+	* d30v-opc.c:
+	(d30v_format_table):
+	(REL6S3): Renamed from IMM6S3.
+	Added flag OPERAND_PCREL.
+	(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
+	added flag OPERAND_PCREL.
+	(IMM12S3U): Replaced with REL12S3.
+	(SHORT_D2, LONG_D): Delay target is pc-relative.
+	(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
+	Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
+	using the REL* operands.
+	(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
+	(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
+	LONG_Db, using REL* operands.
+	(SHORT_U, SHORT_A5S): Removed stray alternatives.
+	(d30v_opcode_table): Use new *r formats.
+
+2000-02-28  Nick Clifton  <nickc@redhat.com>
 
-Wed Feb 17 09:19:47 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+	* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
+	'signed_overflow_ok_p'.
 
-	* mips-dis.c (print_insn_arg): Now returns void.
+2000-02-27  Eli Zaretskii  <eliz@is.elta.co.il>
 
-Mon Jan 11 16:09:16 1993  Fred Fish  (fnf@cygnus.com)
+	* Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
+	name of the libtool directory.
+	* Makefile.in: Rebuild.
 
-	* mips-dis.c (ansidecl.h):  Include for benefit of sysdep.h
-	files that use the macros.
+2000-02-24  Nick Clifton  <nickc@redhat.com>
 
-Thu Jan  7 13:15:17 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+	* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
+	(cgen_clear_signed_overflow_ok): New function.
+	(cgen_signed_overflow_ok_p): New function.
 
-	* mips-dis.c: New file, from gdb/mips-pinsn.c.
-	* Makefile.in (DIS_LIBS): Added mips-dis.o.
-	(CFILES): Added mips-dis.c.
+2000-02-23  Andrew Haley  <aph@redhat.com>
 
-Thu Jan  7 07:36:33 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+	* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
+	m32r-ibld.c, m32r-opc.h: Rebuild.
 
-    	* z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines
-	* z8kgen.c, z8k-opc.h: fix sizes of some shifts.
+2000-02-23  Linas Vepstas <linas@linas.org>
 
-Tue Dec 22 15:42:44 1992  Per Bothner  (bothner@rtl.cygnus.com)
+	* i370-dis.c, i370-opc.c: New.
 
-	* Makefile.in:  Improve *clean rules.
-	* configure.in:  Allow a default host.
+	* disassemble.c (ARCH_i370): Define.
+	(disassembler): Handle it.
 
-Tue Nov 17 19:53:54 1992  david d `zoo' zuhn  (zoo at cirdan.cygnus.com)
+	* Makefile.am: Add support for Linux/IBM 370.
+	* configure.in: Likewise.
 
-	* Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep
-	files include other sysdep files
+	* Makefile.in: Regenerate.
+	* configure: Likewise.
 
-Thu Nov 12 16:10:37 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+2000-02-22  Chandra Chavva   <cchavva@redhat.com>
 
-	* z8k-dis.c z8k-opc.h z8kgen.c: checkpoint
+	* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
+	ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
+	procedure.
 
-Fri Oct  9 04:56:05 1992  John Gilmore  (gnu@cygnus.com)
+2000-02-22  Andrew Haley  <aph@redhat.com>
 
-	* configure.in:  For host support, use ../bfd/configure.host
-	so it stays in sync with the ../bfd/hosts database.
+	* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
+	force gp32 to zero.
+	* mips-opc.c (G6): New define.
+	(mips_builtin_op): Add "move" definition for -gp32.
 
-Thu Oct  1 23:38:54 1992  david d `zoo' zuhn  (zoo at cirdan.cygnus.com)
+2000-02-22  Ian Lance Taylor  <ian@zembu.com>
 
-	* configure.in: use cpu-vendor-os triple instead of nested cases
+	From Grant Erickson <gerickso@Brocade.COM>:
+	* ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.
 
-Wed Sep 30 16:09:20 1992  Michael Werner  (mtw@cygnus.com)
+2000-02-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
-	* z8k-dis.c (unparse_instr): fix bug where opcode returned was
-	*always* the wrong one.
+	* dis-buf.c (buffer_read_memory): Change `length' param and all int
+	vars to unsigned.
 
-Wed Sep 30 07:42:17 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk>
 
-	* z8kgen.c: added copyright info
+	* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
+	(print_insn_ppi): Likewise.
+	(print_insn_shx): Use info->mach to select appropriate insn set.
+	Add support for sh-dsp.  Remove FD_REG_N support.
+	* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
+	(sh_arg_type): Likewise.  Remove FD_REG_N.
+	(sh_dsp_reg_nums): New enum.
+	(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
+	(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
+	(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
+	(arch_sh3_dsp_up): Likewise.
+	(sh_opcode_info): New field: arch.
+	(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
+	D_REG_N.  Fill in arch field.  Add sh-dsp insns.
 
-Tue Sep 29 12:20:21 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+2000-02-14  Fernando Nasser  <fnasser@totem.to.redhat.com>
 
-	* z8k-dis.c (unparse_instr): prettier tabs
-	* z8kgen.c -> z8k-opc.h: bug fixes in tables
+	* arm-dis.c: Change flavor name from atpcs-special to
+	special-atpcs to prevent name conflict in gdb.
+	(get_arm_regname_num_options, set_arm_regname_option,
+	get_arm_regnames): New functions.  API to access the several
+	flavor of register names.  Note: Used by gdb.
+	(print_insn_thumb): Use the register name entry from the currently
+	selected flavor for LR and PC.
 
-Fri Sep 25 12:50:32 1992  Stu Grossman  (grossman at cygnus.com)
+2000-02-10  Nick Clifton  <nickc@redhat.com>
 
-	* configure.in:  Add ncr* configuration.
-	* z8k-dis.c (struct instr_data_s):  Make instr_asmsrc char to make
-	picayune ANSI compilers happy.
+	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
+	classes.
+	(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
+	"mulsh.h" instructions.
+	* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
+	classes.
+	(print_insn_mcore): Add support for little endian targets.
+	Add support for MULSH and OPSR classes.
 
-Sep 20 08:50:55 1992  Fred Fish  (fnf@cygnus.com)
+2000-02-07  Nick Clifton  <nickc@redhat.com>
 
-	* configure.in (i386):  Make i386 and i486 synonymous for now.
-	* configure.in (i[34]86-*-sysv4):  Add my_host definition.
+	* arm-dis.c (parse_arm_diassembler_option): Rename again.
+	Previous delat did not take.
 
-Fri Sep 18 17:01:23 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+2000-02-03  Timothy Wall  <twall@redhat.com>
 
-	* Makefile.in (install): Fix typo.
+	* dis-buf.c (buffer_read_memory):  Use octets_per_byte field
+	to adjust target address bounds checking and calculate the
+	appropriate octet offset into data.
 
-Fri Sep 18 02:04:24 1992  John Gilmore  (gnu@cygnus.com)
+2000-01-27  Nick Clifton  <nickc@redhat.com>
 
-	* Makefile.in (make):  Remove obsolete crud.
-	(sparc-opc.o):  Avoid Sun Make VPATH bug.
+	* arm-dis.c: (parse_disassembler_option): Rename to
+	parse_arm_disassembler_option and allow to be exported.
 
-Tue Sep  8 17:29:27 1992  K. Richard Pixley  (rich@sendai.cygnus.com)
+	* disassemble.c (disassembler_usage): New function: Print out any
+	target specific disassembler options.
+	Call arm_disassembler_options() if the ARM architecture is being
+	supported.
 
-	* Makefile.in: since there are no SUBDIRS, remove rule and
-	references of subdir_do.
+	* arm-dis.c (NUM_ELEM): Define this macro if not already
+	defined.
+	(arm_regname): New struct type for ARM register names.
+	(arm_toggle_regnames): Delete.
+	(parse_disassembler_option): Use register name structure.
+	(print_insn): New function: Combines duplicate code found in
+	print_insn_big_arm and print_insn_little_arm.
+	(print_insn_big_arm): Call print_insn.
+	(print_insn_little_arm): Call print_insn.
+	(print_arm_disassembler_options): Display list of supported,
+	ARM specific disassembler options.
 
-Tue Sep  8 17:02:58 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+2000-01-27  Thomas de Lellis  <tdel@windriver.com>
 
-	* Makefile.in (install): Get the library name right here too.
-	Don't install bfd.h, since it's unrelated to this library.  No
-	subdirs to recurse into, either.
-	(CFILES): The source file has a .c suffix, not .o.
+	* arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
+	ARM_STT_16BIT flag as Thumb code symbols.
 
-	* sparc-opc.c: New file, moved from BFD.
-	* Makefile.in (OFILES): Build it.
+	* arm-dis.c (printf_insn_little_arm): Ditto.
 
-Thu Sep  3 16:59:20 1992  Michael Werner  (mtw@cygnus.com)
+2000-01-25  Thomas de Lellis  <tdel@windriver.com>
 
-	* z8k-dis.c: fixed forward refferences of some declarations.
+	* arm-dis.c (printf_insn_thumb): Prevent double dumping
+	of raw thumb instructions.
 
-Mon Aug 31 16:09:45 1992  Michael Werner  (mtw@cygnus.com)
+2000-01-20  Nick Clifton  <nickc@redhat.com>
 
-	* Makefile.in: get the name of the library right
+	* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".
 
-Mon Aug 31 13:47:35 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+2000-01-03  Nick Clifton  <nickc@cygnus.com>
 
-	* z8k-dis.c: knows how to disassemble z8k stuff
-	* z8k-opc.h: new file full of z8000 opcodes
+	* arm-dis.c (streq): New macro.
+	(strneq): New macro.
+	(force_thumb): ew local variable.
+	(parse_disassembler_option): New function: Parse a single, ARM
+	specific disassembler command line switch.
+	(parse_disassembler_option): Call parse_disassembler_option to
+	parse individual command line switches.
+	(print_insn_big_arm): Check force_thumb.
+	(print_insn_little_arm): Check force_thumb.
 
+For older changes see ChangeLog-9899
 
 Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
 version-control: never
 End:
diff --git a/gnu/usr.bin/binutils/opcodes/Makefile.in b/gnu/usr.bin/binutils/opcodes/Makefile.in
index 1d78dfb2d16..e8f4fe1a239 100644
--- a/gnu/usr.bin/binutils/opcodes/Makefile.in
+++ b/gnu/usr.bin/binutils/opcodes/Makefile.in
@@ -70,10 +70,14 @@ CATALOGS = @CATALOGS@
 CATOBJEXT = @CATOBJEXT@
 CC = @CC@
 CC_FOR_BUILD = @CC_FOR_BUILD@
+CXX = @CXX@
+CXXCPP = @CXXCPP@
 DATADIRNAME = @DATADIRNAME@
 DLLTOOL = @DLLTOOL@
 EXEEXT = @EXEEXT@
 EXEEXT_FOR_BUILD = @EXEEXT_FOR_BUILD@
+GCJ = @GCJ@
+GCJFLAGS = @GCJFLAGS@
 GMOFILES = @GMOFILES@
 GMSGFMT = @GMSGFMT@
 GT_NO = @GT_NO@
@@ -91,16 +95,19 @@ MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
 OBJDUMP = @OBJDUMP@
+OBJEXT = @OBJEXT@
 PACKAGE = @PACKAGE@
 POFILES = @POFILES@
 POSUB = @POSUB@
 RANLIB = @RANLIB@
+STRIP = @STRIP@
 USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
 USE_NLS = @USE_NLS@
 VERSION = @VERSION@
 WIN32LDFLAGS = @WIN32LDFLAGS@
 WIN32LIBADD = @WIN32LIBADD@
 archdefs = @archdefs@
+cgendir = @cgendir@
 l = @l@
 
 AUTOMAKE_OPTIONS = cygnus
@@ -111,11 +118,17 @@ INCDIR = $(srcdir)/../include
 BFDDIR = $(srcdir)/../bfd
 MKDEP = gcc -MM
 
+WARN_CFLAGS = @WARN_CFLAGS@
+AM_CFLAGS = $(WARN_CFLAGS)
+
 lib_LTLIBRARIES = libopcodes.la
 
 # This is where bfd.h lives.
 BFD_H = ../bfd/bfd.h
 
+# This is where libiberty lives.
+LIBIBERTY = ../libiberty/libiberty.a
+
 # Header files.
 HFILES = \
 	arm-opc.h \
@@ -125,6 +138,8 @@ HFILES = \
 	mcore-opc.h \
 	sh-opc.h \
 	sysdep.h \
+	ia64-asmtab.h \
+	ia64-opc.h \
 	w65-opc.h \
 	z8k-opc.h
 
@@ -136,11 +151,14 @@ CFILES = \
 	alpha-opc.c \
 	arc-dis.c \
 	arc-opc.c \
+	arc-ext.c \
 	arm-dis.c \
 	avr-dis.c \
 	cgen-asm.c \
 	cgen-dis.c \
 	cgen-opc.c \
+	cris-dis.c \
+	cris-opc.c \
 	d10v-dis.c \
 	d10v-opc.c \
 	d30v-dis.c \
@@ -158,13 +176,26 @@ CFILES = \
 	i370-dis.c \
 	i370-opc.c \
 	i386-dis.c \
+	i860-dis.c \
 	i960-dis.c \
+	ia64-dis.c \
+	ia64-opc-a.c \
+	ia64-opc-b.c \
+	ia64-opc-f.c \
+	ia64-opc-i.c \
+	ia64-opc-m.c \
+	ia64-opc-d.c \
+	ia64-opc.c \
+	ia64-gen.c \
+	ia64-asmtab.c \
 	m32r-asm.c \
 	m32r-desc.c \
 	m32r-dis.c \
 	m32r-ibld.c \
 	m32r-opc.c \
 	m32r-opinst.c \
+	m68hc11-dis.c \
+	m68hc11-opc.c \
 	m68k-dis.c \
 	m68k-opc.c \
 	m88k-dis.c \
@@ -185,6 +216,8 @@ CFILES = \
 	sparc-dis.c \
 	sparc-opc.c \
 	tic30-dis.c \
+	tic54x-dis.c \
+	tic54x-opc.c \
 	tic80-dis.c \
 	tic80-opc.c \
 	v850-dis.c \
@@ -201,11 +234,14 @@ ALL_MACHINES = \
 	alpha-opc.lo \
 	arc-dis.lo \
 	arc-opc.lo \
+	arc-ext.lo \
 	arm-dis.lo \
 	avr-dis.lo \
 	cgen-asm.lo \
 	cgen-dis.lo \
 	cgen-opc.lo \
+	cris-dis.lo \
+	cris-opc.lo \
 	d10v-dis.lo \
 	d10v-opc.lo \
 	d30v-dis.lo \
@@ -221,13 +257,18 @@ ALL_MACHINES = \
 	i386-dis.lo \
 	i370-dis.lo \
 	i370-opc.lo \
+	i860-dis.lo \
 	i960-dis.lo \
+	ia64-dis.lo \
+	ia64-opc.lo \
 	m32r-asm.lo \
 	m32r-desc.lo \
 	m32r-dis.lo \
 	m32r-ibld.lo \
 	m32r-opc.lo \
 	m32r-opinst.lo \
+	m68hc11-dis.lo \
+	m68hc11-opc.lo \
 	m68k-dis.lo \
 	m68k-opc.lo \
 	m88k-dis.lo \
@@ -239,15 +280,17 @@ ALL_MACHINES = \
 	mips-dis.lo \
 	mips-opc.lo \
 	mips16-opc.lo \
+	ns32k-dis.lo \
 	pj-dis.lo \
 	pj-opc.lo \
 	ppc-dis.lo \
 	ppc-opc.lo \
-	ns32k-dis.lo \
 	sh-dis.lo \
 	sparc-dis.lo \
 	sparc-opc.lo \
 	tic30-dis.lo \
+	tic54x-dis.lo \
+	tic54x-opc.lo \
 	tic80-dis.lo \
 	tic80-opc.lo \
 	v850-dis.lo \
@@ -276,8 +319,25 @@ noinst_LIBRARIES = libopcodes.a
 POTFILES = $(HFILES) $(CFILES)
 
 CLEANFILES = \
-	libopcodes.a stamp-lib dep.sed DEP DEP1 DEP2
+	stamp-m32r stamp-fr30 \
+	libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
+
 
+CGENDIR = @cgendir@
+CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi`
+CGENFLAGS = -v
+
+CGENDEPS = ../cgen/stamp-cgen \
+	$(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \
+	$(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \
+	$(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \
+	$(CGENDIR)/opc-opinst.scm \
+	cgen-asm.in cgen-dis.in cgen-ibld.in
+
+@CGEN_MAINT_TRUE@M32R_DEPS = @CGEN_MAINT_TRUE@stamp-m32r
+@CGEN_MAINT_FALSE@M32R_DEPS = 
+@CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30
+@CGEN_MAINT_FALSE@FR30_DEPS = 
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
 CONFIG_HEADER = config.h
@@ -291,7 +351,7 @@ LDFLAGS = @LDFLAGS@
 LIBS = @LIBS@
 libopcodes_a_LIBADD = 
 libopcodes_a_SOURCES = libopcodes.a.c
-libopcodes_a_OBJECTS =  libopcodes.a.o
+libopcodes_a_OBJECTS =  libopcodes.a.$(OBJEXT)
 LTLIBRARIES =  $(lib_LTLIBRARIES)
 
 libopcodes_la_OBJECTS =  dis-buf.lo disassemble.lo
@@ -309,11 +369,11 @@ DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
 TAR = tar
 GZIP_ENV = --best
 SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
-OBJECTS = libopcodes.a.o $(libopcodes_la_OBJECTS)
+OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
 
 all: all-redirect
 .SUFFIXES:
-.SUFFIXES: .S .c .lo .o .s
+.SUFFIXES: .S .c .lo .o .obj .s
 $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) 
 	cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile
 
@@ -366,6 +426,11 @@ maintainer-clean-noinstLIBRARIES:
 .c.o:
 	$(COMPILE) -c $<
 
+# FIXME: We should only use cygpath when building on Windows,
+# and only if it is available.
+.c.obj:
+	$(COMPILE) -c `cygpath -w $<`
+
 .s.o:
 	$(COMPILE) -c $<
 
@@ -374,6 +439,7 @@ maintainer-clean-noinstLIBRARIES:
 
 mostlyclean-compile:
 	-rm -f *.o core *.core
+	-rm -f *.$(OBJEXT)
 
 clean-compile:
 
@@ -682,6 +748,7 @@ stamp-lib: libopcodes.la
 	libtooldir=`$(LIBTOOL) --config | sed -n -e 's/^objdir=//p'`; \
 	if [ -f $$libtooldir/libopcodes.a ]; then \
 	  cp $$libtooldir/libopcodes.a libopcodes.tmp; \
+	  $(RANLIB) libopcodes.tmp; \
 	  $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \
 	else true; fi
 	touch stamp-lib
@@ -696,15 +763,45 @@ po/POTFILES.in: @MAINT@ Makefile
 config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in
 	$(SHELL) ./config.status --recheck
 
-# The start marker is written this way to pass through automake unscathed.
+run-cgen:
+	$(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \
+	  $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \
+	  "$(options)" $(extrafiles)
+	touch stamp-${prefix}
+.PHONY: run-cgen
+
+# For now, require developers to configure with --enable-cgen-maint.
+$(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS)
+	@true
+stamp-m32r: $(CGENDEPS) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc
+	$(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst
+
+$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
+	@true
+stamp-fr30: $(CGENDEPS) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc
+	$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
+
+ia64-gen: ia64-gen.o
+	$(LINK) ia64-gen.o $(LIBIBERTY)
+
+ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
+  ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
+
+ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
+	here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c
 
 # This dependency stuff is copied from BFD.
 
 DEP: dep.sed $(CFILES) $(HFILES) config.h
 	rm -f DEP1
 	$(MAKE) MKDEP="$(MKDEP)" DEP1
-	sed -f dep.sed < DEP1 > $@
-	echo '# IF YOU PUT ANYTHING HERE IT WILL GO AWAY' >> $@
+	sed -f dep.sed < DEP1 > DEPA
+	echo '# IF YOU PUT ANYTHING HERE IT WILL GO AWAY' >> DEPA
+	if grep ' /' DEPA > /dev/null 2> /dev/null; then \
+	  echo 'make DEP failed!'; exit 1; \
+	else \
+	  mv -f DEPA $@; \
+	fi
 
 DEP1: $(CFILES)
 	echo '# DO NOT DELETE THIS LINE -- mkdep uses it.' > DEP2
@@ -740,141 +837,191 @@ dep-am: DEP
 
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
-a29k-dis.lo: a29k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/a29k.h
-alpha-dis.lo: alpha-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h
-alpha-opc.lo: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \
-  $(BFD_H) opintl.h
+a29k-dis.lo: a29k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/a29k.h
+alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h
+alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/alpha.h $(BFD_H) opintl.h
 arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h opintl.h \
+  arc-dis.h arc-ext.h
+arc-opc.lo: arc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h
+arc-ext.lo: arc-ext.c $(BFD_H) $(INCDIR)/ansidecl.h \
+  arc-ext.h $(INCDIR)/libiberty.h
+arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h
+avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) opintl.h $(INCDIR)/opcode/avr.h
+cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \
   opintl.h
-arc-opc.lo: arc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h \
+cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h
+cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h
+cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h sysdep.h config.h $(INCDIR)/opcode/cris.h \
+  $(INCDIR)/libiberty.h
+cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h
+d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H)
+d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/d10v.h
+d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \
   opintl.h
-arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \
-  $(INCDIR)/elf/reloc-macros.h
-avr-dis.lo: avr-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h opintl.h
-cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/libiberty.h \
-  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/libiberty.h \
-  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h
-cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
-  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h
-d10v-dis.lo: d10v-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h \
-  $(INCDIR)/dis-asm.h $(BFD_H)
-d10v-opc.lo: d10v-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h
-d30v-dis.lo: d30v-dis.c $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/ansidecl.h opintl.h
-d30v-opc.lo: d30v-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d30v.h
-dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) opintl.h
-disassemble.lo: disassemble.c $(INCDIR)/ansidecl.h \
+d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/d30v.h
+dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
+disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
-fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h opintl.h
-fr30-desc.lo: fr30-desc.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h opintl.h
-fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
   fr30-opc.h opintl.h
-fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h opintl.h
-fr30-opc.lo: fr30-opc.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h
-h8300-dis.lo: h8300-dis.c $(INCDIR)/opcode/h8300.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h opintl.h
-h8500-dis.lo: h8500-dis.c h8500-opc.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/ansidecl.h opintl.h
-hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-i370-dis.lo: i370-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/i370.h
-i370-opc.lo: i370-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/i370.h
+  fr30-opc.h opintl.h $(INCDIR)/libiberty.h
+fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \
+  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h
+fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \
+  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h
+fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
+  fr30-opc.h $(INCDIR)/libiberty.h
+h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
+  opintl.h
+h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
+hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
+i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/i370.h
+i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/i370.h
 i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
-i960-dis.lo: i960-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h
-m32r-asm.lo: m32r-asm.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  m32r-opc.h opintl.h
-m32r-desc.lo: m32r-desc.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  m32r-opc.h opintl.h
-m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/i860.h
+i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H)
+ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ia64.h
+ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h
+ia64-opc-d.lo: ia64-opc-d.c
+ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+  sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \
+  ia64-asmtab.c
+ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+  sysdep.h config.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \
+  ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
+ia64-asmtab.lo: ia64-asmtab.c
+m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
   m32r-opc.h opintl.h
-m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
+  m32r-opc.h opintl.h $(INCDIR)/libiberty.h
+m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \
+  $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h
+m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \
+  $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h
+m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
+  m32r-opc.h $(INCDIR)/libiberty.h
+m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  m32r-opc.h opintl.h
-m32r-opc.lo: m32r-opc.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  m32r-opc.h
-m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
   m32r-opc.h
-m68k-dis.lo: m68k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h opintl.h \
+m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H)
+m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/m68hc11.h
+m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \
+  opintl.h $(INCDIR)/opcode/m68k.h
+m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68k.h
-m68k-opc.lo: m68k-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68k.h
-m88k-dis.lo: m88k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m88k.h opintl.h
-mcore-dis.lo: mcore-dis.c mcore-opc.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H)
-mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/opcode/mips.h opintl.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
-mips-opc.lo: mips-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
-mips16-opc.lo: mips16-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
-m10200-dis.lo: m10200-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10200.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
-m10200-opc.lo: m10200-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10200.h
-m10300-dis.lo: m10300-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10300.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
-m10300-opc.lo: m10300-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10300.h
+m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/m88k.h \
+  opintl.h
+mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H)
+mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/mips.h \
+  opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
+mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mips.h
+mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mips.h
+m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \
+  opintl.h
+m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mn10200.h
+m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \
+  opintl.h
+m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/mn10300.h
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
   sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
   opintl.h
-pj-dis.lo: pj-dis.c $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/ansidecl.h
-pj-opc.lo: pj-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/pj.h
-ppc-dis.lo: ppc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
-ppc-opc.lo: ppc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ppc.h \
-  opintl.h
-sh-dis.lo: sh-dis.c sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h
-sparc-dis.lo: sparc-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/libiberty.h opintl.h
-sparc-opc.lo: sparc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/sparc.h
-tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/opcode/tic30.h
-tic80-dis.lo: tic80-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/tic80.h \
-  $(INCDIR)/dis-asm.h $(BFD_H)
-tic80-opc.lo: tic80-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/tic80.h
-v850-dis.lo: v850-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/v850.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
-v850-opc.lo: v850-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/v850.h \
+pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
+pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/pj.h
+ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
+ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/ppc.h opintl.h
+sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H)
+sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \
+  $(INCDIR)/libiberty.h opintl.h
+sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/sparc.h
+tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic30.h
+tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic54x.h \
+  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h
+tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/tic54x.h
+tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H)
+tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/tic80.h
+v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \
   opintl.h
-vax-dis.lo: vax-dis.c $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/ansidecl.h
-w65-dis.lo: w65-dis.c w65-opc.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/ansidecl.h
-z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) z8k-opc.h
-z8kgen.lo: z8kgen.c sysdep.h config.h
+v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/v850.h opintl.h
+vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H)
+w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H)
+z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) z8k-opc.h
+z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
 
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
diff --git a/gnu/usr.bin/binutils/opcodes/a29k-dis.c b/gnu/usr.bin/binutils/opcodes/a29k-dis.c
index 7b8b1b775a9..3c861677f9b 100644
--- a/gnu/usr.bin/binutils/opcodes/a29k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/a29k-dis.c
@@ -1,5 +1,6 @@
 /* Instruction printing code for the AMD 29000
-   Copyright (C) 1990, 93, 94, 95, 1998 Free Software Foundation, Inc.
+   Copyright 1990, 1993, 1994, 1995, 1998, 2000
+   Free Software Foundation, Inc.
    Contributed by Cygnus Support.  Written by Jim Kingdon.
 
 This file is part of GDB.
diff --git a/gnu/usr.bin/binutils/opcodes/aclocal.m4 b/gnu/usr.bin/binutils/opcodes/aclocal.m4
index 7ba1f4ecb7b..a3aa924df30 100644
--- a/gnu/usr.bin/binutils/opcodes/aclocal.m4
+++ b/gnu/usr.bin/binutils/opcodes/aclocal.m4
@@ -12,6 +12,22 @@ dnl PARTICULAR PURPOSE.
 
 sinclude(../bfd/acinclude.m4)
 
+dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4
+dnl The lines below arrange for aclocal not to bring libtool.m4
+dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake
+dnl to add a definition of LIBTOOL to Makefile.in.
+ifelse(yes,no,[
+AC_DEFUN([AM_PROG_LIBTOOL],)
+AC_DEFUN([AM_DISABLE_SHARED],)
+AC_SUBST(LIBTOOL)
+])
+
+dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4
+ifelse(yes,no,[
+AC_DEFUN([CY_WITH_NLS],)
+AC_SUBST(INTLLIBS)
+])
+
 # Do all the work for Automake.  This macro actually does too much --
 # some checks are only needed if your package does certain things.
 # But this isn't really a big deal.
@@ -104,415 +120,6 @@ else
 fi
 AC_SUBST($1)])
 
-
-# serial 40 AC_PROG_LIBTOOL
-AC_DEFUN(AC_PROG_LIBTOOL,
-[AC_REQUIRE([AC_LIBTOOL_SETUP])dnl
-
-# Save cache, so that ltconfig can load it
-AC_CACHE_SAVE
-
-# Actually configure libtool.  ac_aux_dir is where install-sh is found.
-CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \
-LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \
-LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" \
-DLLTOOL="$DLLTOOL" AS="$AS" OBJDUMP="$OBJDUMP" \
-${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \
-$libtool_flags --no-verify $ac_aux_dir/ltmain.sh $lt_target \
-|| AC_MSG_ERROR([libtool configure failed])
-
-# Reload cache, that may have been modified by ltconfig
-AC_CACHE_LOAD
-
-# This can be used to rebuild libtool when needed
-LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh"
-
-# Always use our own libtool.
-LIBTOOL='$(SHELL) $(top_builddir)/libtool'
-AC_SUBST(LIBTOOL)dnl
-
-# Redirect the config.log output again, so that the ltconfig log is not
-# clobbered by the next message.
-exec 5>>./config.log
-])
-
-AC_DEFUN(AC_LIBTOOL_SETUP,
-[AC_PREREQ(2.13)dnl
-AC_REQUIRE([AC_ENABLE_SHARED])dnl
-AC_REQUIRE([AC_ENABLE_STATIC])dnl
-AC_REQUIRE([AC_ENABLE_FAST_INSTALL])dnl
-AC_REQUIRE([AC_CANONICAL_HOST])dnl
-AC_REQUIRE([AC_CANONICAL_BUILD])dnl
-AC_REQUIRE([AC_PROG_RANLIB])dnl
-AC_REQUIRE([AC_PROG_CC])dnl
-AC_REQUIRE([AC_PROG_LD])dnl
-AC_REQUIRE([AC_PROG_NM])dnl
-AC_REQUIRE([AC_PROG_LN_S])dnl
-dnl
-
-case "$target" in
-NONE) lt_target="$host" ;;
-*) lt_target="$target" ;;
-esac
-
-# Check for any special flags to pass to ltconfig.
-libtool_flags="--cache-file=$cache_file"
-test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared"
-test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static"
-test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install"
-test "$ac_cv_prog_gcc" = yes && libtool_flags="$libtool_flags --with-gcc"
-test "$ac_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld"
-ifdef([AC_PROVIDE_AC_LIBTOOL_DLOPEN],
-[libtool_flags="$libtool_flags --enable-dlopen"])
-ifdef([AC_PROVIDE_AC_LIBTOOL_WIN32_DLL],
-[libtool_flags="$libtool_flags --enable-win32-dll"])
-AC_ARG_ENABLE(libtool-lock,
-  [  --disable-libtool-lock  avoid locking (might break parallel builds)])
-test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock"
-test x"$silent" = xyes && libtool_flags="$libtool_flags --silent"
-
-# Some flags need to be propagated to the compiler or linker for good
-# libtool support.
-case "$lt_target" in
-*-*-irix6*)
-  # Find out which ABI we are using.
-  echo '[#]line __oline__ "configure"' > conftest.$ac_ext
-  if AC_TRY_EVAL(ac_compile); then
-    case "`/usr/bin/file conftest.o`" in
-    *32-bit*)
-      LD="${LD-ld} -32"
-      ;;
-    *N32*)
-      LD="${LD-ld} -n32"
-      ;;
-    *64-bit*)
-      LD="${LD-ld} -64"
-      ;;
-    esac
-  fi
-  rm -rf conftest*
-  ;;
-
-*-*-sco3.2v5*)
-  # On SCO OpenServer 5, we need -belf to get full-featured binaries.
-  SAVE_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -belf"
-  AC_CACHE_CHECK([whether the C compiler needs -belf], lt_cv_cc_needs_belf,
-    [AC_TRY_LINK([],[],[lt_cv_cc_needs_belf=yes],[lt_cv_cc_needs_belf=no])])
-  if test x"$lt_cv_cc_needs_belf" != x"yes"; then
-    # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf
-    CFLAGS="$SAVE_CFLAGS"
-  fi
-  ;;
-
-ifdef([AC_PROVIDE_AC_LIBTOOL_WIN32_DLL],
-[*-*-cygwin* | *-*-mingw*)
-  AC_CHECK_TOOL(DLLTOOL, dlltool, false)
-  AC_CHECK_TOOL(AS, as, false)
-  AC_CHECK_TOOL(OBJDUMP, objdump, false)
-  ;;
-])
-esac
-])
-
-# AC_LIBTOOL_DLOPEN - enable checks for dlopen support
-AC_DEFUN(AC_LIBTOOL_DLOPEN, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])])
-
-# AC_LIBTOOL_WIN32_DLL - declare package support for building win32 dll's
-AC_DEFUN(AC_LIBTOOL_WIN32_DLL, [AC_BEFORE([$0], [AC_LIBTOOL_SETUP])])
-
-# AC_ENABLE_SHARED - implement the --enable-shared flag
-# Usage: AC_ENABLE_SHARED[(DEFAULT)]
-#   Where DEFAULT is either `yes' or `no'.  If omitted, it defaults to
-#   `yes'.
-AC_DEFUN(AC_ENABLE_SHARED, [dnl
-define([AC_ENABLE_SHARED_DEFAULT], ifelse($1, no, no, yes))dnl
-AC_ARG_ENABLE(shared,
-changequote(<<, >>)dnl
-<<  --enable-shared[=PKGS]  build shared libraries [default=>>AC_ENABLE_SHARED_DEFAULT],
-changequote([, ])dnl
-[p=${PACKAGE-default}
-case "$enableval" in
-yes) enable_shared=yes ;;
-no) enable_shared=no ;;
-*)
-  enable_shared=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_shared=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac],
-enable_shared=AC_ENABLE_SHARED_DEFAULT)dnl
-])
-
-# AC_DISABLE_SHARED - set the default shared flag to --disable-shared
-AC_DEFUN(AC_DISABLE_SHARED, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])dnl
-AC_ENABLE_SHARED(no)])
-
-# AC_ENABLE_STATIC - implement the --enable-static flag
-# Usage: AC_ENABLE_STATIC[(DEFAULT)]
-#   Where DEFAULT is either `yes' or `no'.  If omitted, it defaults to
-#   `yes'.
-AC_DEFUN(AC_ENABLE_STATIC, [dnl
-define([AC_ENABLE_STATIC_DEFAULT], ifelse($1, no, no, yes))dnl
-AC_ARG_ENABLE(static,
-changequote(<<, >>)dnl
-<<  --enable-static[=PKGS]  build static libraries [default=>>AC_ENABLE_STATIC_DEFAULT],
-changequote([, ])dnl
-[p=${PACKAGE-default}
-case "$enableval" in
-yes) enable_static=yes ;;
-no) enable_static=no ;;
-*)
-  enable_static=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_static=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac],
-enable_static=AC_ENABLE_STATIC_DEFAULT)dnl
-])
-
-# AC_DISABLE_STATIC - set the default static flag to --disable-static
-AC_DEFUN(AC_DISABLE_STATIC, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])dnl
-AC_ENABLE_STATIC(no)])
-
-
-# AC_ENABLE_FAST_INSTALL - implement the --enable-fast-install flag
-# Usage: AC_ENABLE_FAST_INSTALL[(DEFAULT)]
-#   Where DEFAULT is either `yes' or `no'.  If omitted, it defaults to
-#   `yes'.
-AC_DEFUN(AC_ENABLE_FAST_INSTALL, [dnl
-define([AC_ENABLE_FAST_INSTALL_DEFAULT], ifelse($1, no, no, yes))dnl
-AC_ARG_ENABLE(fast-install,
-changequote(<<, >>)dnl
-<<  --enable-fast-install[=PKGS]  optimize for fast installation [default=>>AC_ENABLE_FAST_INSTALL_DEFAULT],
-changequote([, ])dnl
-[p=${PACKAGE-default}
-case "$enableval" in
-yes) enable_fast_install=yes ;;
-no) enable_fast_install=no ;;
-*)
-  enable_fast_install=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_fast_install=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac],
-enable_fast_install=AC_ENABLE_FAST_INSTALL_DEFAULT)dnl
-])
-
-# AC_ENABLE_FAST_INSTALL - set the default to --disable-fast-install
-AC_DEFUN(AC_DISABLE_FAST_INSTALL, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])dnl
-AC_ENABLE_FAST_INSTALL(no)])
-
-# AC_PROG_LD - find the path to the GNU or non-GNU linker
-AC_DEFUN(AC_PROG_LD,
-[AC_ARG_WITH(gnu-ld,
-[  --with-gnu-ld           assume the C compiler uses GNU ld [default=no]],
-test "$withval" = no || with_gnu_ld=yes, with_gnu_ld=no)
-AC_REQUIRE([AC_PROG_CC])dnl
-AC_REQUIRE([AC_CANONICAL_HOST])dnl
-AC_REQUIRE([AC_CANONICAL_BUILD])dnl
-ac_prog=ld
-if test "$ac_cv_prog_gcc" = yes; then
-  # Check if gcc -print-prog-name=ld gives a path.
-  AC_MSG_CHECKING([for ld used by GCC])
-  ac_prog=`($CC -print-prog-name=ld) 2>&5`
-  case "$ac_prog" in
-    # Accept absolute paths.
-changequote(,)dnl
-    [\\/]* | [A-Za-z]:[\\/]*)
-      re_direlt='/[^/][^/]*/\.\./'
-changequote([,])dnl
-      # Canonicalize the path of ld
-      ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'`
-      while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do
-	ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"`
-      done
-      test -z "$LD" && LD="$ac_prog"
-      ;;
-  "")
-    # If it fails, then pretend we aren't using GCC.
-    ac_prog=ld
-    ;;
-  *)
-    # If it is relative, then search for the first ld in PATH.
-    with_gnu_ld=unknown
-    ;;
-  esac
-elif test "$with_gnu_ld" = yes; then
-  AC_MSG_CHECKING([for GNU ld])
-else
-  AC_MSG_CHECKING([for non-GNU ld])
-fi
-AC_CACHE_VAL(ac_cv_path_LD,
-[if test -z "$LD"; then
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
-      ac_cv_path_LD="$ac_dir/$ac_prog"
-      # Check to see if the program is GNU ld.  I'd rather use --version,
-      # but apparently some GNU ld's only accept -v.
-      # Break only if it was the GNU/non-GNU ld that we prefer.
-      if "$ac_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then
-	test "$with_gnu_ld" != no && break
-      else
-	test "$with_gnu_ld" != yes && break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-else
-  ac_cv_path_LD="$LD" # Let the user override the test with a path.
-fi])
-LD="$ac_cv_path_LD"
-if test -n "$LD"; then
-  AC_MSG_RESULT($LD)
-else
-  AC_MSG_RESULT(no)
-fi
-test -z "$LD" && AC_MSG_ERROR([no acceptable ld found in \$PATH])
-AC_PROG_LD_GNU
-])
-
-AC_DEFUN(AC_PROG_LD_GNU,
-[AC_CACHE_CHECK([if the linker ($LD) is GNU ld], ac_cv_prog_gnu_ld,
-[# I'd rather use --version here, but apparently some GNU ld's only accept -v.
-if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then
-  ac_cv_prog_gnu_ld=yes
-else
-  ac_cv_prog_gnu_ld=no
-fi])
-])
-
-# AC_PROG_NM - find the path to a BSD-compatible name lister
-AC_DEFUN(AC_PROG_NM,
-[AC_MSG_CHECKING([for BSD-compatible nm])
-AC_CACHE_VAL(ac_cv_path_NM,
-[if test -n "$NM"; then
-  # Let the user override the test.
-  ac_cv_path_NM="$NM"
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
-  for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/nm || test -f $ac_dir/nm$ac_exeext ; then
-      # Check to see if the nm accepts a BSD-compat flag.
-      # Adding the `sed 1q' prevents false positives on HP-UX, which says:
-      #   nm: unknown option "B" ignored
-      if ($ac_dir/nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	ac_cv_path_NM="$ac_dir/nm -B"
-	break
-      elif ($ac_dir/nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	ac_cv_path_NM="$ac_dir/nm -p"
-	break
-      else
-	ac_cv_path_NM=${ac_cv_path_NM="$ac_dir/nm"} # keep the first match, but
-	continue # so that we can try to find one that supports BSD flags
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_NM" && ac_cv_path_NM=nm
-fi])
-NM="$ac_cv_path_NM"
-AC_MSG_RESULT([$NM])
-])
-
-# AC_CHECK_LIBM - check for math library
-AC_DEFUN(AC_CHECK_LIBM,
-[AC_REQUIRE([AC_CANONICAL_HOST])dnl
-LIBM=
-case "$lt_target" in
-*-*-beos* | *-*-cygwin*)
-  # These system don't have libm
-  ;;
-*-ncr-sysv4.3*)
-  AC_CHECK_LIB(mw, _mwvalidcheckl, LIBM="-lmw")
-  AC_CHECK_LIB(m, main, LIBM="$LIBM -lm")
-  ;;
-*)
-  AC_CHECK_LIB(m, main, LIBM="-lm")
-  ;;
-esac
-])
-
-# AC_LIBLTDL_CONVENIENCE[(dir)] - sets LIBLTDL to the link flags for
-# the libltdl convenience library, adds --enable-ltdl-convenience to
-# the configure arguments.  Note that LIBLTDL is not AC_SUBSTed, nor
-# is AC_CONFIG_SUBDIRS called.  If DIR is not provided, it is assumed
-# to be `${top_builddir}/libltdl'.  Make sure you start DIR with
-# '${top_builddir}/' (note the single quotes!) if your package is not
-# flat, and, if you're not using automake, define top_builddir as
-# appropriate in the Makefiles.
-AC_DEFUN(AC_LIBLTDL_CONVENIENCE, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])dnl
-  case "$enable_ltdl_convenience" in
-  no) AC_MSG_ERROR([this package needs a convenience libltdl]) ;;
-  "") enable_ltdl_convenience=yes
-      ac_configure_args="$ac_configure_args --enable-ltdl-convenience" ;;
-  esac
-  LIBLTDL=ifelse($#,1,$1,['${top_builddir}/libltdl'])/libltdlc.la
-  INCLTDL=ifelse($#,1,-I$1,['-I${top_builddir}/libltdl'])
-])
-
-# AC_LIBLTDL_INSTALLABLE[(dir)] - sets LIBLTDL to the link flags for
-# the libltdl installable library, and adds --enable-ltdl-install to
-# the configure arguments.  Note that LIBLTDL is not AC_SUBSTed, nor
-# is AC_CONFIG_SUBDIRS called.  If DIR is not provided, it is assumed
-# to be `${top_builddir}/libltdl'.  Make sure you start DIR with
-# '${top_builddir}/' (note the single quotes!) if your package is not
-# flat, and, if you're not using automake, define top_builddir as
-# appropriate in the Makefiles.
-# In the future, this macro may have to be called after AC_PROG_LIBTOOL.
-AC_DEFUN(AC_LIBLTDL_INSTALLABLE, [AC_BEFORE([$0],[AC_LIBTOOL_SETUP])dnl
-  AC_CHECK_LIB(ltdl, main,
-  [test x"$enable_ltdl_install" != xyes && enable_ltdl_install=no],
-  [if test x"$enable_ltdl_install" = xno; then
-     AC_MSG_WARN([libltdl not installed, but installation disabled])
-   else
-     enable_ltdl_install=yes
-   fi
-  ])
-  if test x"$enable_ltdl_install" = x"yes"; then
-    ac_configure_args="$ac_configure_args --enable-ltdl-install"
-    LIBLTDL=ifelse($#,1,$1,['${top_builddir}/libltdl'])/libltdl.la
-    INCLTDL=ifelse($#,1,-I$1,['-I${top_builddir}/libltdl'])
-  else
-    ac_configure_args="$ac_configure_args --enable-ltdl-install=no"
-    LIBLTDL="-lltdl"
-    INCLTDL=
-  fi
-])
-
-dnl old names
-AC_DEFUN(AM_PROG_LIBTOOL, [indir([AC_PROG_LIBTOOL])])dnl
-AC_DEFUN(AM_ENABLE_SHARED, [indir([AC_ENABLE_SHARED], $@)])dnl
-AC_DEFUN(AM_ENABLE_STATIC, [indir([AC_ENABLE_STATIC], $@)])dnl
-AC_DEFUN(AM_DISABLE_SHARED, [indir([AC_DISABLE_SHARED], $@)])dnl
-AC_DEFUN(AM_DISABLE_STATIC, [indir([AC_DISABLE_STATIC], $@)])dnl
-AC_DEFUN(AM_PROG_LD, [indir([AC_PROG_LD])])dnl
-AC_DEFUN(AM_PROG_NM, [indir([AC_PROG_NM])])dnl
-
-dnl This is just to silence aclocal about the macro not being used
-ifelse([AC_DISABLE_FAST_INSTALL])dnl
-
 # Like AC_CONFIG_HEADER, but automatically create stamp file.
 
 AC_DEFUN(AM_CONFIG_HEADER,
@@ -569,348 +176,3 @@ else
   $1_FALSE=
 fi])
 
-# This file is derived from `gettext.m4'.  The difference is that the
-# included macros assume Cygnus-style source and build trees.
-
-# Macro to add for using GNU gettext.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 3
-
-AC_DEFUN(CY_WITH_NLS,
-  [AC_MSG_CHECKING([whether NLS is requested])
-    dnl Default is enabled NLS
-    AC_ARG_ENABLE(nls,
-      [  --disable-nls           do not use Native Language Support],
-      USE_NLS=$enableval, USE_NLS=yes)
-    AC_MSG_RESULT($USE_NLS)
-    AC_SUBST(USE_NLS)
-
-    USE_INCLUDED_LIBINTL=no
-
-    dnl If we use NLS figure out what method
-    if test "$USE_NLS" = "yes"; then
-      AC_DEFINE(ENABLE_NLS, 1, [Define to 1 if NLS is requested])
-      AC_MSG_CHECKING([whether included gettext is requested])
-      AC_ARG_WITH(included-gettext,
-        [  --with-included-gettext use the GNU gettext library included here],
-        nls_cv_force_use_gnu_gettext=$withval,
-        nls_cv_force_use_gnu_gettext=no)
-      AC_MSG_RESULT($nls_cv_force_use_gnu_gettext)
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-        dnl User does not insist on using GNU NLS library.  Figure out what
-        dnl to use.  If gettext or catgets are available (in this order) we
-        dnl use this.  Else we have to fall back to GNU NLS library.
-	dnl catgets is only used if permitted by option --with-catgets.
-	nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=NONE
-
-	AC_CHECK_HEADER(libintl.h,
-	  [AC_CACHE_CHECK([for gettext in libc], gt_cv_func_gettext_libc,
-	    [AC_TRY_LINK([#include <libintl.h>], [return (int) gettext ("")],
-	       gt_cv_func_gettext_libc=yes, gt_cv_func_gettext_libc=no)])
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     AC_CHECK_LIB(intl, bindtextdomain,
-	       [AC_CACHE_CHECK([for gettext in libintl],
-		 gt_cv_func_gettext_libintl,
-		 [AC_TRY_LINK([], [return (int) gettext ("")],
-		 gt_cv_func_gettext_libintl=yes,
-		 gt_cv_func_gettext_libintl=no)])])
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-	      AC_DEFINE(HAVE_GETTEXT, 1,
-			[Define as 1 if you have gettext and don't want to use GNU gettext.])
-	      AM_PATH_PROG_WITH_TEST(MSGFMT, msgfmt,
-		[test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"], no)dnl
-	      if test "$MSGFMT" != "no"; then
-		AC_CHECK_FUNCS(dcgettext)
-		AC_PATH_PROG(GMSGFMT, gmsgfmt, $MSGFMT)
-		AM_PATH_PROG_WITH_TEST(XGETTEXT, xgettext,
-		  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"], :)
-		AC_TRY_LINK(, [extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr],
-		  [CATOBJEXT=.gmo
-		   DATADIRNAME=share],
-		  [CATOBJEXT=.mo
-		   DATADIRNAME=lib])
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-	])
-
-	dnl In the standard gettext, we would now check for catgets.
-        dnl However, we never want to use catgets for our releases.
-
-        if test "$CATOBJEXT" = "NONE"; then
-	  dnl Neither gettext nor catgets in included in the C library.
-	  dnl Fall back on GNU gettext library.
-	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-        dnl Mark actions used to generate GNU NLS library.
-        INTLOBJS="\$(GETTOBJS)"
-        AM_PATH_PROG_WITH_TEST(MSGFMT, msgfmt,
-	  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"], msgfmt)
-        AC_PATH_PROG(GMSGFMT, gmsgfmt, $MSGFMT)
-        AM_PATH_PROG_WITH_TEST(XGETTEXT, xgettext,
-	  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"], :)
-        AC_SUBST(MSGFMT)
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-      dnl Test whether we really found GNU xgettext.
-      if test "$XGETTEXT" != ":"; then
-	dnl If it is no GNU xgettext we define it as : so that the
-	dnl Makefiles still can work.
-	if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  AC_MSG_RESULT(
-	    [found xgettext programs is not GNU xgettext; ignore it])
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
-    else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
-    fi
-
-    dnl These rules are solely for the distribution goal.  While doing this
-    dnl we only have to keep exactly one list of the available catalogs
-    dnl in configure.in.
-    for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-    dnl Make all variables we use known to autoconf.
-    AC_SUBST(USE_INCLUDED_LIBINTL)
-    AC_SUBST(CATALOGS)
-    AC_SUBST(CATOBJEXT)
-    AC_SUBST(DATADIRNAME)
-    AC_SUBST(GMOFILES)
-    AC_SUBST(INSTOBJEXT)
-    AC_SUBST(INTLDEPS)
-    AC_SUBST(INTLLIBS)
-    AC_SUBST(INTLOBJS)
-    AC_SUBST(POFILES)
-    AC_SUBST(POSUB)
-  ])
-
-AC_DEFUN(CY_GNU_GETTEXT,
-  [AC_REQUIRE([AC_PROG_MAKE_SET])dnl
-   AC_REQUIRE([AC_PROG_CC])dnl
-   AC_REQUIRE([AC_PROG_RANLIB])dnl
-   AC_REQUIRE([AC_ISC_POSIX])dnl
-   AC_REQUIRE([AC_HEADER_STDC])dnl
-   AC_REQUIRE([AC_C_CONST])dnl
-   AC_REQUIRE([AC_C_INLINE])dnl
-   AC_REQUIRE([AC_TYPE_OFF_T])dnl
-   AC_REQUIRE([AC_TYPE_SIZE_T])dnl
-   AC_REQUIRE([AC_FUNC_ALLOCA])dnl
-   AC_REQUIRE([AC_FUNC_MMAP])dnl
-
-   AC_CHECK_HEADERS([argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h])
-   AC_CHECK_FUNCS([getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next])
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-     AC_CHECK_FUNCS(stpcpy)
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-     AC_DEFINE(HAVE_STPCPY, 1, [Define if you have the stpcpy function])
-   fi
-
-   AM_LC_MESSAGES
-   CY_WITH_NLS
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       AC_MSG_CHECKING(for catalogs to be installed)
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       AC_MSG_RESULT($LINGUAS)
-     fi
-
-     dnl Construct list of names of catalog files to be constructed.
-     if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-   dnl The reference to <locale.h> in the installed <libintl.h> file
-   dnl must be resolved because we cannot expect the users of this
-   dnl to define HAVE_LOCALE_H.
-   if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-   AC_SUBST(INCLUDE_LOCALE_H)
-
-   dnl Determine which catalog format we have (if any is needed)
-   dnl For now we know about two different formats:
-   dnl   Linux libc-5 and the normal X/Open format
-   if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 AC_CHECK_HEADER(linux/version.h, msgformat=linux, msgformat=xopen)
-
-	 dnl Transform the SED scripts while copying because some dumb SEDs
-         dnl cannot handle comments.
-	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-      dnl po2tbl.sed is always needed.
-      sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-   dnl In the intl/Makefile.in we have a special dependency which makes
-   dnl only sense for gettext.  We comment this out for non-gettext
-   dnl packages.
-   if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-   AC_SUBST(GT_NO)
-   AC_SUBST(GT_YES)
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-   AC_SUBST(MKINSTALLDIRS)
-
-   dnl *** For now the libtool support in intl/Makefile is not for real.
-   l=
-   AC_SUBST(l)
-
-   dnl Generate list of files to be processed by xgettext which will
-   dnl be included in po/Makefile.  But only do this if the po directory
-   dnl exists in srcdir.
-   if test -d $srcdir/po; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
-  ])
-
-# Search path for a program which passes the given test.
-# Ulrich Drepper <drepper@cygnus.com>, 1996.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-dnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR,
-dnl   TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]])
-AC_DEFUN(AM_PATH_PROG_WITH_TEST,
-[# Extract the first word of "$2", so it can be a program name with args.
-set dummy $2; ac_word=[$]2
-AC_MSG_CHECKING([for $ac_word])
-AC_CACHE_VAL(ac_cv_path_$1,
-[case "[$]$1" in
-  /*)
-  ac_cv_path_$1="[$]$1" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in ifelse([$5], , $PATH, [$5]); do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if [$3]; then
-	ac_cv_path_$1="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-dnl If no 4th arg is given, leave the cache variable unset,
-dnl so AC_PATH_PROGS will keep looking.
-ifelse([$4], , , [  test -z "[$]ac_cv_path_$1" && ac_cv_path_$1="$4"
-])dnl
-  ;;
-esac])dnl
-$1="$ac_cv_path_$1"
-if test -n "[$]$1"; then
-  AC_MSG_RESULT([$]$1)
-else
-  AC_MSG_RESULT(no)
-fi
-AC_SUBST($1)dnl
-])
-
-# Check whether LC_MESSAGES is available in <locale.h>.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-AC_DEFUN(AM_LC_MESSAGES,
-  [if test $ac_cv_header_locale_h = yes; then
-    AC_CACHE_CHECK([for LC_MESSAGES], am_cv_val_LC_MESSAGES,
-      [AC_TRY_LINK([#include <locale.h>], [return LC_MESSAGES],
-       am_cv_val_LC_MESSAGES=yes, am_cv_val_LC_MESSAGES=no)])
-    if test $am_cv_val_LC_MESSAGES = yes; then
-      AC_DEFINE(HAVE_LC_MESSAGES, 1,
-		[Define if your locale.h file contains LC_MESSAGES.])
-    fi
-  fi])
-
diff --git a/gnu/usr.bin/binutils/opcodes/alpha-dis.c b/gnu/usr.bin/binutils/opcodes/alpha-dis.c
index ce770bb41c8..8633d7bb5b3 100644
--- a/gnu/usr.bin/binutils/opcodes/alpha-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/alpha-dis.c
@@ -1,5 +1,5 @@
 /* alpha-dis.c -- Disassemble Alpha AXP instructions
-   Copyright 1996, 1999 Free Software Foundation, Inc.
+   Copyright 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
    Contributed by Richard Henderson <rth@tamu.edu>,
    patterned after the PPC opcode handling written by Ian Lance Taylor.
 
diff --git a/gnu/usr.bin/binutils/opcodes/arm-dis.c b/gnu/usr.bin/binutils/opcodes/arm-dis.c
index a3e7112b3fc..b90f820602f 100644
--- a/gnu/usr.bin/binutils/opcodes/arm-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/arm-dis.c
@@ -1,5 +1,6 @@
 /* Instruction printing code for the ARM
-   Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. 
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+   Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
@@ -60,6 +61,8 @@ static arm_regname regnames[] =
 {
   { "raw" , "Select raw register names",
     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
+  { "gcc",  "Select register names used by GCC",
+    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
   { "std",  "Select register names used in ARM's ISA documentation",
     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
   { "apcs", "Select register names used in the APCS",
@@ -70,7 +73,7 @@ static arm_regname regnames[] =
     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
 };
 
-/* Default to standard register name set.  */
+/* Default to GCC register name set.  */
 static unsigned int regname_selected = 1;
 
 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
@@ -419,28 +422,39 @@ print_insn_arm (pc, info, given)
 			}
 		      break;
 
+		    case 'B':
+		      /* Print ARM V5 BLX(1) address: pc+25 bits.  */
+		      {
+			bfd_vma address;
+			bfd_vma offset = 0;
+			
+			if (given & 0x00800000)
+			  /* Is signed, hi bits should be ones.  */
+			  offset = (-1) ^ 0x00ffffff;
+
+			/* Offset is (SignExtend(offset field)<<2).  */
+			offset += given & 0x00ffffff;
+			offset <<= 2;
+			address = offset + pc + 8;
+			
+			if (given & 0x01000000)
+			  /* H bit allows addressing to 2-byte boundaries.  */
+			  address += 2;
+
+		        info->print_address_func (address, info);
+		      }
+		      break;
+
 		    case 'C':
-		      switch (given & 0x000f0000)
-			{
-			default:
-			  func (stream, "_???");
-			  break;
-			case 0x90000:
-			  func (stream, "_all");
-			  break;
-			case 0x10000:
-			  func (stream, "_c");
-			  break;
-			case 0x20000:
-			  func (stream, "_x");
-			  break;
-			case 0x40000:
-			  func (stream, "_s");
-			  break;
-			case 0x80000:
-			  func (stream, "_f");
-			  break;
-			}
+		      func (stream, "_");
+		      if (given & 0x80000)
+			func (stream, "f");
+		      if (given & 0x40000)
+			func (stream, "s");
+		      if (given & 0x20000)
+			func (stream, "x");
+		      if (given & 0x10000)
+			func (stream, "c");
 		      break;
 
 		    case 'F':
@@ -658,6 +672,9 @@ print_insn_thumb (pc, info, given)
 	      info->bytes_per_chunk = 4;
 	      info->bytes_per_line  = 4;
 	      
+	      if ((given & 0x10000000) == 0)
+                 func (stream, "blx\t");
+	      else
                 func (stream, "bl\t");
 		
               info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
@@ -1027,6 +1044,14 @@ print_insn (pc, info, little)
 	given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
     }
   
+  if (info->flags & INSN_HAS_RELOC)
+    /* If the instruction has a reloc associated with it, then
+       the offset field in the instruction will actually be the
+       addend for the reloc.  (We are using REL type relocs).
+       In such cases, we can ignore the pc when computing
+       addresses, since the addend is not currently pc-relative.  */
+    pc = 0;
+  
   if (is_thumb)
     status = print_insn_thumb (pc, info, given);
   else
diff --git a/gnu/usr.bin/binutils/opcodes/arm-opc.h b/gnu/usr.bin/binutils/opcodes/arm-opc.h
index 5ecde4be6ad..36b1809aad4 100644
--- a/gnu/usr.bin/binutils/opcodes/arm-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/arm-opc.h
@@ -1,6 +1,7 @@
 /* Opcode table for the ARM.
 
-   Copyright 1994, 1995, 1996, 1997, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -51,6 +52,7 @@ struct thumb_opcode
    %a			print address for ldr/str instruction
    %s                   print address for ldr/str halfword/signextend instruction
    %b			print branch destination
+   %B			print arm BLX(1) destination
    %A			print address for ldc/stc/ldf/stf instruction
    %m			print register mask for ldm/stm instruction
    %C			print the PSR sub type.
@@ -75,7 +77,7 @@ Thumb specific format options:
 
 static struct arm_opcode arm_opcodes[] =
 {
-    /* ARM instructions */
+    /* ARM instructions.  */
     {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
     {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
     {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
@@ -83,6 +85,59 @@ static struct arm_opcode arm_opcodes[] =
     {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
     {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
     {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+
+    /* XScale instructions.  */
+    {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
+    {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
+    {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
+    {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
+    {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
+    {0xf450f000, 0xfc70f000, "pld\t%a"},
+    
+    /* V5 Instructions.  */
+    {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
+    {0xfa000000, 0xfe000000, "blx\t%B"},
+    {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
+    {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
+    {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
+    {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
+    {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+    {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+    {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+
+    /* V5E "El Segundo" Instructions.  */    
+    {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
+    {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
+    {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+    {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+    {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+    {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+
+    {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+    {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+
+    {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+    {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+    {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+    {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+
+    {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
+    {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
+    {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
+    {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
+
+    {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
+    {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
+
+    {0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15r, %0-3r, %16-19r"},
+    {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
+    {0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
+    {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
+
+    {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+    {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+
+    /* ARM Instructions.  */
     {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"},
     {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"},
     {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
@@ -174,10 +229,21 @@ static struct arm_opcode arm_opcodes[] =
 
 static struct thumb_opcode thumb_opcodes[] =
 {
-  /* Thumb instructions */
-  {0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */
+  /* Thumb instructions.  */
+
+  /* ARM V5 ISA extends Thumb.  */
+  {0xbe00, 0xff00, "bkpt\t%0-7x"},
+  {0x4780, 0xff87, "blx\t%3-6r"},	/* note: 4 bit register number.  */
+  /* Note: this is BLX(2).  BLX(1) is done in arm-dis.c/print_insn_thumb()
+     as an extension of the special processing there for Thumb BL.
+     BL and BLX(1) involve 2 successive 16-bit instructions, which must
+     always appear together in the correct order.  So, the empty
+     string is put in this table, and the string interpreter takes <empty>
+     to mean it has a pair of BL-ish instructions.  */
+  {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
+  /* Format 5 instructions do not update the PSR.  */
   {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
-  /* format 4 */
+  /* Format 4.  */
   {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
   {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
   {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
diff --git a/gnu/usr.bin/binutils/opcodes/configure b/gnu/usr.bin/binutils/opcodes/configure
index e868e217de3..a38b19c4d99 100644
--- a/gnu/usr.bin/binutils/opcodes/configure
+++ b/gnu/usr.bin/binutils/opcodes/configure
@@ -22,16 +22,22 @@ ac_help="$ac_help
 ac_help="$ac_help
   --disable-libtool-lock  avoid locking (might break parallel builds)"
 ac_help="$ac_help
+  --with-pic              try to use only PIC/non-PIC objects [default=use both]"
+ac_help="$ac_help
   --enable-targets        alternative target configurations"
 ac_help="$ac_help
   --enable-commonbfdlib   build shared BFD/opcodes/libiberty library"
 ac_help="$ac_help
+  --enable-build-warnings Enable build-time compiler warnings if gcc is used"
+ac_help="$ac_help
   --enable-maintainer-mode enable make rules and dependencies not useful
                           (and sometimes confusing) to the casual installer"
 ac_help="$ac_help
   --disable-nls           do not use Native Language Support"
 ac_help="$ac_help
   --with-included-gettext use the GNU gettext library included here"
+ac_help="$ac_help
+  --enable-cgen-maint[=dir]    build cgen generated files"
 
 # Initialize some variables set by options.
 # The variables have the same names as the options, with
@@ -552,6 +558,68 @@ else
   ac_n= ac_c='\c' ac_t=
 fi
 
+echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
+echo "configure:563: checking for Cygwin environment" >&5
+if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 568 "configure"
+#include "confdefs.h"
+
+int main() {
+
+#ifndef __CYGWIN__
+#define __CYGWIN__ __CYGWIN32__
+#endif
+return __CYGWIN__;
+; return 0; }
+EOF
+if { (eval echo configure:579: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_cygwin=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_cygwin=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_cygwin" 1>&6
+CYGWIN=
+test "$ac_cv_cygwin" = yes && CYGWIN=yes
+echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
+echo "configure:596: checking for mingw32 environment" >&5
+if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  cat > conftest.$ac_ext <<EOF
+#line 601 "configure"
+#include "confdefs.h"
+
+int main() {
+return __MINGW32__;
+; return 0; }
+EOF
+if { (eval echo configure:608: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  rm -rf conftest*
+  ac_cv_mingw32=yes
+else
+  echo "configure: failed program was:" >&5
+  cat conftest.$ac_ext >&5
+  rm -rf conftest*
+  ac_cv_mingw32=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_mingw32" 1>&6
+MINGW32=
+test "$ac_cv_mingw32" = yes && MINGW32=yes
 
 
 ac_aux_dir=
@@ -601,7 +669,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
 fi
 
 echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:605: checking host system type" >&5
+echo "configure:673: checking host system type" >&5
 
 host_alias=$host
 case "$host_alias" in
@@ -622,7 +690,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$host" 1>&6
 
 echo $ac_n "checking target system type""... $ac_c" 1>&6
-echo "configure:626: checking target system type" >&5
+echo "configure:694: checking target system type" >&5
 
 target_alias=$target
 case "$target_alias" in
@@ -640,7 +708,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
 echo "$ac_t""$target" 1>&6
 
 echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:644: checking build system type" >&5
+echo "configure:712: checking build system type" >&5
 
 build_alias=$build
 case "$build_alias" in
@@ -665,7 +733,7 @@ test "$host_alias" != "$target_alias" &&
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:669: checking for $ac_word" >&5
+echo "configure:737: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -695,7 +763,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:699: checking for $ac_word" >&5
+echo "configure:767: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -746,7 +814,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:750: checking for $ac_word" >&5
+echo "configure:818: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -778,7 +846,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:782: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:850: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -789,12 +857,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 793 "configure"
+#line 861 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:798: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:866: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -820,12 +888,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:824: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:892: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:829: checking whether we are using GNU C" >&5
+echo "configure:897: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -834,7 +902,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:838: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:906: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -853,7 +921,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:857: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:925: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -885,7 +953,7 @@ else
 fi
 
 echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
-echo "configure:889: checking for POSIXized ISC" >&5
+echo "configure:957: checking for POSIXized ISC" >&5
 if test -d /etc/conf/kconfig.d &&
   grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1
 then
@@ -909,7 +977,7 @@ fi
 # We currently only use the version number for the name of any shared
 # library.  For user convenience, we always use the same version
 # number that BFD is using.
-BFD_VERSION=`grep INIT_AUTOMAKE ${srcdir}/../bfd/configure.in | sed -n -e 's/[ 	]//g' -e 's/^.*,\(.*\)).*$/\1/p'`
+BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ 	]*\([^ 	]*\)[ 	]*).*/\1/p' < ${srcdir}/../bfd/configure.in`
 
 # Find a good install program.  We prefer a C program (faster),
 # so one script is as good as another.  But avoid the broken or
@@ -923,7 +991,7 @@ BFD_VERSION=`grep INIT_AUTOMAKE ${srcdir}/../bfd/configure.in | sed -n -e 's/[
 # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
 # ./install, which can be erroneously created by make from ./install.sh.
 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:927: checking for a BSD compatible install" >&5
+echo "configure:995: checking for a BSD compatible install" >&5
 if test -z "$INSTALL"; then
 if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -976,7 +1044,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
 test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
 
 echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6
-echo "configure:980: checking whether build environment is sane" >&5
+echo "configure:1048: checking whether build environment is sane" >&5
 # Just in case
 sleep 1
 echo timestamp > conftestfile
@@ -1033,7 +1101,7 @@ test "$program_suffix" != NONE &&
 test "$program_transform_name" = "" && program_transform_name="s,x,x,"
 
 echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
-echo "configure:1037: checking whether ${MAKE-make} sets \${MAKE}" >&5
+echo "configure:1105: checking whether ${MAKE-make} sets \${MAKE}" >&5
 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -1079,7 +1147,7 @@ EOF
 
 missing_dir=`cd $ac_aux_dir && pwd`
 echo $ac_n "checking for working aclocal""... $ac_c" 1>&6
-echo "configure:1083: checking for working aclocal" >&5
+echo "configure:1151: checking for working aclocal" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1092,7 +1160,7 @@ else
 fi
 
 echo $ac_n "checking for working autoconf""... $ac_c" 1>&6
-echo "configure:1096: checking for working autoconf" >&5
+echo "configure:1164: checking for working autoconf" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1105,7 +1173,7 @@ else
 fi
 
 echo $ac_n "checking for working automake""... $ac_c" 1>&6
-echo "configure:1109: checking for working automake" >&5
+echo "configure:1177: checking for working automake" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1118,7 +1186,7 @@ else
 fi
 
 echo $ac_n "checking for working autoheader""... $ac_c" 1>&6
-echo "configure:1122: checking for working autoheader" >&5
+echo "configure:1190: checking for working autoheader" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1131,7 +1199,7 @@ else
 fi
 
 echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6
-echo "configure:1135: checking for working makeinfo" >&5
+echo "configure:1203: checking for working makeinfo" >&5
 # Run test in a subshell; some versions of sh will print an error if
 # an executable is not found, even if stderr is redirected.
 # Redirect stdin to placate older versions of autoconf.  Sigh.
@@ -1154,7 +1222,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ar; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1158: checking for $ac_word" >&5
+echo "configure:1226: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1186,7 +1254,7 @@ fi
 # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1190: checking for $ac_word" >&5
+echo "configure:1258: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1218,7 +1286,7 @@ if test -n "$ac_tool_prefix"; then
   # Extract the first word of "ranlib", so it can be a program name with args.
 set dummy ranlib; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1222: checking for $ac_word" >&5
+echo "configure:1290: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1321,36 +1389,6 @@ else
   enable_fast_install=yes
 fi
 
-# Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1328: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_RANLIB="ranlib"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
-fi
-fi
-RANLIB="$ac_cv_prog_RANLIB"
-if test -n "$RANLIB"; then
-  echo "$ac_t""$RANLIB" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
 # Check whether --with-gnu-ld or --without-gnu-ld was given.
 if test "${with_gnu_ld+set}" = set; then
   withval="$with_gnu_ld"
@@ -1363,8 +1401,14 @@ ac_prog=ld
 if test "$ac_cv_prog_gcc" = yes; then
   # Check if gcc -print-prog-name=ld gives a path.
   echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6
-echo "configure:1367: checking for ld used by GCC" >&5
-  ac_prog=`($CC -print-prog-name=ld) 2>&5`
+echo "configure:1405: checking for ld used by GCC" >&5
+  case $host in
+  *-*-mingw*)
+    # gcc leaves a trailing carriage return which upsets mingw
+    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;;
+  *)
+    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;
+  esac
   case "$ac_prog" in
     # Accept absolute paths.
     [\\/]* | [A-Za-z]:[\\/]*)
@@ -1387,10 +1431,10 @@ echo "configure:1367: checking for ld used by GCC" >&5
   esac
 elif test "$with_gnu_ld" = yes; then
   echo $ac_n "checking for GNU ld""... $ac_c" 1>&6
-echo "configure:1391: checking for GNU ld" >&5
+echo "configure:1435: checking for GNU ld" >&5
 else
   echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6
-echo "configure:1394: checking for non-GNU ld" >&5
+echo "configure:1438: checking for non-GNU ld" >&5
 fi
 if eval "test \"`echo '$''{'ac_cv_path_LD'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -1425,7 +1469,7 @@ else
 fi
 test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; }
 echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6
-echo "configure:1429: checking if the linker ($LD) is GNU ld" >&5
+echo "configure:1473: checking if the linker ($LD) is GNU ld" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gnu_ld'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1438,10 +1482,23 @@ fi
 fi
 
 echo "$ac_t""$ac_cv_prog_gnu_ld" 1>&6
+with_gnu_ld=$ac_cv_prog_gnu_ld
+
 
+echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6
+echo "configure:1490: checking for $LD option to reload object files" >&5
+if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  lt_cv_ld_reload_flag='-r'
+fi
+
+echo "$ac_t""$lt_cv_ld_reload_flag" 1>&6
+reload_flag=$lt_cv_ld_reload_flag
+test -n "$reload_flag" && reload_flag=" $reload_flag"
 
 echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6
-echo "configure:1445: checking for BSD-compatible nm" >&5
+echo "configure:1502: checking for BSD-compatible nm" >&5
 if eval "test \"`echo '$''{'ac_cv_path_NM'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1452,18 +1509,20 @@ else
   IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
   for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do
     test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/nm || test -f $ac_dir/nm$ac_exeext ; then
+    tmp_nm=$ac_dir/${ac_tool_prefix}nm
+    if test -f $tmp_nm || test -f $tmp_nm$ac_exeext ; then
       # Check to see if the nm accepts a BSD-compat flag.
       # Adding the `sed 1q' prevents false positives on HP-UX, which says:
       #   nm: unknown option "B" ignored
-      if ($ac_dir/nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	ac_cv_path_NM="$ac_dir/nm -B"
+      # Tru64's nm complains that /dev/null is an invalid object file
+      if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then
+	ac_cv_path_NM="$tmp_nm -B"
 	break
-      elif ($ac_dir/nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	ac_cv_path_NM="$ac_dir/nm -p"
+      elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
+	ac_cv_path_NM="$tmp_nm -p"
 	break
       else
-	ac_cv_path_NM=${ac_cv_path_NM="$ac_dir/nm"} # keep the first match, but
+	ac_cv_path_NM=${ac_cv_path_NM="$tmp_nm"} # keep the first match, but
 	continue # so that we can try to find one that supports BSD flags
       fi
     fi
@@ -1477,7 +1536,7 @@ NM="$ac_cv_path_NM"
 echo "$ac_t""$NM" 1>&6
 
 echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6
-echo "configure:1481: checking whether ln -s works" >&5
+echo "configure:1540: checking whether ln -s works" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1497,12 +1556,478 @@ else
   echo "$ac_t""no" 1>&6
 fi
 
+echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6
+echo "configure:1561: checking how to recognise dependant libraries" >&5
+if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  lt_cv_file_magic_cmd='$MAGIC_CMD'
+lt_cv_file_magic_test_file=
+lt_cv_deplibs_check_method='unknown'
+# Need to set the preceding variable on all platforms that support
+# interlibrary dependencies.
+# 'none' -- dependencies not supported.
+# `unknown' -- same as none, but documents that we really don't know.
+# 'pass_all' -- all dependencies passed with no checks.
+# 'test_compile' -- check by making test program.
+# 'file_magic [regex]' -- check by looking for files in library path
+# which responds to the $file_magic_cmd with a given egrep regex.
+# If you have `file' or equivalent on your system and you're not sure
+# whether `pass_all' will *always* work, you probably want this one.
+
+case "$host_os" in
+aix4*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+beos*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+bsdi4*)
+    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)'
+    lt_cv_file_magic_cmd='/usr/bin/file -L'
+  lt_cv_file_magic_test_file=/shlib/libc.so
+  ;;
+
+cygwin* | mingw* |pw32*)
+  lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
+  lt_cv_file_magic_cmd='$OBJDUMP -f'
+  ;;
+
+freebsd* )
+  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
+    case "$host_cpu" in
+    i*86 )
+      # Not sure whether the presence of OpenBSD here was a mistake.
+      # Let's accept both of them until this is cleared up.
+            lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library'
+            lt_cv_file_magic_cmd=/usr/bin/file
+      lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*`
+      ;;
+    esac
+  else
+    lt_cv_deplibs_check_method=pass_all
+  fi
+  ;;
+
+gnu*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+hpux10.20*)
+  # TODO:  Does this work for hpux-11 too?
+  lt_cv_deplibs_check_method='file_magic (s0-90-90-9|PA-RISC0-9.0-9) shared library'
+  lt_cv_file_magic_cmd=/usr/bin/file
+  lt_cv_file_magic_test_file=/usr/lib/libc.sl
+  ;;
+
+irix5* | irix6*)
+  case "$host_os" in
+  irix5*)
+    # this will be overridden with pass_all, but let us keep it just in case
+    lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1"
+    ;;
+  *)
+    case "$LD" in
+    *-32|*"-32 ") libmagic=32-bit;;
+    *-n32|*"-n32 ") libmagic=N32;;
+    *-64|*"-64 ") libmagic=64-bit;;
+    *) libmagic=never-match;;
+    esac
+    # this will be overridden with pass_all, but let us keep it just in case
+        lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1"
+        ;;
+  esac
+  lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*`
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+# This must be Linux ELF.
+linux-gnu*)
+  case "$host_cpu" in
+  alpha* | i*86 | powerpc* | sparc* | ia64* )
+    lt_cv_deplibs_check_method=pass_all ;;
+  *)
+    # glibc up to 2.1.1 does not perform some relocations on ARM
+        lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;;
+      esac
+  lt_cv_file_magic_test_file=`echo /lib/libc.so* /lib/libc-*.so`
+  ;;
+
+netbsd*)
+  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then :
+  else
+        lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB shared object'
+        lt_cv_file_magic_cmd='/usr/bin/file -L'
+    lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
+  fi
+  ;;
+
+osf3* | osf4* | osf5*)
+  # this will be overridden with pass_all, but let us keep it just in case
+  lt_cv_deplibs_check_method='file_magic COFF format alpha shared library'
+  lt_cv_file_magic_test_file=/shlib/libc.so
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+sco3.2v5*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+solaris*)
+  lt_cv_deplibs_check_method=pass_all
+  lt_cv_file_magic_test_file=/lib/libc.so
+  ;;
+
+sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+  case "$host_vendor" in
+  ncr)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  motorola)
+        lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]'
+        lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
+    ;;
+  esac
+  ;;
+esac
+
+fi
+
+echo "$ac_t""$lt_cv_deplibs_check_method" 1>&6
+file_magic_cmd=$lt_cv_file_magic_cmd
+deplibs_check_method=$lt_cv_deplibs_check_method
+
+echo $ac_n "checking for object suffix""... $ac_c" 1>&6
+echo "configure:1704: checking for object suffix" >&5
+if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  rm -f conftest*
+echo 'int i = 1;' > conftest.$ac_ext
+if { (eval echo configure:1710: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  for ac_file in conftest.*; do
+    case $ac_file in
+    *.c) ;;
+    *) ac_cv_objext=`echo $ac_file | sed -e s/conftest.//` ;;
+    esac
+  done
+else
+  { echo "configure: error: installation or configuration problem; compiler does not work" 1>&2; exit 1; }
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_objext" 1>&6
+OBJEXT=$ac_cv_objext
+ac_objext=$ac_cv_objext
+
+
+
+echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
+echo "configure:1730: checking for executable suffix" >&5
+if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test "$CYGWIN" = yes || test "$MINGW32" = yes; then
+  ac_cv_exeext=.exe
+else
+  rm -f conftest*
+  echo 'int main () { return 0; }' > conftest.$ac_ext
+  ac_cv_exeext=
+  if { (eval echo configure:1740: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+    for file in conftest.*; do
+      case $file in
+      *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+      *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
+      esac
+    done
+  else
+    { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; }
+  fi
+  rm -f conftest*
+  test x"${ac_cv_exeext}" = x && ac_cv_exeext=no
+fi
+fi
+
+EXEEXT=""
+test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext}
+echo "$ac_t""${ac_cv_exeext}" 1>&6
+ac_exeext=$EXEEXT
+
+# Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers!
+
+# Only perform the check for file, if the check method requires it
+case "$deplibs_check_method" in
+file_magic*)
+  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
+    echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6
+echo "configure:1767: checking for ${ac_tool_prefix}file" >&5
+if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MAGIC_CMD" in
+  /*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+  ?:/*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
+  ;;
+  *)
+  ac_save_MAGIC_CMD="$MAGIC_CMD"
+  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="/usr/bin:$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/${ac_tool_prefix}file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
+      if test -n "$file_magic_test_file"; then
+	case "$deplibs_check_method" in
+	"file_magic "*)
+	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    egrep "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  MAGIC_CMD="$ac_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$ac_t""$MAGIC_CMD" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$lt_cv_path_MAGIC_CMD"; then
+  if test -n "$ac_tool_prefix"; then
+    echo $ac_n "checking for file""... $ac_c" 1>&6
+echo "configure:1829: checking for file" >&5
+if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  case "$MAGIC_CMD" in
+  /*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+  ?:/*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
+  ;;
+  *)
+  ac_save_MAGIC_CMD="$MAGIC_CMD"
+  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="/usr/bin:$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/file"
+      if test -n "$file_magic_test_file"; then
+	case "$deplibs_check_method" in
+	"file_magic "*)
+	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    egrep "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  MAGIC_CMD="$ac_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$ac_t""$MAGIC_CMD" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+  else
+    MAGIC_CMD=:
+  fi
+fi
 
-case "$target" in
-NONE) lt_target="$host" ;;
-*) lt_target="$target" ;;
+  fi
+  ;;
 esac
 
+# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1900: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+if test -z "$ac_cv_prog_RANLIB"; then
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1932: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+else
+  RANLIB=":"
+fi
+fi
+
+# Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
+set dummy ${ac_tool_prefix}strip; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1967: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$STRIP"; then
+  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_STRIP="${ac_tool_prefix}strip"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+fi
+fi
+STRIP="$ac_cv_prog_STRIP"
+if test -n "$STRIP"; then
+  echo "$ac_t""$STRIP" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+
+if test -z "$ac_cv_prog_STRIP"; then
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "strip", so it can be a program name with args.
+set dummy strip; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1999: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$STRIP"; then
+  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_STRIP="strip"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_STRIP" && ac_cv_prog_STRIP=":"
+fi
+fi
+STRIP="$ac_cv_prog_STRIP"
+if test -n "$STRIP"; then
+  echo "$ac_t""$STRIP" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
+else
+  STRIP=":"
+fi
+fi
+
+
 # Check for any special flags to pass to ltconfig.
 libtool_flags="--cache-file=$cache_file"
 test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared"
@@ -1521,13 +2046,24 @@ fi
 test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock"
 test x"$silent" = xyes && libtool_flags="$libtool_flags --silent"
 
+# Check whether --with-pic or --without-pic was given.
+if test "${with_pic+set}" = set; then
+  withval="$with_pic"
+  pic_mode="$withval"
+else
+  pic_mode=default
+fi
+
+test x"$pic_mode" = xyes && libtool_flags="$libtool_flags --prefer-pic"
+test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
+
 # Some flags need to be propagated to the compiler or linker for good
 # libtool support.
-case "$lt_target" in
+case "$host" in
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 1530 "configure"' > conftest.$ac_ext
-  if { (eval echo configure:1531: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+  echo '#line 2066 "configure"' > conftest.$ac_ext
+  if { (eval echo configure:2067: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
     case "`/usr/bin/file conftest.o`" in
     *32-bit*)
       LD="${LD-ld} -32"
@@ -1548,19 +2084,27 @@ case "$lt_target" in
   SAVE_CFLAGS="$CFLAGS"
   CFLAGS="$CFLAGS -belf"
   echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6
-echo "configure:1552: checking whether the C compiler needs -belf" >&5
+echo "configure:2088: checking whether the C compiler needs -belf" >&5
 if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
-  cat > conftest.$ac_ext <<EOF
-#line 1557 "configure"
+  
+     ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+     cat > conftest.$ac_ext <<EOF
+#line 2101 "configure"
 #include "confdefs.h"
 
 int main() {
 
 ; return 0; }
 EOF
-if { (eval echo configure:1564: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2108: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   lt_cv_cc_needs_belf=yes
 else
@@ -1570,6 +2114,13 @@ else
   lt_cv_cc_needs_belf=no
 fi
 rm -f conftest*
+     ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
 fi
 
 echo "$ac_t""$lt_cv_cc_needs_belf" 1>&6
@@ -1633,12 +2184,14 @@ rm -f confcache
 
 
 # Actually configure libtool.  ac_aux_dir is where install-sh is found.
-CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \
-LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \
-LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" \
-DLLTOOL="$DLLTOOL" AS="$AS" OBJDUMP="$OBJDUMP" \
+AR="$AR" LTCC="$CC" CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \
+MAGIC_CMD="$MAGIC_CMD" LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \
+LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" STRIP="$STRIP" \
+AS="$AS" DLLTOOL="$DLLTOOL" OBJDUMP="$OBJDUMP" \
+objext="$OBJEXT" exeext="$EXEEXT" reload_flag="$reload_flag" \
+deplibs_check_method="$deplibs_check_method" file_magic_cmd="$file_magic_cmd" \
 ${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \
-$libtool_flags --no-verify $ac_aux_dir/ltmain.sh $lt_target \
+$libtool_flags --no-verify --build="$build" $ac_aux_dir/ltmain.sh $host \
 || { echo "configure: error: libtool configure failed" 1>&2; exit 1; }
 
 # Reload cache, that may have been modified by ltconfig
@@ -1652,7 +2205,7 @@ fi
 
 
 # This can be used to rebuild libtool when needed
-LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh"
+LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh $ac_aux_dir/ltcf-c.sh"
 
 # Always use our own libtool.
 LIBTOOL='$(SHELL) $(top_builddir)/libtool'
@@ -1662,6 +2215,12 @@ LIBTOOL='$(SHELL) $(top_builddir)/libtool'
 exec 5>>./config.log
 
 
+  
+
+  
+	 
+	 
+
 # Check whether --enable-targets or --disable-targets was given.
 if test "${enable_targets+set}" = set; then
   enableval="$enable_targets"
@@ -1682,6 +2241,29 @@ if test "${enable_commonbfdlib+set}" = set; then
 esac
 fi
 
+build_warnings="-W -Wall"
+# Check whether --enable-build-warnings or --disable-build-warnings was given.
+if test "${enable_build_warnings+set}" = set; then
+  enableval="$enable_build_warnings"
+  case "${enableval}" in
+  yes)	;;
+  no)	build_warnings="-w";;
+  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
+        build_warnings="${build_warnings} ${t}";;
+  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
+        build_warnings="${t} ${build_warnings}";;
+  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
+  echo "Setting warning flags = $build_warnings" 6>&1
+fi
+fi
+WARN_CFLAGS=""
+if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then
+    WARN_CFLAGS="${build_warnings}"
+fi
+
+
 
 
 
@@ -1710,7 +2292,7 @@ test "$program_transform_name" = "" && program_transform_name="s,x,x,"
 
 
 echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6
-echo "configure:1714: checking whether to enable maintainer-specific portions of Makefiles" >&5
+echo "configure:2296: checking whether to enable maintainer-specific portions of Makefiles" >&5
     # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
 if test "${enable_maintainer_mode+set}" = set; then
   enableval="$enable_maintainer_mode"
@@ -1732,72 +2314,10 @@ fi
   MAINT=$MAINTAINER_MODE_TRUE
   
 
-echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:1737: checking for Cygwin environment" >&5
-if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1742 "configure"
-#include "confdefs.h"
-
-int main() {
-
-#ifndef __CYGWIN__
-#define __CYGWIN__ __CYGWIN32__
-#endif
-return __CYGWIN__;
-; return 0; }
-EOF
-if { (eval echo configure:1753: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_cygwin=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_cygwin=no
-fi
-rm -f conftest*
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_cygwin" 1>&6
-CYGWIN=
-test "$ac_cv_cygwin" = yes && CYGWIN=yes
-echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:1770: checking for mingw32 environment" >&5
-if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1775 "configure"
-#include "confdefs.h"
-
-int main() {
-return __MINGW32__;
-; return 0; }
-EOF
-if { (eval echo configure:1782: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_mingw32=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_mingw32=no
-fi
-rm -f conftest*
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_mingw32" 1>&6
-MINGW32=
-test "$ac_cv_mingw32" = yes && MINGW32=yes
 
 
 echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1801: checking for executable suffix" >&5
+echo "configure:2321: checking for executable suffix" >&5
 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1807,7 +2327,7 @@ else
   rm -f conftest*
   echo 'int main () { return 0; }' > conftest.$ac_ext
   ac_cv_exeext=
-  if { (eval echo configure:1811: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+  if { (eval echo configure:2331: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
     for file in conftest.*; do
       case $file in
       *.c | *.o | *.obj | *.ilk | *.pdb) ;;
@@ -1833,7 +2353,7 @@ ac_exeext=$EXEEXT
 # Extract the first word of "gcc", so it can be a program name with args.
 set dummy gcc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1837: checking for $ac_word" >&5
+echo "configure:2357: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1863,7 +2383,7 @@ if test -z "$CC"; then
   # Extract the first word of "cc", so it can be a program name with args.
 set dummy cc; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1867: checking for $ac_word" >&5
+echo "configure:2387: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1914,7 +2434,7 @@ fi
       # Extract the first word of "cl", so it can be a program name with args.
 set dummy cl; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1918: checking for $ac_word" >&5
+echo "configure:2438: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -1946,7 +2466,7 @@ fi
 fi
 
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:1950: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:2470: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
 
 ac_ext=c
 # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -1957,12 +2477,12 @@ cross_compiling=$ac_cv_prog_cc_cross
 
 cat > conftest.$ac_ext << EOF
 
-#line 1961 "configure"
+#line 2481 "configure"
 #include "confdefs.h"
 
 main(){return(0);}
 EOF
-if { (eval echo configure:1966: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2486: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   ac_cv_prog_cc_works=yes
   # If we can't run a trivial program, we are probably using a cross compiler.
   if (./conftest; exit) 2>/dev/null; then
@@ -1988,12 +2508,12 @@ if test $ac_cv_prog_cc_works = no; then
   { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
 fi
 echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:1992: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:2512: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
 cross_compiling=$ac_cv_prog_cc_cross
 
 echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:1997: checking whether we are using GNU C" >&5
+echo "configure:2517: checking whether we are using GNU C" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2002,7 +2522,7 @@ else
   yes;
 #endif
 EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2006: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2526: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
   ac_cv_prog_gcc=yes
 else
   ac_cv_prog_gcc=no
@@ -2021,7 +2541,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
 ac_save_CFLAGS="$CFLAGS"
 CFLAGS=
 echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:2025: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:2545: checking whether ${CC-cc} accepts -g" >&5
 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2055,7 +2575,7 @@ fi
 
 ALL_LINGUAS=
 echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
-echo "configure:2059: checking how to run the C preprocessor" >&5
+echo "configure:2579: checking how to run the C preprocessor" >&5
 # On Suns, sometimes $CPP names a directory.
 if test -n "$CPP" && test -d "$CPP"; then
   CPP=
@@ -2070,13 +2590,13 @@ else
   # On the NeXT, cc -E runs the code through the compiler's parser,
   # not just through cpp.
   cat > conftest.$ac_ext <<EOF
-#line 2074 "configure"
+#line 2594 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2080: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2600: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2087,13 +2607,13 @@ else
   rm -rf conftest*
   CPP="${CC-cc} -E -traditional-cpp"
   cat > conftest.$ac_ext <<EOF
-#line 2091 "configure"
+#line 2611 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2097: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2617: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2104,13 +2624,13 @@ else
   rm -rf conftest*
   CPP="${CC-cc} -nologo -E"
   cat > conftest.$ac_ext <<EOF
-#line 2108 "configure"
+#line 2628 "configure"
 #include "confdefs.h"
 #include <assert.h>
 Syntax Error
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2114: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2634: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   :
@@ -2134,13 +2654,43 @@ else
 fi
 echo "$ac_t""$CPP" 1>&6
 
+# Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2661: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+  echo $ac_n "(cached) $ac_c" 1>&6
+else
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
+  ac_dummy="$PATH"
+  for ac_dir in $ac_dummy; do
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$ac_word; then
+      ac_cv_prog_RANLIB="ranlib"
+      break
+    fi
+  done
+  IFS="$ac_save_ifs"
+  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+  echo "$ac_t""$RANLIB" 1>&6
+else
+  echo "$ac_t""no" 1>&6
+fi
+
 echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
-echo "configure:2139: checking for ANSI C header files" >&5
+echo "configure:2689: checking for ANSI C header files" >&5
 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2144 "configure"
+#line 2694 "configure"
 #include "confdefs.h"
 #include <stdlib.h>
 #include <stdarg.h>
@@ -2148,7 +2698,7 @@ else
 #include <float.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2152: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2702: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -2165,7 +2715,7 @@ rm -f conftest*
 if test $ac_cv_header_stdc = yes; then
   # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
 cat > conftest.$ac_ext <<EOF
-#line 2169 "configure"
+#line 2719 "configure"
 #include "confdefs.h"
 #include <string.h>
 EOF
@@ -2183,7 +2733,7 @@ fi
 if test $ac_cv_header_stdc = yes; then
   # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
 cat > conftest.$ac_ext <<EOF
-#line 2187 "configure"
+#line 2737 "configure"
 #include "confdefs.h"
 #include <stdlib.h>
 EOF
@@ -2204,7 +2754,7 @@ if test "$cross_compiling" = yes; then
   :
 else
   cat > conftest.$ac_ext <<EOF
-#line 2208 "configure"
+#line 2758 "configure"
 #include "confdefs.h"
 #include <ctype.h>
 #define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
@@ -2215,7 +2765,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
 exit (0); }
 
 EOF
-if { (eval echo configure:2219: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:2769: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   :
 else
@@ -2239,12 +2789,12 @@ EOF
 fi
 
 echo $ac_n "checking for working const""... $ac_c" 1>&6
-echo "configure:2243: checking for working const" >&5
+echo "configure:2793: checking for working const" >&5
 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2248 "configure"
+#line 2798 "configure"
 #include "confdefs.h"
 
 int main() {
@@ -2293,7 +2843,7 @@ ccp = (char const *const *) p;
 
 ; return 0; }
 EOF
-if { (eval echo configure:2297: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2847: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_c_const=yes
 else
@@ -2314,21 +2864,21 @@ EOF
 fi
 
 echo $ac_n "checking for inline""... $ac_c" 1>&6
-echo "configure:2318: checking for inline" >&5
+echo "configure:2868: checking for inline" >&5
 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   ac_cv_c_inline=no
 for ac_kw in inline __inline__ __inline; do
   cat > conftest.$ac_ext <<EOF
-#line 2325 "configure"
+#line 2875 "configure"
 #include "confdefs.h"
 
 int main() {
 } $ac_kw foo() {
 ; return 0; }
 EOF
-if { (eval echo configure:2332: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2882: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
   rm -rf conftest*
   ac_cv_c_inline=$ac_kw; break
 else
@@ -2354,12 +2904,12 @@ EOF
 esac
 
 echo $ac_n "checking for off_t""... $ac_c" 1>&6
-echo "configure:2358: checking for off_t" >&5
+echo "configure:2908: checking for off_t" >&5
 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2363 "configure"
+#line 2913 "configure"
 #include "confdefs.h"
 #include <sys/types.h>
 #if STDC_HEADERS
@@ -2387,12 +2937,12 @@ EOF
 fi
 
 echo $ac_n "checking for size_t""... $ac_c" 1>&6
-echo "configure:2391: checking for size_t" >&5
+echo "configure:2941: checking for size_t" >&5
 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2396 "configure"
+#line 2946 "configure"
 #include "confdefs.h"
 #include <sys/types.h>
 #if STDC_HEADERS
@@ -2422,19 +2972,19 @@ fi
 # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
 # for constant arguments.  Useless!
 echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
-echo "configure:2426: checking for working alloca.h" >&5
+echo "configure:2976: checking for working alloca.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2431 "configure"
+#line 2981 "configure"
 #include "confdefs.h"
 #include <alloca.h>
 int main() {
 char *p = alloca(2 * sizeof(int));
 ; return 0; }
 EOF
-if { (eval echo configure:2438: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2988: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   ac_cv_header_alloca_h=yes
 else
@@ -2455,12 +3005,12 @@ EOF
 fi
 
 echo $ac_n "checking for alloca""... $ac_c" 1>&6
-echo "configure:2459: checking for alloca" >&5
+echo "configure:3009: checking for alloca" >&5
 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2464 "configure"
+#line 3014 "configure"
 #include "confdefs.h"
 
 #ifdef __GNUC__
@@ -2488,7 +3038,7 @@ int main() {
 char *p = (char *) alloca(1);
 ; return 0; }
 EOF
-if { (eval echo configure:2492: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3042: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   ac_cv_func_alloca_works=yes
 else
@@ -2520,12 +3070,12 @@ EOF
 
 
 echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:2524: checking whether alloca needs Cray hooks" >&5
+echo "configure:3074: checking whether alloca needs Cray hooks" >&5
 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2529 "configure"
+#line 3079 "configure"
 #include "confdefs.h"
 #if defined(CRAY) && ! defined(CRAY2)
 webecray
@@ -2550,12 +3100,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6
 if test $ac_cv_os_cray = yes; then
 for ac_func in _getb67 GETB67 getb67; do
   echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2554: checking for $ac_func" >&5
+echo "configure:3104: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2559 "configure"
+#line 3109 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -2578,7 +3128,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:2582: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3132: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -2605,7 +3155,7 @@ done
 fi
 
 echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:2609: checking stack direction for C alloca" >&5
+echo "configure:3159: checking stack direction for C alloca" >&5
 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2613,7 +3163,7 @@ else
   ac_cv_c_stack_direction=0
 else
   cat > conftest.$ac_ext <<EOF
-#line 2617 "configure"
+#line 3167 "configure"
 #include "confdefs.h"
 find_stack_direction ()
 {
@@ -2632,7 +3182,7 @@ main ()
   exit (find_stack_direction() < 0);
 }
 EOF
-if { (eval echo configure:2636: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3186: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   ac_cv_c_stack_direction=1
 else
@@ -2657,17 +3207,17 @@ for ac_hdr in unistd.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2661: checking for $ac_hdr" >&5
+echo "configure:3211: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2666 "configure"
+#line 3216 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2671: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3221: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -2696,12 +3246,12 @@ done
 for ac_func in getpagesize
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2700: checking for $ac_func" >&5
+echo "configure:3250: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2705 "configure"
+#line 3255 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -2724,7 +3274,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:2728: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3278: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -2749,7 +3299,7 @@ fi
 done
 
 echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:2753: checking for working mmap" >&5
+echo "configure:3303: checking for working mmap" >&5
 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -2757,7 +3307,7 @@ else
   ac_cv_func_mmap_fixed_mapped=no
 else
   cat > conftest.$ac_ext <<EOF
-#line 2761 "configure"
+#line 3311 "configure"
 #include "confdefs.h"
 
 /* Thanks to Mike Haertel and Jim Avera for this test.
@@ -2897,7 +3447,7 @@ main()
 }
 
 EOF
-if { (eval echo configure:2901: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3451: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   ac_cv_func_mmap_fixed_mapped=yes
 else
@@ -2925,17 +3475,17 @@ unistd.h values.h sys/param.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2929: checking for $ac_hdr" >&5
+echo "configure:3479: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2934 "configure"
+#line 3484 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2939: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3489: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -2965,12 +3515,12 @@ done
 __argz_count __argz_stringify __argz_next
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2969: checking for $ac_func" >&5
+echo "configure:3519: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 2974 "configure"
+#line 3524 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -2993,7 +3543,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:2997: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3547: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3022,12 +3572,12 @@ done
      for ac_func in stpcpy
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3026: checking for $ac_func" >&5
+echo "configure:3576: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3031 "configure"
+#line 3581 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3050,7 +3600,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3054: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3604: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3084,19 +3634,19 @@ EOF
 
    if test $ac_cv_header_locale_h = yes; then
     echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
-echo "configure:3088: checking for LC_MESSAGES" >&5
+echo "configure:3638: checking for LC_MESSAGES" >&5
 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3093 "configure"
+#line 3643 "configure"
 #include "confdefs.h"
 #include <locale.h>
 int main() {
 return LC_MESSAGES
 ; return 0; }
 EOF
-if { (eval echo configure:3100: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3650: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   am_cv_val_LC_MESSAGES=yes
 else
@@ -3117,7 +3667,7 @@ EOF
     fi
   fi
    echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
-echo "configure:3121: checking whether NLS is requested" >&5
+echo "configure:3671: checking whether NLS is requested" >&5
         # Check whether --enable-nls or --disable-nls was given.
 if test "${enable_nls+set}" = set; then
   enableval="$enable_nls"
@@ -3137,7 +3687,7 @@ fi
 EOF
 
       echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
-echo "configure:3141: checking whether included gettext is requested" >&5
+echo "configure:3691: checking whether included gettext is requested" >&5
       # Check whether --with-included-gettext or --without-included-gettext was given.
 if test "${with_included_gettext+set}" = set; then
   withval="$with_included_gettext"
@@ -3156,17 +3706,17 @@ fi
 
 	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
-echo "configure:3160: checking for libintl.h" >&5
+echo "configure:3710: checking for libintl.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3165 "configure"
+#line 3715 "configure"
 #include "confdefs.h"
 #include <libintl.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3170: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3720: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3183,19 +3733,19 @@ fi
 if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
   echo "$ac_t""yes" 1>&6
   echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
-echo "configure:3187: checking for gettext in libc" >&5
+echo "configure:3737: checking for gettext in libc" >&5
 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3192 "configure"
+#line 3742 "configure"
 #include "confdefs.h"
 #include <libintl.h>
 int main() {
 return (int) gettext ("")
 ; return 0; }
 EOF
-if { (eval echo configure:3199: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   gt_cv_func_gettext_libc=yes
 else
@@ -3211,7 +3761,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
 
 	   if test "$gt_cv_func_gettext_libc" != "yes"; then
 	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
-echo "configure:3215: checking for bindtextdomain in -lintl" >&5
+echo "configure:3765: checking for bindtextdomain in -lintl" >&5
 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
 if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -3219,7 +3769,7 @@ else
   ac_save_LIBS="$LIBS"
 LIBS="-lintl  $LIBS"
 cat > conftest.$ac_ext <<EOF
-#line 3223 "configure"
+#line 3773 "configure"
 #include "confdefs.h"
 /* Override any gcc2 internal prototype to avoid an error.  */
 /* We use char because int might match the return type of a gcc2
@@ -3230,7 +3780,7 @@ int main() {
 bindtextdomain()
 ; return 0; }
 EOF
-if { (eval echo configure:3234: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3784: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_lib_$ac_lib_var=yes"
 else
@@ -3246,19 +3796,19 @@ fi
 if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
   echo "$ac_t""yes" 1>&6
   echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
-echo "configure:3250: checking for gettext in libintl" >&5
+echo "configure:3800: checking for gettext in libintl" >&5
 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3255 "configure"
+#line 3805 "configure"
 #include "confdefs.h"
 
 int main() {
 return (int) gettext ("")
 ; return 0; }
 EOF
-if { (eval echo configure:3262: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3812: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   gt_cv_func_gettext_libintl=yes
 else
@@ -3286,7 +3836,7 @@ EOF
 	      # Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3290: checking for $ac_word" >&5
+echo "configure:3840: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3320,12 +3870,12 @@ fi
 		for ac_func in dcgettext
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3324: checking for $ac_func" >&5
+echo "configure:3874: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3329 "configure"
+#line 3879 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -3348,7 +3898,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:3352: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3902: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -3375,7 +3925,7 @@ done
 		# Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3379: checking for $ac_word" >&5
+echo "configure:3929: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3411,7 +3961,7 @@ fi
 		# Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3415: checking for $ac_word" >&5
+echo "configure:3965: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3443,7 +3993,7 @@ else
 fi
 
 		cat > conftest.$ac_ext <<EOF
-#line 3447 "configure"
+#line 3997 "configure"
 #include "confdefs.h"
 
 int main() {
@@ -3451,7 +4001,7 @@ extern int _nl_msg_cat_cntr;
 			       return _nl_msg_cat_cntr
 ; return 0; }
 EOF
-if { (eval echo configure:3455: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4005: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   CATOBJEXT=.gmo
 		   DATADIRNAME=share
@@ -3483,7 +4033,7 @@ fi
         # Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3487: checking for $ac_word" >&5
+echo "configure:4037: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3517,7 +4067,7 @@ fi
         # Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3521: checking for $ac_word" >&5
+echo "configure:4071: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3553,7 +4103,7 @@ fi
         # Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3557: checking for $ac_word" >&5
+echo "configure:4107: checking for $ac_word" >&5
 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -3643,7 +4193,7 @@ fi
        LINGUAS=
      else
        echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
-echo "configure:3647: checking for catalogs to be installed" >&5
+echo "configure:4197: checking for catalogs to be installed" >&5
        NEW_LINGUAS=
        for lang in ${LINGUAS=$ALL_LINGUAS}; do
          case "$ALL_LINGUAS" in
@@ -3671,17 +4221,17 @@ echo "configure:3647: checking for catalogs to be installed" >&5
       if test "$CATOBJEXT" = ".cat"; then
 	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
-echo "configure:3675: checking for linux/version.h" >&5
+echo "configure:4225: checking for linux/version.h" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3680 "configure"
+#line 4230 "configure"
 #include "confdefs.h"
 #include <linux/version.h>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3685: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4235: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3758,7 +4308,7 @@ fi
 # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
 # ./install, which can be erroneously created by make from ./install.sh.
 echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:3762: checking for a BSD compatible install" >&5
+echo "configure:4312: checking for a BSD compatible install" >&5
 if test -z "$INSTALL"; then
 if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
@@ -3815,17 +4365,17 @@ for ac_hdr in string.h strings.h stdlib.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3819: checking for $ac_hdr" >&5
+echo "configure:4369: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 3824 "configure"
+#line 4374 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3829: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4379: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -3852,6 +4402,34 @@ fi
 done
 
 
+cgen_maint=no
+cgendir='$(srcdir)/../cgen'
+
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+  enableval="$enable_cgen_maint"
+  case "${enableval}" in
+  yes)	cgen_maint=yes ;;
+  no)	cgen_maint=no ;;
+  *)
+	# argument is cgen install directory (not implemented yet).
+	# Having a `share' directory might be more appropriate for the .scm,
+	# .cpu, etc. files.
+	cgen_maint=yes
+	cgendir=${cgen_maint}/lib/cgen
+	;;
+esac
+fi
+
+
+if test x${cgen_maint} = xyes; then
+  CGEN_MAINT_TRUE=
+  CGEN_MAINT_FALSE='#'
+else
+  CGEN_MAINT_TRUE='#'
+  CGEN_MAINT_FALSE=
+fi
+
 
 using_cgen=no
 
@@ -3916,10 +4494,11 @@ if test x${all_targets} = xfalse ; then
 	bfd_a29k_arch)		ta="$ta a29k-dis.lo" ;;
 	bfd_alliant_arch)	;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
-	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo" ;;
+	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
 	bfd_avr_arch)		ta="$ta avr-dis.lo" ;;
 	bfd_convex_arch)	;;
+	bfd_cris_arch)		ta="$ta cris-dis.lo cris-opc.lo" ;;
 	bfd_d10v_arch)		ta="$ta d10v-dis.lo d10v-opc.lo" ;;
 	bfd_d30v_arch)		ta="$ta d30v-dis.lo d30v-opc.lo" ;;
 	bfd_fr30_arch)          ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;;
@@ -3928,9 +4507,12 @@ if test x${all_targets} = xfalse ; then
 	bfd_hppa_arch)		ta="$ta hppa-dis.lo" ;;
 	bfd_i370_arch)		ta="$ta i370-dis.lo i370-opc.lo" ;;
 	bfd_i386_arch)		ta="$ta i386-dis.lo" ;;
-	bfd_i860_arch)		;;
+	bfd_i860_arch)		ta="$ta i860-dis.lo" ;;
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
+	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_m32r_arch)		ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
+	bfd_m68hc11_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
 	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
@@ -3940,13 +4522,16 @@ if test x${all_targets} = xfalse ; then
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+	bfd_powerpc_64_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;
 	bfd_romp_arch)		;;
 	bfd_rs6000_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
-	bfd_sh_arch)		ta="$ta sh-dis.lo" ;;
+	bfd_sh_arch)
+				ta="$ta sh-dis.lo" ;;
 	bfd_sparc_arch)		ta="$ta sparc-dis.lo sparc-opc.lo" ;;
 	bfd_tahoe_arch)		;;
 	bfd_tic30_arch)		ta="$ta tic30-dis.lo" ;;
+	bfd_tic54x_arch)	ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
 	bfd_tic80_arch)		ta="$ta tic80-dis.lo tic80-opc.lo" ;;
 	bfd_v850_arch)		ta="$ta v850-opc.lo v850-dis.lo" ;;
 	bfd_v850e_arch)		ta="$ta v850-opc.lo v850-dis.lo" ;;
@@ -4158,11 +4743,14 @@ s%@SET_MAKE@%$SET_MAKE%g
 s%@AR@%$AR%g
 s%@RANLIB@%$RANLIB%g
 s%@LN_S@%$LN_S%g
+s%@OBJEXT@%$OBJEXT%g
+s%@EXEEXT@%$EXEEXT%g
+s%@STRIP@%$STRIP%g
 s%@LIBTOOL@%$LIBTOOL%g
+s%@WARN_CFLAGS@%$WARN_CFLAGS%g
 s%@MAINTAINER_MODE_TRUE@%$MAINTAINER_MODE_TRUE%g
 s%@MAINTAINER_MODE_FALSE@%$MAINTAINER_MODE_FALSE%g
 s%@MAINT@%$MAINT%g
-s%@EXEEXT@%$EXEEXT%g
 s%@CPP@%$CPP%g
 s%@ALLOCA@%$ALLOCA%g
 s%@USE_NLS@%$USE_NLS%g
@@ -4186,6 +4774,9 @@ s%@GT_YES@%$GT_YES%g
 s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
 s%@l@%$l%g
 s%@HDEFINES@%$HDEFINES%g
+s%@CGEN_MAINT_TRUE@%$CGEN_MAINT_TRUE%g
+s%@CGEN_MAINT_FALSE@%$CGEN_MAINT_FALSE%g
+s%@cgendir@%$cgendir%g
 s%@WIN32LDFLAGS@%$WIN32LDFLAGS%g
 s%@WIN32LIBADD@%$WIN32LIBADD%g
 s%@archdefs@%$archdefs%g
diff --git a/gnu/usr.bin/binutils/opcodes/configure.in b/gnu/usr.bin/binutils/opcodes/configure.in
index 6ef461f9a49..28f12ede14d 100644
--- a/gnu/usr.bin/binutils/opcodes/configure.in
+++ b/gnu/usr.bin/binutils/opcodes/configure.in
@@ -11,7 +11,7 @@ AC_ISC_POSIX
 # library.  For user convenience, we always use the same version
 # number that BFD is using.
 changequote(,)dnl
-BFD_VERSION=`grep INIT_AUTOMAKE ${srcdir}/../bfd/configure.in | sed -n -e 's/[ 	]//g' -e 's/^.*,\(.*\)).*$/\1/p'`
+BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ 	]*\([^ 	]*\)[ 	]*).*/\1/p' < ${srcdir}/../bfd/configure.in`
 changequote([,])dnl
 
 AM_INIT_AUTOMAKE(opcodes, ${BFD_VERSION})
@@ -43,6 +43,27 @@ AC_ARG_ENABLE(commonbfdlib,
   *)   AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;;
 esac])dnl
 
+build_warnings="-W -Wall"
+AC_ARG_ENABLE(build-warnings,
+[  --enable-build-warnings Enable build-time compiler warnings if gcc is used],
+[case "${enableval}" in
+  yes)	;;
+  no)	build_warnings="-w";;
+  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
+        build_warnings="${build_warnings} ${t}";;
+  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
+        build_warnings="${t} ${build_warnings}";;
+  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
+  echo "Setting warning flags = $build_warnings" 6>&1
+fi])dnl
+WARN_CFLAGS=""
+if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then
+    WARN_CFLAGS="${build_warnings}"
+fi
+AC_SUBST(WARN_CFLAGS)
+
 AM_CONFIG_HEADER(config.h:config.in)
 
 if test -z "$target" ; then
@@ -67,6 +88,24 @@ AC_PROG_INSTALL
 
 AC_CHECK_HEADERS(string.h strings.h stdlib.h)
 
+cgen_maint=no
+cgendir='$(srcdir)/../cgen'
+
+AC_ARG_ENABLE(cgen-maint,
+[  --enable-cgen-maint[=dir]    build cgen generated files],
+[case "${enableval}" in
+  yes)	cgen_maint=yes ;;
+  no)	cgen_maint=no ;;
+  *)
+	# argument is cgen install directory (not implemented yet).
+	# Having a `share' directory might be more appropriate for the .scm,
+	# .cpu, etc. files.
+	cgen_maint=yes
+	cgendir=${cgen_maint}/lib/cgen
+	;;
+esac])dnl
+AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} = xyes)
+AC_SUBST(cgendir)
 
 using_cgen=no
 
@@ -131,10 +170,11 @@ if test x${all_targets} = xfalse ; then
 	bfd_a29k_arch)		ta="$ta a29k-dis.lo" ;;
 	bfd_alliant_arch)	;;
 	bfd_alpha_arch)		ta="$ta alpha-dis.lo alpha-opc.lo" ;;
-	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo" ;;
+	bfd_arc_arch)		ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
 	bfd_arm_arch)		ta="$ta arm-dis.lo" ;;
 	bfd_avr_arch)		ta="$ta avr-dis.lo" ;;
 	bfd_convex_arch)	;;
+	bfd_cris_arch)		ta="$ta cris-dis.lo cris-opc.lo" ;;
 	bfd_d10v_arch)		ta="$ta d10v-dis.lo d10v-opc.lo" ;;
 	bfd_d30v_arch)		ta="$ta d30v-dis.lo d30v-opc.lo" ;;
 	bfd_fr30_arch)          ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;;
@@ -143,9 +183,12 @@ if test x${all_targets} = xfalse ; then
 	bfd_hppa_arch)		ta="$ta hppa-dis.lo" ;;
 	bfd_i370_arch)		ta="$ta i370-dis.lo i370-opc.lo" ;;
 	bfd_i386_arch)		ta="$ta i386-dis.lo" ;;
-	bfd_i860_arch)		;;
+	bfd_i860_arch)		ta="$ta i860-dis.lo" ;;
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
+	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_m32r_arch)		ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
+	bfd_m68hc11_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
 	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
@@ -155,13 +198,16 @@ if test x${all_targets} = xfalse ; then
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+	bfd_powerpc_64_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;
 	bfd_romp_arch)		;;
 	bfd_rs6000_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
-	bfd_sh_arch)		ta="$ta sh-dis.lo" ;;
+	bfd_sh_arch)
+				ta="$ta sh-dis.lo" ;;
 	bfd_sparc_arch)		ta="$ta sparc-dis.lo sparc-opc.lo" ;;
 	bfd_tahoe_arch)		;;
 	bfd_tic30_arch)		ta="$ta tic30-dis.lo" ;;
+	bfd_tic54x_arch)	ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
 	bfd_tic80_arch)		ta="$ta tic80-dis.lo tic80-opc.lo" ;;
 	bfd_v850_arch)		ta="$ta v850-opc.lo v850-dis.lo" ;;
 	bfd_v850e_arch)		ta="$ta v850-opc.lo v850-dis.lo" ;;
diff --git a/gnu/usr.bin/binutils/opcodes/dis-buf.c b/gnu/usr.bin/binutils/opcodes/dis-buf.c
index b828206d43f..46ac2f7724b 100644
--- a/gnu/usr.bin/binutils/opcodes/dis-buf.c
+++ b/gnu/usr.bin/binutils/opcodes/dis-buf.c
@@ -1,5 +1,6 @@
 /* Disassemble from a buffer, for GNU.
-   Copyright (C) 1993, 1994, 1998, 1999 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/gnu/usr.bin/binutils/opcodes/disassemble.c b/gnu/usr.bin/binutils/opcodes/disassemble.c
index 373b6526cb1..3a76d55ce52 100644
--- a/gnu/usr.bin/binutils/opcodes/disassemble.c
+++ b/gnu/usr.bin/binutils/opcodes/disassemble.c
@@ -1,5 +1,5 @@
 /* Select disassembly routine for specified architecture.
-   Copyright (C) 1994, 95, 96, 97, 98, 99, 2000
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
    Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
@@ -25,6 +25,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_arc
 #define ARCH_arm
 #define ARCH_avr
+#define ARCH_cris
 #define ARCH_d10v
 #define ARCH_d30v
 #define ARCH_h8300
@@ -32,10 +33,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_hppa
 #define ARCH_i370
 #define ARCH_i386
+#define ARCH_i860
 #define ARCH_i960
+#define ARCH_ia64
 #define ARCH_fr30
 #define ARCH_m32r
 #define ARCH_m68k
+#define ARCH_m68hc11
+#define ARCH_m68hc12
 #define ARCH_m88k
 #define ARCH_mcore
 #define ARCH_mips
@@ -48,6 +53,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_sh
 #define ARCH_sparc
 #define ARCH_tic30
+#define ARCH_tic54x
 #define ARCH_tic80
 #define ARCH_v850
 #define ARCH_vax
@@ -81,8 +87,7 @@ disassembler (abfd)
 #ifdef ARCH_arc
     case bfd_arch_arc:
       {
-	disassemble = arc_get_disassembler (bfd_get_mach (abfd),
-					    bfd_big_endian (abfd));
+	disassemble = arc_get_disassembler (abfd);
 	break;
       }
 #endif
@@ -99,6 +104,11 @@ disassembler (abfd)
       disassemble = print_insn_avr;
       break;
 #endif
+#ifdef ARCH_cris
+    case bfd_arch_cris:
+      disassemble = cris_get_disassembler (abfd);
+      break;
+#endif
 #ifdef ARCH_d10v
     case bfd_arch_d10v:
       disassemble = print_insn_d10v;
@@ -115,7 +125,7 @@ disassembler (abfd)
 	disassemble = print_insn_h8300h;
       else if (bfd_get_mach(abfd) == bfd_mach_h8300s)
 	disassemble = print_insn_h8300s;
-      else 
+      else
 	disassemble = print_insn_h8300;
       break;
 #endif
@@ -136,17 +146,28 @@ disassembler (abfd)
 #endif
 #ifdef ARCH_i386
     case bfd_arch_i386:
-      if (bfd_get_mach (abfd) == bfd_mach_i386_i386_intel_syntax)
+      if (bfd_get_mach (abfd) == bfd_mach_i386_i386_intel_syntax
+          || bfd_get_mach (abfd) == bfd_mach_x86_64_intel_syntax)
         disassemble = print_insn_i386_intel;
       else
         disassemble = print_insn_i386_att;
       break;
 #endif
+#ifdef ARCH_i860
+    case bfd_arch_i860:
+      disassemble = print_insn_i860;
+      break;
+#endif
 #ifdef ARCH_i960
     case bfd_arch_i960:
       disassemble = print_insn_i960;
       break;
 #endif
+#ifdef ARCH_ia64
+    case bfd_arch_ia64:
+      disassemble = print_insn_ia64;
+      break;
+#endif
 #ifdef ARCH_fr30
     case bfd_arch_fr30:
       disassemble = print_insn_fr30;
@@ -157,6 +178,14 @@ disassembler (abfd)
       disassemble = print_insn_m32r;
       break;
 #endif
+#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
+    case bfd_arch_m68hc11:
+      disassemble = print_insn_m68hc11;
+      break;
+    case bfd_arch_m68hc12:
+      disassemble = print_insn_m68hc12;
+      break;
+#endif
 #ifdef ARCH_m68k
     case bfd_arch_m68k:
       disassemble = print_insn_m68k;
@@ -210,7 +239,10 @@ disassembler (abfd)
 #endif
 #ifdef ARCH_rs6000
     case bfd_arch_rs6000:
-      disassemble = print_insn_rs6000;
+      if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
+	disassemble = print_insn_big_powerpc;
+      else
+	disassemble = print_insn_rs6000;
       break;
 #endif
 #ifdef ARCH_sh
@@ -231,6 +263,11 @@ disassembler (abfd)
       disassemble = print_insn_tic30;
       break;
 #endif
+#ifdef ARCH_tic54x
+    case bfd_arch_tic54x:
+      disassemble = print_insn_tic54x;
+      break;
+#endif
 #ifdef ARCH_tic80
     case bfd_arch_tic80:
       disassemble = print_insn_tic80;
@@ -250,7 +287,7 @@ disassembler (abfd)
     case bfd_arch_z8k:
       if (bfd_get_mach(abfd) == bfd_mach_z8001)
 	disassemble = print_insn_z8001;
-      else 
+      else
 	disassemble = print_insn_z8002;
       break;
 #endif
@@ -267,11 +304,11 @@ disassembler (abfd)
 
 void
 disassembler_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
+     FILE * stream ATTRIBUTE_UNUSED;
 {
 #ifdef ARCH_arm
   print_arm_disassembler_options (stream);
 #endif
-  
+
   return;
 }
diff --git a/gnu/usr.bin/binutils/opcodes/h8300-dis.c b/gnu/usr.bin/binutils/opcodes/h8300-dis.c
index 84f4aadc72d..ab95db42caa 100644
--- a/gnu/usr.bin/binutils/opcodes/h8300-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/h8300-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble h8300 instructions.
-   Copyright (C) 1993, 1998 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1996, 1998, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -23,16 +23,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include "dis-asm.h"
 #include "opintl.h"
 
-
 /* Run through the opcodes and sort them into order to make them easy
-   to disassemble
- */
+   to disassemble.  */
 static void
 bfd_h8_disassemble_init ()
 {
   unsigned int i;
-
-
   struct h8_opcode *p;
 
   for (p = h8_opcodes; p->name; p++)
@@ -41,55 +37,49 @@ bfd_h8_disassemble_init ()
       int n2 = 0;
 
       if ((int) p->data.nib[0] < 16)
-	{
-	  n1 = (int) p->data.nib[0];
-	}
+	n1 = (int) p->data.nib[0];
       else
 	n1 = 0;
+
       if ((int) p->data.nib[1] < 16)
-	{
-	  n2 = (int) p->data.nib[1];
-	}
+	n2 = (int) p->data.nib[1];
       else
 	n2 = 0;
 
       /* Just make sure there are an even number of nibbles in it, and
-	 that the count is the same s the length */
+	 that the count is the same as the length.  */
       for (i = 0; p->data.nib[i] != E; i++)
-	/*EMPTY*/ ;
+	;
+
       if (i & 1)
 	abort ();
+
       p->length = i / 2;
     }
-
 }
 
-
 unsigned int
 bfd_h8_disassemble (addr, info, mode)
      bfd_vma addr;
      disassemble_info *info;
      int mode;
 {
-  /* Find the first entry in the table for this opcode */
+  /* Find the first entry in the table for this opcode.  */
   static CONST char *regnames[] =
     {
       "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
-      "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l"};
-  
+      "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l"
+    };
   static CONST char *wregnames[] =
     {
       "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
       "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"
-      };
-  
+    };
   static CONST char *lregnames[] =
     {
       "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7",
       "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"
-      }
-  ;
-
+    };
   int rs = 0;
   int rd = 0;
   int rdisp = 0;
@@ -97,12 +87,11 @@ bfd_h8_disassemble (addr, info, mode)
   int bit = 0;
   int plen = 0;
   static boolean init = 0;
-  struct h8_opcode *q = h8_opcodes;
+  struct h8_opcode *q;
   char CONST **pregnames = mode != 0 ? lregnames : wregnames;
   int status;
   int l;
-  
-  unsigned char data[20];  
+  unsigned char data[20];
   void *stream = info->stream;
   fprintf_ftype fprintf = info->fprintf_func;
 
@@ -112,111 +101,103 @@ bfd_h8_disassemble (addr, info, mode)
       init = 1;
     }
 
-  status = info->read_memory_func(addr, data, 2, info);
-  if (status != 0) 
+  status = info->read_memory_func (addr, data, 2, info);
+  if (status != 0)
     {
-      info->memory_error_func(status, addr, info);
+      info->memory_error_func (status, addr, info);
       return -1;
     }
-  for (l = 2; status == 0 && l < 10; l+=2)
-    {
-      status = info->read_memory_func(addr+l, data+l, 2, info);
-    }
-  
-  
 
-  /* Find the exact opcode/arg combo */
-  while (q->name)
+  for (l = 2; status == 0 && l < 10; l += 2)
+    status = info->read_memory_func (addr + l, data + l, 2, info);
+
+  /* Find the exact opcode/arg combo.  */
+  for (q = h8_opcodes; q->name; q++)
     {
-      op_type *nib;
+      op_type *nib = q->data.nib;
       unsigned int len = 0;
 
-      nib = q->data.nib;
-      
       while (1)
 	{
 	  op_type looking_for = *nib;
 	  int thisnib = data[len >> 1];
-	  
+
 	  thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
-	  
-	  if (looking_for < 16 && looking_for >=0) 
+
+	  if (looking_for < 16 && looking_for >= 0)
 	    {
-	      
-	      if (looking_for != thisnib) 
+	      if (looking_for != thisnib)
 		goto fail;
 	    }
-	  
-	  else 
+	  else
 	    {
-	      
 	      if ((int) looking_for & (int) B31)
 		{
-		  if (! (((int) thisnib & 0x8) != 0)) 
+		  if (!(((int) thisnib & 0x8) != 0))
 		    goto fail;
+
 		  looking_for = (op_type) ((int) looking_for & ~(int) B31);
 		}
+
 	      if ((int) looking_for & (int) B30)
 		{
-		  if (!(((int) thisnib & 0x8) == 0)) 
+		  if (!(((int) thisnib & 0x8) == 0))
 		    goto fail;
+
 		  looking_for = (op_type) ((int) looking_for & ~(int) B30);
 		}
 
 	      if (looking_for & DBIT)
 		{
-		  if ((looking_for & 5) != (thisnib &5)) goto fail;
+		  /* Exclude adds/subs by looking at bit 0 and 2, and
+                     make sure the operand size, either w or l,
+                     matches by looking at bit 1.  */
+		  if ((looking_for & 7) != (thisnib & 7))
+		    goto fail;
+
 		  abs = (thisnib & 0x8) ? 2 : 1;
-		}		  
-	      
-	      else  if (looking_for & (REG | IND|INC|DEC))
+		}
+	      else if (looking_for & (REG | IND | INC | DEC))
 		{
 		  if (looking_for & SRC)
-		    {
-		      rs = thisnib;
-		    }
+		    rs = thisnib;
 		  else
-		    {
-		      rd = thisnib;
-		    }
+		    rd = thisnib;
 		}
 	      else if (looking_for & L_16)
 		{
 		  abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
 		  plen = 16;
-	      
 		}
-	      else if(looking_for & ABSJMP)
+	      else if (looking_for & ABSJMP)
 		{
-		  abs =
-		    (data[1] << 16)
-		      | (data[2] << 8)
-			| (data[3]);
+		  abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
 		}
-	      else if(looking_for & MEMIND)
+	      else if (looking_for & MEMIND)
 		{
 		  abs = data[1];
 		}
 	      else if (looking_for & L_32)
 		{
 		  int i = len >> 1;
+
 		  abs = (data[i] << 24)
 		    | (data[i + 1] << 16)
-		      | (data[i + 2] << 8)
-			| (data[i+ 3]);
+		    | (data[i + 2] << 8)
+		    | (data[i + 3]);
 
-		  plen =32;
-	      
+		  plen = 32;
 		}
 	      else if (looking_for & L_24)
 		{
 		  int i = len >> 1;
-		  abs = (data[i] << 16) | (data[i + 1] << 8)|  (data[i+2]);
-		  plen =24;
+
+		  abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
+		  plen = 24;
 		}
 	      else if (looking_for & IGNORE)
 		{
-		  
+		  ;
 		}
 	      else if (looking_for & DISPREG)
 		{
@@ -224,7 +205,7 @@ bfd_h8_disassemble (addr, info, mode)
 		}
 	      else if (looking_for & KBIT)
 		{
-		  switch (thisnib) 
+		  switch (thisnib)
 		    {
 		    case 9:
 		      abs = 4;
@@ -241,7 +222,7 @@ bfd_h8_disassemble (addr, info, mode)
 		}
 	      else if (looking_for & L_8)
 		{
-		  plen = 8;		  
+		  plen = 8;
 		  abs = data[len >> 1];
 		}
 	      else if (looking_for & L_3)
@@ -259,19 +240,14 @@ bfd_h8_disassemble (addr, info, mode)
 		}
 	      else if (looking_for == E)
 		{
+		  int i;
 
-		  {
-		    int i;
+		  for (i = 0; i < q->length; i++)
+		    fprintf (stream, "%02x ", data[i]);
+
+		  for (; i < 6; i++)
+		    fprintf (stream, "   ");
 
-		    for (i = 0; i < q->length; i++)
-		      {
-			fprintf (stream, "%02x ", data[i]);
-		      }
-		    for (; i < 6; i++)
-		      {
-			fprintf (stream, "   ");
-		      }
-		  }
 		  fprintf (stream, "%s\t", q->name);
 
 		  /* Gross.  Disgusting.  */
@@ -297,27 +273,26 @@ bfd_h8_disassemble (addr, info, mode)
 		      return q->length;
 		    }
 
-		  /* Fill in the args */
+		  /* Fill in the args.  */
 		  {
 		    op_type *args = q->args.nib;
 		    int hadone = 0;
 
-
 		    while (*args != E)
 		      {
 			int x = *args;
+
 			if (hadone)
 			  fprintf (stream, ",");
 
-
 			if (x & L_3)
 			  {
 			    fprintf (stream, "#0x%x", (unsigned) bit);
 			  }
-			else if (x & (IMM|KBIT|DBIT))
+			else if (x & (IMM | KBIT | DBIT))
 			  {
 			    /* Bletch.  For shal #2,er0 and friends.  */
-			    if (*(args+1) & SRC_IN_DST)
+			    if (*(args + 1) & SRC_IN_DST)
 			      abs = 2;
 
 			    fprintf (stream, "#0x%x", (unsigned) abs);
@@ -325,6 +300,7 @@ bfd_h8_disassemble (addr, info, mode)
 			else if (x & REG)
 			  {
 			    int rn = (x & DST) ? rd : rs;
+
 			    switch (x & SIZE)
 			      {
 			      case L_8:
@@ -337,7 +313,6 @@ bfd_h8_disassemble (addr, info, mode)
 			      case L_32:
 				fprintf (stream, "%s", lregnames[rn]);
 				break;
-		    
 			      }
 			  }
 			else if (x & MACREG)
@@ -352,46 +327,46 @@ bfd_h8_disassemble (addr, info, mode)
 			  {
 			    fprintf (stream, "@-%s", pregnames[rd]);
 			  }
-
 			else if (x & IND)
 			  {
 			    int rn = (x & DST) ? rd : rs;
 			    fprintf (stream, "@%s", pregnames[rn]);
 			  }
-
 			else if (x & ABS8MEM)
 			  {
 			    fprintf (stream, "@0x%x:8", (unsigned) abs);
 			  }
-
-			else if (x & (ABS|ABSJMP))
+			else if (x & (ABS | ABSJMP))
 			  {
 			    fprintf (stream, "@0x%x:%d", (unsigned) abs, plen);
 			  }
-
 			else if (x & MEMIND)
 			  {
 			    fprintf (stream, "@@%d (%x)", abs, abs);
 			  }
-
 			else if (x & PCREL)
 			  {
-			    if (x & L_16) 
+			    if (x & L_16)
 			      {
-				abs  +=2;
-				fprintf (stream, ".%s%d (%x)", (short) abs > 0 ? "+" : "", (short) abs,
-					 addr + (short) abs + 2);
+				abs += 2;
+				fprintf (stream,
+					 ".%s%d (%x)",
+					 (short) abs > 0 ? "+" : "",
+					 (short) abs, addr + (short) abs + 2);
+			      }
+			    else
+			      {
+				fprintf (stream,
+					 ".%s%d (%x)",
+					 (char) abs > 0 ? "+" : "",
+					 (char) abs, addr + (char) abs + 2);
 			      }
-			    else {
-			      fprintf (stream, ".%s%d (%x)", (char) abs > 0 ? "+" : "", (char) abs,
-				       addr + (char) abs + 2);
-			    }
 			  }
 			else if (x & DISP)
 			  {
-			    fprintf (stream, "@(0x%x:%d,%s)", abs,plen, pregnames[rdisp]);
+			    fprintf (stream, "@(0x%x:%d,%s)",
+				     abs, plen, pregnames[rdisp]);
 			  }
-
 			else if (x & CCR)
 			  {
 			    fprintf (stream, "ccr");
@@ -403,56 +378,54 @@ bfd_h8_disassemble (addr, info, mode)
 			else
 			  /* xgettext:c-format */
 			  fprintf (stream, _("Hmmmm %x"), x);
+
 			hadone = 1;
 			args++;
 		      }
 		  }
+
 		  return q->length;
 		}
-
-      
 	      else
-		{
-		  /* xgettext:c-format */
-		  fprintf (stream, _("Don't understand %x \n"), looking_for);
-		}
+		/* xgettext:c-format */
+		fprintf (stream, _("Don't understand %x \n"), looking_for);
 	    }
-	  
+
 	  len++;
 	  nib++;
 	}
-      
+
     fail:
-      q++;
+      ;
     }
 
-  /* Fell of the end */
+  /* Fell off the end.  */
   fprintf (stream, "%02x %02x        .word\tH'%x,H'%x",
 	   data[0], data[1],
 	   data[0], data[1]);
   return 2;
 }
 
-int 
+int
 print_insn_h8300 (addr, info)
-bfd_vma addr; 
-disassemble_info *info;
+     bfd_vma addr;
+     disassemble_info *info;
 {
-  return bfd_h8_disassemble (addr, info , 0);
+  return bfd_h8_disassemble (addr, info, 0);
 }
 
-int 
+int
 print_insn_h8300h (addr, info)
-bfd_vma addr;
-disassemble_info *info;
+     bfd_vma addr;
+     disassemble_info *info;
 {
-  return bfd_h8_disassemble (addr, info , 1);
+  return bfd_h8_disassemble (addr, info, 1);
 }
 
-int 
+int
 print_insn_h8300s (addr, info)
-bfd_vma addr;
-disassemble_info *info;
+     bfd_vma addr;
+     disassemble_info *info;
 {
-  return bfd_h8_disassemble (addr, info , 2);
+  return bfd_h8_disassemble (addr, info, 2);
 }
diff --git a/gnu/usr.bin/binutils/opcodes/h8500-dis.c b/gnu/usr.bin/binutils/opcodes/h8500-dis.c
index d5e15d4fdb6..437207c7bff 100644
--- a/gnu/usr.bin/binutils/opcodes/h8500-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/h8500-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble h8500 instructions.
-   Copyright (C) 1993, 94, 95, 1998 Free Software Foundation, Inc.
+   Copyright 1993, 1998, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -69,8 +69,7 @@ fetch_data (info, addr)
   return 1;
 }
 
-static char *crname[] =
-{"sr", "ccr", "*", "br", "ep", "dp", "*", "tp"};
+static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" };
 
 int
 print_insn_h8500 (addr, info)
@@ -91,21 +90,22 @@ print_insn_h8500 (addr, info)
     /* Error return.  */
     return -1;
 
-if (0)  {
-    static    int one;
-    if (!one ) 
-      {
-	one = 1;
-	for (opcode = h8500_table; opcode->name; opcode++)
-	  {
-	    if ((opcode->bytes[0].contents & 0x8) == 0)
-	      printf("%s\n", opcode->name);
-	  }
-      }
-  }
+  if (0)
+    {
+      static int one;
 
+      if (!one)
+	{
+	  one = 1;
+	  for (opcode = h8500_table; opcode->name; opcode++)
+	    {
+	      if ((opcode->bytes[0].contents & 0x8) == 0)
+		printf ("%s\n", opcode->name);
+	    }
+	}
+    }
 
-  /* Run down the table to find the one which matches */
+  /* Run down the table to find the one which matches.  */
   for (opcode = h8500_table; opcode->name; opcode++)
     {
       int byte;
@@ -119,6 +119,7 @@ if (0)  {
       int qim = 0;
       int i;
       int cr = 0;
+
       for (byte = 0; byte < opcode->length; byte++)
 	{
 	  FETCH_DATA (info, buffer + byte + 1);
@@ -129,7 +130,7 @@ if (0)  {
 	    }
 	  else
 	    {
-	      /* extract any info parts */
+	      /* Extract any info parts.  */
 	      switch (opcode->bytes[byte].insert)
 		{
 		case 0:
@@ -221,8 +222,8 @@ if (0)  {
 		}
 	    }
 	}
-      /* We get here when all the masks have passed so we can output the
-	 operands*/
+      /* We get here when all the masks have passed so we can output
+	 the operands.  */
       FETCH_DATA (info, buffer + opcode->length);
       for (i = 0; i < opcode->length; i++)
 	{
@@ -322,7 +323,8 @@ if (0)  {
 	      func (stream, "#0x%0x:8", imm & 0xff);
 	      break;
 	    case PCREL16:
-	      func (stream, "0x%0x:16", (pcrel + addr + opcode->length) & 0xffff);
+	      func (stream, "0x%0x:16",
+		    (pcrel + addr + opcode->length) & 0xffff);
 	      break;
 	    case PCREL8:
 	      func (stream, "#0x%0x:8",
@@ -337,12 +339,12 @@ if (0)  {
 	    }
 	}
       return opcode->length;
-    next:;
+    next:
+      ;
     }
 
-  /* Couldn't understand anything */
+  /* Couldn't understand anything.  */
   /* xgettext:c-format */
   func (stream, _("%02x\t\t*unknown*"), buffer[0]);
   return 1;
-
 }
diff --git a/gnu/usr.bin/binutils/opcodes/h8500-opc.h b/gnu/usr.bin/binutils/opcodes/h8500-opc.h
index d4949af34d0..62b60397de9 100644
--- a/gnu/usr.bin/binutils/opcodes/h8500-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/h8500-opc.h
@@ -1,3 +1,25 @@
+/* Instruction opcode header for Hitachi 8500.
+
+Copyright 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
 typedef enum
 {
   GR0,GR1,GR2,GR3,GR4,GR5,GR6,GR7,
diff --git a/gnu/usr.bin/binutils/opcodes/hppa-dis.c b/gnu/usr.bin/binutils/opcodes/hppa-dis.c
index 94d05561a79..6d7c54deb9e 100644
--- a/gnu/usr.bin/binutils/opcodes/hppa-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/hppa-dis.c
@@ -1,5 +1,6 @@
 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
-   Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
+   Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001
+   Free Software Foundation, Inc.
 
    Contributed by the Center for Software Science at the
    University of Utah (pa-gdb-bugs@cs.utah.edu).
@@ -42,19 +43,23 @@ static const char *const fp_reg_names[] =
 
 typedef unsigned int CORE_ADDR;
 
-/* Get at various relevent fields of an instruction word. */
+/* Get at various relevent fields of an instruction word.  */
 
 #define MASK_5 0x1f
 #define MASK_10 0x3ff
 #define MASK_11 0x7ff
 #define MASK_14 0x3fff
+#define MASK_16 0xffff
 #define MASK_21 0x1fffff
 
-/* This macro gets bit fields using HP's numbering (MSB = 0) */
+/* These macros get bit fields using HP's numbering (MSB = 0) */
 
 #define GET_FIELD(X, FROM, TO) \
   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
 
+#define GET_BIT(X, WHICH) \
+  GET_FIELD (X, WHICH, WHICH)
+
 /* Some of these have been converted to 2-d arrays because they
    consume less storage this way.  If the maintenance becomes a
    problem, convert them back to const 1-d pointer arrays.  */
@@ -132,13 +137,33 @@ static const char *const read_write_names[] = {",r", ",w"};
 static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
 
 /* For a bunch of different instructions form an index into a 
-   completer name table. */
+   completer name table.  */
 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
 			 GET_FIELD (insn, 18, 18) << 1)
 
 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
 			(GET_FIELD ((insn), 19, 19) ? 8 : 0))
 
+static void fput_reg PARAMS ((unsigned int, disassemble_info *));
+static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *));
+static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *));
+static void fput_creg PARAMS ((unsigned int, disassemble_info *));
+static void fput_const PARAMS ((unsigned int, disassemble_info *));
+static int extract_3 PARAMS ((unsigned int));
+static int extract_5_load PARAMS ((unsigned int));
+static int extract_5_store PARAMS ((unsigned int));
+static unsigned extract_5r_store PARAMS ((unsigned int));
+static unsigned extract_5R_store PARAMS ((unsigned int));
+static unsigned extract_10U_store PARAMS ((unsigned int));
+static unsigned extract_5Q_store PARAMS ((unsigned int));
+static int extract_11 PARAMS ((unsigned int));
+static int extract_14 PARAMS ((unsigned int));
+static int extract_16 PARAMS ((unsigned int));
+static int extract_21 PARAMS ((unsigned int));
+static int extract_12 PARAMS ((unsigned int));
+static int extract_17 PARAMS ((unsigned int));
+static int extract_22 PARAMS ((unsigned int));
+
 /* Utility function to print registers.  Put these first, so gcc's function
    inlining can do its stuff.  */
 
@@ -181,7 +206,7 @@ fput_creg (reg, info)
   (*info->fprintf_func) (info->stream, control_reg[reg]);
 }
 
-/* print constants with sign */
+/* Print constants with sign.  */
 
 static void
 fput_const (num, info)
@@ -195,9 +220,9 @@ fput_const (num, info)
 }
 
 /* Routines to extract various sized constants out of hppa
-   instructions. */
+   instructions.  */
 
-/* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
+/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp.  */
 static int
 extract_3 (word)
      unsigned word;
@@ -212,7 +237,7 @@ extract_5_load (word)
   return low_sign_extend (word >> 16 & MASK_5, 5);
 }
 
-/* extract the immediate field from a st{bhw}s instruction */
+/* Extract the immediate field from a st{bhw}s instruction.  */
 static int
 extract_5_store (word)
      unsigned word;
@@ -220,7 +245,7 @@ extract_5_store (word)
   return low_sign_extend (word & MASK_5, 5);
 }
 
-/* extract the immediate field from a break instruction */
+/* Extract the immediate field from a break instruction.  */
 static unsigned
 extract_5r_store (word)
      unsigned word;
@@ -228,7 +253,7 @@ extract_5r_store (word)
   return (word & MASK_5);
 }
 
-/* extract the immediate field from a {sr}sm instruction */
+/* Extract the immediate field from a {sr}sm instruction.  */
 static unsigned
 extract_5R_store (word)
      unsigned word;
@@ -236,7 +261,7 @@ extract_5R_store (word)
   return (word >> 16 & MASK_5);
 }
 
-/* extract the 10 bit immediate field from a {sr}sm instruction */
+/* Extract the 10 bit immediate field from a {sr}sm instruction.  */
 static unsigned
 extract_10U_store (word)
      unsigned word;
@@ -244,7 +269,7 @@ extract_10U_store (word)
   return (word >> 16 & MASK_10);
 }
 
-/* extract the immediate field from a bb instruction */
+/* Extract the immediate field from a bb instruction.  */
 static unsigned
 extract_5Q_store (word)
      unsigned word;
@@ -252,7 +277,7 @@ extract_5Q_store (word)
   return (word >> 21 & MASK_5);
 }
 
-/* extract an 11 bit immediate field */
+/* Extract an 11 bit immediate field.  */
 static int
 extract_11 (word)
      unsigned word;
@@ -260,7 +285,7 @@ extract_11 (word)
   return low_sign_extend (word & MASK_11, 11);
 }
 
-/* extract a 14 bit immediate field */
+/* Extract a 14 bit immediate field.  */
 static int
 extract_14 (word)
      unsigned word;
@@ -268,7 +293,21 @@ extract_14 (word)
   return low_sign_extend (word & MASK_14, 14);
 }
 
-/* extract a 21 bit constant */
+/* Extract a 16 bit immediate field (PA2.0 wide only).  */
+static int
+extract_16 (word)
+     unsigned word;
+{
+  int m15, m0, m1;
+  m0 = GET_BIT (word, 16);
+  m1 = GET_BIT (word, 17);
+  m15 = GET_BIT (word, 31);
+  word = (word >> 1) & 0x1fff;
+  word = word | (m15 << 15) | ((m15 ^ m0) << 14) | ((m15 ^ m1) << 13);
+  return sign_extend (word, 16);
+}
+
+/* Extract a 21 bit constant.  */
 
 static int
 extract_21 (word)
@@ -290,7 +329,7 @@ extract_21 (word)
   return sign_extend (val, 21) << 11;
 }
 
-/* extract a 12 bit constant from branch instructions */
+/* Extract a 12 bit constant from branch instructions.  */
 
 static int
 extract_12 (word)
@@ -301,8 +340,8 @@ extract_12 (word)
                       (word & 0x1) << 11, 12) << 2;
 }
 
-/* extract a 17 bit constant from branch instructions, returning the
-   19 bit signed value. */
+/* Extract a 17 bit constant from branch instructions, returning the
+   19 bit signed value.  */
 
 static int
 extract_17 (word)
@@ -352,7 +391,10 @@ print_insn_hppa (memaddr, info)
       if ((insn & opcode->mask) == opcode->match)
 	{
 	  register const char *s;
-	  
+#ifndef BFD64
+	  if (opcode->arch == pa20w)
+	    continue;
+#endif
 	  (*info->fprintf_func) (info->stream, "%s", opcode->name);
 
 	  if (!strchr ("cfCY?-+nHNZFIuv", opcode->args[0]))
@@ -473,13 +515,25 @@ print_insn_hppa (memaddr, info)
 			fput_fp_reg (reg, info);
 			break;
 		      }
+
+		    /* 'fe' will not generate a space before the register
+			name.  Normally that is fine.  Except that it
+			causes problems with fstw fe,y(b) which has no FP
+			format completer.  */
+		    case 'E':
+		      fputs_filtered (" ", info);
+
+		    /* FALLTHRU */
+
 		    case 'e':
-		      if (GET_FIELD (insn, 25, 25))
+		      if (GET_FIELD (insn, 30, 30))
 			fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
 		      else
 			fput_fp_reg (GET_FIELD (insn, 11, 15), info);
 		      break;
-
+		    case 'x':
+		      fput_fp_reg (GET_FIELD (insn, 11, 15), info);
+		      break;
 		    }
 		  break;
 
@@ -660,9 +714,9 @@ print_insn_hppa (memaddr, info)
 
 		    case 'J':
 		      {
-			int opcode = GET_FIELD (insn, 0, 5);
+			int opc = GET_FIELD (insn, 0, 5);
 
-			if (opcode == 0x16 || opcode == 0x1e)
+			if (opc == 0x16 || opc == 0x1e)
 			  {
 			    if (GET_FIELD (insn, 29, 29) == 0)
 			      fputs_filtered (",ma ", info);
@@ -676,16 +730,16 @@ print_insn_hppa (memaddr, info)
 
 		    case 'e':
 		      {
-			int opcode = GET_FIELD (insn, 0, 5);
+			int opc = GET_FIELD (insn, 0, 5);
 
-			if (opcode == 0x13 || opcode == 0x1b)
+			if (opc == 0x13 || opc == 0x1b)
 			  {
 			    if (GET_FIELD (insn, 18, 18) == 1)
 			      fputs_filtered (",mb ", info);
 			    else
 			      fputs_filtered (",ma ", info);
 			  }
-			else if (opcode == 0x17 || opcode == 0x1f)
+			else if (opc == 0x17 || opc == 0x1f)
 			  {
 			    if (GET_FIELD (insn, 31, 31) == 1)
 			      fputs_filtered (",ma ", info);
@@ -835,6 +889,11 @@ print_insn_hppa (memaddr, info)
 		case 'k':
 		  fput_const (extract_21 (insn), info);
 		  break;
+		case '<':
+		case 'l':
+		  /* 16-bit long disp., PA2.0 wide only.  */
+		  fput_const (extract_16 (insn), info);
+		  break;
 		case 'n':
 		  if (insn & 0x2)
 		    (*info->fprintf_func) (info->stream, ",n ");
@@ -1041,6 +1100,25 @@ print_insn_hppa (memaddr, info)
 		    break;
 		  }
 
+		case '>':
+		case 'y':
+		  {
+		    /* 16-bit long disp., PA2.0 wide only.  */
+		    int disp = extract_16 (insn);
+		    disp &= ~3;
+		    fput_const (disp, info);
+		    break;
+		  }
+
+		case '&':
+		  {
+		    /* 16-bit long disp., PA2.0 wide only.  */
+		    int disp = extract_16 (insn);
+		    disp &= ~7;
+		    fput_const (disp, info);
+		    break;
+		  }
+
 		/* ?!? FIXME */
 		case '_':
 		case '{':
diff --git a/gnu/usr.bin/binutils/opcodes/i386-dis.c b/gnu/usr.bin/binutils/opcodes/i386-dis.c
index a75d6e316c3..5621d8afadf 100644
--- a/gnu/usr.bin/binutils/opcodes/i386-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/i386-dis.c
@@ -1,5 +1,6 @@
 /* Print i386 instructions for GDB, the GNU debugger.
-   Copyright (C) 1988, 89, 91, 93, 94, 95, 96, 97, 98, 1999
+   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2001
    Free Software Foundation, Inc.
 
 This file is part of GDB.
@@ -22,6 +23,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  * July 1988
  *  modified by John Hassey (hassey@dg-rtp.dg.com)
+ *  x86-64 support added by Jan Hubicka (jh@suse.cz)
  */
 
 /*
@@ -62,9 +64,32 @@ struct dis_private
    when we can.  */
 #define FWAIT_OPCODE (0x9b)
 
+/* Set to 1 for 64bit mode disassembly.  */
+static int mode_64bit;
+
 /* Flags for the prefixes for the current instruction.  See below.  */
 static int prefixes;
 
+/* REX prefix the current instruction.  See below.  */
+static int rex;
+/* Bits of REX we've already used.  */
+static int rex_used;
+#define REX_MODE64	8
+#define REX_EXTX	4
+#define REX_EXTY	2
+#define REX_EXTZ	1
+/* Mark parts used in the REX prefix.  When we are testing for
+   empty prefix (for 8bit register REX extension), just mask it
+   out.  Otherwise test for REX bit is excuse for existence of REX
+   only in case value is nonzero.  */
+#define USED_REX(value)					\
+  {							\
+    if (value)						\
+      rex_used |= (rex & value) ? (value) | 0x40 : 0;	\
+    else						\
+      rex_used |= 0x40;					\
+  }
+
 /* Flags for prefixes which we somehow handled when printing the
    current instruction.  */
 static int used_prefixes;
@@ -121,52 +146,87 @@ fetch_data (info, addr)
 #define XX NULL, 0
 
 #define Eb OP_E, b_mode
-#define indirEb OP_indirE, b_mode
-#define Gb OP_G, b_mode
 #define Ev OP_E, v_mode
 #define Ed OP_E, d_mode
+#define indirEb OP_indirE, b_mode
 #define indirEv OP_indirE, v_mode
 #define Ew OP_E, w_mode
 #define Ma OP_E, v_mode
 #define M OP_E, 0		/* lea */
 #define Mp OP_E, 0		/* 32 or 48 bit memory operand for LDS, LES etc */
+#define Gb OP_G, b_mode
 #define Gv OP_G, v_mode
+#define Gd OP_G, d_mode
 #define Gw OP_G, w_mode
 #define Rd OP_Rd, d_mode
+#define Rm OP_Rd, m_mode
 #define Ib OP_I, b_mode
 #define sIb OP_sI, b_mode	/* sign extened byte */
 #define Iv OP_I, v_mode
+#define Iq OP_I, q_mode
+#define Iv64 OP_I64, v_mode
 #define Iw OP_I, w_mode
 #define Jb OP_J, b_mode
 #define Jv OP_J, v_mode
-#define Cd OP_C, d_mode
-#define Dd OP_D, d_mode
+#define Cm OP_C, m_mode
+#define Dm OP_D, m_mode
 #define Td OP_T, d_mode
 
-#define eAX OP_REG, eAX_reg
-#define eBX OP_REG, eBX_reg
-#define eCX OP_REG, eCX_reg
-#define eDX OP_REG, eDX_reg
-#define eSP OP_REG, eSP_reg
-#define eBP OP_REG, eBP_reg
-#define eSI OP_REG, eSI_reg
-#define eDI OP_REG, eDI_reg
-#define AL OP_REG, al_reg
-#define CL OP_REG, cl_reg
-#define DL OP_REG, dl_reg
-#define BL OP_REG, bl_reg
-#define AH OP_REG, ah_reg
-#define CH OP_REG, ch_reg
-#define DH OP_REG, dh_reg
-#define BH OP_REG, bh_reg
-#define AX OP_REG, ax_reg
-#define DX OP_REG, dx_reg
-#define indirDX OP_REG, indir_dx_reg
+#define RMeAX OP_REG, eAX_reg
+#define RMeBX OP_REG, eBX_reg
+#define RMeCX OP_REG, eCX_reg
+#define RMeDX OP_REG, eDX_reg
+#define RMeSP OP_REG, eSP_reg
+#define RMeBP OP_REG, eBP_reg
+#define RMeSI OP_REG, eSI_reg
+#define RMeDI OP_REG, eDI_reg
+#define RMrAX OP_REG, rAX_reg
+#define RMrBX OP_REG, rBX_reg
+#define RMrCX OP_REG, rCX_reg
+#define RMrDX OP_REG, rDX_reg
+#define RMrSP OP_REG, rSP_reg
+#define RMrBP OP_REG, rBP_reg
+#define RMrSI OP_REG, rSI_reg
+#define RMrDI OP_REG, rDI_reg
+#define RMAL OP_REG, al_reg
+#define RMAL OP_REG, al_reg
+#define RMCL OP_REG, cl_reg
+#define RMDL OP_REG, dl_reg
+#define RMBL OP_REG, bl_reg
+#define RMAH OP_REG, ah_reg
+#define RMCH OP_REG, ch_reg
+#define RMDH OP_REG, dh_reg
+#define RMBH OP_REG, bh_reg
+#define RMAX OP_REG, ax_reg
+#define RMDX OP_REG, dx_reg
+
+#define eAX OP_IMREG, eAX_reg
+#define eBX OP_IMREG, eBX_reg
+#define eCX OP_IMREG, eCX_reg
+#define eDX OP_IMREG, eDX_reg
+#define eSP OP_IMREG, eSP_reg
+#define eBP OP_IMREG, eBP_reg
+#define eSI OP_IMREG, eSI_reg
+#define eDI OP_IMREG, eDI_reg
+#define AL OP_IMREG, al_reg
+#define AL OP_IMREG, al_reg
+#define CL OP_IMREG, cl_reg
+#define DL OP_IMREG, dl_reg
+#define BL OP_IMREG, bl_reg
+#define AH OP_IMREG, ah_reg
+#define CH OP_IMREG, ch_reg
+#define DH OP_IMREG, dh_reg
+#define BH OP_IMREG, bh_reg
+#define AX OP_IMREG, ax_reg
+#define DX OP_IMREG, dx_reg
+#define indirDX OP_IMREG, indir_dx_reg
 
 #define Sw OP_SEG, w_mode
 #define Ap OP_DIR, 0
 #define Ob OP_OFF, b_mode
+#define Ob64 OP_OFF64, b_mode
 #define Ov OP_OFF, v_mode
+#define Ov64 OP_OFF64, v_mode
 #define Xb OP_DSreg, eSI_reg
 #define Xv OP_DSreg, eSI_reg
 #define Yb OP_ESreg, eDI_reg
@@ -185,10 +245,14 @@ fetch_data (info, addr)
 #define EM OP_EM, v_mode
 #define EX OP_EX, v_mode
 #define MS OP_MS, v_mode
+#define XS OP_XS, v_mode
 #define None OP_E, 0
 #define OPSUF OP_3DNowSuffix, 0
 #define OPSIMD OP_SIMD_Suffix, 0
 
+#define cond_jump_flag NULL, cond_jump_mode
+#define loop_jcxz_flag NULL, loop_jcxz_mode
+
 /* bits in sizeflag */
 #if 0 /* leave undefined until someone adds the extra flag to objdump */
 #define SUFFIX_ALWAYS 4
@@ -201,6 +265,11 @@ typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag));
 static void OP_E PARAMS ((int, int));
 static void OP_G PARAMS ((int, int));
 static void OP_I PARAMS ((int, int));
+static void OP_I64 PARAMS ((int, int));
+static void OP_OFF PARAMS ((int, int));
+static void OP_REG PARAMS ((int, int));
+static void OP_IMREG PARAMS ((int, int));
+static void OP_OFF64 PARAMS ((int, int));
 static void OP_indirE PARAMS ((int, int));
 static void OP_sI PARAMS ((int, int));
 static void OP_REG PARAMS ((int, int));
@@ -221,26 +290,33 @@ static void OP_XMM PARAMS ((int, int));
 static void OP_EM PARAMS ((int, int));
 static void OP_EX PARAMS ((int, int));
 static void OP_MS PARAMS ((int, int));
+static void OP_XS PARAMS ((int, int));
 static void OP_3DNowSuffix PARAMS ((int, int));
 static void OP_SIMD_Suffix PARAMS ((int, int));
 static void SIMD_Fixup PARAMS ((int, int));
 
 static void append_seg PARAMS ((void));
-static void set_op PARAMS ((unsigned int op));
+static void set_op PARAMS ((unsigned int op, int));
 static void putop PARAMS ((const char *template, int sizeflag));
 static void dofloat PARAMS ((int sizeflag));
 static int get16 PARAMS ((void));
-static int get32 PARAMS ((void));
+static bfd_vma get64 PARAMS ((void));
+static bfd_signed_vma get32 PARAMS ((void));
+static bfd_signed_vma get32s PARAMS ((void));
 static void ckprefix PARAMS ((void));
 static const char *prefix_name PARAMS ((int, int));
 static void ptr_reg PARAMS ((int, int));
 static void BadOp PARAMS ((void));
 
-#define b_mode 1
-#define v_mode 2
-#define w_mode 3
-#define d_mode 4
-#define x_mode 5
+#define b_mode 1  /* byte operand */
+#define v_mode 2  /* operand size depends on prefixes */
+#define w_mode 3  /* word operand */
+#define d_mode 4  /* double word operand  */
+#define q_mode 5  /* quad word operand */
+#define x_mode 6
+#define m_mode 7  /* d_mode in 32bit, q_mode in 64bit mode.  */
+#define cond_jump_mode 8
+#define loop_jcxz_mode 9
 
 #define es_reg 100
 #define cs_reg 101
@@ -276,6 +352,15 @@ static void BadOp PARAMS ((void));
 #define si_reg 130
 #define di_reg 131
 
+#define rAX_reg 132
+#define rCX_reg 133
+#define rDX_reg 134
+#define rBX_reg 135
+#define rSP_reg 136
+#define rBP_reg 137
+#define rSI_reg 138
+#define rDI_reg 139
+
 #define indir_dx_reg 150
 
 #define USE_GROUPS 1
@@ -320,6 +405,18 @@ static void BadOp PARAMS ((void));
 #define PREGRP12 NULL, NULL, 12, NULL, USE_PREFIX_USER_TABLE, NULL, 0
 #define PREGRP13 NULL, NULL, 13, NULL, USE_PREFIX_USER_TABLE, NULL, 0
 #define PREGRP14 NULL, NULL, 14, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP15 NULL, NULL, 15, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP16 NULL, NULL, 16, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP17 NULL, NULL, 17, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP18 NULL, NULL, 18, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP19 NULL, NULL, 19, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP20 NULL, NULL, 20, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP21 NULL, NULL, 21, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP22 NULL, NULL, 22, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP23 NULL, NULL, 23, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP24 NULL, NULL, 24, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP25 NULL, NULL, 25, NULL, USE_PREFIX_USER_TABLE, NULL, 0
+#define PREGRP26 NULL, NULL, 26, NULL, USE_PREFIX_USER_TABLE, NULL, 0
 
 #define FLOATCODE 50
 #define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
@@ -338,14 +435,21 @@ struct dis386 {
    'A' => print 'b' if no register operands or suffix_always is true
    'B' => print 'b' if suffix_always is true
    'E' => print 'e' if 32-bit form of jcxz
+   'F' => print 'w' or 'l' depending on address size prefix (loop insns)
    'L' => print 'l' if suffix_always is true
    'N' => print 'n' if instruction has no wait "prefix"
-   'P' => print 'w' or 'l' if instruction has an operand size prefix,
+   'O' => print 'd', or 'o'
+   'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
                               or suffix_always is true
-   'Q' => print 'w' or 'l' if no register operands or suffix_always is true
-   'R' => print 'w' or 'l' ("wd" or "dq" in intel mode)
-   'S' => print 'w' or 'l' if suffix_always is true
+	  print 'q' if rex prefix is present.
+   'I' => print 'q' in 64bit mode and behave as 'P' otherwise
+   'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always is true
+   'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
+   'S' => print 'w', 'l' or 'q' if suffix_always is true
+   'T' => print 'q' in 64bit mode and behave as 'I' otherwise
+   'X' => print 's', 'd' depending on data16 prefix (for XMM)
    'W' => print 'b' or 'w' ("w" or "de" in intel mode)
+   'Y' => 'q' if instruction has an REX 64bit overwrite prefix
 */
 
 static const struct dis386 dis386_att[] = {
@@ -356,8 +460,8 @@ static const struct dis386 dis386_att[] = {
   { "addS",	Gv, Ev, XX },
   { "addB",	AL, Ib, XX },
   { "addS",	eAX, Iv, XX },
-  { "pushP",	es, XX, XX },
-  { "popP",	es, XX, XX },
+  { "pushI",	es, XX, XX },
+  { "popI",	es, XX, XX },
   /* 08 */
   { "orB",	Eb, Gb, XX },
   { "orS",	Ev, Gv, XX },
@@ -365,7 +469,7 @@ static const struct dis386 dis386_att[] = {
   { "orS",	Gv, Ev, XX },
   { "orB",	AL, Ib, XX },
   { "orS",	eAX, Iv, XX },
-  { "pushP",	cs, XX, XX },
+  { "pushI",	cs, XX, XX },
   { "(bad)",	XX, XX, XX },	/* 0x0f extended opcode escape */
   /* 10 */
   { "adcB",	Eb, Gb, XX },
@@ -374,8 +478,8 @@ static const struct dis386 dis386_att[] = {
   { "adcS",	Gv, Ev, XX },
   { "adcB",	AL, Ib, XX },
   { "adcS",	eAX, Iv, XX },
-  { "pushP",	ss, XX, XX },
-  { "popP",	ss, XX, XX },
+  { "pushI",	ss, XX, XX },
+  { "popI",	ss, XX, XX },
   /* 18 */
   { "sbbB",	Eb, Gb, XX },
   { "sbbS",	Ev, Gv, XX },
@@ -383,8 +487,8 @@ static const struct dis386 dis386_att[] = {
   { "sbbS",	Gv, Ev, XX },
   { "sbbB",	AL, Ib, XX },
   { "sbbS",	eAX, Iv, XX },
-  { "pushP",	ds, XX, XX },
-  { "popP",	ds, XX, XX },
+  { "pushI",	ds, XX, XX },
+  { "popI",	ds, XX, XX },
   /* 20 */
   { "andB",	Eb, Gb, XX },
   { "andS",	Ev, Gv, XX },
@@ -422,41 +526,41 @@ static const struct dis386 dis386_att[] = {
   { "(bad)",	XX, XX, XX },			/* SEG DS prefix */
   { "aas",	XX, XX, XX },
   /* 40 */
-  { "incS",	eAX, XX, XX },
-  { "incS",	eCX, XX, XX },
-  { "incS",	eDX, XX, XX },
-  { "incS",	eBX, XX, XX },
-  { "incS",	eSP, XX, XX },
-  { "incS",	eBP, XX, XX },
-  { "incS",	eSI, XX, XX },
-  { "incS",	eDI, XX, XX },
+  { "incS",	RMeAX, XX, XX },
+  { "incS",	RMeCX, XX, XX },
+  { "incS",	RMeDX, XX, XX },
+  { "incS",	RMeBX, XX, XX },
+  { "incS",	RMeSP, XX, XX },
+  { "incS",	RMeBP, XX, XX },
+  { "incS",	RMeSI, XX, XX },
+  { "incS",	RMeDI, XX, XX },
   /* 48 */
-  { "decS",	eAX, XX, XX },
-  { "decS",	eCX, XX, XX },
-  { "decS",	eDX, XX, XX },
-  { "decS",	eBX, XX, XX },
-  { "decS",	eSP, XX, XX },
-  { "decS",	eBP, XX, XX },
-  { "decS",	eSI, XX, XX },
-  { "decS",	eDI, XX, XX },
+  { "decS",	RMeAX, XX, XX },
+  { "decS",	RMeCX, XX, XX },
+  { "decS",	RMeDX, XX, XX },
+  { "decS",	RMeBX, XX, XX },
+  { "decS",	RMeSP, XX, XX },
+  { "decS",	RMeBP, XX, XX },
+  { "decS",	RMeSI, XX, XX },
+  { "decS",	RMeDI, XX, XX },
   /* 50 */
-  { "pushS",	eAX, XX, XX },
-  { "pushS",	eCX, XX, XX },
-  { "pushS",	eDX, XX, XX },
-  { "pushS",	eBX, XX, XX },
-  { "pushS",	eSP, XX, XX },
-  { "pushS",	eBP, XX, XX },
-  { "pushS",	eSI, XX, XX },
-  { "pushS",	eDI, XX, XX },
+  { "pushS",	RMeAX, XX, XX },
+  { "pushS",	RMeCX, XX, XX },
+  { "pushS",	RMeDX, XX, XX },
+  { "pushS",	RMeBX, XX, XX },
+  { "pushS",	RMeSP, XX, XX },
+  { "pushS",	RMeBP, XX, XX },
+  { "pushS",	RMeSI, XX, XX },
+  { "pushS",	RMeDI, XX, XX },
   /* 58 */
-  { "popS",	eAX, XX, XX },
-  { "popS",	eCX, XX, XX },
-  { "popS",	eDX, XX, XX },
-  { "popS",	eBX, XX, XX },
-  { "popS",	eSP, XX, XX },
-  { "popS",	eBP, XX, XX },
-  { "popS",	eSI, XX, XX },
-  { "popS",	eDI, XX, XX },
+  { "popS",	RMeAX, XX, XX },
+  { "popS",	RMeCX, XX, XX },
+  { "popS",	RMeDX, XX, XX },
+  { "popS",	RMeBX, XX, XX },
+  { "popS",	RMeSP, XX, XX },
+  { "popS",	RMeBP, XX, XX },
+  { "popS",	RMeSI, XX, XX },
+  { "popS",	RMeDI, XX, XX },
   /* 60 */
   { "pushaP",	XX, XX, XX },
   { "popaP",	XX, XX, XX },
@@ -467,32 +571,32 @@ static const struct dis386 dis386_att[] = {
   { "(bad)",	XX, XX, XX },			/* op size prefix */
   { "(bad)",	XX, XX, XX },			/* adr size prefix */
   /* 68 */
-  { "pushP",	Iv, XX, XX },		/* 386 book wrong */
+  { "pushI",	Iv, XX, XX },		/* 386 book wrong */
   { "imulS",	Gv, Ev, Iv },
-  { "pushP",	sIb, XX, XX },	/* push of byte really pushes 2 or 4 bytes */
+  { "pushI",	sIb, XX, XX },	/* push of byte really pushes 2 or 4 bytes */
   { "imulS",	Gv, Ev, sIb },
   { "insb",	Yb, indirDX, XX },
   { "insR",	Yv, indirDX, XX },
   { "outsb",	indirDX, Xb, XX },
   { "outsR",	indirDX, Xv, XX },
   /* 70 */
-  { "jo",	Jb, XX, XX },
-  { "jno",	Jb, XX, XX },
-  { "jb",	Jb, XX, XX },
-  { "jae",	Jb, XX, XX },
-  { "je",	Jb, XX, XX },
-  { "jne",	Jb, XX, XX },
-  { "jbe",	Jb, XX, XX },
-  { "ja",	Jb, XX, XX },
+  { "jo",	Jb, cond_jump_flag, XX },
+  { "jno",	Jb, cond_jump_flag, XX },
+  { "jb",	Jb, cond_jump_flag, XX },
+  { "jae",	Jb, cond_jump_flag, XX },
+  { "je",	Jb, cond_jump_flag, XX },
+  { "jne",	Jb, cond_jump_flag, XX },
+  { "jbe",	Jb, cond_jump_flag, XX },
+  { "ja",	Jb, cond_jump_flag, XX },
   /* 78 */
-  { "js",	Jb, XX, XX },
-  { "jns",	Jb, XX, XX },
-  { "jp",	Jb, XX, XX },
-  { "jnp",	Jb, XX, XX },
-  { "jl",	Jb, XX, XX },
-  { "jge",	Jb, XX, XX },
-  { "jle",	Jb, XX, XX },
-  { "jg",	Jb, XX, XX },
+  { "js",	Jb, cond_jump_flag, XX },
+  { "jns",	Jb, cond_jump_flag, XX },
+  { "jp",	Jb, cond_jump_flag, XX },
+  { "jnp",	Jb, cond_jump_flag, XX },
+  { "jl",	Jb, cond_jump_flag, XX },
+  { "jge",	Jb, cond_jump_flag, XX },
+  { "jle",	Jb, cond_jump_flag, XX },
+  { "jg",	Jb, cond_jump_flag, XX },
   /* 80 */
   { GRP1b },
   { GRP1S },
@@ -510,23 +614,24 @@ static const struct dis386 dis386_att[] = {
   { "movQ",	Ev, Sw, XX },
   { "leaS",	Gv, M, XX },
   { "movQ",	Sw, Ev, XX },
-  { "popQ",	Ev, XX, XX },
+  { "popT",	Ev, XX, XX },
   /* 90 */
   { "nop",	XX, XX, XX },
-  { "xchgS",	eCX, eAX, XX },
-  { "xchgS",	eDX, eAX, XX },
-  { "xchgS",	eBX, eAX, XX },
-  { "xchgS",	eSP, eAX, XX },
-  { "xchgS",	eBP, eAX, XX },
-  { "xchgS",	eSI, eAX, XX },
-  { "xchgS",	eDI, eAX, XX },
+  /* FIXME: NOP with REPz prefix is called PAUSE.  */
+  { "xchgS",	RMeCX, eAX, XX },
+  { "xchgS",	RMeDX, eAX, XX },
+  { "xchgS",	RMeBX, eAX, XX },
+  { "xchgS",	RMeSP, eAX, XX },
+  { "xchgS",	RMeBP, eAX, XX },
+  { "xchgS",	RMeSI, eAX, XX },
+  { "xchgS",	RMeDI, eAX, XX },
   /* 98 */
   { "cWtR",	XX, XX, XX },
-  { "cRtd",	XX, XX, XX },
-  { "lcallP",	Ap, XX, XX },
+  { "cRtO",	XX, XX, XX },
+  { "lcallI",	Ap, XX, XX },
   { "(bad)",	XX, XX, XX },		/* fwait */
-  { "pushfP",	XX, XX, XX },
-  { "popfP",	XX, XX, XX },
+  { "pushfI",	XX, XX, XX },
+  { "popfI",	XX, XX, XX },
   { "sahf",	XX, XX, XX },
   { "lahf",	XX, XX, XX },
   /* a0 */
@@ -548,35 +653,35 @@ static const struct dis386 dis386_att[] = {
   { "scasB",	AL, Yb, XX },
   { "scasS",	eAX, Yv, XX },
   /* b0 */
-  { "movB",	AL, Ib, XX },
-  { "movB",	CL, Ib, XX },
-  { "movB",	DL, Ib, XX },
-  { "movB",	BL, Ib, XX },
-  { "movB",	AH, Ib, XX },
-  { "movB",	CH, Ib, XX },
-  { "movB",	DH, Ib, XX },
-  { "movB",	BH, Ib, XX },
+  { "movB",	RMAL, Ib, XX },
+  { "movB",	RMCL, Ib, XX },
+  { "movB",	RMDL, Ib, XX },
+  { "movB",	RMBL, Ib, XX },
+  { "movB",	RMAH, Ib, XX },
+  { "movB",	RMCH, Ib, XX },
+  { "movB",	RMDH, Ib, XX },
+  { "movB",	RMBH, Ib, XX },
   /* b8 */
-  { "movS",	eAX, Iv, XX },
-  { "movS",	eCX, Iv, XX },
-  { "movS",	eDX, Iv, XX },
-  { "movS",	eBX, Iv, XX },
-  { "movS",	eSP, Iv, XX },
-  { "movS",	eBP, Iv, XX },
-  { "movS",	eSI, Iv, XX },
-  { "movS",	eDI, Iv, XX },
+  { "movS",	RMeAX, Iv, XX },
+  { "movS",	RMeCX, Iv, XX },
+  { "movS",	RMeDX, Iv, XX },
+  { "movS",	RMeBX, Iv, XX },
+  { "movS",	RMeSP, Iv, XX },
+  { "movS",	RMeBP, Iv, XX },
+  { "movS",	RMeSI, Iv, XX },
+  { "movS",	RMeDI, Iv, XX },
   /* c0 */
   { GRP2b },
   { GRP2S },
-  { "retP",	Iw, XX, XX },
-  { "retP",	XX, XX, XX },
+  { "retI",	Iw, XX, XX },
+  { "retI",	XX, XX, XX },
   { "lesS",	Gv, Mp, XX },
   { "ldsS",	Gv, Mp, XX },
   { "movA",	Eb, Ib, XX },
   { "movQ",	Ev, Iv, XX },
   /* c8 */
-  { "enterP",	Iw, Ib, XX },
-  { "leaveP",	XX, XX, XX },
+  { "enterI",	Iw, Ib, XX },
+  { "leaveI",	XX, XX, XX },
   { "lretP",	Iw, XX, XX },
   { "lretP",	XX, XX, XX },
   { "int3",	XX, XX, XX },
@@ -602,18 +707,18 @@ static const struct dis386 dis386_att[] = {
   { FLOAT },
   { FLOAT },
   /* e0 */
-  { "loopne",	Jb, XX, XX },
-  { "loope",	Jb, XX, XX },
-  { "loop",	Jb, XX, XX },
-  { "jEcxz",	Jb, XX, XX },
+  { "loopneF",	Jb, loop_jcxz_flag, XX },
+  { "loopeF",	Jb, loop_jcxz_flag, XX },
+  { "loopF",	Jb, loop_jcxz_flag, XX },
+  { "jEcxz",	Jb, loop_jcxz_flag, XX },
   { "inB",	AL, Ib, XX },
   { "inS",	eAX, Ib, XX },
   { "outB",	Ib, AL, XX },
   { "outS",	Ib, eAX, XX },
   /* e8 */
-  { "callP",	Jv, XX, XX },
-  { "jmpP",	Jv, XX, XX },
-  { "ljmpP",	Ap, XX, XX },
+  { "callI",	Jv, XX, XX },
+  { "jmpI",	Jv, XX, XX },
+  { "ljmpI",	Ap, XX, XX },
   { "jmp",	Jb, XX, XX },
   { "inB",	AL, indirDX, XX },
   { "inS",	eAX, indirDX, XX },
@@ -713,41 +818,41 @@ static const struct dis386 dis386_intel[] = {
   { "(bad)",	XX, XX, XX },			/* SEG DS prefix */
   { "aas",	XX, XX, XX },
   /* 40 */
-  { "inc",	eAX, XX, XX },
-  { "inc",	eCX, XX, XX },
-  { "inc",	eDX, XX, XX },
-  { "inc",	eBX, XX, XX },
-  { "inc",	eSP, XX, XX },
-  { "inc",	eBP, XX, XX },
-  { "inc",	eSI, XX, XX },
-  { "inc",	eDI, XX, XX },
+  { "inc",	RMeAX, XX, XX },
+  { "inc",	RMeCX, XX, XX },
+  { "inc",	RMeDX, XX, XX },
+  { "inc",	RMeBX, XX, XX },
+  { "inc",	RMeSP, XX, XX },
+  { "inc",	RMeBP, XX, XX },
+  { "inc",	RMeSI, XX, XX },
+  { "inc",	RMeDI, XX, XX },
   /* 48 */
-  { "dec",	eAX, XX, XX },
-  { "dec",	eCX, XX, XX },
-  { "dec",	eDX, XX, XX },
-  { "dec",	eBX, XX, XX },
-  { "dec",	eSP, XX, XX },
-  { "dec",	eBP, XX, XX },
-  { "dec",	eSI, XX, XX },
-  { "dec",	eDI, XX, XX },
+  { "dec",	RMeAX, XX, XX },
+  { "dec",	RMeCX, XX, XX },
+  { "dec",	RMeDX, XX, XX },
+  { "dec",	RMeBX, XX, XX },
+  { "dec",	RMeSP, XX, XX },
+  { "dec",	RMeBP, XX, XX },
+  { "dec",	RMeSI, XX, XX },
+  { "dec",	RMeDI, XX, XX },
   /* 50 */
-  { "push",	eAX, XX, XX },
-  { "push",	eCX, XX, XX },
-  { "push",	eDX, XX, XX },
-  { "push",	eBX, XX, XX },
-  { "push",	eSP, XX, XX },
-  { "push",	eBP, XX, XX },
-  { "push",	eSI, XX, XX },
-  { "push",	eDI, XX, XX },
+  { "push",	RMeAX, XX, XX },
+  { "push",	RMeCX, XX, XX },
+  { "push",	RMeDX, XX, XX },
+  { "push",	RMeBX, XX, XX },
+  { "push",	RMeSP, XX, XX },
+  { "push",	RMeBP, XX, XX },
+  { "push",	RMeSI, XX, XX },
+  { "push",	RMeDI, XX, XX },
   /* 58 */
-  { "pop",	eAX, XX, XX },
-  { "pop",	eCX, XX, XX },
-  { "pop",	eDX, XX, XX },
-  { "pop",	eBX, XX, XX },
-  { "pop",	eSP, XX, XX },
-  { "pop",	eBP, XX, XX },
-  { "pop",	eSI, XX, XX },
-  { "pop",	eDI, XX, XX },
+  { "pop",	RMeAX, XX, XX },
+  { "pop",	RMeCX, XX, XX },
+  { "pop",	RMeDX, XX, XX },
+  { "pop",	RMeBX, XX, XX },
+  { "pop",	RMeSP, XX, XX },
+  { "pop",	RMeBP, XX, XX },
+  { "pop",	RMeSI, XX, XX },
+  { "pop",	RMeDI, XX, XX },
   /* 60 */
   { "pusha",	XX, XX, XX },
   { "popa",	XX, XX, XX },
@@ -804,13 +909,14 @@ static const struct dis386 dis386_intel[] = {
   { "pop",	Ev, XX, XX },
   /* 90 */
   { "nop",	XX, XX, XX },
-  { "xchg",	eCX, eAX, XX },
-  { "xchg",	eDX, eAX, XX },
-  { "xchg",	eBX, eAX, XX },
-  { "xchg",	eSP, eAX, XX },
-  { "xchg",	eBP, eAX, XX },
-  { "xchg",	eSI, eAX, XX },
-  { "xchg",	eDI, eAX, XX },
+  /* FIXME: NOP with REPz prefix is called PAUSE.  */
+  { "xchg",	RMeCX, eAX, XX },
+  { "xchg",	RMeDX, eAX, XX },
+  { "xchg",	RMeBX, eAX, XX },
+  { "xchg",	RMeSP, eAX, XX },
+  { "xchg",	RMeBP, eAX, XX },
+  { "xchg",	RMeSI, eAX, XX },
+  { "xchg",	RMeDI, eAX, XX },
   /* 98 */
   { "cW",	XX, XX, XX },		/* cwde and cbw */
   { "cR",	XX, XX, XX },		/* cdq and cwd */
@@ -839,23 +945,23 @@ static const struct dis386 dis386_intel[] = {
   { "scas",	AL, Yb, XX },
   { "scas",	eAX, Yv, XX },
   /* b0 */
-  { "mov",	AL, Ib, XX },
-  { "mov",	CL, Ib, XX },
-  { "mov",	DL, Ib, XX },
-  { "mov",	BL, Ib, XX },
-  { "mov",	AH, Ib, XX },
-  { "mov",	CH, Ib, XX },
-  { "mov",	DH, Ib, XX },
-  { "mov",	BH, Ib, XX },
+  { "mov",	RMAL, Ib, XX },
+  { "mov",	RMCL, Ib, XX },
+  { "mov",	RMDL, Ib, XX },
+  { "mov",	RMBL, Ib, XX },
+  { "mov",	RMAH, Ib, XX },
+  { "mov",	RMCH, Ib, XX },
+  { "mov",	RMDH, Ib, XX },
+  { "mov",	RMBH, Ib, XX },
   /* b8 */
-  { "mov",	eAX, Iv, XX },
-  { "mov",	eCX, Iv, XX },
-  { "mov",	eDX, Iv, XX },
-  { "mov",	eBX, Iv, XX },
-  { "mov",	eSP, Iv, XX },
-  { "mov",	eBP, Iv, XX },
-  { "mov",	eSI, Iv, XX },
-  { "mov",	eDI, Iv, XX },
+  { "mov",	RMeAX, Iv, XX },
+  { "mov",	RMeCX, Iv, XX },
+  { "mov",	RMeDX, Iv, XX },
+  { "mov",	RMeBX, Iv, XX },
+  { "mov",	RMeSP, Iv, XX },
+  { "mov",	RMeBP, Iv, XX },
+  { "mov",	RMeSI, Iv, XX },
+  { "mov",	RMeDI, Iv, XX },
   /* c0 */
   { GRP2b },
   { GRP2S },
@@ -930,6 +1036,592 @@ static const struct dis386 dis386_intel[] = {
   { GRP5 },
 };
 
+/* 64bit mode is having some instruction set differences, so separate table is
+   needed.  */
+static const struct dis386 disx86_64_att[] = {
+  /* 00 */
+  { "addB",	Eb, Gb, XX },
+  { "addS",	Ev, Gv, XX },
+  { "addB",	Gb, Eb, XX },
+  { "addS",	Gv, Ev, XX },
+  { "addB",	AL, Ib, XX },
+  { "addS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 08 */
+  { "orB",	Eb, Gb, XX },
+  { "orS",	Ev, Gv, XX },
+  { "orB",	Gb, Eb, XX },
+  { "orS",	Gv, Ev, XX },
+  { "orB",	AL, Ib, XX },
+  { "orS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },	/* 0x0f extended opcode escape */
+  /* 10 */
+  { "adcB",	Eb, Gb, XX },
+  { "adcS",	Ev, Gv, XX },
+  { "adcB",	Gb, Eb, XX },
+  { "adcS",	Gv, Ev, XX },
+  { "adcB",	AL, Ib, XX },
+  { "adcS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 18 */
+  { "sbbB",	Eb, Gb, XX },
+  { "sbbS",	Ev, Gv, XX },
+  { "sbbB",	Gb, Eb, XX },
+  { "sbbS",	Gv, Ev, XX },
+  { "sbbB",	AL, Ib, XX },
+  { "sbbS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 20 */
+  { "andB",	Eb, Gb, XX },
+  { "andS",	Ev, Gv, XX },
+  { "andB",	Gb, Eb, XX },
+  { "andS",	Gv, Ev, XX },
+  { "andB",	AL, Ib, XX },
+  { "andS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG ES prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 28 */
+  { "subB",	Eb, Gb, XX },
+  { "subS",	Ev, Gv, XX },
+  { "subB",	Gb, Eb, XX },
+  { "subS",	Gv, Ev, XX },
+  { "subB",	AL, Ib, XX },
+  { "subS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG CS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 30 */
+  { "xorB",	Eb, Gb, XX },
+  { "xorS",	Ev, Gv, XX },
+  { "xorB",	Gb, Eb, XX },
+  { "xorS",	Gv, Ev, XX },
+  { "xorB",	AL, Ib, XX },
+  { "xorS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG SS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 38 */
+  { "cmpB",	Eb, Gb, XX },
+  { "cmpS",	Ev, Gv, XX },
+  { "cmpB",	Gb, Eb, XX },
+  { "cmpS",	Gv, Ev, XX },
+  { "cmpB",	AL, Ib, XX },
+  { "cmpS",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG DS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 40 */
+  { "(bad)",	XX, XX, XX },			/* REX prefix area.  */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  /* 48 */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  /* 50 */
+  { "pushI",	RMrAX, XX, XX },
+  { "pushI",	RMrCX, XX, XX },
+  { "pushI",	RMrDX, XX, XX },
+  { "pushI",	RMrBX, XX, XX },
+  { "pushI",	RMrSP, XX, XX },
+  { "pushI",	RMrBP, XX, XX },
+  { "pushI",	RMrSI, XX, XX },
+  { "pushI",	RMrDI, XX, XX },
+  /* 58 */
+  { "popI",	RMrAX, XX, XX },
+  { "popI",	RMrCX, XX, XX },
+  { "popI",	RMrDX, XX, XX },
+  { "popI",	RMrBX, XX, XX },
+  { "popI",	RMrSP, XX, XX },
+  { "popI",	RMrBP, XX, XX },
+  { "popI",	RMrSI, XX, XX },
+  { "popI",	RMrDI, XX, XX },
+  /* 60 */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "movslR",   Gv, Ed, XX },
+  { "(bad)",	XX, XX, XX },			/* seg fs */
+  { "(bad)",	XX, XX, XX },			/* seg gs */
+  { "(bad)",	XX, XX, XX },			/* op size prefix */
+  { "(bad)",	XX, XX, XX },			/* adr size prefix */
+  /* 68 */
+  { "pushI",	Iq, XX, XX },		/* 386 book wrong */
+  { "imulS",	Gv, Ev, Iv },
+  { "pushI",	sIb, XX, XX },	/* push of byte really pushes 2 or 4 bytes */
+  { "imulS",	Gv, Ev, sIb },
+  { "insb",	Yb, indirDX, XX },
+  { "insR",	Yv, indirDX, XX },
+  { "outsb",	indirDX, Xb, XX },
+  { "outsR",	indirDX, Xv, XX },
+  /* 70 */
+  { "jo",	Jb, cond_jump_flag, XX },
+  { "jno",	Jb, cond_jump_flag, XX },
+  { "jb",	Jb, cond_jump_flag, XX },
+  { "jae",	Jb, cond_jump_flag, XX },
+  { "je",	Jb, cond_jump_flag, XX },
+  { "jne",	Jb, cond_jump_flag, XX },
+  { "jbe",	Jb, cond_jump_flag, XX },
+  { "ja",	Jb, cond_jump_flag, XX },
+  /* 78 */
+  { "js",	Jb, cond_jump_flag, XX },
+  { "jns",	Jb, cond_jump_flag, XX },
+  { "jp",	Jb, cond_jump_flag, XX },
+  { "jnp",	Jb, cond_jump_flag, XX },
+  { "jl",	Jb, cond_jump_flag, XX },
+  { "jge",	Jb, cond_jump_flag, XX },
+  { "jle",	Jb, cond_jump_flag, XX },
+  { "jg",	Jb, cond_jump_flag, XX },
+  /* 80 */
+  { GRP1b },
+  { GRP1S },
+  { "(bad)",	XX, XX, XX },
+  { GRP1Ss },
+  { "testB",	Eb, Gb, XX },
+  { "testS",	Ev, Gv, XX },
+  { "xchgB",	Eb, Gb, XX },
+  { "xchgS",	Ev, Gv, XX },
+  /* 88 */
+  { "movB",	Eb, Gb, XX },
+  { "movS",	Ev, Gv, XX },
+  { "movB",	Gb, Eb, XX },
+  { "movS",	Gv, Ev, XX },
+  { "movQ",	Ev, Sw, XX },
+  { "leaS",	Gv, M, XX },
+  { "movQ",	Sw, Ev, XX },
+  { "popI",	Ev, XX, XX },
+  /* 90 */
+  { "nop",	XX, XX, XX },
+  /* FIXME: NOP with REPz prefix is called PAUSE.  */
+  { "xchgS",	RMeCX, eAX, XX },
+  { "xchgS",	RMeDX, eAX, XX },
+  { "xchgS",	RMeBX, eAX, XX },
+  { "xchgS",	RMeSP, eAX, XX },
+  { "xchgS",	RMeBP, eAX, XX },
+  { "xchgS",	RMeSI, eAX, XX },
+  { "xchgS",	RMeDI, eAX, XX },
+  /* 98 */
+  { "cWtR",	XX, XX, XX },
+  { "cRtO",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },		/* fwait */
+  { "pushfI",	XX, XX, XX },
+  { "popfI",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  /* a0 */
+  { "movB",	AL, Ob64, XX },
+  { "movS",	eAX, Ov64, XX },
+  { "movB",	Ob64, AL, XX },
+  { "movS",	Ov64, eAX, XX },
+  { "movsb",	Yb, Xb, XX },
+  { "movsR",	Yv, Xv, XX },
+  { "cmpsb",	Xb, Yb, XX },
+  { "cmpsR",	Xv, Yv, XX },
+  /* a8 */
+  { "testB",	AL, Ib, XX },
+  { "testS",	eAX, Iv, XX },
+  { "stosB",	Yb, AL, XX },
+  { "stosS",	Yv, eAX, XX },
+  { "lodsB",	AL, Xb, XX },
+  { "lodsS",	eAX, Xv, XX },
+  { "scasB",	AL, Yb, XX },
+  { "scasS",	eAX, Yv, XX },
+  /* b0 */
+  { "movB",	RMAL, Ib, XX },
+  { "movB",	RMCL, Ib, XX },
+  { "movB",	RMDL, Ib, XX },
+  { "movB",	RMBL, Ib, XX },
+  { "movB",	RMAH, Ib, XX },
+  { "movB",	RMCH, Ib, XX },
+  { "movB",	RMDH, Ib, XX },
+  { "movB",	RMBH, Ib, XX },
+  /* b8 */
+  { "movS",	RMeAX, Iv64, XX },
+  { "movS",	RMeCX, Iv64, XX },
+  { "movS",	RMeDX, Iv64, XX },
+  { "movS",	RMeBX, Iv64, XX },
+  { "movS",	RMeSP, Iv64, XX },
+  { "movS",	RMeBP, Iv64, XX },
+  { "movS",	RMeSI, Iv64, XX },
+  { "movS",	RMeDI, Iv64, XX },
+  /* c0 */
+  { GRP2b },
+  { GRP2S },
+  { "retI",	Iw, XX, XX },
+  { "retI",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "ldsS",	Gv, Mp, XX },
+  { "movA",	Eb, Ib, XX },
+  { "movQ",	Ev, Iv, XX },
+  /* c8 */
+  { "enterI",	Iw, Ib, XX },
+  { "leaveI",	XX, XX, XX },
+  { "lretP",	Iw, XX, XX },
+  { "lretP",	XX, XX, XX },
+  { "int3",	XX, XX, XX },
+  { "int",	Ib, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "iretP",	XX, XX, XX },
+  /* d0 */
+  { GRP2b_one },
+  { GRP2S_one },
+  { GRP2b_cl },
+  { GRP2S_cl },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "xlat",	DSBX, XX, XX },
+  /* d8 */
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  /* e0 */
+  { "loopneF",	Jb, loop_jcxz_flag, XX },
+  { "loopeF",	Jb, loop_jcxz_flag, XX },
+  { "loopF",	Jb, loop_jcxz_flag, XX },
+  { "jEcxz",	Jb, loop_jcxz_flag, XX },
+  { "inB",	AL, Ib, XX },
+  { "inS",	eAX, Ib, XX },
+  { "outB",	Ib, AL, XX },
+  { "outS",	Ib, eAX, XX },
+  /* e8 */
+  { "callI",	Jv, XX, XX },
+  { "jmpI",	Jv, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* reserved.  */
+  { "jmp",	Jb, XX, XX },
+  { "inB",	AL, indirDX, XX },
+  { "inS",	eAX, indirDX, XX },
+  { "outB",	indirDX, AL, XX },
+  { "outS",	indirDX, eAX, XX },
+  /* f0 */
+  { "(bad)",	XX, XX, XX },			/* lock prefix */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },			/* repne */
+  { "(bad)",	XX, XX, XX },			/* repz */
+  { "hlt",	XX, XX, XX },
+  { "cmc",	XX, XX, XX },
+  { GRP3b },
+  { GRP3S },
+  /* f8 */
+  { "clc",	XX, XX, XX },
+  { "stc",	XX, XX, XX },
+  { "cli",	XX, XX, XX },
+  { "sti",	XX, XX, XX },
+  { "cld",	XX, XX, XX },
+  { "std",	XX, XX, XX },
+  { GRP4 },
+  { GRP5 },
+};
+
+static const struct dis386 dis386_64_intel[] = {
+  /* 00 */
+  { "add",	Eb, Gb, XX },
+  { "add",	Ev, Gv, XX },
+  { "add",	Gb, Eb, XX },
+  { "add",	Gv, Ev, XX },
+  { "add",	AL, Ib, XX },
+  { "add",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 08 */
+  { "or",	Eb, Gb, XX },
+  { "or",	Ev, Gv, XX },
+  { "or",	Gb, Eb, XX },
+  { "or",	Gv, Ev, XX },
+  { "or",	AL, Ib, XX },
+  { "or",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },	/* 0x0f extended opcode escape */
+  /* 10 */
+  { "adc",	Eb, Gb, XX },
+  { "adc",	Ev, Gv, XX },
+  { "adc",	Gb, Eb, XX },
+  { "adc",	Gv, Ev, XX },
+  { "adc",	AL, Ib, XX },
+  { "adc",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 18 */
+  { "sbb",	Eb, Gb, XX },
+  { "sbb",	Ev, Gv, XX },
+  { "sbb",	Gb, Eb, XX },
+  { "sbb",	Gv, Ev, XX },
+  { "sbb",	AL, Ib, XX },
+  { "sbb",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 20 */
+  { "and",	Eb, Gb, XX },
+  { "and",	Ev, Gv, XX },
+  { "and",	Gb, Eb, XX },
+  { "and",	Gv, Ev, XX },
+  { "and",	AL, Ib, XX },
+  { "and",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG ES prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 28 */
+  { "sub",	Eb, Gb, XX },
+  { "sub",	Ev, Gv, XX },
+  { "sub",	Gb, Eb, XX },
+  { "sub",	Gv, Ev, XX },
+  { "sub",	AL, Ib, XX },
+  { "sub",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG CS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 30 */
+  { "xor",	Eb, Gb, XX },
+  { "xor",	Ev, Gv, XX },
+  { "xor",	Gb, Eb, XX },
+  { "xor",	Gv, Ev, XX },
+  { "xor",	AL, Ib, XX },
+  { "xor",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG SS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 38 */
+  { "cmp",	Eb, Gb, XX },
+  { "cmp",	Ev, Gv, XX },
+  { "cmp",	Gb, Eb, XX },
+  { "cmp",	Gv, Ev, XX },
+  { "cmp",	AL, Ib, XX },
+  { "cmp",	eAX, Iv, XX },
+  { "(bad)",	XX, XX, XX },			/* SEG DS prefix */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* 40 */
+  { "(bad)",	XX, XX, XX },			/* REX prefix area.  */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  /* 48 */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },
+  /* 50 */
+  { "push",	RMrAX, XX, XX },
+  { "push",	RMrCX, XX, XX },
+  { "push",	RMrDX, XX, XX },
+  { "push",	RMrBX, XX, XX },
+  { "push",	RMrSP, XX, XX },
+  { "push",	RMrBP, XX, XX },
+  { "push",	RMrSI, XX, XX },
+  { "push",	RMrDI, XX, XX },
+  /* 58 */
+  { "pop",	RMrAX, XX, XX },
+  { "pop",	RMrCX, XX, XX },
+  { "pop",	RMrDX, XX, XX },
+  { "pop",	RMrBX, XX, XX },
+  { "pop",	RMrSP, XX, XX },
+  { "pop",	RMrBP, XX, XX },
+  { "pop",	RMrSI, XX, XX },
+  { "pop",	RMrDI, XX, XX },
+  /* 60 */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "movsx",	Gv, Ed, XX },
+  { "(bad)",	XX, XX, XX },			/* seg fs */
+  { "(bad)",	XX, XX, XX },			/* seg gs */
+  { "(bad)",	XX, XX, XX },			/* op size prefix */
+  { "(bad)",	XX, XX, XX },			/* adr size prefix */
+  /* 68 */
+  { "push",	Iq, XX, XX },		/* 386 book wrong */
+  { "imul",	Gv, Ev, Iv },
+  { "push",	sIb, XX, XX },	/* push of byte really pushes 2 or 4 bytes */
+  { "imul",	Gv, Ev, sIb },
+  { "ins",	Yb, indirDX, XX },
+  { "ins",	Yv, indirDX, XX },
+  { "outs",	indirDX, Xb, XX },
+  { "outs",	indirDX, Xv, XX },
+  /* 70 */
+  { "jo",	Jb, XX, XX },
+  { "jno",	Jb, XX, XX },
+  { "jb",	Jb, XX, XX },
+  { "jae",	Jb, XX, XX },
+  { "je",	Jb, XX, XX },
+  { "jne",	Jb, XX, XX },
+  { "jbe",	Jb, XX, XX },
+  { "ja",	Jb, XX, XX },
+  /* 78 */
+  { "js",	Jb, XX, XX },
+  { "jns",	Jb, XX, XX },
+  { "jp",	Jb, XX, XX },
+  { "jnp",	Jb, XX, XX },
+  { "jl",	Jb, XX, XX },
+  { "jge",	Jb, XX, XX },
+  { "jle",	Jb, XX, XX },
+  { "jg",	Jb, XX, XX },
+  /* 80 */
+  { GRP1b },
+  { GRP1S },
+  { "(bad)",	XX, XX, XX },
+  { GRP1Ss },
+  { "test",	Eb, Gb, XX },
+  { "test",	Ev, Gv, XX },
+  { "xchg",	Eb, Gb, XX },
+  { "xchg",	Ev, Gv, XX },
+  /* 88 */
+  { "mov",	Eb, Gb, XX },
+  { "mov",	Ev, Gv, XX },
+  { "mov",	Gb, Eb, XX },
+  { "mov",	Gv, Ev, XX },
+  { "mov",	Ev, Sw, XX },
+  { "lea",	Gv, M, XX },
+  { "mov",	Sw, Ev, XX },
+  { "pop",	Ev, XX, XX },
+  /* 90 */
+  { "nop",	XX, XX, XX },
+  /* FIXME: NOP with REPz prefix is called PAUSE.  */
+  { "xchg",	RMeCX, eAX, XX },
+  { "xchg",	RMeDX, eAX, XX },
+  { "xchg",	RMeBX, eAX, XX },
+  { "xchg",	RMeSP, eAX, XX },
+  { "xchg",	RMeBP, eAX, XX },
+  { "xchg",	RMeSI, eAX, XX },
+  { "xchg",	RMeDI, eAX, XX },
+  /* 98 */
+  { "cW",	XX, XX, XX },		/* cwde and cbw */
+  { "cR",	XX, XX, XX },		/* cdq and cwd */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },		/* fwait */
+  { "pushf",	XX, XX, XX },
+  { "popf",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  /* a0 */
+  { "mov",	AL, Ob, XX },
+  { "mov",	eAX, Ov, XX },
+  { "mov",	Ob, AL, XX },
+  { "mov",	Ov, eAX, XX },
+  { "movs",	Yb, Xb, XX },
+  { "movs",	Yv, Xv, XX },
+  { "cmps",	Xb, Yb, XX },
+  { "cmps",	Xv, Yv, XX },
+  /* a8 */
+  { "test",	AL, Ib, XX },
+  { "test",	eAX, Iv, XX },
+  { "stos",	Yb, AL, XX },
+  { "stos",	Yv, eAX, XX },
+  { "lods",	AL, Xb, XX },
+  { "lods",	eAX, Xv, XX },
+  { "scas",	AL, Yb, XX },
+  { "scas",	eAX, Yv, XX },
+  /* b0 */
+  { "mov",	RMAL, Ib, XX },
+  { "mov",	RMCL, Ib, XX },
+  { "mov",	RMDL, Ib, XX },
+  { "mov",	RMBL, Ib, XX },
+  { "mov",	RMAH, Ib, XX },
+  { "mov",	RMCH, Ib, XX },
+  { "mov",	RMDH, Ib, XX },
+  { "mov",	RMBH, Ib, XX },
+  /* b8 */
+  { "mov",	RMeAX, Iv, XX },
+  { "mov",	RMeCX, Iv, XX },
+  { "mov",	RMeDX, Iv, XX },
+  { "mov",	RMeBX, Iv, XX },
+  { "mov",	RMeSP, Iv, XX },
+  { "mov",	RMeBP, Iv, XX },
+  { "mov",	RMeSI, Iv, XX },
+  { "mov",	RMeDI, Iv, XX },
+  /* c0 */
+  { GRP2b },
+  { GRP2S },
+  { "ret",	Iw, XX, XX },
+  { "ret",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "lds",	Gv, Mp, XX },
+  { "mov",	Eb, Ib, XX },
+  { "mov",	Ev, Iv, XX },
+  /* c8 */
+  { "enter",	Iw, Ib, XX },
+  { "leave",	XX, XX, XX },
+  { "lret",	Iw, XX, XX },
+  { "lret",	XX, XX, XX },
+  { "int3",	XX, XX, XX },
+  { "int",	Ib, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "iret",	XX, XX, XX },
+  /* d0 */
+  { GRP2b_one },
+  { GRP2S_one },
+  { GRP2b_cl },
+  { GRP2S_cl },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "xlat",	DSBX, XX, XX },
+  /* d8 */
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  { FLOAT },
+  /* e0 */
+  { "loopne",	Jb, XX, XX },
+  { "loope",	Jb, XX, XX },
+  { "loop",	Jb, XX, XX },
+  { "jEcxz",	Jb, XX, XX },
+  { "in",	AL, Ib, XX },
+  { "in",	eAX, Ib, XX },
+  { "out",	Ib, AL, XX },
+  { "out",	Ib, eAX, XX },
+  /* e8 */
+  { "call",	Jv, XX, XX },
+  { "jmp",	Jv, XX, XX },
+  { "(bad)",	XX, XX, XX },   /* Reserved.  */
+  { "jmp",	Jb, XX, XX },
+  { "in",	AL, indirDX, XX },
+  { "in",	eAX, indirDX, XX },
+  { "out",	indirDX, AL, XX },
+  { "out",	indirDX, eAX, XX },
+  /* f0 */
+  { "(bad)",	XX, XX, XX },			/* lock prefix */
+  { "(bad)",	XX, XX, XX },
+  { "(bad)",	XX, XX, XX },			/* repne */
+  { "(bad)",	XX, XX, XX },			/* repz */
+  { "hlt",	XX, XX, XX },
+  { "cmc",	XX, XX, XX },
+  { GRP3b },
+  { GRP3S },
+  /* f8 */
+  { "clc",	XX, XX, XX },
+  { "stc",	XX, XX, XX },
+  { "cli",	XX, XX, XX },
+  { "sti",	XX, XX, XX },
+  { "cld",	XX, XX, XX },
+  { "std",	XX, XX, XX },
+  { GRP4 },
+  { GRP5 },
+};
+
 static const struct dis386 dis386_twobyte_att[] = {
   /* 00 */
   { GRP6 },
@@ -937,9 +1629,9 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "larS", Gv, Ew, XX },
   { "lslS", Gv, Ew, XX },
   { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { "syscall", XX, XX, XX },
   { "clts", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { "sysretP", XX, XX, XX },
   /* 08 */
   { "invd", XX, XX, XX },
   { "wbinvd", XX, XX, XX },
@@ -952,12 +1644,12 @@ static const struct dis386 dis386_twobyte_att[] = {
   /* 10 */
   { PREGRP8 },
   { PREGRP9 },
-  { "movlps", XM, EX, SIMD_Fixup, 'h' },  /* really only 2 operands */
-  { "movlps", EX, XM, SIMD_Fixup, 'h' },
-  { "unpcklps", XM, EX, XX },
-  { "unpckhps", XM, EX, XX },
-  { "movhps", XM, EX, SIMD_Fixup, 'l' },
-  { "movhps", EX, XM, SIMD_Fixup, 'l' },
+  { "movlpX", XM, EX, SIMD_Fixup, 'h' },  /* really only 2 operands */
+  { "movlpX", EX, XM, SIMD_Fixup, 'h' },
+  { "unpcklpX", XM, EX, XX },
+  { "unpckhpX", XM, EX, XX },
+  { "movhpX", XM, EX, SIMD_Fixup, 'l' },
+  { "movhpX", EX, XM, SIMD_Fixup, 'l' },
   /* 18 */
   { GRP14 },
   { "(bad)", XX, XX, XX },
@@ -969,23 +1661,23 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "(bad)", XX, XX, XX },
   /* 20 */
   /* these are all backward in appendix A of the intel book */
-  { "movL", Rd, Cd, XX },
-  { "movL", Rd, Dd, XX },
-  { "movL", Cd, Rd, XX },
-  { "movL", Dd, Rd, XX },
+  { "movL", Rm, Cm, XX },
+  { "movL", Rm, Dm, XX },
+  { "movL", Cm, Rm, XX },
+  { "movL", Dm, Rm, XX },
   { "movL", Rd, Td, XX },
   { "(bad)", XX, XX, XX },
   { "movL", Td, Rd, XX },
   { "(bad)", XX, XX, XX },
   /* 28 */
-  { "movaps", XM, EX, XX },
-  { "movaps", EX, XM, XX },
+  { "movapX", XM, EX, XX },
+  { "movapX", EX, XM, XX },
   { PREGRP2 },
-  { "movntps", Ev, XM, XX },
+  { "movntpX", Ev, XM, XX },
   { PREGRP4 },
   { PREGRP3 },
-  { "ucomiss", XM, EX, XX },
-  { "comiss", XM, EX, XX },
+  { "ucomisX", XM,EX, XX },
+  { "comisX", XM,EX, XX },
   /* 30 */
   { "wrmsr", XX, XX, XX },
   { "rdtsc", XX, XX, XX },
@@ -1023,19 +1715,19 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "cmovle", Gv, Ev, XX },
   { "cmovg", Gv, Ev, XX },
   /* 50 */
-  { "movmskps", Gv, EX, XX },
+  { "movmskpX", Gd, XS, XX },
   { PREGRP13 },
   { PREGRP12 },
   { PREGRP11 },
-  { "andps", XM, EX, XX },
-  { "andnps", XM, EX, XX },
-  { "orps", XM, EX, XX },
-  { "xorps", XM, EX, XX },
+  { "andpX", XM, EX, XX },
+  { "andnpX", XM, EX, XX },
+  { "orpX", XM, EX, XX },
+  { "xorpX", XM, EX, XX },
   /* 58 */
   { PREGRP0 },
   { PREGRP10 },
-  { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { PREGRP17 },
+  { PREGRP16 },
   { PREGRP14 },
   { PREGRP7 },
   { PREGRP5 },
@@ -1054,12 +1746,12 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "punpckhwd", MX, EM, XX },
   { "punpckhdq", MX, EM, XX },
   { "packssdw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { PREGRP26 },
+  { PREGRP24 },
   { "movd", MX, Ed, XX },
-  { "movq", MX, EM, XX },
+  { PREGRP19 },
   /* 70 */
-  { "pshufw", MX, EM, Ib },
+  { PREGRP22 },
   { GRP10 },
   { GRP11 },
   { GRP12 },
@@ -1074,26 +1766,26 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "(bad)", XX, XX, XX },
   { "(bad)", XX, XX, XX },
   { "(bad)", XX, XX, XX },
-  { "movd", Ed, MX, XX },
-  { "movq", EM, MX, XX },
+  { PREGRP23 },
+  { PREGRP20 },
   /* 80 */
-  { "jo", Jv, XX, XX },
-  { "jno", Jv, XX, XX },
-  { "jb", Jv, XX, XX },
-  { "jae", Jv, XX, XX },
-  { "je", Jv, XX, XX },
-  { "jne", Jv, XX, XX },
-  { "jbe", Jv, XX, XX },
-  { "ja", Jv, XX, XX },
+  { "jo",  Jv, cond_jump_flag, XX },
+  { "jno", Jv, cond_jump_flag, XX },
+  { "jb",  Jv, cond_jump_flag, XX },
+  { "jae", Jv, cond_jump_flag, XX },
+  { "je",  Jv, cond_jump_flag, XX },
+  { "jne", Jv, cond_jump_flag, XX },
+  { "jbe", Jv, cond_jump_flag, XX },
+  { "ja",  Jv, cond_jump_flag, XX },
   /* 88 */
-  { "js", Jv, XX, XX },
-  { "jns", Jv, XX, XX },
-  { "jp", Jv, XX, XX },
-  { "jnp", Jv, XX, XX },
-  { "jl", Jv, XX, XX },
-  { "jge", Jv, XX, XX },
-  { "jle", Jv, XX, XX },
-  { "jg", Jv, XX, XX },
+  { "js",  Jv, cond_jump_flag, XX },
+  { "jns", Jv, cond_jump_flag, XX },
+  { "jp",  Jv, cond_jump_flag, XX },
+  { "jnp", Jv, cond_jump_flag, XX },
+  { "jl",  Jv, cond_jump_flag, XX },
+  { "jge", Jv, cond_jump_flag, XX },
+  { "jle", Jv, cond_jump_flag, XX },
+  { "jg",  Jv, cond_jump_flag, XX },
   /* 90 */
   { "seto", Eb, XX, XX },
   { "setno", Eb, XX, XX },
@@ -1113,8 +1805,8 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "setle", Eb, XX, XX },
   { "setg", Eb, XX, XX },
   /* a0 */
-  { "pushP", fs, XX, XX },
-  { "popP", fs, XX, XX },
+  { "pushI", fs, XX, XX },
+  { "popI", fs, XX, XX },
   { "cpuid", XX, XX, XX },
   { "btS", Ev, Gv, XX },
   { "shldS", Ev, Gv, Ib },
@@ -1122,8 +1814,8 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "(bad)", XX, XX, XX },
   { "(bad)", XX, XX, XX },
   /* a8 */
-  { "pushP", gs, XX, XX },
-  { "popP", gs, XX, XX },
+  { "pushI", gs, XX, XX },
+  { "popI", gs, XX, XX },
   { "rsm", XX, XX, XX },
   { "btsS", Ev, Gv, XX },
   { "shrdS", Ev, Gv, Ib },
@@ -1152,29 +1844,29 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "xaddB", Eb, Gb, XX },
   { "xaddS", Ev, Gv, XX },
   { PREGRP1 },
-  { "(bad)", XX, XX, XX },
-  { "pinsrw", MX, Ev, Ib },
-  { "pextrw", Ev, MX, Ib },
-  { "shufps", XM, EX, Ib },
+  { "movntiS", Ev, Gv, XX },
+  { "pinsrw", MX, Ed, Ib },
+  { "pextrw", Gd, MS, Ib },
+  { "shufpX", XM, EX, Ib },
   { GRP9 },
   /* c8 */
-  { "bswap", eAX, XX, XX },	/* bswap doesn't support 16 bit regs */
-  { "bswap", eCX, XX, XX },
-  { "bswap", eDX, XX, XX },
-  { "bswap", eBX, XX, XX },
-  { "bswap", eSP, XX, XX },
-  { "bswap", eBP, XX, XX },
-  { "bswap", eSI, XX, XX },
-  { "bswap", eDI, XX, XX },
+  { "bswap", RMeAX, XX, XX },	/* bswap doesn't support 16 bit regs */
+  { "bswap", RMeCX, XX, XX },
+  { "bswap", RMeDX, XX, XX },
+  { "bswap", RMeBX, XX, XX },
+  { "bswap", RMeSP, XX, XX },
+  { "bswap", RMeBP, XX, XX },
+  { "bswap", RMeSI, XX, XX },
+  { "bswap", RMeDI, XX, XX },
   /* d0 */
   { "(bad)", XX, XX, XX },
   { "psrlw", MX, EM, XX },
   { "psrld", MX, EM, XX },
   { "psrlq", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "paddq", MX, EM, XX },
   { "pmullw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "pmovmskb", Ev, MX, XX },
+  { PREGRP21 },
+  { "pmovmskb", Gd, MS, XX },
   /* d8 */
   { "psubusb", MX, EM, XX },
   { "psubusw", MX, EM, XX },
@@ -1191,8 +1883,8 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "pavgw", MX, EM, XX },
   { "pmulhuw", MX, EM, XX },
   { "pmulhw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "movntq", Ev, MX, XX },
+  { PREGRP15 },
+  { PREGRP25 },
   /* e8 */
   { "psubsb", MX, EM, XX },
   { "psubsw", MX, EM, XX },
@@ -1207,15 +1899,15 @@ static const struct dis386 dis386_twobyte_att[] = {
   { "psllw", MX, EM, XX },
   { "pslld", MX, EM, XX },
   { "psllq", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "pmuludq", MX, EM, XX },
   { "pmaddwd", MX, EM, XX },
   { "psadbw", MX, EM, XX },
-  { "maskmovq", MX, EM, XX },
+  { PREGRP18 },
   /* f8 */
   { "psubb", MX, EM, XX },
   { "psubw", MX, EM, XX },
   { "psubd", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "psubq", MX, EM, XX },
   { "paddb", MX, EM, XX },
   { "paddw", MX, EM, XX },
   { "paddd", MX, EM, XX },
@@ -1229,9 +1921,9 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "lar", Gv, Ew, XX },
   { "lsl", Gv, Ew, XX },
   { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { "syscall", XX, XX, XX },
   { "clts", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { "sysretP", XX, XX, XX },
   /* 08 */
   { "invd", XX, XX, XX },
   { "wbinvd", XX, XX, XX },
@@ -1244,12 +1936,12 @@ static const struct dis386 dis386_twobyte_intel[] = {
   /* 10 */
   { PREGRP8 },
   { PREGRP9 },
-  { "movlps", XM, EX, SIMD_Fixup, 'h' },  /* really only 2 operands */
-  { "movlps", EX, XM, SIMD_Fixup, 'h' },
-  { "unpcklps", XM, EX, XX },
-  { "unpckhps", XM, EX, XX },
-  { "movhps", XM, EX, SIMD_Fixup, 'l' },
-  { "movhps", EX, XM, SIMD_Fixup, 'l' },
+  { "movlpX", XM, EX, SIMD_Fixup, 'h' },  /* really only 2 operands */
+  { "movlpX", EX, XM, SIMD_Fixup, 'h' },
+  { "unpcklpX", XM, EX, XX },
+  { "unpckhpX", XM, EX, XX },
+  { "movhpX", XM, EX, SIMD_Fixup, 'l' },
+  { "movhpX", EX, XM, SIMD_Fixup, 'l' },
   /* 18 */
   { GRP14 },
   { "(bad)", XX, XX, XX },
@@ -1261,23 +1953,23 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "(bad)", XX, XX, XX },
   /* 20 */
   /* these are all backward in appendix A of the intel book */
-  { "mov", Rd, Cd, XX },
-  { "mov", Rd, Dd, XX },
-  { "mov", Cd, Rd, XX },
-  { "mov", Dd, Rd, XX },
+  { "mov", Rm, Cm, XX },
+  { "mov", Rm, Dm, XX },
+  { "mov", Cm, Rm, XX },
+  { "mov", Dm, Rm, XX },
   { "mov", Rd, Td, XX },
   { "(bad)", XX, XX, XX },
   { "mov", Td, Rd, XX },
   { "(bad)", XX, XX, XX },
   /* 28 */
-  { "movaps", XM, EX, XX },
-  { "movaps", EX, XM, XX },
+  { "movapX", XM, EX, XX },
+  { "movapX", EX, XM, XX },
   { PREGRP2 },
-  { "movntps", Ev, XM, XX },
+  { "movntpX", Ev, XM, XX },
   { PREGRP4 },
   { PREGRP3 },
-  { "ucomiss", XM, EX, XX },
-  { "comiss", XM, EX, XX },
+  { "ucomisX", XM,EX, XX },
+  { "comisX", XM,EX, XX },
   /* 30 */
   { "wrmsr", XX, XX, XX },
   { "rdtsc", XX, XX, XX },
@@ -1315,19 +2007,19 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "cmovle", Gv, Ev, XX },
   { "cmovg", Gv, Ev, XX },
   /* 50 */
-  { "movmskps", Gv, EX, XX },
+  { "movmskpX", Gd, XS, XX },
   { PREGRP13 },
   { PREGRP12 },
   { PREGRP11 },
-  { "andps", XM, EX, XX },
-  { "andnps", XM, EX, XX },
-  { "orps", XM, EX, XX },
-  { "xorps", XM, EX, XX },
+  { "andpX", XM, EX, XX },
+  { "andnpX", XM, EX, XX },
+  { "orpX", XM, EX, XX },
+  { "xorpX", XM, EX, XX },
   /* 58 */
   { PREGRP0 },
   { PREGRP10 },
-  { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { PREGRP17 },
+  { PREGRP16 },
   { PREGRP14 },
   { PREGRP7 },
   { PREGRP5 },
@@ -1346,12 +2038,12 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "punpckhwd", MX, EM, XX },
   { "punpckhdq", MX, EM, XX },
   { "packssdw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "(bad)", XX, XX, XX },
+  { PREGRP26 },
+  { PREGRP24 },
   { "movd", MX, Ed, XX },
-  { "movq", MX, EM, XX },
+  { PREGRP19 },
   /* 70 */
-  { "pshufw", MX, EM, Ib },
+  { PREGRP22 },
   { GRP10 },
   { GRP11 },
   { GRP12 },
@@ -1366,8 +2058,8 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "(bad)", XX, XX, XX },
   { "(bad)", XX, XX, XX },
   { "(bad)", XX, XX, XX },
-  { "movd", Ed, MX, XX },
-  { "movq", EM, MX, XX },
+  { PREGRP23 },
+  { PREGRP20 },
   /* 80 */
   { "jo", Jv, XX, XX },
   { "jno", Jv, XX, XX },
@@ -1444,29 +2136,29 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "xadd", Eb, Gb, XX },
   { "xadd", Ev, Gv, XX },
   { PREGRP1 },
-  { "(bad)", XX, XX, XX },
-  { "pinsrw", MX, Ev, Ib },
-  { "pextrw", Ev, MX, Ib },
-  { "shufps", XM, EX, Ib },
+  { "movnti", Ev, Gv, XX },
+  { "pinsrw", MX, Ed, Ib },
+  { "pextrw", Gd, MS, Ib },
+  { "shufpX", XM, EX, Ib },
   { GRP9 },
   /* c8 */
-  { "bswap", eAX, XX, XX },	/* bswap doesn't support 16 bit regs */
-  { "bswap", eCX, XX, XX },
-  { "bswap", eDX, XX, XX },
-  { "bswap", eBX, XX, XX },
-  { "bswap", eSP, XX, XX },
-  { "bswap", eBP, XX, XX },
-  { "bswap", eSI, XX, XX },
-  { "bswap", eDI, XX, XX },
+  { "bswap", RMeAX, XX, XX },	/* bswap doesn't support 16 bit regs */
+  { "bswap", RMeCX, XX, XX },
+  { "bswap", RMeDX, XX, XX },
+  { "bswap", RMeBX, XX, XX },
+  { "bswap", RMeSP, XX, XX },
+  { "bswap", RMeBP, XX, XX },
+  { "bswap", RMeSI, XX, XX },
+  { "bswap", RMeDI, XX, XX },
   /* d0 */
   { "(bad)", XX, XX, XX },
   { "psrlw", MX, EM, XX },
   { "psrld", MX, EM, XX },
   { "psrlq", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "paddq", MX, EM, XX },
   { "pmullw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "pmovmskb", Ev, MX, XX },
+  { PREGRP21 },
+  { "pmovmskb", Gd, MS, XX },
   /* d8 */
   { "psubusb", MX, EM, XX },
   { "psubusw", MX, EM, XX },
@@ -1483,8 +2175,8 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "pavgw", MX, EM, XX },
   { "pmulhuw", MX, EM, XX },
   { "pmulhw", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
-  { "movntq", Ev, MX, XX },
+  { PREGRP15 },
+  { PREGRP25 },
   /* e8 */
   { "psubsb", MX, EM, XX },
   { "psubsw", MX, EM, XX },
@@ -1499,15 +2191,15 @@ static const struct dis386 dis386_twobyte_intel[] = {
   { "psllw", MX, EM, XX },
   { "pslld", MX, EM, XX },
   { "psllq", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "pmuludq", MX, EM, XX },
   { "pmaddwd", MX, EM, XX },
   { "psadbw", MX, EM, XX },
-  { "maskmovq", MX, EM, XX },
+  { PREGRP18 },
   /* f8 */
   { "psubb", MX, EM, XX },
   { "psubw", MX, EM, XX },
   { "psubd", MX, EM, XX },
-  { "(bad)", XX, XX, XX },
+  { "psubq", MX, EM, XX },
   { "paddb", MX, EM, XX },
   { "paddw", MX, EM, XX },
   { "paddd", MX, EM, XX },
@@ -1542,25 +2234,25 @@ static const unsigned char twobyte_has_modrm[256] = {
   /*       -------------------------------        */
   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
   /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */
-  /* 20 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 2f */
+  /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
   /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
-  /* 50 */ 1,1,1,1,1,1,1,1,1,1,0,0,1,1,1,1, /* 5f */
-  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,1,1, /* 6f */
+  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
+  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
   /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */
   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
-  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
+  /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */
   /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */
   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
-  /* d0 */ 0,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1, /* df */
-  /* e0 */ 1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1, /* ef */
-  /* f0 */ 0,1,1,1,0,1,1,1,1,1,1,0,1,1,1,0  /* ff */
+  /* d0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
+  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
+  /* f0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
   /*       -------------------------------        */
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
 };
 
-static const unsigned char twobyte_uses_f3_prefix[256] = {
+static const unsigned char twobyte_uses_SSE_prefix[256] = {
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
   /*       -------------------------------        */
   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
@@ -1568,17 +2260,17 @@ static const unsigned char twobyte_uses_f3_prefix[256] = {
   /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */
   /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
-  /* 50 */ 0,1,1,1,0,0,0,0,1,1,0,0,1,1,1,1, /* 5f */
-  /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
-  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
+  /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
+  /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
+  /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */
   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
   /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
-  /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
-  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
-  /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0  /* ff */
+  /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
+  /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
+  /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0  /* ff */
   /*       -------------------------------        */
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
 };
@@ -1593,17 +2285,33 @@ static disassemble_info *the_info;
 static int mod;
 static int rm;
 static int reg;
+static unsigned char need_modrm;
 static void oappend PARAMS ((const char *s));
 
-static const char *names32[]={
+/* If we are accessing mod/rm/reg without need_modrm set, then the
+   values are stale.  Hitting this abort likely indicates that you
+   need to update onebyte_has_modrm or twobyte_has_modrm.  */
+#define MODRM_CHECK  if (!need_modrm) abort ()
+
+static const char *names64[] = {
+  "%rax","%rcx","%rdx","%rbx", "%rsp","%rbp","%rsi","%rdi",
+  "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
+};
+static const char *names32[] = {
   "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
+  "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
 };
 static const char *names16[] = {
   "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
+  "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
 };
 static const char *names8[] = {
   "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
 };
+static const char *names8rex[] = {
+  "%al","%cl","%dl","%bl","%spl", "%bpl", "%sil", "%dil",
+  "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
+};
 static const char *names_seg[] = {
   "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
 };
@@ -1748,11 +2456,11 @@ static const struct dis386 grps[][8] = {
   {
     { "incQ",	Ev, XX, XX },
     { "decQ",	Ev, XX, XX },
-    { "callP",	indirEv, XX, XX },
-    { "lcallP",	indirEv, XX, XX },
-    { "jmpP",	indirEv, XX, XX },
-    { "ljmpP",	indirEv, XX, XX },
-    { "pushQ",	Ev, XX, XX },
+    { "callI",	indirEv, XX, XX },
+    { "lcallI",	indirEv, XX, XX },
+    { "jmpI",	indirEv, XX, XX },
+    { "ljmpI",	indirEv, XX, XX },
+    { "pushT",	Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
   },
   /* GRP6 */
@@ -1826,11 +2534,11 @@ static const struct dis386 grps[][8] = {
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "psrlq",	MS, Ib, XX },
-    { "(bad)",	XX, XX, XX },
+    { "psrldq",	MS, Ib, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "psllq",	MS, Ib, XX },
-    { "(bad)",	XX, XX, XX },
+    { "pslldq",	MS, Ib, XX },
   },
   /* GRP13 */
   {
@@ -1839,9 +2547,10 @@ static const struct dis386 grps[][8] = {
     { "ldmxcsr", Ev, XX, XX },
     { "stmxcsr", Ev, XX, XX },
     { "(bad)",	XX, XX, XX },
-    { "(bad)",	XX, XX, XX },
-    { "(bad)",	XX, XX, XX },
+    { "lfence", None, XX, XX },
+    { "mfence", None, XX, XX },
     { "sfence", None, XX, XX },
+    /* FIXME: the sfence with memory operand is clflush! */
   },
   /* GRP14 */
   {
@@ -1868,82 +2577,196 @@ static const struct dis386 grps[][8] = {
 
 };
 
-static const struct dis386 prefix_user_table[][2] = {
+static const struct dis386 prefix_user_table[][4] = {
   /* PREGRP0 */
   {
     { "addps", XM, EX, XX },
     { "addss", XM, EX, XX },
+    { "addpd", XM, EX, XX },
+    { "addsd", XM, EX, XX },
   },
   /* PREGRP1 */
   {
     { "", XM, EX, OPSIMD },	/* See OP_SIMD_SUFFIX */
     { "", XM, EX, OPSIMD },
+    { "", XM, EX, OPSIMD },
+    { "", XM, EX, OPSIMD },
   },
   /* PREGRP2 */
   {
     { "cvtpi2ps", XM, EM, XX },
-    { "cvtsi2ss", XM, Ev, XX },
+    { "cvtsi2ssY", XM, Ev, XX },
+    { "cvtpi2pd", XM, EM, XX },
+    { "cvtsi2sdY", XM, Ev, XX },
   },
   /* PREGRP3 */
   {
     { "cvtps2pi", MX, EX, XX },
-    { "cvtss2si", Gv, EX, XX },
+    { "cvtss2siY", Gv, EX, XX },
+    { "cvtpd2pi", MX, EX, XX },
+    { "cvtsd2siY", Gv, EX, XX },
   },
   /* PREGRP4 */
   {
     { "cvttps2pi", MX, EX, XX },
-    { "cvttss2si", Gv, EX, XX },
+    { "cvttss2siY", Gv, EX, XX },
+    { "cvttpd2pi", MX, EX, XX },
+    { "cvttsd2siY", Gv, EX, XX },
   },
   /* PREGRP5 */
   {
     { "divps", XM, EX, XX },
     { "divss", XM, EX, XX },
+    { "divpd", XM, EX, XX },
+    { "divsd", XM, EX, XX },
   },
   /* PREGRP6 */
   {
     { "maxps", XM, EX, XX },
     { "maxss", XM, EX, XX },
+    { "maxpd", XM, EX, XX },
+    { "maxsd", XM, EX, XX },
   },
   /* PREGRP7 */
   {
     { "minps", XM, EX, XX },
     { "minss", XM, EX, XX },
+    { "minpd", XM, EX, XX },
+    { "minsd", XM, EX, XX },
   },
   /* PREGRP8 */
   {
     { "movups", XM, EX, XX },
     { "movss", XM, EX, XX },
+    { "movupd", XM, EX, XX },
+    { "movsd", XM, EX, XX },
   },
   /* PREGRP9 */
   {
     { "movups", EX, XM, XX },
     { "movss", EX, XM, XX },
+    { "movupd", EX, XM, XX },
+    { "movsd", EX, XM, XX },
   },
   /* PREGRP10 */
   {
     { "mulps", XM, EX, XX },
     { "mulss", XM, EX, XX },
+    { "mulpd", XM, EX, XX },
+    { "mulsd", XM, EX, XX },
   },
   /* PREGRP11 */
   {
     { "rcpps", XM, EX, XX },
     { "rcpss", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
   },
   /* PREGRP12 */
   {
     { "rsqrtps", XM, EX, XX },
     { "rsqrtss", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
   },
   /* PREGRP13 */
   {
     { "sqrtps", XM, EX, XX },
     { "sqrtss", XM, EX, XX },
+    { "sqrtpd", XM, EX, XX },
+    { "sqrtsd", XM, EX, XX },
   },
   /* PREGRP14 */
   {
     { "subps", XM, EX, XX },
     { "subss", XM, EX, XX },
-  }
+    { "subpd", XM, EX, XX },
+    { "subsd", XM, EX, XX },
+  },
+  /* PREGRP15 */
+  {
+    { "(bad)", XM, EX, XX },
+    { "cvtdq2pd", XM, EX, XX },
+    { "cvttpd2dq", XM, EX, XX },
+    { "cvtpd2dq", XM, EX, XX },
+  },
+  /* PREGRP16 */
+  {
+    { "cvtdq2ps", XM, EX, XX },
+    { "cvttps2dq",XM, EX, XX },
+    { "cvtps2dq",XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+  },
+  /* PREGRP17 */
+  {
+    { "cvtps2pd", XM, EX, XX },
+    { "cvtss2sd", XM, EX, XX },
+    { "cvtpd2ps", XM, EX, XX },
+    { "cvtsd2ss", XM, EX, XX },
+  },
+  /* PREGRP18 */
+  {
+    { "maskmovq", MX, MS, XX },
+    { "(bad)", XM, EX, XX },
+    { "maskmovdqu", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+  },
+  /* PREGRP19 */
+  {
+    { "movq", MX, EM, XX },
+    { "movdqu", XM, EX, XX },
+    { "movdqa", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+  },
+  /* PREGRP20 */
+  {
+    { "movq", EM, MX, XX },
+    { "movdqu", EX, XM, XX },
+    { "movdqa", EX, XM, XX },
+    { "(bad)", EX, XM, XX },
+  },
+  /* PREGRP21 */
+  {
+    { "(bad)", EX, XM, XX },
+    { "movq2dq", XM, MS, XX },
+    { "movq", EX, XM, XX },
+    { "movdq2q", MX, XS, XX },
+  },
+  /* PREGRP22 */
+  {
+    { "pshufw", MX, EM, Ib },
+    { "pshufhw", XM, EX, Ib },
+    { "pshufd", XM, EX, Ib },
+    { "pshuflw", XM, EX, Ib },
+  },
+  /* PREGRP23 */
+  {
+    { "movd", Ed, MX, XX },
+    { "movq", XM, EX, XX },
+    { "movd", Ed, XM, XX },
+    { "(bad)", Ed, XM, XX },
+  },
+  /* PREGRP24 */
+  {
+    { "(bad)", MX, EX, XX },
+    { "(bad)", XM, EX, XX },
+    { "punpckhqdq", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+  },
+  /* PREGRP25 */
+  {
+  { "movntq", Ev, MX, XX },
+  { "(bad)", Ev, XM, XX },
+  { "movntdq", Ev, XM, XX },
+  { "(bad)", Ev, XM, XX },
+  },
+  /* PREGRP26 */
+  {
+    { "(bad)", MX, EX, XX },
+    { "(bad)", XM, EX, XX },
+    { "punpcklqdq", XM, EX, XX },
+    { "(bad)", XM, EX, XX },
+  },
 };
 
 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
@@ -1951,13 +2774,39 @@ static const struct dis386 prefix_user_table[][2] = {
 static void
 ckprefix ()
 {
+  int newrex;
+  rex = 0;
   prefixes = 0;
   used_prefixes = 0;
+  rex_used = 0;
   while (1)
     {
       FETCH_DATA (the_info, codep + 1);
+      newrex = 0;
       switch (*codep)
 	{
+	/* REX prefixes family.  */
+	case 0x40:
+	case 0x41:
+	case 0x42:
+	case 0x43:
+	case 0x44:
+	case 0x45:
+	case 0x46:
+	case 0x47:
+	case 0x48:
+	case 0x49:
+	case 0x4a:
+	case 0x4b:
+	case 0x4c:
+	case 0x4d:
+	case 0x4e:
+	case 0x4f:
+	    if (mode_64bit)
+	      newrex = *codep;
+	    else
+	      return;
+	  break;
 	case 0xf3:
 	  prefixes |= PREFIX_REPZ;
 	  break;
@@ -2006,6 +2855,13 @@ ckprefix ()
 	default:
 	  return;
 	}
+      /* Rex is ignored when followed by another prefix.  */
+      if (rex)
+	{
+	  oappend (prefix_name (rex, 0));
+	  oappend (" ");
+	}
+      rex = newrex;
       codep++;
     }
 }
@@ -2020,6 +2876,39 @@ prefix_name (pref, sizeflag)
 {
   switch (pref)
     {
+    /* REX prefixes family.  */
+    case 0x40:
+      return "rex";
+    case 0x41:
+      return "rexZ";
+    case 0x42:
+      return "rexY";
+    case 0x43:
+      return "rexYZ";
+    case 0x44:
+      return "rexX";
+    case 0x45:
+      return "rexXZ";
+    case 0x46:
+      return "rexXY";
+    case 0x47:
+      return "rexXYZ";
+    case 0x48:
+      return "rex64";
+    case 0x49:
+      return "rex64Z";
+    case 0x4a:
+      return "rex64Y";
+    case 0x4b:
+      return "rex64YZ";
+    case 0x4c:
+      return "rex64X";
+    case 0x4d:
+      return "rex64XZ";
+    case 0x4e:
+      return "rex64XY";
+    case 0x4f:
+      return "rex64XYZ";
     case 0xf3:
       return "repz";
     case 0xf2:
@@ -2052,7 +2941,8 @@ prefix_name (pref, sizeflag)
 static char op1out[100], op2out[100], op3out[100];
 static int op_ad, op_index[3];
 static unsigned int op_address[3];
-static unsigned int start_pc;
+static unsigned int op_riprel[3];
+static bfd_vma start_pc;
 
 
 /*
@@ -2111,16 +3001,20 @@ print_insn_i386 (pc, info)
   int two_source_ops;
   char *first, *second, *third;
   int needcomma;
-  unsigned char need_modrm;
-  unsigned char uses_f3_prefix;
+  unsigned char uses_SSE_prefix;
   VOLATILE int sizeflag;
   VOLATILE int orig_sizeflag;
 
   struct dis_private priv;
   bfd_byte *inbuf = priv.the_buffer;
 
+  mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax
+		|| info->mach == bfd_mach_x86_64);
+
   if (info->mach == bfd_mach_i386_i386
-      || info->mach == bfd_mach_i386_i386_intel_syntax)
+      || info->mach == bfd_mach_x86_64
+      || info->mach == bfd_mach_i386_i386_intel_syntax
+      || info->mach == bfd_mach_x86_64_intel_syntax)
     sizeflag = AFLAG|DFLAG;
   else if (info->mach == bfd_mach_i386_i8086)
     sizeflag = 0;
@@ -2173,6 +3067,7 @@ print_insn_i386 (pc, info)
       return -1;
     }
 
+  obufp = obuf;
   ckprefix ();
 
   insn_codep = codep;
@@ -2180,8 +3075,6 @@ print_insn_i386 (pc, info)
   FETCH_DATA (info, codep + 1);
   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
 
-  obufp = obuf;
-
   if ((prefixes & PREFIX_FWAIT)
       && ((*codep < 0xd8) || (*codep > 0xdf)))
     {
@@ -2204,25 +3097,31 @@ print_insn_i386 (pc, info)
       else
         dp = &dis386_twobyte_att[*++codep];
       need_modrm = twobyte_has_modrm[*codep];
-      uses_f3_prefix = twobyte_uses_f3_prefix[*codep];
+      uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep];
     }
   else
     {
       if (intel_syntax)
-        dp = &dis386_intel[*codep];
+	if (mode_64bit)
+	  dp = &dis386_64_intel[*codep];
+	else
+	  dp = &dis386_intel[*codep];
       else
-        dp = &dis386_att[*codep];
+	if (mode_64bit)
+	  dp = &disx86_64_att[*codep];
+	else
+	  dp = &dis386_att[*codep];
       need_modrm = onebyte_has_modrm[*codep];
-      uses_f3_prefix = 0;
+      uses_SSE_prefix = 0;
     }
   codep++;
 
-  if (!uses_f3_prefix && (prefixes & PREFIX_REPZ))
+  if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ))
     {
       oappend ("repz ");
       used_prefixes |= PREFIX_REPZ;
     }
-  if (prefixes & PREFIX_REPNZ)
+  if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ))
     {
       oappend ("repnz ");
       used_prefixes |= PREFIX_REPNZ;
@@ -2233,17 +3132,44 @@ print_insn_i386 (pc, info)
       used_prefixes |= PREFIX_LOCK;
     }
 
-  if (prefixes & PREFIX_DATA)
-    sizeflag ^= DFLAG;
-
   if (prefixes & PREFIX_ADDR)
     {
       sizeflag ^= AFLAG;
-      if (sizeflag & AFLAG)
-        oappend ("addr32 ");
-      else
-	oappend ("addr16 ");
-      used_prefixes |= PREFIX_ADDR;
+      if (dp->bytemode2 != loop_jcxz_mode)
+	{
+	  if (sizeflag & AFLAG)
+	    oappend ("addr32 ");
+	  else
+	    oappend ("addr16 ");
+	  used_prefixes |= PREFIX_ADDR;
+	}
+    }
+
+  if (!uses_SSE_prefix && (prefixes & PREFIX_DATA))
+    {
+      sizeflag ^= DFLAG;
+      if (dp->bytemode2 == cond_jump_mode && dp->bytemode1 == v_mode)
+	{
+	  if (sizeflag & DFLAG)
+	    oappend ("data32 ");
+	  else
+	    oappend ("data16 ");
+	  used_prefixes |= PREFIX_DATA;
+	}
+    }
+
+  if (dp->bytemode2 == cond_jump_mode || dp->bytemode2 == loop_jcxz_mode)
+    {
+      if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS)
+	{
+	  oappend ("cs ");
+	  used_prefixes |= PREFIX_CS;
+	}
+      if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
+	{
+	  oappend ("ds ");
+	  used_prefixes |= PREFIX_DS;
+	}
     }
 
   if (need_modrm)
@@ -2260,6 +3186,7 @@ print_insn_i386 (pc, info)
     }
   else
     {
+      int index;
       if (dp->name == NULL)
 	{
 	  switch(dp->bytemode2)
@@ -2268,8 +3195,23 @@ print_insn_i386 (pc, info)
 	        dp = &grps[dp->bytemode1][reg];
 		break;
 	      case USE_PREFIX_USER_TABLE:
-		dp = &prefix_user_table[dp->bytemode1][prefixes & PREFIX_REPZ ? 1 : 0];
+		index = 0;
 		used_prefixes |= (prefixes & PREFIX_REPZ);
+		if (prefixes & PREFIX_REPZ)
+		  index = 1;
+		else
+		  {
+		    used_prefixes |= (prefixes & PREFIX_DATA);
+		    if (prefixes & PREFIX_DATA)
+		      index = 2;
+		    else
+		      {
+			used_prefixes |= (prefixes & PREFIX_REPNZ);
+			if (prefixes & PREFIX_REPNZ)
+			  index = 3;
+		      }
+		  }
+		dp = &prefix_user_table[dp->bytemode1][index];
 		break;
 	      default:
 		oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -2309,6 +3251,14 @@ print_insn_i386 (pc, info)
       (*info->fprintf_func) (info->stream, "%s", name);
       return 1;
     }
+  if (rex & ~rex_used)
+    {
+      const char *name;
+      name = prefix_name (rex | 0x40, orig_sizeflag);
+      if (name == NULL)
+	name = INTERNAL_DISASSEMBLER_ERROR;
+      (*info->fprintf_func) (info->stream, "%s ", name);
+    }
 
   obufp = obuf + strlen (obuf);
   for (i = strlen (obuf); i < 6; i++)
@@ -2336,7 +3286,7 @@ print_insn_i386 (pc, info)
   needcomma = 0;
   if (*first)
     {
-      if (op_index[0] != -1)
+      if (op_index[0] != -1 && !op_riprel[0])
 	(*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info);
       else
 	(*info->fprintf_func) (info->stream, "%s", first);
@@ -2346,7 +3296,7 @@ print_insn_i386 (pc, info)
     {
       if (needcomma)
 	(*info->fprintf_func) (info->stream, ",");
-      if (op_index[1] != -1)
+      if (op_index[1] != -1 && !op_riprel[1])
 	(*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info);
       else
 	(*info->fprintf_func) (info->stream, "%s", second);
@@ -2356,11 +3306,18 @@ print_insn_i386 (pc, info)
     {
       if (needcomma)
 	(*info->fprintf_func) (info->stream, ",");
-      if (op_index[2] != -1)
+      if (op_index[2] != -1 && !op_riprel[2])
 	(*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info);
       else
 	(*info->fprintf_func) (info->stream, "%s", third);
     }
+  for (i = 0; i < 3; i++)
+    if (op_index[i] != -1 && op_riprel[i])
+      {
+	(*info->fprintf_func) (info->stream, "        # ");
+	(*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
+						+ op_address[op_index[i]]), info);
+      }
   return codep - inbuf;
 }
 
@@ -2621,7 +3578,7 @@ static const struct dis386 float_reg[][8] = {
   },
   /* df */
   {
-    { "(bad)",	XX, XX, XX },
+    { "ffreep",	STi, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
     { "(bad)",	XX, XX, XX },
@@ -2705,6 +3662,8 @@ dofloat (sizeflag)
         OP_E (v_mode, sizeflag);
       return;
     }
+  /* skip mod/rm byte */
+  MODRM_CHECK;
   codep++;
 
   dp = &float_reg[floatop - 0xd8][reg];
@@ -2785,6 +3744,42 @@ putop (template, sizeflag)
 	case 'E':		/* For jcxz/jecxz */
 	  if (sizeflag & AFLAG)
 	    *obufp++ = 'e';
+	  used_prefixes |= (prefixes & PREFIX_ADDR);
+	  break;
+	case 'F':
+	  if ((prefixes & PREFIX_ADDR)
+#ifdef SUFFIX_ALWAYS
+	      || (sizeflag & SUFFIX_ALWAYS)
+#endif
+	      )
+	    {
+	      if (sizeflag & AFLAG)
+		*obufp++ = 'l';
+	      else
+		*obufp++ = 'w';
+	      used_prefixes |= (prefixes & PREFIX_ADDR);
+	    }
+	  break;
+	case 'I':
+          if (intel_syntax)
+            break;
+	  if (mode_64bit)
+	    *obufp++ = 'q';
+	  else
+	    {
+	      if ((prefixes & PREFIX_DATA)
+#ifdef SUFFIX_ALWAYS
+		  || (sizeflag & SUFFIX_ALWAYS)
+#endif
+		  )
+		{
+		  if (sizeflag & DFLAG)
+		    *obufp++ = 'l';
+		  else
+		    *obufp++ = 'w';
+		  used_prefixes |= (prefixes & PREFIX_DATA);
+	      }
+	    }
 	  break;
 	case 'L':
           if (intel_syntax)
@@ -2800,42 +3795,68 @@ putop (template, sizeflag)
 	  else
 	    used_prefixes |= PREFIX_FWAIT;
 	  break;
+	case 'O':
+	  USED_REX (REX_MODE64);
+	  if (rex & REX_MODE64)
+	      *obufp++ = 'o';
+	  else
+	    *obufp++ = 'd';
+	  break;
 	case 'P':
           if (intel_syntax)
             break;
 	  if ((prefixes & PREFIX_DATA)
+	      || (rex & REX_MODE64)
 #ifdef SUFFIX_ALWAYS
 	      || (sizeflag & SUFFIX_ALWAYS)
 #endif
 	      )
 	    {
-	      if (sizeflag & DFLAG)
-		*obufp++ = 'l';
+	      USED_REX (REX_MODE64);
+	      if (rex & REX_MODE64)
+		*obufp++ = 'q';
 	      else
-		*obufp++ = 'w';
-	      used_prefixes |= (prefixes & PREFIX_DATA);
+		{
+		   if (sizeflag & DFLAG)
+		      *obufp++ = 'l';
+		   else
+		     *obufp++ = 'w';
+		   used_prefixes |= (prefixes & PREFIX_DATA);
+		}
 	    }
 	  break;
 	case 'Q':
           if (intel_syntax)
             break;
+	  USED_REX (REX_MODE64);
 	  if (mod != 3
 #ifdef SUFFIX_ALWAYS
 	      || (sizeflag & SUFFIX_ALWAYS)
 #endif
 	      )
 	    {
-	      if (sizeflag & DFLAG)
-		*obufp++ = 'l';
+	      if (rex & REX_MODE64)
+		*obufp++ = 'q';
 	      else
-		*obufp++ = 'w';
-	      used_prefixes |= (prefixes & PREFIX_DATA);
+		{
+		  if (sizeflag & DFLAG)
+		    *obufp++ = 'l';
+		  else
+		    *obufp++ = 'w';
+		  used_prefixes |= (prefixes & PREFIX_DATA);
+		}
 	    }
 	  break;
 	case 'R':
+	  USED_REX (REX_MODE64);
           if (intel_syntax)
 	    {
-	      if (sizeflag & DFLAG)
+	      if (rex & REX_MODE64)
+		{
+		  *obufp++ = 'q';
+		  *obufp++ = 't';
+		}
+	      else if (sizeflag & DFLAG)
 		{
 		  *obufp++ = 'd';
 		  *obufp++ = 'q';
@@ -2848,12 +3869,15 @@ putop (template, sizeflag)
 	    }
 	  else
 	    {
-	      if (sizeflag & DFLAG)
+	      if (rex & REX_MODE64)
+		*obufp++ = 'q';
+	      else if (sizeflag & DFLAG)
 		*obufp++ = 'l';
 	      else
 		*obufp++ = 'w';
 	    }
-	  used_prefixes |= (prefixes & PREFIX_DATA);
+	  if (!(rex & REX_MODE64))
+	    used_prefixes |= (prefixes & PREFIX_DATA);
 	  break;
 	case 'S':
           if (intel_syntax)
@@ -2861,22 +3885,70 @@ putop (template, sizeflag)
 #ifdef SUFFIX_ALWAYS
 	  if (sizeflag & SUFFIX_ALWAYS)
 	    {
+	      if (rex & REX_MODE64)
+		*obufp++ = 'q';
+	      else
+		{
+		  if (sizeflag & DFLAG)
+		    *obufp++ = 'l';
+		  else
+		    *obufp++ = 'w';
+		  used_prefixes |= (prefixes & PREFIX_DATA);
+		}
+	    }
+#endif
+	  break;
+	case 'T':
+          if (intel_syntax)
+            break;
+	  if (mode_64bit)
+	    *obufp++ = 'q';
+	  else if (mod != 3
+#ifdef SUFFIX_ALWAYS
+		   || (sizeflag & SUFFIX_ALWAYS)
+#endif
+		  )
+	    {
 	      if (sizeflag & DFLAG)
 		*obufp++ = 'l';
 	      else
 		*obufp++ = 'w';
 	      used_prefixes |= (prefixes & PREFIX_DATA);
 	    }
-#endif
 	  break;
+	case 'X':
+	  if (prefixes & PREFIX_DATA)
+	    *obufp++ = 'd';
+	  else
+	    *obufp++ = 's';
+          used_prefixes |= (prefixes & PREFIX_DATA);
+	  break;
+	case 'Y':
+          if (intel_syntax)
+            break;
+	  if (rex & REX_MODE64)
+	    {
+	      USED_REX (REX_MODE64);
+	      *obufp++ = 'q';
+	    }
+	  break;
+	  /* implicit operand size 'l' for i386 or 'q' for x86-64 */
 	case 'W':
 	  /* operand size flag for cwtl, cbtw */
-	  if (sizeflag & DFLAG)
+	  USED_REX (0);
+	  if (rex)
+	    *obufp++ = 'l';
+	  else if (sizeflag & DFLAG)
 	    *obufp++ = 'w';
 	  else
 	    *obufp++ = 'b';
           if (intel_syntax)
 	    {
+	      if (rex)
+		{
+		  *obufp++ = 'q';
+		  *obufp++ = 'e';
+		}
 	      if (sizeflag & DFLAG)
 		{
 		  *obufp++ = 'd';
@@ -2887,7 +3959,8 @@ putop (template, sizeflag)
 		  *obufp++ = 'w';
 		}
 	    }
-	  used_prefixes |= (prefixes & PREFIX_DATA);
+	  if (!rex)
+	    used_prefixes |= (prefixes & PREFIX_DATA);
 	  break;
 	}
     }
@@ -2948,13 +4021,79 @@ OP_indirE (bytemode, sizeflag)
 }
 
 static void
+print_operand_value (buf, hex, disp)
+  char *buf;
+  int hex;
+  bfd_vma disp;
+{
+  if (mode_64bit)
+    {
+      if (hex)
+	{
+	  char tmp[30];
+	  int i;
+	  buf[0] = '0';
+	  buf[1] = 'x';
+	  sprintf_vma (tmp, disp);
+	  for (i = 0; tmp[i] == '0' && tmp[i+1]; i++);
+	  strcpy (buf + 2, tmp + i);
+	}
+      else
+	{
+	  bfd_signed_vma v = disp;
+	  char tmp[30];
+	  int i;
+	  if (v < 0)
+	    {
+	      *(buf++) = '-';
+	      v = -disp;
+	      /* Check for possible overflow on 0x8000000000000000 */
+	      if (v < 0)
+		{
+		  strcpy (buf, "9223372036854775808");
+		  return;
+		}
+	    }
+	  if (!v)
+	    {
+	      strcpy (buf, "0");
+	      return;
+	    }
+
+	  i = 0;
+	  tmp[29] = 0;
+	  while (v)
+	    {
+	      tmp[28-i] = (v % 10) + '0';
+	      v /= 10;
+	      i++;
+	    }
+	  strcpy (buf, tmp + 29 - i);
+	}
+    }
+  else
+    {
+      if (hex)
+	sprintf (buf, "0x%x", (unsigned int) disp);
+      else
+	sprintf (buf, "%d", (int) disp);
+    }
+}
+
+static void
 OP_E (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
-  int disp;
+  bfd_vma disp;
+  int add = 0;
+  int riprel = 0;
+  USED_REX (REX_EXTZ);
+  if (rex & REX_EXTZ)
+    add += 8;
 
   /* skip mod/rm byte */
+  MODRM_CHECK;
   codep++;
 
   if (mod == 3)
@@ -2962,23 +4101,41 @@ OP_E (bytemode, sizeflag)
       switch (bytemode)
 	{
 	case b_mode:
-	  oappend (names8[rm]);
+	  USED_REX (0);
+	  if (rex)
+	    oappend (names8rex[rm + add]);
+	  else
+	    oappend (names8[rm + add]);
 	  break;
 	case w_mode:
-	  oappend (names16[rm]);
+	  oappend (names16[rm + add]);
 	  break;
 	case d_mode:
-	  oappend (names32[rm]);
+	  oappend (names32[rm + add]);
+	  break;
+	case q_mode:
+	  oappend (names64[rm + add]);
+	  break;
+	case m_mode:
+	  if (mode_64bit)
+	    oappend (names64[rm + add]);
+	  else
+	    oappend (names32[rm + add]);
 	  break;
 	case v_mode:
-	  if (sizeflag & DFLAG)
-	    oappend (names32[rm]);
+	  USED_REX (REX_MODE64);
+	  if (rex & REX_MODE64)
+	    oappend (names64[rm + add]);
+	  else if (sizeflag & DFLAG)
+	    oappend (names32[rm + add]);
 	  else
-	    oappend (names16[rm]);
+	    oappend (names16[rm + add]);
 	  used_prefixes |= (prefixes & PREFIX_DATA);
 	  break;
 	case 0:
-	  if ( !(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */))
+	  if ( !(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */)
+	      && !(codep[-2] == 0xAE && codep[-1] == 0xF0 /* mfence */)
+	      && !(codep[-2] == 0xAE && codep[-1] == 0xe8 /* lfence */))
 	    BadOp();	/* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
 	  break;
 	default:
@@ -3010,16 +4167,24 @@ OP_E (bytemode, sizeflag)
 	  scale = (*codep >> 6) & 3;
 	  index = (*codep >> 3) & 7;
 	  base = *codep & 7;
+	  USED_REX (REX_EXTY);
+	  USED_REX (REX_EXTZ);
+	  if (rex & REX_EXTY)
+	    index += 8;
+	  if (rex & REX_EXTZ)
+	    base += 8;
 	  codep++;
 	}
 
       switch (mod)
 	{
 	case 0:
-	  if (base == 5)
+	  if ((base & 7) == 5)
 	    {
 	      havebase = 0;
-	      disp = get32 ();
+	      if (mode_64bit && !havesib)
+		riprel = 1;
+	      disp = get32s ();
 	    }
 	  break;
 	case 1:
@@ -3029,15 +4194,20 @@ OP_E (bytemode, sizeflag)
 	    disp -= 0x100;
 	  break;
 	case 2:
-	  disp = get32 ();
+	  disp = get32s ();
 	  break;
 	}
 
       if (!intel_syntax)
-        if (mod != 0 || base == 5)
+        if (mod != 0 || (base & 7) == 5)
           {
-            sprintf (scratchbuf, "0x%x", disp);
+	    print_operand_value (scratchbuf, !riprel, disp);
             oappend (scratchbuf);
+	    if (riprel)
+	      {
+		set_op (disp, 1);
+		oappend ("(%rip)");
+	      }
           }
 
       if (havebase || (havesib && (index != 4 || scale != 0)))
@@ -3047,28 +4217,39 @@ OP_E (bytemode, sizeflag)
               switch (bytemode)
                 {
                 case b_mode:
-                  oappend("BYTE PTR ");
+                  oappend ("BYTE PTR ");
                   break;
                 case w_mode:
-                  oappend("WORD PTR ");
+                  oappend ("WORD PTR ");
                   break;
                 case v_mode:
-                  oappend("DWORD PTR ");
+                  oappend ("DWORD PTR ");
                   break;
                 case d_mode:
-                  oappend("QWORD PTR ");
+                  oappend ("QWORD PTR ");
                   break;
+                case m_mode:
+		  if (mode_64bit)
+		    oappend ("DWORD PTR ");
+		  else
+		    oappend ("QWORD PTR ");
+		  break;
                 case x_mode:
-                  oappend("XWORD PTR ");
+                  oappend ("XWORD PTR ");
                   break;
                 default:
                   break;
                 }
              }
 	  *obufp++ = open_char;
+	  if (intel_syntax && riprel)
+	    oappend ("rip + ");
           *obufp = '\0';
+	  USED_REX (REX_EXTZ);
+	  if (!havesib && (rex & REX_EXTZ))
+	    base += 8;
 	  if (havebase)
-	    oappend (names32[base]);
+	    oappend (mode_64bit ? names64[base] : names32[base]);
 	  if (havesib)
 	    {
 	      if (index != 4)
@@ -3080,10 +4261,10 @@ OP_E (bytemode, sizeflag)
                           *obufp++ = separator_char;
                           *obufp = '\0';
                         }
-                      sprintf (scratchbuf, "%s", names32[index]);
+                      sprintf (scratchbuf, "%s", mode_64bit ? names64[index] : names32[index]);
                     }
                   else
-		    sprintf (scratchbuf, ",%s", names32[index]);
+		    sprintf (scratchbuf, ",%s", mode_64bit ? names64[index] : names32[index]);
 		  oappend (scratchbuf);
 		}
               if (!intel_syntax
@@ -3099,17 +4280,12 @@ OP_E (bytemode, sizeflag)
                 }
 	    }
           if (intel_syntax)
-            if (mod != 0 || base == 5)
+            if (mod != 0 || (base & 7) == 5)
               {
                 /* Don't print zero displacements */
-                if (disp > 0)
+                if (disp != 0)
                   {
-                    sprintf (scratchbuf, "+%d", disp);
-                    oappend (scratchbuf);
-                  }
-                else if (disp < 0)
-                  {
-                    sprintf (scratchbuf, "%d", disp);
+		    print_operand_value (scratchbuf, 0, disp);
                     oappend (scratchbuf);
                   }
               }
@@ -3119,7 +4295,7 @@ OP_E (bytemode, sizeflag)
 	}
       else if (intel_syntax)
         {
-          if (mod != 0 || base == 5)
+          if (mod != 0 || (base & 7) == 5)
             {
 	      if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
 			      | PREFIX_ES | PREFIX_FS | PREFIX_GS))
@@ -3129,7 +4305,7 @@ OP_E (bytemode, sizeflag)
 		  oappend (names_seg[3]);
 		  oappend (":");
 		}
-              sprintf (scratchbuf, "0x%x", disp);
+	      print_operand_value (scratchbuf, 1, disp);
               oappend (scratchbuf);
             }
         }
@@ -3139,7 +4315,7 @@ OP_E (bytemode, sizeflag)
       switch (mod)
 	{
 	case 0:
-	  if (rm == 6)
+	  if ((rm & 7) == 6)
 	    {
 	      disp = get16 ();
 	      if ((disp & 0x8000) != 0)
@@ -3160,17 +4336,17 @@ OP_E (bytemode, sizeflag)
 	}
 
       if (!intel_syntax)
-        if (mod != 0 || rm == 6)
+        if (mod != 0 || (rm & 7) == 6)
           {
-            sprintf (scratchbuf, "%d", disp);
+	    print_operand_value (scratchbuf, 0, disp);
             oappend (scratchbuf);
           }
 
-      if (mod != 0 || rm != 6)
+      if (mod != 0 || (rm & 7) != 6)
 	{
 	  *obufp++ = open_char;
           *obufp = '\0';
-	  oappend (index16[rm]);
+	  oappend (index16[rm + add]);
           *obufp++ = close_char;
           *obufp = '\0';
 	}
@@ -3182,22 +4358,36 @@ OP_G (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
+  int add = 0;
+  USED_REX (REX_EXTX);
+  if (rex & REX_EXTX)
+    add += 8;
   switch (bytemode)
     {
     case b_mode:
-      oappend (names8[reg]);
+      USED_REX (0);
+      if (rex)
+	oappend (names8rex[reg + add]);
+      else
+	oappend (names8[reg + add]);
       break;
     case w_mode:
-      oappend (names16[reg]);
+      oappend (names16[reg + add]);
       break;
     case d_mode:
-      oappend (names32[reg]);
+      oappend (names32[reg + add]);
+      break;
+    case q_mode:
+      oappend (names64[reg + add]);
       break;
     case v_mode:
-      if (sizeflag & DFLAG)
-	oappend (names32[reg]);
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	oappend (names64[reg + add]);
+      else if (sizeflag & DFLAG)
+	oappend (names32[reg + add]);
       else
-	oappend (names16[reg]);
+	oappend (names16[reg + add]);
       used_prefixes |= (prefixes & PREFIX_DATA);
       break;
     default:
@@ -3206,16 +4396,56 @@ OP_G (bytemode, sizeflag)
     }
 }
 
-static int
+static bfd_vma
+get64 ()
+{
+  unsigned int a = 0;
+  unsigned int b = 0;
+  bfd_vma x = 0;
+
+#ifdef BFD64
+  FETCH_DATA (the_info, codep + 8);
+  a = *codep++ & 0xff;
+  a |= (*codep++ & 0xff) << 8;
+  a |= (*codep++ & 0xff) << 16;
+  a |= (*codep++ & 0xff) << 24;
+  b |= (*codep++ & 0xff);
+  b |= (*codep++ & 0xff) << 8;
+  b |= (*codep++ & 0xff) << 16;
+  b |= (*codep++ & 0xff) << 24;
+  x = a + ((bfd_vma) b << 32);
+#else
+  abort();
+#endif
+  return x;
+}
+
+static bfd_signed_vma
 get32 ()
 {
-  int x = 0;
+  bfd_signed_vma x = 0;
 
   FETCH_DATA (the_info, codep + 4);
-  x = *codep++ & 0xff;
-  x |= (*codep++ & 0xff) << 8;
-  x |= (*codep++ & 0xff) << 16;
-  x |= (*codep++ & 0xff) << 24;
+  x = *codep++ & (bfd_signed_vma) 0xff;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
+  return x;
+}
+
+static bfd_signed_vma
+get32s ()
+{
+  bfd_signed_vma x = 0;
+
+  FETCH_DATA (the_info, codep + 4);
+  x = *codep++ & (bfd_signed_vma) 0xff;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
+  x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
+
+  x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
+
   return x;
 }
 
@@ -3231,11 +4461,13 @@ get16 ()
 }
 
 static void
-set_op (op)
+set_op (op, riprel)
      unsigned int op;
+     int riprel;
 {
   op_index[op_ad] = op_ad;
   op_address[op_ad] = op;
+  op_riprel[op_ad] = riprel;
 }
 
 static void
@@ -3244,6 +4476,60 @@ OP_REG (code, sizeflag)
      int sizeflag;
 {
   const char *s;
+  int add = 0;
+  USED_REX (REX_EXTZ);
+  if (rex & REX_EXTZ)
+    add = 8;
+
+  switch (code)
+    {
+    case indir_dx_reg:
+      s = "(%dx)";
+      break;
+    case ax_reg: case cx_reg: case dx_reg: case bx_reg:
+    case sp_reg: case bp_reg: case si_reg: case di_reg:
+      s = names16[code - ax_reg + add];
+      break;
+    case es_reg: case ss_reg: case cs_reg:
+    case ds_reg: case fs_reg: case gs_reg:
+      s = names_seg[code - es_reg + add];
+      break;
+    case al_reg: case ah_reg: case cl_reg: case ch_reg:
+    case dl_reg: case dh_reg: case bl_reg: case bh_reg:
+      USED_REX (0);
+      if (rex)
+	s = names8rex[code - al_reg + add];
+      else
+	s = names8[code - al_reg];
+      break;
+    case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
+    case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	s = names64[code - eAX_reg + add];
+      else if (sizeflag & DFLAG)
+	s = names32[code - eAX_reg + add];
+      else
+	s = names16[code - eAX_reg + add];
+      used_prefixes |= (prefixes & PREFIX_DATA);
+      break;
+    case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
+    case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
+      s = names64[code - rAX_reg + add];
+      break;
+    default:
+      s = INTERNAL_DISASSEMBLER_ERROR;
+      break;
+    }
+  oappend (s);
+}
+
+static void
+OP_IMREG (code, sizeflag)
+     int code;
+     int sizeflag;
+{
+  const char *s;
 
   switch (code)
     {
@@ -3260,11 +4546,18 @@ OP_REG (code, sizeflag)
       break;
     case al_reg: case ah_reg: case cl_reg: case ch_reg:
     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
-      s = names8[code - al_reg];
+      USED_REX (0);
+      if (rex)
+	s = names8rex[code - al_reg];
+      else
+	s = names8[code - al_reg];
       break;
     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
-      if (sizeflag & DFLAG)
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	s = names64[code - eAX_reg];
+      else if (sizeflag & DFLAG)
 	s = names32[code - eAX_reg];
       else
 	s = names16[code - eAX_reg];
@@ -3282,22 +4575,37 @@ OP_I (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
-  int op;
+  bfd_signed_vma op;
+  bfd_signed_vma mask = -1;
 
   switch (bytemode)
     {
     case b_mode:
       FETCH_DATA (the_info, codep + 1);
-      op = *codep++ & 0xff;
+      op = *codep++;
+      mask = 0xff;
+      break;
+    case q_mode:
+      op = get32s ();
       break;
     case v_mode:
-      if (sizeflag & DFLAG)
-	op = get32 ();
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	op = get32s ();
+      else if (sizeflag & DFLAG)
+	{
+	  op = get32 ();
+	  mask = 0xffffffff;
+	}
       else
-	op = get16 ();
+	{
+	  op = get16 ();
+	  mask = 0xfffff;
+	}
       used_prefixes |= (prefixes & PREFIX_DATA);
       break;
     case w_mode:
+      mask = 0xfffff;
       op = get16 ();
       break;
     default:
@@ -3305,10 +4613,56 @@ OP_I (bytemode, sizeflag)
       return;
     }
 
-  if (intel_syntax)
-    sprintf (scratchbuf, "0x%x", op);
-  else
-    sprintf (scratchbuf, "$0x%x", op);
+  op &= mask;
+  scratchbuf[0] = '$';
+  print_operand_value (scratchbuf + !intel_syntax, 1, op);
+  oappend (scratchbuf);
+  scratchbuf[0] = '\0';
+}
+
+static void
+OP_I64 (bytemode, sizeflag)
+     int bytemode;
+     int sizeflag;
+{
+  bfd_signed_vma op;
+  bfd_signed_vma mask = -1;
+
+  switch (bytemode)
+    {
+    case b_mode:
+      FETCH_DATA (the_info, codep + 1);
+      op = *codep++;
+      mask = 0xff;
+      break;
+    case v_mode:
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	op = get64 ();
+      else if (sizeflag & DFLAG)
+	{
+	  op = get32 ();
+	  mask = 0xffffffff;
+	}
+      else
+	{
+	  op = get16 ();
+	  mask = 0xfffff;
+	}
+      used_prefixes |= (prefixes & PREFIX_DATA);
+      break;
+    case w_mode:
+      mask = 0xfffff;
+      op = get16 ();
+      break;
+    default:
+      oappend (INTERNAL_DISASSEMBLER_ERROR);
+      return;
+    }
+
+  op &= mask;
+  scratchbuf[0] = '$';
+  print_operand_value (scratchbuf + !intel_syntax, 1, op);
   oappend (scratchbuf);
   scratchbuf[0] = '\0';
 }
@@ -3318,7 +4672,8 @@ OP_sI (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
-  int op;
+  bfd_signed_vma op;
+  bfd_signed_vma mask = -1;
 
   switch (bytemode)
     {
@@ -3327,12 +4682,20 @@ OP_sI (bytemode, sizeflag)
       op = *codep++;
       if ((op & 0x80) != 0)
 	op -= 0x100;
+      mask = 0xffffffff;
       break;
     case v_mode:
-      if (sizeflag & DFLAG)
-	op = get32 ();
+      USED_REX (REX_MODE64);
+      if (rex & REX_MODE64)
+	op = get32s ();
+      else if (sizeflag & DFLAG)
+	{
+	  op = get32s ();
+	  mask = 0xffffffff;
+	}
       else
 	{
+	  mask = 0xffffffff;
 	  op = get16();
 	  if ((op & 0x8000) != 0)
 	    op -= 0x10000;
@@ -3341,6 +4704,7 @@ OP_sI (bytemode, sizeflag)
       break;
     case w_mode:
       op = get16 ();
+      mask = 0xffffffff;
       if ((op & 0x8000) != 0)
 	op -= 0x10000;
       break;
@@ -3348,10 +4712,9 @@ OP_sI (bytemode, sizeflag)
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
     }
-  if (intel_syntax)
-    sprintf (scratchbuf, "%d", op);
-  else
-    sprintf (scratchbuf, "$0x%x", op);
+
+  scratchbuf[0] = '$';
+  print_operand_value (scratchbuf + 1, 1, op);
   oappend (scratchbuf);
 }
 
@@ -3360,7 +4723,7 @@ OP_J (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
-  int disp;
+  bfd_vma disp;
   int mask = -1;
 
   switch (bytemode)
@@ -3373,7 +4736,7 @@ OP_J (bytemode, sizeflag)
       break;
     case v_mode:
       if (sizeflag & DFLAG)
-	disp = get32 ();
+	disp = get32s ();
       else
 	{
 	  disp = get16 ();
@@ -3382,15 +4745,14 @@ OP_J (bytemode, sizeflag)
 	     displacement is added!  */
 	  mask = 0xffff;
 	}
-      used_prefixes |= (prefixes & PREFIX_DATA);
       break;
     default:
       oappend (INTERNAL_DISASSEMBLER_ERROR);
       return;
     }
   disp = (start_pc + codep - start_codep + disp) & mask;
-  set_op (disp);
-  sprintf (scratchbuf, "0x%x", disp);
+  set_op (disp, 0);
+  print_operand_value (scratchbuf, 1, disp);
   oappend (scratchbuf);
 }
 
@@ -3432,11 +4794,11 @@ OP_DIR (dummy, sizeflag)
 
 /* ARGSUSED */
 static void
-OP_OFF (ignore, sizeflag)
-     int ignore ATTRIBUTE_UNUSED;
+OP_OFF (ignored, sizeflag)
+     int ignored ATTRIBUTE_UNUSED;
      int sizeflag;
 {
-  int off;
+  bfd_vma off;
 
   append_seg ();
 
@@ -3454,7 +4816,31 @@ OP_OFF (ignore, sizeflag)
 	  oappend (":");
 	}
     }
-  sprintf (scratchbuf, "0x%x", off);
+  print_operand_value (scratchbuf, 1, off);
+  oappend (scratchbuf);
+}
+/* ARGSUSED */
+static void
+OP_OFF64 (ignored, sizeflag)
+     int ignored ATTRIBUTE_UNUSED;
+     int sizeflag ATTRIBUTE_UNUSED;
+{
+  bfd_vma off;
+
+  append_seg ();
+
+  off = get64();
+
+  if (intel_syntax)
+    {
+      if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
+		        | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
+	{
+	  oappend (names_seg[3]);
+	  oappend (":");
+	}
+    }
+  print_operand_value (scratchbuf, 1, off);
   oappend (scratchbuf);
 }
 
@@ -3465,7 +4851,10 @@ ptr_reg (code, sizeflag)
 {
   const char *s;
   oappend ("(");
-  if (sizeflag & AFLAG)
+  USED_REX (REX_MODE64);
+  if (rex & REX_MODE64)
+    s = names64[code - eAX_reg];
+  else if (sizeflag & AFLAG)
     s = names32[code - eAX_reg];
   else
     s = names16[code - eAX_reg];
@@ -3505,7 +4894,11 @@ OP_C (dummy, sizeflag)
      int dummy ATTRIBUTE_UNUSED;
      int sizeflag ATTRIBUTE_UNUSED;
 {
-  sprintf (scratchbuf, "%%cr%d", reg);
+  int add = 0;
+  USED_REX (REX_EXTX);
+  if (rex & REX_EXTX)
+    add = 8;
+  sprintf (scratchbuf, "%%cr%d", reg+add);
   oappend (scratchbuf);
 }
 
@@ -3515,7 +4908,11 @@ OP_D (dummy, sizeflag)
      int dummy ATTRIBUTE_UNUSED;
      int sizeflag ATTRIBUTE_UNUSED;
 {
-  sprintf (scratchbuf, "%%db%d", reg);
+  int add = 0;
+  USED_REX (REX_EXTX);
+  if (rex & REX_EXTX)
+    add = 8;
+  sprintf (scratchbuf, "%%db%d", reg+add);
   oappend (scratchbuf);
 }
 
@@ -3545,7 +4942,15 @@ OP_MMX (ignore, sizeflag)
      int ignore ATTRIBUTE_UNUSED;
      int sizeflag ATTRIBUTE_UNUSED;
 {
-  sprintf (scratchbuf, "%%mm%d", reg);
+  int add = 0;
+  USED_REX (REX_EXTX);
+  if (rex & REX_EXTX)
+    add = 8;
+  used_prefixes |= (prefixes & PREFIX_DATA);
+  if (prefixes & PREFIX_DATA)
+    sprintf (scratchbuf, "%%xmm%d", reg + add);
+  else
+    sprintf (scratchbuf, "%%mm%d", reg + add);
   oappend (scratchbuf);
 }
 
@@ -3554,7 +4959,11 @@ OP_XMM (bytemode, sizeflag)
      int bytemode ATTRIBUTE_UNUSED;
      int sizeflag ATTRIBUTE_UNUSED;
 {
-  sprintf (scratchbuf, "%%xmm%d", reg);
+  int add = 0;
+  USED_REX (REX_EXTX);
+  if (rex & REX_EXTX)
+    add = 8;
+  sprintf (scratchbuf, "%%xmm%d", reg + add);
   oappend (scratchbuf);
 }
 
@@ -3563,14 +4972,24 @@ OP_EM (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
+  int add = 0;
   if (mod != 3)
     {
       OP_E (bytemode, sizeflag);
       return;
     }
+  USED_REX (REX_EXTZ);
+  if (rex & REX_EXTZ)
+    add = 8;
 
+  /* skip mod/rm byte */
+  MODRM_CHECK;
   codep++;
-  sprintf (scratchbuf, "%%mm%d", rm);
+  used_prefixes |= (prefixes & PREFIX_DATA);
+  if (prefixes & PREFIX_DATA)
+    sprintf (scratchbuf, "%%xmm%d", rm + add);
+  else
+    sprintf (scratchbuf, "%%mm%d", rm + add);
   oappend (scratchbuf);
 }
 
@@ -3579,14 +4998,20 @@ OP_EX (bytemode, sizeflag)
      int bytemode;
      int sizeflag;
 {
+  int add = 0;
   if (mod != 3)
     {
       OP_E (bytemode, sizeflag);
       return;
     }
+  USED_REX (REX_EXTZ);
+  if (rex & REX_EXTZ)
+    add = 8;
 
+  /* skip mod/rm byte */
+  MODRM_CHECK;
   codep++;
-  sprintf (scratchbuf, "%%xmm%d", rm);
+  sprintf (scratchbuf, "%%xmm%d", rm + add);
   oappend (scratchbuf);
 }
 
@@ -3601,6 +5026,17 @@ OP_MS (bytemode, sizeflag)
     BadOp();
 }
 
+static void
+OP_XS (bytemode, sizeflag)
+     int bytemode;
+     int sizeflag;
+{
+  if (mod == 3)
+    OP_EX (bytemode, sizeflag);
+  else
+    BadOp();
+}
+
 static const char *Suffix3DNow[] = {
 /* 00 */	NULL,		NULL,		NULL,		NULL,
 /* 04 */	NULL,		NULL,		NULL,		NULL,
@@ -3719,9 +5155,24 @@ OP_SIMD_Suffix (bytemode, sizeflag)
   cmp_type = *codep++ & 0xff;
   if (cmp_type < 8)
     {
-      sprintf (scratchbuf, "cmp%s%cs",
-	       simd_cmp_op[cmp_type],
-	       prefixes & PREFIX_REPZ ? 's' : 'p');
+      char suffix1 = 'p', suffix2 = 's';
+      used_prefixes |= (prefixes & PREFIX_REPZ);
+      if (prefixes & PREFIX_REPZ)
+	suffix1 = 's';
+      else
+	{
+	  used_prefixes |= (prefixes & PREFIX_DATA);
+	  if (prefixes & PREFIX_DATA)
+	    suffix2 = 'd';
+	  else
+	    {
+	      used_prefixes |= (prefixes & PREFIX_REPNZ);
+	      if (prefixes & PREFIX_REPNZ)
+		suffix1 = 's', suffix2 = 'd';
+	    }
+	}
+      sprintf (scratchbuf, "cmp%s%c%c",
+	       simd_cmp_op[cmp_type], suffix1, suffix2);
       used_prefixes |= (prefixes & PREFIX_REPZ);
       oappend (scratchbuf);
     }
diff --git a/gnu/usr.bin/binutils/opcodes/i960-dis.c b/gnu/usr.bin/binutils/opcodes/i960-dis.c
index 79820850b4f..90b170a3bb8 100644
--- a/gnu/usr.bin/binutils/opcodes/i960-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/i960-dis.c
@@ -1,5 +1,6 @@
 /* Disassemble i80960 instructions.
-   Copyright (C) 1990, 91, 93, 94, 95, 96, 1998 Free Software Foundation, Inc.
+   Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000
+   Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
diff --git a/gnu/usr.bin/binutils/opcodes/m68k-dis.c b/gnu/usr.bin/binutils/opcodes/m68k-dis.c
index 10c461dae59..fd7d912aec1 100644
--- a/gnu/usr.bin/binutils/opcodes/m68k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/m68k-dis.c
@@ -1,5 +1,6 @@
 /* Print Motorola 68k instructions.
-   Copyright 1986, 87, 89, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+   Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
+   1998, 1999, 2000, 2001
    Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify
@@ -45,14 +46,18 @@ static int
 print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *,
 			bfd_vma, disassemble_info *));
 
-CONST char * CONST fpcr_names[] = {
-  "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
-  "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"};
+CONST char * CONST fpcr_names[] =
+  {
+    "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
+    "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
+  };
 
-static char *const reg_names[] = {
-  "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
-  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
-  "%ps", "%pc"};
+static char *const reg_names[] =
+  {
+    "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
+    "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
+    "%ps", "%pc"
+  };
 
 /* Sign-extend an (unsigned char). */
 #if __STDC__ == 1
@@ -151,16 +156,17 @@ fetch_data (info, addr)
 /* This function is used to print to the bit-bucket. */
 static int
 #ifdef __STDC__
-dummy_printer (FILE * file, const char * format, ...)
+dummy_printer (FILE * file ATTRIBUTE_UNUSED,
+	       const char * format ATTRIBUTE_UNUSED, ...)
 #else
-dummy_printer (file) FILE *file;
+dummy_printer (file) FILE *file ATTRIBUTE_UNUSED;
 #endif
  { return 0; }
 
 static void
 dummy_print_address (vma, info)
-     bfd_vma vma;
-     struct disassemble_info *info;
+     bfd_vma vma ATTRIBUTE_UNUSED;
+     struct disassemble_info *info ATTRIBUTE_UNUSED;
 {
 }
 
@@ -177,7 +183,7 @@ print_insn_m68k (memaddr, info)
   unsigned char *save_p;
   register const char *d;
   register unsigned long bestmask;
-  const struct m68k_opcode *best = 0;
+  const struct m68k_opcode *best;
   unsigned int arch_mask;
   struct private priv;
   bfd_byte *buffer = priv.the_buffer;
@@ -227,6 +233,7 @@ print_insn_m68k (memaddr, info)
     /* Error return.  */
     return -1;
 
+  best = NULL;
   switch (info->mach)
     {
     default:
@@ -254,6 +261,18 @@ print_insn_m68k (memaddr, info)
     case bfd_mach_m68060:
       arch_mask = m68060;
       break;
+    case bfd_mach_mcf5200:
+      arch_mask = mcf5200;
+      break;
+    case bfd_mach_mcf5206e:
+      arch_mask = mcf5206e;
+      break;
+    case bfd_mach_mcf5307:
+      arch_mask = mcf5307;
+      break;
+    case bfd_mach_mcf5407:
+      arch_mask = mcf5407;
+      break;
     }
 
   arch_mask |= m68881 | m68851;
@@ -318,7 +337,7 @@ print_insn_m68k (memaddr, info)
 	}
     }
 
-  if (best == 0)
+  if (best == NULL)
     goto invalid;
 
   /* Point at first word of argument data,
diff --git a/gnu/usr.bin/binutils/opcodes/m68k-opc.c b/gnu/usr.bin/binutils/opcodes/m68k-opc.c
index 49ce5de704b..84451fbe30c 100644
--- a/gnu/usr.bin/binutils/opcodes/m68k-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/m68k-opc.c
@@ -1,6 +1,7 @@
 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
-   Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999
-   Free Software Foundation.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000, 2001
+   Free Software Foundation, Inc.
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -130,20 +131,20 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bgtw",	one(0067000),	one(0177777), "BW", m68000up | mcf },
 {"blew",	one(0067400),	one(0177777), "BW", m68000up | mcf },
 
-{"bhil",	one(0061377),	one(0177777), "BL", m68020up | cpu32 },
-{"blsl",	one(0061777),	one(0177777), "BL", m68020up | cpu32 },
-{"bccl",	one(0062377),	one(0177777), "BL", m68020up | cpu32 },
-{"bcsl",	one(0062777),	one(0177777), "BL", m68020up | cpu32 },
-{"bnel",	one(0063377),	one(0177777), "BL", m68020up | cpu32 },
-{"beql",	one(0063777),	one(0177777), "BL", m68020up | cpu32 },
-{"bvcl",	one(0064377),	one(0177777), "BL", m68020up | cpu32 },
-{"bvsl",	one(0064777),	one(0177777), "BL", m68020up | cpu32 },
-{"bpll",	one(0065377),	one(0177777), "BL", m68020up | cpu32 },
-{"bmil",	one(0065777),	one(0177777), "BL", m68020up | cpu32 },
-{"bgel",	one(0066377),	one(0177777), "BL", m68020up | cpu32 },
-{"bltl",	one(0066777),	one(0177777), "BL", m68020up | cpu32 },
-{"bgtl",	one(0067377),	one(0177777), "BL", m68020up | cpu32 },
-{"blel",	one(0067777),	one(0177777), "BL", m68020up | cpu32 },
+{"bhil",	one(0061377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"blsl",	one(0061777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bccl",	one(0062377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bcsl",	one(0062777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bnel",	one(0063377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"beql",	one(0063777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bvcl",	one(0064377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bvsl",	one(0064777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bpll",	one(0065377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bmil",	one(0065777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bgel",	one(0066377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bltl",	one(0066777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"bgtl",	one(0067377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
+{"blel",	one(0067777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
 
 {"bhis",	one(0061000),	one(0177400), "BB", m68000up | mcf },
 {"blss",	one(0061400),	one(0177400), "BB", m68000up | mcf },
@@ -198,7 +199,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bkpt",	one(0044110),		one(0177770), "ts", m68010up },
 
 {"braw",	one(0060000),	one(0177777), "BW", m68000up | mcf },
-{"bral",	one(0060377),	one(0177777), "BL", m68020up | cpu32 },
+{"bral",	one(0060377),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
 {"bras",	one(0060000),	one(0177400), "BB", m68000up | mcf },
 
 {"bset",	one(0000700),	one(0170700), "Dd$s", m68000up },
@@ -207,7 +208,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"bset",	one(0004300),	one(0177700), "#bqs", mcf },
 
 {"bsrw",	one(0060400),	one(0177777), "BW", m68000up | mcf },
-{"bsrl",	one(0060777),	one(0177777), "BL", m68020up | cpu32 },
+{"bsrl",	one(0060777),	one(0177777), "BL", m68020up | cpu32 | mcf5407},
 {"bsrs",	one(0060400),	one(0177400), "BB", m68000up | mcf },
 
 {"btst",	one(0000400),	one(0170700), "Dd;b", m68000up | mcf },
@@ -241,8 +242,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"cinvp",	one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
 
 {"cpusha",	one(0xf420|SCOPE_ALL),  one(0xff38), "ce",   m68040up },
-{"cpushl",	one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up },
-{"cpushl",	one(0x04e8),		one(0xfff8), "as",   mcf },
+{"cpushl",	one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcf },
 {"cpushp",	one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
 
 #undef SCOPE_LINE
@@ -261,7 +261,9 @@ const struct m68k_opcode m68k_opcodes[] =
 {"cmpal",	one(0130700),	one(0170700), "*lAd", m68000up | mcf },
 
 {"cmpib",	one(0006000),	one(0177700), "#b@s", m68000up },
+{"cmpib",	one(0006000),	one(0177700), "#bDs", mcf5407 },
 {"cmpiw",	one(0006100),	one(0177700), "#w@s", m68000up },
+{"cmpiw",	one(0006100),	one(0177700), "#wDs", mcf5407 },
 {"cmpil",	one(0006200),	one(0177700), "#l@s", m68000up },
 {"cmpil",	one(0006200),	one(0177700), "#lDs", mcf },
 
@@ -271,12 +273,15 @@ const struct m68k_opcode m68k_opcodes[] =
 
 /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions.  */
 {"cmpb",	one(0006000),	one(0177700), "#b@s", m68000up },
+{"cmpb",	one(0006000),	one(0177700), "#bDs", mcf5407 },
 {"cmpb",	one(0130410),	one(0170770), "+s+d", m68000up },
 {"cmpb",	one(0130000),	one(0170700), ";bDd", m68000up },
+{"cmpb",	one(0130000),	one(0170700), "*bDd", mcf5407 },
 {"cmpw",	one(0130300),	one(0170700), "*wAd", m68000up },
 {"cmpw",	one(0006100),	one(0177700), "#w@s", m68000up },
+{"cmpw",	one(0006100),	one(0177700), "#wDs", mcf5407 },
 {"cmpw",	one(0130510),	one(0170770), "+s+d", m68000up },
-{"cmpw",	one(0130100),	one(0170700), "*wDd", m68000up },
+{"cmpw",	one(0130100),	one(0170700), "*wDd", m68000up | mcf5407 },
 {"cmpl",	one(0130700),	one(0170700), "*lAd", m68000up | mcf },
 {"cmpl",	one(0006200),	one(0177700), "#l@s", m68000up },
 {"cmpl",	one(0006200),	one(0177700), "#lDs", mcf },
@@ -300,22 +305,20 @@ const struct m68k_opcode m68k_opcodes[] =
 {"dbvc",	one(0054310),	one(0177770), "DsBw", m68000up },
 {"dbvs",	one(0054710),	one(0177770), "DsBw", m68000up },
 
-{"divsw",	one(0100700),		one(0170700), ";wDd", m68000up },
-{"divsw",	one(0100700),   one(0170700), "vsDd", mcf5307 | mcf5206e },
+{"divsw",	one(0100700),	one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
 
 {"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
 {"divsl", two(0046100,0004000),two(0177700,0107770),";lDD",   m68020up|cpu32 },
-{"divsl", two(0046100,0004000),two(0177700,0107770),"vsDD",   mcf5307 | mcf5206e },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD",   mcf5307up | mcf5206e },
 
 {"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
 {"divsll", two(0046100,0004000),two(0177700,0107770),";lDD",  m68020up|cpu32 },
 
-{"divuw",	one(0100300),		one(0170700), ";wDd", m68000up },
-{"divuw",	one(0100300),		one(0170700), "vsDd", mcf5307 | mcf5206e },
+{"divuw",	one(0100300),		one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
 
 {"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
 {"divul", two(0046100,0000000),two(0177700,0107770),";lDD",   m68020up|cpu32 },
-{"divul", two(0046100,0000000),two(0177700,0107770),"vsDD",   mcf5307 | mcf5206e },
+{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD",   mcf5307up | mcf5206e },
 
 {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
 {"divull", two(0046100,0000000),two(0177700,0107770),";lDD",  m68020up|cpu32 },
@@ -1242,43 +1245,43 @@ const struct m68k_opcode m68k_opcodes[] =
 {"lsrl",	one(0160250),	one(0170770), "DdDs", m68000up | mcf },
 
   /* FIXME: add MAM mode (`&' after <ea> operand) / remove MACM */
-{"macw",  two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5307 | mcf5206e },
-{"macw",  two(0120000, 0001000), two(0170660, 0005400), "uMumMh", mcf5307 | mcf5206e },
-{"macw",  two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e },
-{"macw",  two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e },
-{"macw",  two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e },
-{"macw",  two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e },
-{"macw",  two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e },
-{"macw",  two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e },
-{"macw",  two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e },
-{"macw",  two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e },
-{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e },
-{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e },
-{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e },
-{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e },
-{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e },
-{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e },
-{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e },
-{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e },
-
-{"macl",  two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5307 | mcf5206e },
-{"macl",  two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5307 | mcf5206e },
-{"macl",  two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e },
-{"macl",  two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e },
-{"macl",  two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e },
-{"macl",  two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e },
-{"macl",  two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e },
-{"macl",  two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e },
-{"macl",  two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e },
-{"macl",  two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e },
-{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e },
-{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e },
-{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e },
-{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e },
-{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e },
-{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e },
-{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e },
-{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e },
+{"macw",  two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e },
+{"macw",  two(0120000, 0001000), two(0170660, 0005400), "uMumMh", mcf5307up | mcf5206e },
+{"macw",  two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
+{"macw",  two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
+{"macw",  two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
+{"macw",  two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
+{"macw",  two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
+{"macw",  two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
+{"macw",  two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
+{"macw",  two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
+{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
+{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
+{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
+{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
+{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
+{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
+{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
+{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
+
+{"macl",  two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e },
+{"macl",  two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e },
+{"macl",  two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
+{"macl",  two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
+{"macl",  two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
+{"macl",  two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
+{"macl",  two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
+{"macl",  two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
+{"macl",  two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
+{"macl",  two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
+{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
+{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
+{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
+{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
+{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
+{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
+{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
+{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
 
 /* NOTE: The mcf5200 family programmer's reference manual does not 
    indicate the byte form of the movea instruction is invalid (as it
@@ -1335,14 +1338,22 @@ const struct m68k_opcode m68k_opcodes[] =
 
 /* The move opcode can generate the movea and moveq instructions.  */
 {"moveb",	one(0010000),	one(0170000), ";b$d", m68000up },
-{"moveb",	one(0010000),	one(0170000), "ms%d", mcf },
-{"moveb",	one(0010000),	one(0170000), "nspd", mcf },
-{"moveb",	one(0010000),	one(0170000), "obmd", mcf },
+{"moveb",	one(0010000),	one(0170070), "Ds$d", mcf },
+{"moveb",	one(0010020),	one(0170070), "as$d", mcf },
+{"moveb",	one(0010030),	one(0170070), "+s$d", mcf },
+{"moveb",	one(0010040),	one(0170070), "-s$d", mcf },
+{"moveb",	one(0010000),	one(0170000), "nsqd", mcf },
+{"moveb",	one(0010000),	one(0170700), "obDd", mcf },
+{"moveb",	one(0010200),	one(0170700), "obad", mcf },
+{"moveb",	one(0010300),	one(0170700), "ob+d", mcf },
+{"moveb",	one(0010400),	one(0170700), "ob-d", mcf },
+{"moveb",	one(0010000),	one(0170000), "obnd", mcf5407 },
 
 {"movew",	one(0030000),	one(0170000), "*w%d", m68000up },
 {"movew",	one(0030000),	one(0170000), "ms%d", mcf },
 {"movew",	one(0030000),	one(0170000), "nspd", mcf },
 {"movew",	one(0030000),	one(0170000), "owmd", mcf },
+{"movew",	one(0030000),	one(0170000), "ownd", mcf5407 },
 {"movew",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"movew",	one(0040300),	one(0177770), "SsDs", mcf },
 {"movew",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1359,23 +1370,25 @@ const struct m68k_opcode m68k_opcodes[] =
 {"movel",	one(0020000),	one(0170000), "ms%d", mcf },
 {"movel",	one(0020000),	one(0170000), "nspd", mcf },
 {"movel",	one(0020000),	one(0170000), "olmd", mcf },
+{"movel",	one(0020000),	one(0170000), "olnd", mcf5407 },
 {"movel",	one(0047140),	one(0177770), "AsUd", m68000up },
 {"movel",	one(0047150),	one(0177770), "UdAs", m68000up },
-{"movel",	one(0120600),	one(0177760), "EsRs", mcf5307 | mcf5206e },
-{"movel",	one(0120400),	one(0177760), "RsEs", mcf5307 | mcf5206e },
-{"movel",	one(0120474),	one(0177777), "#lEs", mcf5307 | mcf5206e },
-{"movel",	one(0124600),	one(0177760), "GsRs", mcf5307 | mcf5206e },
-{"movel",	one(0124400),	one(0177760), "RsGs", mcf5307 | mcf5206e },
-{"movel",	one(0124474),	one(0177777), "#lGs", mcf5307 | mcf5206e },
-{"movel",	one(0126600),	one(0177760), "HsRs", mcf5307 | mcf5206e },
-{"movel",	one(0126400),	one(0177760), "RsHs", mcf5307 | mcf5206e },
-{"movel",	one(0126474),	one(0177777), "#lHs", mcf5307 | mcf5206e },
-{"movel",	one(0124700),	one(0177777), "GsCs", mcf5307 | mcf5206e },
+{"movel",	one(0120600),	one(0177760), "EsRs", mcf5307up | mcf5206e },
+{"movel",	one(0120400),	one(0177760), "RsEs", mcf5307up | mcf5206e },
+{"movel",	one(0120474),	one(0177777), "#lEs", mcf5307up | mcf5206e },
+{"movel",	one(0124600),	one(0177760), "GsRs", mcf5307up | mcf5206e },
+{"movel",	one(0124400),	one(0177760), "RsGs", mcf5307up | mcf5206e },
+{"movel",	one(0124474),	one(0177777), "#lGs", mcf5307up | mcf5206e },
+{"movel",	one(0126600),	one(0177760), "HsRs", mcf5307up | mcf5206e },
+{"movel",	one(0126400),	one(0177760), "RsHs", mcf5307up | mcf5206e },
+{"movel",	one(0126474),	one(0177777), "#lHs", mcf5307up | mcf5206e },
+{"movel",	one(0124700),	one(0177777), "GsCs", mcf5307up | mcf5206e },
 
 {"move",	one(0030000),	one(0170000), "*w%d", m68000up },
 {"move",	one(0030000),	one(0170000), "ms%d", mcf },
 {"move",	one(0030000),	one(0170000), "nspd", mcf },
 {"move",	one(0030000),	one(0170000), "owmd", mcf },
+{"move",	one(0030000),	one(0170000), "ownd", mcf5407 },
 {"move",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"move",	one(0040300),	one(0177770), "SsDs", mcf },
 {"move",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1390,6 +1403,12 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move",	one(0047140),	one(0177770), "AsUd", m68000up },
 {"move",	one(0047150),	one(0177770), "UdAs", m68000up },
 
+{"mov3ql",	one(0120500),	one(0170700), "Qd%s", mcf5407 },
+{"mvsb",	one(0070400),	one(0170700), "*bDd", mcf5407 },
+{"mvsw",	one(0070500),	one(0170700), "*wDd", mcf5407 },
+{"mvzb",	one(0070600),	one(0170700), "*bDd", mcf5407 },
+{"mvzw",	one(0070700),	one(0170700), "*wDd", mcf5407 },
+
 {"movesb",	two(0007000, 0),     two(0177700, 07777), "~sR1", m68010up },
 {"movesb",	two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up },
 {"movesw",	two(0007100, 0),     two(0177700, 07777), "~sR1", m68010up },
@@ -1404,43 +1423,43 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move16",	one(0xf618),		one(0xfff8), "_Las", m68040up },
 
   /* FIXME: add MAM mode (`&' after <ea> operand) / remove MSACM */
-{"msacw",  two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5307 | mcf5206e },
-{"msacw",  two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5307 | mcf5206e },
-{"msacw",  two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e },
-{"msacw",  two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5307 | mcf5206e },
-{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5307 | mcf5206e },
-
-{"msacl",  two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5307 | mcf5206e },
-{"msacl",  two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5307 | mcf5206e },
-{"msacl",  two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e },
-{"msacl",  two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e },
-{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5307 | mcf5206e },
-{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5307 | mcf5206e },
-{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5307 | mcf5206e },
-{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5307 | mcf5206e },
-{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5307 | mcf5206e },
-{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307 | mcf5206e },
-{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307 | mcf5206e },
-{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5307 | mcf5206e },
+{"msacw",  two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e },
+{"msacw",  two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5307up | mcf5206e },
+{"msacw",  two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
+{"msacw",  two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e },
+{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e },
+
+{"msacl",  two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e },
+{"msacl",  two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e },
+{"msacl",  two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
+{"msacl",  two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
+{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e },
+{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e },
+{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e },
+{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e },
+{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e },
+{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e },
+{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e },
+{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e },
 
 {"mulsw",	one(0140700),		one(0170700), ";wDd", m68000up|mcf },
 {"mulsl",	two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
@@ -1717,8 +1736,8 @@ const struct m68k_opcode m68k_opcodes[] =
 {"pvalid",	two(0xf000, 0x2c00),	two(0xffc0, 0xfff8), "A3&s", m68851 },
 
   /* FIXME: don't allow Dw==Dx. */
-{"remsl",       two(0x4c40, 0x0800),    two(0xffc0, 0x8ff8), "vsD3D1", mcf5307 | mcf5206e },
-{"remul",       two(0x4c40, 0x0000),    two(0xffc0, 0x8ff8), "vsD3D1", mcf5307 | mcf5206e },
+{"remsl",       two(0x4c40, 0x0800),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
+{"remul",       two(0x4c40, 0x0000),    two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
 
 {"reset",	one(0047160),		one(0177777), "", m68000up },
 
@@ -1756,18 +1775,19 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"rtd",		one(0047164),		one(0177777), "#w", m68010up },
 
-{"rte",		one(0047163),		one(0177777), "",   m68000up|mcf },
+{"rte",		one(0047163),		one(0177777), "",   m68000up | mcf },
 
 {"rtm",		one(0003300),		one(0177760), "Rs", m68020 },
 
 {"rtr",		one(0047167),		one(0177777), "",   m68000up },
 
-{"rts",		one(0047165),		one(0177777), "",   m68000up|mcf },
+{"rts",		one(0047165),		one(0177777), "",   m68000up | mcf },
+
+{"satsl",	one(0046200),		one(0177770), "Ds", mcf5407 },
 
 {"sbcd",	one(0100400),		one(0170770), "DsDd", m68000up },
 {"sbcd",	one(0100410),		one(0170770), "-s-d", m68000up },
 
-
 {"scc",		one(0052300),	one(0177700), "$s", m68000up },
 {"scc",		one(0052300),	one(0177700), "Ds", mcf },
 {"scs",		one(0052700),	one(0177700), "$s", m68000up },
@@ -1850,7 +1870,7 @@ const struct m68k_opcode m68k_opcodes[] =
 {"swbeg",	one(0045374),	one(0177777), "#w",   m68000up | mcf },
 {"swbegl",	one(0045375),	one(0177777), "#l",   m68000up | mcf },
 
-{"tas",		one(0045300),		one(0177700), "$s", m68000up },
+{"tas",		one(0045300),	one(0177700), "$s", m68000up | mcf5407 },
 
 #define TBL1(name,signed,round,size)					\
   {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400),	\
@@ -2089,6 +2109,7 @@ const struct m68k_opcode_alias m68k_opcode_aliases[] =
   { "ror",	"rorw", },
   { "roxl",	"roxlw", },
   { "roxr",	"roxrw", },
+  { "sats",	"satsl", },
   { "sbcdb",	"sbcd", },
   { "sccb",	"scc", },
   { "scsb",	"scs", },
@@ -2150,6 +2171,7 @@ const struct m68k_opcode_alias m68k_opcode_aliases[] =
   { "movsb",	"movesb", },
   { "movsl",	"movesl", },
   { "movsw",	"movesw", },
+  { "mov3q",	"mov3ql", },
 
   { "tdivul",	"divul", },	/* for m68k-svr4 */
   { "fmovb",	"fmoveb", },
diff --git a/gnu/usr.bin/binutils/opcodes/m88k-dis.c b/gnu/usr.bin/binutils/opcodes/m88k-dis.c
index ef3f32a284b..f0336c7bd5f 100644
--- a/gnu/usr.bin/binutils/opcodes/m88k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/m88k-dis.c
@@ -1,5 +1,5 @@
 /* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
-   Copyright (c) 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998
+   Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000
    Free Software Foundation, Inc.
    Contributed by Data General Corporation, November 1989.
    Partially derived from an earlier printcmd.c.
diff --git a/gnu/usr.bin/binutils/opcodes/mips-dis.c b/gnu/usr.bin/binutils/opcodes/mips-dis.c
index 9ab9f98690c..3d737f67c31 100644
--- a/gnu/usr.bin/binutils/opcodes/mips-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/mips-dis.c
@@ -1,5 +1,7 @@
 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
-   Copyright (c) 1989, 91-97, 1998 Free Software Foundation, Inc.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000, 2001
+   Free Software Foundation, Inc.
    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -34,44 +36,65 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include "elf/mips.h"
 #endif
 
-static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *));
+/* Mips instructions are at maximum this many bytes long.  */
+#define INSNLEN 4
+
+static int _print_insn_mips
+  PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
+static int print_insn_mips
+  PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
+static void print_insn_arg
+  PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
+static int print_insn_mips16
+  PARAMS ((bfd_vma, struct disassemble_info *));
 static void print_mips16_insn_arg
   PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma,
 	   struct disassemble_info *));
-
-/* Mips instructions are never longer than this many bytes.  */
-#define MAXLEN 4
-
-static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma,
-				    struct disassemble_info *));
-static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int,
-				     struct disassemble_info *));
-
 
-/* FIXME: This should be shared with gdb somehow.  */
-#define REGISTER_NAMES 	\
-    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
-	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
-	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
-	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
-	"sr",	"lo",	"hi",	"bad",	"cause","pc",    \
-	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
-	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
-	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
-	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
-	"fsr",  "fir",  "fp",   "inx",  "rand", "tlblo","ctxt", "tlbhi",\
-	"epc",  "prid"\
-    }
-
-static CONST char * CONST reg_names[] = REGISTER_NAMES;
+/* FIXME: These should be shared with gdb somehow.  */
 
 /* The mips16 register names.  */
 static const char * const mips16_reg_names[] =
 {
   "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
 };
+
+static const char * const mips32_reg_names[] =
+{
+  "zero", "at",	  "v0",	 "v1",	 "a0",	  "a1",	   "a2",   "a3",
+  "t0",	  "t1",	  "t2",	 "t3",	 "t4",	  "t5",	   "t6",   "t7",
+  "s0",	  "s1",	  "s2",	 "s3",	 "s4",	  "s5",	   "s6",   "s7",
+  "t8",	  "t9",	  "k0",	 "k1",	 "gp",	  "sp",	   "s8",   "ra",
+  "sr",	  "lo",	  "hi",	 "bad",	 "cause", "pc",
+  "fv0",  "$f1",  "fv1", "$f3",  "ft0",   "$f5",   "ft1",  "$f7",
+  "ft2",  "$f9",  "ft3", "$f11", "fa0",   "$f13",  "fa1",  "$f15",
+  "ft4",  "f17",  "ft5", "f19",  "fs0",   "f21",   "fs1",  "f23",
+  "fs2",  "$f25", "fs3", "$f27", "fs4",   "$f29",  "fs5",  "$f31",
+  "fsr",  "fir",  "fp",  "inx",  "rand",  "tlblo", "ctxt", "tlbhi",
+  "epc",  "prid"
+};
+
+static const char * const mips64_reg_names[] =
+{
+  "zero", "at",	  "v0",	  "v1",	  "a0",	   "a1",    "a2",   "a3",
+  "a4",	  "a5",	  "a6",   "a7",	  "t0",	   "t1",    "t2",   "t3",
+  "s0",	  "s1",	  "s2",	  "s3",	  "s4",	   "s5",    "s6",   "s7",
+  "t8",	  "t9",	  "k0",	  "k1",	  "gp",	   "sp",    "s8",   "ra",
+  "sr",	  "lo",	  "hi",	  "bad",  "cause", "pc",
+  "fv0",  "$f1",  "fv1",  "$f3",  "ft0",   "ft1",   "ft2",  "ft3",
+  "ft4",  "ft5",  "ft6",  "ft7",  "fa0",   "fa1",   "fa2",  "fa3",
+  "fa4",  "fa5",  "fa6",  "fa7",  "ft8",   "ft9",   "ft10", "ft11",
+  "fs0",  "fs1",  "fs2",  "fs3",  "fs4",   "fs5",   "fs6",  "fs7",
+  "fsr",  "fir",  "fp",   "inx",  "rand",  "tlblo", "ctxt", "tlbhi",
+  "epc",  "prid"
+};
+
+/* Scalar register names. _print_insn_mips() decides which register name
+   table to use.  */
+static const char * const *reg_names = NULL;
 
-/* subroutine */
+/* Print insn arguments for 32/64-bit code */
+
 static void
 print_insn_arg (d, l, pc, info)
      const char *d;
@@ -93,13 +116,13 @@ print_insn_arg (d, l, pc, info)
     case 'b':
     case 'r':
     case 'v':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     reg_names[(l >> OP_SH_RS) & OP_MASK_RS]);
       break;
 
     case 't':
     case 'w':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
       break;
 
@@ -132,7 +155,8 @@ print_insn_arg (d, l, pc, info)
 
     case 'a':
       (*info->print_address_func)
-	(((pc & 0xF0000000) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)),
+	((((pc + 4) & ~ (bfd_vma) 0x0fffffff)
+	  | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)),
 	 info);
       break;
 
@@ -142,17 +166,41 @@ print_insn_arg (d, l, pc, info)
       if (delta & 0x8000)
 	delta |= ~0xffff;
       (*info->print_address_func)
-	((delta << 2) + pc + 4,
+	((delta << 2) + pc + INSNLEN,
 	 info);
       break;
 
     case 'd':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
       break;
 
+    case 'U':
+      {
+      /* First check for both rd and rt being equal. */
+      unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
+      if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
+        (*info->fprintf_func) (info->stream, "%s",
+                               reg_names[reg]);
+      else
+        {
+          /* If one is zero use the other. */
+          if (reg == 0)
+            (*info->fprintf_func) (info->stream, "%s",
+                                   reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+          else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
+            (*info->fprintf_func) (info->stream, "%s",
+                                   reg_names[reg]);
+          else /* Bogus, result depends on processor. */
+            (*info->fprintf_func) (info->stream, "%s or %s",
+                                   reg_names[reg],
+                                   reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+          }
+      }
+      break;
+
     case 'z':
-      (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
+      (*info->fprintf_func) (info->stream, "%s", reg_names[0]);
       break;
 
     case '<':
@@ -165,7 +213,6 @@ print_insn_arg (d, l, pc, info)
 			     (l >> OP_SH_CODE) & OP_MASK_CODE);
       break;
 
-
     case 'q':
       (*info->fprintf_func) (info->stream, "0x%x",
 			     (l >> OP_SH_CODE2) & OP_MASK_CODE2);
@@ -178,7 +225,12 @@ print_insn_arg (d, l, pc, info)
 
     case 'B':
       (*info->fprintf_func) (info->stream, "0x%x",
-			     (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
+			     (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+      break;
+
+    case 'J':
+      (*info->fprintf_func) (info->stream, "0x%x",
+			     (l >> OP_SH_CODE19) & OP_MASK_CODE19);
       break;
 
     case 'S':
@@ -187,7 +239,6 @@ print_insn_arg (d, l, pc, info)
 			     (l >> OP_SH_FS) & OP_MASK_FS);
       break;
 
-
     case 'T':
     case 'W':
       (*info->fprintf_func) (info->stream, "$f%d",
@@ -205,13 +256,13 @@ print_insn_arg (d, l, pc, info)
       break;
 
     case 'E':
-      (*info->fprintf_func) (info->stream, "$%d",
-			     (l >> OP_SH_RT) & OP_MASK_RT);
+      (*info->fprintf_func) (info->stream, "%s",
+			     reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
       break;
 
     case 'G':
-      (*info->fprintf_func) (info->stream, "$%d",
-			     (l >> OP_SH_RD) & OP_MASK_RD);
+      (*info->fprintf_func) (info->stream, "%s",
+			     reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
       break;
 
     case 'N':
@@ -229,6 +280,10 @@ print_insn_arg (d, l, pc, info)
 			     (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
       break;
 
+    case 'H':
+      (*info->fprintf_func) (info->stream, "%d",
+			     (l >> OP_SH_SEL) & OP_MASK_SEL);
+      break;
 
     default:
       /* xgettext:c-format */
@@ -239,102 +294,127 @@ print_insn_arg (d, l, pc, info)
     }
 }
 
-#if SYMTAB_AVAILABLE
-
-/* Figure out the MIPS ISA and CPU based on the machine number.
-   FIXME: What does this have to do with SYMTAB_AVAILABLE?  */
+/* Figure out the MIPS ISA and CPU based on the machine number. */
 
 static void
-set_mips_isa_type (mach, isa, cputype)
+mips_isa_type (mach, isa, cputype)
      int mach;
      int *isa;
      int *cputype;
 {
-  int target_processor = 0;
-  int mips_isa = 0;
-
   switch (mach)
     {
-      case bfd_mach_mips3000:
-	target_processor = 3000;
-	mips_isa = 1;
-	break;
-      case bfd_mach_mips3900:
-	target_processor = 3900;
-	mips_isa = 1;
-	break;
-      case bfd_mach_mips4000:
-	target_processor = 4000;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4010:
-	target_processor = 4010;
-	mips_isa = 2;
-	break;
-      case bfd_mach_mips4100:
-	target_processor = 4100;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4111:
-	target_processor = 4100;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4300:
-	target_processor = 4300;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4400:
-	target_processor = 4400;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4600:
-	target_processor = 4600;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips4650:
-	target_processor = 4650;
-	mips_isa = 3;
-	break;
-      case bfd_mach_mips5000:
-	target_processor = 5000;
-	mips_isa = 4;
-	break;
-      case bfd_mach_mips6000:
-	target_processor = 6000;
-	mips_isa = 2;
-	break;
-      case bfd_mach_mips8000:
-	target_processor = 8000;
-	mips_isa = 4;
-	break;
-      case bfd_mach_mips10000:
-	target_processor = 10000;
-	mips_isa = 4;
-	break;
-      case bfd_mach_mips16:
-	target_processor = 16;
-	mips_isa = 3;
-	break;
-      default:
-	target_processor = 3000;
-	mips_isa = 3;
-	break;
-
+    case bfd_mach_mips3000:
+      *cputype = CPU_R3000;
+      *isa = ISA_MIPS1;
+      break;
+    case bfd_mach_mips3900:
+      *cputype = CPU_R3900;
+      *isa = ISA_MIPS1;
+      break;
+    case bfd_mach_mips4000:
+      *cputype = CPU_R4000;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4010:
+      *cputype = CPU_R4010;
+      *isa = ISA_MIPS2;
+      break;
+    case bfd_mach_mips4100:
+      *cputype = CPU_VR4100;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4111:
+      *cputype = CPU_R4111;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4300:
+      *cputype = CPU_R4300;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4400:
+      *cputype = CPU_R4400;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4600:
+      *cputype = CPU_R4600;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips4650:
+      *cputype = CPU_R4650;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips5000:
+      *cputype = CPU_R5000;
+      *isa = ISA_MIPS4;
+      break;
+    case bfd_mach_mips6000:
+      *cputype = CPU_R6000;
+      *isa = ISA_MIPS2;
+      break;
+    case bfd_mach_mips8000:
+      *cputype = CPU_R8000;
+      *isa = ISA_MIPS4;
+      break;
+    case bfd_mach_mips10000:
+      *cputype = CPU_R10000;
+      *isa = ISA_MIPS4;
+      break;
+    case bfd_mach_mips12000:
+      *cputype = CPU_R12000;
+      *isa = ISA_MIPS4;
+      break;
+    case bfd_mach_mips16:
+      *cputype = CPU_MIPS16;
+      *isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips32:
+      *cputype = CPU_MIPS32;
+      *isa = ISA_MIPS32;
+      break;
+    case bfd_mach_mips32_4k:
+      *cputype = CPU_MIPS32_4K;
+      *isa = ISA_MIPS32;
+      break;
+    case bfd_mach_mips5:
+      *cputype = CPU_MIPS5;
+      *isa = ISA_MIPS5;
+      break;
+    case bfd_mach_mips64:
+      *cputype = CPU_MIPS64;
+      *isa = ISA_MIPS64;
+      break;
+    case bfd_mach_mips_sb1:
+      *cputype = CPU_SB1;
+      *isa = ISA_MIPS64;
+      break;
+    default:
+      *cputype = CPU_R3000;
+      *isa = ISA_MIPS3;
+      break;
     }
-
-  *isa = mips_isa;
-  *cputype = target_processor;
 }
 
-#endif /* SYMTAB_AVAILABLE */
+/* Figure out ISA from disassemble_info data */
 
+static int
+get_mips_isa (info)
+     struct disassemble_info *info;
+{
+  int isa;
+  int cpu;
+
+  mips_isa_type (info->mach, &isa, &cpu);
+  return isa;
+}
+
 /* Print the mips instruction at address MEMADDR in debugged memory,
    on using INFO.  Returns length of the instruction, in bytes, which is
-   always 4.  BIGENDIAN must be 1 if this is big-endian code, 0 if
+   always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
    this is little-endian code.  */
 
 static int
-_print_insn_mips (memaddr, word, info)
+print_insn_mips (memaddr, word, info)
      bfd_vma memaddr;
      unsigned long int word;
      struct disassemble_info *info;
@@ -371,11 +451,11 @@ _print_insn_mips (memaddr, word, info)
      FIXME: Where does mips_target_info come from?  */
   target_processor = mips_target_info.processor;
   mips_isa = mips_target_info.isa;
-#else  
-  set_mips_isa_type (info->mach, &mips_isa, &target_processor);
-#endif  
+#else
+  mips_isa_type (info->mach, &mips_isa, &target_processor);
+#endif
 
-  info->bytes_per_chunk = 4;
+  info->bytes_per_chunk = INSNLEN;
   info->display_endian = info->endian;
 
   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
@@ -400,29 +480,29 @@ _print_insn_mips (memaddr, word, info)
 		      print_insn_arg (d, word, memaddr, info);
 		}
 
-	      return 4;
+	      return INSNLEN;
 	    }
 	}
     }
 
   /* Handle undefined instructions.  */
   (*info->fprintf_func) (info->stream, "0x%x", word);
-  return 4;
+  return INSNLEN;
 }
-
-
+
 /* In an environment where we do not know the symbol type of the
    instruction we are forced to assume that the low order bit of the
    instructions' address may mark it as a mips16 instruction.  If we
    are single stepping, or the pc is within the disassembled function,
    this works.  Otherwise, we need a clue.  Sometimes.  */
 
-int
-print_insn_big_mips (memaddr, info)
+static int
+_print_insn_mips (memaddr, info, endianness)
      bfd_vma memaddr;
      struct disassemble_info *info;
+     enum bfd_endian endianness;
 {
-  bfd_byte buffer[4];
+  bfd_byte buffer[INSNLEN];
   int status;
 
 #if 1
@@ -430,7 +510,7 @@ print_insn_big_mips (memaddr, info)
   /* Only a few tools will work this way.  */
   if (memaddr & 0x01)
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
 #if SYMTAB_AVAILABLE
   if (info->mach == 16
@@ -439,12 +519,30 @@ print_insn_big_mips (memaddr, info)
 	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
 	      == STO_MIPS16)))
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
-  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+  /* Use mips64_reg_names for new ABI.  */
+  if (info->flavour == bfd_target_elf_flavour
+      && info->symbols != NULL
+      && (((get_mips_isa(info) | INSN_ISA_MASK) & ISA_MIPS2) != 0)
+      && ((elf_elfheader (bfd_asymbol_bfd(*(info->symbols)))->e_flags
+	   & EF_MIPS_ABI2) != 0))
+    reg_names = mips64_reg_names;
+  else
+    reg_names = mips32_reg_names;
+
+  status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
   if (status == 0)
-    return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer),
-			     info);
+    {
+      unsigned long insn;
+
+      if (endianness == BFD_ENDIAN_BIG)
+        insn = (unsigned long) bfd_getb32 (buffer);
+      else
+	insn = (unsigned long) bfd_getl32 (buffer);
+
+      return print_insn_mips (memaddr, insn, info);
+    }
   else
     {
       (*info->memory_error_func) (status, memaddr, info);
@@ -453,37 +551,19 @@ print_insn_big_mips (memaddr, info)
 }
 
 int
-print_insn_little_mips (memaddr, info)
+print_insn_big_mips (memaddr, info)
      bfd_vma memaddr;
      struct disassemble_info *info;
 {
-  bfd_byte buffer[4];
-  int status;
-
-
-#if 1
-  if (memaddr & 0x01)
-    return print_insn_mips16 (memaddr, info);
-#endif  
-
-#if SYMTAB_AVAILABLE
-  if (info->mach == 16
-      || (info->flavour == bfd_target_elf_flavour
-	  && info->symbols != NULL
-	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
-	      == STO_MIPS16)))
-    return print_insn_mips16 (memaddr, info);
-#endif  
+  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
+}
 
-  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
-  if (status == 0)
-    return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer),
-			     info);
-  else
-    {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
-    }
+int
+print_insn_little_mips (memaddr, info)
+     bfd_vma memaddr;
+     struct disassemble_info *info;
+{
+  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
 }
 
 /* Disassemble mips16 instructions.  */
@@ -503,7 +583,6 @@ print_insn_mips16 (memaddr, info)
 
   info->bytes_per_chunk = 2;
   info->display_endian = info->endian;
-
   info->insn_info_valid = 1;
   info->branch_delay_insns = 0;
   info->data_size = 0;
@@ -647,7 +726,7 @@ print_insn_mips16 (memaddr, info)
 
 static void
 print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
-     int type;
+     char type;
      const struct mips_opcode *op;
      int l;
      boolean use_extend;
@@ -665,36 +744,36 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
 
     case 'y':
     case 'w':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     mips16_reg_names[((l >> MIPS16OP_SH_RY)
 					       & MIPS16OP_MASK_RY)]);
       break;
 
     case 'x':
     case 'v':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     mips16_reg_names[((l >> MIPS16OP_SH_RX)
 					       & MIPS16OP_MASK_RX)]);
       break;
 
     case 'z':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     mips16_reg_names[((l >> MIPS16OP_SH_RZ)
 					       & MIPS16OP_MASK_RZ)]);
       break;
 
     case 'Z':
-      (*info->fprintf_func) (info->stream, "$%s",
+      (*info->fprintf_func) (info->stream, "%s",
 			     mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
 					       & MIPS16OP_MASK_MOVE32Z)]);
       break;
 
     case '0':
-      (*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
+      (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[0]);
       break;
 
     case 'S':
-      (*info->fprintf_func) (info->stream, "$%s", reg_names[29]);
+      (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[29]);
       break;
 
     case 'P':
@@ -702,18 +781,18 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
       break;
 
     case 'R':
-      (*info->fprintf_func) (info->stream, "$%s", reg_names[31]);
+      (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[31]);
       break;
 
     case 'X':
-      (*info->fprintf_func) (info->stream, "$%s",
-			     reg_names[((l >> MIPS16OP_SH_REGR32)
+      (*info->fprintf_func) (info->stream, "%s",
+			     mips32_reg_names[((l >> MIPS16OP_SH_REGR32)
 					& MIPS16OP_MASK_REGR32)]);
       break;
 
     case 'Y':
-      (*info->fprintf_func) (info->stream, "$%s",
-			     reg_names[MIPS16OP_EXTRACT_REG32R (l)]);
+      (*info->fprintf_func) (info->stream, "%s",
+			     mips32_reg_names[MIPS16OP_EXTRACT_REG32R (l)]);
       break;
 
     case '<':
@@ -979,9 +1058,9 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
       if (! use_extend)
 	extend = 0;
       l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
-      (*info->print_address_func) ((memaddr & 0xf0000000) | l, info);
+      (*info->print_address_func) (((memaddr + 4) & 0xf0000000) | l, info);
       info->insn_type = dis_jsr;
-      info->target = (memaddr & 0xf0000000) | l;
+      info->target = ((memaddr + 4) & 0xf0000000) | l;
       info->branch_delay_insns = 1;
       break;
 
@@ -998,10 +1077,10 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
 
 	if (amask > 0 && amask < 5)
 	  {
-	    (*info->fprintf_func) (info->stream, "$%s", reg_names[4]);
+	    (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[4]);
 	    if (amask > 1)
-	      (*info->fprintf_func) (info->stream, "-$%s",
-				     reg_names[amask + 3]);
+	      (*info->fprintf_func) (info->stream, "-%s",
+				     mips32_reg_names[amask + 3]);
 	    need_comma = 1;
 	  }
 
@@ -1014,20 +1093,20 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
 	  }
 	else if (smask > 0)
 	  {
-	    (*info->fprintf_func) (info->stream, "%s$%s",
+	    (*info->fprintf_func) (info->stream, "%s%s",
 				   need_comma ? "," : "",
-				   reg_names[16]);
+				   mips32_reg_names[16]);
 	    if (smask > 1)
-	      (*info->fprintf_func) (info->stream, "-$%s",
-				     reg_names[smask + 15]);
+	      (*info->fprintf_func) (info->stream, "-%s",
+				     mips32_reg_names[smask + 15]);
 	    need_comma = 1;
 	  }
 
 	if (l & 1)
 	  {
-	    (*info->fprintf_func) (info->stream, "%s$%s",
+	    (*info->fprintf_func) (info->stream, "%s%s",
 				   need_comma ? "," : "",
-				   reg_names[31]);
+				   mips32_reg_names[31]);
 	    need_comma = 1;
 	  }
 
@@ -1042,6 +1121,11 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
       break;
 
     default:
+      /* xgettext:c-format */
+      (*info->fprintf_func)
+	(info->stream,
+	 _("# internal disassembler error, unrecognised modifier (%c)"),
+	 type);
       abort ();
     }
 }
diff --git a/gnu/usr.bin/binutils/opcodes/mips-opc.c b/gnu/usr.bin/binutils/opcodes/mips-opc.c
index b1000db069c..5fc17ba5652 100644
--- a/gnu/usr.bin/binutils/opcodes/mips-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/mips-opc.c
@@ -1,7 +1,9 @@
-/* mips.h.  Mips opcode list for GDB, the GNU debugger.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
+/* mips-opc.c -- MIPS opcode list.
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
+   Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -37,15 +39,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 #define WR_d    INSN_WRITE_GPR_D
 #define WR_t    INSN_WRITE_GPR_T
-#define WR_31   INSN_WRITE_GPR_31       
-#define WR_D    INSN_WRITE_FPR_D        
+#define WR_31   INSN_WRITE_GPR_31
+#define WR_D    INSN_WRITE_FPR_D
 #define WR_T	INSN_WRITE_FPR_T
 #define WR_S	INSN_WRITE_FPR_S
-#define RD_s    INSN_READ_GPR_S         
-#define RD_b    INSN_READ_GPR_S         
-#define RD_t    INSN_READ_GPR_T         
-#define RD_S    INSN_READ_FPR_S         
-#define RD_T    INSN_READ_FPR_T         
+#define RD_s    INSN_READ_GPR_S
+#define RD_b    INSN_READ_GPR_S
+#define RD_t    INSN_READ_GPR_T
+#define RD_S    INSN_READ_FPR_S
+#define RD_T    INSN_READ_FPR_T
 #define RD_R	INSN_READ_FPR_R
 #define WR_CC	INSN_WRITE_COND_CODE
 #define RD_CC	INSN_READ_COND_CODE
@@ -77,12 +79,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I3	INSN_ISA3
 #define I4	INSN_ISA4
 #define I5	INSN_ISA5
+#define I32	INSN_ISA32
+#define I64     INSN_ISA64
+
 #define P3	INSN_4650
 #define L1	INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
 
-#define G1      (T3                   \
+#define G1      (T3             \
                  )
 
 #define G2      (T3                   \
@@ -93,9 +98,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 #define G6      INSN_GP32
 
-#define M1      0
-#define M2      0
-
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -106,721 +108,750 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
    Many instructions are short hand for other instructions (i.e., The
    jal <register> instruction is short for jalr <register>).  */
 
-const struct mips_opcode mips_builtin_opcodes[] = {
+const struct mips_opcode mips_builtin_opcodes[] =
+{
 /* These instructions appear first so that the disassembler will find
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
-/* name,	args,	mask,		match,	pinfo */
-{"nop",     "",		0x00000000, 0xffffffff,	0,		I1	},
-{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,		I1	}, /* addiu */
-{"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,		I1	}, /* ori */
-{"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,	I1	},
-{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,	I1|G6	},/* or */
-{"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,	I3	},/* daddu */
-{"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,	I1	},/* addu */
-{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,	I1	},/* or */
-{"b",       "p",	0x10000000, 0xffff0000,	UBD,		I1	},/* beq 0,0 */
-{"b",       "p",	0x04010000, 0xffff0000,	UBD,		I1	},/* bgez 0 */
-{"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,	I1	},/* bgezal 0*/
-
-{"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,	I1	},
-{"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,	I1	},
-{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
-{"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,	I5	},
-{"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,	I1	},
-{"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1},
-{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1},
-{"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-{"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,	I1	},
-{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-{"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,	I1	},
-{"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,	I1	},
+/* name,    args,	match,	    mask,	pinfo,          	membership */
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	I32|G3	},
+{"nop",     "",         0x00000000, 0xffffffff, 0,              	I1      },
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,              	I32	},
+{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			I1	}, /* addiu */
+{"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			I1	}, /* ori */
+{"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		I1	},
+{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1|G6	},/* or */
+{"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,		I3	},/* daddu */
+{"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,		I1	},/* addu */
+{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1	},/* or */
+{"b",       "p",	0x10000000, 0xffff0000,	UBD,			I1	},/* beq 0,0 */
+{"b",       "p",	0x04010000, 0xffff0000,	UBD,			I1	},/* bgez 0 */
+{"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,		I1	},/* bgezal 0*/
+
+{"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		I1	},
+{"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
+{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
+{"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		I5	},
+{"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		I1	},
+{"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
+{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
+{"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		I1	},
+{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		I1	},
+{"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		I1	},
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
-{"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,	I1|M1	},
-{"bc1f",    "N,p",	0x45000000, 0xffe30000,	CBD|RD_CC|FP_S,	I4|M1	},
-{"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,	I2|T3|M1},
-{"bc1fl",   "N,p",	0x45020000, 0xffe30000,	CBL|RD_CC|FP_S,	I4|M1	},
-{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,	I1	},
-{"bc1t",    "N,p",	0x45010000, 0xffe30000,	CBD|RD_CC|FP_S,	I4	},
-{"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,	I2|T3	},
-{"bc1tl",   "N,p",	0x45030000, 0xffe30000,	CBL|RD_CC|FP_S,	I4	},
-{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,	I1	},
-{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,	I2|T3	},
-{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t,	I1	},
-{"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,	I1	},
-{"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t,	I2|T3	},
-{"beql",    "s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,	I2	},
-{"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO,	I1	},
-{"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,	I1	},
-{"bgel",    "s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,	I2	},
-{"bgel",    "s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,	I2	},
-{"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,	I1	},
-{"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,	I1	},
-{"bgeul",   "s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,	I2	},
-{"bgeul",   "s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,	I2	},
-{"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,	I1	},
-{"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO,	I1	},
-{"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,	I1	},
-{"bgtl",    "s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,	I2	},
-{"bgtl",    "s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,	I2	},
-{"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,	I1	},
-{"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,	I1	},
-{"bgtul",   "s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,	I2	},
-{"bgtul",   "s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,	I2	},
-{"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO,	I1	},
-{"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,	I1	},
-{"blel",    "s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,	I2	},
-{"blel",    "s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,	I2	},
-{"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,	I1	},
-{"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,	I1	},
-{"bleul",   "s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,	I2	},
-{"bleul",   "s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,	I2	},
-{"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO,	I1	},
-{"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,	I1	},
-{"bltl",    "s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,	I2	},
-{"bltl",    "s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,	I2	},
-{"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,	I1	},
-{"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,	I1	},
-{"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,	I2	},
-{"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,	I2	},
-{"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s|WR_31,	I1	},
-{"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s,	I1	},
-{"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBL|RD_s,	I2|T3	},
-{"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t,	I1	},
-{"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,	I1	},
-{"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 	I2|T3	},
-{"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,	I2	},
-{"break",   "",		0x0000000d, 0xffffffff,	TRAP,		I1	},
-{"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,		I1	},
-{"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,		I1	},
+{"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},
+{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},
+{"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},
+{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},
+{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},
+{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},
+{"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},
+{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},
+{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		I1	},
+{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},
+{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t,		I1	},
+{"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		I1	},
+{"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t,		I2|T3	},
+{"beql",    "s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		I2	},
+{"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		I1	},
+{"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,		I1	},
+{"bgel",    "s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		I2	},
+{"bgel",    "s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		I2	},
+{"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,		I1	},
+{"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,		I1	},
+{"bgeul",   "s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		I2	},
+{"bgeul",   "s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		I2	},
+{"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,		I1	},
+{"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO,		I1	},
+{"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,		I1	},
+{"bgtl",    "s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		I2	},
+{"bgtl",    "s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		I2	},
+{"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,		I1	},
+{"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,		I1	},
+{"bgtul",   "s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		I2	},
+{"bgtul",   "s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		I2	},
+{"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO,		I1	},
+{"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,		I1	},
+{"blel",    "s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		I2	},
+{"blel",    "s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		I2	},
+{"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,		I1	},
+{"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,		I1	},
+{"bleul",   "s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		I2	},
+{"bleul",   "s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		I2	},
+{"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO,		I1	},
+{"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,		I1	},
+{"bltl",    "s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		I2	},
+{"bltl",    "s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		I2	},
+{"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,		I1	},
+{"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,		I1	},
+{"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		I2	},
+{"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		I2	},
+{"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s|WR_31,		I1	},
+{"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s,		I1	},
+{"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},
+{"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t,		I1	},
+{"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		I1	},
+{"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		I2|T3	},
+{"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		I2	},
+{"break",   "",		0x0000000d, 0xffffffff,	TRAP,			I1	},
+{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           	I32     },
+{"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			I1	},
+{"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			I1	},
 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.f.d",   "M,S,T",	0x46200030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.f.s",   "S,T",	0x46000030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.f.s",   "M,S,T",	0x46000030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.f.ps",  "S,T",	0x46c00030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.un.d",  "S,T",	0x46200031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.un.d",  "M,S,T",	0x46200031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.un.s",  "S,T",	0x46000031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.un.s",  "M,S,T",	0x46000031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.un.ps", "S,T",	0x46c00031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.un.ps", "M,S,T",	0x46c00031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.eq.d",  "S,T",	0x46200032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.eq.d",  "M,S,T",	0x46200032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.eq.s",  "S,T",	0x46000032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.eq.s",  "M,S,T",	0x46000032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.eq.ps", "S,T",	0x46c00032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.eq.ps", "M,S,T",	0x46c00032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ueq.d", "S,T",	0x46200033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ueq.d", "M,S,T",	0x46200033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ueq.s", "S,T",	0x46000033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ueq.s", "M,S,T",	0x46000033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ueq.ps","S,T",	0x46c00033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ueq.ps","M,S,T",	0x46c00033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.lt.s",  "S,T",	0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.lt.s",  "M,S,T",	0x4600003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
-{"c.olt.d", "S,T",	0x46200034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.olt.d", "M,S,T",	0x46200034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
+{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
+{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
+{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
 {"c.olt.s", "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.olt.s", "M,S,T",	0x46000034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.olt.ps","S,T",	0x46c00034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.olt.ps","M,S,T",	0x46c00034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ult.d", "S,T",	0x46200035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ult.d", "M,S,T",	0x46200035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ult.s", "S,T",	0x46000035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ult.s", "M,S,T",	0x46000035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ult.ps","S,T",	0x46c00035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ult.ps","M,S,T",	0x46c00035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.le.s",  "M,S,T",	0x4600003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
-{"c.ole.d", "S,T",	0x46200036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ole.d", "M,S,T",	0x46200036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ole.s", "S,T",	0x46000036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ole.s", "M,S,T",	0x46000036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
+{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
+{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ole.ps","S,T",	0x46c00036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ole.ps","M,S,T",	0x46c00036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ule.d", "S,T",	0x46200037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ule.d", "M,S,T",	0x46200037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ule.s", "S,T",	0x46000037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ule.s", "M,S,T",	0x46000037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ule.ps","S,T",	0x46c00037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ule.ps","M,S,T",	0x46c00037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.sf.d",  "S,T",	0x46200038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.sf.d",  "M,S,T",	0x46200038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.sf.s",  "S,T",	0x46000038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.sf.s",  "M,S,T",	0x46000038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.sf.ps", "S,T",	0x46c00038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.sf.ps", "M,S,T",	0x46c00038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngle.d","S,T",	0x46200039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ngle.d","M,S,T",	0x46200039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ngle.s","S,T",	0x46000039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ngle.s","M,S,T",	0x46000039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ngle.ps","S,T",	0x46c00039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngle.ps","M,S,T",	0x46c00039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.seq.d", "S,T",	0x4620003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.seq.d", "M,S,T",	0x4620003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.seq.s", "S,T",	0x4600003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.seq.s", "M,S,T",	0x4600003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.seq.ps","S,T",	0x46c0003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.seq.ps","M,S,T",	0x46c0003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngl.d", "S,T",	0x4620003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ngl.d", "M,S,T",	0x4620003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ngl.s", "S,T",	0x4600003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ngl.s", "M,S,T",	0x4600003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ngl.ps","S,T",	0x46c0003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngl.ps","M,S,T",	0x46c0003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.lt.d",  "S,T",	0x4620003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.lt.d",  "M,S,T",	0x4620003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
+{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
 {"c.lt.ps", "S,T",	0x46c0003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.lt.ps", "M,S,T",	0x46c0003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.nge.d", "S,T",	0x4620003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.nge.d", "M,S,T",	0x4620003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.nge.s", "S,T",	0x4600003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.nge.s", "M,S,T",	0x4600003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.nge.ps","S,T",	0x46c0003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.nge.ps","M,S,T",	0x46c0003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.le.d",  "S,T",	0x4620003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.le.d",  "M,S,T",	0x4620003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
+{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
 {"c.le.ps", "S,T",	0x46c0003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.le.ps", "M,S,T",	0x46c0003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
-{"c.ngt.d", "M,S,T",	0x4620003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I4	},
-{"c.ngt.s", "S,T",	0x4600003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	I1	},
-{"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4	},
+{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32	},
+{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32	},
 {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
-{"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1	},
-{"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
-{"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
-{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,	I2	},
-{"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	I3|I32|T3},
+{"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
+{"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
+{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,		I2	},
+{"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0,		I1	},
 {"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
 {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
-{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
-{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
-{"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
+{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,		I1	},
+{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,		I1	},
+{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 	I32     },
+{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 	I32     },
+{"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,		I1	},
 {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
 {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
-{"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
-{"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
-{"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|FP_D,	I3	},
+{"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC,		I1	},
+{"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC,		I1	},
+{"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|FP_D,		I3	},
 {"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S|FP_D|FP_S,	I1	},
-{"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
-{"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|FP_D,	I3	},
-{"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|FP_S,	I3	},
-{"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|FP_S,	I3	},
+{"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
+{"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|FP_D,		I3	},
+{"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|FP_S,		I3	},
+{"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|FP_S,		I3	},
 {"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	I1	},
-{"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S|FP_S,	I1	},
+{"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
 {"cvt.s.pl","D,S",	0x46c00028, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	I5	},
 {"cvt.s.pu","D,S",	0x46c00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	I5	},
-{"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
-{"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,	I1	},
-{"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-{"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,	I3	},
-{"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,	I3	},
-{"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,	I3	},
-{"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,	I3	},
-{"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,	I3	},
-{"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,	I3	},
-{"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,	I3	},
+{"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
+{"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
+{"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		I3	},
+{"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		I3	},
+{"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		I3	},
+{"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		I3	},
+{"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		I3	},
+{"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		I3	},
+{"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		I3	},
+{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	I64     },
+{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	I64     },
 /* dctr and dctw are used on the r5000.  */
-{"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
-{"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
-{"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1	},
+{"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,			I3	},
+{"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,			I3	},
+{"deret",   "",         0x4200001f, 0xffffffff, 0, 			I32|G2	},
 /* For ddiv, see the comments about div.  */
-{"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
-{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
-{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,	I3	},
+{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
+{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		I3	},
+{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		I3	},
 /* For ddivu, see the comments about div.  */
-{"ddivu",   "z,s,t",	0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
-{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,	I3	},
-{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,	I3	},
+{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
+{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		I3	},
+{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		I3	},
 /* The MIPS assembler treats the div opcode with two operands as
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
-{"div",     "z,s,t",	0x0000001a, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1	},
-{"div",     "z,t",	0x0000001a, 0xffe0ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1	},
-{"div",     "d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,	I1	},
-{"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,	I1	},
+{"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
+{"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
+{"div",     "d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		I1	},
+{"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		I1	},
 {"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
 {"div.s",   "D,V,T",	0x46000003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
 /* For divu, see the comments about div.  */
-{"divu",    "z,s,t",	0x0000001b, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1	},
-{"divu",    "z,t",	0x0000001b, 0xffe0ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1	},
-{"divu",    "d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,	I1	},
-{"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,	I1	},
-{"dla",     "t,o(b)",	0x64000000, 0xfc000000, WR_t|RD_s,	I3	}, /* daddiu */
-{"dla",     "t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,	I3	},
-{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,	I3	}, /* addiu */
-{"dli",	    "t,i",	0x34000000, 0xffe00000, WR_t,	I3	}, /* ori */
-{"dli",     "t,I",	0,    (int) M_DLI,	INSN_MACRO,	I3	},
-
-{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO,	V1	},
-{"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,	I3	},
+{"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
+{"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
+{"divu",    "d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		I1	},
+{"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		I1	},
+{"dla",     "t,o(b)",	0x64000000, 0xfc000000, WR_t|RD_s,		I3	}, /* daddiu */
+{"dla",     "t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		I3	},
+{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,			I3	}, /* addiu */
+{"dli",	    "t,i",	0x34000000, 0xffe00000, WR_t,			I3	}, /* ori */
+{"dli",     "t,I",	0,    (int) M_DLI,	INSN_MACRO,		I3	},
+
+{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       V1      },
+{"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,		I3	},
+{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	I64     },
 {"dmtc0",   "t,G",	0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,	I3	},
+{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
 {"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,	I3	},
+{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
 {"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,	I3	},
-{"dmfc2",   "t,S",	0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,	I3	},
-{"dmtc2",   "t,S",	0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,	I3	},
-{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,	I3	},
-{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,	I3	},
-{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,	I3	},
-{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,	I3	},
-{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,	I3	},
-{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,	I3	},
-{"dmult",   "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,	    I3},
-{"dmultu",  "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,      I3},
-{"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,	I3	}, /* dsub 0 */
-{"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,	I3	}, /* dsubu 0*/
-{"drem",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
-{"drem",    "d,v,t",	3,    (int) M_DREM_3,	INSN_MACRO,	I3	},
-{"drem",    "d,v,I",	3,    (int) M_DREM_3I,	INSN_MACRO,	I3	},
-{"dremu",   "z,s,t",	0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
-{"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,	I3	},
-{"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,	I3	},
-{"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	},
-{"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,	I3	},
-{"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	}, /* dsllv */
-{"dsll",    "d,w,>",	0x0000003c, 0xffe0003f, WR_d|RD_t,	I3	}, /* dsll32 */
-{"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t,	I3	},
-{"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	},
-{"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t,	I3	},
-{"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	}, /* dsrav */
-{"dsra",    "d,w,>",	0x0000003f, 0xffe0003f, WR_d|RD_t,	I3	}, /* dsra32 */
-{"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t,	I3	},
-{"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	},
-{"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t,	I3	},
-{"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	}, /* dsrlv */
-{"dsrl",    "d,w,>",	0x0000003e, 0xffe0003f, WR_d|RD_t,	I3	}, /* dsrl32 */
-{"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t,	I3	},
-{"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
-{"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
-{"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
-{"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
-{"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1	},
-{"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
-{"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
-{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,	I2	},
-{"flushi",  "",		0xbc010000, 0xffffffff, 0,		L1	},
-{"flushd",  "",		0xbc020000, 0xffffffff, 0, L1		},
-{"flushid", "",		0xbc030000, 0xffffffff, 0, L1		},
-{"hibernate","",        0x42000023, 0xffffffff,	0, V1	},
-{"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,	I1	},
-{"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,	I1	}, /* jr */
+{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I3      },
+{"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 	I3      },
+{"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 	I64     },
+{"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I3      },
+{"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I64     },
+{"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 	I3      },
+{"dmfc3",   "t,G,H",    0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, 	I64     },
+{"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I3      },
+{"dmtc3",   "t,G,H",    0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I64     },
+{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		I3	},
+{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		I3	},
+{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		I3	},
+{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		I3	},
+{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		I3	},
+{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		I3	},
+{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3	},
+{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3	},
+{"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,		I3	}, /* dsub 0 */
+{"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		I3	}, /* dsubu 0*/
+{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
+{"drem",    "d,v,t",	3,    (int) M_DREM_3,	INSN_MACRO,		I3	},
+{"drem",    "d,v,I",	3,    (int) M_DREM_3I,	INSN_MACRO,		I3	},
+{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
+{"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,		I3	},
+{"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,		I3	},
+{"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	},
+{"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,		I3	},
+{"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	}, /* dsllv */
+{"dsll",    "d,w,>",	0x0000003c, 0xffe0003f, WR_d|RD_t,		I3	}, /* dsll32 */
+{"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t,		I3	},
+{"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	},
+{"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t,		I3	},
+{"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	}, /* dsrav */
+{"dsra",    "d,w,>",	0x0000003f, 0xffe0003f, WR_d|RD_t,		I3	}, /* dsra32 */
+{"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t,		I3	},
+{"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	},
+{"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t,		I3	},
+{"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		I3	}, /* dsrlv */
+{"dsrl",    "d,w,>",	0x0000003e, 0xffe0003f, WR_d|RD_t,		I3	}, /* dsrl32 */
+{"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t,		I3	},
+{"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t,		I3	},
+{"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		I3	},
+{"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,		I3	},
+{"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		I3	},
+{"eret",    "",         0x42000018, 0xffffffff, 0,      		I3|I32	},
+{"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
+{"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
+{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		I2	},
+{"flushi",  "",		0xbc010000, 0xffffffff, 0,			L1	},
+{"flushd",  "",		0xbc020000, 0xffffffff, 0, 			L1	},
+{"flushid", "",		0xbc030000, 0xffffffff, 0, 			L1	},
+{"hibernate","",        0x42000023, 0xffffffff,	0, 			V1	},
+{"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		I1	},
+{"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		I1	}, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
-{"j",	    "a",	0,     (int) M_J_A,	INSN_MACRO,	I1	},
+{"j",	    "a",	0,     (int) M_J_A,	INSN_MACRO,		I1	},
 /* This form of j is used by the disassembler and internally by the
    assembler, but will never match user input (because the line above
    will match first).  */
-{"j",       "a",	0x08000000, 0xfc000000,	UBD,		I1	},
-{"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,	I1	},
-{"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,	I1	},
+{"j",       "a",	0x08000000, 0xfc000000,	UBD,			I1	},
+{"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,		I1	},
+{"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,		I1	},
 /* SVR4 PIC code requires special handling for jal, so it must be a
    macro.  */
-{"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,	I1	},
-{"jal",     "s",	0,     (int) M_JAL_1,	INSN_MACRO,	I1	},
-{"jal",     "a",	0,     (int) M_JAL_A,	INSN_MACRO,	I1	},
+{"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,		I1	},
+{"jal",     "s",	0,     (int) M_JAL_1,	INSN_MACRO,		I1	},
+{"jal",     "a",	0,     (int) M_JAL_A,	INSN_MACRO,		I1	},
 /* This form of jal is used by the disassembler and internally by the
    assembler, but will never match user input (because the line above
    will match first).  */
-{"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,	I1	},
+{"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		I1	},
   /* jalx really should only be avaliable if mips16 is available,
      but for now make it I1. */
-{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,	I1      },
-{"la",      "t,o(b)",	0x24000000, 0xfc000000,	WR_t|RD_s,	I1	}, /* addiu */
-{"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,	I1	},
-{"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,	I1	},
-{"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO,	I1	},
-{"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,	I3	},
-{"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,	I1	},
-{"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,	I1	},
+{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		I1      },
+{"la",      "t,o(b)",	0x24000000, 0xfc000000,	WR_t|RD_s,		I1	}, /* addiu */
+{"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		I1	},
+{"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,		I1	},
+{"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO,		I1	},
+{"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		I3	},
+{"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		I1	},
+{"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		I1	},
 {"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	I2	},
 {"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	I2	},
-{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,	I2	},
-{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,	I2	},
+{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		I2	},
+{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		I2	},
 {"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	I2	}, /* ldc1 */
-{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,	I1	},
-{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,	I1	},
-{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,	I2	},
-{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,	I2	},
-{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,	I2	},
-{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,	I2	},
-{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,	I3	},
-{"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,	I3	},
-{"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,	I3	},
-{"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,	I3	},
+{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		I1	},
+{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		I1	},
+{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		I2	},
+{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		I2	},
+{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		I2	},
+{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		I2	},
+{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		I3	},
+{"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		I3	},
+{"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		I3	},
+{"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		I3	},
 {"ldxc1",   "D,t(b)",	0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
-{"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,	I1	},
-{"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,	I1	},
+{"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,		I1	},
+{"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,		I1	},
 /* li is at the start of the table.  */
-{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,	I1	},
-{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,	I1	},
-{"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,	I1	},
-{"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,	I1	},
-{"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,	I2	},
-{"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,	I2	},
-{"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,	I3	},
-{"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,	I3	},
-{"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t,		I1	},
+{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		I1	},
+{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		I1	},
+{"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,		I1	},
+{"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,		I1	},
+{"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,		I2	},
+{"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		I2	},
+{"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,		I3	},
+{"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		I3	},
+{"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t,			I1	},
 {"luxc1",   "D,t(b)",	0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I5	},
-{"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,	I1	},
-{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC,	I1	},
-{"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,	I1	},
+{"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,		I1	},
+{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC,		I1	},
+{"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		I1	},
 {"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	I1	},
 {"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	I1	},
-{"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,	I1	},
-{"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,	I1	},
+{"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		I1	},
+{"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		I1	},
 {"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	I1	}, /* lwc1 */
-{"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,	I1	},
-{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,	I1	},
-{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,	I1	},
-{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,	I1	},
-{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,	I1	},
-{"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,	I1	},
-{"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,	I2	}, /* same */
-{"lcache",  "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,	I2	}, /* as lwl */
-{"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,	I1	},
-{"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,	I1	},
-{"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,	I2	}, /* same */
-{"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,	I2	}, /* as lwr */
-{"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
-{"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
+{"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		I1	},
+{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		I1	},
+{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		I1	},
+{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		I1	},
+{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		I1	},
+{"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		I1	},
+{"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		I2	}, /* same */
+{"lcache",  "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		I2	}, /* as lwl */
+{"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},
+{"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		I1	},
+{"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		I2	}, /* same */
+{"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		I2	}, /* as lwr */
+{"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,		I3	},
+{"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		I3	},
 {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
-
-
-{"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3	},
-{"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3	},
-{"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
-{"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
-{"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
-{"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
-{"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
-{"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
-{"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
-{"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
-{"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
-{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
-{"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
+{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
+{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
+{"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I4	},
+{"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    I4	},
+{"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I5	},
+{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1 },
+{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
+{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32},
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1	},
+{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1	},
+{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          V1 },
+{"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,		I1	},
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	I32     },
 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
 {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
-{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
-{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
-{"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,	I1	},
-{"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,	I1	},
-{"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
-{"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,	I1	},
-{"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,	I5	},
-{"movf",    "d,s,N",	0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|M1},
-{"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
-{"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
+{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,		I1	},
+{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 	I32     },
+{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		I1	},
+{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	I32     },
+{"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		I1	},
+{"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		I1	},
+{"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
+{"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
+{"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,		I5	},
+{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
+{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32	},
+{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32	},
 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
-{"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1	},
-{"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
-{"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
-{"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
-{"movt",    "d,s,N",	0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,	I4|M1	},
-{"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
-{"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
-{"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
-{"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1	},
-{"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
-{"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
-{"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	I4|I32	},
+{"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		L1	},
+{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32	},
+{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32	},
+{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32	},
+{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32	},
+{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32	},
+{"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	I4|I32	},
+{"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		L1	},
+{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32	},
+{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32	},
 /* move is at the top of the table.  */
-{"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
-{"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
-{"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
-{"msub",    "s,t",	0x0000001e, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
-{"msubu",   "s,t",	0x0000001f, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
+{"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4	},
+{"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4	},
+{"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5	},
+{"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	L1    	},
+{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
+{"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	L1	},
+{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
+{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
 {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
 {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
+{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
 {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	I1	},
-{"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,	I1	},
-{"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,	I1	},
+{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
+{"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		I1	},
+{"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		I1	},
 {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
 {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
 {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
-{"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
-{"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
-{"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
-{"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
-{"mulo",    "d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,	I1	},
-{"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,	I1	},
-{"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,	I1	},
-{"mult",    "s,t",	0x00000018, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	I1},
-{"mult",    "d,s,t",	0x00000018, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
-{"multu",   "s,t",	0x00000019, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	I1},
-{"multu",   "d,s,t",	0x00000019, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
-{"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,	I1	}, /* sub 0 */
-{"negu",    "d,w",	0x00000023, 0xffe007ff,	WR_d|RD_t,	I1	}, /* subu 0 */
-{"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
-{"neg.s",   "D,V",	0x46000007, 0xffff003f,	WR_D|RD_S|FP_S,	I1	},
-{"neg.ps",  "D,V",	0x46c00007, 0xffff003f,	WR_D|RD_S|FP_D,I5	},
-{"nmadd.d", "D,R,S,T",	0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
-{"nmadd.s", "D,R,S,T",	0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
-{"nmadd.ps","D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
-{"nmsub.d", "D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
-{"nmsub.s", "D,R,S,T",	0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
-{"nmsub.ps","D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
+{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3  },
+{"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		I1	},
+{"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		I1	},
+{"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		I1	},
+{"mulo",    "d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		I1	},
+{"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		I1	},
+{"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		I1	},
+{"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1	},
+{"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1	},
+{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1	},
+{"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1	},
+{"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		I1	}, /* sub 0 */
+{"negu",    "d,w",	0x00000023, 0xffe007ff,	WR_d|RD_t,		I1	}, /* subu 0 */
+{"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},
+{"neg.s",   "D,V",	0x46000007, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},
+{"neg.ps",  "D,V",	0x46c00007, 0xffff003f,	WR_D|RD_S|FP_D,		I5	},
+{"nmadd.d", "D,R,S,T",	0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4	},
+{"nmadd.s", "D,R,S,T",	0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4	},
+{"nmadd.ps","D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5	},
+{"nmsub.d", "D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4	},
+{"nmsub.s", "D,R,S,T",	0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4	},
+{"nmsub.ps","D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5	},
 /* nop is at the start of the table.  */
-{"nor",     "d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"nor",     "t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,	I1	},
-{"not",     "d,v",	0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,	I1	},/*nor d,s,0*/
-{"or",      "d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"or",      "t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,	I1	},
-{"ori",     "t,r,i",	0x34000000, 0xfc000000,	WR_t|RD_s,	I1	},
-
-{"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-{"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-
-{"pref",    "k,o(b)",	0xcc000000, 0xfc000000, RD_b,		G3|M1	},
-{"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,	I4	},
-
-{"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-{"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5},
-
-{"recip.d", "D,S",	0x46200015, 0xffff003f, WR_D|RD_S|FP_D,	I4	},
-{"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,	I4	},
-{"rem",     "z,s,t",	0x0000001a, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1 },
-{"rem",     "d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,	I1	},
-{"rem",     "d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,	I1	},
-{"remu",    "z,s,t",	0x0000001b, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,	I1 },
-{"remu",    "d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,	I1	},
-{"remu",    "d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,	I1	},
-{"rfe",     "",		0x42000010, 0xffffffff,	0,	I1|T3		},
-{"rol",     "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,	I1	},
-{"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,	I1	},
-{"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,	I1	},
-{"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,	I1	},
-{"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
-{"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
-{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,	I2	},
-{"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,	I4	},
-{"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,	I4	},
-{"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,	I1	},
-{"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,	I1	},
+{"nor",     "d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"nor",     "t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		I1	},
+{"not",     "d,v",	0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,		I1	},/*nor d,s,0*/
+{"or",      "d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"or",      "t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		I1	},
+{"ori",     "t,r,i",	0x34000000, 0xfc000000,	WR_t|RD_s,		I1	},
+
+{"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+
+/* pref is at the start of the table.  */
+{"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,		I4	},
+
+{"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+{"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
+
+{"recip.d", "D,S",	0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		I4	},
+{"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
+{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1	},
+{"rem",     "d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		I1	},
+{"rem",     "d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		I1	},
+{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1	},
+{"remu",    "d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		I1	},
+{"remu",    "d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		I1	},
+{"rfe",     "",		0x42000010, 0xffffffff,	0,			I1|T3	},
+{"rol",     "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		I1	},
+{"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		I1	},
+{"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		I1	},
+{"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		I1	},
+{"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
+{"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
+{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		I2	},
+{"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		I4	},
+{"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		I4	},
+{"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
+{"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		I1	},
 {"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	I2	},
-{"sc",	    "t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,	I2	},
+{"sc",	    "t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		I2	},
 {"scd",	    "t,o(b)",	0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	I3	},
-{"scd",	    "t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,	I3	},
-{"sd",	    "t,o(b)",	0xfc000000, 0xfc000000,	SM|RD_t|RD_b,	I3	},
-{"sd",      "t,o(b)",	0,    (int) M_SD_OB,	INSN_MACRO,	I1	},
-{"sd",      "t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO,	I1	},
-{"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           G2|M1	},
-{"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,		G2|M1	},
-{"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,		G2|M1	},
+{"scd",	    "t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,		I3	},
+{"sd",	    "t,o(b)",	0xfc000000, 0xfc000000,	SM|RD_t|RD_b,		I3	},
+{"sd",      "t,o(b)",	0,    (int) M_SD_OB,	INSN_MACRO,		I1	},
+{"sd",      "t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO,		I1	},
+{"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           	G2	},
+{"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,			G2	},
+{"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,			G2	},
+{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	I32     },
+{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	I32     },
 {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
 {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
-{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
-{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
-{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,	I2	},
-{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,	I2	},
-{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,	I2	},
-{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,	I2	},
+{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		I2	},
+{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		I2	},
+{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		I2	},
+{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		I2	},
+{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		I2	},
+{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		I2	},
 {"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
-{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,	I1	},
-{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,	I1	},
-{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,	I3	},
-{"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,	I3	},
-{"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,	I3	},
-{"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,	I3	},
+{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		I1	},
+{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		I1	},
+{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		I3	},
+{"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		I3	},
+{"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		I3	},
+{"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		I3	},
 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	I4	},
-{"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,L1	},
-{"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,L1	},
-{"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,	I1	},
-{"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,	I1	},
-{"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,	I1	},
-{"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,	I1	},
-{"sgeu",    "d,v,t",	0,    (int) M_SGEU,	INSN_MACRO,	I1	},
-{"sgeu",    "d,v,I",	0,    (int) M_SGEU_I,	INSN_MACRO,	I1	},
-{"sgt",     "d,v,t",	0,    (int) M_SGT,	INSN_MACRO,	I1	},
-{"sgt",     "d,v,I",	0,    (int) M_SGT_I,	INSN_MACRO,	I1	},
-{"sgtu",    "d,v,t",	0,    (int) M_SGTU,	INSN_MACRO,	I1	},
-{"sgtu",    "d,v,I",	0,    (int) M_SGTU_I,	INSN_MACRO,	I1	},
-{"sh",      "t,o(b)",	0xa4000000, 0xfc000000,	SM|RD_t|RD_b,	I1	},
-{"sh",      "t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,	I1	},
-{"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,	I1	},
-{"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,	I1	},
-{"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,	I1	},
-{"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,	I1	},
-{"sllv",    "d,t,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	},
-{"sll",     "d,w,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	}, /* sllv */
-{"sll",     "d,w,<",	0x00000000, 0xffe0003f,	WR_d|RD_t,	I1	},
-{"slt",     "d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,	I1	},
-{"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,	I1	},
-{"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,	I1	},
-{"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,	I1	},
-{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,	I2	},
-{"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	},
-{"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	}, /* srav */
-{"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t,	I1	},
-{"srlv",    "d,t,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	},
-{"srl",     "d,w,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,	I1	}, /* srlv */
-{"srl",     "d,w,<",	0x00000002, 0xffe0003f,	WR_d|RD_t,	I1	},
-{"ssnop",     "",	0x00000040, 0xffffffff,	0,		M1	},
-{"standby", "",         0x42000021, 0xffffffff,	0,		V1	},
-{"sub",     "d,v,t",	0x00000022, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,	I1	},
+{"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,		L1	},
+{"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,		L1	},
+{"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		I1	},
+{"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		I1	},
+{"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		I1	},
+{"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		I1	},
+{"sgeu",    "d,v,t",	0,    (int) M_SGEU,	INSN_MACRO,		I1	},
+{"sgeu",    "d,v,I",	0,    (int) M_SGEU_I,	INSN_MACRO,		I1	},
+{"sgt",     "d,v,t",	0,    (int) M_SGT,	INSN_MACRO,		I1	},
+{"sgt",     "d,v,I",	0,    (int) M_SGT_I,	INSN_MACRO,		I1	},
+{"sgtu",    "d,v,t",	0,    (int) M_SGTU,	INSN_MACRO,		I1	},
+{"sgtu",    "d,v,I",	0,    (int) M_SGTU_I,	INSN_MACRO,		I1	},
+{"sh",      "t,o(b)",	0xa4000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
+{"sh",      "t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,		I1	},
+{"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		I1	},
+{"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		I1	},
+{"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		I1	},
+{"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		I1	},
+{"sllv",    "d,t,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	},
+{"sll",     "d,w,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	}, /* sllv */
+{"sll",     "d,w,<",	0x00000000, 0xffe0003f,	WR_d|RD_t,		I1	},
+{"slt",     "d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		I1	},
+{"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		I1	},
+{"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		I1	},
+{"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		I1	},
+{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,		I2	},
+{"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	},
+{"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	}, /* srav */
+{"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t,		I1	},
+{"srlv",    "d,t,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	},
+{"srl",     "d,w,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		I1	}, /* srlv */
+{"srl",     "d,w,<",	0x00000002, 0xffe0003f,	WR_d|RD_t,		I1	},
+/* ssnop is at the start of the table.  */
+{"standby", "",         0x42000021, 0xffffffff,	0,			V1	},
+{"sub",     "d,v,t",	0x00000022, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		I1	},
 {"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},     
 {"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
 {"sub.ps",  "D,V,T",	0x46c00001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
-{"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,	I1	},
-{"suspend", "",         0x42000022, 0xffffffff,	0,		V1	},
+{"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		I1	},
+{"suspend", "",         0x42000022, 0xffffffff,	0,			V1	},
 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	I5	},
-{"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,	I1	},
-{"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,	I1	},
-{"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,	I1	},
-{"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,	I1	},
+{"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
+{"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		I1	},
+{"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,		I1	},
+{"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		I1	},
 {"swc1",    "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	I1	},
 {"swc1",    "E,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	I1	},
-{"swc1",    "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,	I1	},
-{"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,	I1	},
+{"swc1",    "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		I1	},
+{"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		I1	},
 {"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	I1	}, /* swc1 */
-{"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,	I1	},
-{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,	I1	},
-{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,	I1	},
-{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,	I1	},
-{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,	I1	},
-{"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,	I1	},
-{"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,	I1	},
-{"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,	I2	}, /* same */
-{"scache",  "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,	I2	}, /* as swl */
-{"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	SM|RD_t|RD_b,	I1	},
-{"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,	I1	},
-{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,	I2	}, /* same */
-{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,	I2	}, /* as swr */
+{"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		I1	},
+{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		I1	},
+{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		I1	},
+{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		I1	},
+{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		I1	},
+{"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
+{"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		I1	},
+{"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,		I2	}, /* same */
+{"scache",  "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		I2	}, /* as swl */
+{"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	SM|RD_t|RD_b,		I1	},
+{"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		I1	},
+{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		I2	}, /* same */
+{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		I2	}, /* as swr */
 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	I4	},
-{"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,	I2|G1	},
-{"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,	I2	},
-{"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,	I2	},
-{"syscall", "",		0x0000000c, 0xffffffff,	TRAP,	I1		},
-{"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,	I1		},
-{"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,	I2	},
-{"teq",	    "s,t",	0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	},
-{"teq",	    "s,t,q",	0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,	I2	},
-{"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,	I2	}, /* teqi */
-{"teq",     "s,I",	0,    (int) M_TEQ_I,	INSN_MACRO,	I2	},
-{"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,	I2	},
-{"tge",	    "s,t",	0x00000030, 0xfc00ffff,	RD_s|RD_t|TRAP,	I2	},
-{"tge",	    "s,t,q",	0x00000030, 0xfc00003f,	RD_s|RD_t|TRAP,	I2	},
-{"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,	I2	}, /* tgei */
-{"tge",	    "s,I",	0,    (int) M_TGE_I,    INSN_MACRO,	I2	},
-{"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		},
-{"tgeu",    "s,t",	0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
-{"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
-{"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
-{"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
-{"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1	},
-{"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1	},
-{"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1	},
-{"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1	},
-{"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
-{"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
-{"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
-{"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		}, /* tlti */
-{"tlt",     "s,I",	0,    (int) M_TLT_I,	INSN_MACRO,	I2	},
-{"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,	I2		},
-{"tltu",    "s,t",	0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
-{"tltu",    "s,t,q",	0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
-{"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tltiu */
-{"tltu",    "s,I",	0,    (int) M_TLTU_I,	INSN_MACRO,	I2	},
-{"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,	I2		},
-{"tne",     "s,t",	0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
-{"tne",     "s,t,q",	0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
-{"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tnei */
-{"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,	I2	},
-{"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
-{"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|FP_S,	I3	},
-{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
-{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,	I1	},
-{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,	I2	},
-{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,	I2	},
-{"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,	I1	},
-{"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,	I3	},
-{"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,	I3	},
-{"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO,	I1	},
-{"ulh",     "t,A(b)",	0,    (int) M_ULH_A,	INSN_MACRO,	I1	},
-{"ulhu",    "t,o(b)",	0,    (int) M_ULHU,	INSN_MACRO,	I1	},
-{"ulhu",    "t,A(b)",	0,    (int) M_ULHU_A,	INSN_MACRO,	I1	},
-{"ulw",     "t,o(b)",	0,    (int) M_ULW,	INSN_MACRO,	I1	},
-{"ulw",     "t,A(b)",	0,    (int) M_ULW_A,	INSN_MACRO,	I1	},
-{"usd",     "t,o(b)",	0,    (int) M_USD,	INSN_MACRO,	I3	},
-{"usd",     "t,A(b)",	0,    (int) M_USD_A,	INSN_MACRO,	I3	},
-{"ush",     "t,o(b)",	0,    (int) M_USH,	INSN_MACRO,	I1	},
-{"ush",     "t,A(b)",	0,    (int) M_USH_A,	INSN_MACRO,	I1	},
-{"usw",     "t,o(b)",	0,    (int) M_USW,	INSN_MACRO,	I1	},
-{"usw",     "t,A(b)",	0,    (int) M_USW_A,	INSN_MACRO,	I1	},
-{"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
-{"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
-{"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1	},
-{"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
-{"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
+{"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		I2|G1	},
+{"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		I2	},
+{"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		I2	},
+{"syscall", "",		0x0000000c, 0xffffffff,	TRAP,			I1	},
+{"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,			I1	},
+{"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		I2	},
+{"teq",	    "s,t",	0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,		I2	},
+{"teq",	    "s,t,q",	0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,		I2	},
+{"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		I2	}, /* teqi */
+{"teq",     "s,I",	0,    (int) M_TEQ_I,	INSN_MACRO,		I2	},
+{"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		I2	},
+{"tge",	    "s,t",	0x00000030, 0xfc00ffff,	RD_s|RD_t|TRAP,		I2	},
+{"tge",	    "s,t,q",	0x00000030, 0xfc00003f,	RD_s|RD_t|TRAP,		I2	},
+{"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		I2	}, /* tgei */
+{"tge",	    "s,I",	0,    (int) M_TGE_I,    INSN_MACRO,		I2	},
+{"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		I2	},
+{"tgeu",    "s,t",	0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,		I2	},
+{"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,		I2	},
+{"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		I2	}, /* tgeiu */
+{"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,		I2	},
+{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       	I1   	},
+{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       	I1   	},
+{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       	I1   	},
+{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       	I1   	},
+{"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		I2	},
+{"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,		I2	},
+{"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,		I2	},
+{"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		I2	}, /* tlti */
+{"tlt",     "s,I",	0,    (int) M_TLT_I,	INSN_MACRO,		I2	},
+{"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		I2	},
+{"tltu",    "s,t",	0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,		I2	},
+{"tltu",    "s,t,q",	0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,		I2	},
+{"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		I2	}, /* tltiu */
+{"tltu",    "s,I",	0,    (int) M_TLTU_I,	INSN_MACRO,		I2	},
+{"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		I2	},
+{"tne",     "s,t",	0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,		I2	},
+{"tne",     "s,t,q",	0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,		I2	},
+{"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		I2	}, /* tnei */
+{"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,		I2	},
+{"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
+{"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|FP_S,		I3	},
+{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
+{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		I1	},
+{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		I2	},
+{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		I2	},
+{"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		I1	},
+{"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,		I3	},
+{"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,		I3	},
+{"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO,		I1	},
+{"ulh",     "t,A(b)",	0,    (int) M_ULH_A,	INSN_MACRO,		I1	},
+{"ulhu",    "t,o(b)",	0,    (int) M_ULHU,	INSN_MACRO,		I1	},
+{"ulhu",    "t,A(b)",	0,    (int) M_ULHU_A,	INSN_MACRO,		I1	},
+{"ulw",     "t,o(b)",	0,    (int) M_ULW,	INSN_MACRO,		I1	},
+{"ulw",     "t,A(b)",	0,    (int) M_ULW_A,	INSN_MACRO,		I1	},
+{"usd",     "t,o(b)",	0,    (int) M_USD,	INSN_MACRO,		I3	},
+{"usd",     "t,A(b)",	0,    (int) M_USD_A,	INSN_MACRO,		I3	},
+{"ush",     "t,o(b)",	0,    (int) M_USH,	INSN_MACRO,		I1	},
+{"ush",     "t,A(b)",	0,    (int) M_USH_A,	INSN_MACRO,		I1	},
+{"usw",     "t,o(b)",	0,    (int) M_USW,	INSN_MACRO,		I1	},
+{"usw",     "t,A(b)",	0,    (int) M_USW_A,	INSN_MACRO,		I1	},
+{"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
+{"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		I1	},
+{"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		I1	},
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,   		I3|I32	},
+{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   		I32     },
+{"waiti",   "",		0x42000020, 0xffffffff,	TRAP,			L1	},
+{"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,		L1	},
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
    disasembler recognizes more specific versions first.  */
-{"c0",      "C",	0x42000000, 0xfe000000,	0,	I1		},
-{"c1",      "C",	0x46000000, 0xfe000000,	0,	I1		},
-{"c2",      "C",	0x4a000000, 0xfe000000,	0,	I1		},
-{"c3",      "C",	0x4e000000, 0xfe000000,	0,	I1		},
-{"cop0",     "C",	0,    (int) M_COP0,	INSN_MACRO,	I1	},
-{"cop1",     "C",	0,    (int) M_COP1,	INSN_MACRO,	I1	},
-{"cop2",     "C",	0,    (int) M_COP2,	INSN_MACRO,	I1	},
-{"cop3",     "C",	0,    (int) M_COP3,	INSN_MACRO,	I1	},
+{"c0",      "C",	0x42000000, 0xfe000000,	0,			I1	},
+{"c1",      "C",	0x46000000, 0xfe000000,	0,			I1	},
+{"c2",      "C",	0x4a000000, 0xfe000000,	0,			I1	},
+{"c3",      "C",	0x4e000000, 0xfe000000,	0,			I1	},
+{"cop0",     "C",	0,    (int) M_COP0,	INSN_MACRO,		I1	},
+{"cop1",     "C",	0,    (int) M_COP1,	INSN_MACRO,		I1	},
+{"cop2",     "C",	0,    (int) M_COP2,	INSN_MACRO,		I1	},
+{"cop3",     "C",	0,    (int) M_COP3,	INSN_MACRO,		I1	},
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
      format gave us more info, we could do this right.  */
-{"addciu",  "t,r,j",	0x70000000, 0xfc000000,	WR_t|RD_s,L1	},
+{"addciu",  "t,r,j",	0x70000000, 0xfc000000,	WR_t|RD_s,		L1	},
 };
 
 #define MIPS_NUM_OPCODES \
diff --git a/gnu/usr.bin/binutils/opcodes/ns32k-dis.c b/gnu/usr.bin/binutils/opcodes/ns32k-dis.c
index 050266be849..610e37305f7 100644
--- a/gnu/usr.bin/binutils/opcodes/ns32k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/ns32k-dis.c
@@ -1,5 +1,6 @@
 /* Print National Semiconductor 32000 instructions.
-   Copyright (c) 1986, 88, 91, 92, 94, 95, 1998 Free Software Foundation, Inc.
+   Copyright 1986, 1988, 1991, 1992, 1994, 1998
+   Free Software Foundation, Inc.
 
 This file is part of opcodes library.
 
diff --git a/gnu/usr.bin/binutils/opcodes/ppc-dis.c b/gnu/usr.bin/binutils/opcodes/ppc-dis.c
index f2566328548..c59a9201f67 100644
--- a/gnu/usr.bin/binutils/opcodes/ppc-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/ppc-dis.c
@@ -1,5 +1,5 @@
 /* ppc-dis.c -- Disassemble PowerPC instructions
-   Copyright 1994 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -33,7 +33,8 @@ static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
 				       int bigendian, int dialect));
 
 /* Print a big endian PowerPC instruction.  For convenience, also
-   disassemble instructions supported by the Motorola PowerPC 601.  */
+   disassemble instructions supported by the Motorola PowerPC 601
+   and the Altivec vector unit.  */
 
 int
 print_insn_big_powerpc (memaddr, info)
@@ -41,11 +42,13 @@ print_insn_big_powerpc (memaddr, info)
      struct disassemble_info *info;
 {
   return print_insn_powerpc (memaddr, info, 1,
-			     PPC_OPCODE_PPC | PPC_OPCODE_601);
+			     PPC_OPCODE_PPC | PPC_OPCODE_601 |
+			     PPC_OPCODE_ALTIVEC);
 }
 
 /* Print a little endian PowerPC instruction.  For convenience, also
-   disassemble instructions supported by the Motorola PowerPC 601.  */
+   disassemble instructions supported by the Motorola PowerPC 601
+   and the Altivec vector unit.  */
 
 int
 print_insn_little_powerpc (memaddr, info)
@@ -53,7 +56,8 @@ print_insn_little_powerpc (memaddr, info)
      struct disassemble_info *info;
 {
   return print_insn_powerpc (memaddr, info, 0,
-			     PPC_OPCODE_PPC | PPC_OPCODE_601);
+			     PPC_OPCODE_PPC | PPC_OPCODE_601 |
+			     PPC_OPCODE_ALTIVEC);
 }
 
 /* Print a POWER (RS/6000) instruction.  */
@@ -181,6 +185,8 @@ print_insn_powerpc (memaddr, info, bigendian, dialect)
 	    (*info->fprintf_func) (info->stream, "r%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 	    (*info->fprintf_func) (info->stream, "f%ld", value);
+	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
+	    (*info->fprintf_func) (info->stream, "v%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 	    (*info->print_address_func) (memaddr + value, info);
 	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
diff --git a/gnu/usr.bin/binutils/opcodes/ppc-opc.c b/gnu/usr.bin/binutils/opcodes/ppc-opc.c
index 02fb7a4edf6..aa9616f2499 100644
--- a/gnu/usr.bin/binutils/opcodes/ppc-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/ppc-opc.c
@@ -1,5 +1,6 @@
 /* ppc-opc.c -- PowerPC opcode list
-   Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000
+   Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -396,6 +397,39 @@ const struct powerpc_operand powerpc_operands[] =
   /* The UI field in a D form instruction.  */
 #define UI U + 1
   { 16, 0, 0, 0, 0 },
+
+  /* The VA field in a VA, VX or VXR form instruction. */
+#define VA UI + 1
+#define VA_MASK	(0x1f << 16)
+  {5, 16, 0, 0, PPC_OPERAND_VR},
+
+  /* The VB field in a VA, VX or VXR form instruction. */
+#define VB VA + 1
+#define VB_MASK (0x1f << 11)
+  {5, 11, 0, 0, PPC_OPERAND_VR}, 
+
+  /* The VC field in a VA form instruction. */
+#define VC VB + 1
+#define VC_MASK (0x1f << 6)
+  {5, 6, 0, 0, PPC_OPERAND_VR},
+
+  /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+#define VD VC + 1
+#define VS VD
+#define VD_MASK (0x1f << 21)
+  {5, 21, 0, 0, PPC_OPERAND_VR},
+
+  /* The SIMM field in a VX form instruction. */
+#define SIMM VD + 1
+  { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
+
+  /* The UIMM field in a VX form instruction. */
+#define UIMM SIMM + 1
+  { 5, 16, 0, 0, 0 },
+
+  /* The SHB field in a VA form instruction. */
+#define SHB UIMM + 1
+  { 4, 6, 0, 0, 0 },
 };
 
 /* The functions used to insert and extract complicated operands.  */
@@ -722,7 +756,7 @@ insert_mbe (insn, value, errmsg)
   /* me: location of last 1->0 transition */
   /* count: # transitions */
 
-  for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
+  for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
     {
       if ((uval & mask) && !last)
 	{
@@ -1105,6 +1139,24 @@ extract_tbr (insn, invalid)
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 
+/* An VX form instruction. */
+#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+/* The mask for an VX form instruction. */
+#define VX_MASK	VX(0x3f, 0x7ff)
+
+/* An VA form instruction. */
+#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
+
+/* The mask for an VA form instruction. */
+#define VXA_MASK VXA(0x3f, 0x7f)
+
+/* An VXR form instruction. */
+#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
+
+/* The mask for a VXR form instruction. */
+#define VXR_MASK VXR(0x3f, 0x3ff, 1)
+
 /* An X form instruction.  */
 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
@@ -1143,6 +1195,10 @@ extract_tbr (insn, invalid)
 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
 #define XTO_MASK (X_MASK | TO_MASK)
 
+/* An X form tlb instruction with the SH field specified.  */
+#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
+#define XTLB_MASK (X_MASK | SH_MASK)
+
 /* An XFL form instruction.  */
 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
@@ -1270,8 +1326,10 @@ extract_tbr (insn, invalid)
 #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
 #define PPCONLY	PPC_OPCODE_PPC
 #define PPC403	PPC
+#define PPC405	PPC403
 #define PPC750	PPC
 #define PPC860	PPC
+#define PPCVEC	PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
 #define	POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
 #define	POWER2	PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
 #define PPCPWR2	PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
@@ -1349,6 +1407,248 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
 { "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
 
+{ "macchw",	XO(4,172,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchw.",	XO(4,172,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwo",	XO(4,172,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwo.",	XO(4,172,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchws",	XO(4,236,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchws.",	XO(4,236,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwso",	XO(4,236,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwso.",	XO(4,236,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwsu",	XO(4,204,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwsu.",	XO(4,204,0,1), XO_MASK, PPC405,		{ RT, RA, RB } },
+{ "macchwsuo",	XO(4,204,1,0), XO_MASK, PPC405,		{ RT, RA, RB } },
+{ "macchwsuo.",	XO(4,204,1,1), XO_MASK, PPC405,		{ RT, RA, RB } },
+{ "macchwu",	XO(4,140,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwu.",	XO(4,140,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwuo",	XO(4,140,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "macchwuo.",	XO(4,140,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhw",	XO(4,44,0,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhw.",	XO(4,44,0,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwo",	XO(4,44,1,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwo.",	XO(4,44,1,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhws",	XO(4,108,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhws.",	XO(4,108,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwso",	XO(4,108,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwso.",	XO(4,108,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwsu",	XO(4,76,0,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwsu.",	XO(4,76,0,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwsuo",	XO(4,76,1,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwsuo.",	XO(4,76,1,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwu",	XO(4,12,0,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwu.",	XO(4,12,0,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwuo",	XO(4,12,1,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "machhwuo.",	XO(4,12,1,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhw",	XO(4,428,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhw.",	XO(4,428,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwo",	XO(4,428,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwo.",	XO(4,428,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhws",	XO(4,492,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhws.",	XO(4,492,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwso",	XO(4,492,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwso.",	XO(4,492,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwsu",	XO(4,460,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwsu.",	XO(4,460,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwsuo",	XO(4,460,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwsuo.",	XO(4,460,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwu",	XO(4,396,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwu.",	XO(4,396,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwuo",	XO(4,396,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "maclhwuo.",	XO(4,396,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulchw",	XRC(4,168,0),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulchw.",	XRC(4,168,1),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulchwu",	XRC(4,136,0),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulchwu.",	XRC(4,136,1),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulhhw",	XRC(4,40,0),   X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulhhw.",	XRC(4,40,1),   X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulhhwu",	XRC(4,8,0),    X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mulhhwu.",	XRC(4,8,1),    X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mullhw",	XRC(4,424,0),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mullhw.",	XRC(4,424,1),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mullhwu",	XRC(4,392,0),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mullhwu.",	XRC(4,392,1),  X_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchw",	XO(4,174,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchw.",	XO(4,174,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchwo",	XO(4,174,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchwo.",	XO(4,174,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchws",	XO(4,238,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchws.",	XO(4,238,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchwso",	XO(4,238,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmacchwso.",	XO(4,238,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhw",	XO(4,46,0,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhw.",	XO(4,46,0,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhwo",	XO(4,46,1,0),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhwo.",	XO(4,46,1,1),  XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhws",	XO(4,110,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhws.",	XO(4,110,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhwso",	XO(4,110,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmachhwso.",	XO(4,110,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhw",	XO(4,430,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhw.",	XO(4,430,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhwo",	XO(4,430,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhwo.",	XO(4,430,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhws",	XO(4,494,0,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhws.",	XO(4,494,0,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhwso",	XO(4,494,1,0), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "nmaclhwso.",	XO(4,494,1,1), XO_MASK,	PPC405,		{ RT, RA, RB } },
+{ "mfvscr",  VX(4, 1540), VX_MASK,	PPCVEC,		{ VD } },
+{ "mtvscr",  VX(4, 1604), VX_MASK,	PPCVEC,		{ VD } },
+{ "vaddcuw", VX(4,  384), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vaddfp",  VX(4,   10), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
+{ "vaddsbs", VX(4,  768), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vaddshs", VX(4,  832), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vaddsws", VX(4,  896), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vaddubm", VX(4,    0), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
+{ "vaddubs", VX(4,  512), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vadduhm", VX(4,   64), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vadduhs", VX(4,  576), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vadduwm", VX(4,  128), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vadduws", VX(4,  640), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vand",    VX(4, 1028), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vandc",   VX(4, 1092), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavgsb",  VX(4, 1282), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavgsh",  VX(4, 1346), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavgsw",  VX(4, 1410), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavgub",  VX(4, 1026), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavguh",  VX(4, 1090), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vavguw",  VX(4, 1154), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vcfsx",   VX(4,  842), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vcfux",   VX(4,  778), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
+{ "vctsxs",    VX(4,  970), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxsw",    VX(4,  386), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxub",    VX(4,    2), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxuh",    VX(4,   66), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmaxuw",    VX(4,  130), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmhaddshs", VXA(4,  32), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmhraddshs", VXA(4, 33), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vminfp",    VX(4, 1098), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminsb",    VX(4,  770), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminsh",    VX(4,  834), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminsw",    VX(4,  898), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminub",    VX(4,  514), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminuh",    VX(4,  578), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vminuw",    VX(4,  642), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmladduhm", VXA(4,  34), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmrghb",    VX(4,   12), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,		{ VD, VA, VB } },
+{ "vmrghw",    VX(4,  140), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmrglb",    VX(4,  268), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmrglh",    VX(4,  332), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmrglw",    VX(4,  396), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmsummbm",  VXA(4,  37), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmsumshm",  VXA(4,  40), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmsumshs",  VXA(4,  41), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmulesb",   VX(4,  776), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmulesh",   VX(4,  840), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmuleub",   VX(4,  520), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmuleuh",   VX(4,  584), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmulosb",   VX(4,  264), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmulosh",   VX(4,  328), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmuloub",   VX(4,    8), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vmulouh",   VX(4,   72), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vnmsubfp",  VXA(4,  47), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
+{ "vnor",      VX(4, 1284), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vor",       VX(4, 1156), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vperm",     VXA(4,  43), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vpkpx",     VX(4,  782), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkshss",   VX(4,  398), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkshus",   VX(4,  270), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkswss",   VX(4,  462), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkswus",   VX(4,  334), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkuhum",   VX(4,   14), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkuhus",   VX(4,  142), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkuwum",   VX(4,   78), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vpkuwus",   VX(4,  206), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vrefp",     VX(4,  266), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vrfim",     VX(4,  714), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vrfin",     VX(4,  522), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vrfip",     VX(4,  650), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vrfiz",     VX(4,  586), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vrlb",      VX(4,    4), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vrlh",      VX(4,   68), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vrlw",      VX(4,  132), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vrsqrtefp", VX(4,  330), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vsel",      VXA(4,  42), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vsl",       VX(4,  452), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vslb",      VX(4,  260), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsldoi",    VXA(4,  44), VXA_MASK,	PPCVEC,		{ VD, VA, VB, SHB } },
+{ "vslh",      VX(4,  324), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vslo",      VX(4, 1036), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vslw",      VX(4,  388), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vspltb",    VX(4,  524), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vsplth",    VX(4,  588), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vspltisb",  VX(4,  780), VX_MASK,	PPCVEC,		{ VD, SIMM } },
+{ "vspltish",  VX(4,  844), VX_MASK,	PPCVEC,		{ VD, SIMM } },
+{ "vspltisw",  VX(4,  908), VX_MASK,	PPCVEC,		{ VD, SIMM } },
+{ "vspltw",    VX(4,  652), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
+{ "vsr",       VX(4,  708), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsrab",     VX(4,  772), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsrah",     VX(4,  836), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsraw",     VX(4,  900), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsrb",      VX(4,  516), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsrh",      VX(4,  580), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsro",      VX(4, 1100), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsrw",      VX(4,  644), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubcuw",   VX(4, 1408), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubfp",    VX(4,   74), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubsbs",   VX(4, 1792), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubshs",   VX(4, 1856), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubsws",   VX(4, 1920), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsububm",   VX(4, 1024), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsububs",   VX(4, 1536), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubuhm",   VX(4, 1088), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubuhs",   VX(4, 1600), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubuwm",   VX(4, 1152), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsubuws",   VX(4, 1664), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsumsws",   VX(4, 1928), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsum2sws",  VX(4, 1672), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsum4sbs",  VX(4, 1800), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsum4shs",  VX(4, 1608), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vsum4ubs",  VX(4, 1544), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+{ "vupkhpx",   VX(4,  846), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vupkhsb",   VX(4,  526), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vupkhsh",   VX(4,  590), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vupklpx",   VX(4,  974), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vupklsb",   VX(4,  654), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vupklsh",   VX(4,  718), VX_MASK,	PPCVEC,		{ VD, VB } },
+{ "vxor",      VX(4, 1220), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
+
 { "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
 { "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
 
@@ -1388,269 +1688,269 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA,SISIGNOPT } },
 { "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
 
-{ "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,	{ BDM } },
-{ "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,	{ BDP } },
+{ "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,	{ BDM } },
+{ "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,	{ BDP } },
 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,	{ BD } },
 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,	{ BD } },
-{ "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,	{ BDM } },
-{ "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,	{ BDP } },
+{ "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,	{ BDM } },
+{ "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,	{ BDP } },
 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,	{ BD } },
 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,	{ BD } },
-{ "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,	{ BDMA } },
-{ "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,	{ BDPA } },
+{ "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,	{ BDMA } },
+{ "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,	{ BDPA } },
 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,	{ BDA } },
 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,	{ BDA } },
-{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,	{ BDMA } },
-{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,	{ BDPA } },
+{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,	{ BDMA } },
+{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,	{ BDPA } },
 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,	{ BDA } },
 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,	{ BDA } },
-{ "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPC,	{ BDM } },
-{ "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPC,	{ BDP } },
+{ "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,	{ BDM } },
+{ "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,	{ BDP } },
 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,	{ BD } },
-{ "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPC,	{ BDM } },
-{ "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPC,	{ BDP } },
+{ "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,	{ BDM } },
+{ "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,	{ BDP } },
 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,	{ BD } },
-{ "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPC,	{ BDMA } },
-{ "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPC,	{ BDPA } },
+{ "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,	{ BDMA } },
+{ "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,	{ BDPA } },
 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,	{ BDA } },
-{ "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPC,	{ BDMA } },
-{ "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPC,	{ BDPA } },
+{ "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,	{ BDMA } },
+{ "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,	{ BDPA } },
 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,	{ BDA } },
-{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
-{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
-{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
-{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
-{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,	{ CR, BD } },
-{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,	{ CR, BDA } },
-{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
-{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },
-{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },
-{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
-{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
-{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDMA } },
-{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,	{ CR, BDPA } },
-{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
-{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,	{ BI, BDM } },
-{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,	{ BI, BDP } },
+{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BD } },
+{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BD } },
+{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDA } },
+{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDA } },
+{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,		{ CR, BD } },
+{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,		{ CR, BDA } },
+{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,	{ CR, BD } },
+{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDM } },
+{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BDP } },
+{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,	{ CR, BD } },
+{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,	{ CR, BDA } },
+{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDMA } },
+{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDPA } },
+{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,	{ CR, BDA } },
+{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,	{ BI, BDM } },
-{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,	{ BI, BDP } },
+{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,	{ BI, BDMA } },
-{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,	{ BI, BDPA } },
+{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,	{ BI, BDMA } },
-{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,	{ BI, BDPA } },
+{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,	{ BI, BDM } },
-{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,	{ BI, BDP } },
+{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,	{ BI, BDM } },
-{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,	{ BI, BDP } },
+{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,	{ BI, BDMA } },
-{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,	{ BI, BDPA } },
+{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,	{ BI, BDMA } },
-{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,	{ BI, BDPA } },
+{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bt",	     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,	{ BI, BD } },
-{ "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,	{ BI, BD } },
-{ "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,	{ BI, BDA } },
-{ "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,	{ BI, BDA } },
-{ "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bf",	     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,	{ BI, BD } },
-{ "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,	{ BI, BD } },
-{ "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,	{ BI, BDA } },
-{ "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,	{ BI, BDA } },
-{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,		{ BI, BDM } },
-{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,		{ BI, BDP } },
+{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDM } },
+{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BDP } },
 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
-{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC,		{ BI, BDMA } },
-{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC,		{ BI, BDPA } },
+{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDMA } },
+{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDPA } },
 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
-{ "bc-",     B(16,0,0),	B_MASK,		PPC,		{ BOE, BI, BDM } },
-{ "bc+",     B(16,0,0),	B_MASK,		PPC,		{ BOE, BI, BDP } },
+{ "bc-",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
+{ "bc+",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
 { "bc",	     B(16,0,0),	B_MASK,		COM,		{ BO, BI, BD } },
-{ "bcl-",    B(16,0,1),	B_MASK,		PPC,		{ BOE, BI, BDM } },
-{ "bcl+",    B(16,0,1),	B_MASK,		PPC,		{ BOE, BI, BDP } },
+{ "bcl-",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
+{ "bcl+",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
 { "bcl",     B(16,0,1),	B_MASK,		COM,		{ BO, BI, BD } },
-{ "bca-",    B(16,1,0),	B_MASK,		PPC,		{ BOE, BI, BDMA } },
-{ "bca+",    B(16,1,0),	B_MASK,		PPC,		{ BOE, BI, BDPA } },
+{ "bca-",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
+{ "bca+",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
 { "bca",     B(16,1,0),	B_MASK,		COM,		{ BO, BI, BDA } },
-{ "bcla-",   B(16,1,1),	B_MASK,		PPC,		{ BOE, BI, BDMA } },
-{ "bcla+",   B(16,1,1),	B_MASK,		PPC,		{ BOE, BI, BDPA } },
+{ "bcla-",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
+{ "bcla+",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
 { "bcla",    B(16,1,1),	B_MASK,		COM,		{ BO, BI, BDA } },
 
 { "sc",      SC(17,1,0), 0xffffffff,	PPC,		{ 0 } },
@@ -1671,163 +1971,165 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,	{ 0 } },
 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
-{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,	{ 0 } },
-{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC,	{ 0 } },
+{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
+{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
-{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,	{ 0 } },
-{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC,	{ 0 } },
+{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
+{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
-{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,	{ 0 } },
-{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC,	{ 0 } },
+{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
+{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
-{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,	{ 0 } },
-{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC,	{ 0 } },
+{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
+{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
-{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
+{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,	{ BI } },
-{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bclr",    XLLK(19,16,0), XLYBB_MASK,	PPCCOM,		{ BO, BI } },
 { "bclrl",   XLLK(19,16,1), XLYBB_MASK,	PPCCOM,		{ BO, BI } },
-{ "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPC,		{ BOE, BI } },
-{ "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPC,		{ BOE, BI } },
-{ "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPC,		{ BOE, BI } },
-{ "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPC,		{ BOE, BI } },
+{ "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
+{ "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
+{ "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
+{ "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
 { "bcr",     XLLK(19,16,0), XLBB_MASK,	PWRCOM,		{ BO, BI } },
 { "bcrl",    XLLK(19,16,1), XLBB_MASK,	PWRCOM,		{ BO, BI } },
 
+{ "rfid",    XL(19,18),	0xffffffff,	PPC64,		{ 0 } },
+
 { "crnot",   XL(19,33), XL_MASK,	PPCCOM,		{ BT, BA, BBA } },
 { "crnor",   XL(19,33),	XL_MASK,	COM,		{ BT, BA, BB } },
 
 { "rfi",     XL(19,50),	0xffffffff,	COM,		{ 0 } },
-{ "rfci",    XL(19,51),	0xffffffff,	PPC,		{ 0 } },
+{ "rfci",    XL(19,51),	0xffffffff,	PPC403,		{ 0 } },
 
 { "rfsvc",   XL(19,82),	0xffffffff,	POWER,		{ 0 } },
 
@@ -1854,95 +2156,95 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,	{ 0 } },
 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,	{ 0 } },
 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
-{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPC,	{ CR } },
-{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC,	{ CR } },
+{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
+{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,	{ CR } },
 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPC,	{ BI } },
-{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPC,	{ BI } },
-{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPC,	{ BI } },
-{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPC,	{ BI } },
+{ "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
-{ "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPC,	{ BI } },
-{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC,	{ BI } },
+{ "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
+{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM,	{ BI } },
 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,	{ BO, BI } },
-{ "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPC,	{ BOE, BI } },
-{ "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPC,	{ BOE, BI } },
+{ "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
+{ "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,	{ BO, BI } },
-{ "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPC,	{ BOE, BI } },
-{ "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPC,	{ BOE, BI } },
+{ "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
+{ "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
 
@@ -2156,6 +2458,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulhw",   XO(31,75,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
 { "mulhw.",  XO(31,75,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
 
+{ "mtsrd",   X(31,82),	XRB_MASK|(1<<20), PPC64,	{ SR, RS } },
+
 { "mfmsr",   X(31,83),	XRARB_MASK,	COM,		{ RT } },
 
 { "ldarx",   X(31,84),	X_MASK,		PPC64,		{ RT, RA, RB } },
@@ -2174,6 +2478,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulo",    XO(31,107,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
 { "mulo.",   XO(31,107,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
 
+{ "mtsrdin", X(31,114),	XRA_MASK,	PPC64,		{ RS, RB } },
+
 { "clf",     X(31,118), XRB_MASK,	POWER,		{ RT, RA } },
 
 { "lbzux",   X(31,119),	X_MASK,		COM,		{ RT, RAL, RB } },
@@ -2223,6 +2529,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "wrteei",  X(31,163),	XE_MASK,	PPC403,		{ E } },
 
+{ "mtmsrd",  X(31,178),	XRARB_MASK,	PPC64,		{ RS } },
+
 { "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
 
 { "stwux",   X(31,183),	X_MASK,		PPCCOM,		{ RS, RAS, RB } },
@@ -2324,7 +2632,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA, RB } },
 
-{ "icbt",    X(31,262),	XRT_MASK,	PPC,		{ RA, RB } },
+{ "icbt",    X(31,262),	XRT_MASK,	PPC403,		{ RA, RB } },
 
 { "eqv",     XRC(31,284,0), X_MASK,	COM,		{ RA, RS, RB } },
 { "eqv.",    XRC(31,284,1), X_MASK,	COM,		{ RA, RS, RB } },
@@ -2373,7 +2681,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,	{ RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,	{ RT } },
 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,	{ RT } },
-{ "mfdcr",   X(31,323),	X_MASK,		PPC,		{ RT, SPR } },
+{ "mfdcr",   X(31,323),	X_MASK,		PPC403,		{ RT, SPR } },
 
 { "div",     XO(31,331,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
@@ -2411,6 +2719,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,	{ RT } },
 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,	{ RT } },
 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,	{ RT } },
+{ "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,	{ RT } },
+{ "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,	{ RT } },
 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,	{ RT, SPRG } },
 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,		{ RT } },
 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,		{ RT } },
@@ -2451,9 +2763,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,	{ RT } },
 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,	{ RT } },
 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,	{ RT } },
-{ "mfzpr",   XSPR(31,339,944), XSPR_MASK, PPC403,	{ RT } },
-{ "mfpid",   XSPR(31,339,945), XSPR_MASK, PPC403,	{ RT } },
-{ "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403,	{ RT } },
+{ "mfzpr",   	XSPR(31,339,944), XSPR_MASK, PPC403,	{ RT } },
+{ "mfpid",   	XSPR(31,339,945), XSPR_MASK, PPC403,	{ RT } },
+{ "mfccr0",  	XSPR(31,339,947), XSPR_MASK, PPC405,	{ RT } },
+{ "mficdbdr",	XSPR(31,339,979), XSPR_MASK, PPC403,	{ RT } },
 { "mfummcr0",	XSPR(31,339,936),  XSPR_MASK, PPC750,	{ RT } },
 { "mfupmc1",	XSPR(31,339,937),  XSPR_MASK, PPC750,	{ RT } },
 { "mfupmc2",	XSPR(31,339,938),  XSPR_MASK, PPC750,	{ RT } },
@@ -2461,12 +2774,21 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfummcr1",	XSPR(31,339,940),  XSPR_MASK, PPC750,	{ RT } },
 { "mfupmc3",	XSPR(31,339,941),  XSPR_MASK, PPC750,	{ RT } },
 { "mfupmc4",	XSPR(31,339,942),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,	{ RT } },
+{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,	{ RT } },
 { "mfmmcr0",	XSPR(31,339,952),  XSPR_MASK, PPC750,	{ RT } },
 { "mfpmc1",	XSPR(31,339,953),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfsgr",	XSPR(31,339,953),  XSPR_MASK, PPC403,	{ RT } },
 { "mfpmc2",	XSPR(31,339,954),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfdcwr", 	XSPR(31,339,954),  XSPR_MASK, PPC403,	{ RT } },
 { "mfsia",	XSPR(31,339,955),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfsler",	XSPR(31,339,955),  XSPR_MASK, PPC405,	{ RT } },
 { "mfmmcr1",	XSPR(31,339,956),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfsu0r",	XSPR(31,339,956),  XSPR_MASK, PPC405,	{ RT } },
 { "mfpmc3",	XSPR(31,339,957),  XSPR_MASK, PPC750,	{ RT } },
+{ "mfdbcr1", 	XSPR(31,339,957),  XSPR_MASK, PPC405,	{ RT } },
 { "mfpmc4",	XSPR(31,339,958),  XSPR_MASK, PPC750,	{ RT } },
 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,	{ RT } },
 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,	{ RT } },
@@ -2480,6 +2802,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,	{ RT } },
 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,	{ RT } },
 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,	{ RT } },
+{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,	{ RT } },
 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,	{ RT } },
 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,	{ RT } },
 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,	{ RT } },
@@ -2501,7 +2824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA, RB } },
 
-{ "dccci",   X(31,454),	XRT_MASK,	PPC,		{ RA, RB } },
+{ "dccci",   X(31,454),	XRT_MASK,	PPC403,		{ RA, RB } },
 
 { "abs",     XO(31,360,0,0), XORB_MASK, M601,		{ RT, RA } },
 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,		{ RT, RA } },
@@ -2515,6 +2838,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbia",   X(31,370),	0xffffffff,	PPC,		{ 0 } },
 
+{ "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,		{ RT } },
 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,		{ RT } },
 { "mftb",    X(31,371),	X_MASK,		PPC,		{ RT, TBR } },
 
@@ -2583,26 +2907,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,	{ RT } },
 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,	{ RT } },
 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,	{ RT } },
-{ "mtummcr0",	XSPR(31,451,936),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtupmc1",	XSPR(31,451,937),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtupmc2",	XSPR(31,451,938),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtusia",	XSPR(31,451,939),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtummcr1",	XSPR(31,451,940),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtupmc3",	XSPR(31,451,941),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtupmc4",	XSPR(31,451,942),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtmmcr0",	XSPR(31,451,952),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtpmc1",	XSPR(31,451,953),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtpmc2",	XSPR(31,451,954),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtsia",	XSPR(31,451,955),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtmmcr1",	XSPR(31,451,956),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtpmc3",	XSPR(31,451,957),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtpmc4",	XSPR(31,451,958),  XSPR_MASK, PPC750,	{ RT } },
-{ "mtl2cr",	XSPR(31,451,1017), XSPR_MASK, PPC750,	{ RT } },
-{ "mtictc",	XSPR(31,451,1019), XSPR_MASK, PPC750,	{ RT } },
-{ "mtthrm1",	XSPR(31,451,1020), XSPR_MASK, PPC750,	{ RT } },
-{ "mtthrm2",	XSPR(31,451,1021), XSPR_MASK, PPC750,	{ RT } },
-{ "mtthrm3",	XSPR(31,451,1022), XSPR_MASK, PPC750,	{ RT } },
-{ "mtdcr",   X(31,451),	X_MASK,		PPC,		{ SPR, RS } },
+{ "mtdcr",   X(31,451),	X_MASK,		PPC403,		{ SPR, RS } },
 
 { "divdu",   XO(31,457,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
 { "divdu.",  XO(31,457,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
@@ -2649,6 +2954,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,	{ RT } },
 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,	{ RT } },
 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,	{ RT } },
+{ "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,	{ RT } },
+{ "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,	{ RT } },
+{ "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,	{ RT } },
+{ "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,	{ RT } },
 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,	{ RS } },
 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,	{ RS } },
 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,	{ RS } },
@@ -2659,8 +2968,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,	{ RT } },
 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,	{ RT } },
+{ "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,	{ RT } },
+{ "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,	{ RT } },
+{ "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,	{ RT } },
+{ "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,	{ RT } },
+{ "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,	{ RT } },
+{ "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,	{ RT } },
+{ "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,	{ RT } },
+{ "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,	{ RT } },
+{ "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,	{ RT } },
+{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,	{ RT } },
 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,	{ RT } },
 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,	{ RT } },
+{ "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,	{ RT } },
 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,	{ RT } },
 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,	{ RT } },
 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,	{ RT } },
@@ -2671,6 +2991,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,	{ RT } },
 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,	{ RT } },
 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,	{ RT } },
+{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,	{ RT } },
 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,	{ RT } },
 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,	{ RT } },
 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,	{ RT } },
@@ -2681,6 +3002,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,	{ RT } },
 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,	{ RT } },
 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,	{ RT } },
+{ "mtummcr0",	XSPR(31,467,936),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtupmc1",	XSPR(31,467,937),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtupmc2",	XSPR(31,467,938),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtusia",	XSPR(31,467,939),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtummcr1",	XSPR(31,467,940),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtupmc3",	XSPR(31,467,941),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtupmc4",	XSPR(31,467,942),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtmmcr0",	XSPR(31,467,952),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtpmc1",	XSPR(31,467,953),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtpmc2",	XSPR(31,467,954),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtsia",	XSPR(31,467,955),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtmmcr1",	XSPR(31,467,956),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtpmc3",	XSPR(31,467,957),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtpmc4",	XSPR(31,467,958),  XSPR_MASK, PPC750,	{ RT } },
+{ "mtl2cr",	XSPR(31,467,1017), XSPR_MASK, PPC750,	{ RT } },
+{ "mtictc",	XSPR(31,467,1019), XSPR_MASK, PPC750,	{ RT } },
+{ "mtthrm1",	XSPR(31,467,1020), XSPR_MASK, PPC750,	{ RT } },
+{ "mtthrm2",	XSPR(31,467,1021), XSPR_MASK, PPC750,	{ RT } },
+{ "mtthrm3",	XSPR(31,467,1022), XSPR_MASK, PPC750,	{ RT } },
 { "mtspr",   X(31,467),	       X_MASK,	     COM,	{ SPR, RS } },
 
 { "dcbi",    X(31,470),	XRT_MASK,	PPC,		{ RA, RB } },
@@ -2787,6 +3127,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sreq",    XRC(31,729,0), X_MASK,	M601,		{ RA, RS, RB } },
 { "sreq.",   XRC(31,729,1), X_MASK,	M601,		{ RA, RS, RB } },
 
+{ "dcba",    X(31,758),	XRT_MASK,	PPC405,		{ RA, RB } },
+
 { "stfdux",  X(31,759),	X_MASK,		COM,		{ FRS, RAS, RB } },
 
 { "srliq",   XRC(31,760,0), X_MASK,	M601,		{ RA, RS, SH } },
@@ -2827,6 +3169,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsh.",  XRC(31,922,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
 { "exts.",   XRC(31,922,1), XRB_MASK,	PWRCOM,		{ RA, RS } },
 
+{ "tlbrehi", XTLB(31,946,0), XTLB_MASK,	PPC403,		{ RT, RA } },
+{ "tlbrelo", XTLB(31,946,1), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbre",   X(31,946),	X_MASK,		PPC403,		{ RT, RA, SH } },
 
 { "sraiq",   XRC(31,952,0), X_MASK,	M601,		{ RA, RS, SH } },
@@ -2835,9 +3179,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsb",   XRC(31,954,0), XRB_MASK,	PPC,		{ RA, RS} },
 { "extsb.",  XRC(31,954,1), XRB_MASK,	PPC,		{ RA, RS} },
 
-{ "iccci",   X(31,966),	XRT_MASK,	PPC,		{ RA, RB } },
+{ "iccci",   X(31,966),	XRT_MASK,	PPC403,		{ RA, RB } },
 
 { "tlbld",   X(31,978),	XRTRA_MASK,	PPC,		{ RB } },
+
+{ "tlbwehi", XTLB(31,978,0), XTLB_MASK,	PPC403,		{ RT, RA } },
+{ "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwe",   X(31,978),	X_MASK,		PPC403,		{ RS, RA, SH } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },
@@ -2854,6 +3201,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "dcbz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
 { "dclz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
 
+{ "lvebx",   X(31,   7), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvehx",   X(31,  39), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvewx",   X(31,  71), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvsl",    X(31,   6), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvsr",    X(31,  38), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvx",     X(31, 103), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "lvxl",    X(31, 359), X_MASK,	PPCVEC,		{ VD, RA, RB } },
+{ "stvebx",  X(31, 135), X_MASK,	PPCVEC,		{ VS, RA, RB } },
+{ "stvehx",  X(31, 167), X_MASK,	PPCVEC,		{ VS, RA, RB } },
+{ "stvewx",  X(31, 199), X_MASK,	PPCVEC,		{ VS, RA, RB } },
+{ "stvx",    X(31, 231), X_MASK,	PPCVEC,		{ VS, RA, RB } },
+{ "stvxl",   X(31, 487), X_MASK,	PPCVEC,		{ VS, RA, RB } },
+
 { "lwz",     OP(32),	OP_MASK,	PPCCOM,		{ RT, D, RA } },
 { "l",	     OP(32),	OP_MASK,	PWRCOM,		{ RT, D, RA } },
 
diff --git a/gnu/usr.bin/binutils/opcodes/sh-dis.c b/gnu/usr.bin/binutils/opcodes/sh-dis.c
index c4e960c24e8..80ccfdc000d 100644
--- a/gnu/usr.bin/binutils/opcodes/sh-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/sh-dis.c
@@ -1,5 +1,6 @@
 /* Disassemble SH instructions.
-   Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1997, 1998, 2000
+   Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -15,8 +16,8 @@ You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-#include "sysdep.h"
 #include <stdio.h>
+#include "sysdep.h"
 #define STATIC_TABLE
 #define DEFINE_TABLE
 
@@ -34,22 +35,22 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
 {
   int n;
 
-  fprintf_fn (stream,"%s\t", op->name);
+  fprintf_fn (stream, "%s\t", op->name);
   for (n = 0; n < 2; n++)
     {
       switch (op->arg[n])
 	{
 	case A_IND_N:
-	  fprintf_fn (stream, "@r%d", rn);	
+	  fprintf_fn (stream, "@r%d", rn);
 	  break;
 	case A_INC_N:
-	  fprintf_fn (stream, "@r%d+", rn);	
+	  fprintf_fn (stream, "@r%d+", rn);
 	  break;
 	case A_PMOD_N:
-	  fprintf_fn (stream, "@r%d+r8", rn);	
+	  fprintf_fn (stream, "@r%d+r8", rn);
 	  break;
 	case A_PMODY_N:
-	  fprintf_fn (stream, "@r%d+r9", rn);	
+	  fprintf_fn (stream, "@r%d+r9", rn);
 	  break;
 	case DSP_REG_M:
 	  fprintf_fn (stream, "a%c", '0' + rm);
@@ -64,7 +65,7 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
 	  abort ();
 	}
       if (n == 0)
-	fprintf_fn (stream, ",");	
+	fprintf_fn (stream, ",");
     }
 }
 
@@ -72,6 +73,7 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
    nibbles of the insn, i.e. field a and the bit that indicates if
    a parallel processing insn follows.
    Return nonzero if a field b of a parallel processing insns follows.  */
+
 static void
 print_insn_ddt (insn, info)
      int insn;
@@ -97,19 +99,20 @@ print_insn_ddt (insn, info)
     {
       static sh_opcode_info *first_movx, *first_movy;
       sh_opcode_info *opx, *opy;
-      int insn_x, insn_y;
+      unsigned int insn_x, insn_y;
 
       if (! first_movx)
 	{
-	  for (first_movx = sh_table; first_movx->nibbles[1] != MOVX; )
+	  for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
 	    first_movx++;
-	  for (first_movy = first_movx; first_movy->nibbles[1] != MOVY; )
+	  for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
 	    first_movy++;
 	}
       insn_x = (insn >> 2) & 0xb;
       if (insn_x)
 	{
-	  for (opx = first_movx; opx->nibbles[2] != insn_x; ) opx++;
+	  for (opx = first_movx; opx->nibbles[2] != insn_x;)
+	    opx++;
 	  print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
 		       fprintf_fn, stream);
 	}
@@ -118,7 +121,8 @@ print_insn_ddt (insn, info)
 	{
 	  if (insn_x)
 	    fprintf_fn (stream, "\t");
-	  for (opy = first_movy; opy->nibbles[2] != insn_y; ) opy++;
+	  for (opy = first_movy; opy->nibbles[2] != insn_y;)
+	    opy++;
 	  print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
 		       fprintf_fn, stream);
 	}
@@ -174,12 +178,12 @@ print_insn_ppi (field_b, info)
      int field_b;
      struct disassemble_info *info;
 {
-  static char *sx_tab[] = {"x0","x1","a0","a1"};
-  static char *sy_tab[] = {"y0","y1","m0","m1"};
+  static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
+  static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
   fprintf_ftype fprintf_fn = info->fprintf_func;
   void *stream = info->stream;
-  int nib1, nib2, nib3;
-  char *dc;
+  unsigned int nib1, nib2, nib3;
+  char *dc = NULL;
   sh_opcode_info *op;
 
   if ((field_b & 0xe800) == 0)
@@ -192,10 +196,10 @@ print_insn_ppi (field_b, info)
     }
   if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
     {
-      static char *du_tab[] = {"x0","y0","a0","a1"};
-      static char *se_tab[] = {"x0","x1","y0","a1"};
-      static char *sf_tab[] = {"y0","y1","x0","a1"};
-      static char *sg_tab[] = {"m0","m1","a0","a1"};
+      static char *du_tab[] = { "x0", "y0", "a0", "a1" };
+      static char *se_tab[] = { "x0", "x1", "y0", "a1" };
+      static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
+      static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
 
       if (field_b & 0x2000)
 	{
@@ -243,11 +247,11 @@ print_insn_ppi (field_b, info)
 	  int n;
 
 	  fprintf_fn (stream, "%s%s\t", dc, op->name);
-	  for (n = 0; n < 3 && op->arg[n] != A_END; n++) 
+	  for (n = 0; n < 3 && op->arg[n] != A_END; n++)
 	    {
 	      if (n && op->arg[1] != A_END)
 		fprintf_fn (stream, ",");
-	      switch (op->arg[n]) 
+	      switch (op->arg[n])
 		{
 		case DSP_REG_N:
 		  print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
@@ -262,7 +266,7 @@ print_insn_ppi (field_b, info)
 		  fprintf_fn (stream, "mach");
 		  break;
 		case A_MACL:
-		  fprintf_fn (stream ,"macl");
+		  fprintf_fn (stream, "macl");
 		  break;
 		default:
 		  abort ();
@@ -275,7 +279,7 @@ print_insn_ppi (field_b, info)
   fprintf_fn (stream, ".word 0x%x", field_b);
 }
 
-static int 
+static int
 print_insn_shx (memaddr, info)
      bfd_vma memaddr;
      struct disassemble_info *info;
@@ -285,7 +289,7 @@ print_insn_shx (memaddr, info)
   unsigned char insn[2];
   unsigned char nibs[4];
   int status;
-  bfd_vma relmask = ~ (bfd_vma) 0;
+  bfd_vma relmask = ~(bfd_vma) 0;
   sh_opcode_info *op;
   int target_arch;
 
@@ -318,13 +322,13 @@ print_insn_shx (memaddr, info)
 
   status = info->read_memory_func (memaddr, insn, 2, info);
 
-  if (status != 0) 
+  if (status != 0)
     {
       info->memory_error_func (status, memaddr, info);
       return -1;
     }
 
-  if (info->flags & LITTLE_BIT) 
+  if (info->flags & LITTLE_BIT)
     {
       nibs[0] = (insn[1] >> 4) & 0xf;
       nibs[1] = insn[1] & 0xf;
@@ -332,7 +336,7 @@ print_insn_shx (memaddr, info)
       nibs[2] = (insn[0] >> 4) & 0xf;
       nibs[3] = insn[0] & 0xf;
     }
-  else 
+  else
     {
       nibs[0] = (insn[0] >> 4) & 0xf;
       nibs[1] = insn[0] & 0xf;
@@ -349,13 +353,13 @@ print_insn_shx (memaddr, info)
 
 	  status = info->read_memory_func (memaddr + 2, insn, 2, info);
 
-	  if (status != 0) 
+	  if (status != 0)
 	    {
 	      info->memory_error_func (status, memaddr + 2, info);
 	      return -1;
 	    }
 
-	  if (info->flags & LITTLE_BIT) 
+	  if (info->flags & LITTLE_BIT)
 	    field_b = insn[1] << 8 | insn[0];
 	  else
 	    field_b = insn[0] << 8 | insn[1];
@@ -367,7 +371,7 @@ print_insn_shx (memaddr, info)
       print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
       return 2;
     }
-  for (op = sh_table; op->name; op++) 
+  for (op = sh_table; op->name; op++)
     {
       int n;
       int imm = 0;
@@ -383,7 +387,7 @@ print_insn_shx (memaddr, info)
 	{
 	  int i = op->nibbles[n];
 
-	  if (i < 16) 
+	  if (i < 16)
 	    {
 	      if (nibs[n] == i)
 		continue;
@@ -392,10 +396,10 @@ print_insn_shx (memaddr, info)
 	  switch (i)
 	    {
 	    case BRANCH_8:
-	      imm = (nibs[2] << 4) | (nibs[3]);	  
+	      imm = (nibs[2] << 4) | (nibs[3]);
 	      if (imm & 0x80)
 		imm |= ~0xff;
-	      imm = ((char)imm) * 2 + 4 ;
+	      imm = ((char) imm) * 2 + 4;
 	      goto ok;
 	    case BRANCH_12:
 	      imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
@@ -403,37 +407,37 @@ print_insn_shx (memaddr, info)
 		imm |= ~0xfff;
 	      imm = imm * 2 + 4;
 	      goto ok;
-	    case IMM_4:
+	    case IMM0_4:
+	    case IMM1_4:
 	      imm = nibs[3];
 	      goto ok;
-	    case IMM_4BY2:
-	      imm = nibs[3] <<1;
+	    case IMM0_4BY2:
+	    case IMM1_4BY2:
+	      imm = nibs[3] << 1;
 	      goto ok;
-	    case IMM_4BY4:
-	      imm = nibs[3] <<2;
+	    case IMM0_4BY4:
+	    case IMM1_4BY4:
+	      imm = nibs[3] << 2;
 	      goto ok;
-	    case IMM_8:
+	    case IMM0_8:
+	    case IMM1_8:
 	      imm = (nibs[2] << 4) | nibs[3];
 	      goto ok;
 	    case PCRELIMM_8BY2:
-	      imm = ((nibs[2] << 4) | nibs[3]) <<1;
-	      relmask = ~ (bfd_vma) 1;
+	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
+	      relmask = ~(bfd_vma) 1;
 	      goto ok;
 	    case PCRELIMM_8BY4:
-	      imm = ((nibs[2] << 4) | nibs[3]) <<2;
-	      relmask = ~ (bfd_vma) 3;
-	      goto ok;
-	    case IMM_8BY2:
-	      imm = ((nibs[2] << 4) | nibs[3]) <<1;
+	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
+	      relmask = ~(bfd_vma) 3;
 	      goto ok;
-	    case IMM_8BY4:
-	      imm = ((nibs[2] << 4) | nibs[3]) <<2;
+	    case IMM0_8BY2:
+	    case IMM1_8BY2:
+	      imm = ((nibs[2] << 4) | nibs[3]) << 1;
 	      goto ok;
-	    case DISP_8:
-	      imm = (nibs[2] << 4) | (nibs[3]);	  
-	      goto ok;
-	    case DISP_4:
-	      imm = nibs[3];
+	    case IMM0_8BY4:
+	    case IMM1_8BY4:
+	      imm = ((nibs[2] << 4) | nibs[3]) << 2;
 	      goto ok;
 	    case REG_N:
 	      rn = nibs[n];
@@ -447,7 +451,7 @@ print_insn_shx (memaddr, info)
 	      break;
 	    case REG_B:
 	      rb = nibs[n] & 0x07;
-	      break;	
+	      break;
 	    case SDT_REG_N:
 	      /* sh-dsp: single data transfer.  */
 	      rn = nibs[n];
@@ -457,23 +461,24 @@ print_insn_shx (memaddr, info)
 	      rn |= (rn & 2) << 1;
 	      break;
 	    case PPI:
+	    case REPEAT:
 	      goto fail;
 	    default:
-	      abort();
+	      abort ();
 	    }
 	}
 
     ok:
-      fprintf_fn (stream,"%s\t", op->name);
+      fprintf_fn (stream, "%s\t", op->name);
       disp_pc = 0;
-      for (n = 0; n < 3 && op->arg[n] != A_END; n++) 
+      for (n = 0; n < 3 && op->arg[n] != A_END; n++)
 	{
 	  if (n && op->arg[1] != A_END)
 	    fprintf_fn (stream, ",");
-	  switch (op->arg[n]) 
+	  switch (op->arg[n])
 	    {
 	    case A_IMM:
-	      fprintf_fn (stream, "#%d", (char)(imm));
+	      fprintf_fn (stream, "#%d", (char) (imm));
 	      break;
 	    case A_R0:
 	      fprintf_fn (stream, "r0");
@@ -482,34 +487,34 @@ print_insn_shx (memaddr, info)
 	      fprintf_fn (stream, "r%d", rn);
 	      break;
 	    case A_INC_N:
-	      fprintf_fn (stream, "@r%d+", rn);	
+	      fprintf_fn (stream, "@r%d+", rn);
 	      break;
 	    case A_DEC_N:
-	      fprintf_fn (stream, "@-r%d", rn);	
+	      fprintf_fn (stream, "@-r%d", rn);
 	      break;
 	    case A_IND_N:
-	      fprintf_fn (stream, "@r%d", rn);	
+	      fprintf_fn (stream, "@r%d", rn);
 	      break;
 	    case A_DISP_REG_N:
-	      fprintf_fn (stream, "@(%d,r%d)", imm, rn);	
+	      fprintf_fn (stream, "@(%d,r%d)", imm, rn);
 	      break;
 	    case A_PMOD_N:
-	      fprintf_fn (stream, "@r%d+r8", rn);	
+	      fprintf_fn (stream, "@r%d+r8", rn);
 	      break;
 	    case A_REG_M:
 	      fprintf_fn (stream, "r%d", rm);
 	      break;
 	    case A_INC_M:
-	      fprintf_fn (stream, "@r%d+", rm);	
+	      fprintf_fn (stream, "@r%d+", rm);
 	      break;
 	    case A_DEC_M:
-	      fprintf_fn (stream, "@-r%d", rm);	
+	      fprintf_fn (stream, "@-r%d", rm);
 	      break;
 	    case A_IND_M:
-	      fprintf_fn (stream, "@r%d", rm);	
+	      fprintf_fn (stream, "@r%d", rm);
 	      break;
 	    case A_DISP_REG_M:
-	      fprintf_fn (stream, "@(%d,r%d)", imm, rm);	
+	      fprintf_fn (stream, "@(%d,r%d)", imm, rm);
 	      break;
 	    case A_REG_B:
 	      fprintf_fn (stream, "r%d_bank", rb);
@@ -521,12 +526,12 @@ print_insn_shx (memaddr, info)
 	      break;
 	    case A_IND_R0_REG_N:
 	      fprintf_fn (stream, "@(r0,r%d)", rn);
-	      break; 
+	      break;
 	    case A_IND_R0_REG_M:
 	      fprintf_fn (stream, "@(r0,r%d)", rm);
-	      break; 
+	      break;
 	    case A_DISP_GBR:
-	      fprintf_fn (stream, "@(%d,gbr)",imm);
+	      fprintf_fn (stream, "@(%d,gbr)", imm);
 	      break;
 	    case A_R0_GBR:
 	      fprintf_fn (stream, "@(r0,gbr)");
@@ -584,7 +589,7 @@ print_insn_shx (memaddr, info)
 	      fprintf_fn (stream, "mach");
 	      break;
 	    case A_MACL:
-	      fprintf_fn (stream ,"macl");
+	      fprintf_fn (stream, "macl");
 	      break;
 	    case A_PR:
 	      fprintf_fn (stream, "pr");
@@ -607,7 +612,6 @@ print_insn_shx (memaddr, info)
 		  fprintf_fn (stream, "xd%d", rn & ~1);
 		  break;
 		}
-	    d_reg_n:
 	    case D_REG_N:
 	      fprintf_fn (stream, "dr%d", rn);
 	      break;
@@ -632,16 +636,16 @@ print_insn_shx (memaddr, info)
 	      fprintf_fn (stream, "fr0");
 	      break;
 	    case V_REG_N:
-	      fprintf_fn (stream, "fv%d", rn*4);
+	      fprintf_fn (stream, "fv%d", rn * 4);
 	      break;
 	    case V_REG_M:
-	      fprintf_fn (stream, "fv%d", rm*4);
+	      fprintf_fn (stream, "fv%d", rm * 4);
 	      break;
 	    case XMTRX_M4:
 	      fprintf_fn (stream, "xmtrx");
 	      break;
 	    default:
-	      abort();
+	      abort ();
 	    }
 	}
 
@@ -654,7 +658,7 @@ print_insn_shx (memaddr, info)
       if (!(info->flags & 1)
 	  && (op->name[0] == 'j'
 	      || (op->name[0] == 'b'
-		  && (op->name[1] == 'r' 
+		  && (op->name[1] == 'r'
 		      || op->name[1] == 's'))
 	      || (op->name[0] == 'r' && op->name[1] == 't')
 	      || (op->name[0] == 'b' && op->name[2] == '.')))
@@ -673,7 +677,7 @@ print_insn_shx (memaddr, info)
 	  int size;
 	  bfd_byte bytes[4];
 
-	  if (relmask == ~ (bfd_vma) 1)
+	  if (relmask == ~(bfd_vma) 1)
 	    size = 2;
 	  else
 	    size = 4;
@@ -709,7 +713,7 @@ print_insn_shx (memaddr, info)
   return 2;
 }
 
-int 
+int
 print_insn_shl (memaddr, info)
      bfd_vma memaddr;
      struct disassemble_info *info;
@@ -721,7 +725,7 @@ print_insn_shl (memaddr, info)
   return r;
 }
 
-int 
+int
 print_insn_sh (memaddr, info)
      bfd_vma memaddr;
      struct disassemble_info *info;
diff --git a/gnu/usr.bin/binutils/opcodes/sh-opc.h b/gnu/usr.bin/binutils/opcodes/sh-opc.h
index 38bfbcde4b6..a2822f51fdc 100644
--- a/gnu/usr.bin/binutils/opcodes/sh-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/sh-opc.h
@@ -1,5 +1,6 @@
 /* Definitions for SH opcodes.
-   Copyright (C) 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1997, 1999, 2000
+   Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -39,16 +40,20 @@ typedef enum {
         REG_B,
 	BRANCH_12,
 	BRANCH_8,
-	DISP_8,
-	DISP_4,
-	IMM_4,
-	IMM_4BY2,
-	IMM_4BY4,
+	IMM0_4,
+	IMM0_4BY2,
+	IMM0_4BY4,
+	IMM1_4,
+	IMM1_4BY2,
+	IMM1_4BY4,
 	PCRELIMM_8BY2,
 	PCRELIMM_8BY4,
-	IMM_8,
-	IMM_8BY2,
-	IMM_8BY4,
+	IMM0_8,
+	IMM0_8BY2,
+	IMM0_8BY4,
+	IMM1_8,
+	IMM1_8BY2,
+	IMM1_8BY4,
 	PPI,
 	NOPX,
 	NOPY,
@@ -58,7 +63,8 @@ typedef enum {
 	PMUL,
 	PPI3,
 	PDC,
-	PPIC
+	PPIC,
+	REPEAT
 } sh_nibble_type;
 
 typedef enum {
@@ -68,6 +74,7 @@ typedef enum {
 	A_DEC_M,
 	A_DEC_N,
 	A_DISP_GBR,
+	A_PC,
 	A_DISP_PC,
 	A_DISP_REG_M,
 	A_DISP_REG_N,
@@ -164,7 +171,7 @@ typedef struct {
 
 sh_opcode_info sh_table[] = {
 
-/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}, arch_sh1_up},
+/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
 
 /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
 
@@ -172,11 +179,11 @@ sh_opcode_info sh_table[] = {
 
 /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
 
-/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}, arch_sh1_up},
+/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
 
 /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
 
-/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}, arch_sh1_up},
+/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
 
 /* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
 
@@ -200,7 +207,7 @@ sh_opcode_info sh_table[] = {
 
 /* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
 
-/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}, arch_sh1_up},
+/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
 
 /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
 
@@ -276,9 +283,9 @@ sh_opcode_info sh_table[] = {
 
 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
 
-/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_BDISP8},{HEX_8,HEX_E,BRANCH_8}, arch_sh_dsp_up},
+/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
 
-/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_BDISP8},{HEX_8,HEX_C,BRANCH_8}, arch_sh_dsp_up},
+/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
 
 /* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
 
@@ -328,7 +335,7 @@ sh_opcode_info sh_table[] = {
 
 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
 
-/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}, arch_sh1_up},
+/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
 
 /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
 
@@ -338,9 +345,9 @@ sh_opcode_info sh_table[] = {
 
 /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
 
-/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}, arch_sh1_up},
+/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
 
-/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}, arch_sh1_up},
+/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
 
 /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
 
@@ -348,11 +355,11 @@ sh_opcode_info sh_table[] = {
 
 /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
 
-/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}, arch_sh1_up},
+/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
 
-/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}, arch_sh1_up},
+/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
 
-/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}, arch_sh1_up},
+/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
 
 /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
 
@@ -360,9 +367,9 @@ sh_opcode_info sh_table[] = {
 
 /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
 
-/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}, arch_sh1_up},
+/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
 
-/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}, arch_sh1_up},
+/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
 
 /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
 
@@ -372,7 +379,7 @@ sh_opcode_info sh_table[] = {
 
 /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
 
-/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}, arch_sh1_up},
+/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
 
 /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
 
@@ -380,9 +387,9 @@ sh_opcode_info sh_table[] = {
 
 /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
 
-/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}, arch_sh1_up},
+/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
 
-/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}, arch_sh1_up},
+/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
 
 /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
 
@@ -392,9 +399,9 @@ sh_opcode_info sh_table[] = {
 
 /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
 
-/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}, arch_sh1_up},
+/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
 
-/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}, arch_sh1_up},
+/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
 
 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
 /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up},
@@ -424,11 +431,11 @@ sh_opcode_info sh_table[] = {
 /* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up},
 
 
-/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}, arch_sh1_up},
+/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
 
 /* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
 
-/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}, arch_sh1_up},
+/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
 
 /* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up},
 
@@ -449,7 +456,11 @@ sh_opcode_info sh_table[] = {
 
 /* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
 
-/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM_8}, arch_sh_dsp_up},
+/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
+
+/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
+
+/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
 
 /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up},
 
@@ -513,7 +524,7 @@ sh_opcode_info sh_table[] = {
 
 /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up},
 
-/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh4_up},
+/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
 
 /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up},
 
@@ -577,19 +588,19 @@ sh_opcode_info sh_table[] = {
 
 /* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
 
-/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}, arch_sh1_up},
+/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
 
-/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}, arch_sh1_up},
+/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
 
 /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
 
-/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}, arch_sh1_up},
+/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
 
-/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}, arch_sh1_up},
+/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
 
 /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
 
-/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}, arch_sh1_up},
+/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
 
 /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
 
@@ -667,22 +678,22 @@ sh_opcode_info sh_table[] = {
 {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
 /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
 {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up},
-/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
-{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
 /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
 {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up},
+/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
+{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
 /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
 {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up},
 
 {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
 {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
 
-/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
 /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
-/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
+/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
 /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
+/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
 /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
 /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
@@ -695,10 +706,10 @@ sh_opcode_info sh_table[] = {
 {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
 /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
 {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
-/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
-{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
 /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
 {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
+/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
+{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
 /* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
 {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up},
 /* 10001101xxyynnnn pclr <DSP_REG_N> */
@@ -709,10 +720,10 @@ sh_opcode_info sh_table[] = {
 {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up},
 /* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */
 {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
-/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
-{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
 /* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */
 {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
+/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
+{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
 /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
 {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
 /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
diff --git a/gnu/usr.bin/binutils/opcodes/sparc-dis.c b/gnu/usr.bin/binutils/opcodes/sparc-dis.c
index a595d0f3835..359050723d4 100644
--- a/gnu/usr.bin/binutils/opcodes/sparc-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/sparc-dis.c
@@ -1,5 +1,6 @@
 /* Print SPARC instructions.
-   Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -25,7 +26,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /* Bitmask of v9 architectures.  */
 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
-		 | (1 << SPARC_OPCODE_ARCH_V9A))
+		 | (1 << SPARC_OPCODE_ARCH_V9A) \
+		 | (1 << SPARC_OPCODE_ARCH_V9B))
 /* 1 if INSN is for v9 only.  */
 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
 /* 1 if INSN is for v9.  */
@@ -95,7 +97,7 @@ static char *v9_priv_reg_names[] =
 static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
-  "softint", "tick_cmpr"
+  "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
@@ -463,6 +465,10 @@ print_insn_sparc (memaddr, info)
 		    }
 		    break;
 
+		  case '3':
+		    (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
+		    break;
+
 		  case 'K':
 		    {
 		      int mask = X_MEMBAR (insn);
@@ -551,7 +557,7 @@ print_insn_sparc (memaddr, info)
 		    break;
 
 		  case '/':
-		    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23)
+		    if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
 		      (*info->fprintf_func) (stream, "%%reserved");
 		    else
 		      (*info->fprintf_func) (stream, "%%%s",
@@ -559,7 +565,7 @@ print_insn_sparc (memaddr, info)
 		    break;
 
 		  case '_':
-		    if (X_RD (insn) < 16 || X_RD (insn) > 23)
+		    if (X_RD (insn) < 16 || X_RD (insn) > 25)
 		      (*info->fprintf_func) (stream, "%%reserved");
 		    else
 		      (*info->fprintf_func) (stream, "%%%s",
@@ -770,6 +776,9 @@ compute_arch_mask (mach)
     case bfd_mach_sparc_v8plusa :
     case bfd_mach_sparc_v9a :
       return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+    case bfd_mach_sparc_v8plusb :
+    case bfd_mach_sparc_v9b :
+      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
     }
   abort ();
 }
diff --git a/gnu/usr.bin/binutils/opcodes/sparc-opc.c b/gnu/usr.bin/binutils/opcodes/sparc-opc.c
index a7132bb61f7..5c06d01df14 100644
--- a/gnu/usr.bin/binutils/opcodes/sparc-opc.c
+++ b/gnu/usr.bin/binutils/opcodes/sparc-opc.c
@@ -1,5 +1,6 @@
 /* Table of opcodes for the sparc.
-   Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000
    Free Software Foundation, Inc.
 
 This file is part of the BFD library.
@@ -35,27 +36,30 @@ Boston, MA 02111-1307, USA.	*/
 #define MASK_SPARCLITE	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
 #define MASK_V9		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
 #define MASK_V9A	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
+#define MASK_V9B	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
 
 /* Bit masks of architectures supporting the insn.  */
 
 #define v6		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 /* v6 insns not supported on the sparclet */
 #define v6notlet	(MASK_V6 | MASK_V7 | MASK_V8 \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 #define v7		(MASK_V7 | MASK_V8 | MASK_SPARCLET \
-			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
 /* Although not all insns are implemented in hardware, sparclite is defined
    to be a superset of v8.  Unimplemented insns trap and are then theoretically
    implemented in software.
    It's not clear that the same is true for sparclet, although the docs
    suggest it is.  Rather than complicating things, the sparclet assembler
    recognizes all v8 insns.  */
-#define v8		(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
+#define v8		(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
+			 | MASK_V9 | MASK_V9A | MASK_V9B)
 #define sparclet	(MASK_SPARCLET)
 #define sparclite	(MASK_SPARCLITE)
-#define v9		(MASK_V9 | MASK_V9A)
-#define v9a		(MASK_V9A)
+#define v9		(MASK_V9 | MASK_V9A | MASK_V9B)
+#define v9a		(MASK_V9A | MASK_V9B)
+#define v9b		(MASK_V9B)
 /* v6 insns not supported by v9 */
 #define v6notv9		(MASK_V6 | MASK_V7 | MASK_V8 \
 			 | MASK_SPARCLET | MASK_SPARCLITE)
@@ -76,6 +80,8 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = {
   { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
   /* v9 with ultrasparc additions */
   { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
+  /* v9 with cheetah additions */
+  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
   { NULL, 0 }
 };
 
@@ -755,8 +761,8 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "scan",	F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),	"1,2,d", 0, sparclet|sparclite },
 { "scan",	F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),		"1,i,d", 0, sparclet|sparclite },
 
-{ "popc",	F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS2_G0|ASI(~0),"2,d", 0, v9 },
-{ "popc",	F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS2_G0,	"i,d", 0, v9 },
+{ "popc",	F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
+{ "popc",	F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,	"i,d", 0, v9 },
 
 { "clr",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"d", F_ALIAS, v6 }, /* or %g0,%g0,d */
 { "clr",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),		"d", F_ALIAS, v6 }, /* or %g0,0,d	*/
@@ -843,6 +849,10 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "wr", F3(2, 0x30, 1)|RD(22),	F3(~2, ~0x30, ~1)|RD(~22),		"1,i,_", 0, v9a }, /* wr r,i,%softint */
 { "wr", F3(2, 0x30, 0)|RD(23),	F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),	"1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
 { "wr", F3(2, 0x30, 1)|RD(23),	F3(~2, ~0x30, ~1)|RD(~23),		"1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
+{ "wr", F3(2, 0x30, 0)|RD(24),	F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),	"1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
+{ "wr", F3(2, 0x30, 1)|RD(24),	F3(~2, ~0x30, ~1)|RD(~24),		"1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
+{ "wr", F3(2, 0x30, 0)|RD(25),	F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),	"1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
+{ "wr", F3(2, 0x30, 1)|RD(25),	F3(~2, ~0x30, ~1)|RD(~25),		"1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
 
 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|SIMM13(~0),		"M,d", 0, v8 }, /* rd %asrX,r */
 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),	"y,d", 0, v6 }, /* rd %y,r */
@@ -862,6 +872,8 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "rd",	F3(2, 0x28, 0)|RS1(19),		F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %gsr,r */
 { "rd",	F3(2, 0x28, 0)|RS1(22),		F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %softint,r */
 { "rd",	F3(2, 0x28, 0)|RS1(23),		F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),	"/,d", 0, v9a }, /* rd %tick_cmpr,r */
+{ "rd",	F3(2, 0x28, 0)|RS1(24),		F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),	"/,d", 0, v9b }, /* rd %sys_tick,r */
+{ "rd",	F3(2, 0x28, 0)|RS1(25),		F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),	"/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
 
 { "rdpr",	F3(2, 0x2a, 0),		F3(~2, ~0x2a, ~0)|SIMM13(~0),	"?,d", 0, v9 },   /* rdpr %priv,r */
 { "wrpr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0),		"1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
@@ -1814,6 +1826,19 @@ SLCBCC("cbnefr", 15),
 { "array16",	F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
 { "array32",	F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
 
+/* Cheetah instructions */
+{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
+{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
+{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
+{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
+{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
+{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
+
+{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
+{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
+
+{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
+
 /* More v9 specific insns, these need to come last so they do not clash
    with v9a instructions such as "edge8" which looks like impdep1. */
 
@@ -1976,6 +2001,7 @@ static arg prefetch_table[] =
   { 2, "#n_writes" },
   { 3, "#one_write" },
   { 4, "#page" },
+  { 16, "#invalidate" },
   { 0, 0 }
 };
 
diff --git a/gnu/usr.bin/binutils/opcodes/sysdep.h b/gnu/usr.bin/binutils/opcodes/sysdep.h
index bb23e5fcf5d..ce9adde399e 100644
--- a/gnu/usr.bin/binutils/opcodes/sysdep.h
+++ b/gnu/usr.bin/binutils/opcodes/sysdep.h
@@ -1,5 +1,5 @@
 /* Random host-dependent support code.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
+   Copyright 1995, 1997, 2000 Free Software Foundation, Inc.
    Written by Ken Raeburn.
 
 This file is part of libopcodes, the opcodes library.
@@ -27,7 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "config.h"
 
-#include <ansidecl.h>
+#include "ansidecl.h"
 
 #ifdef HAVE_STDLIB_H
 #include <stdlib.h>
diff --git a/gnu/usr.bin/binutils/opcodes/w65-dis.c b/gnu/usr.bin/binutils/opcodes/w65-dis.c
index 09a17bbb8e7..8f08d6310cb 100644
--- a/gnu/usr.bin/binutils/opcodes/w65-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/w65-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble WDC 65816 instructions.
-   Copyright (C) 1995, 1998 Free Software Foundation, Inc.
+   Copyright 1995, 1998, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -15,21 +15,22 @@ You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
-#include "sysdep.h"
 #include <stdio.h>
+#include "sysdep.h"
 #define STATIC_TABLE
 #define DEFINE_TABLE
 
 #include "w65-opc.h"
 #include "dis-asm.h"
 
-static   fprintf_ftype fpr;
-static   void *stream;
-static   struct disassemble_info *local_info;
+static fprintf_ftype fpr;
+static void *stream;
+static struct disassemble_info *local_info;
 #if 0
-static char *lname[] =  {"r0","r1","r2","r3","r4","r5","r6","r7","s0"};
+static char *lname[] = { "r0","r1","r2","r3","r4","r5","r6","r7","s0" };
 
-static char *findname (val)
+static char *
+findname (val)
      unsigned int val;
 {
   if (val >= 0x10 && val <= 0x20)
@@ -41,79 +42,77 @@ static void
 print_operand (lookup, format, args)
      int lookup;
      char *format;
-     unsigned     int *args;
+     unsigned int *args;
 {
   int val;
   int c;
 
   while (*format)
     {
-      switch ( c = *format++) 
+      switch (c = *format++)
 	{
 	case '$':
 	  val = args[(*format++) - '0'];
-	  if (lookup) 
+	  if (lookup)
 	    {
 #if 0
-	      name = findname(val);
+	      name = findname (val);
 	      if (name)
-		fpr(stream, "%s", name);
+		fpr (stream, "%s", name);
 	      else
 #endif
-		local_info->print_address_func (val, local_info);  
+		local_info->print_address_func (val, local_info);
 	    }
 	  else
 	    fpr (stream, "0x%x", val);
 
 	  break;
 	default:
-	  fpr(stream,"%c", c);
+	  fpr (stream, "%c", c);
 	  break;
 	}
     }
 }
-int 
-print_insn_w65(memaddr, info)
+
+int
+print_insn_w65 (memaddr, info)
      bfd_vma memaddr;
      struct disassemble_info *info;
 {
-
-
   int status = 0;
   unsigned char insn[4];
   register struct opinfo *op;
   int i;
-  int X =0;
+  int X = 0;
   int M = 0;
   int args[2];
-stream = info->stream;
+  stream = info->stream;
   fpr = info->fprintf_func;
-local_info =    info;
-  for (i = 0; i <4 && status == 0; i++) 
+  local_info = info;
+  for (i = 0; i < 4 && status == 0; i++)
     {
-    status = info->read_memory_func(memaddr+i, insn + i, 1, info);
-  }
-
+      status = info->read_memory_func (memaddr + i, insn + i, 1, info);
+    }
 
-  for (op = optable; op->val != insn[0]; op++) 
+  for (op = optable; op->val != insn[0]; op++)
     ;
 
-  fpr(stream,"%s", op->name);
-  
-  /* Prepare all the posible operand values */
+  fpr (stream, "%s", op->name);
+
+  /* Prepare all the posible operand values.  */
   {
     int size = 1;
     int asR_W65_ABS8 = insn[1];
     int asR_W65_ABS16 = (insn[2] << 8) + asR_W65_ABS8;
     int asR_W65_ABS24 = (insn[3] << 16) + asR_W65_ABS16;
-    int asR_W65_PCR8 = ((char)(asR_W65_ABS8)) + memaddr + 2;
-    int asR_W65_PCR16 = ((short)(asR_W65_ABS16)) + memaddr + 3;
+    int asR_W65_PCR8 = ((char) (asR_W65_ABS8)) + memaddr + 2;
+    int asR_W65_PCR16 = ((short) (asR_W65_ABS16)) + memaddr + 3;
 
-    switch (op->amode) {
-      DISASM();
-    }
+    switch (op->amode)
+      {
+	DISASM ();
+      }
 
-  return size;
+    return size;
   }
-
 }
diff --git a/gnu/usr.bin/binutils/opcodes/w65-opc.h b/gnu/usr.bin/binutils/opcodes/w65-opc.h
index 9dc3535c787..a6e17df2ce5 100644
--- a/gnu/usr.bin/binutils/opcodes/w65-opc.h
+++ b/gnu/usr.bin/binutils/opcodes/w65-opc.h
@@ -1,5 +1,26 @@
-			/* WDC 65816 Assembler opcode table */
-			/*   (generated by the program sim/w65/gencode -a) */
+/* Instruction opcode header for WDC 65816 
+   (generated by the program sim/w65/gencode -a)
+
+Copyright 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
 #define ADDR_IMMTOA              1	 /* #a      */
 #define ADDR_IMMCOP              2	 /* #c      */
 #define ADDR_IMMTOI              3	 /* #i      */
diff --git a/gnu/usr.bin/binutils/opcodes/z8k-dis.c b/gnu/usr.bin/binutils/opcodes/z8k-dis.c
index 590f9d30bf0..825950059da 100644
--- a/gnu/usr.bin/binutils/opcodes/z8k-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/z8k-dis.c
@@ -1,5 +1,6 @@
 /* Disassemble z8000 code.
-   Copyright 1992, 1993, 1995, 1998 Free Software Foundation, Inc.
+   Copyright 1992, 1993, 1998, 2000
+   Free Software Foundation, Inc.
 
 This file is part of GNU Binutils.
 
@@ -22,10 +23,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #define DEFINE_TABLE
 #include "z8k-opc.h"
-
 
 #include <setjmp.h>
-
 
 typedef struct
 {
@@ -67,7 +66,7 @@ fetch_data (info, nibble)
 {
   unsigned char mybuf[20];
   int status;
-  instr_data_s *priv = (instr_data_s *)info->private_data;
+  instr_data_s *priv = (instr_data_s *) info->private_data;
 
   if ((nibble % 4) != 0)
     abort ();
@@ -84,15 +83,15 @@ fetch_data (info, nibble)
 
   {
     int i;
-    unsigned char *p = mybuf ;
-    
+    unsigned char *p = mybuf;
+
     for (i = 0; i < nibble;)
       {
 	priv->words[i] = (p[0] << 8) | p[1];
-	
+
 	priv->bytes[i] = *p;
 	priv->nibbles[i++] = *p >> 4;
-	priv->nibbles[i++] = *p &0xf;
+	priv->nibbles[i++] = *p & 0xf;
 
 	++p;
 	priv->bytes[i] = *p;
@@ -126,7 +125,7 @@ static char *codes[16] =
   "nc/uge"
 };
 
-int z8k_lookup_instr PARAMS ((unsigned char*, disassemble_info *));
+int z8k_lookup_instr PARAMS ((unsigned char *, disassemble_info *));
 static void output_instr
   PARAMS ((instr_data_s *, unsigned long, disassemble_info *));
 static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *));
@@ -196,7 +195,9 @@ z8k_lookup_instr (nibbles, info)
   while (!nibl_matched && z8k_table[tabl_index].name)
     {
       nibl_matched = 1;
-      for (nibl_index = 0; nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; nibl_index++)
+      for (nibl_index = 0;
+	   nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched;
+	   nibl_index++)
 	{
 	  if ((nibl_index % 4) == 0)
 	    /* Fetch one word at a time.  */
@@ -439,7 +440,7 @@ unpack_instr (instr_data, is_segmented, info)
 	  instr_data->interrupts = instr_nibl & 0x3;
 	  break;
 	case CLASS_BIT:
-	  /* do nothing */
+	  /* Do nothing.  */
 	  break;
 	case CLASS_IR:
 	  instr_data->arg_reg[datum_value] = instr_nibl;
diff --git a/gnu/usr.bin/binutils/opcodes/z8kgen.c b/gnu/usr.bin/binutils/opcodes/z8kgen.c
index 44df0b2ec0d..c8f3970d096 100644
--- a/gnu/usr.bin/binutils/opcodes/z8kgen.c
+++ b/gnu/usr.bin/binutils/opcodes/z8kgen.c
@@ -1,20 +1,21 @@
 /*
-This file is part of GNU Binutils.
+  Copyright 2001 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+  This file is part of GNU Binutils.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
 
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /* This program generates z8k-opc.h */