diff options
| author | Federico G. Schwindt <fgsch@cvs.openbsd.org> | 2002-05-13 14:00:18 +0000 |
|---|---|---|
| committer | Federico G. Schwindt <fgsch@cvs.openbsd.org> | 2002-05-13 14:00:18 +0000 |
| commit | 80569f10d304683516f20f86bbafb107127ff63e (patch) | |
| tree | 5d81f65131a54f7b47340b5148a9f878549db293 /gnu/usr.bin/binutils/opcodes | |
| parent | 9ed85e2bfb346f753dcf53ed63b65520ed413f8b (diff) | |
Import binutils-2.11.2
- only the binutils package (no gdb here)
- don't import libiberty and texinfo, they are elsewhere
- remove all .info* generated files
Diffstat (limited to 'gnu/usr.bin/binutils/opcodes')
79 files changed, 31377 insertions, 1889 deletions
diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog-9297 b/gnu/usr.bin/binutils/opcodes/ChangeLog-9297 new file mode 100644 index 00000000000..5fa3fa02d6b --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ChangeLog-9297 @@ -0,0 +1,3791 @@ +Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add FP_D to s.d instruction flags. + +Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (halt, pulse): Enable them on the 68060. + +Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit + PC relative offset forms before the 15 bit forms. An assembler command + line option now chooses the default. + +Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-opc.c (d30v_opcode_table): Set new flags bits + FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. + +1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com> + + * configure: Only build libopcodes shared if --enable-shared's value + was `yes', or was set to `*opcodes*'. + * aclocal.m4: Likewise. + * NOTE: this really needs to be fixed in libtool/libtool.m4, the + original source of this bit of code. It's not clear what the best fix + would be, though. + +Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. + (tic80_opcodes): Reorder table entries to put the 32 bit PC relative + offset forms before the 15 bit forms, to default to the long forms. + +Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com> + + * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. + +Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_little_arm): Prevent examination of stored + symbol if none is present. + (print_insn_big_arm): Prevent examination of stored symbol if + none is present. + +Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com> + + * d10v-opc.c (d10v_opcodes): Correct entry for RTE. + +Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com> + + * disassemble.c: Remove disasm_symaddr() function. + + * arm-dis.c: Use info->symbol instead of info->flags to determine + if disassmbly should be in Thumb or Arm mode. + +Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c: Add support for disassembling Thumb opcodes. + (print_insn_thumb): New function. + + * disassemble.c (disasm_symaddr): New function. + + * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. + (thumb_opcodes): Table of Thumb opcodes. + +Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (btst): Change Dd@s to Dd;b. + + * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', + and 'v' as operand types. + +Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Add argument for lpstop. From Olivier Carmona + <olivier.carmona@di.epfl.ch>. + * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, + which has a two word opcode with a one word argument. + +Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is + unsigned, not signed. + (d30v_format_table): Add SHORT_CMPU cases for cmpu. + +Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d10v-dis.c (print_operand): + Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d10v-opc.c (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + (FSRC): Split into: + (FFSRC, CFSRC). + +Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Move the INSN_MACRO ISA value to the membership + field for all INSN_MACRO's. + * mips16-opc.c: same + +Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c (sync,cache): These are 3900 insns. + +Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + sh-opc.h (sh_table): Remove ftst/nan. + +Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips-opc.c (ffc, ffs): Fix mask. + +Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m + control registers. + +Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Replace // with /* ... */ + +Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com> + + * sparc-opc.c: Add wr & rd for v9a asr's. + * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. + (v9a_asr_reg_names): New variable. + Patch from David Miller <davem@vger.rutgers.edu>. + +Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com> + + * sparc-opc.c (v9notv9a): New insn type. + (IMPDEP): Move to the end to not conflict with edge8 et al. + Patch from David Miller <davem@vger.rutgers.edu>. + +Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c (bnezl,beqzl): Mark these as also tx39. + +Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. + +Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Use new symbol_at_address_func() field + of disassemble_info structure to determine if an overlay address + has a matching symbol in low memory. + + * dis-buf.c (generic_symbol_at_address): New (dummy) function for + new symbol_at_address_func field in disassemble_info structure. + +Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (extract_d22): Use signed arithmatic. + +Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Three op mult is not an ISA insn. + +Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Fix formatting. + +Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather + than assuming that char is signed. Explicitly sign extend 16 bit + values, rather than assuming that short is 16 bits. + (OP_sI, OP_J, OP_DIR): Likewise. + +Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (v850_sreg_names): Use symbolic names for higher + system registers. + +Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c: Fix typo in comment. + + * v850-dis.c (disassemble): Add test of processor type when + determining opcodes. + +Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Use a diversion to set enable_shared before the + arguments are parsed. + * configure: Rebuild. + +Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (TBL1): Use ! rather than `. + * m68k-dis.c (print_insn_arg): Remove ` operand specifier. + +Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. + + * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. + + * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr + for mcf5200. + + * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. + * aclocal.m4: Rebuild with new libtool. + * configure: Rebuild. + +Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. + +Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. + +Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (v850_opcodes): Further rearrangements. + +Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com> + + * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. + +Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (v850_opcodes): Fields reordered to allow assembler + parser to work. + +Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. + +Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c: Initialise processors field of v850_opcode structure. + +Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com> + + Merge changes from Martin Hunt: + + * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. + + * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. + (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix + rot2h, sra2h, and srl2h to use new SHORT_A5S format. + + * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. + + * d30v-dis.c (print_insn): First operand of d*i (delayed + branch) instructions is relative. + + * d30v-opc.c (d30v_opcode_table): Change form for repeati. + (d30v_operand_table): Add IMM6S3 type. + (d30v_format_table): Change SHORT_D2. Add LONG_Db. + + * d30v-dis.c: Fix bug with ".s" and ".l" extensions + and cmp instructions. + + * d30v-opc.c: Correct entries for repeat*, and sat*. + Make IMM5 unsigned. Create IMM6U and IMM12S3U operand + types. Correct several formats. + + * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. + + * d30v-opc.c (pre_defined_registers): Change control registers. + + * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and + SHORT_C2. Manual was incorrect. + + * d30v-dis.c (lookup_opcode): Return value now indicates + if an opcode has a short and a long form. Used for deciding + to append a ".s" or ".l". + (print_insn): Append a ".s" to an instruction if it is + the short form and ".l" if it is a long form. Do not append + anything if the instruction has only one possible size. + + * d30v-opc.c: Change mulx2h to require an even register. + New form: SHORT_A2; a SHORT_A form that needs an even + register as the first operand. + + * d30v-dis.c (print_insn_d30v): Fix problem where the last + instruction was not being disassembled if there were an odd + number of instructions. + + * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. + +Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Improved display of register lists. + +Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Fix assembler args to + fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, + fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, + fandnot1s, fandnot2s. + +Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. + +Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen-asm.c (cgen_parse_address): New argument resultp. + All callers updated. + * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. + +Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): PC relative instructions are + relative to the next instruction, not the current instruction. + +Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Only signed extend values that are not + returned by extract functions. + Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. + +Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c: Update comments. Remove use of + V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. + +Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (MOVHI): Immediate parameter is unsigned. + +Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com> + + * configure: Rebuilt with latest devo autoconf for NT support. + +Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Use curly brace syntax for register + lists. + + * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases + where r0 is being used as a destination register. + +Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. + +Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com> + + * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. + +Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (v850_opcodes[]): Remove use of flag field. + * v850-opc.c (v850_opcodes[]): Add support for reversed short load + opcodes.. + +Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> + + * configure (cgen_files): Add support for v850e target. + * configure.in (cgen_files): Add support for v850e target. + +Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> + + * configure (cgen_files): Add support for v850ea target. + * configure.in (cgen_files): Add support for v850ea target. + +Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com> + + * configure.in (bfd_arc_arch): Add. + * configure: Rebuild. + * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. + * Makefile.in: Rebuild. + * arc-dis.c, arc-opc.c: New files. + * disassemble.c (ARCH_all): Define ARCH_arc. + (disassembler): Add ARC support. + +Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com> + + * v850-dis.c (disassemble): Add support for v850EA instructions. + + * v850-opc.c (insert_i5div, extract_i5div): New Functions. + (v850_opcodes): Add v850EA instructions. + + * v850-dis.c (disassemble): Add support for v850E instructions. + + * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, + extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, + insert_spe, extract_spe): New Functions. + (v850_opcodes): Add v850E instructions. + + * v850-opc.c: Reorganised and re-layed out to improve readability + and portability. + +Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com> + + * configure: Rebuild with autoconf 2.12.1. + +Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com> + + * aclocal.m4, configure: Rebuild with new automake patches. + +Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Set enable_shared before AM_PROG_LIBTOOL. + * acinclude.m4: Just include acinclude.m4 from BFD. + * aclocal.m4, configure: Rebuild. + +Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.am: New file, based on old Makefile.in. + * acconfig.h: New file. + * acinclude.m4: New file. + * stamp-h.in: New file. + * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. + Removed shared library handling; now handled by libtool. Replace + AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, + AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with + AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h + handling in AC_OUTPUT. + * dep-in.sed: Change .o to .lo. + * Makefile.in: Now built with automake. + * aclocal.m4: Now built with aclocal. + * config.in, configure: Rebuild. + +Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Fix typo/thinko in "eret" instruction. + +Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. + Make array const. + * sparc-dis.c (sorted_opcodes): New static local. + (struct opcode_hash): `opcode' is pointer to const element. + (build_hash): First arg is now table of sorted pointers. + (print_insn_sparc): Sort opcodes by sorting table of pointers. + (compare_opcodes): Update. + +Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen-opc.c: #include <ctype.h>. + (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. + Handle case insensitive hashing. + (hash_keyword_value): Change type of `value' to unsigned int. + +Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (mips_builtin_opcodes): If an insn uses single + precision FP, mark it as such. Likewise for double precision + FP. Mark ISA1 insns. Consolidate duplicate opcodes where + possible. + +Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com> + + * ppc-opc.c (extract_nsi): make unsigned expression signed before + negating it. + (UNUSED): remove one level of parens, so MSVC doesn't choke on + nesting depth when all the macros are expanded. + +Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: The fcmp v9a instructions take an integer register + as a destination, not a floating point register. From Christian + Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>. + +Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() + syntax. From Roman Hodek + <rnhodek@faui22c.informatik.uni-erlangen.de>. + + * i386-dis.c (twobyte_has_modrm): Fix pand. + +Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu> + + * i386-dis.c (dis386_twobyte): Fix pand and pandn. + +Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * arm-dis.c: Add prototypes for arm_decode_shift and + print_insn_arm. + +Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c: Add r3900 insns. + +Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com> + + * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't + print delay slot instructions on the same line. When using a PC + relative load, add a comment with the value being loaded if it can + be obtained. + +Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl + to pushS/popS for segment regs and byte constant so that + pushw/popw printed when in 16 bit data mode. + + * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to + print cbtw, cwtd in 16 bit data mode. + * i386-dis.c (putop): extra case W to support above. + + * i386-dis.c (print_insn_x86): print addr32 prefix when given + address size prefix in 16 bit address mode. + +Fri May 23 16:47:23 1997 Ian Lance Taylor <ian@cygnus.com> + + * sh-dis.c: Reindent. Rename local variable fprintf to + fprintf_fn. + +Thu May 22 14:06:02 1997 Doug Evans <dje@canuck.cygnus.com> + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. + +Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com> + + * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new + field membership. + * mips16-opc.c (mip16_opcodes): same. + +Mon May 12 15:10:53 1997 Jim Wilson <wilson@cygnus.com> + + * m68k-opc.c (moveb): Change $d to %d. + +Mon May 5 14:28:41 1997 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c: (dis386_twobyte): Add MMX instructions. + (twobyte_has_modrm): Likewise. + (grps): Likewise. + (OP_MMX, OP_EM, OP_MS): New static functions. + + * i386-dis.c: Revert patch of April 4. The output now matches + what gcc generates. + +Fri May 2 12:48:37 1997 Doug Evans <dje@canuck.cygnus.com> + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead + of $simm16. + +Thu May 1 15:34:15 1997 Doug Evans <dje@canuck.cygnus.com> + + * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. + +Tue Apr 15 12:40:08 1997 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (install): Depend upon installdirs. + (installdirs): New target. + +Mon Apr 14 12:13:51 1997 Ian Lance Taylor <ian@cygnus.com> + + From Thomas Graichen <graichen@rzpd.de>: + * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. + * configure: Rebuild. + +Sun Apr 13 17:50:41 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. + Delete string{,s}.h support. + +Thu Apr 10 14:44:56 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen-asm.c (cgen_parse_operand_fn): New global. + (cgen_parse_{{,un}signed_integer,address}): Update call to + cgen_parse_operand_fn. + (cgen_init_parse_operand): New function. + * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed + from cgen_asm_init_parse. + (m32r_cgen_assemble_insn): New operand `errmsg'. + Delete call to as_bad, return error message to caller. + (m32r_cgen_asm_hash_keywords): #if 0 out. + +Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, + not data register. + [case 'J']: Fix typo in register name. + +Mon Apr 7 16:48:22 1997 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Substitute SHLIB_LIBS. + * configure: Rebuild. + * Makefile.in (SHLIB_LIBS): New variable. + ($(SHLIB)): Use $(SHLIB_LIBS). + +Mon Apr 7 11:45:44 1997 Doug Evans <dje@canuck.cygnus.com> + + * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. + + * cgen-opc.c (hash_keyword_name): Improve algorithm. + + * disassemble.c (disassembler): Handle m32r. + +Fri Apr 4 12:29:38 1997 Doug Evans <dje@canuck.cygnus.com> + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. + * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. + * Makefile.in (CFILES): Add them. + (ALL_MACHINES): Add them. + (dependencies): Regenerate. + * configure.in (cgen_files): New variable. + (bfd_m32r_arch): Add entry. + * configure: Regenerate. + +Fri Apr 4 14:04:16 1997 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Correct file names for bfd_mn10[23]00_arch. + * configure: Rebuild. + + * Makefile.in: Rebuild dependencies. + + * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". + + * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and + fdivp. + +Thu Apr 3 13:22:45 1997 Ian Lance Taylor <ian@cygnus.com> + + * Branched binutils 2.8. + +Wed Apr 2 12:23:53 1997 Ian Lance Taylor <ian@cygnus.com> + + * m10200-dis.c: Rename from mn10200-dis.c. + * m10200-opc.c: Rename from mn10200-opc.c. + * m10300-dis.c: Rename from mn10300-dis.c + * m10300-opc.c: Rename from mn10300-opc.c. + * Makefile.in: Update accordingly. + + * mips16-opc.c: Add mul and dmul macros. + +Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: Update CFLAGS, add clean target. + +Fri Mar 28 12:10:09 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add "wait". From Ralf Baechle + <ralf@gnu.ai.mit.edu>. + + * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. + * configure, config.in: Rebuild. + * sysdep.h: Include <stdlib.h> if it exists. + * sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include + <string.h>. + * Makefile.in: Rebuild dependencies. + +Thu Mar 27 14:24:43 1997 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From + Andrew Bray <andy@madhouse.demon.co.uk>. + + * mips-opc.c: Add cast when setting mips_opcodes. + +Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Fix sign extension problem. + * v850-opc.c (extract_d*): Fix sign extension problems to make + disassembly calculate branch offsets correctly. + +Mon Mar 24 13:22:13 1997 Ian Lance Taylor <ian@cygnus.com> + + * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. + + * mips-opc.c: Add dctr and dctw. + +Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v-dis.c (print_insn): Change the way signed constants + are displayed. + +Fri Mar 21 14:37:52 1997 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (BFD_H): New variable. + (HFILES): New variable. + (CFILES): Add all C files. + (.dep, .dep1, dep.sed, dep, dep-in): New targets. + Delete old dependencies, and build new ones. + * dep-in.sed: New file. + +Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be> + + * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. + +Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Change "trap" to "syscall". + * mn10300-opc.c: Add new "syscall" instruction. + +Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and + mulul insns on the coldfire. + +Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com> + + * arm-dis.c (print_insn_arm): Don't print instruction bytes. + (print_insn_big_arm): Set bytes_per_chunk and display_endian. + (print_insn_little_arm): Likewise. + +Fri Mar 14 15:08:59 1997 Ian Lance Taylor <ian@cygnus.com> + + Based on patches from H.J. Lu <hjl@lucon.org>: + * i386-dis.c (fetch_data): Add prototype. + * m68k-dis.c (fetch_data): Add prototype. + (dummy_print_address): Add prototype. Make static. + * ppc-opc.c (valid_bo): Add prototype. + * sparc-dis.c (build_hash_table): Add prototype. + (is_delayed_branch, compute_arch_mask): Add prototypes. + (print_insn_sparc): Make several local variables const. + (compare_opcodes): Change arguments to const PTR. Add prototype. + * sparc-opc.c (arg): Change name field to be const. + (lookup_name, lookup_value): Add prototypes. Change table and + name parameters to be const. + (sparc_encode_asi): Change name parameter to be const. + (sparc_encode_membar, sparc_encode_prefetch): Likewise. + (sparc_encode_sparclet_cpreg): Likewise. + (sparc_decode_asi): Change return type to be const. + (sparc_decode_membar, sparc_decode_prefetch): Likewise. + (sparc_decode_sparclet_cpreg): Likewise. + +Fri Mar 7 10:51:49 1997 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since + Solaris doesn't like the combined options, and the -f is + unnecessary. + (stamp-tshlink, install): Likewise. + +Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these + as relaxable. + +Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. + +Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on + the mc68000. + +Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be> + + * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. + +Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com> + + * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. + +Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com> + + * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. + +Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use + floatformat_to_double to make portable. + (print_insn_arg): Use NEXTEXTEND macro when extracting extended + precision float. + +Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com> + + * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, + and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. + +Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to + d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. + +Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (LSI_SCALED): Renamed from this ... + (OFF_SL_BR_SCALED): ... to this, and added the flag + TIC80_OPERAND_BASEREL to the flags word. + (tic80_opcodes): Replace all occurances of LSI_SCALED with + OFF_SL_BR_SCALED. + +Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> + + * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. + Change mips_opcodes from const array to a pointer, + and change bfd_mips_num_opcodes from const int to int, + so that we can increase the size of the mips opcodes table + dynamically. + +Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_predefined_symbols): Revert change to + store BITNUM values in the table in one's complement form + to match behavior when assembler is given a raw numeric + value for a BITNUM operand. + * tic80-dis.c (print_operand_bitnum): Ditto. + +Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v-opc.c: Removed references to FLAG_X. + +Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in: Add dependencies on ../bfd/bfd.h as required. + +Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * Makefile.in: Added d30v object files. + * configure: (bfd_d30v_arch) Rebuilt. + * configure.in: (bfd_d30v_arch) Added new case. + * d30v-dis.c: New file. + * d30v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d30v. + +Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_predefined_symbols): Add symbolic + representations for the floating point BITNUM values. + +Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values + in the table in one's complement form, as they appear in the + actual instruction. + (tic80_symbol_to_value): Use macros to access predefined + symbol fields. + (tic80_value_to_symbol): Ditto. + (tic80_next_predefined_symbol): New function. + * tic80-dis.c (print_operand_bitnum): Remove code that did + one's complement for BITNUM values. + +Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: Remove 8 bit characters. Update to latest + gcc release. + +Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be> + + * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. + +Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (IMM16_PCREL): This is a signed operand. + (IMM24_PCREL): Likewise. + +Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base + address for an extended PC relative instruction that is not a + branch. + +Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and + bytes_per_line. + +Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. + (tic80_opcodes): Sort entries so that long immediate forms + come after short immediate forms, making it easier for + assembler to select the right one for a given operand. + +Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and + display_endian. + (print_insn_mips16): Likewise. + +Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_symbol_to_value): Changed to accept + a symbol class that restricts translation to just that + class (general register, condition code, etc). + +Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, + and REG_DEST_E for register operands that have to be + an even numbered register. Add REG_FPA for operands that + are one of the floating point accumulator registers. + Add TIC80_OPERAND_MASK to flags for ENDMASK operand. + (tic80_opcodes): Change entries that need even numbered + register operands to use the new operand table entries. + Add "or" entries that are identical to "or.tt" entries. + +Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips16-opc.c: Add new cases of exit instruction for + disassembler. + * mips-dis.c (print_mips16_insn_arg): Display floating point + registers in operands of exit instruction. Print `$' before + register names in operands of entry and exit instructions. + +Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_predefined_symbols): Table of name/value + pairs for all predefined symbols recognized by the assembler. + Also used by the disassembling routines. + (tic80_symbol_to_value): New function. + (tic80_value_to_symbol): New function. + * tic80-dis.c (print_operand_control_register, + print_operand_condition_code, print_operand_bitnum): + Remove private tables and use tic80_value_to_symbol function. + +Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-dis.c (print_operand): Change address printing + to correctly handle PC wrapping. Fixes PR11490. + +Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative + branches relaxable. + +Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_insn_mips16): Set insn_info information. + (print_mips16_insn_arg): Likewise. + + * mips-dis.c (print_insn_mips16): Better handling of an extend + opcode followed by an instruction which can not be extended. + +Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Changed operand specifier for the + coldfire moveb instruction to not allow an address register as + destination. Although the documentation does not indicate that + this is invalid, experiments uncovered unexpected behavior. + Added a comment explaining the situation. Thanks to Andreas + Schwab for pointing this out to me. + +Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_opcodes): Expand comment to note that the + entries are presorted so that entries with the same mnemonic are + adjacent to each other in the table. Sort the entries for each + instruction so that this is true. + +Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c: Include <libiberty.h>. + (print_insn_m68k): Sort the opcode table on the most significant + nibble of the opcode. + +Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", + "vsub", "vst", "xnor", and "xor" instructions. + (V_a1): Renamed from V_a, msb of accumulator reg number. + (V_a0): Add macro, lsb of accumulator reg number. + +Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (print_insn_tic80): Broke excessively long + function up into several smaller ones and arranged for + the instruction printing function to be callable recursively + to print vector instructions that have both a load and a + math instruction packed into a single opcode. + * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode + to explain why it comes after the other vector opcodes. + +Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com> + + * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire + move insns to handle immediate operands. + +Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". + fix operand mask in the "moveml" entries for the coldfire. + +Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): + New macros for building vector instruction opcodes. + (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and + FMT_LI, which were unused. The field is now a flags field. + Remove some opcodes that are possible, but illegal, such + as long immediate instructions with doubles for immediate + values. Add "vadd" and "vld" instructions. + +Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (tic80_operands): Reorder some table entries to make + the order more logical. Move the shift alias instructions ("rotl", + "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be + interspersed with the regular sr.x and sl.x instructions. Add + and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", + "sub", "subu", "swcr", and "trap". + +Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com> + + * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. + (OFF_SL_PC): Renamed from OFF_SL. + (OFF_SS_BR): New operand type for base relative operand. + (OFF_SL_BR): New operand type for base relative operand. + (REG_BASE): New operand type for base register operand. + (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", + "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", + "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" + instructions. + * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width + 10 char field, padded with spaces on rhs, rather than a string + followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather + than old TIC80_OPERAND_RELATIVE. Add support for new + TIC80_OPERAND_BASEREL flag bit. + +Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (print_insn_tic80): Print floating point operands + as floats. + * tic80-opc.c (SPFI): Add single precision floating point + immediate operand type. + (ROTATE): Add rotate operand type for shifts. + (ENDMASK): Add for shifts. + (n): Macro for the 'n' bit. + (i): Macro for the 'i' bit. + (PD): Macro for the 'PD' field. + (P2): Macro for the 'P2' field. + (P1): Macro for the 'P1' field. + (tic80_opcodes): Add entries for "exts", "extu", "fadd", + "fcmp", and "fdiv". + +Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): Mask off unwanted bits after + adding in current address for pc-relative operands. + +Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. + (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. + * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names + changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. + (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, + REG_BASE_M_SI, REG_BASE_M_LI respectively. + (REG_SCALED, LSI_SCALED): New operand types. + (E): New macro for 'E' bit at bit 27. + (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap + opcodes, including the various size flavors (b,h,w,d) for + the direct load and store instructions. + +Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit + in an instruction. + * tic80-dis.c (print_insn_tic80): Change comma and paren handling. + Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. + * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. + (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. + (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode + masks with "MASK_* & ~M_*" to get the M bit reset. + (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. + +Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com> + + * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE + correctly. Add support for printing TIC80_OPERAND_BITNUM and + TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic + form. + * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, + CC, SICR, and LICR table entries. + (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", + "bcnd", and "brcr" opcodes. + +Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com> + + * ppc-opc.c (powerpc_operands): Make comment match the + actual fields (no shift field). + * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". + * tic80-dis.c (print_insn_tic80): Replace abort stub with a + partial implementation, work in progress. + * tic80-opc.c (tic80_operands): Begin construction operands table. + (tic80_opcodes): Continue populating opcodes table and start + filling in the operand indices. + (tic80_num_opcodes): Add this. + +Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Add #B case for moveq. + +Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Make sure all variables are initialized + before they are used. + +Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Put curly-braces around operands + for "breakpoint" instruction. + +Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. + (dep): Use ALL_CFLAGS rather than CFLAGS. + +Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY + flag. + +Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com> + + * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. + (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. + +Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips16-opc.c: Add "abs". + +Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com> + + * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. + * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. + (disassembler): Add bfd_arch_tic80 support to set disassemble + to print_insn_tic80. + * tic80-dis.c (print_insn_tic80): Add stub. + +Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com> + + * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. + * configure: Regenerate with autoconf. + * tic80-dis.c: Add file. + * tic80-opc.c: Add file. + +Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. + +Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Add SIMM16N. + (mn10200_opcodes): Use it for some logicals and btst insns. + Add "break" and "trap" instructions. + + * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. + + * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". + +Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_mips16_insn_arg): The base address of a PC + relative load or add now depends upon whether the instruction is + in a delay slot. + +Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c: Finish writing disassembler. + * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". + Fix mask for "jmp (an)". + + * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently + handle endianness issues for mn10300. + + * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". + +Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 + instruction. Fix opcode field for "movb (imm24),dn". + + * mn10200-opc.c (mn10200_operands): Fix insertion position + for DI operand. + +Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Create mn10200 opcode table. + * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, + but moving along nicely. + +Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add mips16-opc.o. + +Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Revert change to use < and > + specifiers for fmovem* instructions. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Remove '$' register prefixing. + +Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips16-opc.c: Change opcode for entry/exit to avoid conflicting + with dsrl. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c: Add some comments explaining the various + operands and such. + + * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. + +Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k-dis.c (print_insn_arg): Handle new < and > operand + specifiers. + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in fmovm* instructions. + +Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c (insert_li): Give an error if the offset has the two + least significant bits set. + +Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_insn_mips16): Separate the instruction from + the arguments with a tab, not a space. + +Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disasemble): Finish conversion to '$' as + register prefix. + + * mn10300-opc.c (mn10300_opcodes): Fix mask field for + mov am,(imm32,sp). + +Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure: Rebuild with autoconf 2.12. + + Add support for mips16 (16 bit MIPS implementation): + * mips16-opc.c: New file. + * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". + (mips16_reg_names): New static array. + (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or + after seeing a 16 bit symbol. + (print_insn_little_mips): Likewise. + (print_insn_mips16): New static function. + (print_mips16_insn_arg): New static function. + * mips-opc.c: Add jalx instruction. + * Makefile.in (mips16-opc.o): New target. + * configure.in: Use mips16-opc.o for bfd_mips_arch. + * configure: Rebuild. + +Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in *save, *restore and movem* instructions. + + * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for + the coldfire. + + * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use + register operands for immediate arithmetic, not, neg, negx, and + set according to condition instructions. + + * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage + specifier of the effective-address operand in immediate forms of + arithmetic instructions. The specifier for the immediate operand + notes how and where the constant will be stored. + +Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" + opcode. + + * mn10300-dis.c (disassemble): Use '$' instead of '%' for + register prefix. + + * mn10300-dis.c (disassemble): Prefix registers with '%'. + +Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Handle register lists. + + * mn10300-opc.c: Fix handling of register list operand for + "call", "ret", and "rets" instructions. + + * mn10300-dis.c (disassemble): Print PC-relative and memory + addresses symbolically if possible. + * mn10300-opc.c: Distinguish between absolute memory addresses, + pc-relative offsets & random immediates. + + * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte + in 7 byte insns. + (disassemble): Handle SPLIT and EXTENDED operands. + +Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c: Rough cut at printing some operands. + + * mn10300-dis.c: Start working on disassembler support. + * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. + + * mn10300-opc.c (mn10300_operands): Add "REGS" for a register + list. + (mn10300_opcodes): Use REGS for register list in "movm" instructions. + +Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * d10v-opc.c (d10v_opcodes): Add3 sets the carry. + +Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Demand parens around + register argument is calls and jmp instructions. + +Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and + getx operand. Fix opcode for mulqu imm,dn. + +Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Hijack "bits" field + in MN10300_OPERAND_SPLIT operands for how many bits + appear in the basic insn word. Add IMM32_HIGH24, + IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. + (mn10300_opcodes): Use new operands as needed. + + * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 + for bset, bclr, btst instructions. + (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. + + * mn10300-opc.c (mn10300_operands): Remove many redundant + operands. Update opcode table as appropriate. + (IMM32): Add MN10300_OPERAND_SPLIT flag. + (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. + +Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 + operands (for indexed load/stores). Fix bitpos for DI + operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the + few instructions that insert immediates/displacements in the + middle of the instruction. Add IMM8E for 8 bit immediate in + the extended part of an instruction. + (mn10300_operands): Use new opcodes as appropriate. + +Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_opcodes): Declare the trap instruction + sequential so the assembler never parallelizes it with + other instructions. + +Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for + a data/address register that appears in register field 0 + and register field 1. + (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN + +Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> + + * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for + standard disassembly. + + * alpha-opc.c (alpha_operands): Rearrange flags slot. + (alpha_opcodes): Add new BWX, CIX, and MAX instructions. + Recategorize PALcode instructions. + +Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add relaxing "jbr". + +Tue Oct 29 16:30:28 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (_print_insn_mips): Don't print a trailing tab if + there are no operand types. + +Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (D9_RELAX): Renamed from D9, all references + changed. + (v850_operands): Make sure D22 immediately follows D9_RELAX. + +Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. + +Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w + and sst.w instructions. + + * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for + "bCC"instructions). + +Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (_print_insn_mips): Use a tab between the instruction + and the arguments. + +Tue Oct 22 23:32:56 1996 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c (PPCPWR2): Define. + (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating + it. + +Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode + field for movhu instruction. + + * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, + cast value to "long" not "signed long" to keep hpux10 + compiler quiet. + +Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field + for mov (abs16),DN. + + * mn10300-opc.c (FMT*): Remove definitions. + + * mn10300-opc.c (mn10300_opcodes): Fix destination register + for shift-by-register opcodes. + + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM + into [AD][MN][01] for encoding the position of the register + in the opcode. + +Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, + "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". + +Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. + Fix various typos. Add "PAREN" operand. + (MEM, MEM2): Define. + (mn10300_opcodes): Surround all memory addresses with "PAREN" + operands. Fix several typos. + + * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's + changes. + +Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (FMT_XX): Renumber starting at one. + (mn10300_operands): Rough cut. Enough to parse "mov" instructions + at this time. + (mn10300_opcodes): Break opcode format out into its own field. + Update many operand fields to deal with signed vs unsigned + issues. Fix one or two typos in the "mov" instruction + opcode, mask and/or operand fields. + +Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (plusha): Prefer encoding for m68040up, in case + m68851 wasn't reset. + +Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com> + + * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for + all opcodes. Very rough cut at operands for all opcodes. + + * mn10300-opc.c (mn10300_opcodes): Start fleshing out the + opcode table. + +Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c, mn10300-opc.c: New files. + * mn10200-dis.c, mn10300-dis.c: New files. + * mn10x00-opc.c, mn10x00-dis.c: Deleted. + * disassemble.c: Break mn10x00 support into 10200 and 10300 + support. + * configure.in: Likewise. + * configure: Rebuilt. + +Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. + +Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita + MN10x00 processors. + * disassemble (ARCH_mn10x00): Define. + (disassembler): Handle bfd_arch_mn10x00. + * configure.in: Recognize bfd_mn10x00_arch. + * configure: Rebuilt. + +Tue Oct 1 10:49:11 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses + accordingly. Don't declare functions using op_rtn. + +Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Add memaddr argument. Re-arrange + params to be more standard. + * (disassemble): Print absolute addresses and symbolic names for + branch and jump targets. + * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 + bit operands. + * (v850_opcodes): Add breakpoint insn. + +Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Move the fmovemx data register cases before the + other cases, so that they get recognized before the data register + does gets treated as a degenerate register list. + +Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add a case for "div" and "divu" with two registers + and a destination of $0. + +Tue Sep 10 16:12:39 1996 Fred Fish <fnf@rtl.cygnus.com> + + * mips-dis.c (print_insn_arg): Add prototype. + (_print_insn_mips): Ditto. + +Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_insn_arg): Print condition code registers as + $fccN. + +Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. + +Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Make static. Provide prototype. + +Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d9, insert_d22): Fix boundary case + in range checks. + +Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Handle insertion of ',', '[' and + ']' characters into the output stream. + * v850-opc.c (v850_opcodes: Remove size field from all opcodes. + Add "memop" field to all opcodes (for the disassembler). + Reorder opcodes so that "nop" comes before "mov" and "jr" + comes before "jarl". + + * v850-dis.c (print_insn_v850): Fix typo in last change. + + * v850-dis.c (print_insn_v850): Properly handle disassembling + a two byte insn at the end of a memory region when the memory + region's size is only two byte aligned. + + * v850-dis.c (v850_cc_names): Fix stupid thinkos. + + * v850-dis.c (v850_reg_names): Define. + (v850_sreg_names, v850_cc_names): Likewise. + (disassemble): Very rough cut at printing operands (unformatted). + + * v850-opc.c (BOP_MASK): Fix. + (v850_opcodes): Fix mask for jarl and jr. + + * v850-dis.c: New file. Skeleton for disassembler support. + * Makefile.in Remove v850 references, they're not needed here. + * configure.in: Add v850-dis.o when building v850 toolchains. + * configure: Rebuilt. + * disassemble.c (disassembler): Call v850 disassembler. + + * v850-opc.c (insert_d8_7, extract_d8_7): New functions. + (insert_d8_6, extract_d8_6): New functions. + (v850_operands): Rename D7S to D7; operand for D7 is unsigned. + Rename D8 to D8_7, use {insert,extract}_d8_7 routines. + Add D8_6. + (IF4A, IF4B): Use "D7" instead of "D7S". + (IF4C, IF4D): Use "D8_7" instead of "D8". + (IF4E, IF4F): New. Use "D8_6". + (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for + sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. + + * v850-opc.c (insert_d16_15, extract_d16_15): New functions. + (v850_operands): Change D16 to D16_15, use special insert/extract + routines. New new D16 that uses the generic insert/extract code. + (IF7A, IF7B): Use D16_15. + (IF7C, IF7D): New. Use D16. + (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. + + * v850-opc.c (insert_d9, insert_d22): Slightly improve error + message. Issue an error if the branch offset is odd. + + * v850-opc.c: Add notes about needing special insert/extract + for all the load/store insns, except "ld.b" and "st.b". + + * v850-opc.c (insert_d22, extract_d22): New functions. + (v850_operands): Use insert_d22 and extract_d22 for + D22 operands. + (insert_d9): Fix range check. + +Fri Aug 30 18:01:02 1996 J.T. Conklin <jtc@hippo.cygnus.com> + + * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag + and set bits field to D9 and D22 operands. + +Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Define SR2 operand. + (v850_opcodes): "ldsr" uses R1,SR2. + + * v850-opc.c (v850_opcodes): Fix opcode specs for + sld.w, sst.b, sst.h, sst.w, and nop. + +Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add null opcode to mark the + end of the opcode table. + +Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (pre_defined_registers): Added register pairs, + "r0-r1", "r2-r3", etc. + +Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Make I16 be a signed operand. + Create I16U for an unsigned 16bit mmediate operand. + (v850_opcodes): Use I16U for "ori", "andi" and "xori". + + * v850-opc.c (v850_operands): Define EP operand. + (IF4A, IF4B, IF4C, IF4D): Use EP. + + * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" + with immediate operand, "movhi". Tweak "ldsr". + + * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] + correct. Get sld.[bhw] and sst.[bhw] closer. + + * v850-opc.c (v850_operands): "not" is a two byte insn + + * v850-opc.c (v850_opcodes): Correct bit pattern for setf. + + * v850-opc.c (v850_operands): D16 inserts at offset 16! + + * v850-opc.c (two): Get order of words correct. + + * v850-opc.c (v850_operands): I16 inserts at offset 16! + + * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system + register source and destination operands. + (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". + + * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix + same thinko in "trap" opcode. + + * v850-opc.c (v850_opcodes): Add initializer for size field + on all opcodes. + + * v850-opc.c (v850_operands): D6 -> DS7. References changed. + Add D8 for 8-bit unsigned field in short load/store insns. + (IF4A, IF4D): These both need two registers. + (IF4C, IF4D): Define. Use 8-bit unsigned field. + (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use + IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand + for "ldsr" and "stsr". + * v850-opc.c (v850_operands): 3-bit immediate for bit insns + is unsigned. + + * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and + short store word (sst.w). + +Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * v850-opc.c (v850_operands): Added insert and extract fields, + pointers to functions that handle unusual operand encodings. + +Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Enable "trap". + + * v850-opc.c (v850_opcodes): Fix order of displacement + and register for "set1", "clr1", "not1", and "tst1". + +Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Add "B3" support. + (v850_opcodes): Fix and enable "set1", "clr1", "not1" + and "tst1". + + * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. + + * v850-opc.c: Close unterminated comment. + +Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com> + + * v850-opc.c (v850_operands): Add flags field. + (v850_opcodes): add move opcodes. + +Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com> + + * Makefile.in (ALL_MACHINES): Add v850-opc.o. + * configure: (bfd_v850v_arch) Add new case. + * configure.in: (bfd_v850_arch) Add new case. + * v850-opc.c: New file. + +Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. + +Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c: Add additional information to the opcode + table to help determinine which instructions can be done + in parallel. + +Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-make.sed: Update editing of include pathnames to be + more general. + +Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> + + * arm-opc.h: Added "bx" instruction definition. + +Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> + + * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. + +Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. + +Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. + +Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: Update for alpha-opc changes. + +Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (print_insn_i386): Actually return the correct value. + (ONE, OP_ONE): #ifdef out; not used. + +Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. + Changed subi operand type to treat 0 as 16. + +Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose + <rose@netcom.com>. + +Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> + + * arm-opc.h: (arm_opcodes): Added halfword and sign-extension + memory transfer instructions. Add new format string entries %h and %s. + * arm-dis.c: (print_insn_arm): Provide decoding of the new + formats %h and %s. + +Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. + (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. + +Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com> + + * alpha-dis.c (print_insn_alpha_osf): Remove. + (print_insn_alpha_vms): Remove. + (print_insn_alpha): Make globally visible. Chose the register + names based on info->flavour. + * disassemble.c: Always return print_insn_alpha for the alpha. + +Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-dis.c (dis_long): Handle unknown opcodes. + +Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c: Changes to support signed and unsigned numbers. + All instructions with the same name that have long and short forms + now end in ".l" or ".s". Divs added. + * d10v-dis.c: Changes to support signed and unsigned numbers. + +Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-dis.c: Change all functions to use info->print_address_func. + +Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire + move ccr/sr insns more strict so that the disassembler only + selects them when the addressing mode is data register. + +Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + * d10v-opc.c (pre_defined_registers): Declare. + * d10v-dis.c (print_operand): Now uses pre_defined_registers + to pick a better name for the registers. + +Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix + operands for fexpand and fpmerge. From Christian Kuehnke + <Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>. + +Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> + + * alpha-dis.c (print_insn_alpha): No longer the user-visible + print routine. Take new regnames and cpumask arguments. + Kill the environment variable nonsense. + (print_insn_alpha_osf): New function. Do OSF/1 style regnames. + (print_insn_alpha_vms): New function. Do VMS style regnames. + * disassemble.c (disassembler): Test bfd flavour to pick + between OSF and VMS routines. Default to OSF. + +Thu Jul 18 17:19:34 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_SUBST (INSTALL_SHLIB). + * configure: Rebuild. + * Makefile.in (install): Use @INSTALL_SHLIB@. + +Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * configure: (bfd_d10v_arch) Add new case. + * configure.in: (bfd_d10v_arch) Add new case. + * d10v-dis.c: New file. + * d10v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d10v. + +Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating + to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. + +Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to + distinguish between variants of the instruction set. + * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to + distinguish between variants of the instruction set. + +Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c (print_insn_i8086): New routine to disassemble using + the 8086 instruction set. + * i386-dis.c: General cleanups. Make most things static. Add + prototypes. Get rid of static variables aflags and dflags. Pass + them as args (to almost everything). + +Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. + + * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". + + * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two + if the next arg is marked with SRC_IN_DST. Gross. + + * h8300-dis.c (bfd_h8_disassemble): Print "exr" when + we're looking for and find EXR. + + * h8300-dis.c (bfd_h8_disassemble): We don't have a match + if we're looking for KBIT and we don't find it. + + * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits + for L_3 and L_2. + + * h8300-dis.c (bfd_h8_disassemble): Don't set plen for + 3bit immediate operands. + +Tue Jul 9 10:55:20 1996 Ian Lance Taylor <ian@cygnus.com> + + * Released binutils 2.7. + + * alpha-opc.c: Add new case of "mov". From Klaus Kaempf + <kkaempf@progis.ac-net.de>. + +Thu Jul 4 11:42:51 1996 Ian Lance Taylor <ian@cygnus.com> + + * alpha-opc.c: Correct second case of "mov" to use OPRL. + +Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) + + * sparc-dis.c (print_insn_sparclite): New routine to print + sparclite instructions. + +Wed Jul 3 14:21:18 1996 J.T. Conklin <jtc@rtl.cygnus.com> + + * m68k-opc.c (m68k_opcodes): Add coldfire support. + +Fri Jun 28 15:53:51 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, + #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L + to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. + +Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): + Use autoconf-set values. + (docdir, oldincludedir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + +Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> + + * alpha-opc.c: New file. + * alpha-opc.h: Remove. + * alpha-dis.c: Complete rewrite to use new opcode table. + * configure.in: For bfd_alpha_arch, use alpha-opc.o. + * configure: Rebuild with autoconf 2.10. + * Makefile.in (ALL_MACHINES): Add alpha-opc.o. + (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not + alpha-opc.h. + (alpha-opc.o): New target. + +Wed Jun 19 15:55:12 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-dis.c (print_insn_sparc): Remove unused local variable i. + Set imm_added_to_rs1 even if the source and destination register + are not the same. + + * sparc-opc.c: Add some two operand forms of the wr instruction. + +Tue Jun 18 15:58:27 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument + to just "mode". + + * disassemble.c (disassembler): Handle H8/S. + * h8300-dis.c (print_insn_h8300s): New function for H8/S. + +Tue Jun 18 18:06:50 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: Add beq/teq as aliases for be/te. + + * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko + <sergei@msil.sps.mot.com>. + +Tue Jun 18 15:08:54 1996 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: New file. + + * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. + +Mon Jun 10 18:50:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, + regardless of plen. + +Tue Jun 4 09:15:53 1996 Doug Evans <dje@canuck.cygnus.com> + + * i386-dis.c (OP_OFF): Call append_prefix. + +Thu May 23 15:18:23 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (instruction encoding macros): Add explicit casts to + unsigned long to silence a warning from the Solaris PowerPC + compiler. + +Thu Apr 25 19:33:32 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. + +Mon Apr 22 17:12:35 1996 Doug Evans <dje@blues.cygnus.com> + + * sparc-dis.c (X_IMM,X_SIMM): New macros. + (X_IMM13): Delete. + (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. + * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, + Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, + cpush, cpusha, cpull sparclet insns. + +Wed Apr 17 14:20:22 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. + +Thu Apr 11 17:30:02 1996 Ian Lance Taylor <ian@cygnus.com> + + * sparc-opc.c: Set F_FBR on floating point branch instructions. + Set F_FLOAT on other floating point instructions. + +Mon Apr 8 17:02:48 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and + registers. + (powerpc_opcodes): Add 860/821 specific SPRs. + +Mon Apr 8 14:00:44 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Permit --enable-shared to specify a list of + directories. Set and substitute BFD_PICLIST. + * configure: Rebuild. + * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all + uses. Set to @BFD_PICLIST@. + +Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, + not "abs", which may be needed for the absolute in something + like btst #0,@10:8. Print L_3 immediates separately from other + immediates. Change ABSMOV reference to ABS8MEM. + +Wed Apr 3 10:40:45 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. + (current_arch_mask): New static global. + (compute_arch_mask): New static function. + (print_insn_sparc): Delete sparc_v9_p. New static local + current_mach. Resort opcode table if current_mach changes. + Generalize "insn not supported" test. + (compare_opcodes): Prefer supported opcodes to nonsupported ones. + Delete test for v9/!v9. + * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. + (v6notlet): Define. + (brfc): Split into CBR and FBR for coprocessor/fp branches. + (brfcx): Renamed to FBRX. + (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard + coprocessor mnemonics are not supported on the sparclet). + (condf): Renamed to CONDF. + (SLCBCC2): Delete F_ALIAS flag. + +Sat Mar 30 21:45:59 1996 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): rd must be 0 for + mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. + +Fri Mar 29 13:02:40 1996 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (config.status): Depend upon BFD VERSION file, so + that the shared library version number is set correctly. + +Tue Mar 26 15:47:14 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From + Miles Bader <miles@gnu.ai.mit.edu>. + * configure: Rebuild. + +Sat Mar 16 13:04:07 1996 Fred Fish <fnf@cygnus.com> + + * z8kgen.c (internal, gas): Call xmalloc rather than unchecked + malloc. + +Tue Mar 12 12:14:10 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure: Rebuild with autoconf 2.8. + +Thu Mar 7 15:11:10 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. + * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. + +Tue Mar 5 15:51:57 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Don't set SHLIB or SHLINK to an empty string, + since they appear as targets in Makefile.in. + * configure: Rebuild. + +Mon Feb 26 13:03:40 1996 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-make.sed: Edit out shared library support bits. + +Tue Feb 20 20:48:28 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. + (sparc_opcode_archs): Add MASK_V8 to sparclet entry. + (sparc_opcodes): Add sparclet insns. + (sparclet_cpreg_table): New static local. + (sparc_{encode,decode}_sparclet_cpreg): New functions. + * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. + +Tue Feb 20 11:02:44 1996 Alan Modra <alan@mullet.Levels.UniSA.Edu.Au> + + * i386-dis.c (index16): New static variable. + (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the + other way around. + (OP_indirE): Return result of OP_E. + (OP_E): Check for 16 bit addressing mode, and disassemble + correctly. Optimised 32 bit case a little. Don't print + "(base,index,scale)" when sib specifies only an offset. + +Mon Feb 19 12:32:17 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Set and substitute SHLIB_DEP. + * configure: Rebuild. + * Makefile.in (SHLIB_DEP): New variable. + (LIBIBERTY_LISTS, BFD_LIST): New variables. + (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If + COMMON_SHLIB, add them to piclist with appropriate modifications. + ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB + here: just use piclist. + +Mon Feb 19 02:03:50 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. + (print_insn_sparc): Rewrite v9/not-v9 tests. + (compare_opcodes): Likewise. + * sparc-opc.c (MASK_<ARCH>): Define. + (v6,v7,v8,sparclite,v9,v9a): Redefine. + (sparclet,v6notv9): Define. + (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. + (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. + +Thu Feb 15 14:45:05 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_PROG_CC before configure.host. + * configure: Rebuild. + + * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). + +Wed Feb 14 19:01:27 1996 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (onebyte_has_modrm): New static array. + (twobyte_has_modrm): New static array. + (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. + +Tue Feb 13 15:15:01 1996 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not + $(SHLINK). + +Mon Feb 12 16:26:06 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (PPC): Undef, so default defination on Windows NT + doesn't conflict. + +Wed Feb 7 13:59:54 1996 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on + m68010up, not just m68020up | cpu32. + + * Makefile.in (SONAME): New variable. + ($(SHLINK)): Make a link to the transformed name, as well. + (stamp-tshlink): New target. + (install): Skip stamp-tshlink during install. + +Tue Feb 6 12:28:54 1996 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_ARG_PROGRAM. + * configure: Rebuild. + * Makefile.in (program_transform_name): New variable. + (install): Transform library name before installing it. + +Mon Feb 5 16:14:42 1996 Ian Lance Taylor <ian@cygnus.com> + + * i960-dis.c (mem): Add HX dcinva instruction. + + Support for building as a shared library, based on patches from + Alan Modra <alan@spri.levels.unisa.edu.au>: + * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. + New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, + SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. + * configure: Rebuild. + * Makefile.in (ALLLIBS): New variable. + (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. + (COMMON_SHLIB, SHLINK): New variables. + (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. + (STAGESTUFF): Remove variable. + (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). + (stamp-piclist, piclist): New targets. + ($(SHLIB), $(SHLINK)): New targets. + ($(OFILES)): Depend upon stamp-picdir. + (disassemble.o): Build twice if PICFLAG is set. + (MOSTLYCLEAN): Add pic/*.o. + (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. + (distclean): Remove pic and stamp-picdir. + (install): Install shared libraries. + (stamp-picdir): New target. + +Fri Feb 2 17:15:25 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. + Print unknown instruction as "unknown", rather than in hex. + +Tue Jan 30 14:06:08 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-buf.c: Include "sysdep.h" before "dis-asm.h". + +Thu Jan 25 20:24:07 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. + +Thu Jan 25 11:56:49 1996 Ian Lance Taylor <ian@cygnus.com> + + * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte + when necessary. From Ulrich Drepper + <drepper@myware.rz.uni-karlsruhe.de>. + +Thu Jan 25 03:39:10 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with + sparc_num_opcodes. Update architecture enum values. + * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. + (sparc_opcode_lookup_arch): New function. + (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. + (sparc_opcodes): Add v9a shutdown insn. + +Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com> + + * sparc-dis.c (print_insn_sparc): Renamed from print_insn. + If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode + architecture. + (print_insn_sparc64): Deleted. + * disassemble.c (disassembler, case bfd_arch_sparc): Always use + print_insn_sparc. + + * sparc-opc.c (architecture_pname): Add v9a. + +Fri Jan 12 14:35:58 1996 David Mosberger-Tang <davidm@AZStarNet.com> + + * alpha-opc.h (alpha_insn_set): VAX floating point opcode was + incorrectly defined as 0x16 when it should be 0x15. + (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! + (alpha_insn_set): added cvtst and cvttq float ops. Also added + excb (exception barrier) which is defined in the Alpha + Architecture Handbook version 2. + * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for + OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be + disassembled as or, for example. + +Wed Jan 10 12:37:22 1996 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. + (_print_insn_mips): Change i from int to unsigned int. + +Thu Jan 4 17:21:10 1996 David Edelsohn <edelsohn@mhpcc.edu> + + * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different + from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. + +Thu Dec 28 13:29:19 1995 John Hassey <hassey@rtp.dg.com> + + * i386-dis.c: Added Pentium Pro instructions. + +Tue Dec 19 22:56:35 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to + being for Power2. + +Fri Dec 15 14:14:15 1995 J.T. Conklin <jtc@rtl.cygnus.com> + + * sh-opc.h (sh_nibble_type): Added REG_B. + (sh_arg_type): Added A_REG_B. + (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc + and stc.l opcodes. + * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. + +Fri Dec 15 16:44:31 1995 Ian Lance Taylor <ian@cygnus.com> + + * disassemble.c (disassembler): Use new bfd_big_endian macro. + +Tue Dec 12 12:22:24 1995 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (distclean): Remove stamp-h. From Ronald + F. Guilmette <rfg@monkeys.com>. + +Tue Dec 5 13:42:44 1995 Stan Shebs <shebs@andros.cygnus.com> + + From David Mosberger-Tang <davidm@azstarnet.com>: + * alpha-dis.c (print_insn_alpha): fixed decoding of cpys + instruction. + +Mon Dec 4 12:29:05 1995 J.T. Conklin <jtc@rtl.cygnus.com> + + * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. + (sh_table): Added many SH3 opcodes. + * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. + +Fri Dec 1 07:42:18 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. + (subco,subco.): Mark this PPC, not PPCCOM. + +Mon Nov 27 13:09:52 1995 Ian Lance Taylor <ian@cygnus.com> + + * configure: Rebuild with autoconf 2.7. + +Tue Nov 21 18:28:06 1995 Ian Lance Taylor <ian@cygnus.com> + + * configure: Rebuild with autoconf 2.6. + +Wed Nov 15 19:02:53 1995 Ken Raeburn <raeburn@cygnus.com> + + * configure.in: Sort list of architectures. Accept but do nothing + for alliant, convex, pyramid, romp, and tahoe. + +Wed Nov 8 20:18:59 1995 Ian Lance Taylor <ian@cygnus.com> + + * a29k-dis.c (print_special): Change num to unsigned int. + +Wed Nov 8 20:10:35 1995 Eric Freudenthal <freudenthal@nyu.edu> + + * a29k-dis.c (print_insn): Cast insn24 to unsigned long when + shifting it. + +Tue Nov 7 15:21:06 1995 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_CHECK_PROG to find and cache AR. + * configure: Rebuilt. + +Mon Nov 6 17:39:47 1995 Harry Dolan <dolan@ssd.intel.com> + + * configure.in: Add case for bfd_i860_arch. + * configure: Rebuild. + +Fri Nov 3 12:45:31 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. + * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. + (NEXTDOUBLE): Likewise. + (print_insn_m68k): Don't match fmoveml if there is more than one + register in the list. + (print_insn_arg): Handle a place of '8' for a type of 'L'. + +Thu Nov 2 23:06:33 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Use #W rather than #w. + * m68k-dis.c (print_insn_arg): Handle new 'W' place. + +Wed Nov 1 13:30:24 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, + and likewise for all the dbxx opcodes. + +Mon Oct 30 20:50:40 1995 Fred Fish <fnf@cygnus.com> + + * arc-dis.c: Include elf-bfd.h rather than libelf.h. + +Mon Oct 23 11:11:34 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> + + * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added + the VR4100 specific instructions to the mips_opcodes structure. + +Thu Oct 19 11:05:23 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-config.in, mpw-make.sed: Remove ugly workaround for + ugly Metrowerks bug in CW6, is fixed in CW7. + +Mon Oct 16 12:59:01 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (whole file): Add flags for common/any support. + +Tue Oct 10 11:06:07 1995 Fred Fish <fnf@cygnus.com> + + * Makefile.in (BISON): Remove macro. + (FLAGS_TO_PASS): Remove BISON. + +Fri Oct 6 16:26:45 1995 Ken Raeburn <raeburn@cygnus.com> + + Mon Sep 25 22:49:32 1995 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c (print_insn_m68k): Recognize all two-word + instructions that take no args by looking at the match mask. + (print_insn_arg): Always print "%" before register names. + [case 'c']: Use "nc" for the no-cache case, as recognized by gas. + [case '_']: Don't print "@#" before address. + [case 'J']: Use "%s" as format string, not register name. + [case 'B']: Treat place == 'C' like 'l' and 'L'. + +Thu Oct 5 22:16:20 1995 Ken Raeburn <raeburn@cygnus.com> + + * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode + name correctly. + +Tue Oct 3 08:30:20 1995 steve chamberlain <sac@slash.cygnus.com> + + From David Mosberger-Tang <davidm@azstarnet.com> + + * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. + (alpha_insn_set): added definitions for VAX floating point + instructions (Unix compilers don't generate these, but handcoded + assembly might still use them). + + * alpha-dis.c (print_insn_alpha): added support for disassembling + the miscellaneous instructions in the Alpha instruction set. + +Tue Sep 26 18:47:20 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, + no longer create sysdep.h, sed ppc-opc.c to work around a + serious Metrowerks C bug. + * mpw-make.in: Remove. + * mpw-make.sed: New file, used by mpw-configure to edit + Makefile.in into an MPW makefile. + +Wed Sep 20 12:55:28 1995 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Tue Sep 19 15:28:36 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Split pmove patterns which use 'P' into patterns + which use '0', '1', and '2' instead. Specify the proper size for + a pmove immediate operand. Correct the pmovefd patterns to be + moves to a register, not from a register. + * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. + +Thu Sep 14 11:58:22 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Mark all insns that reference + %psr, %wim, %tbr as F_NOTV9. + +Fri Sep 8 01:07:38 1995 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (Makefile): Just rebuild Makefile when running + config.status. + (config.h, stamp-h): New targets. + * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM + earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when + rebuilding config.h. + * configure: Rebuild. + + * mips-opc.c: Change unaligned loads and stores with "t,A" + operands to use "t,A(b)". + +Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-dis.c (print_insn_shx): Add F_FR0 support. + +Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate + until 3 instead of until 2. + +Wed Sep 6 21:21:33 1995 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.in (ALL_CFLAGS): Define. + (.c.o, disassemble.o): Use $(ALL_CFLAGS). + (MOSTLYCLEAN): Add config.log. + (distclean): Don't remove config.log. + * configure.in: Substitute HDEFINES. + * configure: Rebuild. + +Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-opc.h (sh_arg_type): Add F_FR0. + (sh_table, case fmac): Add F_FR0 as first argument. + +Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-opc.h (sh_opcode_info): Increase arg array size to 4. + +Tue Sep 5 18:28:10 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c: Remove all references to NO_V9. + +Tue Sep 5 20:03:26 1995 Ian Lance Taylor <ian@cygnus.com> + + * aclocal.m4: Just include ../bfd/aclocal.m4. + * configure: Rebuild. + +Tue Sep 5 16:09:59 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (X_DISP19): Define. + (print_insn, case 'G'): Use it. + (print_insn, case 'L'): Sign extend displacement. + +Mon Sep 4 14:28:46 1995 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Run ../bfd/configure.host before AC_PROG_CC. + Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute + host_makefile_frag or frags. + * aclocal.m4: New file. + * configure: Rebuild. + * Makefile.in (INSTALL): Set to @INSTALL@. + (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. + (INSTALL_DATA): Set to @INSTALL_DATA@. + (AR): Set to @AR@. + (AR_FLAGS): Set to rc rather than qc. + (CC): Define as @CC@. + (CFLAGS): Set to @CFLAGS@. + (@host_makefile_frag@): Remove. + (config.status): Remove dependency upon @frags@. + + * configure.in: ../bfd/config.bfd now just sets shell variables. + Use them rather than looking through target Makefile fragments. + * configure: Rebuild. + +Thu Aug 31 12:35:32 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. + +Wed Aug 30 13:52:28 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. + Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic + sparc64 insns. + + * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. + (lookup_{name,value}): New functions. + (prefetch_table): New static local. + (sparc_{encode,decode}_prefetch): New functions. + * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). + +Wed Aug 30 11:11:58 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-opc.h: Add blank lines to improve readabililty of sh3e + instructions. + +Wed Aug 30 11:09:38 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-dis.c: Correct comment on first line of file. + +Tue Aug 29 15:37:18 1995 Doug Evans <dje@canuck.cygnus.com> + + * disassemble.c (disassembler): Handle bfd_mach_sparc64. + + * sparc-opc.c (asi, membar): New static locals. + (sparc_{encode,decode}_{asi,membar}): New functions. + (sparc_opcodes, membar insn): Fix. + * sparc-dis.c (print_insn): Call sparc_decode_asi. + Support decoding of membar masks. + (X_MEMBAR): Define. + +Sat Aug 26 21:22:48 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. + +Mon Aug 21 17:33:36 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, + and likewise for the other branches. Add bhs as an alias for bcc, + and likewise for the size variants. Add dbhs as an alias for + dbcc. + +Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-opc.h (FP sts instructions): Update to match reality. + +Mon Aug 7 16:12:58 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-dis.c: (fpcr_names): Add % before all register names. + (reg_names): Likewise. + (print_insn_arg): Don't explicitly print % before register names. + Add % before register names in static array names. In case 'r', + print data registers as `@(Dn)', not `Dn@'. When printing a + memory address, don't print @# before it. + (print_indexed): Change base_disp and outer_disp from int to + bfd_vma. Print using MIT syntax, not mutant invalid Motorola + syntax. Sign extend 8 byte displacement correctly. + (print_base): Print using MIT syntax. Print zpc when appropriate. + Change parameter disp from int to bfd_vma. + + * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases + for jsr. + +Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, + F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. + * sh-opc.h (sh_arg_type): Add new operand types. + (sh_table): Add new opcodes from SH3E Floating Point ISA. + +Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> + + * Makefile.in (distclean): Remove generated file config.h. + +Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> + + * Makefile.in (distclean): Remove generated file config.h. + +Wed Aug 2 18:33:40 1995 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. + Clean up tables. + * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. + (opcode): Remove. + (print_insn_m68k): Change d to be const. Use m68k_numopcodes + rather than numopcodes. Use m68k_opcodes rather than removed + opcode function. Don't check F_ALIAS. + (print_insn_arg): Change first parameter to be const char *. + * Makefile.in (ALL_MACHINES): Add m68k-opc.o. + (m68k-opc.o): New target. + * configure.in: Build m68k-opc.o for bfd_m68k_arch. + * configure: Rebuild. + +Wed Aug 2 08:23:38 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. + (opcode_bits, opcode_hash_table): New variables. + (opcodes_initialized): Renamed from opcodes_sorted. + (build_hash_table): New function. + (is_delayed_branch): Use hash table. + (print_insn): Renamed from print_insn_sparc, made static. + Build and use hash table. If !sparc64, ignore sparc64 insns, + and vice-versa if sparc64. + (print_insn_sparc, print_insn_sparc64): New functions. + (compare_opcodes): Move sparc64 opcodes to end. + Print commutative insns with constant second. + * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. + +Tue Aug 1 00:12:49 1995 Ian Lance Taylor <ian@cygnus.com> + + * sh-dis.c (print_insn_shx): Remove unused local dslot. Use + print_address_func for A_BDISP12 and A_BDISP8. Correct test which + avoids printing a delay slot in a delay slot. + * sh-opc.h (sh_table): Fully bracket last entry. + +Mon Jul 31 12:04:47 1995 Doug Evans <dje@canuck.cygnus.com> + + * sparc-opc.c (sllx, srax, srlx): Fix disassembly. + +Wed Jul 12 00:59:34 1995 Ken Raeburn <raeburn@kr-pc.cygnus.com> + + * configure.in: Get host_makefile_frag from ${srcdir}. + + * configure.in: Autoconfiscated. Check for string[s].h. Create + config.h from config.in. Don't set up sysdep.h link. + * sysdep.h: New file. + * configure, config.in: New files, generated from configure.in. + * Makefile.in: Updated to be processed autoconf-style. + (distclean): Keep sysdep.h. Remove config.log and config.cache. + (Makefile): Depend on config.status. + (config.status): New rule. + * configure.bat: Update Makefile substitutions. + +Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com> + + * mips-opc.c (L1): Define. + (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, + addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, + and wb. + +Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu + if ISA 3 and addu otherwise, replacing or, since some MIPS chips + have multiple add units but only a single logical unit. + + * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, + shifted by 18, without any insertion or extraction function. + (insert_cr, extract_cr): Remove. + +Wed Jun 21 20:05:39 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before + register names. + +Thu Jun 15 17:23:31 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw-config.in: Add sh and i386 configs, remove sparc config. + * sh-opc.h: Add copyright. + +Mon Jun 5 03:30:43 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> + + * Makefile.in (crunch-m68k): Delete extra target accidentally + checked in a while ago. + +Wed May 24 16:22:13 1995 Jim Wilson <wilson@chestnut.cygnus.com> + + * sh-opc.h (sh_table): Add SH3 support. + +Wed May 24 14:16:08 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * sh-opc.h: Added bsrf and braf. + +Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete + bogus [ls]fm{ea,fd} patterns. + + * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. + * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and + initialize it from memory. Make function static. + (print_insn_{big,little}_arm): New functions. + * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for + the correct endianness. + +Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> + + * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from + enum list. + +Wed Apr 19 14:07:03 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * m68k-dis.c (opcode): Finish change made by Kung Hsu on April + 17th, so that it builds again using GCC as the compiler. + +Tue Apr 18 12:14:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * mips-dis.c (print_insn_little_mips): Cast return value from + bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips + expects an unsigned long, and that might be fewer words of + argument storage (e.g., if bfd_vma is long long on a 32-bit + machine). + (print_insn_big_mips): Likewise with bfd_getb32 value. + (_print_insn_mips): Now static. + +Mon Apr 17 12:23:28 1995 Kung Hsu <kung@rtl.cygnus.com> + + * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because + gcc memory hog problem with initializer is fixed. + +Mon Apr 10 15:55:01 1995 Stan Shebs <shebs@andros.cygnus.com> + + Merge in support for Mac MPW as a host. + (Old change descriptions retained for informational value.) + + * mpw-config.in (archname): Compute from the config. + (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. + + * mpw-config.in (target_arch): Compute from canonical target. + (m68k, mips, powerpc, sparc): Add architectures. + * mpw-make.in (disassemble.c.o): Add. + (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). + + * mpw-config.in (BFD_MACHINES): Set to a default value. + * mpw-make.in (BFD_MACHINES): Remove wired-in value. + + * mpw-make.in (CSEARCH): Add extra-include to search path. + + * mpw-config.in (varargs.h): Don't create. + (sysdep.h): Create using forward-include. + * mpw-make.in (CSEARCH): Add include/mpw to search path. + + * mpw-config.in: New file, MPW version of configure.in. + * mpw-make.in: New file, MPW version of Makefile.in. + +Fri Mar 31 14:23:38 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * alpha-dis.c (print_insn_alpha): Put empty statement after + default label. + +Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. + (low_sign_extend): Likewise. + (get_field): Delete unused function. + (set_field, deposit_14, deposit_21): Likewise. + +Fri Mar 17 15:55:53 1995 J.T. Conklin <jtc@rtl.cygnus.com> + + * i386-dis.c: Support for more pentium opcodes. From Guy Harris + (guy@netapp.com). + +Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) + + * alpha-opc.h (OSF_ASMCODE): define + print pal-code names as defined in App C of the + Alpha Architecture Reference Manual + + * alpha-dis.c: cleaned up output + print stylized code forms as defined in App A.4.3 of the + Alpha Architecture Reference Manual + +Wed Mar 8 15:21:14 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for + `rfe'. + * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', + 'N', and 'M'. + +Wed Mar 8 02:54:05 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * m68k-dis.c (opcode): New function. Returns address of opcode + table entry given index, even if the opcode table was split to + work around gcc bugs. + (print_insn_m68k): Call opcode instead of referencing m68k_opcodes + directly. + (BREAK_UP_BIG_DECL): Make secondary array static and const. + (reg_names): Now const. + (print_insn_arg): Arrays cacheFieldName and names now const. + (print_indexed): Array scales now const. + +Tue Mar 7 16:41:21 1995 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c: Sort recently added instructions by minor opcode + number within major opcode number. + +Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c: Include libhppa.h. + +Fri Feb 24 19:15:36 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Change dli to use M_DLI, and add dla. + +Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add w65-dis.o. + +Thu Feb 16 17:34:41 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add r4650 mul instruction. + +Wed Feb 15 15:45:20 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c: Add uld and usd macros for unaligned double load and + store. + +Tue Feb 14 13:17:37 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, + mfdcr, mtdcr, icbt, iccci. + +Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com> + + * i960-dis.c (struct tabent, struct sparse_tabent): Change the + signed char fields to shorts, more portable. + +Wed Feb 8 17:29:29 1995 Stan Shebs <shebs@andros.cygnus.com> + + * i960-dis.c (struct tabent, struct sparse_tabent): Declare the + char fields as signed chars, since they may have negative values. + +Mon Feb 6 10:52:06 1995 J.T. Conklin <jtc@rtl.cygnus.com> + + * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum + (mycroft@netbsd.org). + +Mon Jan 30 12:38:00 1995 Ian Lance Taylor <ian@cygnus.com> + + From "Logg, Ed" <elogg@ea.com>: + * ppc-opc.c (extract_bdm): Correct parenthezisation. + * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized + value. + +Thu Jan 26 18:32:08 1995 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c: Changes based on patch from David Edelsohn + <edelsohn@mhpcc.edu>. + (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of + SPR. + (FXM_MASK): Define. + (insert_tbr): New static function. + (extract_tbr): New static function. + (XFXFXM_MASK, XFXM): Define. + (XSPRBAT_MASK, XSPRG_MASK): Define. + (powerpc_opcodes): Add instructions to access special registers by + name. Add mtcr and mftbu. + +Tue Jan 17 10:56:43 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * mips-opc.c (P3): Define. + (mips_opcodes): Add mad and madu. + +Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat> + + * configure.in: Add W65 support. + * disassemble.c: Likewise. + * w65-opc.h, w65-dis.c: New files. + +Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit + immediates. + +Tue Dec 20 11:25:12 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * mips-opc.c: Add dli as a synonym for li. + +Thu Dec 8 18:23:31 1994 Ken Raeburn <raeburn@cujo.cygnus.com> + + * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and + print something for reserved opcode values, even if it won't + assemble again. + + * mips-dis.c (_print_insn_mips): When initializing, shift right + and mask, to avoid sign extension problems on the Alpha. + + * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr + control registers. + +Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh-opc.h (mov.l gbr): Get direction right. + * sh-dis.c (print_insn_shx): New function. + (print_insn_shl, print_insn_sh): Call print_insn_shx to + print opcodes with right byte order. + +Thu Nov 3 19:32:22 1994 Ken Raeburn <raeburn@cujo.cygnus.com> + + * ns32k-dis.c (struct ns32k_option): Renamed from struct option, + to avoid conflicts with getopt. + +Mon Oct 31 18:48:10 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * hppa-dis.c (print_insn_hppa): Read the instruction using + bfd_getb32, so that it works on a little endian or 64 bit host. + Remove unused local variable op. + +Tue Oct 25 17:07:57 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * mips-opc.c: Use or instead of addu for pseudo-op move, since + addu does not work correctly if -mips3. + +Wed Oct 19 13:40:16 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * a29k-dis.c (print_special): Add special register names defined + on 29030, 29040 and 29050. + (print_insn): Handle new operand type 'I'. + +Wed Oct 12 11:59:55 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * Makefile.in (INSTALL): Use top level install.sh script. + +Wed Oct 5 19:16:29 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * sparc-dis.c: Rewrite to use bitfields, rather than a union, so + that it works on a little endian host. + +Tue Oct 4 12:14:21 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * configure.in: Use ${config_shell} when running config.bfd. + +Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. + +Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * a29k-dis.c (print_insn): Print the opcode. + +Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. + +Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. + +Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions + which store a value into memory. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * configure.in, Makefile.in, disassemble.c: Add support for the ARM. + * arm-dis.c, arm-opc.h: New files. + +Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) + + * Makefile.in (ns32k-dis.o): Add dependency. + * ns32k-dis.c (print_insn_arg): Declare initialized local as + string, not as array of chars. + +Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. + + * sparc-opc.c: Added sparclite extended FP operations, and + versions of v9 impdep* instructions permitting specification of + the OPF field. + +Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960-dis.c (reg_names): Now const. + (struct sparse_tabent): New type, copied from array type in mem + function. + (ctrl): Local static array ctrl_tab now const. + (cobr): Local static array cobr_tab now const. + (mem): Local variables reg1, reg2, reg3 now point to const. Local + static variable mem_tab no longer explicitly initialized. Changed + mem_init to const array of struct sparse_tabent. + (reg): Local static variable reg_tab no longer explicitly + initialized. Changed reg_init to const array of struct + sparse_tabent. + (ea): Local static array scale_tab now const. + + * i960-dis.c (reg): Added i960JX instructions to reg_init table. + (REG_MAX): Updated. + +Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: the disassember needs to be enabled for + "objdump -d" to work in djgpp. + +Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * ns32k-dis.c: Deleted all code in "#ifdef GDB". + (invalid_float): Enabled general version, doesn't require running + on ns32k host. Changed to take char* argument, and test for + explicitly specified sizes, instead of using sizeof() on host CPU + types. + (INVALID_FLOAT): Cast first argument. + (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, + list_P032, list_M032): Now const. + (optlist, list_search): Made appropriate arguments now point to + const. + (print_insn_arg): Changed static array of one-character-string + pointers into a static const array of characters; fixed sprintf + statement accordingly. + +Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped + from distribution. A ns32k-dis.c from a previous distribution has + been brought up to date and supports the new interface. + + * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. + + * configure.in: add bfd_ns32k_arch target support. + + * Makefile.in: add ns32k-dis.o to ALL_MACHINES. + Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. + +Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch + disassembly right. + +Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) + + * h8300-dis.c, mips-dis.c: Don't use true and false. + +Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) + + * configure.in: Change --with-targets to --enable-targets. + +Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-dis.c (_print_insn_mips): Build a static hash table mapping + opcodes to the first instruction with that opcode, to speed + disassembly of large files. From ralphc@pyramid.com (Ralph + Campbell). + +Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * Makefile.in (mostlyclean): Fix typo (was mostyclean). + +Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: update to latest makefile.in + +Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) + + * a29k-dis.c (print_insn): Print 'x' type operand in hex. + * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. + * sh-dis.c (print_insn_sh): Don't recur endlessly if delay + slot insn is in a delay slot. + * z8k-opc.h: (resflg): Fix patterns. + * h8500-opc.h Fix CR insn patterns. + +Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and + "cmpl" before POWER versions, so that gas -many uses them. + +Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * disassemble.c: New file. + * Makefile.in (OFILES): Add disassemble.o. + (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). + * configure.in: Define ARCHDEFS in Makefile. Code taken from + binutils/configure.in. + + * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the + opcode being examined. + +Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. + (insert_ral, insert_ram, insert_ras): New functions. + (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and + RAS for store with update. + +Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn + (edelsohn@npac.syr.edu). + +Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (mips_opcodes): Correct operands of "nor" with an + immediate argument. + +Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) + + * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". + +Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): The signedp field has been + removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag + instead. Add new operand SISIGNOPT. + (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. + Based on patch from David Edelsohn (edelsohn@npac.syr.edu). + * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather + than signedp field. + +Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * i386-dis.c (struct private): Renamed to dis_private. `private' + is a reserved word for dynix cc. + +Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Change error message to refer to bfd/config.bfd + rather than bfd/configure.in. + +Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) + + * ppc-opc.c: Define POWER2 as short alias flag. + (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and + fsqrt. + +Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Don't read a second word for + opcodes 0, 1, 2 and 3. + +Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. + +Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68881-ext.c: Removed; no longer used. + * Makefile.in: Changed accordingly. + + * m68k-dis.c (ext_format_68881): Don't declare. + (print_insn_m68k): If an instruction uses place 'i', it uses at + least four fixed bytes. + (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For + extended float, convert to double using floatformat_to_double, not + ieee_extended_to_double, and fetch the data before converting it. + +Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: It's sqrt.s, not sqrt.w. From + davidj@ICSI.Berkeley.EDU (David Johnson). + +Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the + PowerPC uses bdnz[l][a]. + +Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * dis-buf.c, i386-dis.c: Include sysdep.h. + +Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. + + * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported + by Motorola PowerPC 601 with PPC_OPCODE_601. + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): + Disassemble Motorola PowerPC 601 instructions as well as normal + PowerPC instructions. + +Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * i960-dis.c (reg, mem): Just use a static array instead of + calling xmalloc. + +Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the + condition name index if this is for a negated condition. + + * hppa-dis.c (print_insn_hppa): No space before 'H' operand. + Floating point format for 'H' operand is backwards from normal + case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' + operands (fmpyadd and fmpysub), handle bizarre register + translation correctly for single precision format. + + * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' + or 'I' operands if the next format specifier is 'M' (fcmp + condition completer). + +Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): New operand type MBE to handle a + single number giving a bitmask for the MB and ME fields of an M + form instruction. Change NB to accept 32, and turn it into 0; + also turn 0 into 32 when disassembling. Seperated SH from NB. + (insert_mbe, extract_mbe): New functions. + (insert_nb, extract_nb): New functions. + (SC_MASK): Mask out SA and LK bits. + (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, + RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark + "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", + "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", + "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to + use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. + (powerpc_macros): Define table of macro definitions. + (powerpc_num_macros): Define. + + * ppc-dis.c (print_insn_powerpc): Don't skip optional operands + if PPC_OPERAND_NEXT is set. + +Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of + char. Retrieve contents using bfd_getl32 instead of shifting. + +Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c: New file. Opcode table for PowerPC, including + opcodes for POWER (RS/6000). + * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. + * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. + (CFILES): Add ppc-dis.c. + (ppc-dis.o, ppc-opc.o): New targets. + * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. + +Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. + No space before 'u', 'f', or 'N'. + +Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading + farther than we should. + + * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. + +Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. + +Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * i960-dis.c (print_insn_i960): Only read word2 if the instruction + needs it, to prevent reading past the end of a section. + +Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.h: Use macro for j instruction, to support SVR4 PIC. + Removed t,A case for la; always use t,A(b) case. + +Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + From Ted Lemen <mellon@pepper.ncd.com> + * mips-dis.c (print_insn_arg): Handle 'k'. + * mips-opc.c: Make cache use k, not t. + +Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add + FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct + FLOAT_FORMAT_CODE to put out floating point register names. + +Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. + +Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. + +Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts + larger than 32. Moved dsxx32 variants first for disassembler. + +Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8kgen.c, z8k-opc.h: Add full lda information. + +Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Do not emit a space after + movb instructions. Any necessary space will be emitted by + the code to handle nullification completers. + +Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Moved l.d down so that it disassembles as ldc1. + +Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h: Add ldl_l, fix typo for ldq_u. + * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. + +Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Correct lwu opcode value (book had it wrong). + +Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8k-dis.c (FETCH_DATA): get just the right amount of data. + (unpack_instr): Cope with ARG_IMM4M1 type instructions. + +Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k-dis.c (m88kdis): comment change. Remove space after + printing mnemonic. + (printop): handle new arg types DEC and XREG for m88110. + +Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'z' operand + type for absolute branch addresses. Delete special + "ble" and "be" code in 'W' operand code. + +Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set hazard information correctly for branch + likely instructions. + +Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use + info->fprintf_func for printing and info->print_address_func for + address output. + +Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set INSN_TRAP for tXX instructions. + +Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): + Corrected second case of "b" for disassembler. + +Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls + to BFD swapping routines to correspond to BFD name changes. + +Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Change div machine instruction to be z,s,t rather + than s,t. Change div macro to be d,v,t rather than d,s,t. + Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, + rem and remu which generates only the corresponding div + instruction. This is for compatibility with the MIPS assembler, + which only generates the simple machine instruction when an + explicit destination of $0 is used. + * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). + +Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set + WR_31 hazard for bal, bgezal, bltzal. + +Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use print function + from within the disassemble_info, not fprintf_filtered. + +Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff + Law, law@cs.utah.edu.) + +Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c ("absu"): Removed. + ("dabs"): Added. + +Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added r6000 and r4000 instructions and macros. + Changed hazard information to distinguish between memory load + delays and coprocessor load delays. + +Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. + +Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * configure.in: Don't pass cpu to config.bfd. + +Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c (m88kdis): Make class unsigned. + +Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha-dis.c (print_insn_alpha): One branch format case was + missing the instruction name. + +Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. + Add the arch-specific auxiliary files. + (OFILES): Remove the arch-specific auxiliary files + and use BFD_MACHINES instead of DIS_LIBS. + * configure.in: Set BFD_MACHINES based on --with-targets option. + +Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly + for swc1. + +Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-opc.c: Change CONST to const to deal with gcc + -Dconst=__const -traditional. + +Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took + coprocessor instructions out of #if 0, and made them use new + argument type "C". + +Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. + +Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) + + * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch + instruction, for use by the disassembler. + + * sparc-dis.c (SEX): Add sign extension macro. Replace many + hand-coded sign extensions that depended on 32-bit host ints. + FIXME, we still depend on big-endian host bitfield ordering. + (sparc_print_insn): Set the insn_info_valid field, and the + other fields that describe the instruction being printed. + +Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) + + * sparc-opc.c (call): Accept all 6 addressing modes valid for + `jmp' instead of just one of them. + +Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. + (fput_fp_reg_r): Renamed from fput_reg_r. + (fput_fp_reg): New function. + (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. + + * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. + + * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. + +Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. + + * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', + don't output a space. + + * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. + +Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * mips-opc.c: New file, containing opcode table from + ../include/opcode/mips.h. + * Makefile.in: Add it. + +Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c: New file, moved in from gdb and changed to use the + new dis-asm.h disassembler interface. + * Makefile.in (DIS_LIBS): Added m88k-dis.o. + (m88k-dis.o): New target. + +Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to + argument string const char * to correspond to opcode/mips.h. + +Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c: Updated to account for name changes in new version + of opcode/mips.h. + * Makefile.in: Added header file dependencies. + +Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. + +Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign + extend, rather than shifts. + +Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * Makefile.in: Undo 15 June change. + +Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) + + * m68k-dis.c (print_insn_arg): Change return value to byte count + or error code. + * m68k-dis.c: Re-write to detect invalid operands before + printing anything, so we can handle this the same way we + handle invalid opcodes. + +Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * sh-dis.c, sh-opc.h: Understand some more opcodes. + +Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) + + * hppa-dis.c: Include <ansidecl.h> and sysdep.h before other + header files. + +Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * sparc-dis.c: Don't declare qsort, since sysdep.h might. + + * configure.in: Do make sysdep.h link. + * Makefile.in: Search ../include. Don't search ../bfd. + +Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. + Do not print a space before the completers specified by + 'a' and 'd'. + +Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) + + * mips-dis.c: No longer need to bomb out if HOST_64_BIT is + defined, since gdb has been fixed. + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, + fput_reg_r, fput_creg, fput_const, and fputs_filtered should + be a *disassemble_info, not a *FILE. + * hppa-dis.c: Support 'd', '!', and 'a'. + * hppa-dis.c: Support 's' to extract a 2 bit space register. + * hppa-dis.c: Delete cases which are no longer needed. + +Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) + + * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. + +Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with + H8/300-H opcodes. + +Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. + * configure.in: No longer need to configure to get sysdep.h. + +Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) + + * Patches from Jeffrey Law <law@cs.utah.edu>. + * hppa-dis.c: Support 'I', 'J', and 'K' in output + templates for 1.1 FP computational instructions. + +Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Address argument is type + bfd_vma. + * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): + Ditto. + + * h8500-opc.h (addr_class_type): No comma at end of enumerator. + * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. + + * sparc-dis.c (compare_opcodes): Move static declaration to + top-level. + +Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp + instruction, remove unimp hack from 'l' argument. + +Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) + + * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's + happy. + +Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) + + * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): + * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor + instructions. + +Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some + arrays of string pointers to 2-d arrays of chars, to save + space. + +Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) + + * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: + Cast second arg to read_memory_func to "bfd_byte *", as necessary. + +Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: New file from Utah, adapted to new disassembler + calling interface. + * Makefile.in: Include it. + +Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * sh-dis.c, sh-opc.h: New files. + +Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha-dis.c, alpha-opc.h: New files. + +Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed + value. + +Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) + + * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. + +Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than + const. + +Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) + + * sparc-dis.c: Use fprintf_func a few places where I forgot, + and double percent signs a few places. + + * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. + + * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: + Use info->print_address_func not print_address. + + * dis-buf.c (generic_print_address): New function. + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add sparc-dis.c. + sparc-dis.c: New file, merges binutils and gdb versions as follows: + From GDB: + Add `add' instruction to the set that get checked + for a preceding `sethi' in order to print an absolute address. + * (print_insn): Disassembly prefers real instructions. + (is_delayed_branch): Speed up. + * sparc-opcode.h: Add ALIAS bit to aliases. Fix up opcode tables. + Still missing some float ops, and needs testing. + * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by + F_ALIAS. Use printf, not fprintf, when not passing a file + pointer... + (compare_opcodes): Check that identical instructions have + identical opcodes, complain otherwise. + From binutils: + * New 'm' arg. + * Include reg_names. + From neither: + Use dis-asm.h/read_memory_func interface. + +Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) + + * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): + deliberately return non-zero to setjmp from longjmp. Otherwise + this code fails to compile. + +Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) + + * m68k-dis.c: Fix prototype for fetch_arg(). + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-buf.c: New file, for new read_memory_func interface. + Makefile.in (OFILES): Include it. + m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: + Use new read_memory_func interface. + +Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. + * h8500-opc.h: Fix couple of opcodes. + +Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: add dvi & installcheck targets + +Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) + + * Makefile.in: Update for h8500-dis.c. + +Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c, h8500-opc.h: New files + +Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) + + * mips-dis.c, z8k-dis.c: Converted to use interface defined in + ../include/dis-asm.h. + * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c + and ../gdb/m68k-pinsn.c). + * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c + and ../gdb/i386-pinsn.c). + * m68881-ext.c: New file. Moved definition of + ext_format ext_format_68881 from ../gdb/m68k-tdep.c. + * Makefile.in: Adjust for new files. + * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). + * m68k-dis.c: Recognize '9' placement code, so (say) pflush + can be dis-assembled. + +Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * mips-dis.c (print_insn_arg): Now returns void. + +Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) + + * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h + files that use the macros. + +Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c: New file, from gdb/mips-pinsn.c. + * Makefile.in (DIS_LIBS): Added mips-dis.o. + (CFILES): Added mips-dis.c. + +Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines + * z8kgen.c, z8k-opc.h: fix sizes of some shifts. + +Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in: Improve *clean rules. + * configure.in: Allow a default host. + +Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep + files include other sysdep files + +Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint + +Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) + + * configure.in: For host support, use ../bfd/configure.host + so it stays in sync with the ../bfd/hosts database. + +Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use cpu-vendor-os triple instead of nested cases + +Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c (unparse_instr): fix bug where opcode returned was + *always* the wrong one. + +Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8kgen.c: added copyright info + +Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (unparse_instr): prettier tabs + * z8kgen.c -> z8k-opc.h: bug fixes in tables + +Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) + + * configure.in: Add ncr* configuration. + * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make + picayune ANSI compilers happy. + +Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) + + * configure.in (i386): Make i386 and i486 synonymous for now. + * configure.in (i[34]86-*-sysv4): Add my_host definition. + +Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Fix typo. + +Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (make): Remove obsolete crud. + (sparc-opc.o): Avoid Sun Make VPATH bug. + +Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * Makefile.in: since there are no SUBDIRS, remove rule and + references of subdir_do. + +Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Get the library name right here too. + Don't install bfd.h, since it's unrelated to this library. No + subdirs to recurse into, either. + (CFILES): The source file has a .c suffix, not .o. + + * sparc-opc.c: New file, moved from BFD. + * Makefile.in (OFILES): Build it. + +Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c: fixed forward refferences of some declarations. + +Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) + + * Makefile.in: get the name of the library right + +Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c: knows how to disassemble z8k stuff + * z8k-opc.h: new file full of z8000 opcodes + + +Local Variables: +version-control: never +End: diff --git a/gnu/usr.bin/binutils/opcodes/ChangeLog-9899 b/gnu/usr.bin/binutils/opcodes/ChangeLog-9899 new file mode 100644 index 00000000000..8588f0a9f72 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ChangeLog-9899 @@ -0,0 +1,1669 @@ +1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall". + +Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c, m10300-dis.c: Add am33 support. + +Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names. + (print_insn_hppa): Handle 'B' operand. + +1999-11-22 Nick Clifton <nickc@cygnus.com> + + * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction. + +1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-opc.c (I5): New. + (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s + madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, + pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New. + +Mon Nov 15 19:34:58 1999 Donald Lindsay <dlindsay@cygnus.com> + + * arm-dis.c (print_insn_arm): Added general purpose 'X' format. + * arm-opc.h (print_insn_arm): Added comment documenting + the 'X' format just added to arm-dis.c. + +1999-11-15 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-opc.c (la): Create a version that just uses addiu directly. + (dla): Expand to daddiu if possible. + +1999-11-11 Nick Clifton <nickc@cygnus.com> + + * mips-opc.c: Add ssnop pattern. + +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. + +1999-10-29 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA + (d30v_format_tab): Define the SHORT_AR format. + +1999-10-28 Nick Clifton <nickc@cygnus.com> + + * mcore-dis.c: Remove spurious code introduced in previous delta. + +1999-10-27 Scott Bambrough <scottb@netwinder.org> + + * arm-dis.c: Include sysdep.h to prevent compile time warnings. + +1999-10-18 Michael Meissner <meissner@cygnus.com> + + * alpha-opc.c (alpha_operands): Fill in missing initializer. + (alpha_num_operands): Convert to unsigned. + (alpha_num_opcodes): Ditto. + (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED. + (insert_rca): Ditto. + (insert_za): Ditto. + (insert_zb): Ditto. + (insert_zc): Ditto. + (extract_bdisp): Ditto. + (extract_jhint): Ditto. + (extract_ev6hwjhint): Ditto. + +Sun Oct 10 01:48:01 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> + + * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC', + 'co', '@'. + + * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'. + + * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q". + +Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for + rac/rachi instructions. + (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi, + slae, st and st2w. + +1999-10-04 Doug Evans <devans@casey.cygnus.com> + + * fr30-asm.c,fr30-desc.h: Rebuild. + * m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild. Add m32rx support. + * m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto. + +1999-09-29 Nick Clifton <nickc@cygnus.com> + + * sh-opc.h: Fix bit patterns for several load and store + instructions. + +Thu Sep 23 08:27:20 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org + + * hppa-dis.c (print_insn_hppa): Replace 'B', 'M', 'g' and 'l' with + cleaner code using completer prefixes. Add 'Y'. + +Sun Sep 19 10:41:27 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c: (print_insn_hppa): Correct 'cJ', 'cc'. + + * hppa-dis.c (extract_22): New function. + + * hppa-dis.c (print_insn_hppa): Handle 'J', 'K', and 'cc'. + + * hppa-dis.c (print_insn_hppa): Handle 'fe' and 'cJ'. + + * hppa-dis.c (print_insn_hppa): Handle '#', 'd', and 'cq'. + + * hppa-dis.c (print_insn_hppa): Handle 'm', 'h', '='. + + * hppa-dis.c (print_insn_hppa): Handle 'X' operand. + + * hppa-dis.c (print_insn_hppa): Handle 'B' operand. + + * hppa-dis.c (print_insn_hppa): Handle 'M' and 'L' operands. + + * hppa-dis.c (print_insn_hppa): Handle 'l' operand. + + * hppa-dis.c (print_insn_hppa): Handle 'g' operand. + +Sat Sep 18 11:36:12 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa): Output a space after 'X' completer. + + * hppa-dis.c: (print_insn_hppa): Do output a space before a 'v' + operand. + + * hppa-dis.c: (print_insn_hppa): Handle 'fX'. + + * hppa-dis.c: (print_insn_hppa): Add missing break after + FP register case. + + * hppa-dis.c: Finish constifying various completers, register + names, etc etc. + +1999-09-14 Michael Meissner <meissner@cygnus.com> + + * configure.in (Canonicalization of target names): Remove adding + ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14 + generates $ac_config_sub with a ${CONFIG_SHELL} already. + * configure: Regenerate. + +Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa): Escape '%' in output strings. + + * hppa-dis.c (print_insn_hppa): Handle 'Z' argument. + +1999-09-07 Nick Clifton <nickc@cygnus.com> + + * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct + names for the mulu and muls patterns. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj-opc.c: New file. + * pj-dis.c: New file. + * disassemble.c (disassembler): Handle bfd_arch_pj. + * configure.in: Handle bfd_pj_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add pj-dis.c and pj-opc.c. + (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo. + * configure, Makefile.in: Rebuild. + +1999-09-04 H.J. Lu <hjl@gnu.org> + + * i386-dis.c (print_insn_i386): Set bytes_per_line to 7. + +Mon Aug 30 18:56:14 1999 Richard Henderson <rth@cygnus.com> + + * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31. + +1999-08-04 Doug Evans <devans@casey.cygnus.com> + + * fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. + * m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float + register args by 'f'. + + * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |. + + * hppa-dis.c (MASK_10, read_write_names, add_compl_names, + extract_10U_store): New. + (print_insn_hppa): Add new completers. + + * hppa-dis.c (signed_unsigned_names,mix_half_names, + saturation_names): New. + (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'. + + * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. + + * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!' + + * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits + to decide to print a space. + +1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c: Add AMD athlon instruction support. + +1999-08-10 Ian Lance Taylor <ian@zembu.com> + + From Wally Iimura <iimura@microunity.com>: + * dis-buf.c (buffer_read_memory): Rewrite expression to avoid + overflow at end of address space. + (generic_print_address): Use sprintf_vma. + +1999-08-08 Ian Lance Taylor <ian@zembu.com> + + * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to + MKDEP. Rebuild dependencies. + * Makefile.in: Rebuild. + +Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names, + add_cond_64_names, wide_add_cond_names, logical_cond_64_names, + unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New. + (print_insn_hppa): Add 64 bit condition completers. + +Thu Aug 5 16:59:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa-dis.c (print_insn_hppa): Change condition args to use + '?' prefix. + +Wed Jul 28 04:33:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E' + code. + +1999-07-21 Ian Lance Taylor <ian@zembu.com> + + From Mark Elbrecht: + * configure.bat: Remove; obsolete. + +1999-07-11 Ian Lance Taylor <ian@zembu.com> + + * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate. + (generic_strcat_address): Add cast to avoid warning. + * i386-dis.c: Initialize all structure fields to avoid warnings. + Add ATTRIBUTE_UNUSED as appropriate. + +1999-07-08 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc-dis.c (print_insn_sparc): Differentiate between + addition and oring when guessing symbol for comment. + +1999-07-05 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_arm): Display hex equivalent of rotated + constant. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c: Mention intel mode specials in macro char comment. + +1999-06-21 Ian Lance Taylor <ian@zembu.com> + + * alpha-dis.c: Don't include <stdlib.h>. + * arm-dis.c: Include "sysdep.h". + * tic30-dis.c: Don't include <stdlib.h> or <string.h>. Include + "sysdep.h". + * Makefile.am: Rebuild dependencies. + * Makefile.in: Rebuild. + +1999-06-16 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange + SWIs. + +1999-06-14 Nick Clifton <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com> + + * arm-dis.c (arm_regnames): Turn into a pointer to a register + name set. + (arm_regnames_standard): New variable: Array of ARM register + names according to ARM instruction set nomenclature. + (arm_regnames_apcs): New variable: Array of ARM register names + according to ARM Procedure Call Standard. + (arm_regnames_raw): New variable: Array of ARM register names + using just 'r' and the register number. + (arm_toggle_regnames): New function: Toggle the chosen register set + naming scheme. + (parse_disassembler_options): New function: Parse any target + disassembler command line options. + (print_insn_big_arm): Call parse_disassembler_options if any + are defined. + (print_insn_little_arm): Call parse_disassembler_options if any + are defined. + +1999-06-13 Ian Lance Taylor <ian@zembu.com> + + * i386-dis.c (FWAIT_OPCODE): Define. + (used_prefixes): New static variable. + (fetch_data): Don't print an error message if we have already + fetched some bytes successfully. + (ckprefix): Clear used_prefixes. Use FWAIT_OPCODE, not 0x9b. + (prefix_name): New static function. + (print_insn_i386): If setjmp fails, indicating a data error, but + we have managed to fetch some bytes, print the first one as a + prefix or a .byte pseudo-op. If fwait is followed by a non + floating point instruction, print the first prefix. Set + used_prefixes when prefixes are used. If any prefixes were not + used after disassembling the instruction, print the first prefix + instead of printing the instruction. + (putop): Set used_prefixes when prefixes are used. + (append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise. + (OP_DIR, OP_SIMD_Suffix): Likewise. + +1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc-opc.c: Fix up set, setsw, setuw operand kinds. + Support signx %reg, clruw %reg. + +1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc-opc.c: Add aliases Solaris as supports. + +Mon Jun 7 12:04:52 1999 Andreas Schwab <schwab@issan.cs.uni-dortmund.de> + + * Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c. + * Makefile.in: Regenerated. + +1999-06-03 Philip Blundell <philb@gnu.org> + + * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR + when target is PC-relative. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k-opc.c: Rename MACL/MSACL to MAC/MSAC. Add MACM/MSACM. Add + MOVE MACSR,CCR. + + * m68k-dis.c (fetch_arg): Add places `n', `o'. + + * m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK. + Add mcf5206e to appropriate instructions. + Add alias for MAC, MSAC. + + * m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place + `N'. + + * m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl, + macw, remsl, remul for mcf5307. Change mcf5200 --> mcf. + + * m68k-dis.c: Add format `u' and places `h', `m', `M'. + +1999-05-18 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (Ed): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd. + (Rw): Remove. + (OP_rm): Rename to OP_Rd. + (ONE): Remove. + (OP_ONE): Remove. + (putop): Add const to template and p. + (print_insn_x86): Delete. + (print_insn_i386): Merge old function print_insn_x86. Add const + to dp. + (struct dis386): Add const to name. + (dis386_att, dis386_intel): Add const. + (dis386_twobyte_att, dis386_twobyte_intel): Add const. + (names32, names16, names8, names_seg, index16): Add const. + (grps, prefix_user_table, float_reg): Add const. + (float_mem_att, float_mem_intel): Add const. + (oappend): Add const to s. + (OP_REG): Add const to s. + (ptr_reg): Add const to s. + (dofloat): Add const to dp. + (OP_C): Don't skip modrm, it's now done in OP_Rd. + (OP_D): Ditto. + (OP_T): Ditto. + (OP_Rd): Check for valid mod. Call Op_E to print. + (OP_E): Handle d_mode arg. Check for bad sfence,lea,lds etc. + (OP_MS): Check for valid mod. Call Op_EM to print. + (OP_3DNowSuffix): Set obufp and use oappend rather than + strcat. Call BadOp() for errors. + (OP_SIMD_Suffix): Likewise. + (BadOp): New function. + +1999-05-12 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (dis386_intel): Remove macro chars, except for + jEcxz. Change cWtR and cRtd to cW and cR. + (dis386_twobyte_intel): Remove macro chars here too. + (putop): Handle R and W macros for intel mode. + + * i386-dis.c (SIMD_Fixup): New function. + (dis386_twobyte_att): Use it on movlps and movhps, and change + Ev to EX on these insns. Change movmskps Ev, XM to Gv, EX. + (dis386_twobyte_intel): Same here. + + * i386-dis.c (Av): Remove. + (Ap): remove lptr. + (lptr): Remove. + (OPSIMD): Define. + (OP_SIMD_Suffix): New function. + (OP_DIR): Remove dead code. + (eAX_reg..eDI_reg): Renumber. + (onebyte_has_modrm): Table numbering comments. + (INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86. + (print_insn_x86): Move all prefix oappends to after uses_f3_prefix + checks. Print error on invalid dp->bytemode2. Remove simd_cmp, + and handle SIMD cmp insns in OP_SIMD_Suffix. + (info->bytes_per_line): Bump from 5 to 6. + (OP_None): Remove. + (OP_E): Use INTERNAL_DISASSEMBLER_ERROR. Handle sfence. + (OP_3DNowSuffix): Ensure mnemonic index unsigned. + + PIII SIMD support from Doug Ledford <dledford@redhat.com> + * i386-dis.c (XM, EX, None): Define. + (OP_XMM, OP_EX, OP_None): New functions. + (USE_GROUPS, USE_PREFIX_USER_TABLE): Define. + (GRP14): Rename to GRPAMD. + (GRP*): Add USE_GROUPS flag. + (PREGRP*): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns. + (twobyte_has_modrm): Add SIMD entries. + (twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New. + (grps): Add SIMD insns. + (print_insn_x86): New vars uses_f3_prefix and simd_cmp. Don't + oappend repz if uses_f3_prefix. Add code to handle new groups for + SIMD insns. + + From Maciej W. Rozycki <macro@ds2.pg.gda.pl> + * i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn + operand from Av to Jv. + +1999-05-07 Nick Clifton <nickc@cygnus.com> + + * mcore-dis.c (print_insn_mcore): Use .short to display + unidentified instructions, not .word. + +1999-04-26 Tom Tromey <tromey@cygnus.com> + + * aclocal.m4, configure: Updated for new version of libtool. + +1999-04-14 Doug Evans <devans@casey.cygnus.com> + + * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. + * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + +Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0 + instructions. + +1999-04-10 Doug Evans <devans@casey.cygnus.com> + + * fr30-desc.c,fr30-desc.h,fr30-ibld.c: Rebuild. + * m32r-desc.c,m32r-desc.h,m32r-opinst.c: Rebuild. + +1999-04-06 Ian Lance Taylor <ian@zembu.com> + + * opintl.h (LC_MESSAGES): Never define. + +1999-04-04 Ian Lance Taylor <ian@zembu.com> + + * i386-dis.c (intel_syntax, open_char, close_char): Make static. + (separator_char, scale_char): Likewise. + (print_insn_x86): Likewise. + (print_insn_i386): Likewise. Add declaration. + +1999-03-26 Doug Evans <devans@casey.cygnus.com> + + * fr30-dis.c: Rebuild. + * m32r-dis.c: Rebuild. + +1999-03-23 Ian Lance Taylor <ian@zembu.com> + + * m68k-opc.c: Change compare instructions to use "@s" rather than + ";s" when used with an immediate operand. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * cgen-opc.c (cgen_set_cpu): Delete. + (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. + * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c,fr30-opc.h: + Rebuild. + * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h: + Rebuild. + * po/opcodes.pot: Rebuild. + +1999-03-16 Martin Hunt <hunt@cygnus.com> + + * d30v-opc.c (mvtsys): Remove FLAG_LKR. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. + (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. + * fr30-asm.c,fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c: Rebuild. + * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c: Rebuild. + * m32r-opinst.c: Rebuild. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. + (cgen_hw_lookup_by_num): Rewrite. + * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. + * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> + + * alpha-opc.c: Add sqrt+flags patterns. Add EV6 PALcode insns. + (insert_jhint): Fix insertion mask. + * alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns. + +1999-02-10 Doug Evans <devans@casey.cygnus.com> + + * Makefile.in: Rebuild. + +1999-02-09 Doug Evans <devans@casey.cygnus.com> + + * i960c-asm.c,i960c-dis.c,i960c-opc.c,i960c-opc.h: Delete. + * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. + * Makefile.am: Remove references to them. + (HFILES): Add fr30-desc.h,m32r-desc.h. + (CFILES): Add fr30-desc.c,fr30-ibld.c,m32r-desc.c,m32r-ibld.c, + m32r-opinst.c. + (ALL_MACHINES): Update. + * configure.in: Redo handling of cgen_files. + (bfd_i960_arch): Delete i960c-*.lo files. + * configure: Regenerate. + * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (cgen_lookup_insn,cgen_get_insn_operands): Define here. + (cgen_lookup_get_insn_operands): Ditto. + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. + * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + * po/POTFILES.in: Rebuild. + * po/opcodes.pot: Rebuild. + +Fri Feb 5 00:04:24 1999 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.am: Rebuild dependencies. + (HFILES): Add fr30-opc.h. + (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. + * Makefile.in: Rebuild. + + * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. + Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to + AC_PROG_INSTALL. + * acconfig.h: Remove. + * configure: Rebuild with current autoconf/automake. + * aclocal.m4: Likewise. + * config.in: Likewise. + * Makefile.in: Likewise. + +Thu Feb 4 13:48:52 1999 Ian Lance Taylor <ian@cygnus.com> + + * m68k-opc.c: Correct move (not movew) to status word on 5200. + +Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com> + + * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. + * i386-dis.c (x_mode): Define. + (dis386): Remove. + (dis386_att): New. + (dis386_intel): New. + (dis386_twobyte): Remove. + (dis386_twobyte_att): New. + (dis386_twobyte_intel): New. + (print_insn_x86): Use new arrays. + (float_mem): Remove. + (float_mem_intel): New. + (float_mem_att): New. + (dofloat): Use new float_mem arrays. + (print_insn_i386_att): New. + (print_insn_i386_intel): New. + (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. + (putop): Handle intel syntax. + (OP_indirE): Handle intel syntax. + (OP_E): Handle intel syntax. + (OP_I): Handle intel syntax. + (OP_sI): Handle intel syntax. + (OP_OFF): Handle intel syntax. + +1999-01-27 Doug Evans <devans@casey.cygnus.com> + + * fr30-opc.h,fr30-opc.c: Rebuild. + * i960c-opc.h,i960c-opc.c: Rebuild. + * m32r-opc.c: Rebuild. + +Tue Jan 19 18:01:54 1999 David Taylor <taylor@texas.cygnus.com> + + * hppa-dis.c: revert HP merge changes until HP gives us + an updated file. + +1999-01-19 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative + offsets as well as symbloic address. + +Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> + + * hppa-dis.c: fix comments and some indentation. + +1999-01-12 Doug Evans <devans@casey.cygnus.com> + + * fr30-opc.c,i960c-opc.c: Regenerate. + +1999-01-11 Doug Evans <devans@casey.cygnus.com> + + * fr30-opc.c: Regenerate. + +1999-01-06 Doug Evans <devans@casey.cygnus.com> + + * m32r-dis.c: Regenerate. + +1999-01-05 Doug Evans <devans@casey.cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate. + * i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate. + * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. + +1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) + + * configure.in: Require autoconf 2.12.1 or higher. + +1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> + + * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. + +Wed Dec 16 16:17:49 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c: Regenerated. + +1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. + +1998-12-15 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c,fr30-opc.h: Regenerated. + +1998-12-14 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c,fr30-opc.h: Regenerated. + +Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c,fr30-opc.h: Regenerated. + +Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate. + +Tue Dec 8 13:56:18 1998 David Taylor <taylor@texas.cygnus.com> + + * dis-buf.c (generic_strcat_address): reformat to GNU coding + conventions. change sprintf call to an sprintf_vma call. + +Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + +Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> + + The following changes were made by + Elena Zannoni <ezannoni@kwikemart.cygnus.com>, + David Taylor <taylor@texas.cygnus.com>, and + Edith Epstein <eepstein@sophia.cygnus.com> as part of a project to + merge in changes by HP; HP did not create ChangeLog entries. + + * dis-buf.c (generic_strcat_address): new function. + + * hppa-dis.c: Changes to improve hppa disassembly. + Changed formatting in : reg_names, fp_reg_names,control_reg, + New variables : sign_extension_names, deposit_names, conversion_names + float_test_names, compare_cond_names_double, add_cond_names_double, + logical_cond_names_double, unit_cond_names_double, + branch_push_pop_names, saturation_names, shift_names, mix_names, + New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG + Move some definitions to libhppa.h: GET_FIELD, GET_BIT + (fput_const): renamed as fput_hex_const + (print_insn_hppa): + - use the macros fputs_filtered and + fput_decimal_const whenever possible; calls to sign_extend require + 2 params -- add a missing second param of 0. + - Some new code ifdefed for LOCAL_ONLY, all related to figuring out + architecture version number of current machine. HP folks are + trying to handle situation where the target program was compiled + for PA 1.x (32-bit), but is running on a PA 2.0 machine and + visa versa. + - added new cases : 'g', 'B', 'm' + - added cases specifically for PA 2.0 + - changed the following cases : '"', 'n', 'N', 'p', 'Z', + - calls to fput_const become calls to fput_hex_const + +1998-12-07 James E Wilson <wilson@wilson-pc.cygnus.com> + + * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. + (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. + (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. + * Makefile.in: Rebuilt. + * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, + i960-dis.c to ta. + * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. + +Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + +Sun Dec 6 14:06:48 1998 Ian Lance Taylor <ian@cygnus.com> + + * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. + + * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. + From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>. + +Fri Dec 4 17:45:51 1998 Doug Evans <devans@canuck.cygnus.com> + + * fr30-opc.c: Regenerate. + +Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + +Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + +Thu Dec 3 00:09:17 1998 Doug Evans <devans@canuck.cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. + +1998-11-30 Doug Evans <devans@casey.cygnus.com> + + * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> + CGEN_INSN_BASE_VALUE. + * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. + * fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate. + +Thu Nov 26 11:26:32 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated. + +Tue Nov 24 11:20:54 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c: Regenerated. + +Mon Nov 23 18:28:48 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + +1998-11-20 Doug Evans <devans@tobor.to.cygnus.com> + + * fr30-opc.c: Regenerated. + +Thu Nov 19 16:02:46 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 19 07:54:15 1998 Doug Evans <devans@charmed.cygnus.com> + + * mips-opc.c (sync.p,sync.l): Swap insn values. + +1998-11-19 Doug Evans <devans@tobor.to.cygnus.com> + + * fr30-opc.c: Regenerate. + +Wed Nov 18 21:36:37 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + +1998-11-18 Doug Evans <devans@casey.cygnus.com> + + * m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild. + * fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild. + +Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c: Regenerated. + +Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com> + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 12 19:24:18 1998 Dave Brolley <brolley@cygnus.com> + + * po/opcodes.pot: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com> + + * disassemble.c (disassembler): Add support for FR30 target. + +Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild. + * fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild. + +Mon Nov 9 18:22:55 1998 Dave Brolley <brolley@cygnus.com> + + * po/opcodes.pot: Regenerate. + * po/POTFILES.in: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + +Fri Nov 6 17:21:38 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-asm.c: Regenerate. + +Wed Nov 4 18:46:47 1998 Dave Brolley <brolley@cygnus.com> + + * configure.in: Added case for bfd_fr30_arch. + * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. + (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. + (CLEANFILES): Added stamp-fr30. + (FR30_DEPS): Added. + * fr30-asm.c: New file. + * fr30-dis.c: New file. + * fr30-opc.c: New file. + * fr30-opc.h: New file. + * po/POTFILES.in: Regenerated + * po/opcodes.pot: Regenerated + +Mon Nov 2 15:05:33 1998 Geoffrey Noer <noer@cygnus.com> + + * configure.in: detect cygwin* instead of cygwin32* + * configure: regenerate + +Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com> + + * mips-opc.c (IS_M): Added. + +Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. + +Fri Oct 9 14:01:56 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-opc.h,m32r-opc.c: Regenerate. + +Sun Oct 4 21:01:44 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (OP_3DNowSuffix): New static function. + (OPSUF): Define. + (GRP14): Define. + (dis386_twobyte): Add GRP14, femms, and 3DNow entries. + (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. + (insn_codep): New static variable. + (print_insn_x86): Init insn_codep after prefixes. + (grps): Add GRP14 entries for prefetch, prefetchw. + (OP_REG): Reformat. + + From Jeff B Epler <jepler@usgs.gov> + * i386-dis.c (Suffix3DNow): New table. + +Wed Sep 30 10:17:50 1998 Nick Clifton <nickc@cygnus.com> + + * d10v-opc.c: Treat TRAP as if it were a branch type instruction. + +Mon Sep 28 14:35:43 1998 Martin M. Hunt <hunt@cygnus.com> + + * d10v-dis.c (print_operand): If num is nonzero, then + add OPERAND_ACC1, not OPERAND_ACC0. + +Thu Sep 24 09:20:03 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP + insns. + +Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit + class. + +Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.h,m32r-opc.c: Add bbpc,bbpsw support. + +1998-09-09 Michael Meissner <meissner@cygnus.com> + + * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move + to/from SPRs. + +Fri Sep 4 19:42:59 1998 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf + object files. + (print_insn_little_arm): Detect Thumb symbols in elf object + files. + +Sat Aug 29 22:24:09 1998 Richard Henderson <rth@cygnus.com> + + * alpha-dis.c (print_insn_alpha): Use the machine type to + decide which PALcode set to include. + +Sun Aug 23 02:16:18 1998 Richard Henderson <rth@cygnus.com> + + * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. + +Fri Aug 21 16:07:52 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, + MSUB and MSUBS instructions. + +Thu Aug 13 16:23:04 1998 Ian Lance Taylor <ian@cygnus.com> + + * ppc-opc.c (powerpc_operands): Omit parens around additions in + operand name macros. + +Wed Aug 12 14:00:38 1998 Ian Lance Taylor <ian@cygnus.com> + + From Peter Jeremy <peter.jeremy@auss2.alcatel.com.au>: + * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, + +, -, and d for ColdFire. + + From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>: + * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. + (extract_mbe): Likewise. + +Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. + + * m10300-opc.c: First cut at UDF instructions. + +Mon Aug 10 14:08:22 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate (remove semantic descriptions). + +Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com> + + * arm-dis.c (print_insn_big_arm): Fix indentation. + (print_insn_little_arm): Likewise. + +Sun Aug 9 20:17:28 1998 Catherine Moore <clm@cygnus.com> + + * arm-dis.c (print_insn_big_arm): Check for thumb symbol + attributes. + (print_insn_little_arm): Likewise. + +Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com> + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen-asm.c (all fns): New first arg of opcode table descriptor. + (cgen_asm_init): Delete. + (cgen_set_parse_operand_fn): New function. + * cgen-dis.c (all fns): New first arg of opcode table descriptor. + (cgen_dis_init): Delete. + * cgen-opc.c (all fns): New first arg of opcode table descriptor. + (cgen_current_{opcode_table_mach,endian}): Delete. + * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + +Thu Jul 30 21:41:10 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some + instructions. + +Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Add entries for "no_match_operands" field in + the opcode table. + +Fri Jul 24 11:41:37 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups). + +Tue Jul 21 13:41:07 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + +Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (ckprefix): Handle fwait specially only when it isn't + the first prefix. + (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather + than `fnstsw %eax'. + (OP_J): Remove unnecessary subtraction when 16-bit displacement + will be masked later. + +Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. + +Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + +Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-dis.c: Only recognize instructions from the currently + selected machine. + * m10300-opc.c: Add field indicating the particular variant of + the mn10300 each instruction is available on. + +Fri Jun 26 12:04:21 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: For bfd_vax_arch, build vax-dis.lo. + * Makefile.am: Rebuild dependencies. + (CFILES): Add vax-dis.c. + (ALL_MACHINES): Add vax-dis.lo. + * aclocal.m4: Rebuild with current libtool. + * configure, Makefile.in: Rebuild. + +Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de> + + * vax-dis.c: New file, from work by Pauline Middelink + <middelin@polyware.iaf.nl>. + * disassemble.c (ARCH_vax): Define if ARCH_all. + (disassembler): Add case for ARCH_vax. + * makefile.vms: Support compilation on vms/vax. + +Tue Jun 23 19:42:18 1998 Mark Alexander <marka@cygnus.com> + + * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities + related to sign extension and the size of ints. + +Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Support one operand "asr", "lsr" and "asl" + instructions. Support (sp) addressing mode by expanding it into + (0,sp). + +Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips-dis.c (_print_insn_mips): Fix argument interchange typo. + +Fri Jun 19 09:16:42 1998 Mark Alexander <marka@cygnus.com> + + * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. + +1998-06-18 Ulrich Drepper <drepper@cygnus.com> + + * i386-dis.c: Add support for fxsave, fxrstor, sysenter and + sysexit. + +Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com> + + * mips-dis.c (print_insn_little_mips): Previously, instruction + printing references the symbol table to determine whether the + instruction resides in a block regular instructions or mips16 + instructions. However, when the disassembler gets used in other + environments where the symbol table is not present, we no longer + rely in the symbol table, rather, use the low bit of the + instructions address to guess. There should be no change for usage + of the disassembler in host based programs, gdb, objdump. + (print_insn_big_mips): ditto. + (print_insn_mips): ditto + +Wed Jun 17 21:19:01 1998 Mark Alexander <marka@cygnus.com> + + * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. + +Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". + +Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (index16): Add '%' to register names. Use ',' + instead of '+'. + +Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c: Don't print opcode suffix when we can figure out the + size (and gas can!) by register operands, or from the default + size. + (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' + macro to 'E'. + (dis386, dis386_twobyte, grps): Use new suffix macros. + (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be + consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse + order of cmps operands to agree with Intel docs. Correct operand + of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to + agree with Intel docs. + (print_insn_x86): Print orphan fwait before other prefixes. + Return correct byte count for orphan fwait with prefixes. Don't + print `bound' operands in reverse order. + (ckprefix): Stop accumulating prefixes if we get fwait. + (OP_DIR): Print `$' before Ap operands of ljmp, lcall. + +Fri Jun 12 13:40:38 1998 Tom Tromey <tromey@cygnus.com> + + * po/Make-in (all-yes): If maintainer mode, depend on .pot file. + ($(PACKAGE).pot): Unconditionally depend on POTFILES. + +Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + Fix problems when bfd_vma is wider than long. + * i386-dis.c: Make op_address and start_pc unsigned. + (set_op): Make parameter unsigned. + (print_insn_x86): Cast to bfd_vma when passing a value to + print_address_func. + * ns32k-dis.c (CORE_ADDR): Don't define. + (print_insn_ns32k): Change type of addr to bfd_vma. Use + bfd_scan_vma to read back address. + (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma + to format it. + * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. + (NEXTULONG): New definition. + (print_insn_m68k): Avoid overflow when computing third argument of + print_insn_arg. + (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. + Use disp instead of val to store offset values. + (print_indexed): Use base_disp instead of word to store base + displacement, to avoid overflow. + * m10300-dis.c (disassemble): Cast value to long when computing + pc-relative address, to get correct sign extension. + +Wed Jun 10 15:58:37 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate. + +Tue Jun 9 14:27:57 1998 Nick Clifton <nickc@cygnus.com> + + * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as + 'mov rX, rY'. Patch courtesy of Tony Thompson <Tony.Thompson@arm.com> + +Mon Jun 8 18:17:21 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. + +Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* + functions to void. + (OP_DSreg): Rename from OP_DSSI. + (OP_ESreg): Rename from OP_ESDI. + (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. + (DSBX): Define. + (append_seg): Rename from append_prefix. + (ptr_reg): New function. + (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. + Add DSBX for xlat. + (PREFIX_ADDR): Rename from PREFIX_ADR. + (float_reg): Add non-broken opcodes for people who don't want + UNIXWARE_COMPAT. + +Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on + 68000/68008/68010. + +Wed Jun 3 18:56:22 1998 H.J. Lu <hjl@gnu.org> + + * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". + +Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au> + + * ppc-opc.c (powerpc_macros): Support shifts and rotates of size + 0; produce error message for shifts of size 32 (or 64 for 64-bit + shifts), because the hardware doesn't support them. + +Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, + LONG_2, LONG_2b formats to use this new operand. + +Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com> + + * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. + +Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com> + + * sparc-dis.c (print_insn_sparc): big endian instruction / little + endian data support. + +Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com> + + * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 + and SHORT_B3b formats to use Rb instead of Ra. + + Add FLAG_MUL16 to MUL2XH opcode. + + Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension + to existing 1.1.1 parallelisation prohibition procedure. + +Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-asm.c,m32r-dis.c: Regenerate. + +Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com> + + * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly + with a shift count of 0. + +Fri May 15 14:58:31 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): New function. + +Wed May 13 17:03:59 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). + +Wed May 13 14:34:31 1998 Mark Alexander <marka@cygnus.com> + + * sparc-dis.c (print_insn_sparc): Always fetch instructions + as big-endian on SPARClite. + +Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com> + + * d30v-opc.c (pre_defined_register): Remove alias for r0. + +Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) + + * po/Make-in (install-info): New target. + +Thu May 7 17:15:59 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in (WIN32LIBADD): Add -lintl on cygwin32. + * configure: Rebuild. + +Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand + variety of ISA2 instructions to set bottom ten bits of trap code. + +Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.am (config.status): Add explicit target so that + config.status depends upon bfd/configure.in. + * Makefile.in: Rebuild. + +Thu May 7 09:33:02 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 + instructions to set bottom ten bits of break code. + * mips-dis.c (print_insn_arg): Implement 'q' operand format used + for above optional argument. + +Wed May 6 15:30:06 1998 Klaus Kaempf <kkaempf@progis.de> + + * makefile.vms: Run dec c with /nodebug. + +Mon May 4 10:19:57 1998 Tom Tromey <tromey@cygnus.com> + + * Makefile.in: Rebuilt. + * Makefile.am: Regenerated dependencies with mkdep. + + * opintl.h (_): Define as dgettext. + +Tue Apr 28 14:12:12 1998 Nick Clifton <nickc@cygnus.com> + + * cgen-asm.c: Internationalised. + * m32r-asm.c: Internationalised. + * m32r-dis.c: Internationalised. + * m32r-opc.c: Internationalised. + + * aclocal.m4: Regenerated. + * configure: Regenerated. + * Makefile.am (POTFILES): Remove inclusion of BFD_H. + * Makefile.in: Rebuild. + * po/POTFILES.in: Rebuilt using rule in Makefile.in. + * po/opcodes.pot: Rebuilt after changing POTFILES.in. + +Tue Apr 28 13:13:13 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT + after AC_PROG_CC. + * aclocal.m4, configure: Rebuild with current tools. + +Mon Apr 27 14:31:00 1998 Nick Clifton <nickc@cygnus.com> + + * opintl.h: New file - contains internationalisation macros used + by source files in this directory. + * po/: New subdirectory - contains internationalisation files. + * po/Make-in: New file - Makefile constructor. + * po/POTFILES.in: New file - list of files in opcodes directory + that should be scan for internationalisation macros. + * po/opcodes.pot: New file - list of internationisation strings + found in files mentioned in po/POTFILES.in. + * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS + entry. Add intl directory to include paths. + * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, + HAVE_STRCPY, HAVE_LC_MESSAGES + * configure.in: Add rule to build Makefile in po subdirectory. + * Makefile.in: Rebuilt. + * aclocal.m4: Rebuilt. + * config.in: Rebuilt. + * configure: Rebuilt. + * alpha-opc.c: Internationalised. + * arc-dis.c: Internationalised. + * arc-opc.c: Internationalised. + * arm-dis.c: Internationalised. + * cgen-asm.c: Internationalised. + * d30v-dis.c: Internationalised. + * dis-buf.c: Internationalised. + * h8300-dis.c: Internationalised. + * h8500-dis.c: Internationalised. + * i386-dis.c: Internationalised. + * m10200-dis.c: Internationalised. + * m10300-dis.c: Internationalised. + * m68k-dis.c: Internationalised. + * m88k-dis.c: Internationalised. + * mips-dis.c: Internationalised. + * ns32k-dis.c: Internationalised. + * opintl.h: Internationalised. + * ppc-opc.c: Internationalised. + * sparc-dis.c: Internationalised. + * v850-dis.c: Internationalised. + * v850-opc.c: Internationalised. + +Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. + (asm_hash_table_entries): New variable. + (cgen_asm_init): Free asm_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_asm_hash_table): Use them. Hash macro insns as well. + (cgen_asm_lookup_insn): Update. + * cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data. + (dis_hash_table_entries): New variable. + (cgen_dis_init): Free dis_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_dis_hash_table): Use them. Hash macro insns as well. + (cgen_dis_lookup_insn): Update. + * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. + (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. + (cgen_macro_insn_count): New function. + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + +Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386-dis.c (OP_DSSI): Print segment override. + +Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' + operator. + +Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. + (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. + * configure.in: Define and substitute WIN32LDFLAGS and + WIN32LIBADD. + * aclocal.m4: Rebuild with new libtool. + * configure, Makefile.in: Rebuild. + +Fri Apr 10 18:14:31 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate. + +Sun Apr 5 16:04:39 1998 H.J. Lu <hjl@gnu.org> + + * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists + before trying to copy it. + * Makefile.in: Rebuild. + +Thu Apr 2 17:25:49 1998 Nick Clifton <nickc@cygnus.com> + + * m32r-opc.c: Use signed immediate values for CMPUI instruction. + +Wed Apr 1 16:20:27 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au> + + * ns32k-dis.c (bit_extract_simple): New function to extract bits + from an arbitrary valid buffer instead of fetching them on demand + using fetch_data(). + (invalid_float): use bit_extract_simple() instead of bit_extract(). + +Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com> + + From H.J. Lu <hjl@gnu.org>: + * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew + to Ev for both. + +Mon Mar 30 17:32:03 1998 Ian Lance Taylor <ian@cygnus.com> + + * Branched binutils 2.9. + +Mon Mar 30 15:18:00 1998 Ken Raeburn <raeburn@cygnus.com> + + * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when + disassembling last 4 bytes of a section. + +Fri Mar 27 18:08:13 1998 Ian Lance Taylor <ian@cygnus.com> + + Fix some gcc -Wall warnings: + * arc-dis.c (print_insn): Add casts to avoid warnings. + * cgen-opc.c (cgen_keyword_lookup_name): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * m10200-dis.c (disassemble): Likewise. + * m10300-dis.c (disassemble): Likewise. + * ns32k-dis.c (print_insn_ns32k): Likewise. + * ppc-opc.c (insert_ral, insert_ram): Likewise. + * cgen-dis.c (build_dis_hash_table): Remove used local variables. + * cgen-opc.c (cgen_keyword_search_next): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. + * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. + * tic80-dis.c (print_one_instruction): Likewise. + * w65-dis.c (print_operand): Likewise. + * z8k-dis.c (fetch_data): Likewise. + * a29k-dis.c: Add return type for find_byte_func_type. + * arc-opc.c: Include <stdio.h>. Remove declarations of + insert_multshift and extract_multshift. + * d30v-dis.c (lookup_opcode): Parenthesize assignments in + conditionals. + (extract_value): Fully parenthesize expression. + * h8500-dis.c (print_insn_h8500): Initialize local variables. + * h8500-opc.h (h8500_table): Fully bracket initializer. + * w65-opc.h (optable): Likewise. + * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. + * i386-dis.c (OP_E): Initialize local variables. + * m10200-dis.c (print_insn_mn10200): Likewise. + * mips-dis.c (print_insn_mips16): Likewise. + * sh-dis.c (print_insn_shx): Likewise. + * v850-dis.c (print_insn_v850): Likewise. + * ns32k-dis.c (print_insn_arg): Declare. + (get_displacement, invalid_float): Declare. + (list_search, sign_extend, flip_bytes): Declare return type. + (get_displacement): Likewise. + (print_insn_arg): Likewise. Make d int. Fix sprintf format + string. + (print_insn_ns32k): Make i unsigned. + (invalid_float): Make static. Declare type of val. + * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen + on each for iteration. + * tic30-dis.c (get_indirect_operand): Likewise. + * z8k-dis.c (print_insn_z8001): Declare return type. + (print_insn_z8002): Likewise. + (unparse_instr): Fix sprintf format strings. + +Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Add "sync.l" and "sync.p". + +Wed Mar 25 14:32:48 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k-dis.c (print_insn_m68k): Use info->mach to select the + default m68k variant to recognize. + + * i960-dis.c (pinsn): Change type of first argument to bfd_vma. + (ctrl, cobr, mem, ea): Likewise. + (print_addr): Likewise. Remove cast. + (ea): Cast argument of print_addr to bfd_vma. + + * cgen-asm.c (cgen_parse_signed_integer): Fix type of local + variable value. + (cgen_parse_unsigned_integer): Likewise. + (cgen_parse_address): Likewise. + +Wed Mar 25 14:31:31 1998 Ian Lance Taylor <ian@cygnus.com> + + * i960-dis.c (ctrl): Add full braces to structure initialization. + (cobr, mem, reg): Likewise. + (ea): Correct parenthesization in expression. + + * cgen-asm.c: Include <ctype.h>. + (build_asm_hash_table): Remove unused local variable i. + (cgen_parse_keyword): Add casts to avoid warnings. + + * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF + symbol. Fix indentation. + (print_insn_little_arm): Likewise. + +Fri Mar 20 18:55:18 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Use AM_DISABLE_SHARED. + * aclocal.m4, configure: Rebuild with libtool 1.2. + +Thu Mar 19 15:46:53 1998 Nick Clifton <nickc@cygnus.com> + + These patches are courtesy of Jonathan Walton and Tony Thompson + (athompso@cambridge.arm.com). + + * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC + relative addresses. + + * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with + both the offset and the label closest to the destination. + +Sat Mar 14 23:47:14 1998 Doug Evans <devans@seba.cygnus.com> + + * m32r-opc.h: Regenerate. + +Wed Mar 4 12:08:14 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + +Sat Feb 28 16:02:34 1998 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not + assume that info->symbols is non-empty. + +Sat Feb 28 12:19:05 1998 Richard Henderson <rth@cygnus.com> + + * alpha-opc.c (cvtqs) There is no such thing. + (cvttq): Missing most of the /*d variants. + +Thu Feb 26 15:53:09 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-opc.c (d30v_opcode_table): Indicate which instructions are + delayed branches or jumps. + +Tue Feb 24 10:46:44 1998 Doug Evans <devans@canuck.cygnus.com> + + * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed + to *info->symbols. + * mips-dis.c (print_insn_{big,little}_mips): Likewise. + * tic30-dis.c (print_branch): Likewise. + +Tue Feb 24 11:06:18 1998 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove + saved_symbol code as it is no longer needed. + +Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-asm.c: Include symcat.h. + * cgen-dis.c,cgen-opc.c: Ditto. + * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. + +Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. + +Thu Feb 19 16:51:13 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.[ch]: Regenerate. + +Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max + arguments. Don't perform validation here. + * m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate. + +Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate. + +Fri Feb 13 14:53:02 1998 Ian Lance Taylor <ian@cygnus.com> + + * Makefile.am (AUTOMAKE_OPTIONS): Define. + * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. + +Fri Feb 13 10:21:09 1998 Mark Alexander <marka@cygnus.com> + + * m10300-dis.c (print_insn_mn10300): Recognize break instruction. + +Fri Feb 13 13:12:14 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Get the version number from BFD. + * configure: Rebuild. + + From H.J. Lu <hjl@gnu.org>: + * Makefile.am (libopcodes_la_LDFLAGS): Define. + * Makefile.in: Rebuild. + +Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com> + + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + +Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.c: Regenerate. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + + Fix rac to accept only a0: + * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): + Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. + Introduce OPERAND_GPR. + * d10v-dis.c (print_operand): Likewise. + +Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. + (cgen_hw_lookup): Make result const. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Sat Feb 7 15:30:27 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure, aclocal.m4: Rebuild with new libtool. + +Thu Feb 5 17:56:10 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-opc.c (repeat{,i} instructions): Repeat/repeati + instructions use a PC relative branch, not absolute. + +Wed Feb 4 19:17:37 1998 Ian Lance Taylor <ian@cygnus.com> + + * configure.in: Set libtool_enable_shared rather than + libtool_shared. Remove diversion hack. + * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. + +Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-opc.c (cgen_set_cpu): Initialize hardware table. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * tic30-dis.c: New file. + * disassemble.c (disassembler): Add bfd_arch_tic30 case. + * configure.in: Handle bfd_tic30_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add tic30-dis.c + (ALL_MACHINES): Add tic30-dis.lo. + * configure, Makefile.in: Rebuild. + +Thu Jan 29 13:02:56 1998 Doug Evans <devans@canuck.cygnus.com> + + * m32r-opc.h (HAVE_CPU_M32R): Define. + +Wed Jan 28 09:55:03 1998 Nick Clifton <nickc@cygnus.com> + + * v850-opc.c (insertion routines): If both alignment and size is + wrong then report this. + +Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. + Only recognize instructions for the current target_processor. + +Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com> + + * d10v-dis.c (PC_MASK): Correct value. + (print_operand): If there's a reloc, don't calculate the + address because they could be in different sections. + +Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com> + + * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" + instruction after the 4650's "mul" instruction; nobody's using the + 4010 these days. If object files someday indicate which processor + variant they're intended for, we can do a better job at this. + +Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MNEMONIC. + (cgen_parse_keyword): Rewrite. + * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MASK_BITSIZE. + * cgen-opc.c: Clean up pass over `struct foo' usage. + (cgen_keyword_lookup_value): Handle "" entry. + (cgen_keyword_add): Likewise. + +For older changes see ChangeLog-9297 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/gnu/usr.bin/binutils/opcodes/MAINTAINERS b/gnu/usr.bin/binutils/opcodes/MAINTAINERS new file mode 100644 index 00000000000..d59a3bd7f88 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/gnu/usr.bin/binutils/opcodes/acinclude.m4 b/gnu/usr.bin/binutils/opcodes/acinclude.m4 index 71b09b9f6ac..bb689a5ce8f 100644 --- a/gnu/usr.bin/binutils/opcodes/acinclude.m4 +++ b/gnu/usr.bin/binutils/opcodes/acinclude.m4 @@ -1 +1,17 @@ sinclude(../bfd/acinclude.m4) + +dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 +dnl The lines below arrange for aclocal not to bring libtool.m4 +dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake +dnl to add a definition of LIBTOOL to Makefile.in. +ifelse(yes,no,[ +AC_DEFUN([AM_PROG_LIBTOOL],) +AC_DEFUN([AM_DISABLE_SHARED],) +AC_SUBST(LIBTOOL) +]) + +dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 +ifelse(yes,no,[ +AC_DEFUN([CY_WITH_NLS],) +AC_SUBST(INTLLIBS) +]) diff --git a/gnu/usr.bin/binutils/opcodes/alpha-opc.c b/gnu/usr.bin/binutils/opcodes/alpha-opc.c index 99458916ad3..7680f47d2a1 100644 --- a/gnu/usr.bin/binutils/opcodes/alpha-opc.c +++ b/gnu/usr.bin/binutils/opcodes/alpha-opc.c @@ -1,5 +1,5 @@ /* alpha-opc.c -- Alpha AXP opcode list - Copyright (c) 1996, 1998, 1999 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@cygnus.com>, patterned after the PPC opcode handling written by Ian Lance Taylor. diff --git a/gnu/usr.bin/binutils/opcodes/arc-dis.c b/gnu/usr.bin/binutils/opcodes/arc-dis.c index 03f13795275..18325a92778 100644 --- a/gnu/usr.bin/binutils/opcodes/arc-dis.c +++ b/gnu/usr.bin/binutils/opcodes/arc-dis.c @@ -1,268 +1,1221 @@ /* Instruction printing code for the ARC. - Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. + Copyright 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include "sysdep.h" +#include <ansidecl.h> +#include <libiberty.h> #include "dis-asm.h" #include "opcode/arc.h" #include "elf-bfd.h" #include "elf/arc.h" +#include <string.h> #include "opintl.h" -static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *)); +#include <ctype.h> +#include <stdarg.h> +#include "arc-dis.h" +#include "arc-ext.h" -static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int)); +#ifndef dbg +#define dbg (0) +#endif -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (4 or 8 for the ARC). */ +#define BIT(word,n) ((word) & (1 << n)) +#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) +#define OPCODE(word) (BITS ((word), 27, 31)) +#define FIELDA(word) (BITS ((word), 21, 26)) +#define FIELDB(word) (BITS ((word), 15, 20)) +#define FIELDC(word) (BITS ((word), 9, 14)) -static int -print_insn (pc, info, mach, big_p) - bfd_vma pc; - disassemble_info *info; - int mach; - int big_p; +/* FIELD D is signed in all of its uses, so we make sure argument is + treated as signed for bit shifting purposes: */ +#define FIELDD(word) (BITS (((signed int)word), 0, 8)) + +#define PUT_NEXT_WORD_IN(a) \ + do \ + { \ + if (is_limm == 1 && !NEXT_WORD (1)) \ + mwerror (state, _("Illegal limm reference in last instruction!\n")); \ + a = state->words[1]; \ + } \ + while (0) + +#define CHECK_FLAG_COND_NULLIFY() \ + do \ + { \ + if (is_shimm == 0) \ + { \ + flag = BIT (state->words[0], 8); \ + state->nullifyMode = BITS (state->words[0], 5, 6); \ + cond = BITS (state->words[0], 0, 4); \ + } \ + } \ + while (0) + +#define CHECK_COND() \ + do \ + { \ + if (is_shimm == 0) \ + cond = BITS (state->words[0], 0, 4); \ + } \ + while (0) + +#define CHECK_FIELD(field) \ + do \ + { \ + if (field == 62) \ + { \ + is_limm++; \ + field##isReg = 0; \ + PUT_NEXT_WORD_IN (field); \ + limm_value = field; \ + } \ + else if (field > 60) \ + { \ + field##isReg = 0; \ + is_shimm++; \ + flag = (field == 61); \ + field = FIELDD (state->words[0]); \ + } \ + } \ + while (0) + +#define CHECK_FIELD_A() \ + do \ + { \ + fieldA = FIELDA(state->words[0]); \ + if (fieldA > 60) \ + { \ + fieldAisReg = 0; \ + fieldA = 0; \ + } \ + } \ + while (0) + +#define CHECK_FIELD_B() \ + do \ + { \ + fieldB = FIELDB (state->words[0]); \ + CHECK_FIELD (fieldB); \ + } \ + while (0) + +#define CHECK_FIELD_C() \ + do \ + { \ + fieldC = FIELDC (state->words[0]); \ + CHECK_FIELD (fieldC); \ + } \ + while (0) + +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") +#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ + (IS_REG (x) ? cb1"%r"ca1 : \ + usesAuxReg ? cb"%a"ca : \ + IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) +#define WRITE_FORMAT_RB() strcat (formatString, "]") +#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) +#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); + +#define NEXT_WORD(x) (offset += 4, state->words[x]) + +#define add_target(x) (state->targets[state->tcnt++] = (x)) + +static char comment_prefix[] = "\t; "; + +static const char * +core_reg_name (state, val) + struct arcDisState * state; + int val; { - const struct arc_opcode *opcode; - bfd_byte buffer[4]; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - int status; - /* First element is insn, second element is limm (if present). */ - arc_insn insn[2]; - int got_limm_p = 0; - static int initialized = 0; - static int current_mach = 0; + if (state->coreRegName) + return (*state->coreRegName)(state->_this, val); + return 0; +} - if (!initialized || mach != current_mach) - { - initialized = 1; - current_mach = arc_get_opcode_mach (mach, big_p); - arc_opcode_init_tables (current_mach); - } +static const char * +aux_reg_name (state, val) + struct arcDisState * state; + int val; +{ + if (state->auxRegName) + return (*state->auxRegName)(state->_this, val); + return 0; +} - status = (*info->read_memory_func) (pc, buffer, 4, info); - if (status != 0) +static const char * +cond_code_name (state, val) + struct arcDisState * state; + int val; +{ + if (state->condCodeName) + return (*state->condCodeName)(state->_this, val); + return 0; +} + +static const char * +instruction_name (state, op1, op2, flags) + struct arcDisState * state; + int op1; + int op2; + int * flags; +{ + if (state->instName) + return (*state->instName)(state->_this, op1, op2, flags); + return 0; +} + +static void +mwerror (state, msg) + struct arcDisState * state; + const char * msg; +{ + if (state->err != 0) + (*state->err)(state->_this, (msg)); +} + +static const char * +post_address (state, addr) + struct arcDisState * state; + int addr; +{ + static char id[3 * ARRAY_SIZE (state->addresses)]; + int j, i = state->acnt; + + if (i < ((int) ARRAY_SIZE (state->addresses))) { - (*info->memory_error_func) (status, pc, info); - return -1; + state->addresses[i] = addr; + ++state->acnt; + j = i*3; + id[j+0] = '@'; + id[j+1] = '0'+i; + id[j+2] = 0; + + return id + j; } - if (big_p) - insn[0] = bfd_getb32 (buffer); - else - insn[0] = bfd_getl32 (buffer); + return ""; +} - (*func) (stream, "%08lx\t", insn[0]); +static void +my_sprintf ( + struct arcDisState * state, + char * buf, + const char * format, + ...) +{ + char *bp; + const char *p; + int size, leading_zero, regMap[2]; + long auxNum; + va_list ap; + + va_start (ap, format); + + bp = buf; + *bp = 0; + p = format; + auxNum = -1; + regMap[0] = 0; + regMap[1] = 0; + + while (1) + switch (*p++) + { + case 0: + goto DOCOMM; /* (return) */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY: ; + switch (*p++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + /* size. */ + size = p[-1] - '0'; + if (size == 0) + leading_zero = 1; /* e.g. %08x */ + while (*p >= '0' && *p <= '9') + { + size = size * 10 + *p - '0'; + p++; + } + goto RETRY; + } +#define inc_bp() bp = bp + strlen (bp) - /* The instructions are stored in lists hashed by the insn code - (though we needn't care how they're hashed). */ + case 'h': + { + unsigned u = va_arg (ap, int); - opcode = arc_opcode_lookup_dis (insn[0]); - for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode)) - { - char *syn; - int mods,invalid; - long value; - const struct arc_operand *operand; - const struct arc_operand_value *opval; - - /* Basic bit mask must be correct. */ - if ((insn[0] & opcode->mask) != opcode->value) - continue; - - /* Supported by this cpu? */ - if (! arc_opcode_supported (opcode)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - - arc_opcode_init_extract (); - invalid = 0; - - /* ??? Granted, this is slower than the `ppc' way. Maybe when this is - done it'll be clear what the right way to do this is. */ - /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets - printed first, but we don't know how to print it until we've processed - the regs. Since we're scanning all the args before printing the insn - anyways, it's actually quite easy. */ - - for (syn = opcode->syntax; *syn; ++syn) - { - int c; + /* Hex. We can change the format to 0x%08x in + one place, here, if we wish. + We add underscores for easy reading. */ + if (u > 65536) + sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); + else + sprintf (bp, "0x%x", u); + inc_bp (); + } + break; + case 'X': case 'x': + { + int val = va_arg (ap, int); - if (*syn != '%' || *++syn == '%') - continue; - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) + if (size != 0) + if (leading_zero) + sprintf (bp, "%0*x", size, val); + else + sprintf (bp, "%*x", size, val); + else + sprintf (bp, "%x", val); + inc_bp (); + } + break; + case 'd': { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; + int val = va_arg (ap, int); + + if (size != 0) + sprintf (bp, "%*d", size, val); + else + sprintf (bp, "%d", val); + inc_bp (); } - operand = arc_operands + arc_operand_map[c]; - if (operand->extract) - (*operand->extract) (insn, operand, mods, - (const struct arc_operand_value **) NULL, - &invalid); - } - if (invalid) - continue; + break; + case 'r': + { + /* Register. */ + int val = va_arg (ap, int); + +#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ + regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; + + switch (val) + { + REG2NAME (26, "gp"); + REG2NAME (27, "fp"); + REG2NAME (28, "sp"); + REG2NAME (29, "ilink1"); + REG2NAME (30, "ilink2"); + REG2NAME (31, "blink"); + REG2NAME (60, "lp_count"); + default: + { + const char * ext; + + ext = core_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + sprintf (bp,"r%d",val); + } + break; + } + inc_bp (); + } break; + + case 'a': + { + /* Aux Register. */ + int val = va_arg (ap, int); - /* The instruction is valid. */ +#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; - /* If we have an insn with a limm, fetch it now. Scanning the insns - twice lets us do this. */ - if (arc_opcode_limm_p (NULL)) - { - status = (*info->read_memory_func) (pc + 4, buffer, 4, info); - if (status != 0) + switch (val) + { + AUXREG2NAME (0x0, "status"); + AUXREG2NAME (0x1, "semaphore"); + AUXREG2NAME (0x2, "lp_start"); + AUXREG2NAME (0x3, "lp_end"); + AUXREG2NAME (0x4, "identity"); + AUXREG2NAME (0x5, "debug"); + default: + { + const char *ext; + + ext = aux_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + my_sprintf (state, bp, "%h", val); + } + break; + } + inc_bp (); + } + break; + + case 's': { - (*info->memory_error_func) (status, pc, info); - return -1; + sprintf (bp, "%s", va_arg (ap, char *)); + inc_bp (); } - if (big_p) - insn[1] = bfd_getb32 (buffer); + break; + + default: + fprintf (stderr, "?? format %c\n", p[-1]); + break; + } + } + + DOCOMM: *bp = 0; +} + +static void +write_comments_(state, shimm, is_limm, limm_value) + struct arcDisState * state; + int shimm; + int is_limm; + long limm_value; +{ + if (state->commentBuffer != 0) + { + int i; + + if (is_limm) + { + const char *name = post_address (state, limm_value + shimm); + + if (*name != 0) + WRITE_COMMENT (name); + } + for (i = 0; i < state->commNum; i++) + { + if (i == 0) + strcpy (state->commentBuffer, comment_prefix); else - insn[1] = bfd_getl32 (buffer); - got_limm_p = 1; + strcat (state->commentBuffer, ", "); + strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer)); } + } +} - for (syn = opcode->syntax; *syn; ++syn) - { - int c; +#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) +#define write_comments() write_comments2(0) + +static const char *condName[] = { + /* 0..15. */ + "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , + "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" +}; + +static void +write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) + struct arcDisState * state; + const char * instrName; + int cond; + int condCodeIsPartOfName; + int flag; + int signExtend; + int addrWriteBack; + int directMem; +{ + strcpy (state->instrBuffer, instrName); + + if (cond > 0) + { + const char *cc = 0; + + if (!condCodeIsPartOfName) + strcat (state->instrBuffer, "."); + + if (cond < 16) + cc = condName[cond]; + else + cc = cond_code_name (state, cond); + + if (!cc) + cc = "???"; + + strcat (state->instrBuffer, cc); + } + + if (flag) + strcat (state->instrBuffer, ".f"); + + switch (state->nullifyMode) + { + case BR_exec_always: + strcat (state->instrBuffer, ".d"); + break; + case BR_exec_when_jump: + strcat (state->instrBuffer, ".jd"); + break; + } + + if (signExtend) + strcat (state->instrBuffer, ".x"); + + if (addrWriteBack) + strcat (state->instrBuffer, ".a"); + + if (directMem) + strcat (state->instrBuffer, ".di"); +} + +#define write_instr_name() \ + do \ + { \ + write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ + flag, signExtend, addrWriteBack, directMem); \ + formatString[0] = '\0'; \ + } \ + while (0) + +enum { + op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, + op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, + op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, + op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 +}; + +extern disassemble_info tm_print_insn_info; - if (*syn != '%' || *++syn == '%') +static int +dsmOneArcInst (addr, state) + bfd_vma addr; + struct arcDisState * state; +{ + int condCodeIsPartOfName = 0; + int decodingClass; + const char * instrName; + int repeatsOp = 0; + int fieldAisReg = 1; + int fieldBisReg = 1; + int fieldCisReg = 1; + int fieldA; + int fieldB; + int fieldC = 0; + int flag = 0; + int cond = 0; + int is_shimm = 0; + int is_limm = 0; + long limm_value = 0; + int signExtend = 0; + int addrWriteBack = 0; + int directMem = 0; + int is_linked = 0; + int offset = 0; + int usesAuxReg = 0; + int flags; + int ignoreFirstOpd; + char formatString[60]; + + state->instructionLen = 4; + state->nullifyMode = BR_exec_when_no_jump; + state->opWidth = 12; + state->isBranch = 0; + + state->_mem_load = 0; + state->_ea_present = 0; + state->_load_len = 0; + state->ea_reg1 = no_reg; + state->ea_reg2 = no_reg; + state->_offset = 0; + + if (! NEXT_WORD (0)) + return 0; + + state->_opcode = OPCODE (state->words[0]); + instrName = 0; + decodingClass = 0; /* default! */ + repeatsOp = 0; + condCodeIsPartOfName=0; + state->commNum = 0; + state->tcnt = 0; + state->acnt = 0; + state->flow = noflow; + ignoreFirstOpd = 0; + + if (state->commentBuffer) + state->commentBuffer[0] = '\0'; + + switch (state->_opcode) + { + case op_LD0: + switch (BITS (state->words[0],1,2)) + { + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = 5; + break; + + case op_LD1: + if (BIT (state->words[0],13)) + { + instrName = "lr"; + decodingClass = 10; + } + else + { + switch (BITS (state->words[0],10,11)) { - (*func) (stream, "%c", *syn); - continue; + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (1[3])"; + state->flow = invalid_instr; + break; } - - /* We have an operand. Fetch any special modifiers. */ - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) + decodingClass = 6; + } + break; + + case op_ST: + if (BIT (state->words[0],25)) + { + instrName = "sr"; + decodingClass = 8; + } + else + { + switch (BITS (state->words[0],22,23)) + { + case 0: + instrName = "st"; + break; + case 1: + instrName = "stb"; + break; + case 2: + instrName = "stw"; + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = 7; + } + break; + + case op_3: + decodingClass = 1; /* default for opcode 3... */ + switch (FIELDC (state->words[0])) + { + case 0: + instrName = "flag"; + decodingClass = 2; + break; + case 1: + instrName = "asr"; + break; + case 2: + instrName = "lsr"; + break; + case 3: + instrName = "ror"; + break; + case 4: + instrName = "rrc"; + break; + case 5: + instrName = "sexb"; + break; + case 6: + instrName = "sexw"; + break; + case 7: + instrName = "extb"; + break; + case 8: + instrName = "extw"; + break; + case 0x3f: + { + decodingClass = 9; + switch( FIELDD (state->words[0]) ) + { + case 0: + instrName = "brk"; + break; + case 1: + instrName = "sleep"; + break; + case 2: + instrName = "swi"; + break; + default: + instrName = "???"; + state->flow=invalid_instr; + break; + } + } + break; + + /* ARC Extension Library Instructions + NOTE: We assume that extension codes are these instrs. */ + default: + instrName = instruction_name (state, + state->_opcode, + FIELDC (state->words[0]), + & flags); + if (!instrName) { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; + instrName = "???"; + state->flow = invalid_instr; } - operand = arc_operands + arc_operand_map[c]; + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + break; - /* Extract the value from the instruction. */ - opval = NULL; - if (operand->extract) + case op_BC: + instrName = "b"; + case op_BLC: + if (!instrName) + instrName = "bl"; + case op_LPC: + if (!instrName) + instrName = "lp"; + case op_JC: + if (!instrName) + { + if (BITS (state->words[0],9,9)) { - value = (*operand->extract) (insn, operand, mods, - &opval, (int *) NULL); + instrName = "jl"; + is_linked = 1; } - else + else { - value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & (1 << (operand->bits - 1)))) - value -= 1 << operand->bits; - - /* If this is a suffix operand, set `opval'. */ - if (operand->flags & ARC_OPERAND_SUFFIX) - opval = arc_opcode_lookup_suffix (operand, value); + instrName = "j"; + is_linked = 0; } + } + condCodeIsPartOfName = 1; + decodingClass = ((state->_opcode == op_JC) ? 4 : 3); + state->isBranch = 1; + break; + + case op_ADD: + case op_ADC: + case op_AND: + repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); + decodingClass = 0; - /* Print the operand as directed by the flags. */ - if (operand->flags & ARC_OPERAND_FAKE) - ; /* nothing to do (??? at least not yet) */ - else if (operand->flags & ARC_OPERAND_SUFFIX) - { - /* Default suffixes aren't printed. Fortunately, they all have - zero values. Also, zero values for boolean suffixes are - represented by the absence of text. */ + switch (state->_opcode) + { + case op_ADD: + instrName = (repeatsOp ? "asl" : "add"); + break; + case op_ADC: + instrName = (repeatsOp ? "rlc" : "adc"); + break; + case op_AND: + instrName = (repeatsOp ? "mov" : "and"); + break; + } + break; + + case op_SUB: instrName = "sub"; + break; + case op_SBC: instrName = "sbc"; + break; + case op_OR: instrName = "or"; + break; + case op_BIC: instrName = "bic"; + break; - if (value != 0) - { - /* ??? OPVAL should have a value. If it doesn't just cope - as we want disassembly to be reasonably robust. - Also remember that several condition code values (16-31) - aren't defined yet. For these cases just print the - number suitably decorated. */ - if (opval) - (*func) (stream, "%s%s", - mods & ARC_MOD_DOT ? "." : "", - opval->name); - else - (*func) (stream, "%s%c%d", - mods & ARC_MOD_DOT ? "." : "", - operand->fmt, value); - } + case op_XOR: + if (state->words[0] == 0x7fffffff) + { + /* nop encoded as xor -1, -1, -1 */ + instrName = "nop"; + decodingClass = 9; + } + else + instrName = "xor"; + break; + + default: + instrName = instruction_name (state,state->_opcode,0,&flags); + /* if (instrName) printf("FLAGS=0x%x\n", flags); */ + if (!instrName) + { + instrName = "???"; + state->flow=invalid_instr; + } + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + + fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ + flag = cond = is_shimm = is_limm = 0; + state->nullifyMode = BR_exec_when_no_jump; /* 0 */ + signExtend = addrWriteBack = directMem = 0; + usesAuxReg = 0; + + switch (decodingClass) + { + case 0: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + if (!repeatsOp) + CHECK_FIELD_C (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + WRITE_NOP_COMMENT (); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + } + else + { + WRITE_FORMAT_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); + } + write_comments (); + break; + + case 1: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + WRITE_NOP_COMMENT (); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + } + else + { + WRITE_FORMAT_x (B); + my_sprintf (state, state->operandBuffer, formatString, fieldB); + } + write_comments (); + break; + + case 2: + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + flag = 0; /* this is the FLAG instruction -- it's redundant */ + + write_instr_name (); + WRITE_FORMAT_x (B); + my_sprintf (state, state->operandBuffer, formatString, fieldB); + write_comments (); + break; + + case 3: + fieldA = BITS (state->words[0],7,26) << 2; + fieldA = (fieldA << 10) >> 10; /* make it signed */ + fieldA += addr + 4; + CHECK_FLAG_COND_NULLIFY (); + flag = 0; + + write_instr_name (); + /* This address could be a label we know. Convert it. */ + if (state->_opcode != op_LPC /* LP */) + { + add_target (fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BLC /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; + lr dest<- func addr; j [dest]" */ + } + + strcat (formatString, "%s"); /* address/label name */ + my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA)); + write_comments (); + break; + + case 4: + /* For op_JC -- jump to address specified. + Also covers jump and link--bit 9 of the instr. word + selects whether linked, thus "is_linked" is set above. */ + fieldA = 0; + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + if (!fieldBisReg) + { + fieldAisReg = 0; + fieldA = (fieldB >> 25) & 0x7F; /* flags */ + fieldB = (fieldB & 0xFFFFFF) << 2; + state->flow = is_linked ? direct_call : direct_jump; + add_target (fieldB); + /* screwy JLcc requires .jd mode to execute correctly + * but we pretend it is .nd (no delay slot). */ + if (is_linked && state->nullifyMode == BR_exec_when_jump) + state->nullifyMode = BR_exec_when_no_jump; + } + else + { + state->flow = is_linked ? indirect_call : indirect_jump; + /* We should also treat this as indirect call if NOT linked + * but the preceding instruction was a "lr blink,[status]" + * and we have a delay slot with "add blink,blink,2". + * For now we can't detect such. */ + state->register_for_indirect_jump = fieldB; + } + + write_instr_name (); + strcat (formatString, + IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ + if (fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x (A); + } + if (IS_REG (B)) + my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + else + my_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldB), fieldA); + write_comments (); + break; + + case 5: + /* LD instruction. + B and C can be regs, or one (both?) can be limm. */ + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FIELD_C (); + if (dbg) + printf ("5:b reg %d %d c reg %d %d \n", + fieldBisReg,fieldB,fieldCisReg,fieldC); + state->_offset = 0; + state->_ea_present = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + else + state->_offset += fieldB; + if (fieldCisReg) + state->ea_reg2 = fieldC; + else + state->_offset += fieldC; + state->_mem_load = 1; + + directMem = BIT (state->words[0],5); + addrWriteBack = BIT (state->words[0],3); + signExtend = BIT (state->words[0],0); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB(A); + if (fieldBisReg || fieldB != 0) + WRITE_FORMAT_x_COMMA (B); + else + fieldB = fieldC; + + WRITE_FORMAT_x_RB (C); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + write_comments (); + break; + + case 6: + /* LD instruction. */ + CHECK_FIELD_B (); + CHECK_FIELD_A (); + fieldC = FIELDD (state->words[0]); + + if (dbg) + printf ("6:b reg %d %d c 0x%x \n", + fieldBisReg, fieldB, fieldC); + state->_ea_present = 1; + state->_offset = fieldC; + state->_mem_load = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldC) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT (state->words[0],14); + addrWriteBack = BIT (state->words[0],12); + signExtend = BIT (state->words[0],9); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB (B); + } + else + { + WRITE_FORMAT_x (B); + if (fieldC != 0 && !BIT (state->words[0],13)) + { + fieldCisReg = 0; + WRITE_FORMAT_COMMA_x_RB (C); } - else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) - (*info->print_address_func) (pc + 4 + value, info); - /* ??? Not all cases of this are currently caught. */ - else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (operand->flags & ARC_OPERAND_ADDRESS) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (opval) - /* Note that this case catches both normal and auxiliary regs. */ - (*func) (stream, "%s", opval->name); else - (*func) (stream, "%ld", value); + WRITE_FORMAT_RB (); } - - /* We have found and printed an instruction; return. */ - return got_limm_p ? 8 : 4; + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + write_comments (); + break; + + case 7: + /* ST instruction. */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + fieldA = FIELDD(state->words[0]); /* shimm */ + + /* [B,A offset] */ + if (dbg) printf("7:b reg %d %x off %x\n", + fieldBisReg,fieldB,fieldA); + state->_ea_present = 1; + state->_offset = fieldA; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldA) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. + (for is_limm we do the name translation here). */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT(state->words[0],26); + addrWriteBack = BIT(state->words[0],24); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(C); + + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB(B); + } + else + { + WRITE_FORMAT_x(B); + if (fieldBisReg && fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x_RB(A); + } + else + WRITE_FORMAT_RB(); + } + my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); + write_comments2(fieldA); + break; + case 8: + /* SR instruction */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(C); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(B); + WRITE_FORMAT_RB(); + my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); + write_comments(); + break; + + case 9: + write_instr_name(); + state->operandBuffer[0] = '\0'; + break; + + case 10: + /* LR instruction */ + CHECK_FIELD_A(); + CHECK_FIELD_B(); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(A); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(B); + WRITE_FORMAT_RB(); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + write_comments(); + break; + + case 11: + CHECK_COND(); + write_instr_name(); + state->operandBuffer[0] = '\0'; + break; + + default: + mwerror (state, "Bad decoding class in ARC disassembler"); + break; } + + state->_cond = cond; + return state->instructionLen = offset; +} + - (*func) (stream, _("*unknown*")); - return 4; +/* Returns the name the user specified core extension register. */ +static const char * +_coreRegName(arg, regval) + void * arg ATTRIBUTE_UNUSED; + int regval; +{ + return arcExtMap_coreRegName (regval); } -/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use. - This does things a non-standard way (the "standard" way would be to copy - this code into disassemble.c). Since there are more than a couple of - variants, hiding all this crud here seems cleaner. */ +/* Returns the name the user specified AUX extension register. */ +static const char * +_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_auxRegName(regval); +} -disassembler_ftype -arc_get_disassembler (mach, big_p) - int mach; - int big_p; + +/* Returns the name the user specified condition code name. */ +static const char * +_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) { - switch (mach) - { - case bfd_mach_arc_base: - return big_p ? print_insn_arc_base_big : print_insn_arc_base_little; - } - return print_insn_arc_base_little; + return arcExtMap_condCodeName(regval); } -static int -print_insn_arc_base_little (pc, info) - bfd_vma pc; - disassemble_info *info; +/* Returns the name the user specified extension instruction. */ +static const char * +_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) { - return print_insn (pc, info, bfd_mach_arc_base, 0); + return arcExtMap_instName(majop, minop, flags); } +/* Decode an instruction returning the size of the instruction + in bytes or zero if unrecognized. */ static int -print_insn_arc_base_big (pc, info) - bfd_vma pc; - disassemble_info *info; +decodeInstr (address, info) + bfd_vma address; /* Address of this instruction. */ + disassemble_info * info; +{ + int status; + bfd_byte buffer[4]; + struct arcDisState s; /* ARC Disassembler state */ + void *stream = info->stream; /* output stream */ + fprintf_ftype func = info->fprintf_func; + int bytes; + + memset (&s, 0, sizeof(struct arcDisState)); + + /* read first instruction */ + status = (*info->read_memory_func) (address, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, address, info); + return 0; + } + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[0] = bfd_getl32(buffer); + else + s.words[0] = bfd_getb32(buffer); + /* always read second word in case of limm */ + + /* we ignore the result since last insn may not have a limm */ + status = (*info->read_memory_func) (address + 4, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[1] = bfd_getl32(buffer); + else + s.words[1] = bfd_getb32(buffer); + + s._this = &s; + s.coreRegName = _coreRegName; + s.auxRegName = _auxRegName; + s.condCodeName = _condCodeName; + s.instName = _instName; + + /* disassemble */ + bytes = dsmOneArcInst(address, (void *)&s); + + /* display the disassembly instruction */ + (*func) (stream, "%08x ", s.words[0]); + (*func) (stream, " "); + + (*func) (stream, "%-10s ", s.instrBuffer); + + if (__TRANSLATION_REQUIRED(s)) + { + bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + (*info->print_address_func) ((bfd_vma) addr, info); + (*func) (stream, "\n"); + } + else + (*func) (stream, "%s",s.operandBuffer); + return s.instructionLen; +} + +/* Return the print_insn function to use. + Side effect: load (possibly empty) extension section */ + +disassembler_ftype +arc_get_disassembler (void *ptr) { - return print_insn (pc, info, bfd_mach_arc_base, 1); + if (ptr) + build_ARC_extmap (ptr); + return decodeInstr; } diff --git a/gnu/usr.bin/binutils/opcodes/arc-dis.h b/gnu/usr.bin/binutils/opcodes/arc-dis.h new file mode 100644 index 00000000000..04bfbbb00fe --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/arc-dis.h @@ -0,0 +1,81 @@ +/* Disassembler structures definitions for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ARCDIS_H +#define ARCDIS_H + +enum +{ + BR_exec_when_no_jump, + BR_exec_always, + BR_exec_when_jump +}; + +enum Flow +{ + noflow, + direct_jump, + direct_call, + indirect_jump, + indirect_call, + invalid_instr +}; + +enum { no_reg = 99 }; +enum { allOperandsSize = 256 }; + +struct arcDisState +{ + void *_this; + int instructionLen; + void (*err)(void*, const char*); + const char *(*coreRegName)(void*, int); + const char *(*auxRegName)(void*, int); + const char *(*condCodeName)(void*, int); + const char *(*instName)(void*, int, int, int*); + + unsigned char* instruction; + unsigned index; + const char *comm[6]; /* instr name, cond, NOP, 3 operands */ + int opWidth; + int targets[4]; + int addresses[4]; + /* Set as a side-effect of calling the disassembler. + Used only by the debugger. */ + enum Flow flow; + int register_for_indirect_jump; + int ea_reg1, ea_reg2, _offset; + int _cond, _opcode; + unsigned long words[2]; + char *commentBuffer; + char instrBuffer[40]; + char operandBuffer[allOperandsSize]; + char _ea_present; + char _mem_load; + char _load_len; + char nullifyMode; + unsigned char commNum; + unsigned char isBranch; + unsigned char tcnt; + unsigned char acnt; +}; + +#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) + +#endif diff --git a/gnu/usr.bin/binutils/opcodes/arc-ext.c b/gnu/usr.bin/binutils/opcodes/arc-ext.c new file mode 100644 index 00000000000..1a53da93603 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/arc-ext.c @@ -0,0 +1,259 @@ +/* ARC target-dependent stuff. Extension structure access functions + Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <stdlib.h> +#include <stdio.h> +#include "bfd.h" +#include "arc-ext.h" +#include "libiberty.h" + +/* Extension structure */ +static struct arcExtMap arc_extension_map; + +/* Get the name of an extension instruction. */ + +const char * +arcExtMap_instName(int opcode, int minor, int *flags) +{ + if (opcode == 3) + { + /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ + if (minor < 0x09 || minor == 0x3f) + return 0; + else + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + } + else + if (opcode < 0x10) + return 0; + else + opcode -= 0x10; + if (!arc_extension_map.instructions[opcode]) + return 0; + *flags = arc_extension_map.instructions[opcode]->flags; + return arc_extension_map.instructions[opcode]->name; +} + +/* Get the name of an extension core register. */ + +const char * +arcExtMap_coreRegName(int value) +{ + if (value < 32) + return 0; + return (const char *) arc_extension_map.coreRegisters[value-32]; +} + +/* Get the name of an extension condition code. */ + +const char * +arcExtMap_condCodeName(int value) +{ + if (value < 16) + return 0; + return (const char *) arc_extension_map.condCodes[value-16]; +} + +/* Get the name of an extension aux register. */ + +const char * +arcExtMap_auxRegName(long address) +{ + /* walk the list of aux reg names and find the name */ + struct ExtAuxRegister *r; + + for (r = arc_extension_map.auxRegisters; r; r = r->next) { + if (r->address == address) + return (const char *) r->name; + } + return 0; +} + +/* Recursively free auxilliary register strcture pointers until + the list is empty. */ + +static void +clean_aux_registers(struct ExtAuxRegister *r) +{ + if (r -> next) + { + clean_aux_registers( r->next); + free(r -> name); + free(r -> next); + r ->next = NULL; + } + else + free(r -> name); +} + +/* Free memory that has been allocated for the extensions. */ + +static void +cleanup_ext_map(void) +{ + struct ExtAuxRegister *r; + struct ExtInstruction *insn; + int i; + + /* clean aux reg structure */ + r = arc_extension_map.auxRegisters; + if (r) + { + (clean_aux_registers(r)); + free(r); + } + + /* clean instructions */ + for (i = 0; i < NUM_EXT_INST; i++) + { + insn = arc_extension_map.instructions[i]; + if (insn) + free(insn->name); + } + + /* clean core reg struct */ + for (i = 0; i < NUM_EXT_CORE; i++) + { + if (arc_extension_map.coreRegisters[i]) + free(arc_extension_map.coreRegisters[i]); + } + + for (i = 0; i < NUM_EXT_COND; i++) { + if (arc_extension_map.condCodes[i]) + free(arc_extension_map.condCodes[i]); + } + + memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); +} + +int +arcExtMap_add(void *base, unsigned long length) +{ + unsigned char *block = base; + unsigned char *p = block; + + /* Clean up and reset everything if needed. */ + cleanup_ext_map(); + + while (p && p < (block + length)) + { + /* p[0] == length of record + p[1] == type of record + For instructions: + p[2] = opcode + p[3] = minor opcode (if opcode == 3) + p[4] = flags + p[5]+ = name + For core regs and condition codes: + p[2] = value + p[3]+ = name + For aux regs: + p[2..5] = value + p[6]+ = name + (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ + + if (p[0] == 0) + return -1; + + switch (p[1]) + { + case EXT_INSTRUCTION: + { + char opcode = p[2]; + char minor = p[3]; + char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); + struct ExtInstruction * insn = + (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); + + if (opcode==3) + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + else + opcode -= 0x10; + insn -> flags = (char) *(p+4); + strcpy(insn_name, (p+5)); + insn -> name = insn_name; + arc_extension_map.instructions[(int) opcode] = insn; + } + break; + + case EXT_CORE_REGISTER: + { + char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); + + strcpy(core_name, (p+3)); + arc_extension_map.coreRegisters[p[2]-32] = core_name; + } + break; + + case EXT_COND_CODE: + { + char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); + strcpy(cc_name, (p+3)); + arc_extension_map.condCodes[p[2]-16] = cc_name; + } + break; + + case EXT_AUX_REGISTER: + { + /* trickier -- need to store linked list to these */ + struct ExtAuxRegister *newAuxRegister = + (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); + char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); + + strcpy (aux_name, (p+6)); + newAuxRegister->name = aux_name; + newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; + newAuxRegister->next = arc_extension_map.auxRegisters; + arc_extension_map.auxRegisters = newAuxRegister; + } + break; + + default: + return -1; + + } + p += p[0]; /* move to next record */ + } + + return 0; +} + +/* Load hw extension descibed in .extArcMap ELF section. */ + +void +build_ARC_extmap (text_bfd) + bfd *text_bfd; +{ + char *arcExtMap; + bfd_size_type count; + asection *p; + + for (p = text_bfd->sections; p != NULL; p = p->next) + if (!strcmp (p->name, ".arcextmap")) + { + count = p->_raw_size; + arcExtMap = (char *) xmalloc (count); + if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) + { + arcExtMap_add ((PTR) arcExtMap, count); + break; + } + free ((PTR) arcExtMap); + } +} diff --git a/gnu/usr.bin/binutils/opcodes/arc-ext.h b/gnu/usr.bin/binutils/opcodes/arc-ext.h new file mode 100644 index 00000000000..bfe9750b60c --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/arc-ext.h @@ -0,0 +1,62 @@ +/* ARC target-dependent stuff. Extension data structures. + Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ARCEXT_H +#define ARCEXT_H + +enum {EXT_INSTRUCTION = 0}; +enum {EXT_CORE_REGISTER = 1}; +enum {EXT_AUX_REGISTER = 2}; +enum {EXT_COND_CODE = 3}; + +enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; +enum {NUM_EXT_CORE = 59-32+1}; +enum {NUM_EXT_COND = 0x1f-0x10+1}; + +struct ExtInstruction +{ + char flags; + char *name; +}; + +struct ExtAuxRegister +{ + long address; + char *name; + struct ExtAuxRegister *next; +}; + +struct arcExtMap +{ + struct ExtAuxRegister *auxRegisters; + struct ExtInstruction *instructions[NUM_EXT_INST]; + unsigned char *coreRegisters[NUM_EXT_CORE]; + unsigned char *condCodes[NUM_EXT_COND]; +}; + +extern int arcExtMap_add(void*, unsigned long); +extern const char *arcExtMap_coreRegName(int); +extern const char *arcExtMap_auxRegName(long); +extern const char *arcExtMap_condCodeName(int); +extern const char *arcExtMap_instName(int, int, int*); +extern void build_ARC_extmap(bfd *); + +#define IGNORE_FIRST_OPD 1 + +#endif diff --git a/gnu/usr.bin/binutils/opcodes/arc-opc.c b/gnu/usr.bin/binutils/opcodes/arc-opc.c index f17ffc086fe..c67cd8881a6 100644 --- a/gnu/usr.bin/binutils/opcodes/arc-opc.c +++ b/gnu/usr.bin/binutils/opcodes/arc-opc.c @@ -1,7 +1,8 @@ /* Opcode table for the ARC. - Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. + Copyright 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) @@ -13,17 +14,12 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <stdio.h> -#include "sysdep.h" +#include "ansidecl.h" #include "opcode/arc.h" -#include "opintl.h" - -#ifndef NULL -#define NULL 0 -#endif #define INSERT_FN(fn) \ static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ @@ -36,22 +32,43 @@ static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ INSERT_FN (insert_reg); INSERT_FN (insert_shimmfinish); INSERT_FN (insert_limmfinish); -INSERT_FN (insert_shimmoffset); -INSERT_FN (insert_shimmzero); +INSERT_FN (insert_offset); +INSERT_FN (insert_base); +INSERT_FN (insert_st_syntax); +INSERT_FN (insert_ld_syntax); +INSERT_FN (insert_addr_wb); INSERT_FN (insert_flag); +INSERT_FN (insert_nullify); INSERT_FN (insert_flagfinish); INSERT_FN (insert_cond); INSERT_FN (insert_forcelimm); INSERT_FN (insert_reladdr); INSERT_FN (insert_absaddr); +INSERT_FN (insert_jumpflags); INSERT_FN (insert_unopmacro); EXTRACT_FN (extract_reg); +EXTRACT_FN (extract_ld_offset); +EXTRACT_FN (extract_ld_syntax); +EXTRACT_FN (extract_st_offset); +EXTRACT_FN (extract_st_syntax); EXTRACT_FN (extract_flag); EXTRACT_FN (extract_cond); EXTRACT_FN (extract_reladdr); +EXTRACT_FN (extract_jumpflags); EXTRACT_FN (extract_unopmacro); +enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; + +#define OPERANDS 3 + +enum operand ls_operand[OPERANDS]; + +#define LS_VALUE 0 +#define LS_DEST 0 +#define LS_BASE 1 +#define LS_OFFSET 2 + /* Various types of ARC operands, including insn suffixes. */ /* Insn format values: @@ -61,8 +78,13 @@ EXTRACT_FN (extract_unopmacro); 'c' REGC register C field 'S' SHIMMFINISH finish inserting a shimm value 'L' LIMMFINISH finish inserting a limm value - 'd' SHIMMOFFSET shimm offset in ld,st insns - '0' SHIMMZERO 0 shimm value in ld,st insns + 'o' OFFSET offset in st insns + 'O' OFFSET offset in ld insns + '0' SYNTAX_ST_NE enforce store insn syntax, no errors + '1' SYNTAX_LD_NE enforce load insn syntax, no errors + '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only + '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only + 's' BASE base in st insn 'f' FLAG F flag 'F' FLAGFINISH finish inserting the F flag 'G' FLAGINSN insert F flag in "flag" insn @@ -71,6 +93,7 @@ EXTRACT_FN (extract_unopmacro); 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm 'B' BRANCH branch address (22 bit pc relative) 'J' JUMP jump address (26 bit absolute) + 'j' JUMPFLAGS optional high order bits of 'J' 'z' SIZE1 size field in ld a,[b,c] 'Z' SIZE10 size field in ld a,[b,shimm] 'y' SIZE22 size field in st c,[b,shimm] @@ -92,28 +115,27 @@ EXTRACT_FN (extract_unopmacro); Fields are: - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN -*/ + CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ const struct arc_operand arc_operands[] = { -/* place holder (??? not sure if needed) */ +/* place holder (??? not sure if needed). */ #define UNUSED 0 - { 0 }, + { 0, 0, 0, 0, 0, 0 }, -/* register A or shimm/limm indicator */ +/* register A or shimm/limm indicator. */ #define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, + { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* register B or shimm/limm indicator */ +/* register B or shimm/limm indicator. */ #define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, + { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* register C or shimm/limm indicator */ +/* register C or shimm/limm indicator. */ #define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, + { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* fake operand used to insert shimm value into most instructions */ +/* fake operand used to insert shimm value into most instructions. */ #define SHIMMFINISH (REGC + 1) { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, @@ -121,123 +143,141 @@ const struct arc_operand arc_operands[] = #define LIMMFINISH (SHIMMFINISH + 1) { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, -/* shimm operand when there is no reg indicator (ld,st) */ -#define SHIMMOFFSET (LIMMFINISH + 1) - { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 }, +/* shimm operand when there is no reg indicator (st). */ +#define ST_OFFSET (LIMMFINISH + 1) + { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, + +/* shimm operand when there is no reg indicator (ld). */ +#define LD_OFFSET (ST_OFFSET + 1) + { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, + +/* operand for base. */ +#define BASE (LD_OFFSET + 1) + { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, + +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST_NE (BASE + 1) + { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, + +/* 1 enforce syntax for ld insns. */ +#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) + { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, -/* 0 shimm operand for ld,st insns */ -#define SHIMMZERO (SHIMMOFFSET + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 }, +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST (SYNTAX_LD_NE + 1) + { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, -/* flag update bit (insertion is defered until we know how) */ -#define FLAG (SHIMMZERO + 1) +/* 0 enforce syntax for ld insns. */ +#define SYNTAX_LD (SYNTAX_ST + 1) + { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, + +/* flag update bit (insertion is defered until we know how). */ +#define FLAG (SYNTAX_LD + 1) { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, -/* fake utility operand to finish 'f' suffix handling */ +/* fake utility operand to finish 'f' suffix handling. */ #define FLAGFINISH (FLAG + 1) { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, -/* fake utility operand to set the 'f' flag for the "flag" insn */ +/* fake utility operand to set the 'f' flag for the "flag" insn. */ #define FLAGINSN (FLAGFINISH + 1) { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, -/* branch delay types */ +/* branch delay types. */ #define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX }, + { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, -/* conditions */ +/* conditions. */ #define COND (DELAY + 1) { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, -/* set `cond_p' to 1 to ensure a constant is treated as a limm */ +/* set `cond_p' to 1 to ensure a constant is treated as a limm. */ #define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm }, + { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, -/* branch address; b, bl, and lp insns */ +/* branch address; b, bl, and lp insns. */ #define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr }, + { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, /* jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2) */ + value is right shifted by 2). */ #define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr }, + { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, + +/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ +#define JUMPFLAGS (JUMP + 1) + { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, -/* size field, stored in bit 1,2 */ -#define SIZE1 (JUMP + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX }, +/* size field, stored in bit 1,2. */ +#define SIZE1 (JUMPFLAGS + 1) + { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, -/* size field, stored in bit 10,11 */ +/* size field, stored in bit 10,11. */ #define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, }, + { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, -/* size field, stored in bit 22,23 */ +/* size field, stored in bit 22,23. */ #define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, }, + { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, -/* sign extend field, stored in bit 0 */ +/* sign extend field, stored in bit 0. */ #define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX }, + { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, -/* sign extend field, stored in bit 9 */ +/* sign extend field, stored in bit 9. */ #define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX }, + { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, -/* address write back, stored in bit 3 */ +/* address write back, stored in bit 3. */ #define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX }, + { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* address write back, stored in bit 12 */ +/* address write back, stored in bit 12. */ #define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX }, + { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* address write back, stored in bit 24 */ +/* address write back, stored in bit 24. */ #define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX }, + { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* cache bypass, stored in bit 5 */ +/* cache bypass, stored in bit 5. */ #define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX }, + { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, -/* cache bypass, stored in bit 14 */ +/* cache bypass, stored in bit 14. */ #define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX }, + { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, -/* cache bypass, stored in bit 26 */ +/* cache bypass, stored in bit 26. */ #define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX }, + { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, -/* unop macro, used to copy REGB to REGC */ +/* unop macro, used to copy REGB to REGC. */ #define UNOPMACRO (CACHEBYPASS26 + 1) { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, /* '.' modifier ('.' required). */ #define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT }, + { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, /* Dummy 'r' modifier for the register table. It's called a "dummy" because there's no point in inserting an 'r' into all the %a/%b/%c occurrences in the insn table. */ #define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG }, + { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, /* Known auxiliary register modifier (stored in shimm field). */ #define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG }, + { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, -/* end of list place holder */ - { 0 } +/* end of list place holder. */ + { 0, 0, 0, 0, 0, 0 } }; /* Given a format letter, yields the index into `arc_operands'. eg: arc_operand_map['a'] = REGA. */ unsigned char arc_operand_map[256]; -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - /* ARC instructions. Longer versions of insns must appear before shorter ones (if gas sees @@ -246,110 +286,141 @@ unsigned char arc_operand_map[256]; Instructions that are really macros based on other insns must appear before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. - - This table is best viewed on a wide screen (161 columns). I'd prefer to - keep it this way. The rest of the file, however, should be viewable on an - 80 column terminal. */ - -/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has - a more general facility for dealing with macros which could be used if - we need to. */ - -/* This table can't be `const' because members `next_asm' and `next_dis' are - computed at run-time. We could split this into two, but that doesn't seem - worth it. */ + insn is really the `and' insn. */ -struct arc_opcode arc_opcodes[] = { +struct arc_opcode arc_opcodes[] = +{ + /* Base case instruction set (core versions 5-8) */ - /* Macros appear first. */ /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) }, + { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, + { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, + { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, /* "nop" is really an "xor". */ - { "nop", 0xffffffff, 0x7fffffff }, + { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) }, - - /* The rest of these needn't be sorted, but it helps to find them if they are. */ - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) }, - { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH }, - { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) }, - { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) }, - /* %Q: force cond_p=1 --> no shimm values */ - /* ??? This insn allows an optional flags spec. */ - { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. */ - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) }, - { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) }, - { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) }, - { "lp%q%.n %B", I(-1), I(6), }, - { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) }, - { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) }, - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) }, - { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) } + { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, + { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, + { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, + { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, + { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, + { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, + { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, + { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, + { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, + { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, + /* %Q: force cond_p=1 -> no shimm values. This insn allows an + optional flags spec. */ + { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* This insn allows an optional flags spec. */ + { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* Put opcode 1 ld insns first so shimm gets prefered over limm. + "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, + { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, + { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, + { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, + { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, + { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, + { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, + { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, + { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, + { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, + { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, + /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, + { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } }; + const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); const struct arc_operand_value arc_reg_names[] = { - /* Sort this so that the first 61 entries are sequential. - IE: For each i (i<61), arc_reg_names[i].value == i. */ - - { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG }, - { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG }, - { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG }, - { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG }, - { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG }, - { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG }, - { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG }, - { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG }, - { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG }, - { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG }, - { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG }, - { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG }, - { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG }, - { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG }, - { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG }, - { "lp_count", 60, REG }, - - /* I'd prefer to output these as "fp" and "sp" by default, but we still need - to recognize the canonical values. */ - { "r27", 27, REG }, { "r28", 28, REG }, - - /* Someone may wish to refer to these in this way, and it's probably a - good idea to reserve them as such anyway. */ - { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG }, - - /* Standard auxiliary registers. */ - { "status", 0, AUXREG }, - { "semaphore", 1, AUXREG }, - { "lp_start", 2, AUXREG }, - { "lp_end", 3, AUXREG }, - { "identity", 4, AUXREG }, - { "debug", 5, AUXREG }, + /* Core register set r0-r63. */ + + /* r0-r28 - general purpose registers. */ + { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, + { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, + { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, + { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, + { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, + { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, + { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, + { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, + { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, + { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink1", 29, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink2", 30, REG, 0 }, + /* Branch-link register. */ + { "blink", 31, REG, 0 }, + + /* r32-r59 reserved for extensions. */ + { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, + { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, + { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, + { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, + { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, + { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, + { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, + { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, + { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, + { "r59", 59, REG, 0 }, + + /* Loop count register (24 bits). */ + { "lp_count", 60, REG, 0 }, + /* Short immediate data indicator setting flags. */ + { "r61", 61, REG, ARC_REGISTER_READONLY }, + /* Long immediate data indicator setting flags. */ + { "r62", 62, REG, ARC_REGISTER_READONLY }, + /* Short immediate data indicator not setting flags. */ + { "r63", 63, REG, ARC_REGISTER_READONLY }, + + /* Small-data base register. */ + { "gp", 26, REG, 0 }, + /* Frame pointer. */ + { "fp", 27, REG, 0 }, + /* Stack pointer. */ + { "sp", 28, REG, 0 }, + + { "r29", 29, REG, 0 }, + { "r30", 30, REG, 0 }, + { "r31", 31, REG, 0 }, + { "r60", 60, REG, 0 }, + + /* Auxiliary register set. */ + + /* Auxiliary register address map: + 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation + 0xfffffeff-0x80000000 - customer limm allocation + 0x7fffffff-0x00000100 - ARC limm allocation + 0x000000ff-0x00000000 - ARC shimm allocation */ + + /* Base case auxiliary registers (shimm address). */ + { "status", 0x00, AUXREG, 0 }, + { "semaphore", 0x01, AUXREG, 0 }, + { "lp_start", 0x02, AUXREG, 0 }, + { "lp_end", 0x03, AUXREG, 0 }, + { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, + { "debug", 0x05, AUXREG, 0 }, }; -const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + +const int arc_reg_names_count = + sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); /* The suffix table. Operands with the same name must be stored together. */ @@ -357,58 +428,64 @@ const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0 const struct arc_operand_value arc_suffixes[] = { /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1 }, - { "al", 0, COND }, - { "ra", 0, COND }, - { "eq", 1, COND }, - { "z", 1, COND }, - { "ne", 2, COND }, - { "nz", 2, COND }, - { "p", 3, COND }, - { "pl", 3, COND }, - { "n", 4, COND }, - { "mi", 4, COND }, - { "c", 5, COND }, - { "cs", 5, COND }, - { "lo", 5, COND }, - { "nc", 6, COND }, - { "cc", 6, COND }, - { "hs", 6, COND }, - { "v", 7, COND }, - { "vs", 7, COND }, - { "nv", 8, COND }, - { "vc", 8, COND }, - { "gt", 9, COND }, - { "ge", 10, COND }, - { "lt", 11, COND }, - { "le", 12, COND }, - { "hi", 13, COND }, - { "ls", 14, COND }, - { "pnz", 15, COND }, - { "f", 1, FLAG }, - { "nd", ARC_DELAY_NONE, DELAY }, - { "d", ARC_DELAY_NORMAL, DELAY }, - { "jd", ARC_DELAY_JUMP, DELAY }, -/*{ "b", 7, SIZEEXT },*/ -/*{ "b", 5, SIZESEX },*/ - { "b", 1, SIZE1 }, - { "b", 1, SIZE10 }, - { "b", 1, SIZE22 }, -/*{ "w", 8, SIZEEXT },*/ -/*{ "w", 6, SIZESEX },*/ - { "w", 2, SIZE1 }, - { "w", 2, SIZE10 }, - { "w", 2, SIZE22 }, - { "x", 1, SIGN0 }, - { "x", 1, SIGN9 }, - { "a", 1, ADDRESS3 }, - { "a", 1, ADDRESS12 }, - { "a", 1, ADDRESS24 }, - { "di", 1, CACHEBYPASS5 }, - { "di", 1, CACHEBYPASS14 }, - { "di", 1, CACHEBYPASS26 }, + { "", 0, -1, 0 }, + + /* Base case condition codes. */ + { "al", 0, COND, 0 }, + { "ra", 0, COND, 0 }, + { "eq", 1, COND, 0 }, + { "z", 1, COND, 0 }, + { "ne", 2, COND, 0 }, + { "nz", 2, COND, 0 }, + { "pl", 3, COND, 0 }, + { "p", 3, COND, 0 }, + { "mi", 4, COND, 0 }, + { "n", 4, COND, 0 }, + { "cs", 5, COND, 0 }, + { "c", 5, COND, 0 }, + { "lo", 5, COND, 0 }, + { "cc", 6, COND, 0 }, + { "nc", 6, COND, 0 }, + { "hs", 6, COND, 0 }, + { "vs", 7, COND, 0 }, + { "v", 7, COND, 0 }, + { "vc", 8, COND, 0 }, + { "nv", 8, COND, 0 }, + { "gt", 9, COND, 0 }, + { "ge", 10, COND, 0 }, + { "lt", 11, COND, 0 }, + { "le", 12, COND, 0 }, + { "hi", 13, COND, 0 }, + { "ls", 14, COND, 0 }, + { "pnz", 15, COND, 0 }, + + /* Condition codes 16-31 reserved for extensions. */ + + { "f", 1, FLAG, 0 }, + + { "nd", ARC_DELAY_NONE, DELAY, 0 }, + { "d", ARC_DELAY_NORMAL, DELAY, 0 }, + { "jd", ARC_DELAY_JUMP, DELAY, 0 }, + + { "b", 1, SIZE1, 0 }, + { "b", 1, SIZE10, 0 }, + { "b", 1, SIZE22, 0 }, + { "w", 2, SIZE1, 0 }, + { "w", 2, SIZE10, 0 }, + { "w", 2, SIZE22, 0 }, + { "x", 1, SIGN0, 0 }, + { "x", 1, SIGN9, 0 }, + { "a", 1, ADDRESS3, 0 }, + { "a", 1, ADDRESS12, 0 }, + { "a", 1, ADDRESS24, 0 }, + + { "di", 1, CACHEBYPASS5, 0 }, + { "di", 1, CACHEBYPASS14, 0 }, + { "di", 1, CACHEBYPASS26, 0 }, }; -const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); + +const int arc_suffixes_count = + sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); /* Indexed by first letter of opcode. Points to chain of opcodes with same first letter. */ @@ -429,10 +506,12 @@ arc_get_opcode_mach (bfd_mach, big_p) int bfd_mach, big_p; { static int mach_type_map[] = - { - ARC_MACH_BASE - }; - + { + ARC_MACH_5, + ARC_MACH_6, + ARC_MACH_7, + ARC_MACH_8 + }; return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); } @@ -453,8 +532,6 @@ arc_opcode_init_tables (flags) /* We may be intentionally called more than once (for example gdb will call us each time the user switches cpu). These tables only need to be init'd once though. */ - /* ??? We can remove the need for arc_opcode_supported by taking it into - account here, but I'm not sure I want to do that yet (if ever). */ if (!init_p) { register int i,n; @@ -490,23 +567,7 @@ int arc_opcode_supported (opcode) const struct arc_opcode *opcode; { - if (ARC_OPCODE_CPU (opcode->flags) == 0) - return 1; - if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return non-zero if OPVAL is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opval_supported (opval) - const struct arc_operand_value *opval; -{ - if (ARC_OPVAL_CPU (opval->flags) == 0) - return 1; - if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type)) + if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) return 1; return 0; } @@ -535,14 +596,26 @@ static int flag_p; /* Nonzero if we've finished processing the 'f' suffix. */ static int flagshimm_handled_p; +/* Nonzero if we've seen a 'a' suffix (address writeback). */ +static int addrwb_p; + /* Nonzero if we've seen a 'q' suffix (condition code). */ static int cond_p; +/* Nonzero if we've inserted a nullify condition. */ +static int nullify_p; + +/* The value of the a nullify condition we inserted. */ +static int nullify; + +/* Nonzero if we've inserted jumpflags. */ +static int jumpflags_p; + /* Nonzero if we've inserted a shimm. */ static int shimm_p; /* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times. */ + appear multiple times). */ static int shimm; /* Nonzero if we've inserted a limm (during assembly) or seen a limm @@ -560,11 +633,20 @@ static long limm; void arc_opcode_init_insert () { + int i; + + for(i = 0; i < OPERANDS; i++) + ls_operand[i] = OP_NONE; + flag_p = 0; flagshimm_handled_p = 0; cond_p = 0; + addrwb_p = 0; shimm_p = 0; limm_p = 0; + jumpflags_p = 0; + nullify_p = 0; + nullify = 0; /* the default is important. */ } /* Called by the assembler to see if the insn has a limm operand. @@ -594,6 +676,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg) const char **errmsg; { static char buf[100]; + enum operand op_type = OP_NONE; if (reg == NULL) { @@ -609,16 +692,30 @@ insert_reg (insn, operand, mods, reg, value, errmsg) we have to use a limm. */ && (!shimm_p || shimm == value)) { - int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - flagshimm_handled_p = 1; - shimm_p = 1; - shimm = value; + int marker; + + op_type = OP_SHIMM; + /* forget about shimm as dest mlm. */ + + if ('a' != operand->fmt) + { + shimm_p = 1; + shimm = value; + flagshimm_handled_p = 1; + marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; + } + else + { + /* don't request flag setting on shimm as dest. */ + marker = ARC_REG_SHIMM; + } insn |= marker << operand->shift; - /* insn |= value & 511; - done later */ + /* insn |= value & 511; - done later. */ } /* We have to use a limm. If we've already seen one they must match. */ else if (!limm_p || limm == value) { + op_type = OP_LIMM; limm_p = 1; limm = value; insn |= ARC_REG_LIMM << operand->shift; @@ -626,7 +723,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg) } else { - *errmsg = _("unable to fit different valued constants into instruction"); + *errmsg = "unable to fit different valued constants into instruction"; } } else @@ -636,27 +733,66 @@ insert_reg (insn, operand, mods, reg, value, errmsg) if (reg->type == AUXREG) { if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); + *errmsg = "auxiliary register not allowed here"; else { + if ((insn & I(-1)) == I(2)) /* check for use validity. */ + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = "attempt to set readonly register"; + } + else + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = "attempt to read writeonly register"; + } insn |= ARC_REG_SHIMM << operand->shift; insn |= reg->value << arc_operands[reg->type].shift; } } else { + /* check for use validity. */ + if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = "attempt to set readonly register"; + } + if ('a' != operand->fmt) + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = "attempt to read writeonly register"; + } /* We should never get an invalid register number here. */ if ((unsigned int) reg->value > 60) { - /* xgettext:c-format */ - sprintf (buf, _("invalid register number `%d'"), reg->value); + sprintf (buf, "invalid register number `%d'", reg->value); *errmsg = buf; } - else - insn |= reg->value << operand->shift; + insn |= reg->value << operand->shift; + op_type = OP_REG; } } + switch (operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn & I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + return insn; } @@ -665,17 +801,33 @@ insert_reg (insn, operand, mods, reg, value, errmsg) static arc_insn insert_flag (insn, operand, mods, reg, value, errmsg) arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; { /* We can't store anything in the insn until we've parsed the registers. Just record the fact that we've got this flag. `insert_reg' will use it to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ flag_p = 1; + return insn; +} +/* Called when we see an nullify condition. */ + +static arc_insn +insert_nullify (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + nullify_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + nullify = value; return insn; } @@ -687,10 +839,10 @@ static arc_insn insert_flagfinish (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; { if (flag_p && !flagshimm_handled_p) { @@ -708,10 +860,10 @@ static arc_insn insert_cond (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; long value; - const char **errmsg; + const char **errmsg ATTRIBUTE_UNUSED; { cond_p = 1; insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; @@ -727,20 +879,82 @@ insert_cond (insn, operand, mods, reg, value, errmsg) static arc_insn insert_forcelimm (insn, operand, mods, reg, value, errmsg) arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + cond_p = 1; + return insn; +} + +static arc_insn +insert_addr_wb (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + addrwb_p = 1 << operand->shift; + return insn; +} + +static arc_insn +insert_base (insn, operand, mods, reg, value, errmsg) + arc_insn insn; const struct arc_operand *operand; int mods; const struct arc_operand_value *reg; long value; const char **errmsg; { - cond_p = 1; + if (reg != NULL) + { + arc_insn myinsn; + myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; + insn |= B(myinsn); + ls_operand[LS_BASE] = OP_REG; + } + else if (ARC_SHIMM_CONST_P (value) && !cond_p) + { + if (shimm_p && value != shimm) + { + /* convert the previous shimm operand to a limm. */ + limm_p = 1; + limm = shimm; + insn &= ~C(-1); /* we know where the value is in insn. */ + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + insn |= ARC_REG_SHIMM << operand->shift; + shimm_p = 1; + shimm = value; + ls_operand[LS_BASE] = OP_SHIMM; + } + else + { + if (limm_p && value != limm) + { + *errmsg = "too many long constants"; + return insn; + } + limm_p = 1; + limm = value; + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + return insn; } -/* Used in ld/st insns to handle the shimm offset field. */ +/* Used in ld/st insns to handle the offset field. We don't try to + match operand syntax here. we catch bad combinations later. */ static arc_insn -insert_shimmoffset (insn, operand, mods, reg, value, errmsg) +insert_offset (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; int mods; @@ -749,11 +963,15 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg) const char **errmsg; { long minval, maxval; - static char buf[100]; if (reg != NULL) { - *errmsg = "register appears where shimm value expected"; + arc_insn myinsn; + myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; + ls_operand[LS_OFFSET] = OP_REG; + if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */ + if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */ + insn |= C(myinsn); } else { @@ -769,35 +987,271 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg) minval = 0; maxval = (1 << operand->bits) - 1; } - if (value < minval || value > maxval) + if ((cond_p && !limm_p) || (value < minval || value > maxval)) { - /* xgettext:c-format */ - sprintf (buf, _("value won't fit in range %ld - %ld"), - minval, maxval); - *errmsg = buf; + if (limm_p && value != limm) + { + *errmsg = "too many long constants"; + } + else + { + limm_p = 1; + limm = value; + if (operand->flags & ARC_OPERAND_STORE) + insn |= B(ARC_REG_LIMM); + if (operand->flags & ARC_OPERAND_LOAD) + insn |= C(ARC_REG_LIMM); + ls_operand[LS_OFFSET] = OP_LIMM; + } } else - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + { + if ((value < minval || value > maxval)) + *errmsg = "need too many limms"; + else if (shimm_p && value != shimm) + { + /* check for bad operand combinations before we lose info about them. */ + if ((insn & I(-1)) == I(1)) + { + *errmsg = "to many shimms in load"; + goto out; + } + if (limm_p && operand->flags & ARC_OPERAND_LOAD) + { + *errmsg = "too many long constants"; + goto out; + } + /* convert what we thought was a shimm to a limm. */ + limm_p = 1; + limm = shimm; + if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~C(-1); + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~B(-1); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + } + shimm = value; + shimm_p = 1; + ls_operand[LS_OFFSET] = OP_SHIMM; + } } + out: return insn; } -/* Used in ld/st insns when the shimm offset is 0. */ +/* Used in st insns to do final disasemble syntax check. */ + +static long +extract_st_syntax (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ +#define ST_SYNTAX(V,B,O) \ +((ls_operand[LS_VALUE] == (V) && \ + ls_operand[LS_BASE] == (B) && \ + ls_operand[LS_OFFSET] == (O))) + + if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) + || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) + *invalid = 1; + return 0; +} + +int +arc_limm_fixup_adjust(insn) + arc_insn insn; +{ + int retval = 0; + + /* check for st shimm,[limm]. */ + if ((insn & (I(-1) | C(-1) | B(-1))) == + (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) + { + retval = insn & 0x1ff; + if (retval & 0x100) /* sign extend 9 bit offset. */ + retval |= ~0x1ff; + } + return -retval; /* negate offset for return. */ +} + +/* Used in st insns to do final syntax check. */ static arc_insn -insert_shimmzero (insn, operand, mods, reg, value, errmsg) +insert_st_syntax (insn, operand, mods, reg, value, errmsg) arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; const char **errmsg; { - shimm_p = 1; - shimm = 0; + if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) + { + /* change an illegal insn into a legal one, it's easier to + do it here than to try to handle it during operand scan. */ + limm_p = 1; + limm = shimm; + shimm_p = 0; + shimm = 0; + insn = insn & ~(C(-1) | 511); + insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; + ls_operand[LS_VALUE] = OP_LIMM; + } + + if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)) + { + /* try to salvage this syntax. */ + if (shimm & 0x1) /* odd shimms won't work. */ + { + if (limm_p) /* do we have a limm already? */ + { + *errmsg = "impossible store"; + } + limm_p = 1; + limm = shimm; + shimm = 0; + shimm_p = 0; + insn = insn & ~(B(-1) | 511); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + else + { + shimm >>= 1; + insn = insn & ~511; + insn |= shimm; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } + if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) + { + limm += arc_limm_fixup_adjust(insn); + } + if (ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) && (shimm * 2 == limm)) + { + insn &= ~C(-1); + limm_p = 0; + limm = 0; + insn |= C(ARC_REG_SHIMM); + ls_operand[LS_VALUE] = OP_SHIMM; + } + if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) + || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) + *errmsg = "st operand error"; + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = "address writeback not allowed"; + insn |= addrwb_p; + } + if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) + *errmsg = "store value must be zero"; + return insn; +} + +/* Used in ld insns to do final syntax check. */ + +static arc_insn +insert_ld_syntax (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg; +{ +#define LD_SYNTAX(D,B,O) \ +((ls_operand[LS_DEST] == (D) && \ + ls_operand[LS_BASE] == (B) && \ + ls_operand[LS_OFFSET] == (O))) + + int test = insn & I(-1); + + if (!(test == I(1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *errmsg = "invalid load/shimm insn"; + } + if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) + || LD_SYNTAX(OP_REG,OP_REG,OP_REG) + || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) + || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + *errmsg = "ld operand error"; + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = "address writeback not allowed"; + insn |= addrwb_p; + } return insn; } +/* Used in ld insns to do final syntax check. */ + +static long +extract_ld_syntax (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + int test = insn[0] & I(-1); + + if (!(test == I(1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *invalid = 1; + } + if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1))) + || LD_SYNTAX(OP_REG,OP_REG,OP_REG) + || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0)) + || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + *invalid = 1; + return 0; +} + /* Called at the end of processing normal insns (eg: add) to insert a shimm value (if present) into the insn. */ @@ -805,10 +1259,10 @@ static arc_insn insert_shimmfinish (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; { if (shimm_p) insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; @@ -830,14 +1284,51 @@ insert_shimmfinish (insn, operand, mods, reg, value, errmsg) static arc_insn insert_limmfinish (insn, operand, mods, reg, value, errmsg) arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ +#if 0 + if (limm_p) + ; /* nothing to do, gas does it. */ +#endif + return insn; +} + +static arc_insn +insert_jumpflags (insn, operand, mods, reg, value, errmsg) + arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; long value; const char **errmsg; { - if (limm_p) - ; /* nothing to do, gas does it */ + if (!flag_p) + { + *errmsg = "jump flags, but no .f seen"; + } + if (!limm_p) + { + *errmsg = "jump flags, but no limm addr"; + } + if (limm & 0xfc000000) + { + *errmsg = "flag bits of jump address limm lost"; + } + if (limm & 0x03000000) + { + *errmsg = "attempt to set HR bits"; + } + if ((value & ((1 << operand->bits) - 1)) != value) + { + *errmsg = "bad jump flags value"; + } + jumpflags_p = 1; + limm = ((limm & ((1 << operand->shift) - 1)) + | ((value & ((1 << operand->bits) - 1)) << operand->shift)); return insn; } @@ -847,10 +1338,10 @@ static arc_insn insert_unopmacro (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; { insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; return insn; @@ -862,13 +1353,13 @@ static arc_insn insert_reladdr (insn, operand, mods, reg, value, errmsg) arc_insn insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; long value; const char **errmsg; { if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); + *errmsg = "branch address not on 4 byte boundary"; insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; return insn; } @@ -878,23 +1369,42 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg) Note that this function is only intended to handle instructions (with 4 byte immediate operands). It is not intended to handle data. */ -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the +/* ??? Actually, there's little for us to do as we can't call frag_more, the caller must do that. The extract fns take a pointer to two words. The insert fns could be converted and then we could do something useful, but then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ + a 2 word quantity. That's too much so we don't handle them. + + We do check for correct usage of the nullify suffix, or we + set the default correctly, though. */ static arc_insn insert_absaddr (insn, operand, mods, reg, value, errmsg) arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; const char **errmsg; { if (limm_p) - ; /* nothing to do */ + { + /* if it is a jump and link, .jd must be specified. */ + if (insn & R(-1,9,1)) + { + if (!nullify_p) + { + insn |= 0x02 << 5; /* default nullify to .jd. */ + } + else + { + if (nullify != 0x02) + { + *errmsg = "must specify .jd or no nullify suffix"; + } + } + } + } return insn; } @@ -912,10 +1422,7 @@ static const struct arc_operand_value *lookup_register (int type, long regno); void arc_opcode_init_extract () { - flag_p = 0; - flagshimm_handled_p = 0; - shimm_p = 0; - limm_p = 0; + arc_opcode_init_insert(); } /* As we're extracting registers, keep an eye out for the 'f' indicator @@ -931,42 +1438,72 @@ extract_reg (insn, operand, mods, opval, invalid) const struct arc_operand *operand; int mods; const struct arc_operand_value **opval; - int *invalid; + int *invalid ATTRIBUTE_UNUSED; { int regno; long value; + enum operand op_type; /* Get the register number. */ - regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); + regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); /* Is it a constant marker? */ if (regno == ARC_REG_SHIMM) { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flagshimm_handled_p = 1; + op_type = OP_SHIMM; + /* always return zero if dest is a shimm mlm. */ + + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) + && (value & 256)) + value -= 512; + if (!flagshimm_handled_p) + flag_p = 0; + flagshimm_handled_p = 1; + } + else + { + value = 0; + } } else if (regno == ARC_REG_SHIMM_UPDATE) { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; + op_type = OP_SHIMM; + + /* always return zero if dest is a shimm mlm. */ + + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + } + else + { + value = 0; + } flag_p = 1; flagshimm_handled_p = 1; } else if (regno == ARC_REG_LIMM) { + op_type = OP_LIMM; value = insn[1]; limm_p = 1; + /* if this is a jump instruction (j,jl), show new pc correctly. */ + if (0x07 == ((*insn & I(-1)) >> 27)) + { + value = (value & 0xffffff); + } } /* It's a register, set OPVAL (that's the only way we distinguish registers from constants here). */ else { const struct arc_operand_value *reg = lookup_register (REG, regno); + op_type = OP_REG; if (reg == NULL) abort (); @@ -986,6 +1523,24 @@ extract_reg (insn, operand, mods, opval, invalid) if (reg != NULL && opval != NULL) *opval = reg; } + switch(operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn[0]& I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } return value; } @@ -997,9 +1552,9 @@ static long extract_flag (insn, operand, mods, opval, invalid) arc_insn *insn; const struct arc_operand *operand; - int mods; + int mods ATTRIBUTE_UNUSED; const struct arc_operand_value **opval; - int *invalid; + int *invalid ATTRIBUTE_UNUSED; { int f; const struct arc_operand_value *val; @@ -1007,12 +1562,12 @@ extract_flag (insn, operand, mods, opval, invalid) if (flagshimm_handled_p) f = flag_p != 0; else - f = (insn[0] & (1 << operand->shift)) != 0; + f = (*insn & (1 << operand->shift)) != 0; /* There is no text for zero values. */ if (f == 0) return 0; - + flag_p = 1; val = arc_opcode_lookup_suffix (operand, 1); if (opval != NULL && val != NULL) *opval = val; @@ -1028,9 +1583,9 @@ static long extract_cond (insn, operand, mods, opval, invalid) arc_insn *insn; const struct arc_operand *operand; - int mods; + int mods ATTRIBUTE_UNUSED; const struct arc_operand_value **opval; - int *invalid; + int *invalid ATTRIBUTE_UNUSED; { long cond; const struct arc_operand_value *val; @@ -1038,7 +1593,7 @@ extract_cond (insn, operand, mods, opval, invalid) if (flagshimm_handled_p) return 0; - cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); + cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); val = arc_opcode_lookup_suffix (operand, cond); /* Ignore NULL values of `val'. Several condition code values are @@ -1055,20 +1610,88 @@ static long extract_reladdr (insn, operand, mods, opval, invalid) arc_insn *insn; const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; { long addr; - addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); + addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); if ((operand->flags & ARC_OPERAND_SIGNED) && (addr & (1 << (operand->bits - 1)))) addr -= 1 << operand->bits; - return addr << 2; } +/* extract the flags bits from a j or jl long immediate. */ +static long +extract_jumpflags(insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + if (!flag_p || !limm_p) + *invalid = 1; + return ((flag_p && limm_p) + ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); +} + +/* extract st insn's offset. */ + +static long +extract_st_offset (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + int value = 0; + + if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + } + else + { + *invalid = 1; + } + return(value); +} + +/* extract ld insn's offset. */ + +static long +extract_ld_offset (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value **opval; + int *invalid; +{ + int test = insn[0] & I(-1); + int value; + + if (test) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + return(value); + } + /* if it isn't in the insn, it's concealed behind reg 'c'. */ + return extract_reg (insn, &arc_operands[arc_operand_map['c']], + mods, opval, invalid); +} + /* The only thing this does is set the `invalid' flag if B != C. This is needed because the "mov" macro appears before it's real insn "and" and we don't want the disassembler to confuse them. */ @@ -1076,19 +1699,18 @@ extract_reladdr (insn, operand, mods, opval, invalid) static long extract_unopmacro (insn, operand, mods, opval, invalid) arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; int *invalid; { /* This misses the case where B == ARC_REG_SHIMM_UPDATE && C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get printed as "and"s. */ - if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG)) + if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) + != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) if (invalid != NULL) *invalid = 1; - return 0; } @@ -1101,6 +1723,15 @@ arc_opcode_lookup_suffix (type, value) int value; { register const struct arc_operand_value *v,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (type == &arc_operands[ext_oper->operand.type] + && value == ext_oper->operand.value) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } /* ??? This is a little slow and can be speeded up. */ @@ -1117,6 +1748,14 @@ lookup_register (type, regno) long regno; { register const struct arc_operand_value *r,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (ext_oper->operand.type == type && ext_oper->operand.value == regno) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } if (type == REG) return &arc_reg_names[regno]; @@ -1129,3 +1768,58 @@ lookup_register (type, regno) return r; return 0; } + +int +arc_insn_is_j(insn) + arc_insn insn; +{ + return (insn & (I(-1))) == I(0x7); +} + +int +arc_insn_not_jl(insn) + arc_insn insn; +{ + return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) + != (I(0x7) | R(-1,9,1))); +} + +int +arc_operand_type(int opertype) +{ + switch (opertype) + { + case 0: + return(COND); + break; + case 1: + return(REG); + break; + case 2: + return(AUXREG); + break; + } + return -1; +} + +struct arc_operand_value * +get_ext_suffix(s) + char *s; +{ + struct arc_ext_operand_value *suffix = arc_ext_operands; + + while (suffix) + { + if ((COND == suffix->operand.type) + && !strcmp(s,suffix->operand.name)) + return(&suffix->operand); + suffix = suffix->next; + } + return NULL; +} + +int +arc_get_noshortcut_flag() +{ + return ARC_REGISTER_NOSHORT_CUT; +} diff --git a/gnu/usr.bin/binutils/opcodes/avr-dis.c b/gnu/usr.bin/binutils/opcodes/avr-dis.c index a2d0c29c31a..4598cab4145 100644 --- a/gnu/usr.bin/binutils/opcodes/avr-dis.c +++ b/gnu/usr.bin/binutils/opcodes/avr-dis.c @@ -1,5 +1,5 @@ /* Disassemble AVR instructions. - Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> @@ -17,157 +17,224 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - +#include <assert.h> #include "sysdep.h" #include "dis-asm.h" #include "opintl.h" -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; - -#define IFMASK(a,b) ((opcode & (a)) == (b)) - -static char* SREG_flags = "CZNVSHTI"; -static char* sect94[] = {"COM","NEG","SWAP","INC","NULL","ASR","LSR","ROR", - 0,0,"DEC",0,0,0,0,0}; -static char* sect98[] = {"CBI","SBIC","SBI","SBIS"}; -static char* branchs[] = { - "BRCS","BREQ","BRMI","BRVS", - "BRLT","BRHS","BRTS","BRIE", - "BRCC","BRNE","BRPL","BRVC", - "BRGE","BRHC","BRTC","BRID" -}; - -static char* last4[] = {"BLD","BST","SBRC","SBRS"}; - - -static void dispLDD PARAMS ((u16, char *)); - -static void -dispLDD (opcode, dest) - u16 opcode; - char *dest; -{ - opcode = (((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) - | (opcode & 7)); - sprintf(dest, "%d", opcode); -} - - -static void regPP PARAMS ((u16, char *)); - -static void -regPP (opcode, dest) - u16 opcode; - char *dest; -{ - opcode = ((opcode & 0x0600) >> 5) | (opcode & 0xf); - sprintf(dest, "0x%02X", opcode); -} - - -static void reg50 PARAMS ((u16, char *)); - -static void -reg50 (opcode, dest) - u16 opcode; - char *dest; -{ - opcode = (opcode & 0x01f0) >> 4; - sprintf(dest, "R%d", opcode); -} - - -static void reg104 PARAMS ((u16, char *)); - -static void -reg104 (opcode, dest) - u16 opcode; - char *dest; -{ - opcode = (opcode & 0xf) | ((opcode & 0x0200) >> 5); - sprintf(dest, "R%d", opcode); -} - - -static void reg40 PARAMS ((u16, char *)); -static void -reg40 (opcode, dest) - u16 opcode; - char *dest; +struct avr_opcodes_s { - opcode = (opcode & 0xf0) >> 4; - sprintf(dest, "R%d", opcode + 16); -} - - -static void reg20w PARAMS ((u16, char *)); - -static void -reg20w (opcode, dest) - u16 opcode; - char *dest; -{ - opcode = (opcode & 0x30) >> 4; - sprintf(dest, "R%d", 24 + opcode * 2); -} - + char *name; + char *constraints; + char *opcode; + int insn_size; /* in words */ + int isa; + unsigned int bin_opcode; + unsigned int bin_mask; +}; -static void lit404 PARAMS ((u16, char *)); +#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ +{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0}, -static void -lit404 (opcode, dest) - u16 opcode; - char *dest; +struct avr_opcodes_s avr_opcodes[] = { - opcode = ((opcode & 0xf00) >> 4) | (opcode & 0xf); - sprintf(dest, "0x%02X", opcode); -} - - -static void lit204 PARAMS ((u16, char *)); + #include "opcode/avr.h" + {NULL, NULL, NULL, 0, 0, 0, 0} +}; -static void -lit204 (opcode, dest) - u16 opcode; - char *dest; +static int avr_operand PARAMS ((unsigned int, unsigned int, + unsigned int, int, char *, char *, int)); + +static int +avr_operand (insn, insn2, pc, constraint, buf, comment, regs) + unsigned int insn; + unsigned int insn2; + unsigned int pc; + int constraint; + char *buf; + char *comment; + int regs; { - opcode = ((opcode & 0xc0) >> 2) | (opcode & 0xf); - sprintf(dest, "0x%02X", opcode); -} + int ok = 1; + switch (constraint) + { + /* Any register operand. */ + case 'r': + if (regs) + insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */ + else + insn = (insn & 0x01f0) >> 4; /* destination register */ + + sprintf (buf, "r%d", insn); + break; + + case 'd': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 0xf)); + else + sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); + break; + + case 'w': + sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3)); + break; + + case 'a': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 7)); + else + sprintf (buf, "r%d", 16 + ((insn >> 4) & 7)); + break; -static void add0fff PARAMS ((u16, char *, int)); - -static void -add0fff (op, dest, pc) - u16 op; - char *dest; - int pc; -{ - int rel_addr = (((op & 0xfff) ^ 0x800) - 0x800) * 2; - sprintf(dest, ".%+-8d ; 0x%06X", rel_addr, pc + 2 + rel_addr); -} + case 'v': + if (regs) + sprintf (buf, "r%d", (insn & 0xf) * 2); + else + sprintf (buf, "r%d", ((insn & 0xf0) >> 3)); + break; + case 'e': + { + char *xyz; -static void add03f8 PARAMS ((u16, char *, int)); + switch (insn & 0x100f) + { + case 0x0000: xyz = "Z"; break; + case 0x1001: xyz = "Z+"; break; + case 0x1002: xyz = "-Z"; break; + case 0x0008: xyz = "Y"; break; + case 0x1009: xyz = "Y+"; break; + case 0x100a: xyz = "-Y"; break; + case 0x100c: xyz = "X"; break; + case 0x100d: xyz = "X+"; break; + case 0x100e: xyz = "-X"; break; + default: xyz = "??"; ok = 0; + } + sprintf (buf, xyz); + + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + } + break; + + case 'z': + *buf++ = 'Z'; + if (insn & 0x1) + *buf++ = '+'; + *buf = '\0'; + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + break; + + case 'b': + { + unsigned int x; + + x = (insn & 7); + x |= (insn >> 7) & (3 << 3); + x |= (insn >> 8) & (1 << 5); + + if (insn & 0x8) + *buf++ = 'Y'; + else + *buf++ = 'Z'; + sprintf (buf, "+%d", x); + sprintf (comment, "0x%02x", x); + } + break; + + case 'h': + sprintf (buf, "0x%x", + ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2); + break; + + case 'L': + { + int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2; + sprintf (buf, ".%+-8d", rel_addr); + sprintf (comment, "0x%x", pc + 2 + rel_addr); + } + break; + + case 'l': + { + int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2; + sprintf (buf, ".%+-8d", rel_addr); + sprintf (comment, "0x%x", pc + 2 + rel_addr); + } + break; + + case 'i': + sprintf (buf, "0x%04X", insn2); + break; + + case 'M': + sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf)); + sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf)); + break; + + case 'n': + sprintf (buf, "??"); + fprintf (stderr, _("Internal disassembler error")); + ok = 0; + break; + + case 'K': + { + unsigned int x; + + x = (insn & 0xf) | ((insn >> 2) & 0x30); + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 's': + sprintf (buf, "%d", insn & 7); + break; + + case 'S': + sprintf (buf, "%d", (insn >> 4) & 7); + break; + + case 'P': + { + unsigned int x; + x = (insn & 0xf); + x |= (insn >> 5) & 0x30; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 'p': + { + unsigned int x; + + x = (insn >> 3) & 0x1f; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case '?': + *buf = '\0'; + break; + + default: + sprintf (buf, "??"); + fprintf (stderr, _("unknown constraint `%c'"), constraint); + ok = 0; + } -static void -add03f8 (op, dest, pc) - u16 op; - char *dest; - int pc; -{ - int rel_addr = ((((op >> 3) & 0x7f) ^ 0x40) - 0x40) * 2; - sprintf(dest, ".%+-8d ; 0x%06X", rel_addr, pc + 2 + rel_addr); + return ok; } +static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *)); -static u16 avrdis_opcode PARAMS ((bfd_vma, disassemble_info *)); - -static u16 +static unsigned short avrdis_opcode (addr, info) bfd_vma addr; disassemble_info *info; @@ -189,353 +256,104 @@ print_insn_avr(addr, info) bfd_vma addr; disassemble_info *info; { - char rr[200]; - char rd[200]; - u16 opcode; + unsigned int insn, insn2; + struct avr_opcodes_s *opcode; void *stream = info->stream; fprintf_ftype prin = info->fprintf_func; + static int initialized; int cmd_len = 2; + int ok = 0; + char op1[20], op2[20], comment1[40], comment2[40]; - opcode = avrdis_opcode (addr, info); + if (!initialized) + { + initialized = 1; + + for (opcode = avr_opcodes; opcode->name; opcode++) + { + char * s; + unsigned int bin = 0; + unsigned int mask = 0; + + for (s = opcode->opcode; *s; ++s) + { + bin <<= 1; + mask <<= 1; + bin |= (*s == '1'); + mask |= (*s == '1' || *s == '0'); + } + assert (s - opcode->opcode == 16); + assert (opcode->bin_opcode == bin); + opcode->bin_mask = mask; + } + } - if (IFMASK(0xd000, 0x8000)) + insn = avrdis_opcode (addr, info); + + for (opcode = avr_opcodes; opcode->name; opcode++) { - char letter; - reg50(opcode, rd); - dispLDD(opcode, rr); - if (opcode & 8) - letter = 'Y'; - else - letter = 'Z'; - if (opcode & 0x0200) - (*prin) (stream, " STD %c+%s,%s", letter, rr, rd); - else - (*prin) (stream, " LDD %s,%c+%s", rd, letter, rr); + if ((insn & opcode->bin_mask) == opcode->bin_opcode) + break; } - else + + /* Special case: disassemble `ldd r,b+0' as `ld r,b', and + `std b+0,r' as `st b,r' (next entry in the table). */ + + if (AVR_DISP0_P (insn)) + opcode++; + + op1[0] = 0; + op2[0] = 0; + comment1[0] = 0; + comment2[0] = 0; + + if (opcode->name) { - switch (opcode & 0xf000) - { - case 0x0000: - { - reg50(opcode, rd); - reg104(opcode, rr); - switch (opcode & 0x0c00) - { - case 0x0000: - (*prin) (stream, " NOP"); - break; - case 0x0400: - (*prin) (stream, " CPC %s,%s", rd, rr); - break; - case 0x0800: - (*prin) (stream, " SBC %s,%s", rd, rr); - break; - case 0x0c00: - (*prin) (stream, " ADD %s,%s", rd, rr); - break; - } - } - break; - case 0x1000: - { - reg50(opcode, rd); - reg104(opcode, rr); - switch (opcode & 0x0c00) - { - case 0x0000: - (*prin) (stream, " CPSE %s,%s", rd, rr); - break; - case 0x0400: - (*prin) (stream, " CP %s,%s", rd, rr); - break; - case 0x0800: - (*prin) (stream, " SUB %s,%s", rd, rr); - break; - case 0x0c00: - (*prin) (stream, " ADC %s,%s", rd, rr); - break; - } - } - break; - case 0x2000: - { - reg50(opcode, rd); - reg104(opcode, rr); - switch (opcode & 0x0c00) - { - case 0x0000: - (*prin) (stream, " AND %s,%s", rd, rr); - break; - case 0x0400: - (*prin) (stream, " EOR %s,%s", rd, rr); - break; - case 0x0800: - (*prin) (stream, " OR %s,%s", rd, rr); - break; - case 0x0c00: - (*prin) (stream, " MOV %s,%s", rd, rr); - break; - } - } - break; - case 0x3000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " CPI %s,%s", rd, rr); - } - break; - case 0x4000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " SBCI %s,%s", rd, rr); - } - break; - case 0x5000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " SUBI %s,%s", rd, rr); - } - break; - case 0x6000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " ORI %s,%s", rd, rr); - } - break; - case 0x7000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " ANDI %s,%s", rd, rr); - } - break; - case 0x9000: - { - switch (opcode & 0x0e00) - { - case 0x0000: - { - reg50(opcode, rd); - switch (opcode & 0xf) - { - case 0x0: - { - (*prin) (stream, " LDS %s,0x%04X", rd, - avrdis_opcode(addr + 2, info)); - cmd_len = 4; - } - break; - case 0x1: - (*prin) (stream, " LD %s,Z+", rd); - break; - case 0x2: - (*prin) (stream, " LD %s,-Z", rd); - break; - case 0x9: - (*prin) (stream, " LD %s,Y+", rd); - break; - case 0xa: - (*prin) (stream, " LD %s,-Y", rd); - break; - case 0xc: - (*prin) (stream, " LD %s,X", rd); - break; - case 0xd: - (*prin) (stream, " LD %s,X+", rd); - break; - case 0xe: - (*prin) (stream, " LD %s,-X", rd); - break; - case 0xf: - (*prin) (stream, " POP %s", rd); - break; - default: - (*prin) (stream, " ????"); - break; - } - } - break; - case 0x0200: - { - reg50(opcode, rd); - switch (opcode & 0xf) - { - case 0x0: - { - (*prin) (stream, " STS 0x%04X,%s", - avrdis_opcode(addr + 2, info), rd); - cmd_len = 4; - } - break; - case 0x1: - (*prin) (stream, " ST Z+,%s", rd); - break; - case 0x2: - (*prin) (stream, " ST -Z,%s", rd); - break; - case 0x9: - (*prin) (stream, " ST Y+,%s", rd); - break; - case 0xa: - (*prin) (stream, " ST -Y,%s", rd); - break; - case 0xc: - (*prin) (stream, " ST X,%s", rd); - break; - case 0xd: - (*prin) (stream, " ST X+,%s", rd); - break; - case 0xe: - (*prin) (stream, " ST -X,%s", rd); - break; - case 0xf: - (*prin) (stream, " PUSH %s", rd); - break; - default: - (*prin) (stream, " ????"); - break; - } - } - break; - case 0x0400: - { - if (IFMASK(0x020c, 0x000c)) - { - u32 k = ((opcode & 0x01f0) >> 3) | (opcode & 1); - k = (k << 16) | avrdis_opcode(addr + 2, info); - if (opcode & 0x0002) - (*prin) (stream, " CALL 0x%06X", k*2); - else - (*prin) (stream, " JMP 0x%06X", k*2); - cmd_len = 4; - } - else if (IFMASK(0x010f, 0x0008)) - { - int sf = (opcode & 0x70) >> 4; - if (opcode & 0x0080) - (*prin) (stream, " CL%c", SREG_flags[sf]); - else - (*prin) (stream, " SE%c", SREG_flags[sf]); - } - else if (IFMASK(0x000f, 0x0009)) - { - if (opcode & 0x0100) - (*prin) (stream, " ICALL"); - else - (*prin) (stream, " IJMP"); - } - else if (IFMASK(0x010f, 0x0108)) - { - if (IFMASK(0x0090, 0x0000)) - (*prin) (stream, " RET"); - else if (IFMASK(0x0090, 0x0010)) - (*prin) (stream, " RETI"); - else if (IFMASK(0x00e0, 0x0080)) - (*prin) (stream, " SLEEP"); - else if (IFMASK(0x00e0, 0x00a0)) - (*prin) (stream, " WDR"); - else if (IFMASK(0x00f0, 0x00c0)) - (*prin) (stream, " LPM"); - else if (IFMASK(0x00f0, 0x00d0)) - (*prin) (stream, " ELPM"); - else - (*prin) (stream, " ????"); - } - else - { - const char* p; - reg50(opcode, rd); - p = sect94[opcode & 0xf]; - if (!p) - p = "????"; - (*prin) (stream, " %-8s%s", p, rd); - } - } - break; - case 0x0600: - { - if (opcode & 0x0200) - { - lit204(opcode, rd); - reg20w(opcode, rr); - if (opcode & 0x0100) - (*prin) (stream, " SBIW %s,%s", rr, rd); - else - (*prin) (stream, " ADIW %s,%s", rr, rd); - } - } - break; - case 0x0800: - case 0x0a00: - { - (*prin) (stream, " %-8s0x%02X,%d", - sect98[(opcode & 0x0300) >> 8], - (opcode & 0xf8) >> 3, - opcode & 7); - } - break; - default: - { - reg50(opcode, rd); - reg104(opcode, rr); - (*prin) (stream, " MUL %s,%s", rd, rr); - } - } - } - break; - case 0xb000: - { - reg50(opcode, rd); - regPP(opcode, rr); - if (opcode & 0x0800) - (*prin) (stream, " OUT %s,%s", rr, rd); - else - (*prin) (stream, " IN %s,%s", rd, rr); - } - break; - case 0xc000: - { - add0fff(opcode, rd, addr); - (*prin) (stream, " RJMP %s", rd); - } - break; - case 0xd000: - { - add0fff(opcode, rd, addr); - (*prin) (stream, " RCALL %s", rd); - } - break; - case 0xe000: - { - reg40(opcode, rd); - lit404(opcode, rr); - (*prin) (stream, " LDI %s,%s", rd, rr); - } - break; - case 0xf000: - { - if (opcode & 0x0800) - { - reg50(opcode, rd); - (*prin) (stream, " %-8s%s,%d", - last4[(opcode & 0x0600) >> 9], - rd, opcode & 7); - } - else - { - char* p; - add03f8(opcode, rd, addr); - p = branchs[((opcode & 0x0400) >> 7) | (opcode & 7)]; - (*prin) (stream, " %-8s%s", p, rd); - } - } - break; - } + char *op = opcode->constraints; + + insn2 = 0; + ok = 1; + + if (opcode->insn_size > 1) + { + insn2 = avrdis_opcode (addr + 2, info); + cmd_len = 4; + } + + if (*op && *op != '?') + { + int regs = REGISTER_P (*op); + + ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0); + + if (ok && *(++op) == ',') + ok = avr_operand (insn, insn2, addr, *(++op), op2, + *comment1 ? comment2 : comment1, regs); + } + } + + if (!ok) + { + /* Unknown opcode, or invalid combination of operands. */ + sprintf (op1, "0x%04x", insn); + op2[0] = 0; + sprintf (comment1, "????"); + comment2[0] = 0; } + + (*prin) (stream, "%s", ok ? opcode->name : ".word"); + + if (*op1) + (*prin) (stream, "\t%s", op1); + + if (*op2) + (*prin) (stream, ", %s", op2); + + if (*comment1) + (*prin) (stream, "\t; %s", comment1); + + if (*comment2) + (*prin) (stream, " %s", comment2); + return cmd_len; } diff --git a/gnu/usr.bin/binutils/opcodes/cgen-asm.c b/gnu/usr.bin/binutils/opcodes/cgen-asm.c index 4ed69363a9d..a8d6ff8471b 100644 --- a/gnu/usr.bin/binutils/opcodes/cgen-asm.c +++ b/gnu/usr.bin/binutils/opcodes/cgen-asm.c @@ -1,6 +1,6 @@ /* CGEN generic assembler support code. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -66,7 +66,7 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) CGEN_CPU_DESC cd; const CGEN_INSN *insns; int count; - int entsize; + int entsize ATTRIBUTE_UNUSED; CGEN_INSN_LIST **htable; CGEN_INSN_LIST *hentbuf; { @@ -198,7 +198,7 @@ cgen_asm_lookup_insn (cd, insn) const char * cgen_parse_keyword (cd, strp, keyword_table, valuep) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; const char **strp; CGEN_KEYWORD *keyword_table; long *valuep; diff --git a/gnu/usr.bin/binutils/opcodes/cgen-asm.in b/gnu/usr.bin/binutils/opcodes/cgen-asm.in new file mode 100644 index 00000000000..7249708ebb0 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cgen-asm.in @@ -0,0 +1,321 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <ctype.h> +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here */ + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. +*/ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && tolower (*p) == tolower (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && !isspace (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = @arch@_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (isspace (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + + /* Skip leading white space. */ + while (isspace (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* not usually needed as unsupported opcodes shouldn't be in the hash lists */ + /* Is this insn supported by the selected cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + continue; +#endif + + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc' */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; + +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +@arch@_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! @arch@_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/gnu/usr.bin/binutils/opcodes/cgen-dis.c b/gnu/usr.bin/binutils/opcodes/cgen-dis.c index 78b1cd90ed9..b4297bb44d7 100644 --- a/gnu/usr.bin/binutils/opcodes/cgen-dis.c +++ b/gnu/usr.bin/binutils/opcodes/cgen-dis.c @@ -1,6 +1,7 @@ /* CGEN generic disassembler support code. - Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -43,7 +44,7 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) CGEN_CPU_DESC cd; const CGEN_INSN * insns; int count; - int entsize; + int entsize ATTRIBUTE_UNUSED; CGEN_INSN_LIST ** htable; CGEN_INSN_LIST * hentbuf; { @@ -64,27 +65,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) to hash on, so set both up. */ value = CGEN_INSN_BASE_VALUE (insn); - switch (CGEN_INSN_MASK_BITSIZE (insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - + bfd_put_bits ((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (insn), + big_p); hash = (* cd->dis_hash) (buf, value); hentbuf->next = htable[hash]; hentbuf->insn = insn; @@ -121,27 +105,10 @@ hash_insn_list (cd, insns, htable, hentbuf) to hash on, so set both up. */ value = CGEN_INSN_BASE_VALUE (ilist->insn); - switch (CGEN_INSN_MASK_BITSIZE (ilist->insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - + bfd_put_bits((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (ilist->insn), + big_p); hash = (* cd->dis_hash) (buf, value); hentbuf->next = htable [hash]; hentbuf->insn = ilist->insn; diff --git a/gnu/usr.bin/binutils/opcodes/cgen-dis.in b/gnu/usr.bin/binutils/opcodes/cgen-dis.in new file mode 100644 index 00000000000..0e7c35a5675 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cgen-dis.in @@ -0,0 +1,417 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, + disassemble_info *, char *, int)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + +/* -- disassembler routines inserted here */ + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) +#ifdef CGEN_PRINT_NORMAL + CGEN_CPU_DESC cd; +#else + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; +#endif + PTR dis_info; + long value; + unsigned int attrs; +#ifdef CGEN_PRINT_NORMAL + bfd_vma pc; + int length; +#else + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +#endif +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) +#ifdef CGEN_PRINT_NORMAL + CGEN_CPU_DESC cd; +#else + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; +#endif + PTR dis_info; + bfd_vma value; + unsigned int attrs; +#ifdef CGEN_PRINT_NORMAL + bfd_vma pc; + int length; +#else + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +#endif +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + unsigned long insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + + int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value); + if (rc != 0) + return rc; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* not needed as insn shouldn't be in hash lists if not supported */ + /* Supported by this cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + if ((insn_value & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && + (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int status; + + /* Read the base part of the insn. */ + + status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +int +print_insn_@arch@ (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_@arch@ +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the isa number (e.g. for arm thumb) + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = 0; +#endif + + mach = info->mach; + + /* If we've switched cpu's, close the current table and open a new one. */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + @arch@_cgen_cpu_close (cd); + cd = 0; + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + @arch@_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/gnu/usr.bin/binutils/opcodes/cgen-ibld.in b/gnu/usr.bin/binutils/opcodes/cgen-ibld.in new file mode 100644 index 00000000000..6921a53dac9 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cgen-ibld.in @@ -0,0 +1,514 @@ +/* Instruction building/extraction support for @arch@. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <ctype.h> +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; + + x = bfd_get_bits (bufp, word_length, big_p); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order + (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is + recorded in host byte order, otherwise BUFFER is an array of bytes and the + value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc; +{ + unsigned long x; + int shift; + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; + + x = bfd_get_bits (bufp, word_length, big_p); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + CGEN_INSN_INT value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE? */ + + if (CGEN_INT_INSN_P || word_offset == 0) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ diff --git a/gnu/usr.bin/binutils/opcodes/cgen-opc.c b/gnu/usr.bin/binutils/opcodes/cgen-opc.c index ede3adde115..e55482cfa04 100644 --- a/gnu/usr.bin/binutils/opcodes/cgen-opc.c +++ b/gnu/usr.bin/binutils/opcodes/cgen-opc.c @@ -1,6 +1,7 @@ /* CGEN generic opcode support. - Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -27,6 +28,10 @@ #include "symcat.h" #include "opcode/cgen.h" +#ifdef HAVE_ALLOCA_H +#include <alloca.h> +#endif + static unsigned int hash_keyword_name PARAMS ((const CGEN_KEYWORD *, const char *, int)); static unsigned int hash_keyword_value @@ -263,7 +268,7 @@ cgen_hw_lookup_by_name (cd, name) CGEN_CPU_DESC cd; const char *name; { - int i; + unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; for (i = 0; i < cd->hw_table.num_entries; ++i) @@ -281,9 +286,9 @@ cgen_hw_lookup_by_name (cd, name) const CGEN_HW_ENTRY * cgen_hw_lookup_by_num (cd, hwnum) CGEN_CPU_DESC cd; - int hwnum; + unsigned int hwnum; { - int i; + unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; /* ??? This can be speeded up. */ @@ -305,7 +310,7 @@ cgen_operand_lookup_by_name (cd, name) CGEN_CPU_DESC cd; const char *name; { - int i; + unsigned int i; const CGEN_OPERAND **op = cd->operand_table.entries; for (i = 0; i < cd->operand_table.num_entries; ++i) @@ -370,30 +375,7 @@ cgen_get_insn_value (cd, buf, length) unsigned char *buf; int length; { - CGEN_INSN_INT value; - - switch (length) - { - case 8: - value = *buf; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb16 (buf); - else - value = bfd_getl16 (buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb32 (buf); - else - value = bfd_getl32 (buf); - break; - default: - abort (); - } - - return value; + bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); } /* Cover function to store an insn value properly byteswapped. */ @@ -405,26 +387,8 @@ cgen_put_insn_value (cd, buf, length, value) int length; CGEN_INSN_INT value; { - switch (length) - { - case 8: - buf[0] = value; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb16 (value, buf); - else - bfd_putl16 (value, buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb32 (value, buf); - else - bfd_putl32 (value, buf); - break; - default: - abort (); - } + bfd_put_bits ((bfd_vma) value, buf, length, + cd->insn_endian == CGEN_ENDIAN_BIG); } /* Look up instruction INSN_*_VALUE and extract its fields. diff --git a/gnu/usr.bin/binutils/opcodes/cgen.sh b/gnu/usr.bin/binutils/opcodes/cgen.sh new file mode 100644 index 00000000000..a9483bdb972 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cgen.sh @@ -0,0 +1,154 @@ +#! /bin/sh +# CGEN generic assembler support code. +# +# Copyright 2001 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils and GDB, the GNU debugger. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +# +# Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch], +# arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. +# +# Usage: +# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options +# +# ACTION is currently always "opcodes". It exists to be consistent with the +# simulator. +# OPTIONS is comma separated list of options: +# - opinst - arch-opinst.c is being made, causes semantic analysis +# +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter (or other implementation) with gdb/binutils. +# Maybe we never will. + +# We want to behave like make, any error forces us to stop. +set -e + +action=$1 +srcdir=$2 +cgen=$3 +cgendir=$4 +cgenflags=$5 +arch=$6 +prefix=$7 +options=$8 + +# List of extra files to build. +# Values: opinst (only 1 extra file at present) +extrafiles=$9 + +rootdir=${srcdir}/.. + +# $arch is $6, as passed on the command line. +# $ARCH is the same argument but in all uppercase. +# Both forms are used in this script. + +lowercase='abcdefghijklmnopqrstuvwxyz' +uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` + +extrafile_args="" +for ef in .. $extrafiles +do + case $ef in + ..) ;; + opinst) extrafile_args="-Q tmp-opinst.c1 $extrafile_args" ;; + esac +done + +case $action in +opcodes) + # Remove residual working files. + rm -f tmp-desc.h tmp-desc.h1 + rm -f tmp-desc.c tmp-desc.c1 + rm -f tmp-opc.h tmp-opc.h1 + rm -f tmp-opc.c tmp-opc.c1 + rm -f tmp-opinst.c tmp-opinst.c1 + rm -f tmp-ibld.h tmp-ibld.h1 + rm -f tmp-ibld.c tmp-ibld.in1 + rm -f tmp-asm.c tmp-asm.in1 + rm -f tmp-dis.c tmp-dis.in1 + + # Run CGEN. + ${cgen} -s ${cgendir}/cgen-opc.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${options}" \ + -m all \ + -a ${arch} \ + -H tmp-desc.h1 \ + -C tmp-desc.c1 \ + -O tmp-opc.h1 \ + -P tmp-opc.c1 \ + -L tmp-ibld.in1 \ + -A tmp-asm.in1 \ + -D tmp-dis.in1 \ + ${extrafile_args} + + # Customise generated files for the particular architecture. + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-desc.h1 > tmp-desc.h + ${rootdir}/move-if-change tmp-desc.h ${srcdir}/${prefix}-desc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-desc.c1 > tmp-desc.c + ${rootdir}/move-if-change tmp-desc.c ${srcdir}/${prefix}-desc.c + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-opc.h1 > tmp-opc.h + ${rootdir}/move-if-change tmp-opc.h ${srcdir}/${prefix}-opc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-opc.c1 > tmp-opc.c + ${rootdir}/move-if-change tmp-opc.c ${srcdir}/${prefix}-opc.c + + case $extrafiles in + *opinst*) + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-opinst.c1 >tmp-opinst.c + ${rootdir}/move-if-change tmp-opinst.c ${srcdir}/${prefix}-opinst.c + ;; + esac + + cat ${srcdir}/cgen-ibld.in tmp-ibld.in1 | \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-ibld.c + ${rootdir}/move-if-change tmp-ibld.c ${srcdir}/${prefix}-ibld.c + + sed -e "/ -- assembler routines/ r tmp-asm.in1" ${srcdir}/cgen-asm.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-asm.c + ${rootdir}/move-if-change tmp-asm.c ${srcdir}/${prefix}-asm.c + + sed -e "/ -- disassembler routines/ r tmp-dis.in1" ${srcdir}/cgen-dis.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-dis.c + ${rootdir}/move-if-change tmp-dis.c ${srcdir}/${prefix}-dis.c + + # Remove temporary files. + rm -f tmp-desc.h1 tmp-desc.c1 + rm -f tmp-opc.h1 tmp-opc.c1 + rm -f tmp-opinst.c1 + rm -f tmp-ibld.h1 tmp-ibld.in1 + rm -f tmp-asm.in1 tmp-dis.in1 + ;; + +*) + echo "$0: bad action: ${action}" >&2 + exit 1 + ;; + +esac + +exit 0 diff --git a/gnu/usr.bin/binutils/opcodes/cris-dis.c b/gnu/usr.bin/binutils/opcodes/cris-dis.c new file mode 100644 index 00000000000..3c8db2a1225 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cris-dis.c @@ -0,0 +1,1404 @@ +/* Disassembler code for CRIS. + Copyright 2000 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + +This file is part of the GNU binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 of the License, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/cris.h" +#include "libiberty.h" + +/* No instruction will be disassembled longer than this. In theory, and + in silicon, address prefixes can be cascaded. In practice, cascading + is not used by GCC, and not supported by the assembler. */ +#ifndef MAX_BYTES_PER_CRIS_INSN +#define MAX_BYTES_PER_CRIS_INSN 8 +#endif + +/* Whether or not to decode prefixes, folding it into the following + instruction. FIXME: Make this optional later. */ +#ifndef PARSE_PREFIX +#define PARSE_PREFIX 1 +#endif + +/* Sometimes we prefix all registers with this character. */ +#define REGISTER_PREFIX_CHAR '$' + +/* Whether or not to trace the following sequence: + sub* X,r%d + bound* Y,r%d + adds.w [pc+r%d.w],pc + + This is the assembly form of a switch-statement in C. + The "sub is optional. If there is none, then X will be zero. + X is the value of the first case, + Y is the number of cases (including default). + + This results in case offsets printed on the form: + case N: -> case_address + where N is an estimation on the corresponding 'case' operand in C, + and case_address is where execution of that case continues after the + sequence presented above. + + The old style of output was to print the offsets as instructions, + which made it hard to follow "case"-constructs in the disassembly, + and caused a lot of annoying warnings about undefined instructions. + + FIXME: Make this optional later. */ +#ifndef TRACE_CASE +#define TRACE_CASE 1 +#endif + +/* Value of first element in switch. */ +static long case_offset = 0; + +/* How many more case-offsets to print. */ +static long case_offset_counter = 0; + +/* Number of case offsets. */ +static long no_of_case_offsets = 0; + +/* Candidate for next case_offset. */ +static long last_immediate = 0; + +static int number_of_bits PARAMS ((unsigned int)); +static char *format_hex PARAMS ((unsigned long, char *)); +static char *format_dec PARAMS ((long, char *, int)); +static char *format_reg PARAMS ((int, char *, boolean)); +static int cris_constraint PARAMS ((const char *, unsigned int, + unsigned int)); +static unsigned bytes_to_skip PARAMS ((unsigned int, + const struct cris_opcode *)); +static char *print_flags PARAMS ((unsigned int, char *)); +static void print_with_operands + PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *, + bfd_vma, disassemble_info *, const struct cris_opcode *, + unsigned int, unsigned char *, boolean)); +static const struct cris_spec_reg *spec_reg_info PARAMS ((unsigned int)); +static int print_insn_cris_generic + PARAMS ((bfd_vma, disassemble_info *, boolean)); +static int print_insn_cris_with_register_prefix + PARAMS ((bfd_vma, disassemble_info *)); +static int print_insn_cris_without_register_prefix + PARAMS ((bfd_vma, disassemble_info *)); + +/* Return the descriptor of a special register. + FIXME: Depend on a CPU-version specific argument when all machinery + is in place. */ + +static const struct cris_spec_reg * +spec_reg_info (sreg) + unsigned int sreg; +{ + int i; + for (i = 0; cris_spec_regs[i].name != NULL; i++) + { + if (cris_spec_regs[i].number == sreg) + return &cris_spec_regs[i]; + } + + return NULL; +} + +/* Return the number of bits in the argument. */ + +static int +number_of_bits (val) + unsigned int val; +{ + int bits; + + for (bits = 0; val != 0; val &= val-1) + bits++; + + return bits; +} + +/* Get an entry in the opcode-table. */ + +static const struct cris_opcode * +get_opcode_entry (insn, prefix_insn) + unsigned int insn; + unsigned int prefix_insn; +{ + /* For non-prefixed insns, we keep a table of pointers, indexed by the + insn code. Each entry is initialized when found to be NULL. */ + static const struct cris_opcode **opc_table = NULL; + + const struct cris_opcode *max_matchedp = NULL; + const struct cris_opcode **prefix_opc_table = NULL; + + /* We hold a table for each prefix that need to be handled differently. */ + static const struct cris_opcode **dip_prefixes = NULL; + static const struct cris_opcode **bdapq_m1_prefixes = NULL; + static const struct cris_opcode **bdapq_m2_prefixes = NULL; + static const struct cris_opcode **bdapq_m4_prefixes = NULL; + static const struct cris_opcode **rest_prefixes = NULL; + + /* Allocate and clear the opcode-table. */ + if (opc_table == NULL) + { + opc_table = xmalloc (65536 * sizeof (opc_table[0])); + memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *)); + + dip_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0])); + + bdapq_m1_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0])); + + bdapq_m2_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0])); + + bdapq_m4_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0])); + + rest_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0])); + } + + /* Get the right table if this is a prefix. + This code is connected to cris_constraints in that it knows what + prefixes play a role in recognition of patterns; the necessary + state is reflected by which table is used. If constraints + involving match or non-match of prefix insns are changed, then this + probably needs changing too. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + const struct cris_opcode *popcodep + = (opc_table[prefix_insn] != NULL + ? opc_table[prefix_insn] + : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX)); + + if (popcodep == NULL) + return NULL; + + if (popcodep->match == BDAP_QUICK_OPCODE) + { + /* Since some offsets are recognized with "push" macros, we + have to have different tables for them. */ + int offset = (prefix_insn & 255); + + if (offset > 127) + offset -= 256; + + switch (offset) + { + case -4: + prefix_opc_table = bdapq_m4_prefixes; + break; + + case -2: + prefix_opc_table = bdapq_m2_prefixes; + break; + + case -1: + prefix_opc_table = bdapq_m1_prefixes; + break; + + default: + prefix_opc_table = rest_prefixes; + break; + } + } + else if (popcodep->match == DIP_OPCODE) + /* We don't allow postincrement when the prefix is DIP, so use a + different table for DIP. */ + prefix_opc_table = dip_prefixes; + else + prefix_opc_table = rest_prefixes; + } + + if (prefix_insn != NO_CRIS_PREFIX + && prefix_opc_table[insn] != NULL) + max_matchedp = prefix_opc_table[insn]; + else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) + max_matchedp = opc_table[insn]; + else + { + const struct cris_opcode *opcodep; + int max_level_of_match = -1; + + for (opcodep = cris_opcodes; + opcodep->name != NULL; + opcodep++) + { + int level_of_match; + + /* We give a double lead for bits matching the template in + cris_opcodes. Not even, because then "move p8,r10" would + be given 2 bits lead over "clear.d r10". When there's a + tie, the first entry in the table wins. This is + deliberate, to avoid a more complicated recognition + formula. */ + if ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0 + && ((level_of_match + = cris_constraint (opcodep->args, + insn, + prefix_insn)) + >= 0) + && ((level_of_match + += 2 * number_of_bits (opcodep->match + | opcodep->lose)) + > max_level_of_match)) + { + max_matchedp = opcodep; + max_level_of_match = level_of_match; + + /* If there was a full match, never mind looking + further. */ + if (level_of_match >= 2 * 16) + break; + } + } + /* Fill in the new entry. + + If there are changes to the opcode-table involving prefixes, and + disassembly then does not work correctly, try removing the + else-clause below that fills in the prefix-table. If that + helps, you need to change the prefix_opc_table setting above, or + something related. */ + if (prefix_insn == NO_CRIS_PREFIX) + opc_table[insn] = max_matchedp; + else + prefix_opc_table[insn] = max_matchedp; + } + + return max_matchedp; +} + +/* Format number as hex with a leading "0x" into outbuffer. */ + +static char * +format_hex (number, outbuffer) + unsigned long number; + char *outbuffer; +{ + /* Obfuscate to avoid warning on 32-bit host, but properly truncate + negative numbers on >32-bit hosts. */ + if (sizeof (number) > 4) + number &= (1 << (sizeof (number) > 4 ? 32 : 1)) - 1; + + sprintf (outbuffer, "0x%lx", number); + + /* Save this value for the "case" support. */ + if (TRACE_CASE) + last_immediate = number; + + return outbuffer + strlen (outbuffer); +} + +/* Format number as decimal into outbuffer. Parameter signedp says + whether the number should be formatted as signed (!= 0) or + unsigned (== 0). */ + +static char * +format_dec (number, outbuffer, signedp) + long number; + char *outbuffer; + int signedp; +{ + last_immediate = number; + sprintf (outbuffer, signedp ? "%ld" : "%lu", number); + + return outbuffer + strlen (outbuffer); +} + +/* Format the name of the general register regno into outbuffer. */ + +static char * +format_reg (regno, outbuffer_start, with_reg_prefix) + int regno; + char *outbuffer_start; + boolean with_reg_prefix; +{ + char *outbuffer = outbuffer_start; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + switch (regno) + { + case 15: + strcpy (outbuffer, "pc"); + break; + + case 14: + strcpy (outbuffer, "sp"); + break; + + default: + sprintf (outbuffer, "r%d", regno); + break; + } + + return outbuffer_start + strlen (outbuffer_start); +} + +/* Return -1 if the constraints of a bitwise-matched instruction say + that there is no match. Otherwise return a nonnegative number + indicating the confidence in the match (higher is better). */ + +static int +cris_constraint (cs, insn, prefix_insn) + const char *cs; + unsigned int insn; + unsigned int prefix_insn; +{ + int retval = 0; + int tmp; + int prefix_ok = 0; + + const char *s; + for (s = cs; *s; s++) + switch (*s) + { + case '!': + /* Do not recognize "pop" if there's a prefix. */ + if (prefix_insn != NO_CRIS_PREFIX) + return -1; + break; + + case 'M': + /* Size modifier for "clear", i.e. special register 0, 4 or 8. + Check that it is one of them. Only special register 12 could + be mismatched, but checking for matches is more logical than + checking for mismatches when there are only a few cases. */ + tmp = ((insn >> 12) & 0xf); + if (tmp != 0 && tmp != 4 && tmp != 8) + return -1; + break; + + case 'm': + if ((insn & 0x30) == 0x30) + return -1; + break; + + case 'S': + /* A prefix operand without side-effect. */ + if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) + { + prefix_ok = 1; + break; + } + else + return -1; + + case 's': + case 'y': + /* If this is a prefixed insn with postincrement (side-effect), + the prefix must not be DIP. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + if (insn & 0x400) + { + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX); + + if (prefix_opcodep->match == DIP_OPCODE) + return -1; + } + + prefix_ok = 1; + } + break; + + case 'B': + /* If we don't fall through, then the prefix is ok. */ + prefix_ok = 1; + + /* A "push" prefix. Check for valid "push" size. + In case of special register, it may be != 4. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + /* Match the prefix insn to BDAPQ. */ + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX); + + if (prefix_opcodep->match == BDAP_QUICK_OPCODE) + { + int pushsize = (prefix_insn & 255); + + if (pushsize > 127) + pushsize -= 256; + + if (s[1] == 'P') + { + unsigned int spec_reg = (insn >> 12) & 15; + const struct cris_spec_reg *sregp + = spec_reg_info (spec_reg); + + /* For a special-register, the "prefix size" must + match the size of the register. */ + if (sregp && sregp->reg_size == (unsigned int) -pushsize) + break; + } + else if (s[1] == 'R') + { + if ((insn & 0x30) == 0x20 && pushsize == -4) + break; + } + /* FIXME: Should abort here; next constraint letter + *must* be 'P' or 'R'. */ + } + } + return -1; + + case 'D': + retval = (((insn >> 12) & 15) == (insn & 15)); + if (!retval) + return -1; + else + retval += 4; + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* Since we match four bits, we will give a value of 4-1 = 3 + in a match. If there is a corresponding exact match of a + special register in another pattern, it will get a value of + 4, which will be higher. This should be correct in that an + exact pattern would match better than a general pattern. + + Note that there is a reason for not returning zero; the + pattern for "clear" is partly matched in the bit-pattern + (the two lower bits must be zero), while the bit-pattern + for a move from a special register is matched in the + register constraint. */ + + if (sregp != NULL) + { + retval += 3; + break; + } + else + return -1; + } + } + + if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok) + return -1; + + return retval; +} + +/* Return the length of an instruction. */ + +static unsigned +bytes_to_skip (insn, matchedp) + unsigned int insn; + const struct cris_opcode *matchedp; +{ + /* Each insn is a word plus "immediate" operands. */ + unsigned to_skip = 2; + const char *template = matchedp->args; + const char *s; + + for (s = template; *s; s++) + if (*s == 's' && (insn & 0x400) && (insn & 15) == 15) + { + /* Immediate via [pc+], so we have to check the size of the + operand. */ + int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3)); + + if (matchedp->imm_oprnd_size == SIZE_FIX_32) + to_skip += 4; + else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + return 2; + + /* PC is incremented by two, not one, for a byte. */ + to_skip += (sregp->reg_size + 1) & ~1; + } + else + to_skip += (mode_size + 1) & ~1; + } + else if (*s == 'b') + to_skip += 2; + + return to_skip; +} + +/* Print condition code flags. */ + +static char * +print_flags (insn, cp) + unsigned int insn; + char *cp; +{ + /* Use the v8 (Etrax 100) flag definitions for disassembly. + The differences with v0 (Etrax 1..4) vs. Svinto are: + v0 'd' <=> v8 'm' + v0 'e' <=> v8 'b'. */ + static const char fnames[] = "cvznxibm"; + + unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); + int i; + + for (i = 0; i < 8; i++) + if (flagbits & (1 << i)) + *cp++ = fnames[i]; + + return cp; +} + +/* Print out an insn with its operands, and update the info->insn_type + fields. The prefix_opcodep and the rest hold a prefix insn that is + supposed to be output as an address mode. */ + +static void +print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep, + prefix_insn, prefix_buffer, with_reg_prefix) + const struct cris_opcode *opcodep; + unsigned int insn; + unsigned char *buffer; + bfd_vma addr; + disassemble_info *info; + + /* If a prefix insn was before this insn (and is supposed to be + output as an address), here is a description of it. */ + const struct cris_opcode *prefix_opcodep; + unsigned int prefix_insn; + unsigned char *prefix_buffer; + boolean with_reg_prefix; +{ + /* Get a buffer of somewhat reasonable size where we store + intermediate parts of the insn. */ + char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; + char *tp = temp; + static const char mode_char[] = "bwd?"; + const char *s; + const char *cs; + + /* Print out the name first thing we do. */ + (*info->fprintf_func) (info->stream, "%s", opcodep->name); + + cs = opcodep->args; + s = cs; + + /* Ignore any prefix indicator. */ + if (*s == 'p') + s++; + + if (*s == 'm' || *s == 'M' || *s == 'z') + { + *tp++ = '.'; + + /* Get the size-letter. */ + *tp++ = *s == 'M' + ? (insn & 0x8000 ? 'd' + : insn & 0x4000 ? 'w' : 'b') + : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; + + /* Ignore the size and the space character that follows. */ + s += 2; + } + + /* Add a space if this isn't a long-branch, because for those will add + the condition part of the name later. */ + if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) + *tp++ = ' '; + + /* Fill in the insn-type if deducible from the name (and there's no + better way). */ + if (opcodep->name[0] == 'j') + { + if (strncmp (opcodep->name, "jsr", 3) == 0) + /* It's "jsr" or "jsrc". */ + info->insn_type = dis_jsr; + else + /* Any other jump-type insn is considered a branch. */ + info->insn_type = dis_branch; + } + + /* We might know some more fields right now. */ + info->branch_delay_insns = opcodep->delayed; + + /* Handle operands. */ + for (; *s; s++) + { + switch (*s) + { + case ',': + *tp++ = *s; + break; + + case '!': + /* Ignore at this point; used at earlier stages to avoid recognition + if there's a prefixes at something that in other ways looks like + a "pop". */ + break; + + case 'B': + /* This was the prefix that made this a "push". We've already + handled it by recognizing it, so signal that the prefix is + handled by setting it to NULL. */ + prefix_opcodep = NULL; + break; + + case 'D': + case 'r': + tp = format_reg (insn & 15, tp, with_reg_prefix); + break; + + case 'R': + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + break; + + case 'y': + case 'S': + case 's': + /* Any "normal" memory operand. */ + if ((insn & 0x400) && (insn & 15) == 15) + { + /* We're looking at [pc+], i.e. we need to output an immediate + number, where the size can depend on different things. */ + long number; + int signedp + = ((*cs == 'z' && (insn & 0x20)) + || opcodep->match == BDAP_QUICK_OPCODE); + int nbytes; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + nbytes = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* A NULL return should have been as a non-match earlier, + so catch it as an internal error in the error-case + below. */ + if (sregp == NULL) + /* Whatever non-valid size. */ + nbytes = 42; + else + /* PC is always incremented by a multiple of two. */ + nbytes = (sregp->reg_size + 1) & ~1; + } + else + { + int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + } + + switch (nbytes) + { + case 1: + number = buffer[2]; + if (signedp && number > 127) + number -= 256; + break; + + case 2: + number = buffer[2] + buffer[3] * 256; + if (signedp && number > 32767) + number -= 65536; + break; + + case 4: + number + = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + if ((*cs == 'z' && (insn & 0x20)) + || (opcodep->match == BDAP_QUICK_OPCODE + && (nbytes <= 2 || buffer[1 + nbytes] == 0))) + tp = format_dec (number, tp, signedp); + else + { + unsigned int highbyte = (number >> 24) & 0xff; + + /* Either output this as an address or as a number. If it's + a dword with the same high-byte as the address of the + insn, assume it's an address, and also if it's a non-zero + non-0xff high-byte. If this is a jsr or a jump, then + it's definitely an address. */ + if (nbytes == 4 + && (highbyte == ((addr >> 24) & 0xff) + || (highbyte != 0 && highbyte != 0xff) + || info->insn_type == dis_branch + || info->insn_type == dis_jsr)) + { + /* Finish off and output previous formatted bytes. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + + info->target = number; + } + else + tp = format_hex (number, tp); + } + } + else + { + /* Not an immediate number. Then this is a (possibly + prefixed) memory operand. */ + if (info->insn_type != dis_nonbranch) + { + int mode_size + = 1 << ((insn >> 4) + & (opcodep->args[0] == 'z' ? 1 : 3)); + int size; + info->insn_type = dis_dref; + info->flags |= CRIS_DIS_FLAG_MEMREF; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + size = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + size = 4; + else + size = sregp->reg_size; + } + else + size = mode_size; + + info->data_size = size; + } + + *tp++ = '['; + + if (prefix_opcodep + /* We don't match dip with a postincremented field + as a side-effect address mode. */ + && ((insn & 0x400) == 0 + || prefix_opcodep->match != DIP_OPCODE)) + { + if (insn & 0x400) + { + tp = format_reg (insn & 15, tp, with_reg_prefix); + *tp++ = '='; + } + + + /* We mainly ignore the prefix format string when the + address-mode syntax is output. */ + switch (prefix_opcodep->match) + { + case DIP_OPCODE: + /* It's [r], [r+] or [pc+]. */ + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + /* It's [pc+]. This cannot possibly be anything + but an address. */ + unsigned long number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + + info->target = (bfd_vma) number; + + /* Finish off and output previous formatted + data. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + /* For a memref in an address, we use target2. + In this case, target is zero. */ + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM); + + info->target2 = prefix_insn & 15; + + *tp++ = '['; + tp = format_reg (prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + } + break; + + case BDAP_QUICK_OPCODE: + { + int number; + + number = prefix_buffer[0]; + if (number > 127) + number -= 256; + + /* Output "reg+num" or, if num < 0, "reg-num". */ + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = (prefix_insn >> 12) & 15; + info->target2 = (bfd_vma) number; + break; + } + + case BIAP_OPCODE: + /* Output "r+R.m". */ + tp = format_reg (prefix_insn & 15, tp, with_reg_prefix); + *tp++ = '+'; + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 + : ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); + + /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */ + if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) + /* Then start interpreting data as offsets. */ + case_offset_counter = no_of_case_offsets; + break; + + case BDAP_INDIR_OPCODE: + /* Output "r+s.m", or, if "s" is [pc+], "r+s" or + "r-s". */ + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + long number; + unsigned int nbytes; + + /* It's a value. Get its size. */ + int mode_size = 1 << ((prefix_insn >> 4) & 3); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + + switch (nbytes) + { + case 1: + number = prefix_buffer[2]; + if (number > 127) + number -= 256; + break; + + case 2: + number = prefix_buffer[2] + prefix_buffer[3] * 256; + if (number > 32767) + number -= 65536; + break; + + case 4: + number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target2 = (bfd_vma) number; + + /* If the size is dword, then assume it's an + address. */ + if (nbytes == 4) + { + /* Finish off and output previous formatted + bytes. */ + *tp++ = '+'; + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + } + } + else + { + /* Output "r+[R].m" or "r+[R+].m". */ + *tp++ = '+'; + *tp++ = '['; + tp = format_reg (prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | (((prefix_insn >> 4) == 2) + ? 0 + : (((prefix_insn >> 4) & 3) == 1 + ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD + : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); + } + break; + + default: + (*info->fprintf_func) (info->stream, "?prefix-bug"); + } + + /* To mark that the prefix is used, reset it. */ + prefix_opcodep = NULL; + } + else + { + tp = format_reg (insn & 15, tp, with_reg_prefix); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = insn & 15; + + if (insn & 0x400) + *tp++ = '+'; + } + *tp++ = ']'; + } + break; + + case 'x': + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(insn >> 4) & 3]; + break; + + case 'I': + tp = format_dec (insn & 63, tp, 0); + break; + + case 'b': + { + int where = buffer[2] + buffer[3] * 256; + + if (where > 32767) + where -= 65536; + + where += addr + 4; + + if (insn == BA_PC_INCR_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + info->target = (bfd_vma) where; + + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s%s ", + temp, cris_cc_strings[insn >> 12]); + + (*info->print_address_func) ((bfd_vma) where, info); + } + break; + + case 'c': + tp = format_dec (insn & 31, tp, 0); + break; + + case 'C': + tp = format_dec (insn & 15, tp, 0); + break; + + case 'o': + { + long offset = insn & 0xfe; + + if (insn & 1) + offset |= ~0xff; + + if (opcodep->match == BA_QUICK_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + info->target = (bfd_vma) (addr + 2 + offset); + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) (addr + 2 + offset), info); + } + break; + + case 'O': + { + long number = buffer[0]; + + if (number > 127) + number = number - 256; + + tp = format_dec (number, tp, 1); + *tp++ = ','; + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + } + break; + + case 'f': + tp = print_flags (insn, tp); + break; + + case 'i': + tp = format_dec ((insn & 32) ? (insn & 31) | ~31 : insn & 31, tp, 1); + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + if (sregp->name == NULL) + /* Should have been caught as a non-match eariler. */ + *tp++ = '?'; + else + { + if (with_reg_prefix) + *tp++ = REGISTER_PREFIX_CHAR; + strcpy (tp, sregp->name); + tp += strlen (tp); + } + } + break; + + default: + strcpy (tp, "???"); + tp += 3; + } + } + + *tp = 0; + + if (prefix_opcodep) + (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")", + prefix_opcodep->name, prefix_opcodep->args); + + (*info->fprintf_func) (info->stream, "%s", temp); + + /* Get info for matching case-tables, if we don't have any active. + We assume that the last constant seen is used; either in the insn + itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */ + if (TRACE_CASE && case_offset_counter == 0) + { + if (strncmp (opcodep->name, "sub", 3) == 0) + case_offset = last_immediate; + + /* It could also be an "add", if there are negative case-values. */ + else if (strncmp (opcodep->name, "add", 3) == 0) + { + /* The first case is the negated operand to the add. */ + case_offset = -last_immediate; + } + /* A bound insn will tell us the number of cases. */ + else if (strncmp (opcodep->name, "bound", 5) == 0) + { + no_of_case_offsets = last_immediate + 1; + } + /* A jump or jsr or branch breaks the chain of insns for a + case-table, so assume default first-case again. */ + else if (info->insn_type == dis_jsr + || info->insn_type == dis_branch + || info->insn_type == dis_condbranch) + case_offset = 0; + } +} + + +/* Print the CRIS instruction at address memaddr on stream. Returns + length of the instruction, in bytes. Prefix register names with `$' if + WITH_REG_PREFIX. */ + +static int +print_insn_cris_generic (memaddr, info, with_reg_prefix) + bfd_vma memaddr; + disassemble_info *info; + boolean with_reg_prefix; +{ + int nbytes; + unsigned int insn; + const struct cris_opcode *matchedp; + int advance = 0; + + /* No instruction will be disassembled as longer than this number of + bytes; stacked prefixes will not be expanded. */ + unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; + unsigned char *bufp; + int status; + bfd_vma addr; + + /* There will be an "out of range" error after the last instruction. + Reading pairs of bytes in decreasing number, we hope that we will get + at least the amount that we will consume. + + If we can't get any data, or we do not get enough data, we print + the error message. */ + + for (nbytes = MAX_BYTES_PER_CRIS_INSN; nbytes > 0; nbytes -= 2) + { + status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); + if (status == 0) + break; + } + + /* If we did not get all we asked for, then clear the rest. + Hopefully this makes a reproducible result in case of errors. */ + if (nbytes != MAX_BYTES_PER_CRIS_INSN) + memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes); + + addr = memaddr; + bufp = buffer; + + /* Set some defaults for the insn info. */ + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->flags = 0; + info->target = 0; + info->target2 = 0; + + /* If we got any data, disassemble it. */ + if (nbytes != 0) + { + matchedp = NULL; + + insn = bufp[0] + bufp[1] * 256; + + /* If we're in a case-table, don't disassemble the offsets. */ + if (TRACE_CASE && case_offset_counter != 0) + { + info->insn_type = dis_noninsn; + advance += 2; + + /* If to print data as offsets, then shortcut here. */ + (*info->fprintf_func) (info->stream, "case %d%s: -> ", + case_offset + no_of_case_offsets + - case_offset_counter, + case_offset_counter == 1 ? "/default" : + ""); + + (*info->print_address_func) ((bfd_vma) + ((short) (insn) + + (long) (addr + - (no_of_case_offsets + - case_offset_counter) + * 2)), info); + case_offset_counter--; + + /* The default case start (without a "sub" or "add") must be + zero. */ + if (case_offset_counter == 0) + case_offset = 0; + } + else if (insn == 0) + { + /* We're often called to disassemble zeroes. While this is a + valid "bcc .+2" insn, it is also useless enough and enough + of a nuiscance that we will just output "bcc .+2" for it + and signal it as a noninsn. */ + (*info->fprintf_func) (info->stream, "bcc .+2"); + info->insn_type = dis_noninsn; + advance += 2; + } + else + { + const struct cris_opcode *prefix_opcodep = NULL; + unsigned char *prefix_buffer = bufp; + unsigned int prefix_insn = insn; + int prefix_size = 0; + + matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX); + + /* Check if we're supposed to write out prefixes as address + modes and if this was a prefix. */ + if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') + { + /* If it's a prefix, put it into the prefix vars and get the + main insn. */ + prefix_size = bytes_to_skip (prefix_insn, matchedp); + prefix_opcodep = matchedp; + + insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; + matchedp = get_opcode_entry (insn, prefix_insn); + + if (matchedp != NULL) + { + addr += prefix_size; + bufp += prefix_size; + advance += prefix_size; + } + else + { + /* The "main" insn wasn't valid, at least not when + prefixed. Put back things enough to output the + prefix insn only, as a normal insn. */ + matchedp = prefix_opcodep; + insn = prefix_insn; + prefix_opcodep = NULL; + } + } + + if (matchedp == NULL) + { + (*info->fprintf_func) (info->stream, "??0x%lx", insn); + advance += 2; + + info->insn_type = dis_noninsn; + } + else + { + advance += bytes_to_skip (insn, matchedp); + + /* The info_type and assorted fields will be set according + to the operands. */ + print_with_operands (matchedp, insn, bufp, addr, info, + prefix_opcodep, prefix_insn, + prefix_buffer, with_reg_prefix); + } + } + } + else + info->insn_type = dis_noninsn; + + /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error + status when reading that much, and the insn decoding indicated a + length exceeding what we read, there is an error. */ + if (status != 0 && (nbytes == 0 || advance > nbytes)) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Max supported insn size with one folded prefix insn. */ + info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; + + /* I would like to set this to a fixed value larger than the actual + number of bytes to print in order to avoid spaces between bytes, + but objdump.c (2.9.1) does not like that, so we print 16-bit + chunks, which is the next choice. */ + info->bytes_per_chunk = 2; + + /* Printing bytes in order of increasing addresses makes sense, + especially on a little-endian target. + This is completely the opposite of what you think; setting this to + BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N + we want. */ + info->display_endian = BFD_ENDIAN_BIG; + + return advance; +} + +/* Disassemble, prefixing register names with `$'. */ + +static int +print_insn_cris_with_register_prefix (vma, info) + bfd_vma vma; + disassemble_info *info; +{ + return print_insn_cris_generic (vma, info, true); +} + +/* Disassemble, no prefixes on register names. */ + +static int +print_insn_cris_without_register_prefix (vma, info) + bfd_vma vma; + disassemble_info *info; +{ + return print_insn_cris_generic (vma, info, false); +} + +/* Return a disassembler-function that prints registers with a `$' prefix, + or one that prints registers without a prefix. */ + +disassembler_ftype +cris_get_disassembler (abfd) + bfd *abfd; +{ + /* If there's no bfd in sight, we return what is valid as input in all + contexts if fed back to the assembler: disassembly *with* register + prefix. */ + if (abfd == NULL || bfd_get_symbol_leading_char (abfd) == 0) + return print_insn_cris_with_register_prefix; + + return print_insn_cris_without_register_prefix; +} + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/gnu/usr.bin/binutils/opcodes/cris-opc.c b/gnu/usr.bin/binutils/opcodes/cris-opc.c new file mode 100644 index 00000000000..a1ed19c6af4 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/cris-opc.c @@ -0,0 +1,885 @@ +/* cris-opc.c -- Table of opcodes for the CRIS processor. + Copyright 2000 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Reorganized by Hans-Peter Nilsson. + +This file is part of GAS, GDB and the GNU binutils. + +GAS, GDB, and GNU binutils is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2, or (at your +option) any later version. + +GAS, GDB, and GNU binutils are distributed in the hope that they will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "opcode/cris.h" + +#ifndef NULL +#define NULL (0) +#endif + +const struct cris_spec_reg +cris_spec_regs[] = +{ + {"p0", 0, 1, 0, NULL}, + {"vr", 1, 1, 0, NULL}, + {"p1", 1, 1, 0, NULL}, + {"p2", 2, 1, cris_ver_warning, NULL}, + {"p3", 3, 1, cris_ver_warning, NULL}, + {"p4", 4, 2, 0, NULL}, + {"ccr", 5, 2, 0, NULL}, + {"p5", 5, 2, 0, NULL}, + {"dcr0",6, 2, cris_ver_v0_3, NULL}, + {"p6", 6, 2, cris_ver_v0_3, NULL}, + {"dcr1/mof", 7, 4, cris_ver_v10p, + "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, + {"dcr1/mof", 7, 2, cris_ver_v0_3, + "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, + {"mof", 7, 4, cris_ver_v10p, NULL}, + {"dcr1",7, 2, cris_ver_v0_3, NULL}, + {"p7", 7, 4, cris_ver_v10p, NULL}, + {"p7", 7, 2, cris_ver_v0_3, NULL}, + {"p8", 8, 4, 0, NULL}, + {"ibr", 9, 4, 0, NULL}, + {"p9", 9, 4, 0, NULL}, + {"irp", 10, 4, 0, NULL}, + {"p10", 10, 4, 0, NULL}, + {"srp", 11, 4, 0, NULL}, + {"p11", 11, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"bar/dtp0", 12, 4, cris_ver_warning, + "Ambiguous register `bar/dtp0' specified"}, + {"bar", 12, 4, cris_ver_v8p, NULL}, + {"dtp0",12, 4, cris_ver_v0_3, NULL}, + {"p12", 12, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"dccr/dtp1",13, 4, cris_ver_warning, + "Ambiguous register `dccr/dtp1' specified"}, + {"dccr",13, 4, cris_ver_v8p, NULL}, + {"dtp1",13, 4, cris_ver_v0_3, NULL}, + {"p13", 13, 4, 0, NULL}, + {"brp", 14, 4, cris_ver_v3p, NULL}, + {"p14", 14, 4, cris_ver_v3p, NULL}, + {"usp", 15, 4, cris_ver_v10p, NULL}, + {"p15", 15, 4, cris_ver_v10p, NULL}, + {NULL, 0, 0, NULL} +}; + +/* All CRIS opcodes are 16 bits. + + - The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + - The args component is a string containing characters symbolically + matching the operands of an instruction. Used for both assembly + and disassembly. + + Operand-matching characters: + B Not really an operand. It causes a "BDAP -size,SP" prefix to be + output for the PUSH alias-instructions and recognizes a + push-prefix at disassembly. Must be followed by a R or P letter. + ! Non-match pattern, will not match if there's a prefix insn. + b Non-matching operand, used for branches with 16-bit + displacement. Only recognized by the disassembler. + c 5-bit unsigned immediate in bits <4:0>. + C 4-bit unsigned immediate in bits <3:0>. + D General register in bits <15:12> and <3:0>. + f List of flags in bits <15:12> and <3:0>. + i 6-bit signed immediate in bits <5:0>. + I 6-bit unsigned immediate in bits <5:0>. + M Size modifier (B, W or D) for CLEAR instructions. + m Size modifier (B, W or D) in bits <5:4> + o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit + branch instructions. + O [-128..127] offset in bits <7:0>. Also matches a comma and a + general register after the expression. Used only for the BDAP + prefix insn. + P Special register in bits <15:12>. + p Indicates that the insn is a prefix insn. Must be first + character. + R General register in bits <15:12>. + r General register in bits <3:0>. + S Source operand in bit <10> and a prefix; a 3-operand prefix + without side-effect. + s Source operand in bits <10> and <3:0>, optionally with a + side-effect prefix. + x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. + y Like 's' but do not allow an integer at assembly. + z Size modifier (B or W) in bit <4>. */ + + +/* Please note the order of the opcodes in this table is significant. + The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler might not recognize + them, or may indicate and internal error. + + The disassembler should not normally care about the order of the + opcodes, but will prefer an earlier alternative if the "match-score" + (see cris-dis.c) is computed as equal. + + It should not be significant for proper execution that this table is + in alphabetical order, but please follow that convention for an easy + overview. */ + +const struct cris_opcode +cris_opcodes[] = +{ + {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, + cris_abs_op}, + + {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, + cris_addi_op}, + + {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, + cris_asr_op}, + + {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, + cris_asrq_op}, + + {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + /* FIXME: Should use branch #defines. */ + {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, + cris_sixteen_bit_offset_branch_op}, + + {"ba", + BA_QUICK_OPCODE, + 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bcc", + BRANCH_QUICK_OPCODE+CC_CC*0x1000, + 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bcs", + BRANCH_QUICK_OPCODE+CC_CS*0x1000, + 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bdap", + BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD, 0, + cris_bdap_prefix}, + + {"bdap", + BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 0, + cris_quick_mode_bdap_prefix}, + + {"beq", + BRANCH_QUICK_OPCODE+CC_EQ*0x1000, + 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + /* This is deliberately put before "bext" to trump it, even though not + in alphabetical order. */ + {"bwf", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v10p, + cris_eight_bit_offset_branch_op}, + + {"bext", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v0_3, + cris_eight_bit_offset_branch_op}, + + {"bge", + BRANCH_QUICK_OPCODE+CC_GE*0x1000, + 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bgt", + BRANCH_QUICK_OPCODE+CC_GT*0x1000, + 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhi", + BRANCH_QUICK_OPCODE+CC_HI*0x1000, + 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhs", + BRANCH_QUICK_OPCODE+CC_HS*0x1000, + 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 0, + cris_biap_prefix}, + + {"ble", + BRANCH_QUICK_OPCODE+CC_LE*0x1000, + 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blo", + BRANCH_QUICK_OPCODE+CC_LO*0x1000, + 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bls", + BRANCH_QUICK_OPCODE+CC_LS*0x1000, + 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blt", + BRANCH_QUICK_OPCODE+CC_LT*0x1000, + 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmi", + BRANCH_QUICK_OPCODE+CC_MI*0x1000, + 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, + cris_ver_sim, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, + cris_ver_sim, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, + cris_ver_sim, + cris_not_implemented_op}, + + {"bne", + BRANCH_QUICK_OPCODE+CC_NE*0x1000, + 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_bound_op}, + {"bpl", + BRANCH_QUICK_OPCODE+CC_PL*0x1000, + 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, + cris_ver_v3p, + cris_break_op}, + + {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + {"bvc", + BRANCH_QUICK_OPCODE+CC_VC*0x1000, + 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bvs", + BRANCH_QUICK_OPCODE+CC_VS*0x1000, + 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, + cris_reg_mode_clear_op}, + + {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 0, + cris_dip_prefix}, + + {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, + cris_not_implemented_op}, + + {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, + cris_ver_v10p, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_none_reg_mode_jump_op}, + + {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, + cris_ver_v3p, + cris_not_implemented_op}, + + {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A30, 0x01c0, "s,P", 0, SIZE_SPEC_REG, 0, + cris_move_to_preg_op}, + + {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 0, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, + cris_move_mem_to_reg_movem_op}, + + {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 0, + cris_move_mem_to_reg_movem_op}, + + {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_muls_op}, + + {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_mulu_op}, + + {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + + {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"sa", + 0x0530+CC_A*0x1000, + 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"scc", + 0x0530+CC_CC*0x1000, + 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"scs", + 0x0530+CC_CS*0x1000, + 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"seq", + 0x0530+CC_EQ*0x1000, + 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + /* Need to have "swf" in front of "sext" so it is the one displayed in + disassembly. */ + {"swf", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v10p, + cris_scc_op}, + + {"sext", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v0_3, + cris_scc_op}, + + {"sge", + 0x0530+CC_GE*0x1000, + 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sgt", + 0x0530+CC_GT*0x1000, + 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shi", + 0x0530+CC_HI*0x1000, + 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shs", + 0x0530+CC_HS*0x1000, + 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sle", + 0x0530+CC_LE*0x1000, + 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slo", + 0x0530+CC_LO*0x1000, + 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sls", + 0x0530+CC_LS*0x1000, + 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slt", + 0x0530+CC_LT*0x1000, + 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"smi", + 0x0530+CC_MI*0x1000, + 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sne", + 0x0530+CC_NE*0x1000, + 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"spl", + 0x0530+CC_PL*0x1000, + 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"svc", + 0x0530+CC_VC*0x1000, + 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"svs", + 0x0530+CC_VS*0x1000, + 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + /* The insn "swapn" is the same as "not" and will be disassembled as + such, but the swap* family of mnmonics are generally v8-and-higher + only, so count it in. */ + {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 0, + cris_reg_mode_test_op}, + + {"test", 0x0b80, 0xf040, "m s", 0, SIZE_FIELD, 0, + cris_none_reg_mode_clear_test_op}, + + {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, + cris_xor_op}, + + {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} +}; + +/* Condition-names, indexed by the CC_* numbers as found in cris.h. */ +const char * const +cris_cc_strings[] = +{ + "hs", + "lo", + "ne", + "eq", + "vc", + "vs", + "pl", + "mi", + "ls", + "hi", + "ge", + "lt", + "gt", + "le", + "a", + /* In v0, this would be "ext". */ + "wf", +}; + + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/gnu/usr.bin/binutils/opcodes/d10v-dis.c b/gnu/usr.bin/binutils/opcodes/d10v-dis.c index 92da134eb9f..013ee1410d3 100644 --- a/gnu/usr.bin/binutils/opcodes/d10v-dis.c +++ b/gnu/usr.bin/binutils/opcodes/d10v-dis.c @@ -1,5 +1,5 @@ /* Disassemble D10V instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/d10v-opc.c b/gnu/usr.bin/binutils/opcodes/d10v-opc.c index 94436d4d826..1e099b6cee3 100644 --- a/gnu/usr.bin/binutils/opcodes/d10v-opc.c +++ b/gnu/usr.bin/binutils/opcodes/d10v-opc.c @@ -1,5 +1,5 @@ /* d10v-opc.c -- D10V opcode list - Copyright 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. Written by Martin Hunt, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -179,11 +179,11 @@ const struct d10v_opcode d10v_opcodes[] = { { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } }, { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "bl.s", SHORT_B, 3, MU, BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } }, + { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } }, { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } }, { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }, { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "bra.s", SHORT_B, 3, MU, BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } }, + { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } }, { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } }, @@ -208,7 +208,7 @@ const struct d10v_opcode d10v_opcodes[] = { { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } }, { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } }, { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } }, - { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } }, + { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } }, { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } }, { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } }, @@ -220,8 +220,8 @@ const struct d10v_opcode d10v_opcodes[] = { { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } }, { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, - { "jl", SHORT_2, 3, MU, BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } }, - { "jmp", SHORT_2, 3, MU, BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } }, + { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } }, + { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } }, { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } }, { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } }, @@ -288,13 +288,13 @@ const struct d10v_opcode d10v_opcodes[] = { { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } }, - { "rtd", SHORT_2, 3, MU, PAR, 0x5f60, 0x7fff, { 0 } }, - { "rte", SHORT_2, 3, MU, PAR, 0x5f40, 0x7fff, { 0 } }, + { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } }, + { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } }, { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } }, { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } }, { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } }, - { "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } }, + { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } }, { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } }, @@ -323,7 +323,7 @@ const struct d10v_opcode d10v_opcodes[] = { { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } }, { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, - { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, + { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } }, { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } }, { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } }, { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } }, @@ -333,10 +333,10 @@ const struct d10v_opcode d10v_opcodes[] = { { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } }, - { "trap", SHORT_2, 5, MU, BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } }, + { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } }, { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "wait", SHORT_2, 1, MU, PAR, 0x5f80, 0x7fff, { 0 } }, + { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } }, { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } }, { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } }, { 0, 0, 0, 0, 0, 0, 0, { 0 } }, diff --git a/gnu/usr.bin/binutils/opcodes/d30v-dis.c b/gnu/usr.bin/binutils/opcodes/d30v-dis.c index a579f7d8b50..080c4ef5120 100644 --- a/gnu/usr.bin/binutils/opcodes/d30v-dis.c +++ b/gnu/usr.bin/binutils/opcodes/d30v-dis.c @@ -1,5 +1,5 @@ /* Disassemble D30V instructions. - Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc. + Copyright 1997, 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -15,8 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include "sysdep.h" #include <stdio.h> +#include "sysdep.h" #include "opcode/d30v.h" #include "dis-asm.h" #include "opintl.h" diff --git a/gnu/usr.bin/binutils/opcodes/d30v-opc.c b/gnu/usr.bin/binutils/opcodes/d30v-opc.c index 9dcc156a4d4..6fe993ad128 100644 --- a/gnu/usr.bin/binutils/opcodes/d30v-opc.c +++ b/gnu/usr.bin/binutils/opcodes/d30v-opc.c @@ -1,5 +1,5 @@ /* d30v-opc.c -- D30V opcode list - Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc. + Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc. Written by Martin Hunt, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -349,7 +349,9 @@ const struct d30v_operand d30v_operand_table[] = { 6, 6, 0, OPERAND_REG }, #define Rb (Ra3 + 1) { 6, 6, 6, OPERAND_REG }, -#define Rc (Rb + 1) +#define Rb2 (Rb + 1) + { 6, 6, 6, OPERAND_REG|OPERAND_DEST }, +#define Rc (Rb2 + 1) { 6, 6, 12, OPERAND_REG }, #define Aa (Rc + 1) { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, @@ -460,8 +462,8 @@ const struct d30v_format d30v_format_table[] = { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */ - { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */ - { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */ + { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */ + { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */ { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ diff --git a/gnu/usr.bin/binutils/opcodes/fr30-asm.c b/gnu/usr.bin/binutils/opcodes/fr30-asm.c index 6038dbba917..be64b77bfee 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-asm.c +++ b/gnu/usr.bin/binutils/opcodes/fr30-asm.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-asm.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -398,7 +398,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (*str == CGEN_SYNTAX_CHAR (* syn)) + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (* syn == ' ') @@ -410,9 +410,11 @@ parse_insn_normal (cd, insn, strp, fields) else { /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); + static char msg [80]; + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + *syn, *str); + return msg; } continue; } @@ -478,6 +480,7 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) { const char *start; CGEN_INSN_LIST *ilist; + const char *tmp_errmsg = NULL; /* Skip leading white space. */ while (isspace (* str)) @@ -494,7 +497,8 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) { const CGEN_INSN *insn = ilist->insn; -#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* not usually needed as unsupported opcodes shouldn't be in the hash lists */ /* Is this insn supported by the selected cpu? */ if (! fr30_cgen_insn_supported (cd, insn)) continue; @@ -511,30 +515,44 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) /* Allow parse/insert handlers to obtain length of insn. */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - if (! CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields)) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0) - != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } + tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (tmp_errmsg != NULL) + continue; - /* Try the next entry. */ + /* ??? 0 is passed for `pc' */ + tmp_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (tmp_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; } - /* FIXME: We can return a better error message than this. - Need to track why it failed and pick the right one. */ + /* Make sure we leave this with something at this point. */ + if (tmp_errmsg == NULL) + tmp_errmsg = "unknown mnemonic"; + { - static char errbuf[100]; + static char errbuf[150]; + +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + /* if verbose error messages, use errmsg from CGEN_PARSE_FN */ + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else if (strlen (start) > 50) /* xgettext:c-format */ sprintf (errbuf, _("bad instruction `%.50s...'"), start); else /* xgettext:c-format */ sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif *errmsg = errbuf; return NULL; diff --git a/gnu/usr.bin/binutils/opcodes/fr30-desc.c b/gnu/usr.bin/binutils/opcodes/fr30-desc.c index 810f04b9dcc..208f7ec323c 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-desc.c +++ b/gnu/usr.bin/binutils/opcodes/fr30-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "fr30-desc.h" #include "fr30-opc.h" #include "opintl.h" +#include "libiberty.h" /* Attributes. */ @@ -59,7 +60,7 @@ static const CGEN_ATTR_ENTRY ISA_attr[] = const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, @@ -71,7 +72,7 @@ const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, { "PC", &bool_attr[0], &bool_attr[0] }, @@ -81,7 +82,7 @@ const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, @@ -96,7 +97,7 @@ const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, @@ -114,130 +115,137 @@ const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = /* Instruction set variants. */ static const CGEN_ISA fr30_cgen_isa_table[] = { - { "fr30", 16, 16, 16, 48, }, - { 0 } + { "fr30", 16, 16, 16, 48 }, + { 0, 0, 0, 0, 0 } }; /* Machine variants. */ static const CGEN_MACH fr30_cgen_mach_table[] = { { "fr30", "fr30", MACH_FR30 }, - { 0 } + { 0, 0, 0 } }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = { - { "r0", 0 }, - { "r1", 1 }, - { "r2", 2 }, - { "r3", 3 }, - { "r4", 4 }, - { "r5", 5 }, - { "r6", 6 }, - { "r7", 7 }, - { "r8", 8 }, - { "r9", 9 }, - { "r10", 10 }, - { "r11", 11 }, - { "r12", 12 }, - { "r13", 13 }, - { "r14", 14 }, - { "r15", 15 }, - { "ac", 13 }, - { "fp", 14 }, - { "sp", 15 } + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "ac", 13, {0, {0}}, 0, 0 }, + { "fp", 14, {0, {0}}, 0, 0 }, + { "sp", 15, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_gr_names = { & fr30_cgen_opval_gr_names_entries[0], - 19 + 19, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = { - { "cr0", 0 }, - { "cr1", 1 }, - { "cr2", 2 }, - { "cr3", 3 }, - { "cr4", 4 }, - { "cr5", 5 }, - { "cr6", 6 }, - { "cr7", 7 }, - { "cr8", 8 }, - { "cr9", 9 }, - { "cr10", 10 }, - { "cr11", 11 }, - { "cr12", 12 }, - { "cr13", 13 }, - { "cr14", 14 }, - { "cr15", 15 } + { "cr0", 0, {0, {0}}, 0, 0 }, + { "cr1", 1, {0, {0}}, 0, 0 }, + { "cr2", 2, {0, {0}}, 0, 0 }, + { "cr3", 3, {0, {0}}, 0, 0 }, + { "cr4", 4, {0, {0}}, 0, 0 }, + { "cr5", 5, {0, {0}}, 0, 0 }, + { "cr6", 6, {0, {0}}, 0, 0 }, + { "cr7", 7, {0, {0}}, 0, 0 }, + { "cr8", 8, {0, {0}}, 0, 0 }, + { "cr9", 9, {0, {0}}, 0, 0 }, + { "cr10", 10, {0, {0}}, 0, 0 }, + { "cr11", 11, {0, {0}}, 0, 0 }, + { "cr12", 12, {0, {0}}, 0, 0 }, + { "cr13", 13, {0, {0}}, 0, 0 }, + { "cr14", 14, {0, {0}}, 0, 0 }, + { "cr15", 15, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_cr_names = { & fr30_cgen_opval_cr_names_entries[0], - 16 + 16, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = { - { "tbr", 0 }, - { "rp", 1 }, - { "ssp", 2 }, - { "usp", 3 }, - { "mdh", 4 }, - { "mdl", 5 } + { "tbr", 0, {0, {0}}, 0, 0 }, + { "rp", 1, {0, {0}}, 0, 0 }, + { "ssp", 2, {0, {0}}, 0, 0 }, + { "usp", 3, {0, {0}}, 0, 0 }, + { "mdh", 4, {0, {0}}, 0, 0 }, + { "mdl", 5, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_dr_names = { & fr30_cgen_opval_dr_names_entries[0], - 6 + 6, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = { - { "ps", 0 } + { "ps", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_ps = { & fr30_cgen_opval_h_ps_entries[0], - 1 + 1, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = { - { "r13", 0 } + { "r13", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r13 = { & fr30_cgen_opval_h_r13_entries[0], - 1 + 1, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = { - { "r14", 0 } + { "r14", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r14 = { & fr30_cgen_opval_h_r14_entries[0], - 1 + 1, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = { - { "r15", 0 } + { "r15", 0, {0, {0}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r15 = { & fr30_cgen_opval_h_r15_entries[0], - 1 + 1, + 0, 0, 0, 0 }; @@ -273,7 +281,7 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] = { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } }; #undef A @@ -285,6 +293,7 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] = const CGEN_IFLD fr30_cgen_ifld_table[] = { { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } }, { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } }, { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, @@ -324,7 +333,7 @@ const CGEN_IFLD fr30_cgen_ifld_table[] = { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, 0, 0, 0, 0, {0, {0}} } }; #undef A @@ -483,7 +492,7 @@ const CGEN_OPERAND fr30_cgen_operand_table[] = /* ilm: interrupt level mask */ { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, 0, 0, 0, {0, {0}} } }; #undef A @@ -498,7 +507,7 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0 }, + { 0, 0, 0, 0, {0, {0}} }, /* add $Rj,$Ri */ { FR30_INSN_ADD, "add", "add", 16, @@ -1446,9 +1455,11 @@ static void fr30_cgen_rebuild_tables (cd) CGEN_CPU_TABLE *cd; { - int i,n_isas,n_machs; + int i,n_isas; unsigned int isas = cd->isas; +#if 0 unsigned int machs = cd->machs; +#endif cd->int_insn_p = CGEN_INT_INSN_P; @@ -1490,6 +1501,7 @@ fr30_cgen_rebuild_tables (cd) ++n_isas; } +#if 0 /* Does nothing?? */ /* Data derived from the mach spec. */ for (i = 0; i < MAX_MACHS; ++i) if (((1 << i) & machs) != 0) @@ -1498,6 +1510,7 @@ fr30_cgen_rebuild_tables (cd) ++n_machs; } +#endif /* Determine which hw elements are used by MACH. */ build_hw_table (cd); @@ -1609,6 +1622,9 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) cd->rebuild_tables = fr30_cgen_rebuild_tables; fr30_cgen_rebuild_tables (cd); + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + return (CGEN_CPU_DESC) cd; } diff --git a/gnu/usr.bin/binutils/opcodes/fr30-desc.h b/gnu/usr.bin/binutils/opcodes/fr30-desc.h index 97e29cd1bdb..c69ef765fb5 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-desc.h +++ b/gnu/usr.bin/binutils/opcodes/fr30-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -43,18 +43,16 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INT_INSN_P 0 -/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ +/* Maximum nymber of syntax bytes in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands we can't hash on everything up to the space. */ #define CGEN_MNEMONIC_OPERANDS -/* Maximum number of operands any insn or macro-insn has. */ -#define CGEN_MAX_INSN_OPERANDS 16 - /* Maximum number of fields in an instruction. */ -#define CGEN_MAX_IFMT_OPERANDS 7 +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 /* Enums. */ @@ -157,17 +155,17 @@ typedef enum cgen_ifld_attr { /* Enum declaration for fr30 ifield types. */ typedef enum ifield_type { - FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3 - , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC - , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2 - , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI - , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4 - , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16 - , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8 - , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10 - , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10 - , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD - , FR30_F_REGLIST_LOW_LD, FR30_F_MAX + FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 + , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC + , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 + , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ + , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 + , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 + , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 + , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 + , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 + , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST + , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX } IFIELD_TYPE; #define MAX_IFLD ((int) FR30_F_MAX) @@ -227,7 +225,7 @@ typedef enum cgen_operand_type { } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS ((int) FR30_OPERAND_MAX) +#define MAX_OPERANDS 49 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 diff --git a/gnu/usr.bin/binutils/opcodes/fr30-dis.c b/gnu/usr.bin/binutils/opcodes/fr30-dis.c index c42915b8fe3..18d4e85083a 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-dis.c +++ b/gnu/usr.bin/binutils/opcodes/fr30-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -96,60 +96,60 @@ print_register_list (dis_info, value, offset, load_store) static void print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; - unsigned int attrs; - bfd_vma pc; - int length; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { print_register_list (dis_info, value, 8, 0/*load*/); } static void print_low_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; - unsigned int attrs; - bfd_vma pc; - int length; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { print_register_list (dis_info, value, 0, 0/*load*/); } static void print_hi_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; - unsigned int attrs; - bfd_vma pc; - int length; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { print_register_list (dis_info, value, 8, 1/*store*/); } static void print_low_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; - unsigned int attrs; - bfd_vma pc; - int length; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { print_register_list (dis_info, value, 0, 1/*store*/); } static void print_m4 (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; - unsigned int attrs; - bfd_vma pc; - int length; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "%ld", value); @@ -178,7 +178,7 @@ fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) int opindex; PTR xinfo; CGEN_FIELDS *fields; - void const *attrs; + void const *attrs ATTRIBUTE_UNUSED; bfd_vma pc; int length; { @@ -324,12 +324,21 @@ fr30_cgen_init_dis (cd) static void print_normal (cd, dis_info, value, attrs, pc, length) +#ifdef CGEN_PRINT_NORMAL CGEN_CPU_DESC cd; +#else + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; +#endif PTR dis_info; long value; unsigned int attrs; +#ifdef CGEN_PRINT_NORMAL bfd_vma pc; int length; +#else + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -350,12 +359,21 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) +#ifdef CGEN_PRINT_NORMAL CGEN_CPU_DESC cd; +#else + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; +#endif PTR dis_info; bfd_vma value; unsigned int attrs; +#ifdef CGEN_PRINT_NORMAL bfd_vma pc; int length; +#else + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -380,11 +398,11 @@ print_address (cd, dis_info, value, attrs, pc, length) static void print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; CGEN_KEYWORD *keyword_table; long value; - unsigned int attrs; + unsigned int attrs ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -435,43 +453,70 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) } } -/* Utility to print an insn. - BUF is the base part of the insn, target byte order, BUFLEN bytes long. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; bfd_vma pc; disassemble_info *info; char *buf; int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; { - unsigned long insn_value; - const CGEN_INSN_LIST *insn_list; - CGEN_EXTRACT_INFO ex_info; + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } - ex_info.dis_info = info; - ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1; - ex_info.insn_bytes = buf; + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; switch (buflen) { case 1: - insn_value = buf[0]; + *insn_value = buf[0]; break; case 2: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); + *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); break; case 4: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); + *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); break; default: abort (); } + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; +{ + unsigned long insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + + int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value); + if (rc != 0) + return rc; + /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ @@ -482,10 +527,14 @@ print_insn (cd, pc, info, buf, buflen) CGEN_FIELDS fields; int length; -#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* not needed as insn shouldn't be in hash lists if not supported */ /* Supported by this cpu? */ if (! fr30_cgen_insn_supported (cd, insn)) - continue; + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } #endif /* Basic bit mask must be correct. */ @@ -498,8 +547,24 @@ print_insn (cd, pc, info, buf, buflen) machine insn and extracts the fields. The second pass prints them. */ - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value, &fields, pc); + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value, &fields, pc); + /* length < 0 -> error */ if (length < 0) return length; @@ -556,7 +621,9 @@ print_insn_fr30 (pc, info) disassemble_info *info; { static CGEN_CPU_DESC cd = 0; - static prev_isa,prev_mach,prev_endian; + static int prev_isa; + static int prev_mach; + static int prev_endian; int length; int isa,mach; int endian = (info->endian == BFD_ENDIAN_BIG diff --git a/gnu/usr.bin/binutils/opcodes/fr30-ibld.c b/gnu/usr.bin/binutils/opcodes/fr30-ibld.c index 2aa44589cf2..0d2ee67ebec 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-ibld.c +++ b/gnu/usr.bin/binutils/opcodes/fr30-ibld.c @@ -3,7 +3,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. - the resultant file is machine generated, cgen-ibld.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -57,6 +57,9 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + /* Operand insertion. */ @@ -183,9 +186,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, if (length == 0) return NULL; +#if 0 if (CGEN_INT_INSN_P && word_offset != 0) abort (); +#endif if (word_length > 32) abort (); @@ -203,6 +208,7 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) { unsigned long maxval = mask; + if ((unsigned long) value > maxval) { /* xgettext:c-format */ @@ -214,15 +220,19 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, } else { - long minval = - (1L << (length - 1)); - long maxval = (1L << (length - 1)) - 1; - if (value < minval || value > maxval) + if (! cgen_signed_overflow_ok_p (cd)) { - sprintf - /* xgettext:c-format */ - (errbuf, _("operand out of range (%ld not between %ld and %ld)"), - value, minval, maxval); - return errbuf; + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } } } @@ -232,9 +242,9 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, int shift; if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; + shift = (word_offset + start + 1) - length; else - shift = word_length - (start + length); + shift = total_length - (word_offset + start + length); *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); } @@ -278,7 +288,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #if CGEN_INT_INSN_P - *buffer = value; + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); #else @@ -308,6 +319,30 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } + +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} /* Operand extraction. */ @@ -439,11 +474,19 @@ static int extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, word_length, total_length, pc, valuep) CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif CGEN_INSN_INT insn_value; unsigned int attrs; unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif long *valuep; { CGEN_INSN_INT value; @@ -456,9 +499,11 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, return 1; } +#if 0 if (CGEN_INT_INSN_P && word_offset != 0) abort (); +#endif if (word_length > 32) abort (); @@ -474,15 +519,15 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, /* Does the value reside in INSN_VALUE? */ - if (word_offset == 0) + if (CGEN_INT_INSN_P || word_offset == 0) { /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; if (CGEN_INSN_LSB0_P) - value = insn_value >> ((start + 1) - length); + value = insn_value >> ((word_offset + start + 1) - length); else - value = insn_value >> (word_length - (start + length)); + value = insn_value >> (total_length - ( word_offset + start + length)); value &= mask; /* sign extend? */ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) @@ -858,7 +903,9 @@ fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case FR30_OPERAND_I20 : { length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4); + if (length <= 0) break; length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16); + if (length <= 0) break; { FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16))); } diff --git a/gnu/usr.bin/binutils/opcodes/fr30-opc.c b/gnu/usr.bin/binutils/opcodes/fr30-opc.c index 5ea7e0af0b8..50b86287edc 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-opc.c +++ b/gnu/usr.bin/binutils/opcodes/fr30-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -28,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "symcat.h" #include "fr30-desc.h" #include "fr30-opc.h" +#include "libiberty.h" /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ @@ -42,123 +43,123 @@ static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)] static const CGEN_IFMT ifmt_empty = { - 0, 0, 0x0, { 0 } + 0, 0, 0x0, { { 0 } } }; static const CGEN_IFMT ifmt_add = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RJ) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_addi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U4) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_add2 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_M4) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_div0s = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_div3 = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_OP4) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi8 = { - 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi20 = { - 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 } + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_I20) }, { F (F_OP2) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi32 = { - 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 } + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_I32) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldr14 = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP10) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldr14uh = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP9) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldr14ub = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP8) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldr15 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_UDISP6) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldr15dr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 } + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RS2) }, { 0 } } }; static const CGEN_IFMT ifmt_movdr = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS1) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_call = { - 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 } + 16, 16, 0xf800, { { F (F_OP1) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } }; static const CGEN_IFMT ifmt_int = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U8) }, { 0 } } }; static const CGEN_IFMT ifmt_brad = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_CC) }, { F (F_REL9) }, { 0 } } }; static const CGEN_IFMT ifmt_dmovr13 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR10) }, { 0 } } }; static const CGEN_IFMT ifmt_dmovr13h = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR9) }, { 0 } } }; static const CGEN_IFMT ifmt_dmovr13b = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR8) }, { 0 } } }; static const CGEN_IFMT ifmt_copop = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 } + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } }; static const CGEN_IFMT ifmt_copld = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 } + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RJC) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } }; static const CGEN_IFMT ifmt_copst = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 } + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_RIC) }, { 0 } } }; static const CGEN_IFMT ifmt_addsp = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S10) }, { 0 } } }; static const CGEN_IFMT ifmt_ldm0 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_LD) }, { 0 } } }; static const CGEN_IFMT ifmt_ldm1 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_LD) }, { 0 } } }; static const CGEN_IFMT ifmt_stm0 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_ST) }, { 0 } } }; static const CGEN_IFMT ifmt_stm1 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_ST) }, { 0 } } }; static const CGEN_IFMT ifmt_enter = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U10) }, { 0 } } }; #undef F @@ -175,7 +176,7 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { { 0 } }, + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, /* add $Rj,$Ri */ { { 0, 0, 0, 0 }, @@ -1178,15 +1179,15 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] = #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)] static const CGEN_IFMT ifmt_ldi8m = { - 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi20m = { - 16, 32, 0xff00, { F (F_OP1), F (F_OP2), F (F_RI), F (F_I20), 0 } + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RI) }, { F (F_I20) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi32m = { - 16, 48, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), F (F_I32), 0 } + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { F (F_I32) }, { 0 } } }; #undef F diff --git a/gnu/usr.bin/binutils/opcodes/fr30-opc.h b/gnu/usr.bin/binutils/opcodes/fr30-opc.h index d387ed55e99..33d3094efbd 100644 --- a/gnu/usr.bin/binutils/opcodes/fr30-opc.h +++ b/gnu/usr.bin/binutils/opcodes/fr30-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -91,6 +91,7 @@ struct cgen_fields { int length; long f_nil; + long f_anyof; long f_op1; long f_op2; long f_op3; diff --git a/gnu/usr.bin/binutils/opcodes/i860-dis.c b/gnu/usr.bin/binutils/opcodes/i860-dis.c new file mode 100644 index 00000000000..ba183ab3f70 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/i860-dis.c @@ -0,0 +1,288 @@ +/* Disassembler for the i860. + Copyright 2000 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt <jle@cygnus.com>. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "dis-asm.h" +#include "opcode/i860.h" + +/* Later we should probably choose the prefix based on which OS flavor. */ +#define I860_REG_PREFIX "%" + +/* Integer register names (encoded as 0..31 in the instruction). */ +static const char *const grnames[] = + {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; + +/* FP register names (encoded as 0..31 in the instruction). */ +static const char *const frnames[] = + {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; + +/* Control/status register names (encoded as 0..5 in the instruction). */ +static const char *const crnames[] = + {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""}; + + +/* Prototypes. */ +static int sign_ext PARAMS((unsigned int, int)); +static void print_br_address PARAMS((disassemble_info *, bfd_vma, long)); + + +/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */ +#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \ + || (op) == 0x34 || (op) == 0x35 \ + || (op) == 0x38 || (op) == 0x39 \ + || (op) == 0x3c || (op) == 0x3d \ + || (op) == 0x33 || (op) == 0x37 \ + || (op) == 0x3b || (op) == 0x3f) + + +/* Sign extend N-bit number. */ +static int +sign_ext (x, n) + unsigned int x; + int n; +{ + int t; + t = x >> (n - 1); + t = ((-t) << n) | x; + return t; +} + + +/* Print a PC-relative branch offset. VAL is the sign extended value + from the branch instruction. */ +static void +print_br_address (info, memaddr, val) + disassemble_info *info; + bfd_vma memaddr; + long val; +{ + + long adj = (long)memaddr + 4 + (val << 2); + + (*info->fprintf_func) (info->stream, "0x%08x", adj); + + /* Attempt to obtain a symbol for the target address. */ + + if (info->print_address_func && adj != 0) + { + (*info->fprintf_func) (info->stream, "\t// "); + (*info->print_address_func) (adj, info); + } +} + + +/* Print one instruction. */ +int +print_insn_i860 (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + bfd_byte buff[4]; + unsigned int insn, i; + int status; + const struct i860_opcode *opcode = 0; + + status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Note that i860 instructions are always accessed as little endian + data, regardless of the endian mode of the i860. */ + insn = bfd_getl32 (buff); + + status = 0; + i = 0; + while (i860_opcodes[i].name != NULL) + { + opcode = &i860_opcodes[i]; + if ((insn & opcode->match) == opcode->match + && (insn & opcode->lose) == 0) + { + status = 1; + break; + } + ++i; + } + + if (status == 0) + { + /* Instruction not in opcode table. */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + } + else + { + const char *s; + int val; + + /* If this a flop and its dual bit is set, prefix with 'd.'. */ + if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200)) + (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + + for (s = opcode->args; *s; s++) + { + switch (*s) + { + /* Integer register (src1). */ + case '1': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 11) & 0x1f]); + break; + + /* Integer register (src2). */ + case '2': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 21) & 0x1f]); + break; + + /* Integer destination register. */ + case 'd': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 16) & 0x1f]); + break; + + /* Floating-point register (src1). */ + case 'e': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 11) & 0x1f]); + break; + + /* Floating-point register (src2). */ + case 'f': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 21) & 0x1f]); + break; + + /* Floating-point destination register. */ + case 'g': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 16) & 0x1f]); + break; + + /* Control register. */ + case 'c': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + crnames[(insn >> 21) & 0x7]); + break; + + /* 16-bit immediate (sign extend, except for bitwise ops). */ + case 'i': + if (BITWISE_OP ((insn & 0xfc000000) >> 26)) + (*info->fprintf_func) (info->stream, "0x%04x", + (unsigned int) (insn & 0xffff)); + else + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^0, ld.b). */ + case 'I': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^1, ld.s). */ + case 'J': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffe), 16)); + break; + + /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */ + case 'K': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffc), 16)); + break; + + /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */ + case 'L': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff8), 16)); + break; + + /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */ + case 'M': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff0), 16)); + break; + + /* 5-bit immediate (zero extend). */ + case '5': + (*info->fprintf_func) (info->stream, "%d", + ((insn >> 11) & 0x1f)); + break; + + /* Split 16 bit immediate (20..16:10..0). */ + case 's': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^0, st.b). */ + case 'S': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^1, st.s). */ + case 'T': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fe); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^2, st.l). */ + case 'U': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fc); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* 26-bit PC relative immediate (lbroff). */ + case 'l': + val = sign_ext ((insn & 0x03ffffff), 26); + print_br_address (info, memaddr, val); + break; + + /* 16-bit PC relative immediate (sbroff). */ + case 'r': + val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); + print_br_address (info, memaddr, val); + break; + + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + } + + return sizeof (insn); +} + diff --git a/gnu/usr.bin/binutils/opcodes/ia64-asmtab.c b/gnu/usr.bin/binutils/opcodes/ia64-asmtab.c new file mode 100644 index 00000000000..03ec73c6c46 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-asmtab.c @@ -0,0 +1,7436 @@ +/* This file is automatically generated by ia64-gen. Do not edit! */ +static const char *ia64_strings[] = { + "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", + "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1", + "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1", + "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit", + "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm", + "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4", + "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin", + "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for", + "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax", + "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma", + "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc", + "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge", + "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc", + "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe", + "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs", + "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2", + "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt", + "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz", + "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1", + "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", + "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe", + "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2", + "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi", + "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf", + "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt", + "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8", + "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync", + "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc", + "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w", + "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma", + "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", +}; + +static const struct ia64_dependency +dependencies[] = { + { "ALAT", 0, 0, 0, -1, NULL, }, + { "AR[BSP]", 26, 0, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, + { "AR[CCV]", 26, 0, 2, 32, NULL, }, + { "AR[EC]", 26, 0, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, + { "AR[ITC]", 26, 0, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, + { "AR[LC]", 26, 0, 2, 65, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 0, 64, NULL, }, + { "AR[RNAT]", 26, 0, 2, 19, NULL, }, + { "AR[RSC]", 26, 0, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 0, -1, NULL, }, + { "CPUID#", 7, 0, 5, -1, NULL, }, + { "CR[CMCV]", 27, 0, 3, 74, NULL, }, + { "CR[DCR]", 27, 0, 3, 0, NULL, }, + { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 27, 0, 3, 9, NULL, }, + { "CR[IFA]", 27, 0, 1, 20, NULL, }, + { "CR[IFA]", 27, 0, 3, 20, NULL, }, + { "CR[IFS]", 27, 0, 3, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IHA]", 27, 0, 3, 25, NULL, }, + { "CR[IIM]", 27, 0, 3, 24, NULL, }, + { "CR[IIP]", 27, 0, 3, 19, NULL, }, + { "CR[IIP]", 27, 0, 1, 19, NULL, }, + { "CR[IIPA]", 27, 0, 3, 22, NULL, }, + { "CR[IPSR]", 27, 0, 3, 16, NULL, }, + { "CR[IPSR]", 27, 0, 1, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, + { "CR[ISR]", 27, 0, 3, 17, NULL, }, + { "CR[ITIR]", 27, 0, 3, 21, NULL, }, + { "CR[ITIR]", 27, 0, 1, 21, NULL, }, + { "CR[ITM]", 27, 0, 3, 1, NULL, }, + { "CR[ITV]", 27, 0, 3, 72, NULL, }, + { "CR[IVA]", 27, 0, 4, 2, NULL, }, + { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", }, + { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", }, + { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, + { "CR[PMV]", 27, 0, 3, 73, NULL, }, + { "CR[PTA]", 27, 0, 3, 8, NULL, }, + { "CR[TPR]", 27, 0, 3, 66, NULL, }, + { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, + { "DBR#", 11, 0, 2, -1, NULL, }, + { "DBR#", 11, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC", 0, 0, 0, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 0, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, + { "GR0", 14, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, + { "IBR#", 16, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 3, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "IP", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 0, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "memory", 0, 0, 0, -1, NULL, }, + { "MSR#", 18, 0, 5, -1, NULL, }, + { "PKR#", 19, 0, 3, -1, NULL, }, + { "PKR#", 19, 0, 0, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", }, + { "PMD#", 21, 0, 2, -1, NULL, }, + { "PR0", 0, 0, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 0, -1, NULL, }, + { "PSR.ac", 28, 0, 1, 3, NULL, }, + { "PSR.ac", 28, 0, 3, 3, NULL, }, + { "PSR.ac", 28, 0, 2, 3, NULL, }, + { "PSR.be", 28, 0, 1, 1, NULL, }, + { "PSR.be", 28, 0, 3, 1, NULL, }, + { "PSR.be", 28, 0, 2, 1, NULL, }, + { "PSR.bn", 28, 0, 2, 44, NULL, }, + { "PSR.cpl", 28, 0, 1, 32, NULL, }, + { "PSR.da", 28, 0, 3, 38, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.db", 28, 0, 2, 24, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.dd", 28, 0, 3, 39, NULL, }, + { "PSR.dfh", 28, 0, 3, 19, NULL, }, + { "PSR.dfh", 28, 0, 2, 19, NULL, }, + { "PSR.dfl", 28, 0, 3, 18, NULL, }, + { "PSR.dfl", 28, 0, 2, 18, NULL, }, + { "PSR.di", 28, 0, 3, 22, NULL, }, + { "PSR.di", 28, 0, 2, 22, NULL, }, + { "PSR.dt", 28, 0, 3, 17, NULL, }, + { "PSR.dt", 28, 0, 2, 17, NULL, }, + { "PSR.ed", 28, 0, 3, 43, NULL, }, + { "PSR.i", 28, 0, 2, 14, NULL, }, + { "PSR.i", 28, 0, 3, 14, NULL, }, + { "PSR.ia", 28, 0, 0, 14, NULL, }, + { "PSR.ic", 28, 0, 2, 13, NULL, }, + { "PSR.ic", 28, 0, 3, 13, NULL, }, + { "PSR.id", 28, 0, 0, 14, NULL, }, + { "PSR.is", 28, 0, 0, 14, NULL, }, + { "PSR.it", 28, 0, 3, 14, NULL, }, + { "PSR.lp", 28, 0, 2, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.mc", 28, 0, 0, 35, NULL, }, + { "PSR.mfh", 28, 0, 2, 5, NULL, }, + { "PSR.mfl", 28, 0, 2, 4, NULL, }, + { "PSR.pk", 28, 0, 3, 15, NULL, }, + { "PSR.pk", 28, 0, 2, 15, NULL, }, + { "PSR.pp", 28, 0, 2, 21, NULL, }, + { "PSR.ri", 28, 0, 0, 41, NULL, }, + { "PSR.rt", 28, 0, 2, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.si", 28, 0, 2, 23, NULL, }, + { "PSR.si", 28, 0, 3, 23, NULL, }, + { "PSR.sp", 28, 0, 2, 20, NULL, }, + { "PSR.sp", 28, 0, 3, 20, NULL, }, + { "PSR.ss", 28, 0, 3, 40, NULL, }, + { "PSR.tb", 28, 0, 3, 26, NULL, }, + { "PSR.tb", 28, 0, 2, 26, NULL, }, + { "PSR.up", 28, 0, 2, 2, NULL, }, + { "RR#", 25, 0, 3, -1, NULL, }, + { "RR#", 25, 0, 2, -1, NULL, }, + { "RSE", 29, 0, 2, -1, NULL, }, + { "ALAT", 0, 1, 0, -1, NULL, }, + { "AR[BSP]", 26, 1, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, + { "AR[CCV]", 26, 1, 2, 32, NULL, }, + { "AR[EC]", 26, 1, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, + { "AR[ITC]", 26, 1, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, + { "AR[LC]", 26, 1, 2, 65, NULL, }, + { "AR[PFS]", 26, 1, 0, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[RNAT]", 26, 1, 2, 19, NULL, }, + { "AR[RSC]", 26, 1, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, + { "CFM", 6, 1, 2, -1, NULL, }, + { "CPUID#", 7, 1, 0, -1, NULL, }, + { "CR[CMCV]", 27, 1, 2, 74, NULL, }, + { "CR[DCR]", 27, 1, 2, 0, NULL, }, + { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 27, 1, 2, 9, NULL, }, + { "CR[IFA]", 27, 1, 2, 20, NULL, }, + { "CR[IFS]", 27, 1, 2, 23, NULL, }, + { "CR[IHA]", 27, 1, 2, 25, NULL, }, + { "CR[IIM]", 27, 1, 2, 24, NULL, }, + { "CR[IIP]", 27, 1, 2, 19, NULL, }, + { "CR[IIPA]", 27, 1, 2, 22, NULL, }, + { "CR[IPSR]", 27, 1, 2, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, + { "CR[ISR]", 27, 1, 2, 17, NULL, }, + { "CR[ITIR]", 27, 1, 2, 21, NULL, }, + { "CR[ITM]", 27, 1, 2, 1, NULL, }, + { "CR[ITV]", 27, 1, 2, 72, NULL, }, + { "CR[IVA]", 27, 1, 2, 2, NULL, }, + { "CR[IVR]", 27, 1, 7, 65, "SC", }, + { "CR[LID]", 27, 1, 7, 64, "SC", }, + { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, + { "CR[PMV]", 27, 1, 2, 73, NULL, }, + { "CR[PTA]", 27, 1, 2, 8, NULL, }, + { "CR[TPR]", 27, 1, 2, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, + { "DBR#", 11, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 0, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 0, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, + { "GR0", 14, 1, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, + { "IBR#", 16, 1, 2, -1, NULL, }, + { "InService*", 17, 1, 7, -1, "SC", }, + { "IP", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 0, -1, NULL, }, + { "memory", 0, 1, 0, -1, NULL, }, + { "MSR#", 18, 1, 7, -1, "SC", }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 2, -1, NULL, }, + { "PMC#", 20, 1, 2, -1, NULL, }, + { "PMD#", 21, 1, 2, -1, NULL, }, + { "PR0", 0, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PSR.ac", 28, 1, 2, 3, NULL, }, + { "PSR.be", 28, 1, 2, 1, NULL, }, + { "PSR.bn", 28, 1, 2, 44, NULL, }, + { "PSR.cpl", 28, 1, 2, 32, NULL, }, + { "PSR.da", 28, 1, 2, 38, NULL, }, + { "PSR.db", 28, 1, 2, 24, NULL, }, + { "PSR.dd", 28, 1, 2, 39, NULL, }, + { "PSR.dfh", 28, 1, 2, 19, NULL, }, + { "PSR.dfl", 28, 1, 2, 18, NULL, }, + { "PSR.di", 28, 1, 2, 22, NULL, }, + { "PSR.dt", 28, 1, 2, 17, NULL, }, + { "PSR.ed", 28, 1, 2, 43, NULL, }, + { "PSR.i", 28, 1, 2, 14, NULL, }, + { "PSR.ia", 28, 1, 2, 14, NULL, }, + { "PSR.ic", 28, 1, 2, 13, NULL, }, + { "PSR.id", 28, 1, 2, 14, NULL, }, + { "PSR.is", 28, 1, 2, 14, NULL, }, + { "PSR.it", 28, 1, 2, 14, NULL, }, + { "PSR.lp", 28, 1, 2, 25, NULL, }, + { "PSR.mc", 28, 1, 2, 35, NULL, }, + { "PSR.mfh", 28, 1, 0, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfl", 28, 1, 0, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.pk", 28, 1, 2, 15, NULL, }, + { "PSR.pp", 28, 1, 2, 21, NULL, }, + { "PSR.ri", 28, 1, 2, 41, NULL, }, + { "PSR.rt", 28, 1, 2, 27, NULL, }, + { "PSR.si", 28, 1, 2, 23, NULL, }, + { "PSR.sp", 28, 1, 2, 20, NULL, }, + { "PSR.ss", 28, 1, 2, 40, NULL, }, + { "PSR.tb", 28, 1, 2, 26, NULL, }, + { "PSR.up", 28, 1, 2, 2, NULL, }, + { "RR#", 25, 1, 2, -1, NULL, }, + { "RSE", 29, 1, 2, -1, NULL, }, + { "PR63", 24, 2, 6, -1, NULL, }, +}; + +static const short dep0[] = { + 88, 252, 2131, 2297, +}; + +static const short dep1[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, + 20605, +}; + +static const short dep2[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2317, 2318, 2321, + 2322, 2325, 2326, +}; + +static const short dep3[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, 4127, 20605, +}; + +static const short dep4[] = { + 88, 252, 22637, 22638, 22640, 22641, 22643, 22644, 22646, 22794, 22797, 22798, + 22801, 22802, 22805, 22806, +}; + +static const short dep5[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep6[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2317, 2319, + 2321, 2323, 2325, +}; + +static const short dep7[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, + 2318, 2319, 2322, 2323, 2326, 4127, 20605, +}; + +static const short dep8[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2316, 2318, 2320, + 2322, 2324, 2326, +}; + +static const short dep9[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2316, + 2317, 2320, 2321, 2324, 2325, 4127, 20605, +}; + +static const short dep10[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2316, 2317, + 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, +}; + +static const short dep11[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, + 2316, 2317, 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, 4127, 20605, + +}; + +static const short dep12[] = { + 88, 252, 2364, +}; + +static const short dep13[] = { + 32, 33, 88, 148, 166, 167, 252, 2074, 2075, 2157, 2159, 2160, 2162, 2163, + 2165, 2166, 4127, +}; + +static const short dep14[] = { + 88, 147, 252, 295, 2364, 28844, 28987, +}; + +static const short dep15[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, + 23, 24, 25, 32, 33, 88, 136, 148, 166, 167, 252, 295, 2074, 2075, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, +}; + +static const short dep16[] = { + 1, 4, 32, 88, 126, 174, 177, 211, 252, 282, 2364, 28844, 28987, +}; + +static const short dep17[] = { + 1, 18, 20, 30, 32, 33, 88, 148, 150, 151, 166, 167, 174, 177, 211, 252, 282, + 2074, 2075, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, + +}; + +static const short dep18[] = { + 1, 32, 43, 88, 174, 211, 218, 252, 28844, 28987, +}; + +static const short dep19[] = { + 1, 30, 32, 33, 88, 145, 166, 174, 211, 218, 252, 4127, 28844, 28987, +}; + +static const short dep20[] = { + 32, 88, 211, 252, +}; + +static const short dep21[] = { + 88, 166, 211, 252, +}; + +static const short dep22[] = { + 1, 32, 88, 120, 121, 123, 124, 125, 126, 127, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 142, 143, 144, 145, 146, 147, 148, 151, 152, 153, + 154, 155, 156, 157, 158, 161, 162, 163, 164, 165, 166, 167, 168, 169, 174, + 211, 252, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, + 292, 293, 294, 295, 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, + 309, 310, 311, 312, 313, 28844, 28987, +}; + +static const short dep23[] = { + 1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 126, 166, 174, 211, 252, 279, 280, + 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, + 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, + 313, 4127, 28844, 28987, +}; + +static const short dep24[] = { + 88, 125, 252, 281, +}; + +static const short dep25[] = { + 88, 126, 166, 252, 281, +}; + +static const short dep26[] = { + 88, 126, 252, 282, +}; + +static const short dep27[] = { + 18, 19, 88, 89, 92, 96, 99, 126, 148, 166, 252, 282, +}; + +static const short dep28[] = { + 32, 33, 88, 166, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep29[] = { + 1, 18, 32, 88, 174, 199, 200, 211, 252, 2074, 2255, 2258, 2364, 28844, 28987, + +}; + +static const short dep30[] = { + 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2074, 2075, + 2157, 2159, 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, + +}; + +static const short dep31[] = { + 88, 252, +}; + +static const short dep32[] = { + 88, 166, 252, 2074, 2076, +}; + +static const short dep33[] = { + 32, 33, 88, 148, 166, 167, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, + 4127, +}; + +static const short dep34[] = { + 4, 29, 30, 31, 88, 116, 117, 177, 211, 252, 277, 278, 2364, +}; + +static const short dep35[] = { + 4, 29, 32, 33, 88, 148, 166, 167, 177, 211, 252, 277, 278, 316, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep36[] = { + 17, 88, 198, 252, 2364, +}; + +static const short dep37[] = { + 17, 32, 33, 88, 148, 166, 167, 198, 252, 2157, 2159, 2160, 2162, 2163, 2165, + 2166, 4127, +}; + +static const short dep38[] = { + 4, 17, 29, 30, 31, 88, 116, 117, 177, 198, 211, 252, 277, 278, 2364, +}; + +static const short dep39[] = { + 4, 17, 29, 32, 33, 88, 148, 166, 167, 177, 198, 211, 252, 277, 278, 316, 2157, + 2159, 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep40[] = { + 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, +}; + +static const short dep41[] = { + 88, 166, 252, +}; + +static const short dep42[] = { + 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep43[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep44[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, + 18585, 18586, 18731, 18732, 18734, 18735, 22637, 22638, 22639, 22641, 22642, + 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep45[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, + 18733, 18734, 18736, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep46[] = { + 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep47[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep48[] = { + 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep49[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep50[] = { + 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep51[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep52[] = { + 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep53[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep54[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, + 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep55[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, + 18733, 18734, 18736, +}; + +static const short dep56[] = { + 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep57[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep58[] = { + 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep59[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep60[] = { + 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep61[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep62[] = { + 88, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep63[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, + 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep64[] = { + 5, 88, 178, 252, +}; + +static const short dep65[] = { + 5, 32, 33, 88, 166, 178, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep66[] = { + 5, 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep67[] = { + 6, 88, 179, 252, +}; + +static const short dep68[] = { + 5, 32, 33, 88, 166, 179, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep69[] = { + 7, 88, 180, 252, +}; + +static const short dep70[] = { + 5, 32, 33, 88, 166, 180, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep71[] = { + 8, 88, 181, 252, +}; + +static const short dep72[] = { + 5, 32, 33, 88, 166, 181, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep73[] = { + 9, 88, 183, 184, 252, +}; + +static const short dep74[] = { + 32, 33, 88, 166, 183, 184, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep75[] = { + 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep76[] = { + 10, 88, 186, 187, 252, +}; + +static const short dep77[] = { + 32, 33, 88, 166, 186, 187, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep78[] = { + 11, 88, 189, 190, 252, +}; + +static const short dep79[] = { + 32, 33, 88, 166, 189, 190, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep80[] = { + 12, 88, 192, 193, 252, +}; + +static const short dep81[] = { + 32, 33, 88, 166, 192, 193, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep82[] = { + 9, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep83[] = { + 9, 10, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep84[] = { + 9, 11, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep85[] = { + 9, 12, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep86[] = { + 9, 88, 182, 183, 252, +}; + +static const short dep87[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep88[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, +}; + +static const short dep89[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep90[] = { + 10, 88, 185, 186, 252, +}; + +static const short dep91[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep92[] = { + 11, 88, 188, 189, 252, +}; + +static const short dep93[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep94[] = { + 12, 88, 191, 192, 252, +}; + +static const short dep95[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep96[] = { + 9, 88, 182, 183, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep97[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep98[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2157, 2158, + 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep99[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, 2318, 2321, 2322, + 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep100[] = { + 10, 88, 185, 186, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep101[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep102[] = { + 11, 88, 188, 189, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep103[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep104[] = { + 12, 88, 191, 192, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep105[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep106[] = { + 9, 88, 182, 183, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep107[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep108[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 22637, 22638, + 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, + 22806, +}; + +static const short dep109[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, 16518, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep110[] = { + 10, 88, 185, 186, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep111[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep112[] = { + 11, 88, 188, 189, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep113[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep114[] = { + 12, 88, 191, 192, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep115[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep116[] = { + 88, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, + 2322, 2325, 2326, +}; + +static const short dep117[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep118[] = { + 88, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, + 22801, 22802, 22805, 22806, +}; + +static const short dep119[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, + 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep120[] = { + 13, 14, 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, + 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep121[] = { + 32, 33, 88, 148, 166, 167, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 4127, 20605, +}; + +static const short dep122[] = { + 88, 252, 2075, 2076, 2256, 2257, +}; + +static const short dep123[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2255, 2257, + 4127, 20605, +}; + +static const short dep124[] = { + 32, 33, 88, 166, 252, 2074, 2076, 2157, 2158, 2161, 2164, 2297, 4127, 20605, + +}; + +static const short dep125[] = { + 88, 252, 14446, 14448, 14449, 14451, 14452, 14454, 14605, 14606, 14609, 14610, + 14613, 14614, +}; + +static const short dep126[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 4127, 14605, 14606, 14609, 14610, + 14613, 14614, 20605, 24685, 24686, 24689, 24692, +}; + +static const short dep127[] = { + 88, 113, 115, 116, 118, 252, 273, 274, 277, 278, +}; + +static const short dep128[] = { + 32, 33, 88, 166, 252, 273, 274, 277, 278, 4127, 24685, 24686, 24689, 24692, + +}; + +static const short dep129[] = { + 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep130[] = { + 32, 33, 88, 110, 113, 116, 166, 252, 2297, 4127, 20605, 24685, +}; + +static const short dep131[] = { + 4, 17, 19, 20, 88, 177, 198, 201, 252, 2073, 2254, +}; + +static const short dep132[] = { + 32, 33, 88, 166, 177, 198, 200, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2254, 4127, 20605, +}; + +static const short dep133[] = { + 4, 17, 18, 19, 32, 33, 88, 166, 252, 2073, 2157, 2158, 2161, 2164, 2297, 4127, + 20605, +}; + +static const short dep134[] = { + 0, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep135[] = { + 0, 88, 173, 252, +}; + +static const short dep136[] = { + 0, 32, 33, 88, 148, 166, 167, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep137[] = { + 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep138[] = { + 2, 21, 88, 175, 202, 252, 28844, 28987, +}; + +static const short dep139[] = { + 1, 2, 21, 22, 88, 160, 161, 166, 175, 202, 252, 28844, 28987, +}; + +static const short dep140[] = { + 1, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 252, 4127, 28844, 28987, + +}; + +static const short dep141[] = { + 0, 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep142[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 174, 175, + 176, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, 192, 193, 194, 195, + 196, 202, 203, 204, 252, 2064, 2073, 2245, 2254, 28844, 28987, +}; + +static const short dep143[] = { + 22, 32, 33, 88, 126, 166, 174, 175, 176, 178, 179, 180, 181, 183, 184, 186, + 187, 189, 190, 192, 193, 194, 195, 196, 202, 203, 204, 252, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 2245, 2254, 4127, 20605, 28844, 28987, +}; + +static const short dep144[] = { + 88, 252, 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, + 14637, 14639, 14640, 14649, +}; + +static const short dep145[] = { + 32, 33, 88, 165, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, 14636, + 14637, 14639, 14640, 14649, +}; + +static const short dep146[] = { + 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, 14637, + 14639, 14640, 14649, +}; + +static const short dep147[] = { + 165, 14615, 14616, 14636, 14637, 14639, 14640, 14649, +}; + +static const short dep148[] = { + 88, 252, 14456, 14457, 14459, 14460, 14468, 14469, 14470, 14471, 14472, 14473, + 14474, 14475, 14477, 14480, 14481, 14489, 14490, 14491, 14492, 14493, 14498, + 14499, 14500, 14501, 14505, 14615, 14616, 14622, 14623, 14624, 14625, 14627, + 14629, 14636, 14637, 14639, 14640, 14641, 14642, 14645, 14646, 14649, +}; + +static const short dep149[] = { + 32, 33, 64, 88, 126, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, + 14622, 14623, 14624, 14625, 14627, 14629, 14636, 14637, 14639, 14640, 14641, + 14642, 14645, 14646, 14649, +}; + +static const short dep150[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 126, + 163, 166, 252, 2064, 2073, 2157, 2158, 2161, 2164, 2297, 4127, 20605, 28844, + +}; + +static const short dep151[] = { + 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, + 56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 213, 214, 215, 216, 217, 218, 219, + 220, 221, 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, + 2108, 2280, +}; + +static const short dep152[] = { + 32, 33, 87, 88, 126, 145, 166, 213, 214, 215, 216, 217, 218, 219, 220, 221, + 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, 2129, 2130, + 2131, 2157, 2158, 2161, 2164, 2280, 4127, 20605, +}; + +static const short dep153[] = { + 51, 86, 88, 224, 251, 252, 2131, 2297, +}; + +static const short dep154[] = { + 32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58, + 59, 61, 62, 63, 85, 86, 88, 126, 145, 166, 224, 251, 252, 2099, 2108, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep155[] = { + 2, 21, 33, 88, 175, 202, 211, 252, 2131, 2297, 28844, 28987, +}; + +static const short dep156[] = { + 2, 18, 19, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 211, 252, 2297, + 4127, 20605, 28844, 28987, +}; + +static const short dep157[] = { + 88, 120, 121, 123, 124, 128, 129, 132, 133, 134, 135, 136, 137, 138, 139, + 141, 144, 145, 149, 150, 153, 154, 155, 156, 157, 159, 160, 162, 163, 164, + 165, 167, 168, 169, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, 297, + 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, +}; + +static const short dep158[] = { + 32, 33, 64, 88, 126, 166, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, + 297, 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep159[] = { + 88, 119, 121, 122, 124, 153, 154, 169, 252, 279, 280, 300, 301, 303, 304, + 313, +}; + +static const short dep160[] = { + 32, 33, 88, 165, 166, 252, 279, 280, 300, 301, 303, 304, 313, 2129, 2130, + 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep161[] = { + 32, 33, 88, 121, 124, 126, 129, 130, 133, 135, 137, 139, 141, 142, 144, 148, + 149, 151, 152, 153, 154, 156, 157, 159, 161, 162, 164, 166, 168, 169, 252, + 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep162[] = { + 32, 33, 88, 121, 124, 153, 154, 166, 169, 252, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep163[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 126, 155, 166, 170, 252, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep164[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 126, 127, 128, 130, 131, 155, 166, 170, 252, + 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep165[] = { + 68, 69, 88, 92, 93, 239, 240, 252, 254, 255, +}; + +static const short dep166[] = { + 32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, 252, + 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep167[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, + 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep168[] = { + 88, 252, 12458, 12459, 12602, +}; + +static const short dep169[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 12602, 20605, +}; + +static const short dep170[] = { + 88, 252, 6210, 6211, 6381, +}; + +static const short dep171[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6381, 20605, +}; + +static const short dep172[] = { + 88, 252, 6228, 6394, +}; + +static const short dep173[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6394, 20605, +}; + +static const short dep174[] = { + 88, 252, 6246, 6247, 6248, 6249, 6405, 6407, 8454, +}; + +static const short dep175[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6249, 6406, 6407, 8295, 8453, 20605, +}; + +static const short dep176[] = { + 88, 252, 6250, 6251, 6408, +}; + +static const short dep177[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6408, 20605, +}; + +static const short dep178[] = { + 88, 252, 6252, 6409, +}; + +static const short dep179[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6409, 20605, +}; + +static const short dep180[] = { + 88, 252, 10341, 10500, +}; + +static const short dep181[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 10500, 20605, +}; + +static const short dep182[] = { + 68, 69, 73, 74, 88, 92, 93, 239, 240, 242, 243, 252, 254, 255, +}; + +static const short dep183[] = { + 32, 33, 39, 54, 69, 71, 74, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, + 242, 244, 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep184[] = { + 68, 69, 88, 92, 93, 95, 96, 239, 240, 252, 254, 255, 256, 257, +}; + +static const short dep185[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, + 252, 254, 255, 256, 257, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep186[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 12459, 20605, +}; + +static const short dep187[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6210, 20605, +}; + +static const short dep188[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6228, 20605, +}; + +static const short dep189[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6248, 8294, 20605, +}; + +static const short dep190[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6250, 20605, +}; + +static const short dep191[] = { + 32, 33, 88, 126, 165, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 6251, 6252, 20605, +}; + +static const short dep192[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 10341, 20605, +}; + +static const short dep193[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, + 6178, 20605, +}; + +static const short dep194[] = { + 68, 70, 71, 88, 89, 90, 91, 238, 239, 252, 253, 254, +}; + +static const short dep195[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, + 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep196[] = { + 68, 70, 71, 72, 88, 89, 90, 91, 94, 238, 239, 241, 252, 253, 254, +}; + +static const short dep197[] = { + 32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 126, 166, 170, 238, 240, + 241, 252, 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep198[] = { + 68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 238, 239, 244, 245, 252, 253, 254, + +}; + +static const short dep199[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 126, 166, 170, 238, 240, 243, 245, 252, + 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep200[] = { + 68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 238, 239, 252, 253, 254, 257, 258, + +}; + +static const short dep201[] = { + 32, 33, 69, 70, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, 253, 255, + 256, 258, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep202[] = { + 32, 33, 38, 62, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep203[] = { + 32, 33, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep204[] = { + 32, 33, 68, 73, 75, 88, 126, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep205[] = { + 32, 33, 88, 148, 166, 167, 252, 2126, 2127, 2128, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 4127, 16516, 16518, 20605, +}; + +static const short dep206[] = { + 32, 33, 68, 73, 75, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 4127, 20605, +}; + +static const short dep207[] = { + 32, 33, 69, 70, 88, 91, 126, 166, 238, 240, 252, 253, 255, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep208[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep209[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep210[] = { + 0, 88, 173, 252, 2131, 2297, +}; + +static const short dep211[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep212[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep213[] = { + 23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep214[] = { + 0, 88, 173, 252, 2297, 26706, +}; + +static const short dep215[] = { + 0, 88, 100, 173, 252, 259, +}; + +static const short dep216[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 4127, 20605, +}; + +static const short dep217[] = { + 0, 23, 88, 100, 173, 204, 252, 259, +}; + +static const short dep218[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 4127, 20605, +}; + +static const short dep219[] = { + 0, 88, 100, 173, 252, 259, 2131, 2297, +}; + +static const short dep220[] = { + 0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep221[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep222[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2297, 4127, + 16516, 16518, 20605, +}; + +static const short dep223[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep224[] = { + 0, 23, 88, 100, 173, 204, 252, 259, 2131, 2297, +}; + +static const short dep225[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep226[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, + 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep227[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep228[] = { + 0, 88, 173, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep229[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep230[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, + +}; + +static const short dep231[] = { + 0, 88, 173, 252, 2128, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep232[] = { + 32, 33, 67, 88, 126, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep233[] = { + 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep234[] = { + 32, 33, 67, 88, 126, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep235[] = { + 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep236[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, 4127, + 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep237[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, + 88, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, + 192, 193, 194, 195, 196, 198, 201, 202, 203, 204, 252, 2064, 2073, 2131, 2245, + 2254, 2297, 28844, 28987, +}; + +static const short dep238[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, + 32, 33, 88, 126, 163, 166, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, + 186, 187, 189, 190, 192, 193, 194, 195, 196, 198, 200, 202, 203, 204, 252, + 2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2245, 2254, 2297, 4127, + 20605, 28844, 28987, +}; + +#define NELS(X) (sizeof(X)/sizeof(X[0])) +static const struct ia64_opcode_dependency +op_dependencies[] = { + { NELS(dep1), dep1, NELS(dep0), dep0, }, + { NELS(dep3), dep3, NELS(dep2), dep2, }, + { NELS(dep5), dep5, NELS(dep4), dep4, }, + { NELS(dep7), dep7, NELS(dep6), dep6, }, + { NELS(dep9), dep9, NELS(dep8), dep8, }, + { NELS(dep11), dep11, NELS(dep10), dep10, }, + { NELS(dep13), dep13, NELS(dep12), dep12, }, + { NELS(dep15), dep15, NELS(dep14), dep14, }, + { NELS(dep17), dep17, NELS(dep16), dep16, }, + { NELS(dep19), dep19, NELS(dep18), dep18, }, + { NELS(dep21), dep21, NELS(dep20), dep20, }, + { NELS(dep23), dep23, NELS(dep22), dep22, }, + { NELS(dep25), dep25, NELS(dep24), dep24, }, + { NELS(dep27), dep27, NELS(dep26), dep26, }, + { NELS(dep28), dep28, NELS(dep12), dep12, }, + { NELS(dep30), dep30, NELS(dep29), dep29, }, + { NELS(dep32), dep32, NELS(dep31), dep31, }, + { NELS(dep33), dep33, NELS(dep12), dep12, }, + { NELS(dep35), dep35, NELS(dep34), dep34, }, + { NELS(dep37), dep37, NELS(dep36), dep36, }, + { NELS(dep39), dep39, NELS(dep38), dep38, }, + { NELS(dep40), dep40, NELS(dep29), dep29, }, + { NELS(dep41), dep41, NELS(dep31), dep31, }, + { NELS(dep43), dep43, NELS(dep42), dep42, }, + { NELS(dep45), dep45, NELS(dep44), dep44, }, + { NELS(dep47), dep47, NELS(dep46), dep46, }, + { NELS(dep49), dep49, NELS(dep48), dep48, }, + { NELS(dep51), dep51, NELS(dep50), dep50, }, + { NELS(dep53), dep53, NELS(dep52), dep52, }, + { NELS(dep55), dep55, NELS(dep54), dep54, }, + { NELS(dep57), dep57, NELS(dep56), dep56, }, + { NELS(dep59), dep59, NELS(dep58), dep58, }, + { NELS(dep61), dep61, NELS(dep60), dep60, }, + { NELS(dep63), dep63, NELS(dep62), dep62, }, + { NELS(dep65), dep65, NELS(dep64), dep64, }, + { NELS(dep66), dep66, NELS(dep31), dep31, }, + { NELS(dep68), dep68, NELS(dep67), dep67, }, + { NELS(dep70), dep70, NELS(dep69), dep69, }, + { NELS(dep72), dep72, NELS(dep71), dep71, }, + { NELS(dep74), dep74, NELS(dep73), dep73, }, + { NELS(dep75), dep75, NELS(dep31), dep31, }, + { NELS(dep77), dep77, NELS(dep76), dep76, }, + { NELS(dep79), dep79, NELS(dep78), dep78, }, + { NELS(dep81), dep81, NELS(dep80), dep80, }, + { NELS(dep82), dep82, NELS(dep31), dep31, }, + { NELS(dep83), dep83, NELS(dep31), dep31, }, + { NELS(dep84), dep84, NELS(dep31), dep31, }, + { NELS(dep85), dep85, NELS(dep31), dep31, }, + { NELS(dep87), dep87, NELS(dep86), dep86, }, + { NELS(dep89), dep89, NELS(dep88), dep88, }, + { NELS(dep91), dep91, NELS(dep90), dep90, }, + { NELS(dep93), dep93, NELS(dep92), dep92, }, + { NELS(dep95), dep95, NELS(dep94), dep94, }, + { NELS(dep97), dep97, NELS(dep96), dep96, }, + { NELS(dep99), dep99, NELS(dep98), dep98, }, + { NELS(dep101), dep101, NELS(dep100), dep100, }, + { NELS(dep103), dep103, NELS(dep102), dep102, }, + { NELS(dep105), dep105, NELS(dep104), dep104, }, + { NELS(dep107), dep107, NELS(dep106), dep106, }, + { NELS(dep109), dep109, NELS(dep108), dep108, }, + { NELS(dep111), dep111, NELS(dep110), dep110, }, + { NELS(dep113), dep113, NELS(dep112), dep112, }, + { NELS(dep115), dep115, NELS(dep114), dep114, }, + { NELS(dep117), dep117, NELS(dep116), dep116, }, + { NELS(dep119), dep119, NELS(dep118), dep118, }, + { NELS(dep120), dep120, NELS(dep62), dep62, }, + { NELS(dep121), dep121, NELS(dep31), dep31, }, + { NELS(dep123), dep123, NELS(dep122), dep122, }, + { NELS(dep124), dep124, NELS(dep0), dep0, }, + { NELS(dep126), dep126, NELS(dep125), dep125, }, + { NELS(dep128), dep128, NELS(dep127), dep127, }, + { NELS(dep129), dep129, NELS(dep0), dep0, }, + { NELS(dep130), dep130, NELS(dep0), dep0, }, + { NELS(dep132), dep132, NELS(dep131), dep131, }, + { NELS(dep133), dep133, NELS(dep0), dep0, }, + { NELS(dep134), dep134, NELS(dep31), dep31, }, + { NELS(dep136), dep136, NELS(dep135), dep135, }, + { NELS(dep137), dep137, NELS(dep135), dep135, }, + { NELS(dep139), dep139, NELS(dep138), dep138, }, + { NELS(dep140), dep140, NELS(dep138), dep138, }, + { NELS(dep141), dep141, NELS(dep135), dep135, }, + { NELS(dep143), dep143, NELS(dep142), dep142, }, + { NELS(dep145), dep145, NELS(dep144), dep144, }, + { NELS(dep147), dep147, NELS(dep146), dep146, }, + { NELS(dep149), dep149, NELS(dep148), dep148, }, + { NELS(dep150), dep150, NELS(dep0), dep0, }, + { NELS(dep152), dep152, NELS(dep151), dep151, }, + { NELS(dep154), dep154, NELS(dep153), dep153, }, + { NELS(dep156), dep156, NELS(dep155), dep155, }, + { NELS(dep158), dep158, NELS(dep157), dep157, }, + { NELS(dep160), dep160, NELS(dep159), dep159, }, + { NELS(dep161), dep161, NELS(dep0), dep0, }, + { NELS(dep162), dep162, NELS(dep0), dep0, }, + { NELS(dep163), dep163, NELS(dep0), dep0, }, + { NELS(dep164), dep164, NELS(dep31), dep31, }, + { NELS(dep166), dep166, NELS(dep165), dep165, }, + { NELS(dep167), dep167, NELS(dep165), dep165, }, + { NELS(dep169), dep169, NELS(dep168), dep168, }, + { NELS(dep171), dep171, NELS(dep170), dep170, }, + { NELS(dep173), dep173, NELS(dep172), dep172, }, + { NELS(dep175), dep175, NELS(dep174), dep174, }, + { NELS(dep177), dep177, NELS(dep176), dep176, }, + { NELS(dep179), dep179, NELS(dep178), dep178, }, + { NELS(dep181), dep181, NELS(dep180), dep180, }, + { NELS(dep183), dep183, NELS(dep182), dep182, }, + { NELS(dep185), dep185, NELS(dep184), dep184, }, + { NELS(dep186), dep186, NELS(dep0), dep0, }, + { NELS(dep187), dep187, NELS(dep0), dep0, }, + { NELS(dep188), dep188, NELS(dep0), dep0, }, + { NELS(dep189), dep189, NELS(dep0), dep0, }, + { NELS(dep190), dep190, NELS(dep0), dep0, }, + { NELS(dep191), dep191, NELS(dep0), dep0, }, + { NELS(dep192), dep192, NELS(dep0), dep0, }, + { NELS(dep193), dep193, NELS(dep0), dep0, }, + { NELS(dep195), dep195, NELS(dep194), dep194, }, + { NELS(dep197), dep197, NELS(dep196), dep196, }, + { NELS(dep199), dep199, NELS(dep198), dep198, }, + { NELS(dep201), dep201, NELS(dep200), dep200, }, + { NELS(dep202), dep202, NELS(dep0), dep0, }, + { NELS(dep203), dep203, NELS(dep0), dep0, }, + { NELS(dep204), dep204, NELS(dep0), dep0, }, + { NELS(dep205), dep205, NELS(dep31), dep31, }, + { NELS(dep206), dep206, NELS(dep31), dep31, }, + { NELS(dep207), dep207, NELS(dep194), dep194, }, + { NELS(dep208), dep208, NELS(dep0), dep0, }, + { NELS(dep209), dep209, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep210), dep210, }, + { NELS(dep212), dep212, NELS(dep210), dep210, }, + { NELS(dep213), dep213, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep214), dep214, }, + { NELS(dep216), dep216, NELS(dep215), dep215, }, + { NELS(dep218), dep218, NELS(dep217), dep217, }, + { NELS(dep220), dep220, NELS(dep219), dep219, }, + { NELS(dep221), dep221, NELS(dep219), dep219, }, + { NELS(dep222), dep222, NELS(dep0), dep0, }, + { NELS(dep223), dep223, NELS(dep219), dep219, }, + { NELS(dep225), dep225, NELS(dep224), dep224, }, + { NELS(dep226), dep226, NELS(dep62), dep62, }, + { NELS(dep227), dep227, NELS(dep62), dep62, }, + { NELS(dep229), dep229, NELS(dep228), dep228, }, + { NELS(dep230), dep230, NELS(dep228), dep228, }, + { NELS(dep229), dep229, NELS(dep231), dep231, }, + { NELS(dep232), dep232, NELS(dep31), dep31, }, + { NELS(dep233), dep233, NELS(dep31), dep31, }, + { NELS(dep234), dep234, NELS(dep0), dep0, }, + { NELS(dep235), dep235, NELS(dep0), dep0, }, + { NELS(dep236), dep236, NELS(dep62), dep62, }, + { 0, NULL, 0, NULL, }, + { NELS(dep238), dep238, NELS(dep237), dep237, }, +}; + +static const struct ia64_completer_table +completer_table[] = { + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 88 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 449, -1, 0, 1, 6 }, + { 0x0, 0x0, 0, 512, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 611, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, 1815, -1, 0, 1, 10 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, + { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, 1991, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 122 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 44 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 78 }, + { 0x0, 0x0, 0, 1855, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2034, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1859, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, 1861, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2043, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2046, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2068, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2071, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 35 }, + { 0x0, 0x0, 0, 2079, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1170, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 77 }, + { 0x0, 0x0, 0, 1203, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1212, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1221, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1230, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1239, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1248, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1257, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1266, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1275, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1285, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1295, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1305, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1314, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1320, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1326, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1332, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1338, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1344, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1350, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1356, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1362, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1368, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1374, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1380, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1386, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1392, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1398, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1404, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1410, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1416, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 1420, -1, 0, 1, 142 }, + { 0x0, 0x0, 0, 1424, -1, 0, 1, 144 }, + { 0x0, 0x0, 0, 1428, -1, 0, 1, 144 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 79 }, + { 0x0, 0x0, 0, 250, -1, 0, 1, 40 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 67 }, + { 0x1, 0x1, 0, 975, -1, 20, 1, 67 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 86 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 87 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 89 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 90 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 91 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 92 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 97 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 98 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 99 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 100 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 101 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 102 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 103 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 106 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 107 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 108 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 109 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 110 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 111 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 112 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 113 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2371, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2372, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 1827, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 1828, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2386, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2387, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2388, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2389, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2390, -1, 0, 1, 0 }, + { 0x0, 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}, + { 0x0, 0x0, 232, 2325, 605, 0, 1, 21 }, + { 0x0, 0x0, 232, 2326, 869, 0, 0, -1 }, + { 0x0, 0x0, 232, 2327, 873, 0, 0, -1 }, + { 0x0, 0x0, 232, 2328, 628, 0, 1, 17 }, + { 0x0, 0x0, 232, 2329, 632, 0, 1, 17 }, + { 0x0, 0x0, 232, 2330, 877, 0, 0, -1 }, + { 0x0, 0x0, 232, 2331, 644, 0, 1, 21 }, + { 0x1, 0x1, 232, 770, 964, 27, 1, 16 }, + { 0x0, 0x0, 232, 771, 962, 0, 1, 16 }, + { 0x0, 0x0, 232, 1012, 966, 0, 1, 22 }, + { 0x0, 0x1, 232, 974, 972, 20, 1, 67 }, + { 0x0, 0x0, 232, 108, 970, 0, 1, 67 }, + { 0x1, 0x1, 235, -1, -1, 29, 1, 0 }, + { 0x0, 0x0, 235, -1, -1, 0, 1, 0 }, + { 0x1, 0x1, 235, 2472, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2473, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2474, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2475, -1, 27, 1, 0 }, + { 0x0, 0x0, 256, -1, 1929, 0, 0, -1 }, + { 0x0, 0x0, 256, -1, 1931, 0, 0, -1 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x0, 0x0, 256, -1, 1970, 0, 0, -1 }, + { 0x0, 0x0, 256, -1, 1972, 0, 0, -1 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x0, 0x0, 258, 22, -1, 0, 1, 0 }, + { 0x0, 0x0, 258, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 258, -1, -1, 0, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x0, 258, 176, -1, 0, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 64 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 64 }, + { 0x0, 0x0, 259, -1, 1905, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1907, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1909, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1911, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 259, -1, 1913, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1915, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x0, 0x0, 259, -1, 1917, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1919, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1921, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1923, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 259, -1, 1925, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1927, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, 329, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 387, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 333, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 391, -1, 12, 1, 2 }, + { 0x0, 0x0, 260, -1, 1912, 0, 0, -1 }, + { 0x9, 0x9, 260, -1, 2442, 33, 1, 49 }, + { 0x0, 0x0, 260, 1162, 1961, 0, 0, -1 }, + { 0x3, 0x3, 260, 1163, -1, 27, 1, 49 }, + { 0x0, 0x0, 264, 2369, -1, 0, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 266, 2468, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2469, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2470, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2471, -1, 28, 1, 0 }, + { 0x1, 0x1, 267, -1, -1, 27, 1, 93 }, + { 0x1, 0x1, 267, -1, -1, 27, 1, 93 }, + { 0x0, 0x0, 267, -1, 813, 0, 0, -1 }, + { 0x0, 0x0, 268, 2481, 2346, 0, 0, -1 }, + { 0x0, 0x0, 268, 2482, 2348, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 2347, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 2349, 0, 0, -1 }, + { 0x0, 0x0, 270, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 270, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 275, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 279, -1, 1935, 0, 1, 29 }, + { 0x0, 0x0, 280, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 280, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 280, 1723, 2459, 0, 1, 1 }, + { 0x0, 0x0, 280, -1, 388, 0, 0, -1 }, + { 0x0, 0x0, 280, 1725, 2461, 0, 1, 1 }, + { 0x0, 0x0, 280, -1, 392, 0, 0, -1 }, +}; + +static const struct ia64_main_table +main_table[] = { + { 5, 1, 1, 0x00000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x08000000ull, 0xf8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, }, + { 5, 7, 1, 0x00000000ull, 0x00000000ull, { 23, 65, 26, 0, 0 }, 0x0, 2, }, + { 5, 7, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 3, }, + { 6, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 65, 26, 0, 0 }, 0x0, 4, }, + { 7, 1, 1, 0x40000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 5, }, + { 7, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, }, + { 8, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 7, }, + { 9, 3, 1, 0x00000000ull, 0x00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 8, }, + { 10, 1, 1, 0x60000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 9, }, + { 10, 1, 1, 0x60000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 10, }, + { 11, 1, 1, 0x68000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 11, }, + { 11, 1, 1, 0x68000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 12, }, + { 14, 4, 0, 0x00000000ull, 0xf80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 814, }, + { 14, 4, 0, 0x00000000ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 680, }, + { 14, 4, 0, 0x00000000ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 681, }, + { 14, 4, 0, 0x08000100ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1843, }, + { 14, 4, 0, 0x08000100ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1844, }, + { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, }, + { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, }, + { 14, 4, 0, 0x00000000ull, 0x000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 835, }, + { 14, 4, 0, 0x00000000ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 682, }, + { 14, 4, 0, 0x00000000ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 683, }, + { 14, 4, 0, 0x00000080ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2479, }, + { 14, 4, 0, 0x00000080ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2480, }, + { 14, 4, 0, 0x00000140ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 445, }, + { 14, 4, 0, 0x00000140ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 446, }, + { 14, 4, 0, 0x00000180ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 443, }, + { 14, 4, 0, 0x00000180ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 444, }, + { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 439, }, + { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 440, }, + { 15, 4, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 393, }, + { 15, 5, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 806, }, + { 15, 2, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 949, }, + { 15, 3, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 1038, }, + { 15, 6, 0, 0x00000000ull, 0xf8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 2483, }, + { 15, 7, 0, 0x00000000ull, 0x00000000ull, { 64, 0, 0, 0, 0 }, 0x0, 15, }, + { 16, 6, 0, 0x00000000ull, 0x000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 868, }, + { 16, 6, 0, 0x00000000ull, 0x000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 684, }, + { 16, 6, 0, 0x00000000ull, 0x000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 685, }, + { 16, 6, 1, 0x00000000ull, 0x00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 441, }, + { 16, 6, 1, 0x00000000ull, 0x00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 442, }, + { 17, 4, 0, 0x80000000ull, 0xf8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 2365, }, + { 17, 4, 0, 0x00000000ull, 0x00000018ull, { 80, 76, 0, 0, 0 }, 0x20, 2366, }, + { 18, 4, 0, 0x60000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 216, }, + { 22, 2, 0, 0x00000000ull, 0x00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1848, }, + { 22, 3, 0, 0x00000000ull, 0x00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 218, }, + { 22, 3, 0, 0x00000000ull, 0x00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 219, }, + { 22, 3, 0, 0x00000000ull, 0x00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1849, }, + { 22, 3, 0, 0x00000000ull, 0x00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 1850, }, + { 22, 7, 0, 0x00000000ull, 0x00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1851, }, + { 25, 4, 0, 0x20000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 17, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 1014, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 990, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 918, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 897, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 1146, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 919, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 25, 6, 0 }, 0x40, 1016, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 993, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 1018, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 994, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 922, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 901, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 1149, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 58, 25, 0 }, 0x0, 1009, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 58, 25, 0 }, 0x0, 939, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 1150, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 995, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 25, 6, 0 }, 0x40, 903, }, + { 26, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 1151, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 1021, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 997, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 925, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 904, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 1154, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 926, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 25, 6, 0 }, 0x40, 1023, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 1000, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 1025, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 1001, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 929, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 908, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 1157, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 55, 25, 0 }, 0x0, 1035, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 57, 25, 0 }, 0x0, 1011, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 57, 25, 0 }, 0x0, 941, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 55, 25, 0 }, 0x0, 917, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 1158, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 1002, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 25, 6, 0 }, 0x40, 910, }, + { 27, 1, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 1159, }, + { 28, 3, 1, 0x08000000ull, 0xf8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 251, }, + { 29, 3, 1, 0x48000000ull, 0xf8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 252, }, + { 30, 3, 1, 0x88000000ull, 0xf8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 253, }, + { 31, 3, 1, 0xc8000000ull, 0xf8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 254, }, + { 33, 4, 0, 0x10000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 18, }, + { 35, 2, 1, 0xc0000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 976, }, + { 36, 2, 1, 0xc8000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 977, }, + { 38, 2, 1, 0x00000000ull, 0x00000000ull, { 23, 24, 25, 46, 71 }, 0x0, 19, }, + { 38, 2, 1, 0x00000000ull, 0x04000000ull, { 23, 24, 44, 72, 0 }, 0x0, 2487, }, + { 38, 2, 1, 0x04000000ull, 0x04000000ull, { 23, 54, 44, 72, 0 }, 0x0, 2488, }, + { 38, 2, 1, 0x00000000ull, 0x00000000ull, { 23, 47, 25, 45, 72 }, 0x0, 20, }, + { 42, 4, 0, 0x80000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x20, 21, }, + { 47, 2, 1, 0x00000000ull, 0x00002000ull, { 23, 25, 75, 72, 0 }, 0x0, 2383, }, + { 49, 5, 1, 0x80000000ull, 0xf80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 23, }, + { 50, 5, 1, 0x08000000ull, 0xf8000000ull, { 17, 19, 18, 0, 0 }, 0x40, 1900, }, + { 51, 5, 1, 0xb8000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 1901, }, + { 51, 5, 1, 0xb8000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 25, }, + { 52, 5, 1, 0xb0000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 1902, }, + { 52, 5, 1, 0xb0000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 26, }, + { 53, 5, 1, 0x60000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 27, }, + { 54, 5, 1, 0x68000000ull, 0xf8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 28, }, + { 56, 3, 0, 0x80000000ull, 0xf8000000ull, { 25, 0, 0, 0, 0 }, 0x0, 29, }, + { 57, 5, 0, 0x40000000ull, 0xf8000000ull, { 78, 0, 0, 0, 0 }, 0x0, 1903, }, + { 57, 5, 0, 0x40000000ull, 0xf8000000ull, { 78, 0, 0, 0, 0 }, 0x40, 30, }, + { 58, 5, 2, 0x00000000ull, 0x00001000ull, { 21, 22, 18, 59, 0 }, 0x0, 1040, }, + { 58, 5, 2, 0x00000000ull, 0x00001000ull, { 22, 21, 18, 59, 0 }, 0x40, 1179, }, + { 59, 5, 0, 0x28000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 1904, }, + { 59, 5, 0, 0x28000000ull, 0xf8000000ull, { 0, 0, 0, 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24, 25, 0, 0 }, 0x0, 2384, }, + { 188, 2, 1, 0x70000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 151, }, + { 189, 2, 1, 0x10000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 2385, }, + { 190, 2, 1, 0x30000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 152, }, + { 191, 2, 1, 0xd0000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 1823, }, + { 192, 2, 1, 0x30000000ull, 0x30000000ull, { 23, 24, 25, 41, 0 }, 0x0, 153, }, + { 193, 2, 1, 0x90000000ull, 0xf0000000ull, { 23, 25, 0, 0, 0 }, 0x0, 154, }, + { 195, 3, 1, 0xc0000000ull, 0xf8000000ull, { 23, 25, 24, 0, 0 }, 0x0, 1824, }, + { 195, 3, 1, 0xc0000000ull, 0xf8000000ull, { 23, 25, 48, 0, 0 }, 0x0, 1825, }, + { 195, 3, 0, 0x88000000ull, 0xf8000000ull, { 25, 48, 0, 0, 0 }, 0x0, 1847, }, + { 196, 2, 1, 0xb0000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 155, }, + { 197, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 156, }, + { 197, 2, 1, 0x50000000ull, 0xf0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 157, }, + { 198, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 158, }, + { 198, 2, 1, 0x50000000ull, 0xf0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 159, }, + { 199, 1, 1, 0x80000000ull, 0xe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 160, }, + { 200, 2, 1, 0x20000000ull, 0xf0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 161, }, + { 200, 2, 1, 0x30000000ull, 0xf0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 162, }, + { 201, 2, 1, 0x20000000ull, 0xf0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 163, }, + { 201, 2, 1, 0x30000000ull, 0xf0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 164, }, + { 202, 1, 1, 0xc0000000ull, 0xe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 165, }, + { 203, 1, 1, 0x20000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 166, }, + { 204, 1, 1, 0x20000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 167, }, + { 205, 1, 1, 0x20000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 168, }, + { 206, 3, 0, 0x48000000ull, 0xf8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 984, }, + { 206, 3, 0, 0x50000000ull, 0xf8000000ull, { 25, 24, 0, 0, 0 }, 0xc, 895, }, + { 206, 3, 0, 0xa0000000ull, 0xf8000000ull, { 25, 0, 0, 0, 0 }, 0x8, 777, }, + { 207, 3, 0, 0x60000000ull, 0xf8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 703, }, + { 212, 4, 0, 0x40000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 169, }, + { 213, 3, 0, 0x38000000ull, 0x78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 170, }, + { 214, 3, 0, 0x28000000ull, 0x78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 171, }, + { 223, 3, 1, 0x08000000ull, 0xc8000000ull, { 17, 24, 0, 0, 0 }, 0x0, 2295, }, + { 224, 2, 1, 0x00000000ull, 0x04000000ull, { 23, 24, 44, 0, 0 }, 0x140, 172, }, + { 224, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 173, }, + { 225, 1, 1, 0x80000000ull, 0xe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 174, }, + { 226, 1, 1, 0xc0000000ull, 0xe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 175, }, + { 227, 2, 1, 0x00000000ull, 0x00002000ull, { 23, 25, 75, 0, 0 }, 0x140, 2391, }, + { 227, 2, 1, 0x20000000ull, 0xf0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 177, }, + { 228, 2, 1, 0x00000000ull, 0x00000000ull, { 23, 24, 25, 43, 0 }, 0x0, 178, }, + { 233, 3, 0, 0x80000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 705, }, + { 234, 3, 0, 0x30000000ull, 0x78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 179, }, + { 236, 3, 1, 0x00000000ull, 0xf8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 180, }, + { 236, 3, 1, 0x00000000ull, 0xf0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 181, }, + { 237, 3, 1, 0x40000000ull, 0xf8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 182, }, + { 237, 3, 1, 0x40000000ull, 0xf0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 183, }, + { 238, 3, 1, 0x80000000ull, 0xf8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 184, }, + { 238, 3, 1, 0x80000000ull, 0xf0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 185, }, + { 239, 3, 1, 0xc0000000ull, 0xf8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 186, }, + { 239, 3, 1, 0xc0000000ull, 0xf0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 187, }, + { 240, 3, 1, 0xc0000000ull, 0xf8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 2298, }, + { 240, 3, 1, 0xc0000000ull, 0xf0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 2299, }, + { 241, 3, 1, 0x40000000ull, 0xf8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 188, }, + { 241, 3, 1, 0x40000000ull, 0xf0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 189, }, + { 242, 3, 1, 0xc0000000ull, 0xf8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 190, }, + { 242, 3, 1, 0xc0000000ull, 0xf0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 191, }, + { 243, 3, 1, 0x00000000ull, 0xf8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 192, }, + { 243, 3, 1, 0x00000000ull, 0xf0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 193, }, + { 244, 3, 1, 0x80000000ull, 0xf8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 194, }, + { 244, 3, 1, 0x80000000ull, 0xf0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 195, }, + { 245, 1, 1, 0x28000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 196, }, + { 245, 1, 1, 0x20000000ull, 0xf8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 197, }, + { 245, 1, 1, 0x28000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 198, }, + { 246, 3, 0, 0x20000000ull, 0x78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 199, }, + { 247, 2, 1, 0xa0000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 200, }, + { 248, 2, 1, 0xa8000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 201, }, + { 249, 2, 1, 0xb0000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 202, }, + { 250, 3, 0, 0x98000000ull, 0xf8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 959, }, + { 251, 3, 1, 0xf8000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 203, }, + { 252, 2, 2, 0x00000000ull, 0x00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 2489, }, + { 252, 2, 2, 0x00000000ull, 0x00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 1724, }, + { 253, 3, 1, 0xd0000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 204, }, + { 254, 2, 2, 0x00002000ull, 0x00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 2491, }, + { 254, 2, 2, 0x00002000ull, 0x00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 1726, }, + { 255, 3, 1, 0xf0000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 205, }, + { 257, 3, 1, 0xd8000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 206, }, + { 261, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 942, }, + { 262, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 943, }, + { 263, 2, 1, 0x40000000ull, 0xf0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 944, }, + { 271, 3, 1, 0x08000000ull, 0xf8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 207, }, + { 272, 3, 1, 0x48000000ull, 0xf8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 208, }, + { 273, 3, 1, 0x88000000ull, 0xf8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 209, }, + { 274, 3, 1, 0xc8000000ull, 0xf8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 210, }, + { 276, 5, 1, 0x00000000ull, 0x00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 988, }, + { 276, 5, 1, 0x00000000ull, 0x00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 1036, }, + { 277, 5, 1, 0x00000000ull, 0x000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 989, }, + { 278, 1, 1, 0x78000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 211, }, + { 278, 1, 1, 0x78000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 212, }, + { 281, 2, 1, 0x80000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 213, }, + { 282, 2, 1, 0x88000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 214, }, + { 283, 2, 1, 0x90000000ull, 0xf8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 215, }, +}; + +static const char dis_table[] = { +0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70, +0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x31, 0x48, 0x24, +0x31, 0x40, 0x90, 0x28, 0x24, 0x31, 0x38, 0x24, 0x31, 0x30, 0x90, 0x50, +0x90, 0x28, 0x24, 0x31, 0x20, 0x24, 0x31, 0x18, 0x90, 0x28, 0x24, 0x31, +0x10, 0x24, 0x31, 0x08, 0xa8, 0x0b, 0x28, 0x15, 0x00, 0x97, 0x00, 0x95, +0xa8, 0x9a, 0x98, 0x05, 0x18, 0x90, 0xf8, 0x90, 0x80, 0x90, 0x40, 0x80, +0xa4, 0x21, 0x18, 0x34, 0x26, 0x80, 0xa4, 0x2e, 0xc0, 0x35, 0xdd, 0x90, +0x50, 0x90, 0x28, 0x80, 0x35, 0xd3, 0x80, 0x34, 0x0a, 0x81, 0x33, 0xa6, +0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x20, 0x30, 0x34, 0x07, 0xa4, +0x1d, 0x28, 0x34, 0x04, 0x90, 0x38, 0xa4, 0x30, 0xc0, 0x36, 0x1e, 0xa4, +0x30, 0x68, 0x36, 0x12, 0x90, 0x70, 0x90, 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0x50, 0x00, 0x80, 0xe5, 0x22, 0x16, 0x00, 0x38, 0x54, +0xe5, 0x22, 0x17, 0x00, 0x38, 0x66, 0xcb, 0x61, 0x0f, 0xc0, 0x85, 0x34, +0x4e, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0e, 0x00, 0x38, 0x34, 0xe5, +0x22, 0x0f, 0x00, 0x38, 0x46, 0xcb, 0x61, 0x0f, 0x80, 0x85, 0x34, 0x4d, +0x90, 0x48, 0xcb, 0xa1, 0x0f, 0x40, 0x85, 0x34, 0x4c, 0xcb, 0xa1, 0x0f, +0x00, 0x85, 0x34, 0x4b, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, +0xe5, 0x22, 0x07, 0x00, 0x38, 0x28, 0xe5, 0x22, 0x01, 0x00, 0x38, 0x10, +0xcb, 0x61, 0x0d, 0x40, 0x85, 0x34, 0x3a, 0x98, 0x50, 0x00, 0x80, 0xe5, +0x21, 0xfb, 0x00, 0x37, 0xf8, 0xe5, 0x21, 0xf5, 0x00, 0x37, 0xe0, 0xcb, +0x61, 0x0d, 0x00, 0x85, 0x34, 0x39, 0x90, 0x48, 0xcb, 0xa1, 0x0c, 0xc0, +0x85, 0x34, 0x38, 0xcb, 0xa1, 0x0c, 0x80, 0x85, 0x34, 0x37, 0x91, 0x00, +0x90, 0x80, 0x90, 0x40, 0xe5, 0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, +0x01, 0x80, 0x30, 0x07, 0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, +0xe5, 0x20, 0x00, 0x00, 0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, +0xed, 0x00, 0x37, 0xae, 0xe5, 0x21, 0xee, 0x40, 0x37, 0xc4, 0x90, 0x40, +0xe5, 0x21, 0xe3, 0x80, 0x37, 0x88, 0xe5, 0x21, 0xe4, 0xc0, 0x37, 0x9e, +0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x21, 0x48, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x22, 0x19, 0x00, 0x38, 0x62, 0xe5, 0x22, 0x17, 0x80, 0x38, 0x68, +0x90, 0x40, 0xe5, 0x22, 0x11, 0x00, 0x38, 0x42, 0xe5, 0x22, 0x0f, 0x80, +0x38, 0x48, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, +0x08, 0x00, 0x38, 0x2c, 0xe5, 0x22, 0x02, 0x00, 0x38, 0x14, 0xcb, 0x61, +0x0b, 0x00, 0x85, 0x34, 0x30, 0x90, 0x40, 0xe5, 0x21, 0xfc, 0x00, 0x37, +0xfc, 0xe5, 0x21, 0xf6, 0x00, 0x37, 0xe4, 0x90, 0x48, 0xcb, 0xa1, 0x0a, +0x80, 0x85, 0x34, 0x2e, 0xcb, 0xa1, 0x0a, 0xc0, 0x85, 0x34, 0x2f, 0x10, +0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xf0, 0x80, 0x37, 0xc0, 0xe5, +0x21, 0xef, 0x00, 0x37, 0xc8, 0x90, 0x40, 0xe5, 0x21, 0xe7, 0x00, 0x37, +0x9a, 0xe5, 0x21, 0xe5, 0x80, 0x37, 0xa2, +}; + +static const struct ia64_dis_names ia64_dis_names[] = { +{ 0x51, 40, 0, 9 }, +{ 0x31, 40, 1, 19 }, +{ 0x11, 41, 0, 18 }, +{ 0x29, 40, 0, 11 }, +{ 0x19, 40, 1, 23 }, +{ 0x9, 41, 0, 22 }, +{ 0x15, 40, 0, 13 }, +{ 0xd, 40, 1, 27 }, +{ 0x5, 41, 0, 26 }, +{ 0xb, 40, 0, 15 }, +{ 0x7, 40, 1, 31 }, +{ 0x3, 41, 0, 30 }, +{ 0x51, 38, 1, 57 }, +{ 0x50, 38, 0, 33 }, +{ 0xd1, 38, 1, 56 }, +{ 0xd0, 38, 0, 32 }, +{ 0x31, 38, 1, 67 }, +{ 0x30, 38, 1, 43 }, +{ 0x11, 39, 1, 66 }, +{ 0x10, 39, 0, 42 }, +{ 0x71, 38, 1, 65 }, +{ 0x70, 38, 1, 41 }, +{ 0x31, 39, 1, 64 }, +{ 0x30, 39, 0, 40 }, +{ 0x29, 38, 1, 59 }, +{ 0x28, 38, 0, 35 }, +{ 0x69, 38, 1, 58 }, +{ 0x68, 38, 0, 34 }, +{ 0x19, 38, 1, 71 }, +{ 0x18, 38, 1, 47 }, +{ 0x9, 39, 1, 70 }, +{ 0x8, 39, 0, 46 }, +{ 0x39, 38, 1, 69 }, +{ 0x38, 38, 1, 45 }, +{ 0x19, 39, 1, 68 }, +{ 0x18, 39, 0, 44 }, +{ 0x15, 38, 1, 61 }, +{ 0x14, 38, 0, 37 }, +{ 0x35, 38, 1, 60 }, +{ 0x34, 38, 0, 36 }, +{ 0xd, 38, 1, 75 }, +{ 0xc, 38, 1, 51 }, +{ 0x5, 39, 1, 74 }, +{ 0x4, 39, 0, 50 }, +{ 0x1d, 38, 1, 73 }, +{ 0x1c, 38, 1, 49 }, +{ 0xd, 39, 1, 72 }, +{ 0xc, 39, 0, 48 }, +{ 0xb, 38, 1, 63 }, +{ 0xa, 38, 0, 39 }, +{ 0x1b, 38, 1, 62 }, +{ 0x1a, 38, 0, 38 }, +{ 0x7, 38, 1, 79 }, +{ 0x6, 38, 1, 55 }, +{ 0x3, 39, 1, 78 }, +{ 0x2, 39, 0, 54 }, +{ 0xf, 38, 1, 77 }, +{ 0xe, 38, 1, 53 }, +{ 0x7, 39, 1, 76 }, +{ 0x6, 39, 0, 52 }, +{ 0x8, 37, 0, 81 }, +{ 0x18, 37, 0, 80 }, +{ 0x1, 37, 1, 85 }, +{ 0x2, 37, 0, 84 }, +{ 0x3, 37, 1, 83 }, +{ 0x4, 37, 0, 82 }, +{ 0x1, 284, 0, 86 }, +{ 0x20, 237, 0, 96 }, +{ 0x220, 237, 0, 92 }, +{ 0x1220, 237, 0, 89 }, +{ 0xa20, 237, 0, 90 }, +{ 0x620, 237, 0, 91 }, +{ 0x120, 237, 0, 93 }, +{ 0xa0, 237, 0, 94 }, +{ 0x60, 237, 0, 95 }, +{ 0x10, 237, 0, 100 }, +{ 0x90, 237, 0, 97 }, +{ 0x50, 237, 0, 98 }, +{ 0x30, 237, 0, 99 }, +{ 0x8, 237, 0, 101 }, +{ 0x4, 237, 0, 102 }, +{ 0x2, 237, 0, 103 }, +{ 0x1, 237, 0, 104 }, +{ 0x1, 357, 0, 106 }, +{ 0x3, 357, 0, 105 }, +{ 0x2, 363, 0, 107 }, +{ 0x1, 363, 0, 108 }, +{ 0x2, 359, 0, 109 }, +{ 0x1, 359, 0, 110 }, +{ 0x2, 361, 0, 111 }, +{ 0x1, 361, 0, 112 }, +{ 0x2, 365, 0, 113 }, +{ 0x1, 365, 0, 114 }, +{ 0x1, 216, 0, 141 }, +{ 0x5, 216, 0, 139 }, +{ 0x3, 216, 0, 140 }, +{ 0x140, 225, 0, 117 }, +{ 0x540, 225, 0, 115 }, +{ 0x340, 225, 0, 116 }, +{ 0xc0, 225, 0, 129 }, +{ 0x2c0, 225, 0, 127 }, +{ 0x1c0, 225, 0, 128 }, +{ 0x20, 225, 0, 144 }, +{ 0xa0, 225, 0, 142 }, +{ 0x60, 225, 0, 143 }, +{ 0x10, 225, 0, 156 }, +{ 0x50, 225, 0, 154 }, +{ 0x30, 225, 0, 155 }, +{ 0x8, 225, 0, 168 }, +{ 0x28, 225, 0, 166 }, +{ 0x18, 225, 0, 167 }, +{ 0x4, 225, 0, 178 }, +{ 0x2, 225, 0, 179 }, +{ 0x1, 225, 0, 180 }, +{ 0x140, 219, 0, 120 }, +{ 0x540, 219, 0, 118 }, +{ 0x340, 219, 0, 119 }, +{ 0xc0, 219, 0, 132 }, +{ 0x2c0, 219, 0, 130 }, +{ 0x1c0, 219, 0, 131 }, +{ 0x20, 219, 0, 147 }, +{ 0xa0, 219, 0, 145 }, +{ 0x60, 219, 0, 146 }, +{ 0x10, 219, 0, 159 }, +{ 0x50, 219, 0, 157 }, +{ 0x30, 219, 0, 158 }, +{ 0x8, 219, 0, 171 }, +{ 0x28, 219, 0, 169 }, +{ 0x18, 219, 0, 170 }, +{ 0x4, 219, 0, 181 }, +{ 0x2, 219, 0, 182 }, +{ 0x1, 219, 0, 183 }, +{ 0x140, 222, 0, 123 }, +{ 0x540, 222, 0, 121 }, +{ 0x340, 222, 0, 122 }, +{ 0xc0, 222, 0, 135 }, +{ 0x2c0, 222, 0, 133 }, +{ 0x1c0, 222, 0, 134 }, +{ 0x20, 222, 0, 150 }, +{ 0xa0, 222, 0, 148 }, +{ 0x60, 222, 0, 149 }, +{ 0x10, 222, 0, 162 }, +{ 0x50, 222, 0, 160 }, +{ 0x30, 222, 0, 161 }, +{ 0x8, 222, 0, 174 }, +{ 0x28, 222, 0, 172 }, +{ 0x18, 222, 0, 173 }, +{ 0x4, 222, 0, 184 }, +{ 0x2, 222, 0, 185 }, +{ 0x1, 222, 0, 186 }, +{ 0x140, 234, 0, 126 }, +{ 0x540, 234, 0, 124 }, +{ 0x340, 234, 0, 125 }, +{ 0xc0, 234, 0, 138 }, +{ 0x2c0, 234, 0, 136 }, +{ 0x1c0, 234, 0, 137 }, +{ 0x20, 234, 0, 153 }, +{ 0xa0, 234, 0, 151 }, +{ 0x60, 234, 0, 152 }, +{ 0x10, 234, 0, 165 }, +{ 0x50, 234, 0, 163 }, +{ 0x30, 234, 0, 164 }, +{ 0x8, 234, 0, 177 }, +{ 0x28, 234, 0, 175 }, +{ 0x18, 234, 0, 176 }, +{ 0x4, 234, 0, 187 }, +{ 0x2, 234, 0, 188 }, +{ 0x1, 234, 0, 189 }, +{ 0x8, 338, 0, 190 }, +{ 0x4, 338, 0, 191 }, +{ 0x2, 338, 0, 192 }, +{ 0x1, 338, 0, 193 }, +{ 0x20, 236, 0, 201 }, +{ 0x220, 236, 0, 197 }, +{ 0x1220, 236, 0, 194 }, +{ 0xa20, 236, 0, 195 }, +{ 0x620, 236, 0, 196 }, +{ 0x120, 236, 0, 198 }, +{ 0xa0, 236, 0, 199 }, +{ 0x60, 236, 0, 200 }, +{ 0x10, 236, 0, 205 }, +{ 0x90, 236, 0, 202 }, +{ 0x50, 236, 0, 203 }, +{ 0x30, 236, 0, 204 }, +{ 0x8, 236, 0, 206 }, +{ 0x4, 236, 0, 207 }, +{ 0x2, 236, 0, 208 }, +{ 0x1, 236, 0, 209 }, +{ 0x20, 235, 0, 217 }, +{ 0x220, 235, 0, 213 }, +{ 0x1220, 235, 0, 210 }, +{ 0xa20, 235, 0, 211 }, +{ 0x620, 235, 0, 212 }, +{ 0x120, 235, 0, 214 }, +{ 0xa0, 235, 0, 215 }, +{ 0x60, 235, 0, 216 }, +{ 0x10, 235, 0, 221 }, +{ 0x90, 235, 0, 218 }, +{ 0x50, 235, 0, 219 }, +{ 0x30, 235, 0, 220 }, +{ 0x8, 235, 0, 222 }, +{ 0x4, 235, 0, 223 }, +{ 0x2, 235, 0, 224 }, +{ 0x1, 235, 0, 225 }, +{ 0x140, 227, 0, 228 }, +{ 0x540, 227, 0, 226 }, +{ 0x340, 227, 0, 227 }, +{ 0xc0, 227, 0, 237 }, +{ 0x2c0, 227, 0, 235 }, +{ 0x1c0, 227, 0, 236 }, +{ 0x20, 227, 0, 246 }, +{ 0xa0, 227, 0, 244 }, +{ 0x60, 227, 0, 245 }, +{ 0x10, 227, 0, 255 }, +{ 0x50, 227, 0, 253 }, +{ 0x30, 227, 0, 254 }, +{ 0x8, 227, 0, 264 }, +{ 0x28, 227, 0, 262 }, +{ 0x18, 227, 0, 263 }, +{ 0x4, 227, 0, 271 }, +{ 0x2, 227, 0, 272 }, +{ 0x1, 227, 0, 273 }, +{ 0x140, 229, 0, 231 }, +{ 0x540, 229, 0, 229 }, +{ 0x340, 229, 0, 230 }, +{ 0xc0, 229, 0, 240 }, +{ 0x2c0, 229, 0, 238 }, +{ 0x1c0, 229, 0, 239 }, +{ 0x20, 229, 0, 249 }, +{ 0xa0, 229, 0, 247 }, +{ 0x60, 229, 0, 248 }, +{ 0x10, 229, 0, 258 }, +{ 0x50, 229, 0, 256 }, +{ 0x30, 229, 0, 257 }, +{ 0x8, 229, 0, 267 }, +{ 0x28, 229, 0, 265 }, +{ 0x18, 229, 0, 266 }, +{ 0x4, 229, 0, 274 }, +{ 0x2, 229, 0, 275 }, +{ 0x1, 229, 0, 276 }, +{ 0x140, 231, 0, 234 }, +{ 0x540, 231, 0, 232 }, +{ 0x340, 231, 0, 233 }, +{ 0xc0, 231, 0, 243 }, +{ 0x2c0, 231, 0, 241 }, +{ 0x1c0, 231, 0, 242 }, +{ 0x20, 231, 0, 252 }, +{ 0xa0, 231, 0, 250 }, +{ 0x60, 231, 0, 251 }, +{ 0x10, 231, 0, 261 }, +{ 0x50, 231, 0, 259 }, +{ 0x30, 231, 0, 260 }, +{ 0x8, 231, 0, 270 }, +{ 0x28, 231, 0, 268 }, +{ 0x18, 231, 0, 269 }, +{ 0x4, 231, 0, 277 }, +{ 0x2, 231, 0, 278 }, +{ 0x1, 231, 0, 279 }, +{ 0x140, 226, 0, 282 }, +{ 0x540, 226, 0, 280 }, +{ 0x340, 226, 0, 281 }, +{ 0xc0, 226, 0, 291 }, +{ 0x2c0, 226, 0, 289 }, +{ 0x1c0, 226, 0, 290 }, +{ 0x20, 226, 0, 300 }, +{ 0xa0, 226, 0, 298 }, +{ 0x60, 226, 0, 299 }, +{ 0x10, 226, 0, 309 }, +{ 0x50, 226, 0, 307 }, +{ 0x30, 226, 0, 308 }, +{ 0x8, 226, 0, 318 }, +{ 0x28, 226, 0, 316 }, +{ 0x18, 226, 0, 317 }, +{ 0x4, 226, 0, 325 }, +{ 0x2, 226, 0, 326 }, +{ 0x1, 226, 0, 327 }, +{ 0x140, 228, 0, 285 }, +{ 0x540, 228, 0, 283 }, +{ 0x340, 228, 0, 284 }, +{ 0xc0, 228, 0, 294 }, +{ 0x2c0, 228, 0, 292 }, +{ 0x1c0, 228, 0, 293 }, +{ 0x20, 228, 0, 303 }, +{ 0xa0, 228, 0, 301 }, +{ 0x60, 228, 0, 302 }, +{ 0x10, 228, 0, 312 }, +{ 0x50, 228, 0, 310 }, +{ 0x30, 228, 0, 311 }, +{ 0x8, 228, 0, 321 }, +{ 0x28, 228, 0, 319 }, +{ 0x18, 228, 0, 320 }, +{ 0x4, 228, 0, 328 }, +{ 0x2, 228, 0, 329 }, +{ 0x1, 228, 0, 330 }, +{ 0x140, 230, 0, 288 }, +{ 0x540, 230, 0, 286 }, +{ 0x340, 230, 0, 287 }, +{ 0xc0, 230, 0, 297 }, +{ 0x2c0, 230, 0, 295 }, +{ 0x1c0, 230, 0, 296 }, +{ 0x20, 230, 0, 306 }, +{ 0xa0, 230, 0, 304 }, +{ 0x60, 230, 0, 305 }, +{ 0x10, 230, 0, 315 }, +{ 0x50, 230, 0, 313 }, +{ 0x30, 230, 0, 314 }, +{ 0x8, 230, 0, 324 }, +{ 0x28, 230, 0, 322 }, +{ 0x18, 230, 0, 323 }, +{ 0x4, 230, 0, 331 }, +{ 0x2, 230, 0, 332 }, +{ 0x1, 230, 0, 333 }, +{ 0x1, 356, 0, 335 }, +{ 0x3, 356, 0, 334 }, +{ 0x2, 362, 0, 336 }, +{ 0x1, 362, 0, 337 }, +{ 0x2, 358, 0, 338 }, +{ 0x1, 358, 0, 339 }, +{ 0x2, 360, 0, 340 }, +{ 0x1, 360, 0, 341 }, +{ 0x2, 364, 0, 342 }, +{ 0x1, 364, 0, 343 }, +{ 0x1, 215, 0, 370 }, +{ 0x5, 215, 0, 368 }, +{ 0x3, 215, 0, 369 }, +{ 0x140, 224, 0, 346 }, +{ 0x540, 224, 0, 344 }, +{ 0x340, 224, 0, 345 }, +{ 0xc0, 224, 0, 358 }, +{ 0x2c0, 224, 0, 356 }, +{ 0x1c0, 224, 0, 357 }, +{ 0x20, 224, 0, 373 }, +{ 0xa0, 224, 0, 371 }, +{ 0x60, 224, 0, 372 }, +{ 0x10, 224, 0, 385 }, +{ 0x50, 224, 0, 383 }, +{ 0x30, 224, 0, 384 }, +{ 0x8, 224, 0, 397 }, +{ 0x28, 224, 0, 395 }, +{ 0x18, 224, 0, 396 }, +{ 0x4, 224, 0, 407 }, +{ 0x2, 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1980 }, +{ 0x19, 77, 1, 1979 }, +{ 0x7, 89, 1, 1978 }, +{ 0x7, 90, 0, 1977 }, +{ 0x3, 76, 1, 2132 }, +{ 0x3, 77, 1, 2131 }, +{ 0x6, 77, 1, 2129 }, +{ 0x3, 78, 0, 2130 }, +{ 0x28, 57, 1, 2056 }, +{ 0x44, 58, 1, 2053 }, +{ 0x88, 58, 1, 2055 }, +{ 0x28, 59, 0, 2054 }, +{ 0x68, 57, 1, 1984 }, +{ 0x188, 58, 1, 1983 }, +{ 0x38, 68, 1, 1982 }, +{ 0x38, 69, 0, 1981 }, +{ 0x18, 57, 1, 2136 }, +{ 0x14, 58, 1, 2133 }, +{ 0x28, 58, 1, 2135 }, +{ 0x18, 59, 0, 2134 }, +{ 0x14, 57, 1, 2060 }, +{ 0x24, 58, 1, 2059 }, +{ 0x48, 58, 1, 2057 }, +{ 0x14, 59, 0, 2058 }, +{ 0x34, 57, 1, 1988 }, +{ 0x64, 58, 1, 1987 }, +{ 0x1c, 68, 1, 1986 }, +{ 0x1c, 69, 0, 1985 }, +{ 0xc, 57, 1, 2140 }, +{ 0xc, 58, 1, 2139 }, +{ 0x18, 58, 1, 2137 }, +{ 0xc, 59, 0, 2138 }, +{ 0xa, 57, 1, 2064 }, +{ 0x11, 58, 1, 2061 }, +{ 0x22, 58, 1, 2063 }, +{ 0xa, 59, 0, 2062 }, +{ 0x1a, 57, 1, 1992 }, +{ 0x62, 58, 1, 1991 }, +{ 0xe, 68, 1, 1990 }, +{ 0xe, 69, 0, 1989 }, +{ 0x6, 57, 1, 2144 }, +{ 0x5, 58, 1, 2141 }, +{ 0xa, 58, 1, 2143 }, +{ 0x6, 59, 0, 2142 }, +{ 0x5, 57, 1, 2068 }, +{ 0x9, 58, 1, 2067 }, +{ 0x12, 58, 1, 2065 }, +{ 0x5, 59, 0, 2066 }, +{ 0xd, 57, 1, 1996 }, +{ 0x19, 58, 1, 1995 }, +{ 0x7, 68, 1, 1994 }, +{ 0x7, 69, 0, 1993 }, +{ 0x3, 57, 1, 2148 }, +{ 0x3, 58, 1, 2147 }, +{ 0x6, 58, 1, 2145 }, +{ 0x3, 59, 0, 2146 }, +{ 0x8, 71, 1, 2080 }, +{ 0x2, 72, 1, 2079 }, +{ 0x2, 73, 1, 2078 }, +{ 0x2, 74, 0, 2077 }, +{ 0x18, 71, 1, 2076 }, +{ 0x6, 72, 1, 2075 }, +{ 0x6, 73, 1, 2074 }, +{ 0x6, 74, 0, 2073 }, +{ 0x14, 71, 1, 2070 }, +{ 0xa, 75, 0, 2069 }, +{ 0x34, 71, 1, 1998 }, +{ 0xe, 88, 0, 1997 }, +{ 0xc, 71, 1, 2150 }, +{ 0x6, 75, 0, 2149 }, +{ 0x2, 71, 1, 2004 }, +{ 0x4, 74, 0, 2003 }, +{ 0x12, 71, 1, 2002 }, +{ 0xc, 74, 0, 2001 }, +{ 0xa, 71, 1, 2072 }, +{ 0x5, 75, 0, 2071 }, +{ 0x1a, 71, 1, 2000 }, +{ 0x7, 88, 0, 1999 }, +{ 0x6, 71, 1, 2152 }, +{ 0x3, 75, 0, 2151 }, +{ 0x1, 71, 1, 2160 }, +{ 0x1, 72, 1, 2159 }, +{ 0x1, 73, 1, 2158 }, +{ 0x1, 74, 0, 2157 }, +{ 0x3, 71, 1, 2156 }, +{ 0x3, 72, 1, 2155 }, +{ 0x3, 73, 1, 2154 }, +{ 0x3, 74, 0, 2153 }, +{ 0x8, 52, 1, 2092 }, +{ 0x2, 53, 1, 2091 }, +{ 0x2, 54, 1, 2090 }, +{ 0x2, 55, 0, 2089 }, +{ 0x18, 52, 1, 2088 }, +{ 0x6, 53, 1, 2087 }, +{ 0x6, 54, 1, 2086 }, +{ 0x6, 55, 0, 2085 }, +{ 0x14, 52, 1, 2082 }, +{ 0xa, 56, 0, 2081 }, +{ 0x34, 52, 1, 2006 }, +{ 0xe, 67, 0, 2005 }, +{ 0xc, 52, 1, 2162 }, +{ 0x6, 56, 0, 2161 }, +{ 0x2, 52, 1, 2012 }, +{ 0x4, 55, 0, 2011 }, +{ 0x12, 52, 1, 2010 }, +{ 0xc, 55, 0, 2009 }, +{ 0xa, 52, 1, 2084 }, +{ 0x5, 56, 0, 2083 }, +{ 0x1a, 52, 1, 2008 }, +{ 0x7, 67, 0, 2007 }, +{ 0x6, 52, 1, 2164 }, +{ 0x3, 56, 0, 2163 }, +{ 0x1, 52, 1, 2172 }, +{ 0x1, 53, 1, 2171 }, +{ 0x1, 54, 1, 2170 }, +{ 0x1, 55, 0, 2169 }, +{ 0x3, 52, 1, 2168 }, +{ 0x3, 53, 1, 2167 }, +{ 0x3, 54, 1, 2166 }, +{ 0x3, 55, 0, 2165 }, +{ 0x1, 4, 0, 2173 }, +{ 0x1, 245, 0, 2174 }, +{ 0x1, 327, 0, 2175 }, +{ 0x1, 322, 0, 2176 }, +{ 0x2, 306, 0, 2177 }, +{ 0x1, 306, 0, 2180 }, +{ 0x2, 305, 0, 2178 }, +{ 0x1, 305, 0, 2181 }, +{ 0x2, 304, 0, 2179 }, +{ 0x1, 304, 0, 2182 }, +{ 0x1, 303, 0, 2183 }, +{ 0x1, 302, 0, 2184 }, +{ 0x2, 301, 0, 2185 }, +{ 0x1, 301, 0, 2187 }, +{ 0x2, 300, 0, 2186 }, +{ 0x1, 300, 0, 2188 }, +{ 0x1, 330, 0, 2195 }, +{ 0x8, 329, 0, 2189 }, +{ 0x4, 329, 0, 2191 }, +{ 0x2, 329, 0, 2193 }, +{ 0x1, 329, 0, 2196 }, +{ 0x8, 328, 0, 2190 }, +{ 0x4, 328, 0, 2192 }, +{ 0x2, 328, 0, 2194 }, +{ 0x1, 328, 0, 2197 }, +{ 0x1, 299, 0, 2204 }, +{ 0x8, 298, 0, 2198 }, +{ 0x4, 298, 0, 2200 }, +{ 0x2, 298, 0, 2202 }, +{ 0x1, 298, 0, 2205 }, +{ 0x8, 297, 0, 2199 }, +{ 0x4, 297, 0, 2201 }, +{ 0x2, 297, 1, 2203 }, +{ 0x4, 106, 0, 1249 }, +{ 0x1, 297, 0, 2206 }, +{ 0x1, 6, 0, 2207 }, +{ 0x1, 7, 0, 2208 }, +{ 0x1, 244, 0, 2209 }, +{ 0x1, 243, 0, 2210 }, +{ 0x1, 393, 0, 2211 }, +{ 0x1, 294, 0, 2212 }, +{ 0x1, 12, 0, 2213 }, +{ 0x1, 10, 0, 2214 }, +{ 0x1, 368, 0, 2215 }, +{ 0x1, 342, 0, 2216 }, +{ 0x1, 341, 0, 2217 }, +{ 0x1, 392, 0, 2218 }, +{ 0x1, 293, 0, 2219 }, +{ 0x1, 11, 0, 2220 }, +{ 0x1, 9, 0, 2221 }, +{ 0x1, 5, 0, 2222 }, +{ 0x1, 367, 0, 2223 }, +{ 0x1, 366, 0, 2224 }, +{ 0x1, 1, 0, 2225 }, +{ 0x1, 0, 0, 2226 }, +}; + diff --git a/gnu/usr.bin/binutils/opcodes/ia64-asmtab.h b/gnu/usr.bin/binutils/opcodes/ia64-asmtab.h new file mode 100644 index 00000000000..822007a3b78 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-asmtab.h @@ -0,0 +1,148 @@ +/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Bob Manson of Cygnus Support <manson@cygnus.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_ASMTAB_H +#define IA64_ASMTAB_H + +#include "opcode/ia64.h" + +/* The primary opcode table is made up of the following: */ +struct ia64_main_table +{ + /* The entry in the string table that corresponds to the name of this + opcode. */ + unsigned short name_index; + + /* The type of opcode; corresponds to the TYPE field in + struct ia64_opcode. */ + unsigned char opcode_type; + + /* The number of outputs for this opcode. */ + unsigned char num_outputs; + + /* The base insn value for this opcode. It may be modified by completers. */ + ia64_insn opcode; + + /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ + ia64_insn mask; + + /* The operands of this instruction. Corresponds to the OPERANDS field + in struct ia64_opcode. */ + unsigned char operands[5]; + + /* The flags for this instruction. Corresponds to the FLAGS field in + struct ia64_opcode. */ + short flags; + + /* The tree of completers for this instruction; this is an offset into + completer_table. */ + short completers; +}; + +/* Each instruction has a set of possible "completers", or additional + suffixes that can alter the instruction's behavior, and which has + potentially different dependencies. + + The completer entries modify certain bits in the instruction opcode. + Which bits are to be modified are marked by the BITS, MASK and + OFFSET fields. The completer entry may also note dependencies for the + opcode. + + These completers are arranged in a DAG; the pointers are indexes + into the completer_table array. The completer DAG is searched by + find_completer () and ia64_find_matching_opcode (). + + Note that each completer needs to be applied in turn, so that if we + have the instruction + cmp.lt.unc + the completer entries for both "lt" and "unc" would need to be applied + to the opcode's value. + + Some instructions do not require any completers; these contain an + empty completer entry. Instructions that require a completer do + not contain an empty entry. + + Terminal completers (those completers that validly complete an + instruction) are marked by having the TERMINAL_COMPLETER flag set. + + Only dependencies listed in the terminal completer for an opcode are + considered to apply to that opcode instance. */ + +struct ia64_completer_table +{ + /* The bit value that this completer sets. */ + unsigned int bits; + + /* And its mask. 1s are bits that are to be modified in the + instruction. */ + unsigned int mask; + + /* The entry in the string table that corresponds to the name of this + completer. */ + unsigned short name_index; + + /* An alternative completer, or -1 if this is the end of the chain. */ + short alternative; + + /* A pointer to the DAG of completers that can potentially follow + this one, or -1. */ + short subentries; + + /* The bit offset in the instruction where BITS and MASK should be + applied. */ + unsigned char offset : 7; + + unsigned char terminal_completer : 1; + + /* Index into the dependency list table */ + short dependencies; +}; + +/* This contains sufficient information for the disassembler to resolve + the complete name of the original instruction. */ +struct ia64_dis_names +{ + /* COMPLETER_INDEX represents the tree of completers that make up + the instruction. The LSB represents the top of the tree for the + specified instruction. + + A 0 bit indicates to go to the next alternate completer via the + alternative field; a 1 bit indicates that the current completer + is part of the instruction, and to go down the subentries index. + We know we've reached the final completer when we run out of 1 + bits. + + There is always at least one 1 bit. */ + unsigned int completer_index : 20; + + /* The index in the main_table[] array for the instruction. */ + unsigned short insn_index : 11; + + /* If set, the next entry in this table is an alternate possibility + for this instruction encoding. Which one to use is determined by + the instruction type and other factors (see opcode_verify ()). */ + unsigned int next_flag : 1; + + /* The disassembly priority of this entry among instructions. */ + unsigned short priority; +}; + +#endif diff --git a/gnu/usr.bin/binutils/opcodes/ia64-dis.c b/gnu/usr.bin/binutils/opcodes/ia64-dis.c new file mode 100644 index 00000000000..f9add917770 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-dis.c @@ -0,0 +1,273 @@ +/* ia64-dis.c -- Disassemble ia64 instructions + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include <assert.h> +#include <string.h> + +#include "dis-asm.h" +#include "opcode/ia64.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) + +/* Disassemble ia64 instruction. */ + +/* Return the instruction type for OPCODE found in unit UNIT. */ + +static enum ia64_insn_type +unit_to_type (ia64_insn opcode, enum ia64_unit unit) +{ + enum ia64_insn_type type; + int op; + + op = IA64_OP (opcode); + + if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) + { + type = IA64_TYPE_A; + } + else + { + switch (unit) + { + case IA64_UNIT_I: + type = IA64_TYPE_I; break; + case IA64_UNIT_M: + type = IA64_TYPE_M; break; + case IA64_UNIT_B: + type = IA64_TYPE_B; break; + case IA64_UNIT_F: + type = IA64_TYPE_F; break; + case IA64_UNIT_L: + case IA64_UNIT_X: + type = IA64_TYPE_X; break; + default: + type = -1; + } + } + return type; +} + +int +print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) +{ + ia64_insn t0, t1, slot[3], template, s_bit, insn; + int slotnum, j, status, need_comma, retval, slot_multiplier; + const struct ia64_operand *odesc; + const struct ia64_opcode *idesc; + const char *err, *str, *tname; + BFD_HOST_U_64_BIT value; + bfd_byte bundle[16]; + enum ia64_unit unit; + char regname[16]; + + if (info->bytes_per_line == 0) + info->bytes_per_line = 6; + info->display_endian = info->endian; + + slot_multiplier = info->bytes_per_line; + retval = slot_multiplier; + + slotnum = (((long) memaddr) & 0xf) / slot_multiplier; + if (slotnum > 2) + return -1; + + memaddr -= (memaddr & 0xf); + status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (bundle); + t1 = bfd_getl64 (bundle + 8); + s_bit = t0 & 1; + template = (t0 >> 1) & 0xf; + slot[0] = (t0 >> 5) & 0x1ffffffffffLL; + slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + slot[2] = (t1 >> 23) & 0x1ffffffffffLL; + + tname = ia64_templ_desc[template].name; + if (slotnum == 0) + (*info->fprintf_func) (info->stream, "[%s] ", tname); + else + (*info->fprintf_func) (info->stream, " ", tname); + + unit = ia64_templ_desc[template].exec_unit[slotnum]; + + if (template == 2 && slotnum == 1) + { + /* skip L slot in MLI template: */ + slotnum = 2; + retval += slot_multiplier; + } + + insn = slot[slotnum]; + + if (unit == IA64_UNIT_NIL) + goto decoding_failed; + + idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); + if (idesc == NULL) + goto decoding_failed; + + /* print predicate, if any: */ + + if ((idesc->flags & IA64_OPCODE_NO_PRED) + || (insn & 0x3f) == 0) + (*info->fprintf_func) (info->stream, " "); + else + (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); + + /* now the actual instruction: */ + + (*info->fprintf_func) (info->stream, "%s", idesc->name); + if (idesc->operands[0]) + (*info->fprintf_func) (info->stream, " "); + + need_comma = 0; + for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) + { + odesc = elf64_ia64_operands + idesc->operands[j]; + + if (need_comma) + (*info->fprintf_func) (info->stream, ","); + + if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) + { + /* special case of 64 bit immediate load: */ + value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) + | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) + | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) + { + /* 62-bit immediate for nop.x/break.x */ + value = ((slot[1] & 0x1ffffffffffLL) << 21) + | (((insn >> 36) & 0x1) << 20) + | ((insn >> 6) & 0xfffff); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) + { + /* 60-bit immedate for long branches. */ + value = (((insn >> 13) & 0xfffff) + | (((insn >> 36) & 1) << 59) + | (slot[1] << 20)) << 4; + } + else + { + err = (*odesc->extract) (odesc, insn, &value); + if (err) + { + (*info->fprintf_func) (info->stream, "%s", err); + goto done; + } + } + + switch (odesc->class) + { + case IA64_OPND_CLASS_CST: + (*info->fprintf_func) (info->stream, "%s", odesc->str); + break; + + case IA64_OPND_CLASS_REG: + if (odesc->str[0] == 'a' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: case 1: case 2: case 3: + case 4: case 5: case 6: case 7: + sprintf (regname, "ar.k%u", (unsigned int) value); + break; + case 16: strcpy (regname, "ar.rsc"); break; + case 17: strcpy (regname, "ar.bsp"); break; + case 18: strcpy (regname, "ar.bspstore"); break; + case 19: strcpy (regname, "ar.rnat"); break; + case 32: strcpy (regname, "ar.ccv"); break; + case 36: strcpy (regname, "ar.unat"); break; + case 40: strcpy (regname, "ar.fpsr"); break; + case 44: strcpy (regname, "ar.itc"); break; + case 64: strcpy (regname, "ar.pfs"); break; + case 65: strcpy (regname, "ar.lc"); break; + case 66: strcpy (regname, "ar.ec"); break; + default: + sprintf (regname, "ar%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else + (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_IND: + (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_ABS: + str = 0; + if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) + switch (value) + { + case 0x0: str = "@brcst"; break; + case 0x8: str = "@mix"; break; + case 0x9: str = "@shuf"; break; + case 0xa: str = "@alt"; break; + case 0xb: str = "@rev"; break; + } + + if (str) + (*info->fprintf_func) (info->stream, "%s", str); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) + (*info->fprintf_func) (info->stream, "%lld", value); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) + (*info->fprintf_func) (info->stream, "%llu", value); + else + (*info->fprintf_func) (info->stream, "0x%llx", value); + break; + + case IA64_OPND_CLASS_REL: + (*info->print_address_func) (memaddr + value, info); + break; + } + + need_comma = 1; + if (j + 1 == idesc->num_outputs) + { + (*info->fprintf_func) (info->stream, "="); + need_comma = 0; + } + } + if (slotnum + 1 == ia64_templ_desc[template].group_boundary + || ((slotnum == 2) && s_bit)) + (*info->fprintf_func) (info->stream, ";;"); + + done: + ia64_free_opcode ((struct ia64_opcode *)idesc); + failed: + if (slotnum == 2) + retval += 16 - 3*slot_multiplier; + return retval; + + decoding_failed: + (*info->fprintf_func) (info->stream, " data8 %#011llx", insn); + goto failed; +} diff --git a/gnu/usr.bin/binutils/opcodes/ia64-gen.c b/gnu/usr.bin/binutils/opcodes/ia64-gen.c new file mode 100644 index 00000000000..4b4b1970f57 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-gen.c @@ -0,0 +1,2789 @@ +/* ia64-gen.c -- Generate a shrunk set of opcode tables + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* While the ia64-opc-* set of opcode tables are easy to maintain, + they waste a tremendous amount of space. ia64-gen rearranges the + instructions into a directed acyclic graph (DAG) of instruction opcodes and + their possible completers, as well as compacting the set of strings used. + + The disassembler table consists of a state machine that does + branching based on the bits of the opcode being disassembled. The + state encodings have been chosen to minimize the amount of space + required. + + The resource table is constructed based on some text dependency tables, + which are also easier to maintain than the final representation. + +*/ + +#include <stdio.h> +#include <ctype.h> + +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "ia64-opc.h" +#include "ia64-opc-a.c" +#include "ia64-opc-i.c" +#include "ia64-opc-m.c" +#include "ia64-opc-b.c" +#include "ia64-opc-f.c" +#include "ia64-opc-x.c" +#include "ia64-opc-d.c" + +int debug = 0; + +#define tmalloc(X) (X *) xmalloc (sizeof (X)) + +/* The main opcode table entry. Each entry is a unique combination of + name and flags (no two entries in the table compare as being equal + via opcodes_eq). */ +struct main_entry +{ + /* The base name of this opcode. The names of its completers are + appended to it to generate the full instruction name. */ + struct string_entry *name; + /* The base opcode entry. Which one to use is a fairly arbitrary choice; + it uses the first one passed to add_opcode_entry. */ + struct ia64_opcode *opcode; + /* The list of completers that can be applied to this opcode. */ + struct completer_entry *completers; + /* Next entry in the chain. */ + struct main_entry *next; + /* Index in the main table. */ + int main_index; +} *maintable, **ordered_table; +int otlen = 0; +int ottotlen = 0; +int opcode_count = 0; + +/* The set of possible completers for an opcode. */ +struct completer_entry +{ + /* This entry's index in the ia64_completer_table[] array. */ + int num; + + /* The name of the completer. */ + struct string_entry *name; + + /* This entry's parent. */ + struct completer_entry *parent; + + /* Set if this is a terminal completer (occurs at the end of an + opcode). */ + int is_terminal; + + /* An alternative completer. */ + struct completer_entry *alternative; + + /* Additional completers that can be appended to this one. */ + struct completer_entry *addl_entries; + + /* Before compute_completer_bits () is invoked, this contains the actual + instruction opcode for this combination of opcode and completers. + Afterwards, it contains those bits that are different from its + parent opcode. */ + ia64_insn bits; + + /* Bits set to 1 correspond to those bits in this completer's opcode + that are different from its parent completer's opcode (or from + the base opcode if the entry is the root of the opcode's completer + list). This field is filled in by compute_completer_bits (). */ + ia64_insn mask; + + /* Index into the opcode dependency list, or -1 if none. */ + int dependencies; + + /* Remember the order encountered in the opcode tables. */ + int order; +}; + +/* One entry in the disassembler name table. */ +struct disent +{ + /* The index into the ia64_name_dis array for this entry. */ + int ournum; + + /* The index into the main_table[] array. */ + int insn; + + /* The disassmbly priority of this entry. */ + int priority; + + /* The completer_index value for this entry. */ + int completer_index; + + /* How many other entries share this decode. */ + int nextcnt; + + /* The next entry sharing the same decode. */ + struct disent *nexte; + + /* The next entry in the name list. */ + struct disent *next_ent; +} *disinsntable = NULL; + +/* A state machine that will eventually be used to generate the + disassembler table. */ +struct bittree +{ + struct disent *disent; + struct bittree *bits[3]; /* 0, 1, and X (don't care) */ + int bits_to_skip; + int skip_flag; +} *bittree; + +/* The string table contains all opcodes and completers sorted in + alphabetical order. */ + +/* One entry in the string table. */ +struct string_entry +{ + /* The index in the ia64_strings[] array for this entry. */ + int num; + /* And the string. */ + char *s; +} **string_table = NULL; +int strtablen = 0; +int strtabtotlen = 0; + + +/* resource dependency entries */ +struct rdep +{ + char *name; /* resource name */ + unsigned + mode:2, /* RAW, WAW, or WAR */ + semantics:3; /* dependency semantics */ + char *extra; /* additional semantics info */ + int nchks; + int total_chks; /* total #of terminal insns */ + int *chks; /* insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc */ + int *chknotes; /* dependency notes for each class */ + int nregs; + int total_regs; /* total #of terminal insns */ + int *regs; /* insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc */ + int *regnotes; /* dependency notes for each class */ + + int waw_special; /* special WAW dependency note */ +} **rdeps = NULL; + +static int rdepslen = 0; +static int rdepstotlen = 0; + +/* array of all instruction classes */ +struct iclass +{ + char *name; /* instruction class name */ + int is_class; /* is a class, not a terminal */ + int nsubs; + int *subs; /* other classes within this class */ + int nxsubs; + int xsubs[4]; /* exclusions */ + char *comment; /* optional comment */ + int note; /* optional note */ + int terminal_resolved; /* did we match this with anything? */ + int orphan; /* detect class orphans */ +} **ics = NULL; + +static int iclen = 0; +static int ictotlen = 0; + +/* an opcode dependency (chk/reg pair of dependency lists) */ +struct opdep +{ + int chk; /* index into dlists */ + int reg; /* index into dlists */ +} **opdeps; + +static int opdeplen = 0; +static int opdeptotlen = 0; + +/* a generic list of dependencies w/notes encoded. these may be shared. */ +struct deplist +{ + int len; + unsigned short *deps; +} **dlists; + +static int dlistlen = 0; +static int dlisttotlen = 0; + +/* add NAME to the resource table, where TYPE is RAW or WAW */ +static struct rdep * +insert_resource (const char *name, enum ia64_dependency_mode type) +{ + if (rdepslen == rdepstotlen) + { + rdepstotlen += 20; + rdeps = (struct rdep **) + xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); + } + rdeps[rdepslen] = tmalloc(struct rdep); + memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); + rdeps[rdepslen]->name = xstrdup (name); + rdeps[rdepslen]->mode = type; + rdeps[rdepslen]->waw_special = 0; + + return rdeps[rdepslen++]; +} + +/* are the lists of dependency indexes equivalent? */ +static int +deplist_equals (struct deplist *d1, struct deplist *d2) +{ + int i; + + if (d1->len != d2->len) + return 0; + + for (i=0;i < d1->len;i++) + { + if (d1->deps[i] != d2->deps[i]) + return 0; + } + + return 1; +} + +/* add the list of dependencies to the list of dependency lists */ +static short +insert_deplist(int count, unsigned short *deps) +{ + /* sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists + */ + struct deplist *list; + char set[0x10000]; + int i; + + memset ((void *)set, 0, sizeof(set)); + for (i=0;i < count;i++) + set[deps[i]] = 1; + count = 0; + for (i=0;i < (int)sizeof(set);i++) + if (set[i]) + ++count; + + list = tmalloc(struct deplist); + list->len = count; + list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count); + for (i=0, count=0;i < (int)sizeof(set);i++) + { + if (set[i]) + { + list->deps[count++] = i; + } + } + + /* does this list exist already? */ + for (i=0;i < dlistlen;i++) + { + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } + } + + if (dlistlen == dlisttotlen) + { + dlisttotlen += 20; + dlists = (struct deplist **) + xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); + } + dlists[dlistlen] = list; + + return dlistlen++; +} + +/* add the given pair of dependency lists to the opcode dependency list */ +static short +insert_dependencies (int nchks, unsigned short *chks, + int nregs, unsigned short *regs) +{ + struct opdep *pair; + int i; + int regind = -1; + int chkind = -1; + + if (nregs > 0) + regind = insert_deplist (nregs, regs); + if (nchks > 0) + chkind = insert_deplist (nchks, chks); + + for (i=0;i < opdeplen;i++) + { + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + } + pair = tmalloc(struct opdep); + pair->chk = chkind; + pair->reg = regind; + + if (opdeplen == opdeptotlen) + { + opdeptotlen += 20; + opdeps = (struct opdep **) + xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); + } + opdeps[opdeplen] = pair; + + return opdeplen++; +} + +static void +mark_used (struct iclass *ic, int clear_terminals) +{ + int i; + + ic->orphan = 0; + if (clear_terminals) + ic->terminal_resolved = 1; + + for (i=0;i < ic->nsubs;i++) + { + mark_used (ics[ic->subs[i]], clear_terminals); + } + for (i=0;i < ic->nxsubs;i++) + { + mark_used (ics[ic->xsubs[i]], clear_terminals); + } +} + +/* look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array */ +static int +fetch_insn_class(const char *full_name, int create) +{ + char *name; + char *notestr; + char *xsect; + char *comment; + int i, note = 0; + int ind; + int is_class = 0; + + if (strncmp (full_name, "IC:", 3) == 0) + { + name = xstrdup (full_name + 3); + is_class = 1; + } + else + name = xstrdup (full_name); + + if ((xsect = strchr(name, '\\')) != NULL) + is_class = 1; + if ((comment = strchr(name, '[')) != NULL) + is_class = 1; + if ((notestr = strchr(name, '+')) != NULL) + is_class = 1; + + /* If it is a composite class, then ignore comments and notes that come after + the '\\', since they don't apply to the part we are decoding now. */ + if (xsect) + { + if (comment > xsect) + comment = 0; + if (notestr > xsect) + notestr = 0; + } + + if (notestr) + { + char *nextnotestr; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + } + + /* If it's a composite class, leave the notes and comments in place so that + we have a unique name for the composite class. Otherwise, we remove + them. */ + if (!xsect) + { + if (notestr) + *notestr = 0; + if (comment) + *comment = 0; + } + + for (i=0;i < iclen;i++) + if (strcmp(name, ics[i]->name) == 0 + && ((comment == NULL && ics[i]->comment == NULL) + || (comment != NULL && ics[i]->comment != NULL + && strncmp (ics[i]->comment, comment, + strlen (ics[i]->comment)) == 0)) + && note == ics[i]->note) + return i; + + if (!create) + return -1; + + /* doesn't exist, so make a new one */ + if (iclen == ictotlen) + { + ictotlen += 20; + ics = (struct iclass **) + xrealloc(ics, (ictotlen)*sizeof(struct iclass *)); + } + ind = iclen++; + ics[ind] = tmalloc(struct iclass); + memset((void *)ics[ind], 0, sizeof(struct iclass)); + ics[ind]->name = xstrdup(name); + ics[ind]->is_class = is_class; + ics[ind]->orphan = 1; + + if (comment) + { + ics[ind]->comment = xstrdup (comment + 1); + ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0; + } + if (notestr) + ics[ind]->note = note; + + /* if it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ + if ((xsect || comment || notestr) && is_class) + { + /* First, populate with the class we're based on. */ + char *subname = name; + if (xsect) + *xsect = 0; + else if (comment) + *comment = 0; + else if (notestr) + *notestr = 0; + ics[ind]->nsubs = 1; + ics[ind]->subs = tmalloc(int); + ics[ind]->subs[0] = fetch_insn_class (subname, 1);; + } + + while (xsect) + { + char *subname = xsect + 1; + xsect = strchr (subname, '\\'); + if (xsect) + *xsect = 0; + ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); + ics[ind]->nxsubs++; + } + free (name); + + return ind; +} + +/* for sorting a class's sub-class list only; make sure classes appear before + terminals */ +static int +sub_compare (const void *e1, const void *e2) +{ + struct iclass *ic1 = ics[*(int *)e1]; + struct iclass *ic2 = ics[*(int *)e2]; + + if (ic1->is_class) + { + if (!ic2->is_class) + return -1; + } + else if (ic2->is_class) + return 1; + + return strcmp (ic1->name, ic2->name); +} + +static void +load_insn_classes() +{ + FILE *fp = fopen("ia64-ic.tbl", "r"); + char buf[2048]; + + if (fp == NULL){ + fprintf (stderr, "Can't find ia64-ic.tbl for reading\n"); + exit(1); + } + + /* discard first line */ + fgets (buf, sizeof(buf), fp); + + while (!feof(fp)) + { + int iclass; + char *name; + char *tmp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (isspace(buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort (); + } + *tmp++ = '\0'; + + iclass = fetch_insn_class(name, 1); + ics[iclass]->is_class = 1; + + if (strcmp (name, "none") == 0) + { + ics[iclass]->is_class = 0; + ics[iclass]->terminal_resolved = 1; + continue; + } + + /* for this class, record all sub-classes */ + while (*tmp) + { + char *subname; + int sub; + + while (*tmp && isspace(*tmp)) + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + subname = tmp; + while (*tmp && *tmp != ',') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + if (*tmp == ',') + *tmp++ = '\0'; + + ics[iclass]->subs = (int *) + xrealloc((void *)ics[iclass]->subs, + (ics[iclass]->nsubs+1)*sizeof(int)); + + sub = fetch_insn_class(subname, 1); + ics[iclass]->subs = (int *) + xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int)); + ics[iclass]->subs[ics[iclass]->nsubs++] = sub; + } + /* make sure classes come before terminals */ + qsort ((void *)ics[iclass]->subs, + ics[iclass]->nsubs, sizeof(int), sub_compare); + } + fclose(fp); + + if (debug) + { + printf ("%d classes\n", iclen); + } +} + +/* extract the insn classes from the given line */ +static void +parse_resource_users(ref, usersp, nusersp, notesp) + char *ref; + int **usersp; + int *nusersp; + int **notesp; +{ + int c; + char *line = xstrdup (ref); + char *tmp = line; + int *users = *usersp; + int count = *nusersp; + int *notes = *notesp; + + c = *tmp; + while (c != 0) + { + char *notestr; + int note; + char *xsect; + int iclass; + int create = 0; + char *name; + + while (isspace(*tmp)) + ++tmp; + name = tmp; + while (*tmp && *tmp != ',') + ++tmp; + c = *tmp; + *tmp++ = '\0'; + + xsect = strchr(name, '\\'); + if ((notestr = strstr(name, "+")) != NULL) + { + char *nextnotestr; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + /* note 13 always implies note 1 */ + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + if (!xsect) + *notestr = '\0'; + } + else + note = 0; + + /* All classes are created when the insn class table is parsed; + Individual instructions might not appear until the dependency tables + are read. Only create new classes if it's *not* an insn class, + or if it's a composite class (which wouldn't necessarily be in the IC + table). + */ + if (strncmp(name, "IC:", 3) != 0 || xsect != NULL) + create = 1; + + iclass = fetch_insn_class(name, create); + if (iclass != -1) + { + users = (int *) + xrealloc ((void *)users,(count+1)*sizeof(int)); + notes = (int *) + xrealloc ((void *)notes,(count+1)*sizeof(int)); + notes[count] = note; + users[count++] = iclass; + mark_used (ics[iclass], 0); + } + else + { + if (debug) + printf("Class %s not found\n", name); + } + } + /* update the return values */ + *usersp = users; + *nusersp = count; + *notesp = notes; + + free (line); +} + +static int +parse_semantics (char *sem) +{ + if (strcmp (sem, "none") == 0) + return IA64_DVS_NONE; + else if (strcmp (sem, "implied") == 0) + return IA64_DVS_IMPLIED; + else if (strcmp (sem, "impliedF") == 0) + return IA64_DVS_IMPLIEDF; + else if (strcmp (sem, "data") == 0) + return IA64_DVS_DATA; + else if (strcmp (sem, "instr") == 0) + return IA64_DVS_INSTR; + else if (strcmp (sem, "specific") == 0) + return IA64_DVS_SPECIFIC; + else if (strcmp (sem, "stop") == 0) + return IA64_DVS_STOP; + else + return IA64_DVS_OTHER; +} + +static void +add_dep (const char *name, const char *chk, const char *reg, + int semantics, int mode, char *extra, int flag) +{ + struct rdep *rs; + + rs = insert_resource (name, mode); + parse_resource_users (chk, &rs->chks, &rs->nchks, + &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, + &rs->regnotes); + rs->semantics = semantics; + rs->extra = extra; + rs->waw_special = flag; +} + +static void +load_depfile (const char *filename, enum ia64_dependency_mode mode) +{ + FILE *fp = fopen(filename, "r"); + char buf[1024]; + + if (fp == NULL){ + fprintf (stderr, "Can't find %s for reading\n", filename); + exit(1); + } + + fgets(buf, sizeof(buf), fp); + while (!feof(fp)) + { + char *name, *tmp; + int semantics; + char *extra; + char *regp, *chkp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (isspace(buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + ++tmp; + *tmp++ = '\0'; + + while (isspace (*tmp)) + ++tmp; + regp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (isspace (*tmp)) + ++tmp; + chkp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (isspace (*tmp)) + ++tmp; + semantics = parse_semantics (tmp); + extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; + + /* For WAW entries, if the chks and regs differ, we need to enter the + entries in both positions so that the tables will be parsed properly, + without a lot of extra work */ + if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + add_dep (name, regp, chkp, semantics, mode, extra, 1); + } + else + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + } + } + fclose(fp); +} + +static void +load_dependencies() +{ + load_depfile ("ia64-raw.tbl", IA64_DV_RAW); + load_depfile ("ia64-waw.tbl", IA64_DV_WAW); + load_depfile ("ia64-war.tbl", IA64_DV_WAR); + + if (debug) + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); +} + +/* is the given operand an indirect register file operand? */ +static int +irf_operand (int op, const char *field) +{ + if (!field) + { + return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 + || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 + || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 + || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; + } + else + { + return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) + || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) + || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) + || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) + || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) + || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) + || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) + || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); + } +} + +/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes */ +static int +in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field) +{ + int plain_mov = strcmp (idesc->name, "mov") == 0; + + if (!format) + return 0; + + switch (ic->name[4]) + { + default: + abort (); + case 'a': + { + int i = strcmp (idesc->name, "mov.i") == 0; + int m = strcmp (idesc->name, "mov.m") == 0; + int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; + int i28 = i && idesc->operands[1] == IA64_OPND_AR3; + int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; + int m31 = m && idesc->operands[1] == IA64_OPND_AR3; + int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; + int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; + + /* IC:mov ar */ + if (i2627) + return strstr (format, "I26") || strstr (format, "I27"); + if (i28) + return strstr (format, "I28") != NULL; + if (m2930) + return strstr (format, "M29") || strstr (format, "M30"); + if (m31) + return strstr (format, "M31") != NULL; + if (pseudo0 || pseudo1) + return 1; + } + break; + case 'b': + { + int i21 = idesc->operands[0] == IA64_OPND_B1; + int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; + if (i22) + return strstr (format, "I22") != NULL; + if (i21) + return strstr (format, "I21") != NULL; + } + break; + case 'c': + { + int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; + int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; + if (m32) + return strstr (format, "M32") != NULL; + if (m33) + return strstr (format, "M33") != NULL; + } + break; + case 'i': + if (ic->name[5] == 'n') + { + int m42 = plain_mov && irf_operand (idesc->operands[0], field); + int m43 = plain_mov && irf_operand (idesc->operands[1], field); + if (m42) + return strstr (format, "M42") != NULL; + if (m43) + return strstr (format, "M43") != NULL; + } + else if (ic->name[5] == 'p') + { + return idesc->operands[1] == IA64_OPND_IP; + } + else + abort (); + break; + case 'p': + if (ic->name[5] == 'r') + { + int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; + int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; + int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; + if (i23) + return strstr (format, "I23") != NULL; + if (i24) + return strstr (format, "I24") != NULL; + if (i25) + return strstr (format, "I25") != NULL; + } + else if (ic->name[5] == 's') + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + else + abort (); + break; + case 'u': + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + break; + } + return 0; +} + + +/* is the given opcode in the given insn class? */ +static int +in_iclass(struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) +{ + int i; + int resolved = 0; + + if (ic->comment) + { + if (!strncmp (ic->comment, "Format", 6)) + { + /* assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ + if (format) + { + if (strlen (ic->comment) < strlen (format)) + { + fprintf (stderr, "Warning: most recent format '%s'\n" + "appears more restrictive than '%s'\n", + ic->comment, format); + format = ic->comment; + } + } + else + format = ic->comment; + } + else if (!strncmp (ic->comment, "Field", 5)) + { + if (field) + fprintf (stderr, "Overlapping field %s->%s\n", + ic->comment, field); + field = ic->comment; + } + } + + /* an insn class matches anything that is the same followed by completers, + except when the absence and presence of completers constitutes different + instructions */ + if (ic->nsubs == 0 && ic->nxsubs == 0) + { + int is_mov = strncmp (idesc->name, "mov", 3) == 0; + int plain_mov = strcmp (idesc->name, "mov") == 0; + int len = strlen(ic->name); + + resolved = ((strncmp (ic->name, idesc->name, len) == 0) + && (idesc->name[len] == '\0' + || idesc->name[len] == '.')); + + /* all break and nop variations must match exactly */ + if (resolved && + (strcmp (ic->name, "break") == 0 + || strcmp (ic->name, "nop") == 0)) + resolved = strcmp (ic->name, idesc->name) == 0; + + /* assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block */ + if (resolved && field) + { + /* check Field(sf)==sN against opcode sN */ + if (strstr(field, "(sf)==") != NULL) + { + char *sf; + if ((sf = strstr (idesc->name, ".s")) != 0) + { + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; + } + } + /* check Field(lftype)==XXX */ + else if (strstr (field, "(lftype)") != NULL) + { + if (strstr (idesc->name, "fault") != NULL) + resolved = strstr (field, "fault") != NULL; + else + resolved = strstr (field, "fault") == NULL; + } + /* handle Field(ctype)==XXX */ + else if (strstr (field, "(ctype)") != NULL) + { + if (strstr (idesc->name, "or.andcm")) + resolved = strstr (field, "or.andcm") != NULL; + else if (strstr (idesc->name, "and.orcm")) + resolved = strstr (field, "and.orcm") != NULL; + else if (strstr (idesc->name, "orcm")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "or")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "andcm")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "and")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "unc")) + resolved = strstr (field, "unc") != NULL; + else + resolved = strcmp (field, "Field(ctype)==") == 0; + } + } + if (resolved && format) + { + if (strncmp (idesc->name, "dep", 3) == 0 + && strstr (format, "I13") != NULL) + resolved = idesc->operands[1] == IA64_OPND_IMM8; + else if (strncmp (idesc->name, "chk", 3) == 0 + && strstr (format, "M21") != NULL) + resolved = idesc->operands[0] == IA64_OPND_F2; + else if (strncmp (idesc->name, "lfetch", 6) == 0) + resolved = (strstr (format, "M14 M15") != NULL + && (idesc->operands[1] == IA64_OPND_R2 + || idesc->operands[1] == IA64_OPND_IMM9b)); + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B5") != NULL) + resolved = idesc->operands[1] == IA64_OPND_B2; + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B3") != NULL) + resolved = idesc->operands[1] == IA64_OPND_TGT25c; + else if (strncmp (idesc->name, "brp", 3) == 0 + && strstr (format, "B7") != NULL) + resolved = idesc->operands[0] == IA64_OPND_B2; + else if (strcmp (ic->name, "invala") == 0) + resolved = strcmp (idesc->name, ic->name) == 0; + else if (strncmp (idesc->name, "st", 2) == 0 + && strstr (format, "M5") != NULL) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else + resolved = 0; + } + + /* misc brl variations ('.cond' is optional); + plain brl matches brl.cond */ + if (!resolved + && (strcmp (idesc->name, "brl") == 0 + || strncmp (idesc->name, "brl.", 4) == 0) + && strcmp (ic->name, "brl.cond") == 0) + { + resolved = 1; + } + + /* misc br variations ('.cond' is optional) */ + if (!resolved + && (strcmp (idesc->name, "br") == 0 + || strncmp (idesc->name, "br.", 3) == 0) + && strcmp (ic->name, "br.cond") == 0) + { + if (format) + resolved = (strstr (format, "B4") != NULL + && idesc->operands[0] == IA64_OPND_B2) + || (strstr (format, "B1") != NULL + && idesc->operands[0] == IA64_OPND_TGT25c); + else + resolved = 1; + } + + /* probe variations */ + if (!resolved && strncmp (idesc->name, "probe", 5) == 0) + { + resolved = strcmp (ic->name, "probe") == 0 + && !((strstr (idesc->name, "fault") != NULL) + ^ (format && strstr (format, "M40") != NULL)); + } + /* mov variations */ + if (!resolved && is_mov) + { + if (plain_mov) + { + /* mov alias for fmerge */ + if (strcmp (ic->name, "fmerge") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_F1 + && idesc->operands[1] == IA64_OPND_F3; + } + /* mov alias for adds (r3 or imm14) */ + else if (strcmp (ic->name, "adds") == 0) + { + resolved = (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_R3 + || (idesc->operands[1] == IA64_OPND_IMM14))); + } + /* mov alias for addl */ + else if (strcmp (ic->name, "addl") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_R1 + && idesc->operands[1] == IA64_OPND_IMM22; + } + } + /* some variants of mov and mov.[im] */ + if (!resolved && strncmp (ic->name, "mov_", 4) == 0) + { + resolved = in_iclass_mov_x (idesc, ic, format, field); + } + } + + /* keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn */ + if (resolved) + { + ic->terminal_resolved = 1; + } + } + else for (i=0;i < ic->nsubs;i++) + { + if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep)) + { + int j; + for (j=0;j < ic->nxsubs;j++) + { + if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + } + if (debug > 1) + printf ("%s is in IC %s\n", + idesc->name, ic->name); + resolved = 1; + break; + } + } + + /* If it's in this IC, add the IC note (if any) to the insn */ + if (resolved) + { + if (ic->note && notep) + { + if (*notep && *notep != ic->note) + { + fprintf (stderr, "Warning: overwriting note %d with note %d" + "(IC:%s)\n", + *notep, ic->note, ic->name); + } + *notep = ic->note; + } + } + + return resolved; +} + + +static int +lookup_regindex (const char *name, int specifier) +{ + switch (specifier) + { + case IA64_RS_ARX: + if (strstr (name, "[RSC]")) + return 16; + if (strstr (name, "[BSP]")) + return 17; + else if (strstr (name, "[BSPSTORE]")) + return 18; + else if (strstr (name, "[RNAT]")) + return 19; + else if (strstr (name, "[CCV]")) + return 32; + else if (strstr (name, "[ITC]")) + return 44; + else if (strstr (name, "[PFS]")) + return 64; + else if (strstr (name, "[LC]")) + return 65; + else if (strstr (name, "[EC]")) + return 66; + abort (); + case IA64_RS_CRX: + if (strstr (name, "[DCR]")) + return 0; + else if (strstr (name, "[ITM]")) + return 1; + else if (strstr (name, "[IVA]")) + return 2; + else if (strstr (name, "[PTA]")) + return 8; + else if (strstr (name, "[GPTA]")) + return 9; + else if (strstr (name, "[IPSR]")) + return 16; + else if (strstr (name, "[ISR]")) + return 17; + else if (strstr (name, "[IIP]")) + return 19; + else if (strstr (name, "[IFA]")) + return 20; + else if (strstr (name, "[ITIR]")) + return 21; + else if (strstr (name, "[IIPA]")) + return 22; + else if (strstr (name, "[IFS]")) + return 23; + else if (strstr (name, "[IIM]")) + return 24; + else if (strstr (name, "[IHA]")) + return 25; + else if (strstr (name, "[LID]")) + return 64; + else if (strstr (name, "[IVR]")) + return 65; + else if (strstr (name, "[TPR]")) + return 66; + else if (strstr (name, "[EOI]")) + return 67; + else if (strstr (name, "[ITV]")) + return 72; + else if (strstr (name, "[PMV]")) + return 73; + else if (strstr (name, "[CMCV]")) + return 74; + abort (); + case IA64_RS_PSR: + if (strstr (name, ".be")) + return 1; + else if (strstr (name, ".up")) + return 2; + else if (strstr (name, ".ac")) + return 3; + else if (strstr (name, ".mfl")) + return 4; + else if (strstr (name, ".mfh")) + return 5; + else if (strstr (name, ".ic")) + return 13; + else if (strstr (name, ".i")) + return 14; + else if (strstr (name, ".pk")) + return 15; + else if (strstr (name, ".dt")) + return 17; + else if (strstr (name, ".dfl")) + return 18; + else if (strstr (name, ".dfh")) + return 19; + else if (strstr (name, ".sp")) + return 20; + else if (strstr (name, ".pp")) + return 21; + else if (strstr (name, ".di")) + return 22; + else if (strstr (name, ".si")) + return 23; + else if (strstr (name, ".db")) + return 24; + else if (strstr (name, ".lp")) + return 25; + else if (strstr (name, ".tb")) + return 26; + else if (strstr (name, ".rt")) + return 27; + else if (strstr (name, ".cpl")) + return 32; + else if (strstr (name, ".rs")) + return 34; + else if (strstr (name, ".mc")) + return 35; + else if (strstr (name, ".it")) + return 36; + else if (strstr (name, ".id")) + return 37; + else if (strstr (name, ".da")) + return 38; + else if (strstr (name, ".dd")) + return 39; + else if (strstr (name, ".ss")) + return 40; + else if (strstr (name, ".ri")) + return 41; + else if (strstr (name, ".ed")) + return 43; + else if (strstr (name, ".bn")) + return 44; + else if (strstr (name, ".ia")) + return 45; + else + abort (); + default: + break; + } + return REG_NONE; +} + +static int +lookup_specifier (const char *name) +{ + if (strchr (name, '%')) + { + if (strstr (name, "AR[K%]") != NULL) + return IA64_RS_AR_K; + if (strstr (name, "AR[UNAT]") != NULL) + return IA64_RS_AR_UNAT; + if (strstr (name, "AR%, % in 8") != NULL) + return IA64_RS_AR; + if (strstr (name, "AR%, % in 48") != NULL) + return IA64_RS_ARb; + if (strstr (name, "BR%") != NULL) + return IA64_RS_BR; + if (strstr (name, "CR[IRR%]") != NULL) + return IA64_RS_CR_IRR; + if (strstr (name, "CR[LRR%]") != NULL) + return IA64_RS_CR_LRR; + if (strstr (name, "CR%") != NULL) + return IA64_RS_CR; + if (strstr (name, "FR%, % in 0") != NULL) + return IA64_RS_FR; + if (strstr (name, "FR%, % in 2") != NULL) + return IA64_RS_FRb; + if (strstr (name, "GR%") != NULL) + return IA64_RS_GR; + if (strstr (name, "PR%, % in 1 ") != NULL) + return IA64_RS_PR; + if (strstr (name, "PR%, % in 16 ") != NULL) + return IA64_RS_PRr; + + fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n", + name); + } + else if (strchr (name, '#')) + { + if (strstr (name, "CPUID#") != NULL) + return IA64_RS_CPUID; + if (strstr (name, "DBR#") != NULL) + return IA64_RS_DBR; + if (strstr (name, "IBR#") != NULL) + return IA64_RS_IBR; + if (strstr (name, "MSR#") != NULL) + return IA64_RS_MSR; + if (strstr (name, "PKR#") != NULL) + return IA64_RS_PKR; + if (strstr (name, "PMC#") != NULL) + return IA64_RS_PMC; + if (strstr (name, "PMD#") != NULL) + return IA64_RS_PMD; + if (strstr (name, "RR#") != NULL) + return IA64_RS_RR; + + fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n", + name); + } + else if (strncmp (name, "AR[FPSR]", 8) == 0) + return IA64_RS_AR_FPSR; + else if (strncmp (name, "AR[", 3) == 0) + return IA64_RS_ARX; + else if (strncmp (name, "CR[", 3) == 0) + return IA64_RS_CRX; + else if (strncmp (name, "PSR.", 4) == 0) + return IA64_RS_PSR; + else if (strcmp (name, "InService*") == 0) + return IA64_RS_INSERVICE; + else if (strcmp (name, "GR0") == 0) + return IA64_RS_GR0; + else if (strcmp (name, "CFM") == 0) + return IA64_RS_CFM; + else if (strcmp (name, "PR63") == 0) + return IA64_RS_PR63; + else if (strcmp (name, "RSE") == 0) + return IA64_RS_RSE; + + return IA64_RS_ANY; +} + +void +print_dependency_table () +{ + int i, j; + + if (debug) + { + for (i=0;i < iclen;i++) + { + if (ics[i]->is_class) + { + if (!ics[i]->nsubs) + { + fprintf (stderr, "Warning: IC:%s", ics[i]->name); + if (ics[i]->comment) + fprintf (stderr, "[%s]", ics[i]->comment); + fprintf (stderr, " has no terminals or sub-classes\n"); + } + } + else + { + if (!ics[i]->terminal_resolved && !ics[i]->orphan) + { + fprintf(stderr, "Warning: no insns mapped directly to " + "terminal IC %s", ics[i]->name); + if (ics[i]->comment) + fprintf(stderr, "[%s] ", ics[i]->comment); + fprintf(stderr, "\n"); + } + } + } + + for (i=0;i < iclen;i++) + { + if (ics[i]->orphan) + { + mark_used (ics[i], 1); + fprintf (stderr, "Warning: class %s is defined but not used\n", + ics[i]->name); + } + } + + if (debug > 1) for (i=0;i < rdepslen;i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + if (rdeps[i]->total_chks == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n", + rdeps[i]->name, mode_str[rdeps[i]->mode], + rdeps[i]->total_regs ? "" : " or regs"); + } + else if (rdeps[i]->total_regs == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n", + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + } + } + + /* the dependencies themselves */ + printf ("static const struct ia64_dependency\ndependencies[] = {\n"); + for (i=0;i < rdepslen;i++) + { + /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual + resource used */ + int specifier = lookup_specifier (rdeps[i]->name); + int regindex = lookup_regindex (rdeps[i]->name, specifier); + + printf (" { \"%s\", %d, %d, %d, %d, ", + rdeps[i]->name, specifier, + (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); + if (rdeps[i]->semantics == IA64_DVS_OTHER) + printf ("\"%s\", ", rdeps[i]->extra); + else + printf ("NULL, "); + printf("},\n"); + } + printf ("};\n\n"); + + /* and dependency lists */ + for (i=0;i < dlistlen;i++) + { + int len = 2; + printf ("static const short dep%d[] = {\n ", i); + for (j=0;j < dlists[i]->len; j++) + { + len += printf ("%d, ", dlists[i]->deps[j]); + if (len > 75) + { + printf("\n "); + len = 2; + } + } + printf ("\n};\n\n"); + } + + /* and opcode dependency list */ + printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); + printf ("static const struct ia64_opcode_dependency\n"); + printf ("op_dependencies[] = {\n"); + for (i=0;i < opdeplen;i++) + { + printf (" { "); + if (opdeps[i]->chk == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); + if (opdeps[i]->reg == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); + printf ("},\n"); + } + printf ("};\n\n"); +} + + +/* Add STR to the string table. */ + +static struct string_entry * +insert_string (str) + char *str; +{ + int start = 0, end = strtablen; + int i, x; + + if (strtablen == strtabtotlen) + { + strtabtotlen += 20; + string_table = (struct string_entry **) + xrealloc (string_table, + sizeof (struct string_entry **) * strtabtotlen); + } + + if (strtablen == 0) + { + strtablen = 1; + string_table[0] = tmalloc (struct string_entry); + string_table[0]->s = xstrdup (str); + string_table[0]->num = 0; + return string_table[0]; + } + + if (strcmp (str, string_table[strtablen - 1]->s) > 0) + { + i = end; + } + else if (strcmp (str, string_table[0]->s) < 0) + { + i = 0; + } + else + { + while (1) + { + int c; + + i = (start + end) / 2; + c = strcmp (str, string_table[i]->s); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return string_table[i]; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + } + for (; i > 0 && i < strtablen; i--) + { + if (strcmp (str, string_table[i - 1]->s) > 0) + { + break; + } + } + for (; i < strtablen; i++) + { + if (strcmp (str, string_table[i]->s) < 0) + { + break; + } + } + for (x = strtablen - 1; x >= i; x--) + { + string_table[x + 1] = string_table[x]; + string_table[x + 1]->num = x + 1; + } + string_table[i] = tmalloc (struct string_entry); + string_table[i]->s = xstrdup (str); + string_table[i]->num = i; + strtablen++; + return string_table[i]; +} + +struct bittree * +make_bittree_entry () +{ + struct bittree *res = tmalloc (struct bittree); + + res->disent = NULL; + res->bits[0] = NULL; + res->bits[1] = NULL; + res->bits[2] = NULL; + res->skip_flag = 0; + res->bits_to_skip = 0; + return res; +} + +struct disent * +add_dis_table_ent (which, insn, order, completer_index) + struct disent *which; + int insn; + int order; + int completer_index; +{ + int ci = 0; + struct disent *ent; + + if (which != NULL) + { + ent = which; + + ent->nextcnt++; + while (ent->nexte != NULL) + { + ent = ent->nexte; + } + ent = (ent->nexte = tmalloc (struct disent)); + } + else + { + ent = tmalloc (struct disent); + ent->next_ent = disinsntable; + disinsntable = ent; + which = ent; + } + ent->nextcnt = 0; + ent->nexte = NULL; + ent->insn = insn; + ent->priority = order; + + while (completer_index != 1) + { + ci = (ci << 1) | (completer_index & 1); + completer_index >>= 1; + } + ent->completer_index = ci; + return which; +} + +void +finish_distable () +{ + struct disent *ent = disinsntable; + struct disent *prev = ent; + + ent->ournum = 32768; + while ((ent = ent->next_ent) != NULL) + { + ent->ournum = prev->ournum + prev->nextcnt + 1; + prev = ent; + } +} + +void +insert_bit_table_ent (curr_ent, bit, opcode, mask, + opcodenum, order, completer_index) + struct bittree *curr_ent; + int bit; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + int order; + int completer_index; +{ + ia64_insn m; + int b; + struct bittree *next; + + if (bit == -1) + { + struct disent *nent = add_dis_table_ent (curr_ent->disent, + opcodenum, order, + completer_index); + curr_ent->disent = nent; + return; + } + + m = ((ia64_insn) 1) << bit; + + if (mask & m) + { + b = (opcode & m) ? 1 : 0; + } + else + { + b = 2; + } + next = curr_ent->bits[b]; + if (next == NULL) + { + next = make_bittree_entry (); + curr_ent->bits[b] = next; + } + insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, + completer_index); +} + +void +add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) + struct bittree *first; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + struct completer_entry *ent; + int completer_index; +{ + if (completer_index & (1 << 20)) + { + abort (); + } + + while (ent != NULL) + { + ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; + add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, + (completer_index << 1) | 1); + if (ent->is_terminal) + { + insert_bit_table_ent (bittree, 40, newopcode, mask, + opcodenum, opcode_count - ent->order - 1, + (completer_index << 1) | 1); + } + completer_index <<= 1; + ent = ent->alternative; + } +} + +/* This optimization pass combines multiple "don't care" nodes. */ +void +compact_distree (ent) + struct bittree *ent; +{ +#define IS_SKIP(ent) \ + ((ent->bits[2] !=NULL) \ + && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) + + int bitcnt = 0; + struct bittree *nent = ent; + int x; + + while (IS_SKIP (nent)) + { + bitcnt++; + nent = nent->bits[2]; + } + + if (bitcnt) + { + struct bittree *next = ent->bits[2]; + + ent->bits[0] = nent->bits[0]; + ent->bits[1] = nent->bits[1]; + ent->bits[2] = nent->bits[2]; + ent->disent = nent->disent; + ent->skip_flag = 1; + ent->bits_to_skip = bitcnt; + while (next != nent) + { + struct bittree *b = next; + next = next->bits[2]; + free (b); + } + free (nent); + } + + for (x = 0; x < 3; x++) + { + struct bittree *i = ent->bits[x]; + if (i != NULL) + { + compact_distree (i); + } + } +} + +static unsigned char *insn_list; +static int insn_list_len = 0; +static int tot_insn_list_len = 0; + +/* Generate the disassembler state machine corresponding to the tree + in ENT. */ +void +gen_dis_table (ent) + struct bittree *ent; +{ + int x; + int our_offset = insn_list_len; + int bitsused = 5; + int totbits = bitsused; + int needed_bytes; + int zero_count = 0; + int zero_dest = 0; /* initialize this with 0 to keep gcc quiet... */ + + /* If this is a terminal entry, there's no point in skipping any + bits. */ + if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && + ent->bits[2] == NULL) + { + if (ent->disent == NULL) + { + abort (); + } + else + { + ent->skip_flag = 0; + } + } + + /* Calculate the amount of space needed for this entry, or at least + a conservatively large approximation. */ + if (ent->skip_flag) + { + totbits += 5; + } + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL) + { + totbits += 16; + } + } + + if (ent->disent != NULL) + { + if (ent->bits[2] != NULL) + { + abort (); + } + totbits += 16; + } + + /* Now allocate the space. */ + needed_bytes = (totbits + 7) / 8; + if ((needed_bytes + insn_list_len) > tot_insn_list_len) + { + tot_insn_list_len += 256; + insn_list = (char *) xrealloc (insn_list, tot_insn_list_len); + } + our_offset = insn_list_len; + insn_list_len += needed_bytes; + memset (insn_list + our_offset, 0, needed_bytes); + + /* Encode the skip entry by setting bit 6 set in the state op field, + and store the # of bits to skip immediately after. */ + if (ent->skip_flag) + { + bitsused += 5; + insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); + insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); + } + +#define IS_ONLY_IFZERO(ENT) \ + ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ + && (ENT)->disent == NULL && (ENT)->skip_flag == 0) + + /* Store an "if (bit is zero)" instruction by setting bit 7 in the + state op field. */ + + if (ent->bits[0] != NULL) + { + struct bittree *nent = ent->bits[0]; + zero_count = 0; + + insn_list[our_offset] |= 0x80; + + /* We can encode sequences of multiple "if (bit is zero)" tests + by storing the # of zero bits to check in the lower 3 bits of + the instruction. However, this only applies if the state + solely tests for a zero bit. */ + + if (IS_ONLY_IFZERO (ent)) + { + while (IS_ONLY_IFZERO (nent) && zero_count < 7) + { + nent = nent->bits[0]; + zero_count++; + } + + insn_list[our_offset + 0] |= zero_count; + } + zero_dest = insn_list_len; + gen_dis_table (nent); + } + + /* Now store the remaining tests. We also handle a sole "termination + entry" by storing it as an "any bit" test. */ + + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) + { + struct bittree *i = ent->bits[x]; + int idest; + int currbits = 15; + + if (i != NULL) + { + /* If the instruction being branched to only consists of + a termination entry, use the termination entry as the + place to branch to instead. */ + if (i->bits[0] == NULL && i->bits[1] == NULL + && i->bits[2] == NULL && i->disent != NULL) + { + idest = i->disent->ournum; + i = NULL; + } + else + { + idest = insn_list_len - our_offset; + } + } + else + { + idest = ent->disent->ournum; + } + + /* If the destination offset for the if (bit is 1) test is less + than 256 bytes away, we can store it as 8-bits instead of 16; + the instruction has bit 5 set for the 16-bit address, and bit + 4 for the 8-bit address. Since we've already allocated 16 + bits for the address we need to deallocate the space. + + Note that branchings within the table are relative, and + there are no branches that branch past our instruction yet + so we do not need to adjust any other offsets. */ + + if (x == 1) + { + if (idest <= 256) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 7; + totbits -= 8; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x10; + idest--; + } + else + { + insn_list[our_offset] |= 0x20; + } + } + else + { + /* An instruction which solely consists of a termination + marker and whose disassembly name index is < 4096 + can be stored in 16 bits. The encoding is slightly + odd; the upper 4 bits of the instruction are 0x3, and + bit 3 loses its normal meaning. */ + + if (ent->bits[0] == NULL && ent->bits[1] == NULL + && ent->bits[2] == NULL && ent->skip_flag == 0 + && ent->disent != NULL + && ent->disent->ournum < (32768 + 4096)) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 11; + totbits -= 5; + bitsused--; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x30; + idest &= ~32768; + } + else + { + insn_list[our_offset] |= 0x08; + } + } + if (debug) + { + int id = idest; + + if (i == NULL) + { + id |= 32768; + } + else if (! (id & 32768)) + { + id += our_offset; + } + if (x == 1) + { + printf ("%d: if (1) goto %d\n", our_offset, id); + } + else + { + printf ("%d: try %d\n", our_offset, id); + } + } + + /* Store the address of the entry being branched to. */ + while (currbits >= 0) + { + char *byte = insn_list + our_offset + bitsused / 8; + + if (idest & (1 << currbits)) + { + *byte |= (1 << (7 - (bitsused % 8))); + } + bitsused++; + currbits--; + } + + /* Now generate the states for the entry being branched to. */ + if (i != NULL) + { + gen_dis_table (i); + } + + } + } + if (debug) + { + if (ent->skip_flag) + { + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); + } + + if (ent->bits[0] != NULL) + { + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); + } + } + if (bitsused != totbits) + { + abort (); + } +} + +void +print_dis_table () +{ + int x; + struct disent *cent = disinsntable; + + printf ("static const char dis_table[] = {\n"); + for (x = 0; x < insn_list_len; x++) + { + if ((x > 0) && ((x % 12) == 0)) + { + printf ("\n"); + } + printf ("0x%02x, ", insn_list[x]); + } + printf ("\n};\n\n"); + + printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); + while (cent != NULL) + { + struct disent *ent = cent; + + while (ent != NULL) + { + printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index, + ent->insn, (ent->nexte != NULL ? 1 : 0), + ent->priority); + ent = ent->nexte; + } + cent = cent->next_ent; + } + printf ("};\n\n"); +} + +void +generate_disassembler () +{ + int i; + + bittree = make_bittree_entry (); + + for (i=0; i < otlen;i++) + { + struct main_entry *ptr = ordered_table[i]; + + if (ptr->opcode->type != IA64_TYPE_DYN) + { + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, + ptr->main_index, + ptr->completers, 1); + } + } + + compact_distree (bittree); + finish_distable (); + gen_dis_table (bittree); + + print_dis_table (); +} + +void +print_string_table () +{ + int x; + char lbuf[80], buf[80]; + int blen = 0; + + printf ("static const char *ia64_strings[] = {\n"); + lbuf[0] = '\0'; + for (x = 0; x < strtablen; x++) + { + int len; + + if (strlen (string_table[x]->s) > 75) + { + abort (); + } + sprintf (buf, " \"%s\",", string_table[x]->s); + len = strlen (buf); + if ((blen + len) > 75) + { + printf (" %s\n", lbuf); + lbuf[0] = '\0'; + blen = 0; + } + strcat (lbuf, buf); + blen += len; + } + if (blen > 0) + { + printf (" %s\n", lbuf); + } + printf ("};\n\n"); +} + +static struct completer_entry **glist; +static int glistlen = 0; +static int glisttotlen = 0; + +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ + +int +completer_entries_eq (ent1, ent2) + struct completer_entry *ent1, *ent2; +{ + while (ent1 != NULL && ent2 != NULL) + { + if (ent1->name->num != ent2->name->num + || ent1->bits != ent2->bits + || ent1->mask != ent2->mask + || ent1->is_terminal != ent2->is_terminal + || ent1->dependencies != ent2->dependencies + || ent1->order != ent2->order) + { + return 0; + } + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) + { + return 0; + } + ent1 = ent1->alternative; + ent2 = ent2->alternative; + } + return ent1 == ent2; +} + +/* Insert ENT into the global list of completers and return it. If an + equivalent entry (according to completer_entries_eq) already exists, + it is returned instead. */ +struct completer_entry * +insert_gclist (ent) + struct completer_entry *ent; +{ + if (ent != NULL) + { + int i; + int x; + int start = 0, end; + + ent->addl_entries = insert_gclist (ent->addl_entries); + ent->alternative = insert_gclist (ent->alternative); + + i = glistlen / 2; + end = glistlen; + + if (glisttotlen == glistlen) + { + glisttotlen += 20; + glist = (struct completer_entry **) + xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); + } + + if (glistlen == 0) + { + glist[0] = ent; + glistlen = 1; + return ent; + } + + if (ent->name->num < glist[0]->name->num) + { + i = 0; + } + else if (ent->name->num > glist[end - 1]->name->num) + { + i = end; + } + else + { + int c; + + while (1) + { + i = (start + end) / 2; + c = ent->name->num - glist[i]->name->num; + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + while (i > 0 + && ent->name->num == glist[i - 1]->name->num) + { + i--; + } + break; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + if (c == 0) + { + while (i < glistlen) + { + if (ent->name->num != glist[i]->name->num) + { + break; + } + if (completer_entries_eq (ent, glist[i])) + { + return glist[i]; + } + i++; + } + } + } + for (; i > 0 && i < glistlen; i--) + { + if (ent->name->num >= glist[i - 1]->name->num) + { + break; + } + } + for (; i < glistlen; i++) + { + if (ent->name->num < glist[i]->name->num) + { + break; + } + } + for (x = glistlen - 1; x >= i; x--) + { + glist[x + 1] = glist[x]; + } + glist[i] = ent; + glistlen++; + } + return ent; +} + +static int +get_prefix_len (name) + const char *name; +{ + char *c; + + if (name[0] == '\0') + { + return 0; + } + + c = strchr (name, '.'); + if (c != NULL) + { + return c - name; + } + else + { + return strlen (name); + } +} + +static void +compute_completer_bits (ment, ent) + struct main_entry *ment; + struct completer_entry *ent; +{ + while (ent != NULL) + { + compute_completer_bits (ment, ent->addl_entries); + + if (ent->is_terminal) + { + ia64_insn mask = 0; + ia64_insn our_bits = ent->bits; + struct completer_entry *p = ent->parent; + ia64_insn p_bits; + int x; + + while (p != NULL && ! p->is_terminal) + { + p = p->parent; + } + + if (p != NULL) + { + p_bits = p->bits; + } + else + { + p_bits = ment->opcode->opcode; + } + + for (x = 0; x < 64; x++) + { + ia64_insn m = ((ia64_insn) 1) << x; + if ((p_bits & m) != (our_bits & m)) + { + mask |= m; + } + else + { + our_bits &= ~m; + } + } + ent->bits = our_bits; + ent->mask = mask; + } + else + { + ent->bits = 0; + ent->mask = 0; + } + + ent = ent->alternative; + } +} + +/* Find identical completer trees that are used in different + instructions and collapse their entries. */ +void +collapse_redundant_completers () +{ + struct main_entry *ptr; + int x; + + for (ptr = maintable; ptr != NULL; ptr = ptr->next) + { + if (ptr->completers == NULL) + { + abort (); + } + compute_completer_bits (ptr, ptr->completers); + ptr->completers = insert_gclist (ptr->completers); + } + + /* The table has been finalized, now number the indexes. */ + for (x = 0; x < glistlen; x++) + { + glist[x]->num = x; + } +} + + +/* attach two lists of dependencies to each opcode. + 1) all resources which, when already marked in use, conflict with this + opcode (chks) + 2) all resources which must be marked in use when this opcode is used + (regs) +*/ +int +insert_opcode_dependencies (opc, cmp) + struct ia64_opcode *opc; + struct completer_entry *cmp ATTRIBUTE_UNUSED; +{ + /* note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough */ + int i; + int nregs = 0; + unsigned short regs[256]; + int nchks = 0; + unsigned short chks[256]; + /* flag insns for which no class matched; there should be none */ + int no_class_found = 1; + + for (i=0;i < rdepslen;i++) + { + struct rdep *rs = rdeps[i]; + int j; + + if (strcmp (opc->name, "cmp.eq.and") == 0 + && strncmp (rs->name, "PR%", 3) == 0 + && rs->mode == 1) + no_class_found = 99; + + for (j=0; j < rs->nregs;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->regnotes[j] != 0 + && ic_note != rs->regnotes[j] + && !(ic_note == 11 && rs->regnotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); + /* Instruction class notes override resource notes. + So far, only note 11 applies to an IC instead of a resource, + and note 11 implies note 1. + */ + if (ic_note) + regs[nregs++] = RDEP(ic_note, i); + else + regs[nregs++] = RDEP(rs->regnotes[j], i); + no_class_found = 0; + ++rs->total_regs; + } + } + for (j=0;j < rs->nchks;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->chknotes[j] != 0 + && ic_note != rs->chknotes[j] + && !(ic_note == 11 && rs->chknotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); + if (ic_note) + chks[nchks++] = RDEP(ic_note, i); + else + chks[nchks++] = RDEP(rs->chknotes[j], i); + no_class_found = 0; + ++rs->total_chks; + } + } + } + + if (no_class_found) + fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n", + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); + + return insert_dependencies (nchks, chks, nregs, regs); +} + +void +insert_completer_entry (opc, tabent, order) + struct ia64_opcode *opc; + struct main_entry *tabent; + int order; +{ + struct completer_entry **ptr = &tabent->completers; + struct completer_entry *parent = NULL; + char pcopy[129], *prefix; + int at_end = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + strcpy (pcopy, opc->name); + prefix = pcopy + get_prefix_len (pcopy); + if (prefix[0] != '\0') + { + prefix++; + } + + while (! at_end) + { + int need_new_ent = 1; + int plen = get_prefix_len (prefix); + struct string_entry *sent; + + at_end = (prefix[plen] == '\0'); + prefix[plen] = '\0'; + sent = insert_string (prefix); + + while (*ptr != NULL) + { + int cmpres = sent->num - (*ptr)->name->num; + + if (cmpres == 0) + { + need_new_ent = 0; + break; + } + else + { + ptr = &((*ptr)->alternative); + } + } + if (need_new_ent) + { + struct completer_entry *nent = tmalloc (struct completer_entry); + nent->name = sent; + nent->parent = parent; + nent->addl_entries = NULL; + nent->alternative = *ptr; + *ptr = nent; + nent->is_terminal = 0; + nent->dependencies = -1; + } + + if (! at_end) + { + parent = *ptr; + ptr = &((*ptr)->addl_entries); + prefix += plen + 1; + } + } + + if ((*ptr)->is_terminal) + { + abort (); + } + + (*ptr)->is_terminal = 1; + (*ptr)->mask = (ia64_insn)-1; + (*ptr)->bits = opc->opcode; + (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); + (*ptr)->order = order; +} + +void +print_completer_entry (ent) + struct completer_entry *ent; +{ + int moffset = 0; + ia64_insn mask = ent->mask, bits = ent->bits; + + if (mask != 0) + { + while (! (mask & 1)) + { + moffset++; + mask = mask >> 1; + bits = bits >> 1; + } + if (bits & 0xffffffff00000000LL) + { + abort (); + } + } + + printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", + (int)bits, + (int)mask, + ent->name->num, + ent->alternative != NULL ? ent->alternative->num : -1, + ent->addl_entries != NULL ? ent->addl_entries->num : -1, + moffset, + ent->is_terminal ? 1 : 0, + ent->dependencies); +} + +void +print_completer_table () +{ + int x; + + printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); + for (x = 0; x < glistlen; x++) + { + print_completer_entry (glist[x]); + } + printf ("};\n\n"); +} + +int +opcodes_eq (opc1, opc2) + struct ia64_opcode *opc1; + struct ia64_opcode *opc2; +{ + int x; + int plen1, plen2; + + if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) + || (opc1->num_outputs != opc2->num_outputs) + || (opc1->flags != opc2->flags)) + { + return 0; + } + for (x = 0; x < 5; x++) + { + if (opc1->operands[x] != opc2->operands[x]) + { + return 0; + } + } + plen1 = get_prefix_len (opc1->name); + plen2 = get_prefix_len (opc2->name); + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) + { + return 1; + } + return 0; +} + +void +add_opcode_entry (opc) + struct ia64_opcode *opc; +{ + struct main_entry **place; + struct string_entry *name; + char prefix[129]; + int found_it = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + place = &maintable; + strcpy (prefix, opc->name); + prefix[get_prefix_len (prefix)] = '\0'; + name = insert_string (prefix); + + /* Walk the list of opcode table entries. If it's a new + instruction, allocate and fill in a new entry. Note + the main table is alphabetical by opcode name. */ + + while (*place != NULL) + { + if ((*place)->name->num == name->num + && opcodes_eq ((*place)->opcode, opc)) + { + found_it = 1; + break; + } + if ((*place)->name->num > name->num) + { + break; + } + place = &((*place)->next); + } + if (! found_it) + { + struct main_entry *nent = tmalloc (struct main_entry); + + nent->name = name; + nent->opcode = opc; + nent->next = *place; + nent->completers = 0; + *place = nent; + + if (otlen == ottotlen) + { + ottotlen += 20; + ordered_table = (struct main_entry **) + xrealloc (ordered_table, sizeof (struct main_entry *) * ottotlen); + } + ordered_table[otlen++] = nent; + } + + insert_completer_entry (opc, *place, opcode_count++); +} + +void +print_main_table () +{ + struct main_entry *ptr = maintable; + int index = 0; + + printf ("static const struct ia64_main_table\nmain_table[] = {\n"); + while (ptr != NULL) + { + printf (" { %d, %d, %d, 0x", + ptr->name->num, + ptr->opcode->type, + ptr->opcode->num_outputs); + fprintf_vma (stdout, ptr->opcode->opcode); + printf ("ull, 0x"); + fprintf_vma (stdout, ptr->opcode->mask); + printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + ptr->opcode->operands[0], + ptr->opcode->operands[1], + ptr->opcode->operands[2], + ptr->opcode->operands[3], + ptr->opcode->operands[4], + ptr->opcode->flags, + ptr->completers->num); + + ptr->main_index = index++; + + ptr = ptr->next; + } + printf ("};\n\n"); +} + +void +shrink (table) + struct ia64_opcode *table; +{ + int curr_opcode; + + for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) + { + add_opcode_entry (table + curr_opcode); + } +} + +int +main (argc, argv) + int argc; + char **argv ATTRIBUTE_UNUSED; +{ + if (argc > 1) + { + debug = 1; + } + + load_insn_classes(); + load_dependencies(); + + shrink (ia64_opcodes_a); + shrink (ia64_opcodes_b); + shrink (ia64_opcodes_f); + shrink (ia64_opcodes_i); + shrink (ia64_opcodes_m); + shrink (ia64_opcodes_x); + shrink (ia64_opcodes_d); + + collapse_redundant_completers (); + + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + print_string_table (); + print_dependency_table (); + print_completer_table (); + print_main_table (); + + generate_disassembler (); + + exit (0); +} diff --git a/gnu/usr.bin/binutils/opcodes/ia64-ic.tbl b/gnu/usr.bin/binutils/opcodes/ia64-ic.tbl new file mode 100644 index 00000000000..115a2763d41 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-ic.tbl @@ -0,0 +1,234 @@ +Class; Events/Instructions +all; IC:predicatable-instructions, IC:unpredicatable-instructions +branches; IC:indirect-brs, IC:ip-rel-brs +cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e +chk-a; chk.a.clr, chk.a.nc +cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8 +czx; czx1, czx2 +fcmp-s0; fcmp[Field(sf)==s0] +fcmp-s1; fcmp[Field(sf)==s1] +fcmp-s2; fcmp[Field(sf)==s2] +fcmp-s3; fcmp[Field(sf)==s3] +fetchadd; fetchadd4, fetchadd8 +fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub +fp-arith-s0; IC:fp-arith[Field(sf)==s0] +fp-arith-s1; IC:fp-arith[Field(sf)==s1] +fp-arith-s2; IC:fp-arith[Field(sf)==s2] +fp-arith-s3; IC:fp-arith[Field(sf)==s3] +fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma +fpcmp-s0; fpcmp[Field(sf)==s0] +fpcmp-s1; fpcmp[Field(sf)==s1] +fpcmp-s2; fpcmp[Field(sf)==s2] +fpcmp-s3; fpcmp[Field(sf)==s3] +fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf +fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf +gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat +gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt +gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl +indirect-brp; brp[Format in {B7}] +indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret +invala-all; invala[Format in {M24}], invala.e +ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop +ld; ld1, ld2, ld4, ld8, ld8.fill +ld-a; ld1.a, ld2.a, ld4.a, ld8.a +ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] +ld-c; IC:ld-c-nc, IC:ld-c-clr +ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq +ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq +ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc +ld-s; ld1.s, ld2.s, ld4.s, ld8.s +ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa +ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill +ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a +ldf-c; IC:ldf-c-nc, IC:ldf-c-clr +ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr +ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc +ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s +ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa +ldfp; ldfps, ldfpd, ldfp8 +ldfp-a; ldfps.a, ldfpd.a, ldfp8.a +ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr +ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr +ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc +ldfp-s; ldfps.s, ldfpd.s, ldfp8.s +ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa +lfetch-all; lfetch +lfetch-fault; lfetch[Field(lftype)==fault] +lfetch-nofault; lfetch[Field(lftype)==] +lfetch-postinc; lfetch[Format in {M14 M15}] +mem-readers; IC:mem-readers-fp, IC:mem-readers-int +mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c +mem-readers-fp; IC:ldf, IC:ldfp +mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld +mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa +mem-writers; IC:mem-writers-fp, IC:mem-writers-int +mem-writers-fp; IC:stf +mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st +mix; mix1, mix2, mix4 +mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop +mod-sched-brs-counted; br.cexit, br.cloop, br.ctop +mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM +mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] +mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] +mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] +mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] +mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] +mov-from-AR-I; mov_ar[Format in {I28}] +mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] +mov-from-AR-IM; mov_ar[Format in {I28 M31}] +mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC] +mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC] +mov-from-AR-M; mov_ar[Format in {M31}] +mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] +mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] +mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] +mov-from-AR-rv; IC:none +mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] +mov-from-BR; mov_br[Format in {I22}] +mov-from-CR; mov_cr[Format in {M33}] +mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV] +mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR] +mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI] +mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA] +mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA] +mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS] +mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA] +mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM] +mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP] +mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA] +mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR] +mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR] +mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR] +mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM] +mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV] +mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA] +mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR] +mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID] +mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] +mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV] +mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA] +mov-from-CR-rv; IC:none +mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR] +mov-from-IND; mov_indirect[Format in {M43}] +mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid] +mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr] +mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr] +mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr] +mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr] +mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc] +mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd] +mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}] +mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr] +mov-from-PR; mov_pr[Format in {I25}] +mov-from-PSR; mov_psr[Format in {M36}] +mov-from-PSR-um; mov_um[Format in {M36}] +mov-ip; mov_ip[Format in {I25}] +mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I +mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] +mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] +mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] +mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] +mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] +mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] +mov-to-AR-I; mov_ar[Format in {I26 I27}] +mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] +mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] +mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC] +mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC] +mov-to-AR-M; mov_ar[Format in {M29 M30}] +mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] +mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] +mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] +mov-to-BR; mov_br[Format in {I21}] +mov-to-CR; mov_cr[Format in {M32}] +mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV] +mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR] +mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI] +mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA] +mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA] +mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS] +mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA] +mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM] +mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP] +mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA] +mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR] +mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR] +mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR] +mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM] +mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV] +mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA] +mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR] +mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID] +mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] +mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV] +mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA] +mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR] +mov-to-IND; mov_indirect[Format in {M42}] +mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid] +mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr] +mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr] +mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr] +mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr] +mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc] +mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd] +mov-to-IND-priv; IC:mov-to-IND +mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr] +mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg +mov-to-PR-allreg; mov_pr[Format in {I23}] +mov-to-PR-rotreg; mov_pr[Format in {I24}] +mov-to-PSR-l; mov_psr[Format in {M35}] +mov-to-PSR-um; mov_um[Format in {M35}] +mux; mux1, mux2 +none; - +pack; pack2, pack4 +padd; padd1, padd2, padd4 +pavg; pavg1, pavg2 +pavgsub; pavgsub1, pavgsub2 +pcmp; pcmp1, pcmp2, pcmp4 +pmax; pmax1, pmax2 +pmin; pmin1, pmin2 +pmpy; pmpy2 +pmpyshr; pmpyshr2 +pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-gen-writers-fp; fclass, fcmp +pr-gen-writers-int; cmp, cmp4, tbit, tnat +pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] +pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] +pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, nop.b, IC:ReservedBQP +pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt +pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11 +pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11 +pr-writers; IC:pr-writers-int, IC:pr-writers-fp +pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp +pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-writers, IC:pr-or-writers +predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br, IC:pr-readers-nobr-nomovpr +priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa +probe-all; IC:probe-fault, IC:probe-nofault +probe-fault; probe[Format in {M40}] +probe-nofault; probe[Format in {M38 M39}] +psad; psad1 +pshl; pshl2, pshl4 +pshladd; pshladd2 +pshr; pshr2, pshr4 +pshradd; pshradd2 +psub; psub1, psub2, psub4 +ReservedBQP; -+15 +ReservedQP; -+16 +rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi +rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi +st; st1, st2, st4, st8, st8.spill +st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] +stf; stfs, stfd, stfe, stf8, stf.spill +sxt; sxt1, sxt2, sxt4 +sys-mask-writers-partial; rsm, ssm +unpack; unpack1, unpack2, unpack4 +unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi +user-mask-writers-partial; rum, sum +xchg; xchg1, xchg2, xchg4, xchg8 +zxt; zxt1, zxt2, zxt4 diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-a.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-a.c new file mode 100644 index 00000000000..27d7637f1a2 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-a.c @@ -0,0 +1,412 @@ +/* ia64-opc-a.c -- IA-64 `A' opcode table. + Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define A IA64_TYPE_A, 1 +#define A2 IA64_TYPE_A, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ + (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ + (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) +#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) +#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mImm14 bImm14 (-1) +#define mR3a bR3a (-1) +#define mR3b bR3b (-1) +#define mTa bTa (-1) +#define mTb bTb (-1) +#define mVe bVe (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX4 bX4 (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) +#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ + (mOp | mX2a | mVe) +#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ + (mOp | mX2a | mVe | mR3a) +#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ + (mOp | mX2a | mVe | mImm14) +#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ + (mOp | mX2a | mVe | mX4) +#define OpX2aVeX4X2b(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ + (mOp | mX2a | mVe | mX4 | mX2b) +#define OpX2TbTaC(a,b,c,d,e) \ + (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ + (mOp | mX2 | mTb | mTa | mC) +#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ + (mOp | mX2 | mTa | mC) +#define OpX2aZaZbX4(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ + (mOp | mX2a | mZa | mZb | mX4) +#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ + (mOp | mX2a | mZa | mZb | mX4 | mX2b) + +struct ia64_opcode ia64_opcodes_a[] = + { + /* A-type instruction encodings (sorted according to major opcode) */ + + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}}, + {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO}, + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}}, + + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO}, + {"addl", A, Op (9), {R1, IMM22, R3_2}}, + + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + + {0} + }; + +#undef A +#undef A2 +#undef bC +#undef bImm14 +#undef bR3a +#undef bR3b +#undef bTa +#undef bTb +#undef bVe +#undef bX +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX4 +#undef bZa +#undef bZb +#undef mC +#undef mImm14 +#undef mR3a +#undef mR3b +#undef mTa +#undef mTb +#undef mVe +#undef mX +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX4 +#undef mZa +#undef mZb +#undef OpR3a +#undef OpR3b +#undef OpX2aVe +#undef OpX2aVeImm14 +#undef OpX2aVeX4 +#undef OpX2aVeX4X2b +#undef OpX2TbTaC +#undef OpX2TaC +#undef OpX2aZaZbX4 +#undef OpX2aZaZbX4X2b diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-b.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-b.c new file mode 100644 index 00000000000..9772b37f276 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-b.c @@ -0,0 +1,489 @@ +/* ia64-opc-b.c -- IA-64 `B' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define B0 IA64_TYPE_B, 0 +#define B IA64_TYPE_B, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mIh bIh (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mWha bWha (-1) +#define mWhb bWhb (-1) +#define mX6 bX6 (-1) + +#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) +#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD) +#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) +#define OpIhWhb(a,b,c) \ + (bOp (a) | bIh (b) | bWhb (c)), \ + (mOp | mIh | mWhb) +#define OpX6IhWhb(a,b,c,d) \ + (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ + (mOp | mX6 | mIh | mWhb) + +struct ia64_opcode ia64_opcodes_b[] = + { + /* B-type instruction encodings (sorted according to major opcode) */ + +#define BR(a,b) \ + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2} + {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO}, + {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, + {"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO}, + {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO}, + {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, + {"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO}, + {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO}, + {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, + {"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO}, + {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO}, + {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, + {"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO}, + {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, + {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, + {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, + {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, + {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, + {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, + {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, + {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, + {"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS}, + {"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS}, + {"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS}, + {"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS}, + {"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS}, + {"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS}, + {"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS}, + {"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS}, + {"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS}, + {"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS}, + {"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS}, + {"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS}, + {"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS}, + {"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS}, + {"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS}, + {"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS}, +#undef BR + + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED}, + + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}}, + + {"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}}, + {"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}}, + {"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}}, + {"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}}, + {"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}}, + {"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}}, + {"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}}, + {"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}}, + {"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}}, + {"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}}, + {"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}}, + {"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}}, + +#define BRP(a,b,c) \ + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED + {"brp.sptk", BRP (0x10, 0, 0)}, + {"brp.dptk", BRP (0x10, 0, 2)}, + {"brp.sptk.imp", BRP (0x10, 1, 0)}, + {"brp.dptk.imp", BRP (0x10, 1, 2)}, + {"brp.ret.sptk", BRP (0x11, 0, 0)}, + {"brp.ret.dptk", BRP (0x11, 0, 2)}, + {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, + {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, +#undef BRP + + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}}, + +#define BR(a,b) \ + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c} + {"br.cond.sptk.few", BR (0, 0, 0)}, + {"br.cond.sptk", BR (0, 0, 0), PSEUDO}, + {"br.cond.sptk.few.clr", BR (0, 0, 1)}, + {"br.cond.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.cond.spnt.few", BR (0, 1, 0)}, + {"br.cond.spnt", BR (0, 1, 0), PSEUDO}, + {"br.cond.spnt.few.clr", BR (0, 1, 1)}, + {"br.cond.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.cond.dptk.few", BR (0, 2, 0)}, + {"br.cond.dptk", BR (0, 2, 0), PSEUDO}, + {"br.cond.dptk.few.clr", BR (0, 2, 1)}, + {"br.cond.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.cond.dpnt.few", BR (0, 3, 0)}, + {"br.cond.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, + {"br.cond.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.cond.sptk.many", BR (1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (1, 0, 1)}, + {"br.cond.spnt.many", BR (1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (1, 1, 1)}, + {"br.cond.dptk.many", BR (1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (1, 2, 1)}, + {"br.cond.dpnt.many", BR (1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, + {"br.sptk.few", BR (0, 0, 0)}, + {"br.sptk", BR (0, 0, 0), PSEUDO}, + {"br.sptk.few.clr", BR (0, 0, 1)}, + {"br.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.spnt.few", BR (0, 1, 0)}, + {"br.spnt", BR (0, 1, 0), PSEUDO}, + {"br.spnt.few.clr", BR (0, 1, 1)}, + {"br.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.dptk.few", BR (0, 2, 0)}, + {"br.dptk", BR (0, 2, 0), PSEUDO}, + {"br.dptk.few.clr", BR (0, 2, 1)}, + {"br.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.dpnt.few", BR (0, 3, 0)}, + {"br.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.dpnt.few.clr", BR (0, 3, 1)}, + {"br.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.sptk.many", BR (1, 0, 0)}, + {"br.sptk.many.clr", BR (1, 0, 1)}, + {"br.spnt.many", BR (1, 1, 0)}, + {"br.spnt.many.clr", BR (1, 1, 1)}, + {"br.dptk.many", BR (1, 2, 0)}, + {"br.dptk.many.clr", BR (1, 2, 1)}, + {"br.dpnt.many", BR (1, 3, 0)}, + {"br.dpnt.many.clr", BR (1, 3, 1)}, +#undef BR + +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED + {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, + {"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO}, + {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, + {"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO}, + {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, + {"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO}, + {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, + {"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO}, + {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, + {"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO}, + {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, + {"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO}, + {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, + {"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO}, + {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, + {"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO}, + {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, + {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, + {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, + {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, + {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, + {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, + {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, + {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, + {"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS}, + {"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS}, + {"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS}, + {"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS}, + {"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS}, + {"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS}, + {"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS}, + {"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS}, + {"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS}, + {"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS}, + {"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS}, + {"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS}, + {"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS}, + {"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS}, + {"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS}, + {"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}}, +#undef BR + + /* branch predict */ +#define BRP(a,b) \ + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED + {"brp.sptk", BRP (0, 0)}, + {"brp.loop", BRP (0, 1)}, + {"brp.dptk", BRP (0, 2)}, + {"brp.exit", BRP (0, 3)}, + {"brp.sptk.imp", BRP (1, 0)}, + {"brp.loop.imp", BRP (1, 1)}, + {"brp.dptk.imp", BRP (1, 2)}, + {"brp.exit.imp", BRP (1, 3)}, +#undef BRP + + {0} + }; + +#undef B0 +#undef B +#undef bBtype +#undef bD +#undef bIh +#undef bPa +#undef bPr +#undef bWha +#undef bWhb +#undef bX6 +#undef mBtype +#undef mD +#undef mIh +#undef mPa +#undef mPr +#undef mWha +#undef mWhb +#undef mX6 +#undef OpX6 +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr +#undef OpX6BtypePaWhaD +#undef OpX6BtypePaWhaDPr +#undef OpIhWhb +#undef OpX6IhWhb diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-d.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-d.c new file mode 100644 index 00000000000..27390f59f2e --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-d.c @@ -0,0 +1,14 @@ +struct ia64_opcode ia64_opcodes_d[] = + { + {"add", IA64_TYPE_DYN, 1, 0, 0, + {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}}, + {"add", IA64_TYPE_DYN, 1, 0, 0, + {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {0} + }; diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-f.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-f.c new file mode 100644 index 00000000000..2f898c64d5c --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-f.c @@ -0,0 +1,646 @@ +/* ia64-opc-f.c -- IA-64 `F' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define f0 IA64_TYPE_F, 0 +#define f IA64_TYPE_F, 1 +#define f2 IA64_TYPE_F, 2 + +#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) +#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) +#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mF2 bF2 (-1) +#define mF4 bF4 (-1) +#define mQ bQ (-1) +#define mRa bRa (-1) +#define mRb bRb (-1) +#define mSf bSf (-1) +#define mTa bTa (-1) +#define mXa bXa (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX6 bX6 (-1) + +#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) +#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) +#define OpXaSfF2(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) +#define OpXaSfF4(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) +#define OpXaSfF2F4(a,b,c,d,e) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ + (mOp | mXa | mSf | mF2 | mF4) +#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) +#define OpXaX2F2(a,b,c,d) \ + (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) +#define OpRaRbTaSf(a,b,c,d,e) \ + (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ + (mOp | mRa | mRb | mTa | mSf) +#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) +#define OpXbQSf(a,b,c,d) \ + (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) +#define OpXbX6(a,b,c) \ + (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6F2(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) +#define OpXbX6Sf(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) + +struct ia64_opcode ia64_opcodes_f[] = + { + /* F-type instruction encodings (sorted according to major opcode) */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}}, + {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}}, + + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}}, + {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}}, + {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}}, + + /* pseudo-ops of the above */ + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO}, + + /* note: fnorm and fcvt.xuf have identical encodings! */ + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}}, + + {0} + }; + +#undef f0 +#undef f +#undef f2 +#undef bF2 +#undef bF4 +#undef bQ +#undef bRa +#undef bRb +#undef bSf +#undef bTa +#undef bXa +#undef bXb +#undef bX2 +#undef bX6 +#undef mF2 +#undef mF4 +#undef mQ +#undef mRa +#undef mRb +#undef mSf +#undef mTa +#undef mXa +#undef mXb +#undef mX2 +#undef mX6 +#undef OpXa +#undef OpXaSf +#undef OpXaSfF2 +#undef OpXaSfF4 +#undef OpXaSfF2F4 +#undef OpXaX2 +#undef OpRaRbTaSf +#undef OpTa +#undef OpXbQSf +#undef OpXbX6 +#undef OpXbX6F2 +#undef OpXbX6Sf diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-i.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-i.c new file mode 100644 index 00000000000..899e65181ce --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-i.c @@ -0,0 +1,296 @@ +/* ia64-opc-i.c -- IA-64 `I' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define I0 IA64_TYPE_I, 0 +#define I IA64_TYPE_I, 1 +#define I2 IA64_TYPE_I, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) +#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) +#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) +#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mIh bIh (-1) +#define mTa bTa (-1) +#define mTag13 bTag13 (-1) +#define mTb bTb (-1) +#define mVc bVc (-1) +#define mVe bVe (-1) +#define mWh bWh (-1) +#define mX bX (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX2c bX2c (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mYa bYa (-1) +#define mYb bYb (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b) +#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) +#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) +#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ + (mOp | mX2 | mX | mYa) +#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ + (mOp | mX2 | mX | mYb) +#define OpX2TaTbYaC(a,b,c,d,e,f) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ + (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3XbIhWh(a,b,c,d,e) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ + (mOp | mX3 | mXb | mIh | mWh) +#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ + (mOp | mX3 | mXb | mIh | mWh | mTag13) + +struct ia64_opcode ia64_opcodes_i[] = + { + /* I-type instruction encodings (sorted according to major opcode) */ + + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX}, + {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}}, + + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO}, +#define MOV(a,b,c,d) \ + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b} + {"mov.sptk", MOV (7, 0, 0, 0)}, + {"mov.sptk.imp", MOV (7, 0, 1, 0)}, + {"mov", MOV (7, 0, 0, 1)}, + {"mov.imp", MOV (7, 0, 1, 1)}, + {"mov.dptk", MOV (7, 0, 0, 2)}, + {"mov.dptk.imp", MOV (7, 0, 1, 2)}, + {"mov.ret.sptk", MOV (7, 1, 0, 0)}, + {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, + {"mov.ret", MOV (7, 1, 0, 1)}, + {"mov.ret.imp", MOV (7, 1, 1, 1)}, + {"mov.ret.dptk", MOV (7, 1, 0, 2)}, + {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, +#undef MOV + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}}, + + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}}, + + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}}, + + {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}}, + + {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}}, + + {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, + PSEUDO | LEN_EQ_64MCNT}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}}, +#define TBIT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6} +#define TBITCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO + {"tbit.z", TBIT (0, 0, 0, 0)}, + {"tbit.nz", TBITCM (0, 0, 0, 0)}, + {"tbit.z.unc", TBIT (0, 0, 0, 1)}, + {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, + {"tbit.z.and", TBIT (0, 1, 0, 0)}, + {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, + {"tbit.nz.and", TBIT (0, 1, 0, 1)}, + {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, + {"tbit.z.or", TBIT (1, 0, 0, 0)}, + {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, + {"tbit.nz.or", TBIT (1, 0, 0, 1)}, + {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, + {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, + {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, + {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, + {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, +#undef TBIT +#define TNAT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3} +#define TNATCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO + {"tnat.z", TNAT (0, 0, 1, 0)}, + {"tnat.nz", TNATCM (0, 0, 1, 0)}, + {"tnat.z.unc", TNAT (0, 0, 1, 1)}, + {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, + {"tnat.z.and", TNAT (0, 1, 1, 0)}, + {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, + {"tnat.nz.and", TNAT (0, 1, 1, 1)}, + {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, + {"tnat.z.or", TNAT (1, 0, 1, 0)}, + {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, + {"tnat.nz.or", TNAT (1, 0, 1, 1)}, + {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, + {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, + {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, + {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, + {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, +#undef TNAT + + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}}, + + {0} + }; + +#undef I0 +#undef I +#undef I2 +#undef L +#undef bC +#undef bIh +#undef bTa +#undef bTag13 +#undef bTb +#undef bVc +#undef bVe +#undef bWh +#undef bX +#undef bXb +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX2c +#undef bX3 +#undef bX6 +#undef bY +#undef bZa +#undef bZb +#undef mC +#undef mIh +#undef mTa +#undef mTag13 +#undef mTb +#undef mVc +#undef mVe +#undef mWh +#undef mX +#undef mXb +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX2c +#undef mX3 +#undef mX6 +#undef mY +#undef mZa +#undef mZb +#undef OpZaZbVeX2aX2b +#undef OpZaZbVeX2aX2bX2c +#undef OpX2X +#undef OpX2XYa +#undef OpX2XYb +#undef OpX2TaTbYaC +#undef OpX3 +#undef OpX3X6 +#undef OpX3XbIhWh +#undef OpX3XbIhWhTag13 diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-m.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-m.c new file mode 100644 index 00000000000..bc098160a4b --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-m.c @@ -0,0 +1,1060 @@ +/* ia64-opc-m.c -- IA-64 `M' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define M0 IA64_TYPE_M, 0 +#define M IA64_TYPE_M, 1 +#define M2 IA64_TYPE_M, 2 + +/* instruction bit fields: */ +#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) +#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) +#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) + +#define mM bM (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX3 bX3 (-1) +#define mX4 bX4 (-1) +#define mX6a bX6a (-1) +#define mX6b bX6b (-1) +#define mHint bHint (-1) + +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ + (mOp | mX3 | mX6b) +#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ + (mOp | mX3 | mX4) +#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ + (mOp | mX3 | mX4 | mX2) +#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ + (mOp | mX6a | mHint) +#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ + (mOp | mX | mX6a | mHint) +#define OpMXX6a(a,b,c,d) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) +#define OpMXX6aHint(a,b,c,d,e) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ + (mOp | mM | mX | mX6a | mHint) + +struct ia64_opcode ia64_opcodes_m[] = + { + /* M-type instruction encodings (sorted according to major opcode) */ + + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}}, + + {"invala", M0, OpX3X4X2 (0, 0, 0, 1)}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2)}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2)}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2)}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3)}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3)}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3)}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}}, + + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}}, + {"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}}, + + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV}, + + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV}, + + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS}, + + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}}, + + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV}, + + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV}, + + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}}, + + {"fc", M0, OpX3X6b (1, 0, 0x30), {R3}}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV}, + + /* integer load */ + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}}, + + /* integer load w/increment by register */ +#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, + {"ld1", LDINCREG (0x00, 0)}, + {"ld1.nt1", LDINCREG (0x00, 1)}, + {"ld1.nta", LDINCREG (0x00, 3)}, + {"ld2", LDINCREG (0x01, 0)}, + {"ld2.nt1", LDINCREG (0x01, 1)}, + {"ld2.nta", LDINCREG (0x01, 3)}, + {"ld4", LDINCREG (0x02, 0)}, + {"ld4.nt1", LDINCREG (0x02, 1)}, + {"ld4.nta", LDINCREG (0x02, 3)}, + {"ld8", LDINCREG (0x03, 0)}, + {"ld8.nt1", LDINCREG (0x03, 1)}, + {"ld8.nta", LDINCREG (0x03, 3)}, + {"ld1.s", LDINCREG (0x04, 0)}, + {"ld1.s.nt1", LDINCREG (0x04, 1)}, + {"ld1.s.nta", LDINCREG (0x04, 3)}, + {"ld2.s", LDINCREG (0x05, 0)}, + {"ld2.s.nt1", LDINCREG (0x05, 1)}, + {"ld2.s.nta", LDINCREG (0x05, 3)}, + {"ld4.s", LDINCREG (0x06, 0)}, + {"ld4.s.nt1", LDINCREG (0x06, 1)}, + {"ld4.s.nta", LDINCREG (0x06, 3)}, + {"ld8.s", LDINCREG (0x07, 0)}, + {"ld8.s.nt1", LDINCREG (0x07, 1)}, + {"ld8.s.nta", LDINCREG (0x07, 3)}, + {"ld1.a", LDINCREG (0x08, 0)}, + {"ld1.a.nt1", LDINCREG (0x08, 1)}, + {"ld1.a.nta", LDINCREG (0x08, 3)}, + {"ld2.a", LDINCREG (0x09, 0)}, + {"ld2.a.nt1", LDINCREG (0x09, 1)}, + {"ld2.a.nta", LDINCREG (0x09, 3)}, + {"ld4.a", LDINCREG (0x0a, 0)}, + {"ld4.a.nt1", LDINCREG (0x0a, 1)}, + {"ld4.a.nta", LDINCREG (0x0a, 3)}, + {"ld8.a", LDINCREG (0x0b, 0)}, + {"ld8.a.nt1", LDINCREG (0x0b, 1)}, + {"ld8.a.nta", LDINCREG (0x0b, 3)}, + {"ld1.sa", LDINCREG (0x0c, 0)}, + {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, + {"ld1.sa.nta", LDINCREG (0x0c, 3)}, + {"ld2.sa", LDINCREG (0x0d, 0)}, + {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, + {"ld2.sa.nta", LDINCREG (0x0d, 3)}, + {"ld4.sa", LDINCREG (0x0e, 0)}, + {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, + {"ld4.sa.nta", LDINCREG (0x0e, 3)}, + {"ld8.sa", LDINCREG (0x0f, 0)}, + {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, + {"ld8.sa.nta", LDINCREG (0x0f, 3)}, + {"ld1.bias", LDINCREG (0x10, 0)}, + {"ld1.bias.nt1", LDINCREG (0x10, 1)}, + {"ld1.bias.nta", LDINCREG (0x10, 3)}, + {"ld2.bias", LDINCREG (0x11, 0)}, + {"ld2.bias.nt1", LDINCREG (0x11, 1)}, + {"ld2.bias.nta", LDINCREG (0x11, 3)}, + {"ld4.bias", LDINCREG (0x12, 0)}, + {"ld4.bias.nt1", LDINCREG (0x12, 1)}, + {"ld4.bias.nta", LDINCREG (0x12, 3)}, + {"ld8.bias", LDINCREG (0x13, 0)}, + {"ld8.bias.nt1", LDINCREG (0x13, 1)}, + {"ld8.bias.nta", LDINCREG (0x13, 3)}, + {"ld1.acq", LDINCREG (0x14, 0)}, + {"ld1.acq.nt1", LDINCREG (0x14, 1)}, + {"ld1.acq.nta", LDINCREG (0x14, 3)}, + {"ld2.acq", LDINCREG (0x15, 0)}, + {"ld2.acq.nt1", LDINCREG (0x15, 1)}, + {"ld2.acq.nta", LDINCREG (0x15, 3)}, + {"ld4.acq", LDINCREG (0x16, 0)}, + {"ld4.acq.nt1", LDINCREG (0x16, 1)}, + {"ld4.acq.nta", LDINCREG (0x16, 3)}, + {"ld8.acq", LDINCREG (0x17, 0)}, + {"ld8.acq.nt1", LDINCREG (0x17, 1)}, + {"ld8.acq.nta", LDINCREG (0x17, 3)}, + {"ld8.fill", LDINCREG (0x1b, 0)}, + {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, + {"ld8.fill.nta", LDINCREG (0x1b, 3)}, + {"ld1.c.clr", LDINCREG (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, + {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, + {"ld2.c.clr", LDINCREG (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, + {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, + {"ld4.c.clr", LDINCREG (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, + {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, + {"ld8.c.clr", LDINCREG (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, + {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, + {"ld1.c.nc", LDINCREG (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, + {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, + {"ld2.c.nc", LDINCREG (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, + {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, + {"ld4.c.nc", LDINCREG (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, + {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, + {"ld8.c.nc", LDINCREG (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, + {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, + {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, + {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, + {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, +#undef LDINCREG + + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}}, + +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV} + {"cmpxchg1.acq", CMPXCHG (0x00, 0)}, + {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)}, + {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)}, + {"cmpxchg2.acq", CMPXCHG (0x01, 0)}, + {"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)}, + {"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)}, + {"cmpxchg4.acq", CMPXCHG (0x02, 0)}, + {"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)}, + {"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)}, + {"cmpxchg8.acq", CMPXCHG (0x03, 0)}, + {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)}, + {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)}, + {"cmpxchg1.rel", CMPXCHG (0x04, 0)}, + {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)}, + {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)}, + {"cmpxchg2.rel", CMPXCHG (0x05, 0)}, + {"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)}, + {"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)}, + {"cmpxchg4.rel", CMPXCHG (0x06, 0)}, + {"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)}, + {"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)}, + {"cmpxchg8.rel", CMPXCHG (0x07, 0)}, + {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)}, + {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)}, +#undef CMPXCHG + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}}, + + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}}, + + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}}, + + /* integer load w/increment by immediate */ +#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC + {"ld1", LDINCIMMED (0x00, 0)}, + {"ld1.nt1", LDINCIMMED (0x00, 1)}, + {"ld1.nta", LDINCIMMED (0x00, 3)}, + {"ld2", LDINCIMMED (0x01, 0)}, + {"ld2.nt1", LDINCIMMED (0x01, 1)}, + {"ld2.nta", LDINCIMMED (0x01, 3)}, + {"ld4", LDINCIMMED (0x02, 0)}, + {"ld4.nt1", LDINCIMMED (0x02, 1)}, + {"ld4.nta", LDINCIMMED (0x02, 3)}, + {"ld8", LDINCIMMED (0x03, 0)}, + {"ld8.nt1", LDINCIMMED (0x03, 1)}, + {"ld8.nta", LDINCIMMED (0x03, 3)}, + {"ld1.s", LDINCIMMED (0x04, 0)}, + {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, + {"ld1.s.nta", LDINCIMMED (0x04, 3)}, + {"ld2.s", LDINCIMMED (0x05, 0)}, + {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, + {"ld2.s.nta", LDINCIMMED (0x05, 3)}, + {"ld4.s", LDINCIMMED (0x06, 0)}, + {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, + {"ld4.s.nta", LDINCIMMED (0x06, 3)}, + {"ld8.s", LDINCIMMED (0x07, 0)}, + {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, + {"ld8.s.nta", LDINCIMMED (0x07, 3)}, + {"ld1.a", LDINCIMMED (0x08, 0)}, + {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, + {"ld1.a.nta", LDINCIMMED (0x08, 3)}, + {"ld2.a", LDINCIMMED (0x09, 0)}, + {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, + {"ld2.a.nta", LDINCIMMED (0x09, 3)}, + {"ld4.a", LDINCIMMED (0x0a, 0)}, + {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, + {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, + {"ld8.a", LDINCIMMED (0x0b, 0)}, + {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, + {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, + {"ld1.sa", LDINCIMMED (0x0c, 0)}, + {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, + {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, + {"ld2.sa", LDINCIMMED (0x0d, 0)}, + {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, + {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, + {"ld4.sa", LDINCIMMED (0x0e, 0)}, + {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, + {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, + {"ld8.sa", LDINCIMMED (0x0f, 0)}, + {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, + {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, + {"ld1.bias", LDINCIMMED (0x10, 0)}, + {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, + {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, + {"ld2.bias", LDINCIMMED (0x11, 0)}, + {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, + {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, + {"ld4.bias", LDINCIMMED (0x12, 0)}, + {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, + {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, + {"ld8.bias", LDINCIMMED (0x13, 0)}, + {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, + {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, + {"ld1.acq", LDINCIMMED (0x14, 0)}, + {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, + {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, + {"ld2.acq", LDINCIMMED (0x15, 0)}, + {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, + {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, + {"ld4.acq", LDINCIMMED (0x16, 0)}, + {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, + {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, + {"ld8.acq", LDINCIMMED (0x17, 0)}, + {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, + {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, + {"ld8.fill", LDINCIMMED (0x1b, 0)}, + {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, + {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, + {"ld1.c.clr", LDINCIMMED (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, + {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, + {"ld2.c.clr", LDINCIMMED (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, + {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, + {"ld4.c.clr", LDINCIMMED (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, + {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, + {"ld8.c.clr", LDINCIMMED (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, + {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, + {"ld1.c.nc", LDINCIMMED (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, + {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, + {"ld2.c.nc", LDINCIMMED (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, + {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, + {"ld4.c.nc", LDINCIMMED (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, + {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, + {"ld8.c.nc", LDINCIMMED (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, + {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, + {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, + {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, + {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, +#undef LDINCIMMED + + /* store w/increment by immediate */ +#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC + {"st1", STINCIMMED (0x30, 0)}, + {"st1.nta", STINCIMMED (0x30, 3)}, + {"st2", STINCIMMED (0x31, 0)}, + {"st2.nta", STINCIMMED (0x31, 3)}, + {"st4", STINCIMMED (0x32, 0)}, + {"st4.nta", STINCIMMED (0x32, 3)}, + {"st8", STINCIMMED (0x33, 0)}, + {"st8.nta", STINCIMMED (0x33, 3)}, + {"st1.rel", STINCIMMED (0x34, 0)}, + {"st1.rel.nta", STINCIMMED (0x34, 3)}, + {"st2.rel", STINCIMMED (0x35, 0)}, + {"st2.rel.nta", STINCIMMED (0x35, 3)}, + {"st4.rel", STINCIMMED (0x36, 0)}, + {"st4.rel.nta", STINCIMMED (0x36, 3)}, + {"st8.rel", STINCIMMED (0x37, 0)}, + {"st8.rel.nta", STINCIMMED (0x37, 3)}, + {"st8.spill", STINCIMMED (0x3b, 0)}, + {"st8.spill.nta", STINCIMMED (0x3b, 3)}, +#undef STINCIMMED + + /* floating-point load */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}}, + + /* floating-point load w/increment by register */ +#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC + {"ldfs", FLDINCREG (0x02, 0)}, + {"ldfs.nt1", FLDINCREG (0x02, 1)}, + {"ldfs.nta", FLDINCREG (0x02, 3)}, + {"ldfd", FLDINCREG (0x03, 0)}, + {"ldfd.nt1", FLDINCREG (0x03, 1)}, + {"ldfd.nta", FLDINCREG (0x03, 3)}, + {"ldf8", FLDINCREG (0x01, 0)}, + {"ldf8.nt1", FLDINCREG (0x01, 1)}, + {"ldf8.nta", FLDINCREG (0x01, 3)}, + {"ldfe", FLDINCREG (0x00, 0)}, + {"ldfe.nt1", FLDINCREG (0x00, 1)}, + {"ldfe.nta", FLDINCREG (0x00, 3)}, + {"ldfs.s", FLDINCREG (0x06, 0)}, + {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, + {"ldfs.s.nta", FLDINCREG (0x06, 3)}, + {"ldfd.s", FLDINCREG (0x07, 0)}, + {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, + {"ldfd.s.nta", FLDINCREG (0x07, 3)}, + {"ldf8.s", FLDINCREG (0x05, 0)}, + {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, + {"ldf8.s.nta", FLDINCREG (0x05, 3)}, + {"ldfe.s", FLDINCREG (0x04, 0)}, + {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, + {"ldfe.s.nta", FLDINCREG (0x04, 3)}, + {"ldfs.a", FLDINCREG (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, + {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, + {"ldfd.a", FLDINCREG (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, + {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, + {"ldf8.a", FLDINCREG (0x09, 0)}, + {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, + {"ldf8.a.nta", FLDINCREG (0x09, 3)}, + {"ldfe.a", FLDINCREG (0x08, 0)}, + {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, + {"ldfe.a.nta", FLDINCREG (0x08, 3)}, + {"ldfs.sa", FLDINCREG (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, + {"ldfd.sa", FLDINCREG (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, + {"ldf8.sa", FLDINCREG (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, + {"ldfe.sa", FLDINCREG (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, + {"ldf.fill", FLDINCREG (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, + {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, + {"ldfs.c.clr", FLDINCREG (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, + {"ldfd.c.clr", FLDINCREG (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, + {"ldf8.c.clr", FLDINCREG (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, + {"ldfe.c.clr", FLDINCREG (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, + {"ldfs.c.nc", FLDINCREG (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, + {"ldfd.c.nc", FLDINCREG (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, + {"ldf8.c.nc", FLDINCREG (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, + {"ldfe.c.nc", FLDINCREG (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, +#undef FLDINCREG + + /* floating-point store */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}}, + + /* floating-point load pair */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}}, + + /* floating-point load pair w/increment by immediate */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC + {"ldfps", LD (0x02, 0, C8)}, + {"ldfps.nt1", LD (0x02, 1, C8)}, + {"ldfps.nta", LD (0x02, 3, C8)}, + {"ldfpd", LD (0x03, 0, C16)}, + {"ldfpd.nt1", LD (0x03, 1, C16)}, + {"ldfpd.nta", LD (0x03, 3, C16)}, + {"ldfp8", LD (0x01, 0, C16)}, + {"ldfp8.nt1", LD (0x01, 1, C16)}, + {"ldfp8.nta", LD (0x01, 3, C16)}, + {"ldfps.s", LD (0x06, 0, C8)}, + {"ldfps.s.nt1", LD (0x06, 1, C8)}, + {"ldfps.s.nta", LD (0x06, 3, C8)}, + {"ldfpd.s", LD (0x07, 0, C16)}, + {"ldfpd.s.nt1", LD (0x07, 1, C16)}, + {"ldfpd.s.nta", LD (0x07, 3, C16)}, + {"ldfp8.s", LD (0x05, 0, C16)}, + {"ldfp8.s.nt1", LD (0x05, 1, C16)}, + {"ldfp8.s.nta", LD (0x05, 3, C16)}, + {"ldfps.a", LD (0x0a, 0, C8)}, + {"ldfps.a.nt1", LD (0x0a, 1, C8)}, + {"ldfps.a.nta", LD (0x0a, 3, C8)}, + {"ldfpd.a", LD (0x0b, 0, C16)}, + {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, + {"ldfpd.a.nta", LD (0x0b, 3, C16)}, + {"ldfp8.a", LD (0x09, 0, C16)}, + {"ldfp8.a.nt1", LD (0x09, 1, C16)}, + {"ldfp8.a.nta", LD (0x09, 3, C16)}, + {"ldfps.sa", LD (0x0e, 0, C8)}, + {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, + {"ldfps.sa.nta", LD (0x0e, 3, C8)}, + {"ldfpd.sa", LD (0x0f, 0, C16)}, + {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, + {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, + {"ldfp8.sa", LD (0x0d, 0, C16)}, + {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, + {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, + {"ldfps.c.clr", LD (0x22, 0, C8)}, + {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, + {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, + {"ldfpd.c.clr", LD (0x23, 0, C16)}, + {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, + {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, + {"ldfp8.c.clr", LD (0x21, 0, C16)}, + {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, + {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, + {"ldfps.c.nc", LD (0x26, 0, C8)}, + {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, + {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, + {"ldfpd.c.nc", LD (0x27, 0, C16)}, + {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, + {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, + {"ldfp8.c.nc", LD (0x25, 0, C16)}, + {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, + {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, +#undef LD + + /* line prefetch */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}}, + + /* line prefetch w/increment by register */ +#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC + {"lfetch", LFETCHINCREG (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, + {"lfetch.nta", LFETCHINCREG (0x2c, 3)}, + {"lfetch.excl", LFETCHINCREG (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)}, + {"lfetch.fault", LFETCHINCREG (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, +#undef LFETCHINCREG + + /* semaphore operations */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}}, + + /* floating-point load w/increment by immediate */ +#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC + {"ldfs", FLDINCIMMED (0x02, 0)}, + {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, + {"ldfs.nta", FLDINCIMMED (0x02, 3)}, + {"ldfd", FLDINCIMMED (0x03, 0)}, + {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, + {"ldfd.nta", FLDINCIMMED (0x03, 3)}, + {"ldf8", FLDINCIMMED (0x01, 0)}, + {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, + {"ldf8.nta", FLDINCIMMED (0x01, 3)}, + {"ldfe", FLDINCIMMED (0x00, 0)}, + {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, + {"ldfe.nta", FLDINCIMMED (0x00, 3)}, + {"ldfs.s", FLDINCIMMED (0x06, 0)}, + {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, + {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, + {"ldfd.s", FLDINCIMMED (0x07, 0)}, + {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, + {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, + {"ldf8.s", FLDINCIMMED (0x05, 0)}, + {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, + {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, + {"ldfe.s", FLDINCIMMED (0x04, 0)}, + {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, + {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, + {"ldfs.a", FLDINCIMMED (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, + {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, + {"ldfd.a", FLDINCIMMED (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, + {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, + {"ldf8.a", FLDINCIMMED (0x09, 0)}, + {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, + {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, + {"ldfe.a", FLDINCIMMED (0x08, 0)}, + {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, + {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, + {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, + {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, + {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, + {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, + {"ldf.fill", FLDINCIMMED (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, + {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, + {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, + {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, + {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, + {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, + {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, + {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, + {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, + {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, +#undef FLDINCIMMED + + /* floating-point store w/increment by immediate */ +#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC + {"stfs", FSTINCIMMED (0x32, 0)}, + {"stfs.nta", FSTINCIMMED (0x32, 3)}, + {"stfd", FSTINCIMMED (0x33, 0)}, + {"stfd.nta", FSTINCIMMED (0x33, 3)}, + {"stf8", FSTINCIMMED (0x31, 0)}, + {"stf8.nta", FSTINCIMMED (0x31, 3)}, + {"stfe", FSTINCIMMED (0x30, 0)}, + {"stfe.nta", FSTINCIMMED (0x30, 3)}, + {"stf.spill", FSTINCIMMED (0x3b, 0)}, + {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, +#undef FSTINCIMMED + + /* line prefetch w/increment by immediate */ +#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC + {"lfetch", LFETCHINCIMMED (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, + {"lfetch.nta", LFETCHINCIMMED (0x2c, 3)}, + {"lfetch.excl", LFETCHINCIMMED (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)}, + {"lfetch.fault", LFETCHINCIMMED (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, +#undef LFETCHINCIMMED + + {0} + }; + +#undef M0 +#undef M +#undef M2 +#undef bM +#undef bX +#undef bX2 +#undef bX3 +#undef bX4 +#undef bX6a +#undef bX6b +#undef bHint +#undef mM +#undef mX +#undef mX2 +#undef mX3 +#undef mX4 +#undef mX6a +#undef mX6b +#undef mHint +#undef OpX3 +#undef OpX3X6b +#undef OpX3X4 +#undef OpX3X4X2 +#undef OpX6aHint +#undef OpXX6aHint +#undef OpMXX6a +#undef OpMXX6aHint diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc-x.c b/gnu/usr.bin/binutils/opcodes/ia64-opc-x.c new file mode 100644 index 00000000000..5f382fd6dd5 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc-x.c @@ -0,0 +1,178 @@ +/* ia64-opc-x.c -- IA-64 `X' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by Timothy Wall <twall@cygnus.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +/* identify the specific X-unit type */ +#define X0 IA64_TYPE_X, 0 +#define X IA64_TYPE_X, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mVc bVc (-1) +#define mWha bWha (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) + +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) + +struct ia64_opcode ia64_opcodes_x[] = + { + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}}, + {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}}, +#define BRL(a,b) \ + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0 + {"brl.few", BRL (0, 0) | PSEUDO}, + {"brl", BRL (0, 0) | PSEUDO}, + {"brl.few.clr", BRL (0, 1) | PSEUDO}, + {"brl.clr", BRL (0, 1) | PSEUDO}, + {"brl.many", BRL (1, 0) | PSEUDO}, + {"brl.many.clr", BRL (1, 1) | PSEUDO}, +#undef BRL +#define BRL(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0 + {"brl.cond.sptk.few", BRL (0, 0, 0)}, + {"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.cond.spnt.few", BRL (0, 1, 0)}, + {"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.cond.dptk.few", BRL (0, 2, 0)}, + {"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.cond.dpnt.few", BRL (0, 3, 0)}, + {"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.cond.sptk.many", BRL (1, 0, 0)}, + {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.cond.spnt.many", BRL (1, 1, 0)}, + {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.cond.dptk.many", BRL (1, 2, 0)}, + {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.cond.dpnt.many", BRL (1, 3, 0)}, + {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, + {"brl.sptk.few", BRL (0, 0, 0)}, + {"brl.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.spnt.few", BRL (0, 1, 0)}, + {"brl.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.dptk.few", BRL (0, 2, 0)}, + {"brl.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.dpnt.few", BRL (0, 3, 0)}, + {"brl.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.sptk.many", BRL (1, 0, 0)}, + {"brl.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.spnt.many", BRL (1, 1, 0)}, + {"brl.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.dptk.many", BRL (1, 2, 0)}, + {"brl.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.dpnt.many", BRL (1, 3, 0)}, + {"brl.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0 + {"brl.call.sptk.few", BRL (0, 0, 0)}, + {"brl.call.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.call.spnt.few", BRL (0, 1, 0)}, + {"brl.call.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.call.dptk.few", BRL (0, 2, 0)}, + {"brl.call.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.call.dpnt.few", BRL (0, 3, 0)}, + {"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.call.sptk.many", BRL (1, 0, 0)}, + {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.call.spnt.many", BRL (1, 1, 0)}, + {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.call.dptk.many", BRL (1, 2, 0)}, + {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.call.dpnt.many", BRL (1, 3, 0)}, + {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL + {0} + }; + +#undef X0 +#undef X + +#undef bBtype +#undef bD +#undef bPa +#undef bPr +#undef bVc +#undef bWha +#undef bX3 +#undef bX6 + +#undef mBtype +#undef mD +#undef mPa +#undef mPr +#undef mVc +#undef mWha +#undef mX3 +#undef mX6 + +#undef OpX3X6 +#undef OpVc +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc.c b/gnu/usr.bin/binutils/opcodes/ia64-opc.c new file mode 100644 index 00000000000..84e38377ab7 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc.c @@ -0,0 +1,748 @@ +/* ia64-opc.c -- Functions to access the compacted opcode table + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "ia64-asmtab.h" +#include "ia64-asmtab.c" + +const struct ia64_templ_desc ia64_templ_desc[16] = + { + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ + { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, + { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, + { 0, { 0, }, "-3-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ + { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ + { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, + { 0, { 0, }, "-a-" }, + { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ + { 0, { 0, }, "-d-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, + { 0, { 0, }, "-f-" }, + }; + + +/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. + PTR will be adjusted to point to the start of the next portion + of the opcode, or at the NUL character. */ + +static void +get_opc_prefix (ptr, dest) + const char **ptr; + char *dest; +{ + char *c = strchr (*ptr, '.'); + if (c != NULL) + { + memcpy (dest, *ptr, c - *ptr); + dest[c - *ptr] = '\0'; + *ptr = c + 1; + } + else + { + int l = strlen (*ptr); + memcpy (dest, *ptr, l); + dest[l] = '\0'; + *ptr += l; + } +} + +/* Find the index of the entry in the string table corresponding to + STR; return -1 if one does not exist. */ + +static short +find_string_ent (str) + const char *str; +{ + short start = 0; + short end = sizeof (ia64_strings) / sizeof (const char *); + short i = (start + end) / 2; + + if (strcmp (str, ia64_strings[end - 1]) > 0) + { + return -1; + } + while (start <= end) + { + int c = strcmp (str, ia64_strings[i]); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the opcode in the main opcode table whose name is STRINGINDEX, or + return -1 if one does not exist. */ + +static short +find_main_ent (nameindex) + short nameindex; +{ + short start = 0; + short end = sizeof (main_table) / sizeof (struct ia64_main_table); + short i = (start + end) / 2; + + if (nameindex < main_table[0].name_index + || nameindex > main_table[end - 1].name_index) + { + return -1; + } + while (start <= end) + { + if (nameindex < main_table[i].name_index) + { + end = i - 1; + } + else if (nameindex == main_table[i].name_index) + { + while (i > 0 && main_table[i - 1].name_index == nameindex) + { + i--; + } + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the index of the entry in the completer table that is part of + MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or + return -1 if one does not exist. */ + +static short +find_completer (main_ent, prev_completer, name) + short main_ent; + short prev_completer; + const char *name; +{ + short name_index = find_string_ent (name); + + if (name_index < 0) + { + return -1; + } + + if (prev_completer == -1) + { + prev_completer = main_table[main_ent].completers; + } + else + { + prev_completer = completer_table[prev_completer].subentries; + } + + while (prev_completer != -1) + { + if (completer_table[prev_completer].name_index == name_index) + { + return prev_completer; + } + prev_completer = completer_table[prev_completer].alternative; + } + return -1; +} + +/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and + return the result. */ + +static ia64_insn +apply_completer (opcode, completer_index) + ia64_insn opcode; + int completer_index; +{ + ia64_insn mask = completer_table[completer_index].mask; + ia64_insn bits = completer_table[completer_index].bits; + int shiftamt = (completer_table[completer_index].offset & 63); + + mask = mask << shiftamt; + bits = bits << shiftamt; + opcode = (opcode & ~mask) | bits; + return opcode; +} + +/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in + the dis_table array, and return its value. (BITOFFSET is numbered + starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the + first byte in OP_POINTER.) */ + +static int +extract_op_bits (op_pointer, bitoffset, bits) + int op_pointer; + int bitoffset; + int bits; +{ + int res = 0; + + op_pointer += (bitoffset / 8); + + if (bitoffset % 8) + { + unsigned int op = dis_table[op_pointer++]; + int numb = 8 - (bitoffset % 8); + int mask = (1 << numb) - 1; + int bata = (bits < numb) ? bits : numb; + int delta = numb - bata; + + res = (res << bata) | ((op & mask) >> delta); + bitoffset += bata; + bits -= bata; + } + while (bits >= 8) + { + res = (res << 8) | (dis_table[op_pointer++] & 255); + bits -= 8; + } + if (bits > 0) + { + unsigned int op = (dis_table[op_pointer++] & 255); + res = (res << bits) | (op >> (8 - bits)); + } + return res; +} + +/* Examine the state machine entry at OP_POINTER in the dis_table + array, and extract its values into OPVAL and OP. The length of the + state entry in bits is returned. */ + +static int +extract_op (op_pointer, opval, op) + int op_pointer; + int *opval; + unsigned int *op; +{ + int oplen = 5; + + *op = dis_table[op_pointer]; + + if ((*op) & 0x40) + { + opval[0] = extract_op_bits (op_pointer, oplen, 5); + oplen += 5; + } + switch ((*op) & 0x30) + { + case 0x10: + { + opval[1] = extract_op_bits (op_pointer, oplen, 8); + oplen += 8; + opval[1] += op_pointer; + break; + } + case 0x20: + { + opval[1] = extract_op_bits (op_pointer, oplen, 16); + if (! (opval[1] & 32768)) + { + opval[1] += op_pointer; + } + oplen += 16; + break; + } + case 0x30: + { + oplen--; + opval[2] = extract_op_bits (op_pointer, oplen, 12); + oplen += 12; + opval[2] |= 32768; + break; + } + } + if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) + { + opval[2] = extract_op_bits (op_pointer, oplen, 16); + oplen += 16; + if (! (opval[2] & 32768)) + { + opval[2] += op_pointer; + } + } + return oplen; +} + +/* Returns a non-zero value if the opcode in the main_table list at + PLACE matches OPCODE and is of type TYPE. */ + +static int +opcode_verify (opcode, place, type) + ia64_insn opcode; + int place; + enum ia64_insn_type type; +{ + if (main_table[place].opcode_type != type) + { + return 0; + } + if (main_table[place].flags + & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) + { + const struct ia64_operand *o1, *o2; + ia64_insn f2, f3; + + if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) + { + o1 = elf64_ia64_operands + IA64_OPND_F2; + o2 = elf64_ia64_operands + IA64_OPND_F3; + (*o1->extract) (o1, opcode, &f2); + (*o2->extract) (o2, opcode, &f3); + if (f2 != f3) + return 0; + } + else + { + ia64_insn len, count; + + /* length must equal 64-count: */ + o1 = elf64_ia64_operands + IA64_OPND_LEN6; + o2 = elf64_ia64_operands + main_table[place].operands[2]; + (*o1->extract) (o1, opcode, &len); + (*o2->extract) (o2, opcode, &count); + if (len != 64 - count) + return 0; + } + } + return 1; +} + +/* Find an instruction entry in the ia64_dis_names array that matches + opcode OPCODE and is of type TYPE. Returns either a positive index + into the array, or a negative value if an entry for OPCODE could + not be found. Checks all matches and returns the one with the highest + priority. */ + +static int +locate_opcode_ent (opcode, type) + ia64_insn opcode; + enum ia64_insn_type type; +{ + int currtest[41]; + int bitpos[41]; + int op_ptr[41]; + int currstatenum = 0; + short found_disent = -1; + short found_priority = -1; + + currtest[currstatenum] = 0; + op_ptr[currstatenum] = 0; + bitpos[currstatenum] = 40; + + while (1) + { + int op_pointer = op_ptr[currstatenum]; + unsigned int op; + int currbitnum = bitpos[currstatenum]; + int oplen; + int opval[3]; + int next_op; + int currbit; + + oplen = extract_op (op_pointer, opval, &op); + + bitpos[currstatenum] = currbitnum; + + /* Skip opval[0] bits in the instruction. */ + if (op & 0x40) + { + currbitnum -= opval[0]; + } + + /* The value of the current bit being tested. */ + currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; + next_op = -1; + + /* We always perform the tests specified in the current state in + a particular order, falling through to the next test if the + previous one failed. */ + switch (currtest[currstatenum]) + { + case 0: + currtest[currstatenum]++; + if (currbit == 0 && (op & 0x80)) + { + /* Check for a zero bit. If this test solely checks for + a zero bit, we can check for up to 8 consecutive zero + bits (the number to check is specified by the lower 3 + bits in the state code.) + + If the state instruction matches, we go to the very + next state instruction; otherwise, try the next test. */ + + if ((op & 0xf8) == 0x80) + { + int count = op & 0x7; + int x; + + for (x = 0; x <= count; x++) + { + int i = + opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; + if (i) + { + break; + } + } + if (x > count) + { + next_op = op_pointer + ((oplen + 7) / 8); + currbitnum -= count; + break; + } + } + else if (! currbit) + { + next_op = op_pointer + ((oplen + 7) / 8); + break; + } + } + /* FALLTHROUGH */ + case 1: + /* If the bit in the instruction is one, go to the state + instruction specified by opval[1]. */ + currtest[currstatenum]++; + if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) + { + next_op = opval[1]; + break; + } + /* FALLTHROUGH */ + case 2: + /* Don't care. Skip the current bit and go to the state + instruction specified by opval[2]. + + An encoding of 0x30 is special; this means that a 12-bit + offset into the ia64_dis_names[] array is specified. */ + currtest[currstatenum]++; + if ((op & 0x08) || ((op & 0x30) == 0x30)) + { + next_op = opval[2]; + break; + } + } + + /* If bit 15 is set in the address of the next state, an offset + in the ia64_dis_names array was specified instead. We then + check to see if an entry in the list of opcodes matches the + opcode we were given; if so, we have succeeded. */ + + if ((next_op >= 0) && (next_op & 32768)) + { + short disent = next_op & 32767; + short priority = -1; + + if (next_op > 65535) + { + abort (); + } + + /* Run through the list of opcodes to check, trying to find + one that matches. */ + while (disent >= 0) + { + int place = ia64_dis_names[disent].insn_index; + + priority = ia64_dis_names[disent].priority; + + if (opcode_verify (opcode, place, type) + && priority > found_priority) + { + break; + } + if (ia64_dis_names[disent].next_flag) + { + disent++; + } + else + { + disent = -1; + } + } + + if (disent >= 0) + { + found_disent = disent; + found_priority = priority; + } + /* Try the next test in this state, regardless of whether a match + was found. */ + next_op = -2; + } + + /* next_op == -1 is "back up to the previous state". + next_op == -2 is "stay in this state and try the next test". + Otherwise, transition to the state indicated by next_op. */ + + if (next_op == -1) + { + currstatenum--; + if (currstatenum < 0) + { + return found_disent; + } + } + else if (next_op >= 0) + { + currstatenum++; + bitpos[currstatenum] = currbitnum - 1; + op_ptr[currstatenum] = next_op; + currtest[currstatenum] = 0; + } + } +} + +/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ + +static struct ia64_opcode * +make_ia64_opcode (opcode, name, place, depind) + ia64_insn opcode; + const char *name; + int place; + int depind; +{ + struct ia64_opcode *res = + (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); + res->name = xstrdup (name); + res->type = main_table[place].opcode_type; + res->num_outputs = main_table[place].num_outputs; + res->opcode = opcode; + res->mask = main_table[place].mask; + res->operands[0] = main_table[place].operands[0]; + res->operands[1] = main_table[place].operands[1]; + res->operands[2] = main_table[place].operands[2]; + res->operands[3] = main_table[place].operands[3]; + res->operands[4] = main_table[place].operands[4]; + res->flags = main_table[place].flags; + res->ent_index = place; + res->dependencies = &op_dependencies[depind]; + return res; +} + +/* Determine the ia64_opcode entry for the opcode specified by INSN + and TYPE. If a valid entry is not found, return NULL. */ +struct ia64_opcode * +ia64_dis_opcode (insn, type) + ia64_insn insn; + enum ia64_insn_type type; +{ + int disent = locate_opcode_ent (insn, type); + + if (disent < 0) + { + return NULL; + } + else + { + unsigned int cb = ia64_dis_names[disent].completer_index; + static char name[128]; + int place = ia64_dis_names[disent].insn_index; + int ci = main_table[place].completers; + ia64_insn tinsn = main_table[place].opcode; + + strcpy (name, ia64_strings [main_table[place].name_index]); + + while (cb) + { + if (cb & 1) + { + int cname = completer_table[ci].name_index; + + tinsn = apply_completer (tinsn, ci); + + if (ia64_strings[cname][0] != '\0') + { + strcat (name, "."); + strcat (name, ia64_strings[cname]); + } + if (cb != 1) + { + ci = completer_table[ci].subentries; + } + } + else + { + ci = completer_table[ci].alternative; + } + if (ci < 0) + { + abort (); + } + cb = cb >> 1; + } + if (tinsn != (insn & main_table[place].mask)) + { + abort (); + } + return make_ia64_opcode (insn, name, place, + completer_table[ci].dependencies); + } +} + +/* Search the main_opcode table starting from PLACE for an opcode that + matches NAME. Return NULL if one is not found. */ + +static struct ia64_opcode * +ia64_find_matching_opcode (name, place) + const char *name; + short place; +{ + char op[129]; + const char *suffix; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + while (main_table[place].name_index == name_index) + { + const char *curr_suffix = suffix; + ia64_insn curr_insn = main_table[place].opcode; + short completer = -1; + + do { + if (suffix[0] == '\0') + { + completer = find_completer (place, completer, suffix); + } + else + { + get_opc_prefix (&curr_suffix, op); + completer = find_completer (place, completer, op); + } + if (completer != -1) + { + curr_insn = apply_completer (curr_insn, completer); + } + } while (completer != -1 && curr_suffix[0] != '\0'); + + if (completer != -1 && curr_suffix[0] == '\0' + && completer_table[completer].terminal_completer) + { + int depind = completer_table[completer].dependencies; + return make_ia64_opcode (curr_insn, name, place, depind); + } + else + { + place++; + } + } + return NULL; +} + +/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL + if one does not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_next_opcode (prev_ent) + struct ia64_opcode *prev_ent; +{ + return ia64_find_matching_opcode (prev_ent->name, + prev_ent->ent_index + 1); +} + +/* Find the first opcode that matches NAME, or return NULL if it does + not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_opcode (name) + const char *name; +{ + char op[129]; + const char *suffix; + short place; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + place = find_main_ent (name_index); + + if (place < 0) + { + return NULL; + } + return ia64_find_matching_opcode (name, place); +} + +/* Free any resources used by ENT. */ +void +ia64_free_opcode (ent) + struct ia64_opcode *ent; +{ + free ((void *)ent->name); + free (ent); +} + +const struct ia64_dependency * +ia64_find_dependency (index) + int index; +{ + index = DEP(index); + + if (index < 0 + || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0]))) + return NULL; + + return &dependencies[index]; +} diff --git a/gnu/usr.bin/binutils/opcodes/ia64-opc.h b/gnu/usr.bin/binutils/opcodes/ia64-opc.h new file mode 100644 index 00000000000..b721cb87215 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-opc.h @@ -0,0 +1,130 @@ +/* ia64-opc.h -- IA-64 opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_OPC_H +#define IA64_OPC_H + +#include "opcode/ia64.h" + +/* define a couple of abbreviations: */ + +#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) +#define mOp bOp (-1) +#define Op(x) bOp (x), mOp + +#define FIRST IA64_OPCODE_FIRST +#define X_IN_MLX IA64_OPCODE_X_IN_MLX +#define LAST IA64_OPCODE_LAST +#define PRIV IA64_OPCODE_PRIV +#define NO_PRED IA64_OPCODE_NO_PRED +#define SLOT2 IA64_OPCODE_SLOT2 +#define PSEUDO IA64_OPCODE_PSEUDO +#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 +#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT +#define MOD_RRBS IA64_OPCODE_MOD_RRBS +#define POSTINC IA64_OPCODE_POSTINC + +#define AR_CCV IA64_OPND_AR_CCV +#define AR_PFS IA64_OPND_AR_PFS +#define C1 IA64_OPND_C1 +#define C8 IA64_OPND_C8 +#define C16 IA64_OPND_C16 +#define GR0 IA64_OPND_GR0 +#define IP IA64_OPND_IP +#define PR IA64_OPND_PR +#define PR_ROT IA64_OPND_PR_ROT +#define PSR IA64_OPND_PSR +#define PSR_L IA64_OPND_PSR_L +#define PSR_UM IA64_OPND_PSR_UM + +#define AR3 IA64_OPND_AR3 +#define B1 IA64_OPND_B1 +#define B2 IA64_OPND_B2 +#define CR3 IA64_OPND_CR3 +#define F1 IA64_OPND_F1 +#define F2 IA64_OPND_F2 +#define F3 IA64_OPND_F3 +#define F4 IA64_OPND_F4 +#define P1 IA64_OPND_P1 +#define P2 IA64_OPND_P2 +#define R1 IA64_OPND_R1 +#define R2 IA64_OPND_R2 +#define R3 IA64_OPND_R3 +#define R3_2 IA64_OPND_R3_2 + +#define CPUID_R3 IA64_OPND_CPUID_R3 +#define DBR_R3 IA64_OPND_DBR_R3 +#define DTR_R3 IA64_OPND_DTR_R3 +#define ITR_R3 IA64_OPND_ITR_R3 +#define IBR_R3 IA64_OPND_IBR_R3 +#define MR3 IA64_OPND_MR3 +#define MSR_R3 IA64_OPND_MSR_R3 +#define PKR_R3 IA64_OPND_PKR_R3 +#define PMC_R3 IA64_OPND_PMC_R3 +#define PMD_R3 IA64_OPND_PMD_R3 +#define RR_R3 IA64_OPND_RR_R3 + +#define CCNT5 IA64_OPND_CCNT5 +#define CNT2a IA64_OPND_CNT2a +#define CNT2b IA64_OPND_CNT2b +#define CNT2c IA64_OPND_CNT2c +#define CNT5 IA64_OPND_CNT5 +#define CNT6 IA64_OPND_CNT6 +#define CPOS6a IA64_OPND_CPOS6a +#define CPOS6b IA64_OPND_CPOS6b +#define CPOS6c IA64_OPND_CPOS6c +#define IMM1 IA64_OPND_IMM1 +#define IMM14 IA64_OPND_IMM14 +#define IMM17 IA64_OPND_IMM17 +#define IMM22 IA64_OPND_IMM22 +#define IMM44 IA64_OPND_IMM44 +#define SOF IA64_OPND_SOF +#define SOL IA64_OPND_SOL +#define SOR IA64_OPND_SOR +#define IMM8 IA64_OPND_IMM8 +#define IMM8U4 IA64_OPND_IMM8U4 +#define IMM8M1 IA64_OPND_IMM8M1 +#define IMM8M1U4 IA64_OPND_IMM8M1U4 +#define IMM8M1U8 IA64_OPND_IMM8M1U8 +#define IMM9a IA64_OPND_IMM9a +#define IMM9b IA64_OPND_IMM9b +#define IMMU2 IA64_OPND_IMMU2 +#define IMMU21 IA64_OPND_IMMU21 +#define IMMU24 IA64_OPND_IMMU24 +#define IMMU62 IA64_OPND_IMMU62 +#define IMMU64 IA64_OPND_IMMU64 +#define IMMU7a IA64_OPND_IMMU7a +#define IMMU7b IA64_OPND_IMMU7b +#define IMMU9 IA64_OPND_IMMU9 +#define INC3 IA64_OPND_INC3 +#define LEN4 IA64_OPND_LEN4 +#define LEN6 IA64_OPND_LEN6 +#define MBTYPE4 IA64_OPND_MBTYPE4 +#define MHTYPE8 IA64_OPND_MHTYPE8 +#define POS6 IA64_OPND_POS6 +#define TAG13 IA64_OPND_TAG13 +#define TAG13b IA64_OPND_TAG13b +#define TGT25 IA64_OPND_TGT25 +#define TGT25b IA64_OPND_TGT25b +#define TGT25c IA64_OPND_TGT25c +#define TGT64 IA64_OPND_TGT64 + +#endif diff --git a/gnu/usr.bin/binutils/opcodes/ia64-raw.tbl b/gnu/usr.bin/binutils/opcodes/ia64-raw.tbl new file mode 100644 index 00000000000..ec35888cf48 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-raw.tbl @@ -0,0 +1,174 @@ +Resource Name; Writers; Readers; Semantics of Dependency +ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF +AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF +AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; br.ret; none +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF +AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none +AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF +CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF +CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF +CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF +CFM; alloc; IC:cfm-readers; none +CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data +CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data +CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data +CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data +CR[IFS]; IC:mov-to-CR-IFS; rfi; implied +CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data +CR[IIP]; IC:mov-to-CR-IIP; rfi; implied +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data +CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data +CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr +CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2 +CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1 +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3 +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF +DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF +DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none +DTR; ptr.d; itr.d, itc.d; impliedF +FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none +FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF +FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none +GR0; IC:none; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data +InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none +ITC; itc.i, itc.d, itr.i, itr.d; epc; instr +ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF +ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF +ITR; itr.i; epc; instr +ITR; ptr.i; itc.i, itr.i; impliedF +ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none +ITR; ptr.i; epc; instr +memory; IC:mem-writers; IC:mem-readers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific +PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1 +PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR+12, IC:mov-to-PR+12; none +PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-readers-br+1; none +PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF +PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF +PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied +PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data +PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.i; rfi; IC:mov-from-PSR; data +PSR.ia; rfi; IC:none; none +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data +PSR.id; rfi; IC:none; none +PSR.is; br.ia, rfi; IC:none; none +PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data +PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.lp; IC:mov-to-PSR-l; br.ret; data +PSR.lp; rfi; IC:mov-from-PSR, br.ret; data +PSR.mc; rfi; IC:mov-from-PSR; none +PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ri; rfi; IC:none; none +PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data +PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data +PSR.ss; rfi; IC:all; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data +RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/gnu/usr.bin/binutils/opcodes/ia64-war.tbl b/gnu/usr.bin/binutils/opcodes/ia64-war.tbl new file mode 100644 index 00000000000..8cdfac5b485 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-war.tbl @@ -0,0 +1,2 @@ +Resource Name; Readers; Writers; Semantics of Dependency +PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop diff --git a/gnu/usr.bin/binutils/opcodes/ia64-waw.tbl b/gnu/usr.bin/binutils/opcodes/ia64-waw.tbl new file mode 100644 index 00000000000..c8a3365b1cd --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/ia64-waw.tbl @@ -0,0 +1,128 @@ +Resource Name; Writers; Writers; Semantics of Dependency +ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF +AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none +AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none +AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none +AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none +AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF +AR[PFS]; br.call, brl.call; br.call, brl.call; none +AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none +AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none +CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF +CPUID#; IC:none; IC:none; none +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF +CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF +CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF +CR[IVR]; IC:none; IC:none; SC +CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; itr.d; impliedF +DTR; itr.d; ptr.d; impliedF +DTR; ptr.d; ptr.d; none +FR%, % in 0 - 1; IC:none; IC:none; none +FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF +GR0; IC:none; IC:none; none +GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITR; itr.i; itr.i, ptr.i; impliedF +ITR; ptr.i; ptr.i; none +memory; IC:mem-writers; IC:mem-writers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF +PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-writers+1; none +PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF +PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.bn; bsw, rfi; bsw, rfi; impliedF +PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF +PSR.da; rfi; rfi; impliedF +PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.dd; rfi; rfi; impliedF +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ed; rfi; rfi; impliedF +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ia; rfi; rfi; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.id; rfi; rfi; impliedF +PSR.is; br.ia, rfi; br.ia, rfi; impliedF +PSR.it; rfi; rfi; impliedF +PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.mc; rfi; rfi; impliedF +PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ri; rfi; rfi; impliedF +PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ss; rfi; rfi; impliedF +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF diff --git a/gnu/usr.bin/binutils/opcodes/m10200-dis.c b/gnu/usr.bin/binutils/opcodes/m10200-dis.c index 01d54627b14..bd9a258442a 100644 --- a/gnu/usr.bin/binutils/opcodes/m10200-dis.c +++ b/gnu/usr.bin/binutils/opcodes/m10200-dis.c @@ -1,5 +1,5 @@ /* Disassemble MN10200 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/m10200-opc.c b/gnu/usr.bin/binutils/opcodes/m10200-opc.c index 6d97137dc69..ca565038525 100644 --- a/gnu/usr.bin/binutils/opcodes/m10200-opc.c +++ b/gnu/usr.bin/binutils/opcodes/m10200-opc.c @@ -1,5 +1,5 @@ /* Assemble Matsushita MN10200 instructions. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright 1996, 1997, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/m10300-dis.c b/gnu/usr.bin/binutils/opcodes/m10300-dis.c index 554d3280a6b..f9e60d7e5d3 100644 --- a/gnu/usr.bin/binutils/opcodes/m10300-dis.c +++ b/gnu/usr.bin/binutils/opcodes/m10300-dis.c @@ -1,5 +1,5 @@ /* Disassemble MN10300 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -484,6 +484,8 @@ disassemble (memaddr, info, insn, size) temp = extension >> operand->shift; temp &= ((1 << (32 - operand->bits)) - 1); value |= temp; + value = ((value ^ (((unsigned long)1) << 31)) + - (((unsigned long)1) << 31)); } else if ((operand->flags & MN10300_OPERAND_24BIT) != 0) { @@ -494,7 +496,7 @@ disassemble (memaddr, info, insn, size) temp &= ((1 << (24 - operand->bits)) - 1); value |= temp; if ((operand->flags & MN10300_OPERAND_SIGNED) != 0) - value = ((value & 0xffffff) ^ (~0x7fffff)) + 0x800000; + value = ((value & 0xffffff) ^ 0x800000) - 0x800000; } else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0) { @@ -508,11 +510,10 @@ disassemble (memaddr, info, insn, size) } if ((operand->flags & MN10300_OPERAND_SIGNED) != 0 - /* These are properly extended by the code above. */ - && ((operand->flags & MN10300_OPERAND_24BIT) == 0) - ) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); + /* These are properly extended by the code above. */ + && ((operand->flags & MN10300_OPERAND_24BIT) == 0)) + value = ((value ^ (((unsigned long)1) << (operand->bits - 1))) + - (((unsigned long)1) << (operand->bits - 1))); if (!nocomma && (!paren @@ -525,14 +526,14 @@ disassemble (memaddr, info, insn, size) { value = ((insn >> (operand->shift + extra_shift)) & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "d%d", value); + (*info->fprintf_func) (info->stream, "d%d", (int)value); } else if ((operand->flags & MN10300_OPERAND_AREG) != 0) { value = ((insn >> (operand->shift + extra_shift)) & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "a%d", value); + (*info->fprintf_func) (info->stream, "a%d", (int)value); } else if ((operand->flags & MN10300_OPERAND_SP) != 0) @@ -549,11 +550,11 @@ disassemble (memaddr, info, insn, size) value = ((insn >> (operand->shift + extra_shift)) & ((1 << operand->bits) - 1)); if (value < 8) - (*info->fprintf_func) (info->stream, "r%d", value); + (*info->fprintf_func) (info->stream, "r%d", (int)value); else if (value < 12) - (*info->fprintf_func) (info->stream, "a%d", value - 8); + (*info->fprintf_func) (info->stream, "a%d", (int)value - 8); else - (*info->fprintf_func) (info->stream, "d%d", value - 12); + (*info->fprintf_func) (info->stream, "d%d", (int)value - 12); } else if ((operand->flags & MN10300_OPERAND_XRREG) != 0) @@ -563,7 +564,7 @@ disassemble (memaddr, info, insn, size) if (value == 0) (*info->fprintf_func) (info->stream, "sp", value); else - (*info->fprintf_func) (info->stream, "xr%d", value); + (*info->fprintf_func) (info->stream, "xr%d", (int)value); } else if ((operand->flags & MN10300_OPERAND_USP) != 0) @@ -670,7 +671,7 @@ disassemble (memaddr, info, insn, size) } else - (*info->fprintf_func) (info->stream, "%d", value); + (*info->fprintf_func) (info->stream, "%ld", (long)value); } /* All done. */ break; diff --git a/gnu/usr.bin/binutils/opcodes/m10300-opc.c b/gnu/usr.bin/binutils/opcodes/m10300-opc.c index 2b0b98dc622..409c785c707 100644 --- a/gnu/usr.bin/binutils/opcodes/m10300-opc.c +++ b/gnu/usr.bin/binutils/opcodes/m10300-opc.c @@ -1,5 +1,5 @@ /* Assemble Matsushita MN10300 instructions. - Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/m32r-asm.c b/gnu/usr.bin/binutils/opcodes/m32r-asm.c index 0aa62ce1a15..22b59a5d1e1 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-asm.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-asm.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-asm.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -406,7 +406,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (*str == CGEN_SYNTAX_CHAR (* syn)) + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (* syn == ' ') @@ -418,9 +418,11 @@ parse_insn_normal (cd, insn, strp, fields) else { /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); + static char msg [80]; + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + *syn, *str); + return msg; } continue; } @@ -486,7 +488,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) { const char *start; CGEN_INSN_LIST *ilist; - const char *tmp_errmsg; + const char *tmp_errmsg = NULL; /* Skip leading white space. */ while (isspace (* str)) @@ -521,20 +523,25 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) /* Allow parse/insert handlers to obtain length of insn. */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - if (!(tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields))) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0) - != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } + tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (tmp_errmsg != NULL) + continue; - /* Try the next entry. */ + /* ??? 0 is passed for `pc' */ + tmp_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (tmp_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; } + /* Make sure we leave this with something at this point. */ + if (tmp_errmsg == NULL) + tmp_errmsg = "unknown mnemonic"; + { static char errbuf[150]; diff --git a/gnu/usr.bin/binutils/opcodes/m32r-desc.c b/gnu/usr.bin/binutils/opcodes/m32r-desc.c index 360c38f1642..93a36d3c946 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-desc.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "m32r-desc.h" #include "m32r-opc.h" #include "opintl.h" +#include "libiberty.h" /* Attributes. */ @@ -69,7 +70,7 @@ static const CGEN_ATTR_ENTRY PIPE_attr[] = const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, @@ -82,7 +83,7 @@ const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, { "PC", &bool_attr[0], &bool_attr[0] }, @@ -92,7 +93,7 @@ const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = { - { "MACH", & MACH_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, @@ -108,8 +109,8 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { - { "MACH", & MACH_attr[0] }, - { "PIPE", & PIPE_attr[0] }, + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, @@ -128,8 +129,8 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = /* Instruction set variants. */ static const CGEN_ISA m32r_cgen_isa_table[] = { - { "m32r", 32, 32, 16, 32, }, - { 0 } + { "m32r", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } }; /* Machine variants. */ @@ -137,81 +138,84 @@ static const CGEN_ISA m32r_cgen_isa_table[] = { static const CGEN_MACH m32r_cgen_mach_table[] = { { "m32r", "m32r", MACH_M32R }, { "m32rx", "m32rx", MACH_M32RX }, - { 0 } + { 0, 0, 0 } }; static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = { - { "fp", 13 }, - { "lr", 14 }, - { "sp", 15 }, - { "r0", 0 }, - { "r1", 1 }, - { "r2", 2 }, - { "r3", 3 }, - { "r4", 4 }, - { "r5", 5 }, - { "r6", 6 }, - { "r7", 7 }, - { "r8", 8 }, - { "r9", 9 }, - { "r10", 10 }, - { "r11", 11 }, - { "r12", 12 }, - { "r13", 13 }, - { "r14", 14 }, - { "r15", 15 } + { "fp", 13, {0, {0}}, 0, 0 }, + { "lr", 14, {0, {0}}, 0, 0 }, + { "sp", 15, {0, {0}}, 0, 0 }, + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_gr_names = { & m32r_cgen_opval_gr_names_entries[0], - 19 + 19, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = { - { "psw", 0 }, - { "cbr", 1 }, - { "spi", 2 }, - { "spu", 3 }, - { "bpc", 6 }, - { "bbpsw", 8 }, - { "bbpc", 14 }, - { "cr0", 0 }, - { "cr1", 1 }, - { "cr2", 2 }, - { "cr3", 3 }, - { "cr4", 4 }, - { "cr5", 5 }, - { "cr6", 6 }, - { "cr7", 7 }, - { "cr8", 8 }, - { "cr9", 9 }, - { "cr10", 10 }, - { "cr11", 11 }, - { "cr12", 12 }, - { "cr13", 13 }, - { "cr14", 14 }, - { "cr15", 15 } + { "psw", 0, {0, {0}}, 0, 0 }, + { "cbr", 1, {0, {0}}, 0, 0 }, + { "spi", 2, {0, {0}}, 0, 0 }, + { "spu", 3, {0, {0}}, 0, 0 }, + { "bpc", 6, {0, {0}}, 0, 0 }, + { "bbpsw", 8, {0, {0}}, 0, 0 }, + { "bbpc", 14, {0, {0}}, 0, 0 }, + { "cr0", 0, {0, {0}}, 0, 0 }, + { "cr1", 1, {0, {0}}, 0, 0 }, + { "cr2", 2, {0, {0}}, 0, 0 }, + { "cr3", 3, {0, {0}}, 0, 0 }, + { "cr4", 4, {0, {0}}, 0, 0 }, + { "cr5", 5, {0, {0}}, 0, 0 }, + { "cr6", 6, {0, {0}}, 0, 0 }, + { "cr7", 7, {0, {0}}, 0, 0 }, + { "cr8", 8, {0, {0}}, 0, 0 }, + { "cr9", 9, {0, {0}}, 0, 0 }, + { "cr10", 10, {0, {0}}, 0, 0 }, + { "cr11", 11, {0, {0}}, 0, 0 }, + { "cr12", 12, {0, {0}}, 0, 0 }, + { "cr13", 13, {0, {0}}, 0, 0 }, + { "cr14", 14, {0, {0}}, 0, 0 }, + { "cr15", 15, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_cr_names = { & m32r_cgen_opval_cr_names_entries[0], - 23 + 23, + 0, 0, 0, 0 }; static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = { - { "a0", 0 }, - { "a1", 1 } + { "a0", 0, {0, {0}}, 0, 0 }, + { "a1", 1, {0, {0}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_h_accums = { & m32r_cgen_opval_h_accums_entries[0], - 2 + 2, + 0, 0, 0, 0 }; @@ -240,7 +244,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] = { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } }; #undef A @@ -277,7 +281,7 @@ const CGEN_IFLD m32r_cgen_ifld_table[] = { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } }, { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } }, { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, 0, 0, 0, 0, {0, {0}} } }; #undef A @@ -367,7 +371,7 @@ const CGEN_OPERAND m32r_cgen_operand_table[] = /* accum: accumulator */ { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, - { 0 } + { 0, 0, 0, 0, 0, {0, {0}} } }; #undef A @@ -382,7 +386,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0 }, + { 0, 0, 0, 0, {0, {0}} }, /* add $dr,$sr */ { M32R_INSN_ADD, "add", "add", 16, @@ -1175,9 +1179,11 @@ static void m32r_cgen_rebuild_tables (cd) CGEN_CPU_TABLE *cd; { - int i,n_isas,n_machs; + int i,n_isas; unsigned int isas = cd->isas; +#if 0 unsigned int machs = cd->machs; +#endif cd->int_insn_p = CGEN_INT_INSN_P; @@ -1219,6 +1225,7 @@ m32r_cgen_rebuild_tables (cd) ++n_isas; } +#if 0 /* Does nothing?? */ /* Data derived from the mach spec. */ for (i = 0; i < MAX_MACHS; ++i) if (((1 << i) & machs) != 0) @@ -1227,6 +1234,7 @@ m32r_cgen_rebuild_tables (cd) ++n_machs; } +#endif /* Determine which hw elements are used by MACH. */ build_hw_table (cd); @@ -1338,7 +1346,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) cd->rebuild_tables = m32r_cgen_rebuild_tables; m32r_cgen_rebuild_tables (cd); - /* Initialise flags. */ + /* Default to not allowing signed overflow. */ cd->signed_overflow_ok_p = 0; return (CGEN_CPU_DESC) cd; diff --git a/gnu/usr.bin/binutils/opcodes/m32r-desc.h b/gnu/usr.bin/binutils/opcodes/m32r-desc.h index 7d428072e2a..c94aa03818e 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-desc.h +++ b/gnu/usr.bin/binutils/opcodes/m32r-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -44,18 +44,16 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INT_INSN_P 1 -/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ +/* Maximum nymber of syntax bytes in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands we can't hash on everything up to the space. */ #define CGEN_MNEMONIC_OPERANDS -/* Maximum number of operands any insn or macro-insn has. */ -#define CGEN_MAX_INSN_OPERANDS 16 - /* Maximum number of fields in an instruction. */ -#define CGEN_MAX_IFMT_OPERANDS 7 +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 /* Enums. */ @@ -191,7 +189,7 @@ typedef enum cgen_operand_type { } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS ((int) M32R_OPERAND_MAX) +#define MAX_OPERANDS 26 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 11 diff --git a/gnu/usr.bin/binutils/opcodes/m32r-dis.c b/gnu/usr.bin/binutils/opcodes/m32r-dis.c index d6d53773744..6ad23b63ea1 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-dis.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -68,12 +68,12 @@ do { \ static void print_hash (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; + long value ATTRIBUTE_UNUSED; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "#"); @@ -156,7 +156,7 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) int opindex; PTR xinfo; CGEN_FIELDS *fields; - void const *attrs; + void const *attrs ATTRIBUTE_UNUSED; bfd_vma pc; int length; { @@ -263,12 +263,12 @@ m32r_cgen_init_dis (cd) static void print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; long value; unsigned int attrs; - bfd_vma pc; - int length; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; @@ -289,12 +289,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; bfd_vma value; unsigned int attrs; - bfd_vma pc; - int length; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; @@ -319,11 +319,11 @@ print_address (cd, dis_info, value, attrs, pc, length) static void print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; PTR dis_info; CGEN_KEYWORD *keyword_table; long value; - unsigned int attrs; + unsigned int attrs ATTRIBUTE_UNUSED; { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -374,6 +374,48 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) } } +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + switch (buflen) + { + case 1: + *insn_value = buf[0]; + break; + case 2: + *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); + break; + case 4: + *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); + break; + default: + abort (); + } + + return 0; +} + /* Utility to print an insn. BUF is the base part of the insn, target byte order, BUFLEN bytes long. The result is the size of the insn in bytes or zero for an unknown insn @@ -391,9 +433,13 @@ print_insn (cd, pc, info, buf, buflen) unsigned long insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; - +#if 0 + int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value); + if (rc != 0) + return rc; +#else ex_info.dis_info = info; - ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1; + ex_info.valid = (1 << buflen) - 1; ex_info.insn_bytes = buf; switch (buflen) @@ -410,7 +456,7 @@ print_insn (cd, pc, info, buf, buflen) default: abort (); } - +#endif /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ @@ -441,8 +487,23 @@ print_insn (cd, pc, info, buf, buflen) machine insn and extracts the fields. The second pass prints them. */ - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value, &fields, pc); + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value, &fields, pc); /* length < 0 -> error */ if (length < 0) return length; @@ -466,7 +527,6 @@ print_insn (cd, pc, info, buf, buflen) #ifndef CGEN_PRINT_INSN #define CGEN_PRINT_INSN default_print_insn -#endif static int default_print_insn (cd, pc, info) @@ -488,6 +548,7 @@ default_print_insn (cd, pc, info) return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); } +#endif /* Main entry point. Print one instruction from PC on INFO->STREAM. @@ -499,7 +560,9 @@ print_insn_m32r (pc, info) disassemble_info *info; { static CGEN_CPU_DESC cd = 0; - static prev_isa,prev_mach,prev_endian; + static int prev_isa; + static int prev_mach; + static int prev_endian; int length; int isa,mach; int endian = (info->endian == BFD_ENDIAN_BIG diff --git a/gnu/usr.bin/binutils/opcodes/m32r-ibld.c b/gnu/usr.bin/binutils/opcodes/m32r-ibld.c index 30c3c6a8ce9..31396aa36ce 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-ibld.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-ibld.c @@ -3,7 +3,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. - the resultant file is machine generated, cgen-ibld.in isn't -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -57,6 +57,9 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + /* Operand insertion. */ @@ -183,9 +186,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, if (length == 0) return NULL; +#if 0 if (CGEN_INT_INSN_P && word_offset != 0) abort (); +#endif if (word_length > 32) abort (); @@ -237,9 +242,9 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, int shift; if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; + shift = (word_offset + start + 1) - length; else - shift = word_length - (start + length); + shift = total_length - (word_offset + start + length); *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); } @@ -283,7 +288,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #if CGEN_INT_INSN_P - *buffer = value; + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); #else @@ -313,6 +319,30 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } + +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} /* Operand extraction. */ @@ -444,11 +474,19 @@ static int extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, word_length, total_length, pc, valuep) CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif CGEN_INSN_INT insn_value; unsigned int attrs; unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif long *valuep; { CGEN_INSN_INT value; @@ -461,9 +499,11 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, return 1; } +#if 0 if (CGEN_INT_INSN_P && word_offset != 0) abort (); +#endif if (word_length > 32) abort (); @@ -479,15 +519,15 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, /* Does the value reside in INSN_VALUE? */ - if (word_offset == 0) + if (CGEN_INT_INSN_P || word_offset == 0) { /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; if (CGEN_INSN_LSB0_P) - value = insn_value >> ((start + 1) - length); + value = insn_value >> ((word_offset + start + 1) - length); else - value = insn_value >> (word_length - (start + length)); + value = insn_value >> (total_length - ( word_offset + start + length)); value &= mask; /* sign extend? */ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opc.c b/gnu/usr.bin/binutils/opcodes/m32r-opc.c index a1efecc3c8d..3448e6380be 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-opc.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -28,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "symcat.h" #include "m32r-desc.h" #include "m32r-opc.h" +#include "libiberty.h" /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ @@ -42,131 +43,131 @@ static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] static const CGEN_IFMT ifmt_empty = { - 0, 0, 0x0, { 0 } + 0, 0, 0x0, { { 0 } } }; static const CGEN_IFMT ifmt_add = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_add3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_and3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_or3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_addi = { - 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } }; static const CGEN_IFMT ifmt_addv3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_bc8 = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bc24 = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_beq = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } }; static const CGEN_IFMT ifmt_beqz = { - 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } }; static const CGEN_IFMT ifmt_cmp = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_cmpi = { - 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_cmpz = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_div = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_jc = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ld24 = { - 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 } + 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi16 = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_machi_a = { - 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 } + 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_mvfachi = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_mvfachi_a = { - 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } }; static const CGEN_IFMT ifmt_mvfc = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_mvtachi = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_mvtachi_a = { - 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } }; static const CGEN_IFMT ifmt_mvtc = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_nop = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_rac_dsi = { - 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } + 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } }; static const CGEN_IFMT ifmt_seth = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 } + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } } }; static const CGEN_IFMT ifmt_slli = { - 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 } + 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } } }; static const CGEN_IFMT ifmt_st_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_trap = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 } + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } } }; static const CGEN_IFMT ifmt_satb = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } }; #undef F @@ -183,7 +184,7 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { { 0 } }, + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, /* add $dr,$sr */ { { 0, 0, 0, 0 }, @@ -1000,147 +1001,147 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] static const CGEN_IFMT ifmt_bc8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bc24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_bl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_bcl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bcl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_bnc8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bnc24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_bra8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bra24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_bncl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; static const CGEN_IFMT ifmt_bncl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } }; static const CGEN_IFMT ifmt_ld_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ld_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_ldb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ldb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_ldh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ldh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_ldub_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ldub_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_lduh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_lduh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_pop = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi8a = { - 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } }; static const CGEN_IFMT ifmt_ldi16a = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 } + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_rac_d = { - 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } }; static const CGEN_IFMT ifmt_rac_ds = { - 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } }; static const CGEN_IFMT ifmt_rach_d = { - 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } }; static const CGEN_IFMT ifmt_rach_ds = { - 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } }; static const CGEN_IFMT ifmt_st_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_st_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_stb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_stb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_sth_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; static const CGEN_IFMT ifmt_sth_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } }; static const CGEN_IFMT ifmt_push = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } }; #undef F diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opc.h b/gnu/usr.bin/binutils/opcodes/m32r-opc.h index b98c5f9835c..68fad09f61f 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-opc.h +++ b/gnu/usr.bin/binutils/opcodes/m32r-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/gnu/usr.bin/binutils/opcodes/m32r-opinst.c b/gnu/usr.bin/binutils/opcodes/m32r-opinst.c index 269651f3449..301886efd67 100644 --- a/gnu/usr.bin/binutils/opcodes/m32r-opinst.c +++ b/gnu/usr.bin/binutils/opcodes/m32r-opinst.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c b/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c new file mode 100644 index 00000000000..97c90fb44ad --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/m68hc11-dis.c @@ -0,0 +1,608 @@ +/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <stdio.h> + +#include "ansidecl.h" +#include "opcode/m68hc11.h" +#include "dis-asm.h" + +static const char *const reg_name[] = { + "X", "Y", "SP", "PC" +}; + +static const char *const reg_src_table[] = { + "A", "B", "CCR", "TMP3", "D", "X", "Y", "SP" +}; + +static const char *const reg_dst_table[] = { + "A", "B", "CCR", "TMP2", "D", "X", "Y", "SP" +}; + +#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4) + +static int +read_memory (memaddr, buffer, size, info) + bfd_vma memaddr; + bfd_byte *buffer; + int size; + struct disassemble_info *info; +{ + int status; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = (*info->read_memory_func) (memaddr, buffer, size, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + return 0; +} + + +/* Read the 68HC12 indexed operand byte and print the corresponding mode. + Returns the number of bytes read or -1 if failure. */ +static int +print_indexed_operand (memaddr, info, mov_insn) + bfd_vma memaddr; + struct disassemble_info *info; + int mov_insn; +{ + bfd_byte buffer[4]; + int reg; + int status; + short sval; + int pos = 1; + + status = read_memory (memaddr, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + /* n,r with 5-bits signed constant. */ + if ((buffer[0] & 0x20) == 0) + { + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x1f); + if (sval & 0x10) + sval |= 0xfff0; + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + + /* Auto pre/post increment/decrement. */ + else if ((buffer[0] & 0xc0) != 0xc0) + { + const char *mode; + + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x0f); + if (sval & 0x8) + { + sval |= 0xfff0; + sval = -sval; + mode = "-"; + } + else + { + sval = sval + 1; + mode = "+"; + } + (*info->fprintf_func) (info->stream, "%d,%s%s%s", + (int) sval, + (buffer[0] & 0x10 ? "" : mode), + reg_name[reg], (buffer[0] & 0x10 ? mode : "")); + } + + /* [n,r] 16-bits offset indexed indirect. */ + else if ((buffer[0] & 0x07) == 3) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + (*info->fprintf_func) (info->stream, "[%u,%s]", + sval & 0x0ffff, reg_name[reg]); + } + else if ((buffer[0] & 0x4) == 0) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, + &buffer[1], (buffer[0] & 0x2 ? 2 : 1), info); + if (status != 0) + { + return status; + } + if (buffer[0] & 2) + { + sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF)); + sval &= 0x0FFFF; + pos += 2; + } + else + { + sval = buffer[1] & 0x00ff; + if (buffer[0] & 0x01) + sval |= 0xff00; + pos++; + } + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + else + { + reg = (buffer[0] >> 3) & 0x03; + switch (buffer[0] & 3) + { + case 0: + (*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]); + break; + case 1: + (*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]); + break; + case 2: + (*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]); + break; + case 3: + default: + (*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]); + break; + } + } + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +static int +print_insn (memaddr, info, arch) + bfd_vma memaddr; + struct disassemble_info *info; + int arch; +{ + int status; + bfd_byte buffer[4]; + unsigned char code; + long format, pos, i; + short sval; + const struct m68hc11_opcode *opcode; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = read_memory (memaddr, buffer, 1, info); + if (status != 0) + { + return status; + } + + format = 0; + code = buffer[0]; + pos = 0; + + /* Look for page2,3,4 opcodes. */ + if (code == M6811_OPCODE_PAGE2) + { + pos++; + format = M6811_OP_PAGE2; + } + else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE3; + } + else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE4; + } + + /* We are in page2,3,4; get the real opcode. */ + if (pos == 1) + { + status = read_memory (memaddr + pos, &buffer[1], 1, info); + if (status != 0) + { + return status; + } + code = buffer[1]; + } + + + /* Look first for a 68HC12 alias. All of them are 2-bytes long and + in page 1. There is no operand to print. We read the second byte + only when we have a possible match. */ + if ((arch & cpu6812) && format == 0) + { + int must_read = 1; + + /* Walk the alias table to find a code1+code2 match. */ + for (i = 0; i < m68hc12_num_alias; i++) + { + if (m68hc12_alias[i].code1 == code) + { + if (must_read) + { + status = read_memory (memaddr + pos + 1, + &buffer[1], 1, info); + if (status != 0) + break; + + must_read = 1; + } + if (m68hc12_alias[i].code2 == (unsigned char) buffer[1]) + { + (*info->fprintf_func) (info->stream, "%s", + m68hc12_alias[i].name); + return 2; + } + } + } + } + + pos++; + + /* Scan the opcode table until we find the opcode + with the corresponding page. */ + opcode = m68hc11_opcodes; + for (i = 0; i < m68hc11_num_opcodes; i++, opcode++) + { + int offset; + + if ((opcode->arch & arch) == 0) + continue; + if (opcode->opcode != code) + continue; + if ((opcode->format & OP_PAGE_MASK) != format) + continue; + + if (opcode->format & M6812_OP_REG) + { + int j; + int is_jump; + + if (opcode->format & M6811_OP_JUMP_REL) + is_jump = 1; + else + is_jump = 0; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + for (j = 0; i + j < m68hc11_num_opcodes; j++) + { + if ((opcode[j].arch & arch) == 0) + continue; + if (opcode[j].opcode != code) + continue; + if (is_jump) + { + if (!(opcode[j].format & M6811_OP_JUMP_REL)) + continue; + + if ((opcode[j].format & M6812_OP_IBCC_MARKER) + && (buffer[0] & 0xc0) != 0x80) + continue; + if ((opcode[j].format & M6812_OP_TBCC_MARKER) + && (buffer[0] & 0xc0) != 0x40) + continue; + if ((opcode[j].format & M6812_OP_DBCC_MARKER) + && (buffer[0] & 0xc0) != 0) + continue; + if ((opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) == 0) + break; + if (!(opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) != 0) + break; + continue; + } + if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80) + break; + if ((opcode[j].format & M6812_OP_SEX_MARKER) + && (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7)) + && ((buffer[0] & 0x0f0) <= 0x20)) + break; + if (opcode[j].format & M6812_OP_TFR_MARKER + && !(buffer[0] & 0x80)) + break; + } + if (i + j < m68hc11_num_opcodes) + opcode = &opcode[j]; + } + + /* We have found the opcode. Extract the operand and print it. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + format = opcode->format; + if (format & (M6811_OP_MASK | M6811_OP_BITMASK + | M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + { + (*info->fprintf_func) (info->stream, "\t"); + } + + /* The movb and movw must be handled in a special way... */ + offset = 0; + if (format & (M6812_OP_IDX_P2 | M6812_OP_IND16_P2)) + { + if ((format & M6812_OP_IDX_P2) + && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_IND16))) + offset = 1; + } + + /* Operand with one more byte: - immediate, offset, + direct-low address. */ + if (format & + (M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT)) + { + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + offset = -1; + if (format & M6811_OP_IMM8) + { + (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]); + format &= ~M6811_OP_IMM8; + } + else if (format & M6811_OP_IX) + { + /* Offsets are in range 0..255, print them unsigned. */ + (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF); + format &= ~M6811_OP_IX; + } + else if (format & M6811_OP_IY) + { + (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF); + format &= ~M6811_OP_IY; + } + else if (format & M6811_OP_DIRECT) + { + (*info->fprintf_func) (info->stream, "*"); + (*info->print_address_func) (buffer[0] & 0x0FF, info); + format &= ~M6811_OP_DIRECT; + } + } + +#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2) + /* Analyze the 68HC12 indexed byte. */ + if (format & M6812_INDEXED_FLAGS) + { + status = print_indexed_operand (memaddr + pos, info, 0); + if (status < 0) + { + return status; + } + pos += status; + } + + /* 68HC12 dbcc/ibcc/tbcc operands. */ + if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL)) + { + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + (*info->fprintf_func) (info->stream, "%s,", + reg_src_table[buffer[0] & 0x07]); + sval = buffer[1] & 0x0ff; + if (buffer[0] & 0x10) + sval |= 0xff00; + + pos += 2; + (*info->print_address_func) (memaddr + pos + sval, info); + format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL); + } + else if (format & (M6812_OP_REG | M6812_OP_REG_2)) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + (*info->fprintf_func) (info->stream, "%s,%s", + reg_src_table[(buffer[0] >> 4) & 7], + reg_dst_table[(buffer[0] & 7)]); + } + + /* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately + and in that order. The brset/brclr insn have a bitmask and then + a relative branch offset. */ + if (format & M6811_OP_BITMASK) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos++; + (*info->fprintf_func) (info->stream, " #$%02x%s", + buffer[0] & 0x0FF, + (format & M6811_OP_JUMP_REL ? " " : "")); + format &= ~M6811_OP_BITMASK; + } + if (format & M6811_OP_JUMP_REL) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0]; + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6811_OP_JUMP_REL; + } + else if (format & M6812_OP_JUMP_REL16) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + if (val & 0x8000) + val |= 0xffff0000; + + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6812_OP_JUMP_REL16; + } + if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) + { + int val; + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + if (format & M6812_OP_IDX_P2) + offset = -2; + else + offset = 0; + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + if (format & M6811_OP_IMM16) + { + format &= ~M6811_OP_IMM16; + (*info->fprintf_func) (info->stream, "#"); + } + else + format &= ~M6811_OP_IND16; + + (*info->print_address_func) (val, info); + } + + if (format & M6812_OP_IDX_P2) + { + (*info->fprintf_func) (info->stream, ", "); + status = print_indexed_operand (memaddr + pos + offset, info, 1); + if (status < 0) + return status; + pos += status; + } + + if (format & M6812_OP_IND16_P2) + { + int val; + + (*info->fprintf_func) (info->stream, ", "); + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + (*info->print_address_func) (val, info); + } + +#ifdef DEBUG + /* Consistency check. 'format' must be 0, so that we have handled + all formats; and the computed size of the insn must match the + opcode table content. */ + if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2)) + { + (*info->fprintf_func) (info->stream, "; Error, format: %x", format); + } + if (pos != opcode->size) + { + (*info->fprintf_func) (info->stream, "; Error, size: %d expect %d", + pos, opcode->size); + } +#endif + return pos; + } + + /* Opcode not recognized. */ + if (format == M6811_OP_PAGE2 && arch & cpu6812 + && ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff))) + (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff); + + else if (format == M6811_OP_PAGE2) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE2, code); + else if (format == M6811_OP_PAGE3) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE3, code); + else if (format == M6811_OP_PAGE4) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE4, code); + else + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", code); + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +int +print_insn_m68hc11 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6811); +} + +int +print_insn_m68hc12 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6812); +} diff --git a/gnu/usr.bin/binutils/opcodes/m68hc11-opc.c b/gnu/usr.bin/binutils/opcodes/m68hc11-opc.c new file mode 100644 index 00000000000..1e37971ee81 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/m68hc11-opc.c @@ -0,0 +1,1074 @@ +/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +*/ + +#include <stdio.h> +#include "ansidecl.h" +#include "opcode/m68hc11.h" + +#define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) + +/* Combination of CCR flags. */ +#define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT +#define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT +#define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT +#define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT +#define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT +#define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT +#define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT +#define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT + +/* Flags when the insn only changes some CCR flags. */ +#define CHG_NONE 0,0,0 +#define CHG_Z 0,0,M6811_Z_BIT +#define CHG_C 0,0,M6811_C_BIT +#define CHG_ZVC 0,0,M6811_ZVC_BIT +#define CHG_NZC 0,0,M6811_NZC_BIT +#define CHG_NZV 0,0,M6811_NZV_BIT +#define CHG_NZVC 0,0,M6811_NZVC_BIT +#define CHG_HNZVC 0,0,M6811_HNZVC_BIT +#define CHG_ALL 0,0,0xff + +/* The insn clears and changes some flags. */ +#define CLR_I 0,M6811_I_BIT,0 +#define CLR_C 0,M6811_C_BIT,0 +#define CLR_V 0,M6811_V_BIT,0 +#define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT +#define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT +#define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT +#define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */ +#define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT + +/* The insn sets some flags. */ +#define SET_I M6811_I_BIT,0,0 +#define SET_C M6811_C_BIT,0,0 +#define SET_V M6811_V_BIT,0,0 +#define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0 +#define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT +#define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT + +#define _M 0xff +#define OP_NONE M6811_OP_NONE +#define OP_PAGE2 M6811_OP_PAGE2 +#define OP_PAGE3 M6811_OP_PAGE3 +#define OP_PAGE4 M6811_OP_PAGE4 +#define OP_IMM8 M6811_OP_IMM8 +#define OP_IMM16 M6811_OP_IMM16 +#define OP_IX M6811_OP_IX +#define OP_IY M6811_OP_IY +#define OP_IND16 M6811_OP_IND16 +#define OP_IDX M6812_OP_IDX +#define OP_IDX_1 M6812_OP_IDX_1 +#define OP_IDX_2 M6812_OP_IDX_2 +#define OP_D_IDX M6812_OP_D_IDX +#define OP_D_IDX_2 M6812_OP_D_IDX_2 +#define OP_DIRECT M6811_OP_DIRECT +#define OP_BITMASK M6811_OP_BITMASK +#define OP_JUMP_REL M6811_OP_JUMP_REL +#define OP_JUMP_REL16 M6812_OP_JUMP_REL16 +#define OP_REG M6812_OP_REG +#define OP_REG_1 M6812_OP_REG +#define OP_REG_2 M6812_OP_REG_2 +#define OP_IDX_p2 M6812_OP_IDX_P2 +#define OP_IND16_p2 M6812_OP_IND16_P2 +#define OP_TRAP_ID M6812_OP_TRAP_ID +#define OP_EXG_MARKER M6812_OP_EXG_MARKER +#define OP_TFR_MARKER M6812_OP_TFR_MARKER +#define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER) +#define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER) +#define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER) + +/* + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + +-- cpu + Name -+ +------- Insn CCR changes + Format ------+ +----------- Max # cycles + Size --------------------+ +--------------- Min # cycles + +--------------------- Opcode +*/ +const struct m68hc11_opcode m68hc11_opcodes[] = { + { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 }, + { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 }, + { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 }, + { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 }, + + { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 }, + { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 }, + { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 }, + { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 }, + { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 }, + { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 }, + { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + + { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 }, + + { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 }, + { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 }, + { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + + { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811}, + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK + | OP_JUMP_REL + | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 }, + + { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK + | OP_JUMP_REL + | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 }, + + + { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 }, + { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 }, + + { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "call", OP_IND16, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_1, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_2, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX_2, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + + { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, + { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, + + { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 }, + { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 }, + + { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + + { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + + { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 }, + + { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + + { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + + { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 }, + { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 }, + { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 }, + { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + + { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 }, + { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 }, + { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 }, + { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 }, + { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 }, + { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + + /* After 'daa', the Z flag is undefined. Mark it as changed. */ + { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 }, + { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 }, + + { "dbeq", OP_DBEQ_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "dbne", OP_DBNE_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 }, + + { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 }, + + { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 }, + { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 }, + { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 }, + { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 }, + + { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 }, + { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 }, + { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 }, + + { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 }, + { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 }, + { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 }, + + { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + + { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + + { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + + { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + + { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 }, + { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 }, + + { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 }, + + { "exg", OP_EXG_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811}, + { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 }, + + { "ibeq", OP_IBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "ibne", OP_IBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811}, + { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 }, + { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 }, + + { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 }, + + { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 }, + { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 }, + { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 }, + { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 }, + + { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 }, + + { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 }, + { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, + { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, + + { "jmp", OP_IND16, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, + { "jmp", OP_IND16, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, + + { "jsr", OP_DIRECT, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, + { "jsr", OP_IND16, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_DIRECT, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IND16, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 }, + + { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 }, + { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 }, + { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 }, + { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 }, + { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 }, + { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 }, + { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 }, + { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 }, + { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 }, + { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 }, + { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 }, + { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 }, + { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 }, + { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 }, + + { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + + { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + + { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 }, + + { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 }, + { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 }, + { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + + { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 }, + { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 }, + + { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + + { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + + { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 }, + + { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + + { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + + { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 }, + { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 }, + + { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 }, + + { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 }, + { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 }, + + { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 }, + { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 }, + { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + + { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 }, + { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 }, + + { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 }, + + { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 }, + { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 }, + { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 }, + { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 }, + { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 }, + { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 }, + + { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 }, + { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 }, + { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 }, + { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 }, + { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 }, + { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 }, + + { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 }, + { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 }, + + { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 }, + { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + + { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 }, + { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 }, + { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 }, + { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 }, + + { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 }, + { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 }, + { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + + { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 }, + { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811}, + { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812}, + { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 }, + { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 }, + + { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 }, + { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 }, + + { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 }, + { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 }, + { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 }, + + { "sex", M6812_OP_SEX_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 }, + { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 }, + + { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 }, + { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 }, + { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 }, + { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 }, + { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 }, + { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + + { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 }, + + { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 }, + + { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + + { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 }, + + { "tbeq", OP_TBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 }, + + { "tbne", OP_TBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tfr", OP_TFR_MARKER + | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 }, + + { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 }, + { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 }, + { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 }, + { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 }, + + { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 }, + + { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 }, + + { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 }, + { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 } +}; + +const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes); + +/* The following alias table provides source compatibility to + move from 68HC11 assembly to 68HC12. */ +const struct m68hc12_opcode_alias m68hc12_alias[] = { + { "abx", "leax b,x", 2, 0x1a, 0xe5 }, + { "aby", "leay b,y", 2, 0x19, 0xed }, + { "clc", "andcc #$fe", 2, 0x10, 0xfe }, + { "cli", "andcc #$ef", 2, 0x10, 0xef }, + { "clv", "andcc #$fd", 2, 0x10, 0xfd }, + { "des", "leas -1,sp", 2, 0x1b, 0x9f }, + { "ins", "leas 1,sp", 2, 0x1b, 0x81 }, + { "sec", "orcc #$01", 2, 0x14, 0x01 }, + { "sei", "orcc #$10", 2, 0x14, 0x10 }, + { "sev", "orcc #$02", 2, 0x14, 0x02 }, + { "tap", "tfr a,ccr", 2, 0xb7, 0x02 }, + { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 }, + { "tsx", "tfr sp,x", 2, 0xb7, 0x75 }, + { "tsy", "tfr sp,y", 2, 0xb7, 0x76 }, + { "txs", "tfr x,sp", 2, 0xb7, 0x57 }, + { "tys", "tfr y,sp", 2, 0xb7, 0x67 }, + { "xgdx","exg d,x", 2, 0xb7, 0xc5 }, + { "xgdy","exg d,y", 2, 0xb7, 0xc6 } +}; +const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias); diff --git a/gnu/usr.bin/binutils/opcodes/mcore-dis.c b/gnu/usr.bin/binutils/opcodes/mcore-dis.c index 7ebfd37a569..bbf0f977209 100644 --- a/gnu/usr.bin/binutils/opcodes/mcore-dis.c +++ b/gnu/usr.bin/binutils/opcodes/mcore-dis.c @@ -1,5 +1,5 @@ /* Disassemble Motorola M*Core instructions. - Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc. + Copyright 1993, 1999, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -29,7 +29,7 @@ static const unsigned short imsk[] = /* O0 */ 0xFFFF, /* OT */ 0xFFFC, /* O1 */ 0xFFF0, - /* OC */ 0xFFE0, + /* OC */ 0xFE00, /* O2 */ 0xFF00, /* X1 */ 0xFFF0, /* OI */ 0xFE00, @@ -169,7 +169,7 @@ print_insn_mcore (memaddr, info) if (strcmp (op->name, "bsr") == 0) { - /* for bsr, we'll try to get a symbol for the target */ + /* For bsr, we'll try to get a symbol for the target. */ val = memaddr + 2 + (val << 1); if (info->print_address_func && val != 0) @@ -268,12 +268,12 @@ print_insn_mcore (memaddr, info) break; default: - /* if the disassembler lags the instruction set */ + /* If the disassembler lags the instruction set. */ fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); break; } } - /* Say how many bytes we consumed? */ + /* Say how many bytes we consumed. */ return 2; } diff --git a/gnu/usr.bin/binutils/opcodes/mcore-opc.h b/gnu/usr.bin/binutils/opcodes/mcore-opc.h index 6ff05eeca16..7e4f539dd44 100644 --- a/gnu/usr.bin/binutils/opcodes/mcore-opc.h +++ b/gnu/usr.bin/binutils/opcodes/mcore-opc.h @@ -1,5 +1,5 @@ /* Assembler instructions for Motorola's Mcore processor - Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify diff --git a/gnu/usr.bin/binutils/opcodes/mips16-opc.c b/gnu/usr.bin/binutils/opcodes/mips16-opc.c index ab2d7c0795a..d7fcfc24ac4 100644 --- a/gnu/usr.bin/binutils/opcodes/mips16-opc.c +++ b/gnu/usr.bin/binutils/opcodes/mips16-opc.c @@ -1,5 +1,5 @@ /* mips16-opc.c. Mips16 opcode table. - Copyright 1996, 1997 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. Contributed by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -62,164 +62,165 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define T3 INSN_3900 -const struct mips_opcode mips16_opcodes[] = { -{"nop", "", 0x6500, 0xffff, RD_Z }, /* move $0,$Z */ -{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC }, -{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO }, -{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x }, -{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x }, -{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP }, -{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP }, -{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC }, -{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP }, -{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y }, -{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x }, -{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x }, -{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP }, -{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP }, -{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC }, -{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP }, -{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y }, -{"b", "q", 0x1000, 0xf800, BR}, -{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO }, -{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO }, -{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x }, -{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO }, -{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO }, -{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO }, -{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO }, -{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO }, -{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO }, -{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO }, -{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO }, -{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO }, -{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO }, -{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO }, -{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO }, -{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO }, -{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO }, -{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO }, -{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO }, -{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO }, -{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO }, -{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x }, -{"break", "6", 0xe805, 0xf81f, TRAP }, -{"bteqz", "p", 0x6000, 0xff00, BR|RD_T }, -{"btnez", "p", 0x6100, 0xff00, BR|RD_T }, -{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x }, -{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y }, -{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x }, -{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, -{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, -{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +const struct mips_opcode mips16_opcodes[] = +{ +{"nop", "", 0x6500, 0xffff, RD_Z, 0 }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0 }, +{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, +{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, +{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0 }, +{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, +{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, +{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, +{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0 }, +{"b", "q", 0x1000, 0xf800, BR, 0 }, +{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0 }, +{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0 }, +{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0 }, +{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0 }, +{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0 }, +{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0 }, +{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0 }, +{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0 }, +{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0 }, +{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0 }, +{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0 }, +{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0 }, +{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0 }, +{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0 }, +{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0 }, +{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0 }, +{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0 }, +{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0 }, +{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0 }, +{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0 }, +{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0 }, +{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0 }, +{"break", "6", 0xe805, 0xf81f, TRAP, 0 }, +{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0 }, +{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0 }, +{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, +{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, +{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, {"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 }, -{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, -{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, -{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, {"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0 }, {"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO }, -{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO }, -{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO }, -{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0 }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0 }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0 }, +{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 }, {"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, {"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, {"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0 }, {"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0 }, {"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 }, +{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 }, {"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, {"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 }, +{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 }, {"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, {"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 }, +{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 }, {"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, {"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 }, -{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO }, -{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO }, -{"exit", "L", 0xed09, 0xff1f, TRAP }, -{"exit", "L", 0xee09, 0xff1f, TRAP }, -{"exit", "L", 0xef09, 0xff1f, TRAP }, -{"entry", "l", 0xe809, 0xf81f, TRAP }, -{"extend", "e", 0xf000, 0xf800, 0 }, -{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, -{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, -{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, -{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, -{"jal", "a", 0x1800, 0xfc00, UBD|WR_31 }, -{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31 }, -{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x }, -{"jr", "R", 0xe820, 0xffff, UBD|RD_31 }, -{"j", "x", 0xe800, 0xf8ff, UBD|RD_x }, -{"j", "R", 0xe820, 0xffff, UBD|RD_31 }, -{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x }, -{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x }, -{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 }, -{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, -{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, -{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 }, -{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x }, -{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x }, -{"li", "x,U", 0x6800, 0xf800, WR_x }, -{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x }, -{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC }, -{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC }, -{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP }, -{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 }, -{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI }, -{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO }, -{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X }, -{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z }, -{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO }, -{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y }, -{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y }, -{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y }, -{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO }, -{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, -{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO }, -{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x }, -{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 }, -{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC }, -{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x }, -{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x }, -{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y }, -{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x }, -{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x }, -{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y }, -{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x }, -{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x }, -{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y }, -{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x }, -{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x }, -{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y }, -{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x }, -{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x }, -{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y }, -{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x }, -{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y }, -{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO }, -{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO }, -{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x }, -{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP }, -{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP }, -{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y }, +{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0 }, +{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0 }, +{"exit", "L", 0xed09, 0xff1f, TRAP, 0 }, +{"exit", "L", 0xee09, 0xff1f, TRAP, 0 }, +{"exit", "L", 0xef09, 0xff1f, TRAP, 0 }, +{"entry", "l", 0xe809, 0xf81f, TRAP, 0 }, +{"extend", "e", 0xf000, 0xf800, 0, 0 }, +{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0 }, +{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0 }, +{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, +{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, +{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, +{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, +{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0 }, +{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0 }, +{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 }, +{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 }, +{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0 }, +{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0 }, +{"li", "x,U", 0x6800, 0xf800, WR_x, 0 }, +{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0 }, +{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0 }, +{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0 }, +{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0 }, +{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0 }, +{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0 }, +{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0 }, +{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0 }, +{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0 }, +{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0 }, +{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0 }, +{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0 }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0 }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0 }, +{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0 }, +{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0 }, +{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0 }, +{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0 }, +{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, +{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, +{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, +{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, +{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0 }, +{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0 }, +{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0 }, +{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0 }, +{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0 }, +{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0 }, +{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0 }, +{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0 }, +{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0 }, }; const int bfd_mips16_num_opcodes = diff --git a/gnu/usr.bin/binutils/opcodes/opintl.h b/gnu/usr.bin/binutils/opcodes/opintl.h index a5901604081..d19b66449ee 100644 --- a/gnu/usr.bin/binutils/opcodes/opintl.h +++ b/gnu/usr.bin/binutils/opcodes/opintl.h @@ -1,5 +1,5 @@ /* opintl.h - opcodes specific header for gettext code. - Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. Written by Tom Tromey <tromey@cygnus.com> @@ -12,6 +12,19 @@ #ifdef ENABLE_NLS # include <libintl.h> +/* Note the use of dgetext() and PACKAGE here, rather than gettext(). + + This is because the code in this directory is used to build a library which + will be linked with code in other directories to form programs. We want to + maintain a seperate translation file for this directory however, rather + than being forced to merge it with that of any program linked to + libopcodes. This is a library, so it cannot depend on the catalog + currently loaded. + + In order to do this, we have to make sure that when we extract messages we + use the OPCODES domain rather than the domain of the program that included + the opcodes library, (eg OBJDUMP). Hence we use dgettext (PACKAGE, String) + and define PACKAGE to be 'opcodes'. (See the code in configure). */ # define _(String) dgettext (PACKAGE, String) # ifdef gettext_noop # define N_(String) gettext_noop (String) @@ -19,12 +32,11 @@ # define N_(String) (String) # endif #else -/* Stubs that do something close enough. */ -# define textdomain(String) (String) -# define gettext(String) (String) -# define dgettext(Domain,Message) (Message) -# define dcgettext(Domain,Message,Type) (Message) -# define bindtextdomain(Domain,Directory) (Domain) +# define gettext(Msgid) (Msgid) +# define dgettext(Domainname, Msgid) (Msgid) +# define dcgettext(Domainname, Msgid, Category) (Msgid) +# define textdomain(Domainname) while (0) /* nothing */ +# define bindtextdomain(Domainname, Dirname) while (0) /* nothing */ # define _(String) (String) # define N_(String) (String) #endif diff --git a/gnu/usr.bin/binutils/opcodes/pj-dis.c b/gnu/usr.bin/binutils/opcodes/pj-dis.c index dc6ab2592c1..816b6175b62 100644 --- a/gnu/usr.bin/binutils/opcodes/pj-dis.c +++ b/gnu/usr.bin/binutils/opcodes/pj-dis.c @@ -1,5 +1,5 @@ /* pj-dis.c -- Disassemble picoJava instructions. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright 1999, 2000 Free Software Foundation, Inc. Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify @@ -17,8 +17,8 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include "sysdep.h" #include <stdio.h> +#include "sysdep.h" #include "opcode/pj.h" #include "dis-asm.h" diff --git a/gnu/usr.bin/binutils/opcodes/pj-opc.c b/gnu/usr.bin/binutils/opcodes/pj-opc.c index 0eabc647f6c..ca2a867482a 100644 --- a/gnu/usr.bin/binutils/opcodes/pj-opc.c +++ b/gnu/usr.bin/binutils/opcodes/pj-opc.c @@ -1,5 +1,5 @@ /* pj-opc.c -- Definitions for picoJava opcodes. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright 1999, 2000 Free Software Foundation, Inc. Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify diff --git a/gnu/usr.bin/binutils/opcodes/po/POTFILES.in b/gnu/usr.bin/binutils/opcodes/po/POTFILES.in index f88ddb1c381..f27d27afef6 100644 --- a/gnu/usr.bin/binutils/opcodes/po/POTFILES.in +++ b/gnu/usr.bin/binutils/opcodes/po/POTFILES.in @@ -2,6 +2,7 @@ a29k-dis.c alpha-dis.c alpha-opc.c arc-dis.c +arc-ext.c arc-opc.c arm-dis.c arm-opc.h @@ -9,12 +10,14 @@ avr-dis.c cgen-asm.c cgen-dis.c cgen-opc.c +cris-dis.c +cris-opc.c d10v-dis.c d10v-opc.c d30v-dis.c d30v-opc.c -disassemble.c dis-buf.c +disassemble.c fr30-asm.c fr30-desc.c fr30-desc.h @@ -29,7 +32,20 @@ hppa-dis.c i370-dis.c i370-opc.c i386-dis.c +i860-dis.c i960-dis.c +ia64-asmtab.c +ia64-asmtab.h +ia64-dis.c +ia64-gen.c +ia64-opc-a.c +ia64-opc-b.c +ia64-opc-d.c +ia64-opc-f.c +ia64-opc-i.c +ia64-opc-m.c +ia64-opc.c +ia64-opc.h m10200-dis.c m10200-opc.c m10300-dis.c @@ -42,14 +58,16 @@ m32r-ibld.c m32r-opc.c m32r-opc.h m32r-opinst.c +m68hc11-dis.c +m68hc11-opc.c m68k-dis.c m68k-opc.c m88k-dis.c mcore-dis.c mcore-opc.h -mips16-opc.c mips-dis.c mips-opc.c +mips16-opc.c ns32k-dis.c pj-dis.c pj-opc.c @@ -61,6 +79,8 @@ sparc-dis.c sparc-opc.c sysdep.h tic30-dis.c +tic54x-dis.c +tic54x-opc.c tic80-dis.c tic80-opc.c v850-dis.c @@ -69,5 +89,5 @@ vax-dis.c w65-dis.c w65-opc.h z8k-dis.c -z8kgen.c z8k-opc.h +z8kgen.c diff --git a/gnu/usr.bin/binutils/opcodes/po/opcodes.pot b/gnu/usr.bin/binutils/opcodes/po/opcodes.pot index c5c26b891a3..3336bbd29da 100644 --- a/gnu/usr.bin/binutils/opcodes/po/opcodes.pot +++ b/gnu/usr.bin/binutils/opcodes/po/opcodes.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-04-04 22:10+0930\n" +"POT-Creation-Date: 2001-01-11 12:44-0800\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -22,58 +22,49 @@ msgstr "" msgid "jump hint unaligned" msgstr "" -#: arc-dis.c:231 -msgid "*unknown*" -msgstr "" - -#: arc-opc.c:629 -msgid "unable to fit different valued constants into instruction" -msgstr "" - -#: arc-opc.c:639 -msgid "auxiliary register not allowed here" -msgstr "" - -#: arc-opc.c:652 -#, c-format -msgid "invalid register number `%d'" -msgstr "" - -#: arc-opc.c:775 -#, c-format -msgid "value won't fit in range %ld - %ld" -msgstr "" - -#: arc-opc.c:871 -msgid "branch address not on 4 byte boundary" +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" msgstr "" -#: arm-dis.c:470 +#: arm-dis.c:489 msgid "<illegal precision>" msgstr "" -#: arm-dis.c:882 +#: arm-dis.c:904 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" -#: arm-dis.c:889 +#: arm-dis.c:911 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:1053 +#: arm-dis.c:1083 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" "the -M switch:\n" msgstr "" +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + #: cgen-asm.c:224 msgid "unrecognized keyword/register name" msgstr "" -#: cgen-asm.c:332 fr30-ibld.c:223 m32r-ibld.c:227 +#: cgen-asm.c:332 fr30-ibld.c:232 m32r-ibld.c:232 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" @@ -83,7 +74,7 @@ msgstr "" msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" -#: d30v-dis.c:305 +#: d30v-dis.c:306 #, c-format msgid "<unknown register %d>" msgstr "" @@ -105,93 +96,100 @@ msgid "Unrecognized field %d while parsing.\n" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:447 m32r-asm.c:377 m32r-asm.c:381 -#: m32r-asm.c:455 +#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:449 m32r-asm.c:377 m32r-asm.c:381 +#: m32r-asm.c:457 msgid "unrecognized instruction" msgstr "" -#. Syntax char didn't match. Can't be this insn. -#. FIXME: would like to return something like -#. "expected char `c'" #: fr30-asm.c:415 m32r-asm.c:423 -msgid "syntax error" +#, c-format +msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:441 m32r-asm.c:449 +#: fr30-asm.c:443 m32r-asm.c:451 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:534 m32r-asm.c:552 +#: fr30-asm.c:551 m32r-asm.c:559 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:537 m32r-asm.c:555 +#: fr30-asm.c:554 m32r-asm.c:562 #, c-format msgid "bad instruction `%.50s'" msgstr "" +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 +msgid "*unknown*" +msgstr "" + #: fr30-dis.c:300 m32r-dis.c:239 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:210 m32r-ibld.c:211 +#: fr30-ibld.c:216 m32r-ibld.c:216 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:745 m32r-ibld.c:679 +#: fr30-ibld.c:790 m32r-ibld.c:719 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:947 m32r-ibld.c:809 +#: fr30-ibld.c:994 m32r-ibld.c:849 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1091 m32r-ibld.c:914 +#: fr30-ibld.c:1138 m32r-ibld.c:954 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1220 m32r-ibld.c:1004 +#: fr30-ibld.c:1267 m32r-ibld.c:1044 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1349 m32r-ibld.c:1097 +#: fr30-ibld.c:1396 m32r-ibld.c:1137 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1471 m32r-ibld.c:1183 +#: fr30-ibld.c:1518 m32r-ibld.c:1223 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:404 +#: h8300-dis.c:380 #, c-format msgid "Hmmmm %x" msgstr "" -#: h8300-dis.c:416 +#: h8300-dis.c:391 #, c-format msgid "Don't understand %x \n" msgstr "" -#: h8500-dis.c:139 +#: h8500-dis.c:141 #, c-format msgid "can't cope with insert %d\n" msgstr "" -#. Couldn't understand anything -#: h8500-dis.c:344 +#. Couldn't understand anything. +#: h8500-dis.c:348 #, c-format msgid "%02x\t\t*unknown*" msgstr "" +#: i386-dis.c:2740 +msgid "<internal disassembler error>" +msgstr "" + #: m10200-dis.c:199 #, c-format msgid "unknown\t0x%02x" @@ -202,27 +200,27 @@ msgstr "" msgid "unknown\t0x%04lx" msgstr "" -#: m10300-dis.c:680 +#: m10300-dis.c:685 #, c-format msgid "unknown\t0x%04x" msgstr "" -#: m68k-dis.c:410 +#: m68k-dis.c:412 #, c-format msgid "<internal error in opcode table: %s %s>\n" msgstr "" -#: m68k-dis.c:988 +#: m68k-dis.c:990 #, c-format msgid "<function code %d>" msgstr "" -#: m88k-dis.c:273 +#: m88k-dis.c:274 #, c-format msgid "# <dis error: %08x>" msgstr "" -#: mips-dis.c:237 +#: mips-dis.c:273 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" @@ -237,50 +235,50 @@ msgstr "" msgid "$<undefined>" msgstr "" -#: ppc-opc.c:586 ppc-opc.c:617 +#: ppc-opc.c:619 ppc-opc.c:650 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:619 +#: ppc-opc.c:652 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:674 +#: ppc-opc.c:707 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:709 ppc-opc.c:746 +#: ppc-opc.c:742 ppc-opc.c:779 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:815 +#: ppc-opc.c:848 msgid "value out of range" msgstr "" -#: ppc-opc.c:889 +#: ppc-opc.c:922 msgid "index register in load range" msgstr "" -#: ppc-opc.c:904 +#: ppc-opc.c:937 msgid "invalid register operand when updating" msgstr "" #. Mark as non-valid instruction -#: sparc-dis.c:744 +#: sparc-dis.c:748 msgid "unknown" msgstr "" -#: sparc-dis.c:816 +#: sparc-dis.c:823 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:827 +#: sparc-dis.c:834 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:876 +#: sparc-dis.c:883 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" diff --git a/gnu/usr.bin/binutils/opcodes/tic30-dis.c b/gnu/usr.bin/binutils/opcodes/tic30-dis.c index 5ccf893f2f2..67956f7a380 100644 --- a/gnu/usr.bin/binutils/opcodes/tic30-dis.c +++ b/gnu/usr.bin/binutils/opcodes/tic30-dis.c @@ -1,5 +1,5 @@ /* Disassembly routines for TMS320C30 architecture - Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) This program is free software; you can redistribute it and/or modify @@ -27,10 +27,10 @@ #define PARALLEL_INSN 2 /* Gets the type of instruction based on the top 2 or 3 bits of the - instruction word. */ + instruction word. */ #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) -/* Instruction types. */ +/* Instruction types. */ #define TWO_OPERAND_1 0x00000000 #define TWO_OPERAND_2 0x40000000 #define THREE_OPERAND 0x20000000 @@ -38,14 +38,14 @@ #define MUL_ADDS 0x80000000 #define BRANCHES 0x60000000 -/* Specific instruction id bits. */ +/* Specific instruction id bits. */ #define NORMAL_IDEN 0x1F800000 #define PAR_STORE_IDEN 0x3E000000 #define MUL_ADD_IDEN 0x2C000000 #define BR_IMM_IDEN 0x1F000000 #define BR_COND_IDEN 0x1C3F0000 -/* Addressing modes. */ +/* Addressing modes. */ #define AM_REGISTER 0x00000000 #define AM_DIRECT 0x00200000 #define AM_INDIRECT 0x00400000 @@ -56,15 +56,15 @@ #define REG_AR0 0x08 #define LDP_INSN 0x08700000 -/* TMS320C30 program counter for current instruction. */ +/* TMS320C30 program counter for current instruction. */ static unsigned int _pc; struct instruction - { - int type; - template *tm; - partemplate *ptm; - }; +{ + int type; + template *tm; + partemplate *ptm; +}; int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); int print_two_operand @@ -85,15 +85,14 @@ print_insn_tic30 (pc, info) disassemble_info *info; { unsigned long insn_word; - struct instruction insn = - {0, NULL, NULL}; + struct instruction insn = { 0, NULL, NULL }; bfd_vma bufaddr = pc - info->buffer_vma; - /* Obtain the current instruction word from the buffer. */ + /* Obtain the current instruction word from the buffer. */ insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); _pc = pc / 4; /* Get the instruction refered to by the current instruction word - and print it out based on its type. */ + and print it out based on its type. */ if (!get_tic30_instruction (insn_word, &insn)) return -1; switch (GET_TYPE (insn_word)) @@ -249,7 +248,7 @@ print_two_operand (info, insn_word, insn) if (insn->tm->opcode_modifier == AddressMode) { int src_op, dest_op; - /* Determine whether instruction is a store or a normal instruction. */ + /* Determine whether instruction is a store or a normal instruction. */ if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) { src_op = 1; @@ -260,14 +259,14 @@ print_two_operand (info, insn_word, insn) src_op = 0; dest_op = 1; } - /* Get the destination register. */ + /* Get the destination register. */ if (insn->tm->operands == 2) get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); - /* Get the source operand based on addressing mode. */ + /* Get the source operand based on addressing mode. */ switch (insn_word & AddressMode) { case AM_REGISTER: - /* Check for the NOP instruction before getting the operand. */ + /* Check for the NOP instruction before getting the operand. */ if ((insn->tm->operand_types[0] & NotReq) == 0) get_register_operand ((insn_word & 0x0000001F), operand[src_op]); break; @@ -278,7 +277,7 @@ print_two_operand (info, insn_word, insn) get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); break; case AM_IMM: - /* Get the value of the immediate operand based on variable type. */ + /* Get the value of the immediate operand based on variable type. */ switch (insn->tm->imm_arg_type) { case Imm_Float: @@ -294,7 +293,7 @@ print_two_operand (info, insn_word, insn) default: return 0; } - /* Handle special case for LDP instruction. */ + /* Handle special case for LDP instruction. */ if ((insn_word & 0xFFFFFF00) == LDP_INSN) { strcpy (name, "ldp"); @@ -303,7 +302,7 @@ print_two_operand (info, insn_word, insn) } } } - /* Handle case for stack and rotate instructions. */ + /* Handle case for stack and rotate instructions. */ else if (insn->tm->operands == 1) { if (insn->tm->opcode_modifier == StackOp) @@ -311,7 +310,7 @@ print_two_operand (info, insn_word, insn) get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); } } - /* Output instruction to stream. */ + /* Output instruction to stream. */ info->fprintf_func (info->stream, " %s %s%c%s", name, operand[0][0] ? operand[0] : "", operand[1][0] ? ',' : ' ', @@ -385,7 +384,7 @@ print_par_insn (info, insn_word, insn) if (insn->ptm == NULL) return 0; /* Parse out the names of each of the parallel instructions from the - q_insn1_insn2 format. */ + q_insn1_insn2 format. */ name1 = (char *) strdup (insn->ptm->name + 2); name2 = ""; len = strlen (name1); @@ -398,7 +397,7 @@ print_par_insn (info, insn_word, insn) break; } } - /* Get the operands of the instruction based on the operand order. */ + /* Get the operands of the instruction based on the operand order. */ switch (insn->ptm->oporder) { case OO_4op1: @@ -500,14 +499,14 @@ print_branch (info, insn_word, insn) if (insn->tm == NULL) return 0; - /* Get the operands for 24-bit immediate jumps. */ + /* Get the operands for 24-bit immediate jumps. */ if (insn->tm->operand_types[0] & Imm24) { address = insn_word & 0x00FFFFFF; sprintf (operand[0], "0x%lX", address); print_label = 1; } - /* Get the operand for the trap instruction. */ + /* Get the operand for the trap instruction. */ else if (insn->tm->operand_types[0] & IVector) { address = insn_word & 0x0000001F; @@ -516,7 +515,7 @@ print_branch (info, insn_word, insn) else { address = insn_word & 0x0000FFFF; - /* Get the operands for the DB instructions. */ + /* Get the operands for the DB instructions. */ if (insn->tm->operands == 2) { get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); @@ -528,7 +527,7 @@ print_branch (info, insn_word, insn) else get_register_operand (insn_word & 0x0000001F, operand[1]); } - /* Get the operands for the standard branches. */ + /* Get the operands for the standard branches. */ else if (insn->tm->operands == 1) { if (insn_word & PCRel) @@ -545,7 +544,7 @@ print_branch (info, insn_word, insn) operand[0][0] ? operand[0] : "", operand[1][0] ? ',' : ' ', operand[1][0] ? operand[1] : ""); - /* Print destination of branch in relation to current symbol. */ + /* Print destination of branch in relation to current symbol. */ if (print_label && info->symbols) { asymbol *sym = *info->symbols; @@ -553,7 +552,7 @@ print_branch (info, insn_word, insn) if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) { address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); - /* Check for delayed instruction, if so adjust destination. */ + /* Check for delayed instruction, if so adjust destination. */ if (insn_word & 0x00200000) address += 2; } @@ -583,8 +582,8 @@ get_indirect_operand (fragment, size, buffer) if (buffer == NULL) return 0; - /* Determine which bits identify the sections of the indirect operand based on the - size in bytes. */ + /* Determine which bits identify the sections of the indirect + operand based on the size in bytes. */ switch (size) { case 1: @@ -614,14 +613,15 @@ get_indirect_operand (fragment, size, buffer) { size_t i, len; int bufcnt; - + len = strlen (current_ind->syntax); for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) { buffer[bufcnt] = current_ind->syntax[i]; if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') buffer[++bufcnt] = arnum + '0'; - if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED) + if (buffer[bufcnt] == '(' + && current_ind->displacement == DISP_REQUIRED) { sprintf (&buffer[bufcnt + 1], "%u", disp); bufcnt += strlen (&buffer[bufcnt + 1]); diff --git a/gnu/usr.bin/binutils/opcodes/tic54x-dis.c b/gnu/usr.bin/binutils/opcodes/tic54x-dis.c new file mode 100644 index 00000000000..fbc81053c75 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/tic54x-dis.c @@ -0,0 +1,615 @@ +/* Disassembly routines for TMS320C54X architecture + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include <errno.h> +#include <math.h> +#include <stdlib.h> +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic54x.h" +#include "coff/tic54x.h" + +typedef struct _instruction { + int parallel; + template *tm; + partemplate *ptm; +} instruction; + +static int get_insn_size PARAMS ((unsigned short, instruction *)); +static int get_instruction PARAMS ((disassemble_info *, bfd_vma, + unsigned short, instruction *)); +static int print_instruction PARAMS ((disassemble_info *, bfd_vma, + unsigned short, char *, + enum optype [], int, int)); +static int print_parallel_instruction PARAMS ((disassemble_info *, bfd_vma, + unsigned short, partemplate *, + int)); +static int sprint_dual_address (disassemble_info *,char [], + unsigned short); +static int sprint_indirect_address (disassemble_info *,char [], + unsigned short); +static int sprint_direct_address (disassemble_info *,char [], + unsigned short); +static int sprint_mmr (disassemble_info *,char [],int); +static int sprint_condition (disassemble_info *,char *,unsigned short); +static int sprint_cc2 (disassemble_info *,char *,unsigned short); + +int +print_insn_tic54x(memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + bfd_byte opbuf[2]; + unsigned short opcode; + int status, size; + instruction insn; + + status = (*info->read_memory_func) (memaddr, opbuf, 2, info); + if (status != 0) + { + (*info->memory_error_func)(status, memaddr, info); + return -1; + } + + opcode = bfd_getl16(opbuf); + if (!get_instruction (info, memaddr, opcode, &insn)) + return -1; + + size = get_insn_size (opcode, &insn); + info->bytes_per_line = 2; + info->bytes_per_chunk = 2; + info->octets_per_byte = 2; + info->display_endian = BFD_ENDIAN_LITTLE; + + if (insn.parallel) + { + if (!print_parallel_instruction (info, memaddr, opcode, insn.ptm, size)) + return -1; + } + else + { + if (!print_instruction (info, memaddr, opcode, + (char *)insn.tm->name, + insn.tm->operand_types, + size, (insn.tm->flags & FL_EXT))) + return -1; + } + + return size*2; +} + +static int +has_lkaddr(opcode, tm) + unsigned short opcode; + template *tm; +{ + return IS_LKADDR(opcode) && + (OPTYPE(tm->operand_types[0]) == OP_Smem || + OPTYPE(tm->operand_types[1]) == OP_Smem || + OPTYPE(tm->operand_types[2]) == OP_Smem || + OPTYPE(tm->operand_types[1]) == OP_Sind); +} + +/* always returns 1 (whether an insn template was found) since we provide an + "unknown instruction" template */ +static int +get_instruction (info, addr, opcode, insn) + disassemble_info *info; + bfd_vma addr; + unsigned short opcode; + instruction *insn; +{ + template * tm; + partemplate * ptm; + + insn->parallel = 0; + for (tm = (template *)tic54x_optab; tm->name; tm++) + { + if (tm->opcode == (opcode & tm->mask)) + { + /* a few opcodes span two words */ + if (tm->flags & FL_EXT) + { + /* if lk addressing is used, the second half of the opcode gets + pushed one word later */ + bfd_byte opbuf[2]; + bfd_vma addr2 = addr + 1 + has_lkaddr(opcode, tm); + int status = (*info->read_memory_func)(addr2, opbuf, 2, info); + if (status == 0) + { + unsigned short opcode2 = bfd_getl16(opbuf); + if (tm->opcode2 == (opcode2 & tm->mask2)) + { + insn->tm = tm; + return 1; + } + } + } + else + { + insn->tm = tm; + return 1; + } + } + } + for (ptm = (partemplate *)tic54x_paroptab; ptm->name; ptm++) + { + if (ptm->opcode == (opcode & ptm->mask)) + { + insn->parallel = 1; + insn->ptm = ptm; + return 1; + } + } + + insn->tm = (template *)&tic54x_unknown_opcode; + return 1; +} + +static int +get_insn_size (opcode, insn) + unsigned short opcode; + instruction *insn; +{ + int size; + + if (insn->parallel) + { + /* only non-parallel instructions support lk addressing */ + size = insn->ptm->words; + } + else + { + size = insn->tm->words + has_lkaddr(opcode, insn->tm); + } + + return size; +} + +int +print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + char *tm_name; + enum optype tm_operands[]; + int size; + int ext; +{ + static int n; + /* string storage for multiple operands */ + char operand[4][64] = { {0},{0},{0},{0}, }; + bfd_byte buf[2]; + unsigned long opcode2, lkaddr; + enum optype src = OP_None; + enum optype dst = OP_None; + int i, shift; + char *comma = ""; + + info->fprintf_func (info->stream, "%-7s", tm_name); + + if (size > 1) + { + int status = (*info->read_memory_func) (memaddr+1, buf, 2, info); + if (status != 0) + return 0; + lkaddr = opcode2 = bfd_getl16(buf); + if (size > 2) + { + status = (*info->read_memory_func) (memaddr+2, buf, 2, info); + if (status != 0) + return 0; + opcode2 = bfd_getl16(buf); + } + } + + for (i=0;i < MAX_OPERANDS && OPTYPE(tm_operands[i]) != OP_None;i++) + { + char *next_comma = ","; + int optional = (tm_operands[i] & OPT) != 0; + + switch (OPTYPE(tm_operands[i])) + { + case OP_Xmem: + sprint_dual_address (info, operand[i], XMEM(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Ymem: + sprint_dual_address (info, operand[i], YMEM(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Smem: + case OP_Sind: + case OP_Lmem: + info->fprintf_func (info->stream, "%s", comma); + if (INDIRECT(opcode)) + { + if (MOD(opcode) >= 12) + { + bfd_vma addr = lkaddr; + int arf = ARF(opcode); + int mod = MOD(opcode); + if (mod == 15) + info->fprintf_func (info->stream, "*("); + else + info->fprintf_func (info->stream, "*%sar%d(", + (mod == 13 || mod == 14 ? "+" : ""), + arf); + (*(info->print_address_func))((bfd_vma)addr, info); + info->fprintf_func (info->stream, ")%s", + mod == 14 ? "%" : ""); + } + else + { + sprint_indirect_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + } + else + { + /* FIXME -- use labels (print_address_func) */ + /* in order to do this, we need to guess what DP is */ + sprint_direct_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + break; + case OP_dmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func))((bfd_vma)opcode2, info); + break; + case OP_xpmad: + /* upper 7 bits of address are in the opcode */ + opcode2 += ((unsigned long)opcode & 0x7F) << 16; + /* fall through */ + case OP_pmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func))((bfd_vma)opcode2, info); + break; + case OP_MMRX: + sprint_mmr (info, operand[i], MMRX(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMRY: + sprint_mmr (info, operand[i], MMRY(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMR: + sprint_mmr (info, operand[i], MMR(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_PA: + sprintf (operand[i], "pa%d", (unsigned)opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC: + src = SRC(ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC1: + src = SRC1(ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_RND: + dst = DST(opcode) ? OP_B : OP_A; + sprintf (operand[i], (dst == OP_B) ? "a" : "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DST: + dst = DST(ext ? opcode2 : opcode) ? OP_B : OP_A; + if (!optional || dst != src) + { + sprintf (operand[i], (dst == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_B: + sprintf (operand[i], "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_A: + sprintf (operand[i], "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARX: + sprintf (operand[i],"ar%d", (int)ARX(opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SHIFT: + shift = SHIFT(ext ? opcode2 : opcode); + if (!optional || shift != 0) + { + sprintf (operand[i],"%d", shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_SHFT: + shift = SHFT(opcode); + if (!optional || shift != 0) + { + sprintf (operand[i],"%d", (unsigned)shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_lk: + sprintf (operand[i],"#%d", (int)(short)opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_T: + sprintf (operand[i], "t"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TS: + sprintf (operand[i], "ts"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8: + sprintf (operand[i], "%d", (int)((signed char)(opcode & 0xFF))); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_16: + sprintf (operand[i], "16"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ASM: + sprintf (operand[i], "asm"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_BITC: + sprintf (operand[i], "%d", (int)(opcode & 0xF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC: + /* put all CC operands in the same operand */ + sprint_condition (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + i = MAX_OPERANDS; + break; + case OP_CC2: + sprint_cc2 (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC3: + { + const char *code[] = { "eq", "lt", "gt", "neq" }; + sprintf (operand[i], code[CC3(opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_123: + { + int code = (opcode>>8) & 0x3; + sprintf (operand[i], "%d", (code == 0) ? 1 : (code == 2) ? 2 : 3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_k5: + sprintf (operand[i], "#%d", + (int)(((signed char)opcode & 0x1F) << 3)>>3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8u: + sprintf (operand[i], "#%d", (unsigned)(opcode & 0xFF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k3: + sprintf (operand[i], "#%d", (int)(opcode & 0x7)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_lku: + sprintf (operand[i], "#%d", (unsigned)opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_N: + n = (opcode >> 9) & 0x1; + sprintf (operand[i], "st%d", n); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SBIT: + { + const char *status0[] = { + "0", "1", "2", "3", "4", "5", "6", "7", "8", + "ovb", "ova", "c", "tc", "13", "14", "15" + }; + const char *status1[] = { + "0", "1", "2", "3", "4", + "cmpt", "frct", "c16", "sxm", "ovm", "10", + "intm", "hm", "xf", "cpl", "braf" + }; + sprintf (operand[i], "%s", + n ? status1[SBIT(opcode)] : status0[SBIT(opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_12: + sprintf (operand[i], "%d", (int)((opcode >> 9)&1) + 1); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TRN: + sprintf (operand[i], "trn"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DP: + sprintf (operand[i], "dp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k9: + /* FIXME-- this is DP, print the original address? */ + sprintf (operand[i], "#%d", (int)(opcode & 0x1FF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARP: + sprintf (operand[i], "arp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_031: + sprintf (operand[i], "%d", (int)(opcode & 0x1F)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + default: + sprintf (operand[i], "??? (0x%x)", tm_operands[i]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + comma = next_comma; + } + return 1; +} + +static int +print_parallel_instruction (info, memaddr, opcode, ptm, size) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + partemplate *ptm; + int size; +{ + print_instruction (info, memaddr, opcode, + ptm->name, ptm->operand_types, size, 0); + info->fprintf_func (info->stream, " || "); + return print_instruction (info, memaddr, opcode, + ptm->parname, ptm->paroperand_types, size, 0); +} + +static int +sprint_dual_address (info, buf, code) + disassemble_info *info; + char buf[]; + unsigned short code; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*ar%d+0%%", + }; + return sprintf (buf, formats[XMOD(code)], XARX(code)); +} + +static int +sprint_indirect_address (info, buf, opcode) + disassemble_info *info; + char buf[]; + unsigned short opcode; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*+ar%d", + "*ar%d-0B", + "*ar%d-0", + "*ar%d+0", + "*ar%d+0B", + "*ar%d-%%", + "*ar%d-0%%", + "*ar%d+%%", + "*ar%d+0%%", + }; + return sprintf (buf, formats[MOD(opcode)], ARF(opcode)); +} + +static int +sprint_direct_address (info, buf, opcode) + disassemble_info *info; + char buf[]; + unsigned short opcode; +{ + /* FIXME -- look up relocation if available */ + return sprintf (buf, "0x??%02x", (int)(opcode & 0x7F)); +} + +static int +sprint_mmr (info, buf, mmr) + disassemble_info *info; + char buf[]; + int mmr; +{ + symbol *reg = (symbol *)mmregs; + while (reg->name != NULL) + { + if (mmr == reg->value) + { + sprintf (buf, "%s", (reg+1)->name); + return 1; + } + ++reg; + } + sprintf (buf, "MMR(%d)", mmr); /* FIXME -- different targets. */ + return 0; +} + +static int +sprint_cc2 (info, buf, opcode) + disassemble_info *info; + char *buf; + unsigned short opcode; +{ + const char *cc2[] = { + "??", "??", "ageq", "alt", "aneq", "aeq", "agt", "aleq", + "??", "??", "bgeq", "blt", "bneq", "beq", "bgt", "bleq", + }; + return sprintf (buf, "%s", cc2[opcode & 0xF]); +} + +static int +sprint_condition (info, buf, opcode) + disassemble_info *info; + char *buf; + unsigned short opcode; +{ + char *start = buf; + const char *cmp[] = { + "??", "??", "geq", "lt", "neq", "eq", "gt", "leq" + }; + if (opcode & 0x40) + { + char acc = (opcode & 0x8) ? 'b' : 'a'; + if (opcode & 0x7) + buf += sprintf (buf, "%c%s%s", acc, cmp[(opcode&0x7)], + (opcode&0x20) ? ", " : ""); + if (opcode & 0x20) + buf += sprintf (buf, "%c%s", acc, (opcode&0x10) ? "ov" : "nov"); + } + else if (opcode & 0x3F) + { + if (opcode & 0x30) + buf += sprintf (buf, "%s%s", + ((opcode & 0x30) == 0x30) ? "tc" : "ntc", + (opcode & 0x0F) ? ", " : ""); + if (opcode & 0x0C) + buf += sprintf (buf, "%s%s", + ((opcode & 0x0C) == 0x0C) ? "c" : "nc", + (opcode & 0x03) ? ", " : ""); + if (opcode & 0x03) + buf += sprintf (buf, "%s", + ((opcode & 0x03) == 0x03) ? "bio" : "nbio"); + } + else + buf += sprintf (buf, "unc"); + + return buf - start; +} diff --git a/gnu/usr.bin/binutils/opcodes/tic54x-opc.c b/gnu/usr.bin/binutils/opcodes/tic54x-opc.c new file mode 100644 index 00000000000..39714beb650 --- /dev/null +++ b/gnu/usr.bin/binutils/opcodes/tic54x-opc.c @@ -0,0 +1,476 @@ +/* Table of opcodes for the Texas Instruments TMS320C54X + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "opcode/tic54x.h" + +/* these are the only register names not found in mmregs */ +const symbol regs[] = { + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { NULL, } +}; + +/* status bits, MM registers, condition codes, etc */ +/* some symbols are only valid for certain chips... */ +const symbol mmregs[] = { + { "IMR", 0 }, { "imr", 0 }, + { "IFR", 1 }, { "ifr", 1 }, + { "ST0", 6 }, { "st0", 6 }, + { "ST1", 7 }, { "st1", 7 }, + { "AL", 8 }, { "al", 8 }, + { "AH", 9 }, { "ah", 9 }, + { "AG", 10 }, { "ag", 10 }, + { "BL", 11 }, { "bl", 11 }, + { "BH", 12 }, { "bh", 12 }, + { "BG", 13 }, { "bg", 13 }, + { "T", 14 }, { "t", 14 }, + { "TRN", 15 }, { "trn", 15 }, + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { "SP", 24 }, { "sp", 24 }, + { "BK", 25 }, { "bk", 25 }, + { "BRC", 26 }, { "brc", 26 }, + { "RSA", 27 }, { "rsa", 27 }, + { "REA", 28 }, { "rea", 28 }, + { "PMST",29 }, { "pmst",29 }, + { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ + /* optional peripherals */ /* optional peripherals */ + { "M1F", 31 }, { "m1f", 31 }, + { "DRR0",0x20 }, { "drr0",0x20 }, + { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ + { "DXR0",0x21 }, { "dxr0",0x21 }, + { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ + { "SPC0",0x22 }, { "spc0",0x22 }, + { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ + { "SPCE0",0x23 }, { "spce0",0x23 }, + { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ + { "TIM", 0x24 }, { "tim", 0x24 }, + { "PRD", 0x25 }, { "prd", 0x25 }, + { "TCR", 0x26 }, { "tcr", 0x26 }, + { "SWWSR",0x28 }, { "swwsr",0x28 }, + { "BSCR",0x29 }, { "bscr",0x29 }, + { "HPIC",0x2C }, { "hpic",0x2c }, + /* 'c541, 'c545 */ /* 'c541, 'c545 */ + { "DRR1",0x30 }, { "drr1",0x30 }, + { "DXR1",0x31 }, { "dxr1",0x31 }, + { "SPC1",0x32 }, { "spc1",0x32 }, + /* 'c542, 'c543 */ /* 'c542, 'c543 */ + { "TRCV",0x30 }, { "trcv",0x30 }, + { "TDXR",0x31 }, { "tdxr",0x31 }, + { "TSPC",0x32 }, { "tspc",0x32 }, + { "TCSR",0x33 }, { "tcsr",0x33 }, + { "TRTA",0x34 }, { "trta",0x34 }, + { "TRAD",0x35 }, { "trad",0x35 }, + { "AXR0",0x38 }, { "axr0",0x38 }, + { "BKX0",0x39 }, { "bkx0",0x39 }, + { "ARR0",0x3A }, { "arr0",0x3a }, + { "BKR0",0x3B }, { "bkr0",0x3b }, + /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ + { "CLKMD",0x58 }, { "clkmd",0x58 }, + /* 'c548 */ /* 'c548 */ + { "AXR1",0x3C }, { "axr1",0x3c }, + { "BKX1",0x3D }, { "bkx1",0x3d }, + { "ARR1",0x3E }, { "arr1",0x3e }, + { "BKR1",0x3F }, { "bkr1",0x3f }, + { "BDRR1",0x40 }, { "bdrr1",0x40 }, + { "BDXR1",0x41 }, { "bdxr1",0x41 }, + { "BSPC1",0x42 }, { "bspc1",0x42 }, + { "BSPCE1",0x43 }, { "bspce1",0x43 }, + { NULL }, +}; + +const symbol condition_codes[] = { + /* condition codes */ + { "UNC", 0 }, { "unc", 0 }, +#define CC1 0x40 +#define CCB 0x08 +#define CCEQ 0x05 +#define CCNEQ 0x04 +#define CCLT 0x03 +#define CCLEQ 0x07 +#define CCGT 0x06 +#define CCGEQ 0x02 +#define CCOV 0x70 +#define CCNOV 0x60 +#define CCBIO 0x03 +#define CCNBIO 0x02 +#define CCTC 0x30 +#define CCNTC 0x20 +#define CCC 0x0C +#define CCNC 0x08 + { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ }, + { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ }, + { "alt", CC1|CCLT }, { "ALT", CC1|CCLT }, + { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ }, + { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, + { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, + { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, + { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, + { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, + { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, + { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, + { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, + { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, + { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, + { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, + { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, + { "tc", CCTC }, { "TC", CCTC }, + { "ntc", CCNTC }, { "NTC", CCNTC }, + { "c", CCC }, { "C", CCC }, + { "nc", CCNC }, { "NC", CCNC }, + { "bio", CCBIO }, { "BIO", CCBIO }, + { "nbio", CCNBIO }, { "NBIO", CCNBIO }, + { NULL, } +}; + +const symbol cc2_codes[] = { + { "UNC", 0 }, { "unc", 0 }, + { "AEQ", 5 }, { "aeq", 5 }, + { "ANEQ", 4 }, { "aneq", 4 }, + { "AGT", 6 }, { "agt", 6 }, + { "ALT", 3 }, { "alt", 3 }, + { "ALEQ", 7 }, { "aleq", 7 }, + { "AGEQ", 2 }, { "ageq", 2 }, + { "BEQ", 13 }, { "beq", 13 }, + { "BNEQ", 12 },{ "bneq", 12 }, + { "BGT", 14 }, { "bgt", 14 }, + { "BLT", 11 }, { "blt", 11 }, + { "BLEQ", 15 },{ "bleq", 15 }, + { "BGEQ", 10 },{ "bgeq", 10 }, + { NULL }, +}; + +const symbol cc3_codes[] = { + { "EQ", 0x0000 }, { "eq", 0x0000 }, + { "LT", 0x0100 }, { "lt", 0x0100 }, + { "GT", 0x0200 }, { "gt", 0x0200 }, + { "NEQ", 0x0300 }, { "neq", 0x0300 }, + { "0", 0x0000 }, + { "1", 0x0100 }, + { "2", 0x0200 }, + { "3", 0x0300 }, + { "00", 0x0000 }, + { "01", 0x0100 }, + { "10", 0x0200 }, + { "11", 0x0300 }, + { NULL }, +}; + +/* FIXME -- also allow decimal digits */ +const symbol status_bits[] = { + /* status register 0 */ + { "TC", 12 }, { "tc", 12 }, + { "C", 11 }, { "c", 11 }, + { "OVA", 10 }, { "ova", 10 }, + { "OVB", 9 }, { "ovb", 9 }, + /* status register 1 */ + { "BRAF",15 }, { "braf",15 }, + { "CPL", 14 }, { "cpl", 14 }, + { "XF", 13 }, { "xf", 13 }, + { "HM", 12 }, { "hm", 12 }, + { "INTM",11 }, { "intm",11 }, + { "OVM", 9 }, { "ovm", 9 }, + { "SXM", 8 }, { "sxm", 8 }, + { "C16", 7 }, { "c16", 7 }, + { "FRCT", 6 }, { "frct", 6 }, + { "CMPT", 5 }, { "cmpt", 5 }, + { NULL }, +}; + +const char *misc_symbols[] = { + "ARP", "arp", + "DP", "dp", + "ASM", "asm", + "TS", "ts", + NULL +}; + +/* Due to the way instructions are hashed and scanned in + gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively + placed + + Items marked with "PREFER" have been moved prior to a more costly + instruction with a similar operand format. + + Mnemonics which can take either a predefined symbol or a memory reference + as an argument are arranged so that the more restrictive (predefined + symbol) version is checked first (marked "SRC"). +*/ +const template tic54x_unknown_opcode = + { "???", 1,0,0,0x0000, 0x0000, {0}, }; +const template tic54x_optab[] = { + /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */ + { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, + { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, + { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, + { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, + + { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, }, + { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, + { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ + { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ + { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, + { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR}, + { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, },/*PREFER*/ + { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C00, 0xFCE0}, + { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, + { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, }, + { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, + { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, + { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, }, + { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, + { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, + { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, }, + { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, + { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, + { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, + { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, + { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, }, + { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, }, + { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, }, + { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, }, + { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, }, + { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, + { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR }, + { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, + { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, + { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, + { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, + { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, }, + { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, }, + { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, + { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, + { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, }, + { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, }, + { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, }, + { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, }, + { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR }, + { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, }, + { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, }, + { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, }, + { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, }, + { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, }, + { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, }, + { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, }, + { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, + { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, + { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, + { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, + { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, }, + { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, }, + { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, + { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, + { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, + { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, + { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, }, + { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, + { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, },/*SRC*/ + /* alternate syntax */ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },/*SRC*/ + { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, },/*SRC*/ + { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, },/*SRC*/ + { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, },/*SRC*/ + { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, },/*PREFER */ + { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR },/*SRC*/ + { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR },/*SRC*/ + { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR },/*SRC*/ + { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR }, + { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR }, + { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, },/*PREFER*/ + { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, + FL_EXT|FL_SMR, 0x0C40, 0xFEE0 }, + { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, }, + { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, }, + { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, }, + { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR},/*pseudo-op*/ + { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, }, + { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR }, + { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, + { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, }, + { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR }, + { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR}, + { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ + { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, + { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ + { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, + { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, + { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, + { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, }, + { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, }, + { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, + { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, + { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, },/*SRC*/ + { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, + { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, }, + { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, }, + { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, }, + { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, + { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR }, + { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, }, + { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, }, /*SRC*/ + { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR }, + { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, }, + { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR }, + { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, }, + { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR }, + { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, }, + { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, }, + { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, }, + { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, }, + { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, + { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, }, + { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, + { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ + { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, + { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, + { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, + { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR }, + { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, }, + { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, }, + { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, }, + { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR }, + { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR }, + { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, }, + { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, }, + { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, + { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_NR, }, + { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_DELAY|FL_NR, }, + { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, }, + { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, }, + { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, }, + { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, + { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, }, + { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, + { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR }, + { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, }, + { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, }, + { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, }, + { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, }, + { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, }, + { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, }, + { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, }, + { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, }, + { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, }, + { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, + { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, }, + { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, }, + { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, + { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, }, + { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, + { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, }, + { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, },/*SRC*/ + { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, + { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, }, + { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, + { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, }, + { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, }, + { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, }, + { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, }, + { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, + { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, + { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C60, 0xFEE0 }, + { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, }, + { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, + { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, + { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C80, 0xFEE0 }, + { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, }, + { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, }, + { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, }, + { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ + { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ + { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, + { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR }, + { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, }, /*PREFER*/ + { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C20, 0xFCE0 }, + { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, + { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, + { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, + { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, + { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR }, + { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, }, + { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ + { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, + { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, + { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, }, + { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, }, + { NULL, }, +}; + +/* assume all parallel instructions have at least three operands */ +const partemplate tic54x_paroptab[] = { + { "ld","mac", 1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, + { "ld","macr",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, + { "ld","mas", 1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, + { "ld","masr",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, + { "st","add", 1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","ld", 1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","ld", 1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_T}, }, + { "st","mac", 1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","macr",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","mas", 1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","masr",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","mpy", 1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { "st","sub", 1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, + { NULL,NULL }, +}; diff --git a/gnu/usr.bin/binutils/opcodes/tic80-dis.c b/gnu/usr.bin/binutils/opcodes/tic80-dis.c index 449ce8f7fba..d706bda44d9 100644 --- a/gnu/usr.bin/binutils/opcodes/tic80-dis.c +++ b/gnu/usr.bin/binutils/opcodes/tic80-dis.c @@ -1,5 +1,5 @@ /* Print TI TMS320C80 (MVP) instructions - Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -36,13 +36,12 @@ static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsign const struct tic80_opcode *)); static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long *)); - /* Print an integer operand. Try to be somewhat smart about the format by assuming that small positive or negative integers are probably loop increment values, structure offsets, or similar values that are more meaningful printed as signed decimal values. - Larger numbers are probably better printed as hex values. */ + Larger numbers are probably better printed as hex values. */ static void print_operand_integer (info, value) @@ -51,18 +50,17 @@ print_operand_integer (info, value) { if ((value > 9999 || value < -9999)) { - (*info -> fprintf_func) (info -> stream, "%#lx", value); + (*info->fprintf_func) (info->stream, "%#lx", value); } else { - (*info -> fprintf_func) (info -> stream, "%ld", value); + (*info->fprintf_func) (info->stream, "%ld", value); } } - /* FIXME: depends upon sizeof (long) == sizeof (float) and also upon host floating point format matching target - floating point format. */ + floating point format. */ static void print_operand_float (info, value) @@ -72,9 +70,8 @@ print_operand_float (info, value) union { float f; long l; } fval; fval.l = value; - (*info -> fprintf_func) (info -> stream, "%g", fval.f); + (*info->fprintf_func) (info->stream, "%g", fval.f); } - static void print_operand_control_register (info, value) @@ -86,14 +83,13 @@ print_operand_control_register (info, value) tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); if (tmp != NULL) { - (*info -> fprintf_func) (info -> stream, "%s", tmp); + (*info->fprintf_func) (info->stream, "%s", tmp); } else { - (*info -> fprintf_func) (info -> stream, "%#lx", value); + (*info->fprintf_func) (info->stream, "%#lx", value); } } - static void print_operand_condition_code (info, value) @@ -105,14 +101,13 @@ print_operand_condition_code (info, value) tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); if (tmp != NULL) { - (*info -> fprintf_func) (info -> stream, "%s", tmp); + (*info->fprintf_func) (info->stream, "%s", tmp); } else { - (*info -> fprintf_func) (info -> stream, "%ld", value); + (*info->fprintf_func) (info->stream, "%ld", value); } } - static void print_operand_bitnum (info, value) @@ -126,20 +121,19 @@ print_operand_bitnum (info, value) tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); if (tmp != NULL) { - (*info -> fprintf_func) (info -> stream, "%s", tmp); + (*info->fprintf_func) (info->stream, "%s", tmp); } else { - (*info -> fprintf_func) (info -> stream, "%ld", bitnum); + (*info->fprintf_func) (info->stream, "%ld", bitnum); } } - /* Print the operand as directed by the flags. */ -#define M_SI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) -#define M_LI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) -#define R_SCALED(insn,op) ((((op) -> flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) +#define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) +#define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) +#define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) static void print_operand (info, value, insn, operand, memaddr) @@ -149,61 +143,60 @@ print_operand (info, value, insn, operand, memaddr) const struct tic80_operand *operand; bfd_vma memaddr; { - if ((operand -> flags & TIC80_OPERAND_GPR) != 0) + if ((operand->flags & TIC80_OPERAND_GPR) != 0) { - (*info -> fprintf_func) (info -> stream, "r%ld", value); + (*info->fprintf_func) (info->stream, "r%ld", value); if (M_SI (insn, operand) || M_LI (insn, operand)) { - (*info -> fprintf_func) (info -> stream, ":m"); + (*info->fprintf_func) (info->stream, ":m"); } } - else if ((operand -> flags & TIC80_OPERAND_FPA) != 0) + else if ((operand->flags & TIC80_OPERAND_FPA) != 0) { - (*info -> fprintf_func) (info -> stream, "a%ld", value); + (*info->fprintf_func) (info->stream, "a%ld", value); } - else if ((operand -> flags & TIC80_OPERAND_PCREL) != 0) + else if ((operand->flags & TIC80_OPERAND_PCREL) != 0) { - (*info -> print_address_func) (memaddr + 4 * value, info); + (*info->print_address_func) (memaddr + 4 * value, info); } - else if ((operand -> flags & TIC80_OPERAND_BASEREL) != 0) + else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0) { - (*info -> print_address_func) (value, info); + (*info->print_address_func) (value, info); } - else if ((operand -> flags & TIC80_OPERAND_BITNUM) != 0) + else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0) { print_operand_bitnum (info, value); } - else if ((operand -> flags & TIC80_OPERAND_CC) != 0) + else if ((operand->flags & TIC80_OPERAND_CC) != 0) { print_operand_condition_code (info, value); } - else if ((operand -> flags & TIC80_OPERAND_CR) != 0) + else if ((operand->flags & TIC80_OPERAND_CR) != 0) { print_operand_control_register (info, value); } - else if ((operand -> flags & TIC80_OPERAND_FLOAT) != 0) + else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0) { print_operand_float (info, value); } - else if ((operand -> flags & TIC80_OPERAND_BITFIELD)) + else if ((operand->flags & TIC80_OPERAND_BITFIELD)) { - (*info -> fprintf_func) (info -> stream, "%#lx", value); + (*info->fprintf_func) (info->stream, "%#lx", value); } else { print_operand_integer (info, value); } - /* If this is a scaled operand, then print the modifier */ + /* If this is a scaled operand, then print the modifier. */ if (R_SCALED (insn, operand)) { - (*info -> fprintf_func) (info -> stream, ":s"); + (*info->fprintf_func) (info->stream, ":s"); } } - -/* We have chosen an opcode table entry */ +/* We have chosen an opcode table entry. */ static int print_one_instruction (info, memaddr, insn, opcode) @@ -218,18 +211,18 @@ print_one_instruction (info, memaddr, insn, opcode) const unsigned char *opindex; int close_paren; - (*info -> fprintf_func) (info -> stream, "%-10s", opcode -> name); + (*info->fprintf_func) (info->stream, "%-10s", opcode->name); - for (opindex = opcode -> operands; *opindex != 0; opindex++) + for (opindex = opcode->operands; *opindex != 0; opindex++) { operand = tic80_operands + *opindex; /* Extract the value from the instruction. */ - if (operand -> extract) + if (operand->extract) { - value = (*operand -> extract) (insn, (int *) NULL); + value = (*operand->extract) (insn, (int *) NULL); } - else if (operand -> bits == 32) + else if (operand->bits == 32) { status = fill_instruction (info, memaddr, (unsigned long *) &value); if (status == -1) @@ -239,52 +232,50 @@ print_one_instruction (info, memaddr, insn, opcode) } else { - value = (insn >> operand -> shift) & ((1 << operand -> bits) - 1); - if ((operand -> flags & TIC80_OPERAND_SIGNED) != 0 - && (value & (1 << (operand -> bits - 1))) != 0) + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & TIC80_OPERAND_SIGNED) != 0 + && (value & (1 << (operand->bits - 1))) != 0) { - value -= 1 << operand -> bits; + value -= 1 << operand->bits; } } /* If this operand is enclosed in parenthesis, then print the open paren, otherwise just print the regular comma - separator, except for the first operand. */ + separator, except for the first operand. */ - if ((operand -> flags & TIC80_OPERAND_PARENS) == 0) + if ((operand->flags & TIC80_OPERAND_PARENS) == 0) { close_paren = 0; - if (opindex != opcode -> operands) + if (opindex != opcode->operands) { - (*info -> fprintf_func) (info -> stream, ","); + (*info->fprintf_func) (info->stream, ","); } } else { close_paren = 1; - (*info -> fprintf_func) (info -> stream, "("); + (*info->fprintf_func) (info->stream, "("); } print_operand (info, value, insn, operand, memaddr); /* If we printed an open paren before printing this operand, close - it now. The flag gets reset on each loop. */ + it now. The flag gets reset on each loop. */ if (close_paren) { - (*info -> fprintf_func) (info -> stream, ")"); + (*info->fprintf_func) (info->stream, ")"); } } return (length); } - - /* There are no specific bits that tell us for certain whether a vector instruction opcode contains one or two instructions. However since a destination register of r0 is illegal, we can check for nonzero values in both destination register fields. Only opcodes that have - two valid instructions will have non-zero in both */ + two valid instructions will have non-zero in both. */ #define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) @@ -302,12 +293,12 @@ print_instruction (info, memaddr, insn, vec_opcode) opcodes (vec_opcode != NULL) find the first match that is not the previously found match. FIXME: there should be faster ways to search (hash table or binary search), but don't worry too much - about it until other TIc80 support is finished. */ + about it until other TIc80 support is finished. */ opcode_end = tic80_opcodes + tic80_num_opcodes; for (opcode = tic80_opcodes; opcode < opcode_end; opcode++) { - if ((insn & opcode -> mask) == opcode -> opcode && + if ((insn & opcode->mask) == opcode->opcode && opcode != vec_opcode) { break; @@ -316,19 +307,19 @@ print_instruction (info, memaddr, insn, vec_opcode) if (opcode == opcode_end) { - /* No match found, just print the bits as a .word directive */ - (*info -> fprintf_func) (info -> stream, ".word %#08lx", insn); + /* No match found, just print the bits as a .word directive. */ + (*info->fprintf_func) (info->stream, ".word %#08lx", insn); } else { /* Match found, decode the instruction. */ length = print_one_instruction (info, memaddr, insn, opcode); - if (opcode -> flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) + if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) { /* There is another instruction to print from the same opcode. Print the separator and then find and print the other - instruction. */ - (*info -> fprintf_func) (info -> stream, " || "); + instruction. */ + (*info->fprintf_func) (info->stream, " || "); length = print_instruction (info, memaddr, insn, opcode); } } @@ -337,7 +328,7 @@ print_instruction (info, memaddr, insn, vec_opcode) /* Get the next 32 bit word from the instruction stream and convert it into internal format in the unsigned long INSN, for which we are - passed the address. Return 0 on success, -1 on error. */ + passed the address. Return 0 on success, -1 on error. */ static int fill_instruction (info, memaddr, insnp) @@ -348,37 +339,36 @@ fill_instruction (info, memaddr, insnp) bfd_byte buffer[4]; int status; - /* Get the bits for the next 32 bit word and put in buffer */ + /* Get the bits for the next 32 bit word and put in buffer. */ - status = (*info -> read_memory_func) (memaddr + length, buffer, 4, info); + status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); if (status != 0) { - (*info -> memory_error_func) (status, memaddr, info); + (*info->memory_error_func) (status, memaddr, info); return (-1); } /* Read was successful, so increment count of bytes read and convert - the bits into internal format. */ - + the bits into internal format. */ + length += 4; - if (info -> endian == BFD_ENDIAN_LITTLE) + if (info->endian == BFD_ENDIAN_LITTLE) { *insnp = bfd_getl32 (buffer); } - else if (info -> endian == BFD_ENDIAN_BIG) + else if (info->endian == BFD_ENDIAN_BIG) { *insnp = bfd_getb32 (buffer); } else { - /* FIXME: Should probably just default to one or the other */ + /* FIXME: Should probably just default to one or the other. */ abort (); } return (0); } - -int +int print_insn_tic80 (memaddr, info) bfd_vma memaddr; struct disassemble_info *info; diff --git a/gnu/usr.bin/binutils/opcodes/tic80-opc.c b/gnu/usr.bin/binutils/opcodes/tic80-opc.c index 4cdd06a64ff..a92775955fe 100644 --- a/gnu/usr.bin/binutils/opcodes/tic80-opc.c +++ b/gnu/usr.bin/binutils/opcodes/tic80-opc.c @@ -1,5 +1,5 @@ /* Opcode table for TI TMS320C80 (MVP). - Copyright 1996, 1999 Free Software Foundation, Inc. + Copyright 1996, 1997, 2000 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. diff --git a/gnu/usr.bin/binutils/opcodes/v850-dis.c b/gnu/usr.bin/binutils/opcodes/v850-dis.c index d817f80bceb..0f688678a8a 100644 --- a/gnu/usr.bin/binutils/opcodes/v850-dis.c +++ b/gnu/usr.bin/binutils/opcodes/v850-dis.c @@ -1,5 +1,5 @@ /* Disassemble V850 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/v850-opc.c b/gnu/usr.bin/binutils/opcodes/v850-opc.c index 874db1b6ee9..20a4d6d6464 100644 --- a/gnu/usr.bin/binutils/opcodes/v850-opc.c +++ b/gnu/usr.bin/binutils/opcodes/v850-opc.c @@ -1,5 +1,5 @@ /* Assemble V850 instructions. - Copyright (C) 1996 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gnu/usr.bin/binutils/opcodes/vax-dis.c b/gnu/usr.bin/binutils/opcodes/vax-dis.c index 29641f1768f..e33f87e5e68 100644 --- a/gnu/usr.bin/binutils/opcodes/vax-dis.c +++ b/gnu/usr.bin/binutils/opcodes/vax-dis.c @@ -1,5 +1,5 @@ /* Print VAX instructions. - Copyright (C) 1995, 1998 Free Software Foundation, Inc. + Copyright 1995, 1998, 2000, 2001 Free Software Foundation, Inc. Contributed by Pauline Middelink <middelin@polyware.iaf.nl> This program is free software; you can redistribute it and/or modify @@ -126,7 +126,18 @@ print_insn_vax (memaddr, info) return -1; } - FETCH_DATA (info, buffer + 2); + /* Check if the info buffer has more than one byte left since + the last opcode might be a single byte with no argument data. */ + if (info->buffer_length - (memaddr - info->buffer_vma) > 1) + { + FETCH_DATA (info, buffer + 2); + } + else + { + FETCH_DATA (info, buffer + 1); + buffer[1] = 0; + } + for (votp = &votstrs[0]; votp->name[0]; votp++) { register vax_opcodeT opcode = votp->detail.code; |