initial import of NetBSD tree

16 files changed, 8055 insertions, 0 deletions

diff --git a/gnu/usr.bin/gas/opcode/ChangeLog b/gnu/usr.bin/gas/opcode/ChangeLog
new file mode 100644
index 00000000000..dcb04987b90
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/ChangeLog
@@ -0,0 +1,56 @@
+Mon Feb 24 02:02:04 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* ns32k.h: SEQUENT_COMPATIBILITY -> TE_SEQUENT.
+
+	* i860.h: added "fst.q".
+
+Fri Feb 21 01:29:51 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* i386.h: added inb, inw, outb, outw opcodes, added att syntax for
+	  scmp, slod, smov, ssca, ssto.  Curtesy Minh Tran-Le
+	  <TRANLE@INTELLICORP.COM>.
+
+Thu Jan 30 07:31:44 1992  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* h8300.h: turned op_type enum into #define list
+
+Thu Jan 30 01:07:24 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sparc.h:  Remove "cypress" architecture.  Remove "fitox" and
+	similar instructions -- they've been renamed to "fitoq", etc.
+	REALLY fix tsubcctv.  Fix "fcmpeq" and "fcmpq" which had wrong
+	number of arguments.
+	* h8300.h:  Remove extra ; which produces compiler warning.
+
+Tue Jan 28 22:59:22 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* sparc.h:  fix opcode for tsubcctv.
+
+Tue Jan  7 17:19:39 1992  K. Richard Pixley  (rich at cygnus.com)
+
+	* sparc.h: fba and cba are now aliases for fb and cb respectively.
+
+Fri Dec 27 10:55:50 1991  Per Bothner  (bothner at cygnus.com)
+
+	* sparc.h (nop):  Made the 'lose' field be even tighter,
+	so only a standard 'nop' is disassembled as a nop.
+
+Sun Dec 22 12:18:18 1991  Michael Tiemann  (tiemann at cygnus.com)
+
+	* sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
+	disassembled as a nop.
+
+Tue Dec 10 00:22:20 1991  K. Richard Pixley  (rich at rtl.cygnus.com)
+
+	* sparc.h: fix a typo.
+
+Sat Nov 30 20:40:51 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* a29k.h, arm.h, h8300.h,  i386.h,  i860.h, i960.h , m68k.h, 
+	m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
+	vax.h, ChangeLog: renamed from ../<foo>-opcode.h
+
+
+	
+
+
diff --git a/gnu/usr.bin/gas/opcode/a29k.h b/gnu/usr.bin/gas/opcode/a29k.h
new file mode 100644
index 00000000000..82bb4d2c199
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/a29k.h
@@ -0,0 +1,330 @@
+/* Table of opcodes for the AMD 29000
+   Copyright (C) 1990, 1991 Free Software Foundation, Inc.
+
+This file is part of GDB and GAS.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+struct a29k_opcode {
+  /* Name of the instruction.  */
+  char *name;
+
+  /* Opcode word */
+  unsigned long opcode;
+
+  /* A string of characters which describe the operands.
+     Valid characters are:
+     ,        Itself.  The character appears in the assembly code.
+     a        RA.  The register number is in bits 8-15 of the instruction.
+     b        RB.  The register number is in bits 0-7 of the instruction.
+     c        RC.  The register number is in bits 16-23 of the instruction.
+     i        An immediate operand is in bits 0-7 of the instruction.
+     x        Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
+              (respectively) of the immediate operand.
+     h        Same as x but the instruction contains bits 16-31 of the
+              immediate operand.
+     X        Same as x but bits 16-31 of the signed immediate operand
+              are set to 1 (thus the operand is always negative).
+     P,A      Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
+              (respectively) of the immediate operand.
+	      P=PC-relative, sign-extended to 32 bits.
+	      A=Absolute, zero-extended to 32 bits.
+     e        CE bit (bit 23) for a load/store instruction.
+     n        Control field (bits 16-22) for a load/store instruction.
+     v        Immediate operand in bits 16-23 of the instruction.
+              (used for trap numbers).
+     s        SA.  Special-purpose register number in bits 8-15
+              of the instruction.
+     u        UI--bit 7 of the instruction.
+     r        RND--bits 4-6 of the instruction.
+     d        FD--bits 2-3 of the instruction.
+     f        FS--bits 0-1 of the instruction.
+
+     Extensions for 29050:
+
+     d	      FMT--bits 2-3 of the instruction (not really new).
+     f	      ACN--bits 0-1 of the instruction (not really new).
+     F	      FUNC--Special function in bits 18-21 of the instruction.
+     C	      ACN--bits 16-17 specifying the accumlator register.  */
+  char *args;
+};
+
+#ifndef CONST
+#define CONST
+#endif /* CONST */
+
+static CONST struct a29k_opcode a29k_opcodes[] =
+{
+
+{ "add", 0x14000000, "c,a,b" },
+{ "add", 0x15000000, "c,a,i" },
+{ "addc", 0x1c000000, "c,a,b" },
+{ "addc", 0x1d000000, "c,a,i" },
+{ "addcs", 0x18000000, "c,a,b" },
+{ "addcs", 0x19000000, "c,a,i" },
+{ "addcu", 0x1a000000, "c,a,b" },
+{ "addcu", 0x1b000000, "c,a,i" },
+{ "adds", 0x10000000, "c,a,b" },
+{ "adds", 0x11000000, "c,a,i" },
+{ "addu", 0x12000000, "c,a,b" },
+{ "addu", 0x13000000, "c,a,i" },
+{ "and", 0x90000000, "c,a,b" },
+{ "and", 0x91000000, "c,a,i" },
+{ "andn", 0x9c000000, "c,a,b" },
+{ "andn", 0x9d000000, "c,a,i" },
+{ "aseq", 0x70000000, "v,a,b" },
+{ "aseq", 0x71000000, "v,a,i" },
+{ "asge", 0x5c000000, "v,a,b" },
+{ "asge", 0x5d000000, "v,a,i" },
+{ "asgeu", 0x5e000000, "v,a,b" },
+{ "asgeu", 0x5f000000, "v,a,i" },
+{ "asgt", 0x58000000, "v,a,b" },
+{ "asgt", 0x59000000, "v,a,i" },
+{ "asgtu", 0x5a000000, "v,a,b" },
+{ "asgtu", 0x5b000000, "v,a,i" },
+{ "asle", 0x54000000, "v,a,b" },
+{ "asle", 0x55000000, "v,a,i" },
+{ "asleu", 0x56000000, "v,a,b" },
+{ "asleu", 0x57000000, "v,a,i" },
+{ "aslt", 0x50000000, "v,a,b" },
+{ "aslt", 0x51000000, "v,a,i" },
+{ "asltu", 0x52000000, "v,a,b" },
+{ "asltu", 0x53000000, "v,a,i" },
+{ "asneq", 0x72000000, "v,a,b" },
+{ "asneq", 0x73000000, "v,a,i" },
+{ "call", 0xa8000000, "a,P" },
+{ "call", 0xa9000000, "a,A" },
+{ "calli", 0xc8000000, "a,b" },
+{ "class", 0xe6000000, "c,a,f" },
+{ "clz", 0x08000000, "c,b" },
+{ "clz", 0x09000000, "c,i" },
+{ "const", 0x03000000, "a,x" },
+{ "consth", 0x02000000, "a,h" },
+{ "consthz", 0x05000000, "a,h" },
+{ "constn", 0x01000000, "a,X" },
+{ "convert", 0xe4000000, "c,a,u,r,d,f" },
+{ "cpbyte", 0x2e000000, "c,a,b" },
+{ "cpbyte", 0x2f000000, "c,a,i" },
+{ "cpeq", 0x60000000, "c,a,b" },
+{ "cpeq", 0x61000000, "c,a,i" },
+{ "cpge", 0x4c000000, "c,a,b" },
+{ "cpge", 0x4d000000, "c,a,i" },
+{ "cpgeu", 0x4e000000, "c,a,b" },
+{ "cpgeu", 0x4f000000, "c,a,i" },
+{ "cpgt", 0x48000000, "c,a,b" },
+{ "cpgt", 0x49000000, "c,a,i" },
+{ "cpgtu", 0x4a000000, "c,a,b" },
+{ "cpgtu", 0x4b000000, "c,a,i" },
+{ "cple", 0x44000000, "c,a,b" },
+{ "cple", 0x45000000, "c,a,i" },
+{ "cpleu", 0x46000000, "c,a,b" },
+{ "cpleu", 0x47000000, "c,a,i" },
+{ "cplt", 0x40000000, "c,a,b" },
+{ "cplt", 0x41000000, "c,a,i" },
+{ "cpltu", 0x42000000, "c,a,b" },
+{ "cpltu", 0x43000000, "c,a,i" },
+{ "cpneq", 0x62000000, "c,a,b" },
+{ "cpneq", 0x63000000, "c,a,i" },
+{ "dadd", 0xf1000000, "c,a,b" },
+{ "ddiv", 0xf7000000, "c,a,b" },
+{ "deq", 0xeb000000, "c,a,b" },
+{ "dge", 0xef000000, "c,a,b" },
+{ "dgt", 0xed000000, "c,a,b" },
+{ "div", 0x6a000000, "c,a,b" },
+{ "div", 0x6b000000, "c,a,i" },
+{ "div0", 0x68000000, "c,b" },
+{ "div0", 0x69000000, "c,i" },
+{ "divide", 0xe1000000, "c,a,b" },
+{ "dividu", 0xe3000000, "c,a,b" },
+{ "divl", 0x6c000000, "c,a,b" },
+{ "divl", 0x6d000000, "c,a,i" },
+{ "divrem", 0x6e000000, "c,a,b" },
+{ "divrem", 0x6f000000, "c,a,i" },
+{ "dmac", 0xd9000000, "F,C,a,b" },
+{ "dmsm", 0xdb000000, "c,a,b" },
+{ "dmul", 0xf5000000, "c,a,b" },
+{ "dsub", 0xf3000000, "c,a,b" },
+{ "emulate", 0xd7000000, "v,a,b" },
+{ "exbyte", 0x0a000000, "c,a,b" },
+{ "exbyte", 0x0b000000, "c,a,i" },
+{ "exhw", 0x7c000000, "c,a,b" },
+{ "exhw", 0x7d000000, "c,a,i" },
+{ "exhws", 0x7e000000, "c,a" },
+{ "extract", 0x7a000000, "c,a,b" },
+{ "extract", 0x7b000000, "c,a,i" },
+{ "fadd", 0xf0000000, "c,a,b" },
+{ "fdiv", 0xf6000000, "c,a,b" },
+{ "fdmul", 0xf9000000, "c,a,b" },
+{ "feq", 0xea000000, "c,a,b" },
+{ "fge", 0xee000000, "c,a,b" },
+{ "fgt", 0xec000000, "c,a,b" },
+{ "fmac", 0xd8000000, "F,C,a,b" },
+{ "fmsm", 0xda000000, "c,a,b" },
+{ "fmul", 0xf4000000, "c,a,b" },
+{ "fsub", 0xf2000000, "c,a,b" },
+{ "halt", 0x89000000, "" },
+{ "inbyte", 0x0c000000, "c,a,b" },
+{ "inbyte", 0x0d000000, "c,a,i" },
+{ "inhw", 0x78000000, "c,a,b" },
+{ "inhw", 0x79000000, "c,a,i" },
+{ "inv", 0x9f000000, "" },
+{ "iret", 0x88000000, "" },
+{ "iretinv", 0x8c000000, "" },
+{ "jmp", 0xa0000000, "P" },
+{ "jmp", 0xa1000000, "A" },
+{ "jmpf", 0xa4000000, "a,P" },
+{ "jmpf", 0xa5000000, "a,A" },
+{ "jmpfdec", 0xb4000000, "a,P" },
+{ "jmpfdec", 0xb5000000, "a,A" },
+{ "jmpfi", 0xc4000000, "a,b" },
+{ "jmpi", 0xc0000000, "b" },
+{ "jmpt", 0xac000000, "a,P" },
+{ "jmpt", 0xad000000, "a,A" },
+{ "jmpti", 0xcc000000, "a,b" },
+{ "load", 0x16000000, "e,n,a,b" },
+{ "load", 0x17000000, "e,n,a,i" },
+{ "loadl", 0x06000000, "e,n,a,b" },
+{ "loadl", 0x07000000, "e,n,a,i" },
+{ "loadm", 0x36000000, "e,n,a,b" },
+{ "loadm", 0x37000000, "e,n,a,i" },
+{ "loadset", 0x26000000, "e,n,a,b" },
+{ "loadset", 0x27000000, "e,n,a,i" },
+{ "mfacc", 0xe9000100, "c,d,f" },
+{ "mfsr", 0xc6000000, "c,s" },
+{ "mftlb", 0xb6000000, "c,a" },
+{ "mtacc", 0xe8010000, "a,d,f" },
+{ "mtsr", 0xce000000, "s,b" },
+{ "mtsrim", 0x04000000, "s,x" },
+{ "mttlb", 0xbe000000, "a,b" },
+{ "mul", 0x64000000, "c,a,b" },
+{ "mul", 0x65000000, "c,a,i" },
+{ "mull", 0x66000000, "c,a,b" },
+{ "mull", 0x67000000, "c,a,i" },
+{ "multiplu", 0xe2000000, "c,a,b" },
+{ "multiply", 0xe0000000, "c,a,b" },
+{ "multm", 0xde000000, "c,a,b" },
+{ "multmu", 0xdf000000, "c,a,b" },
+{ "mulu", 0x74000000, "c,a,b" },
+{ "mulu", 0x75000000, "c,a,i" },
+{ "nand", 0x9a000000, "c,a,b" },
+{ "nand", 0x9b000000, "c,a,i" },
+{ "nop", 0x70400101, "" },
+{ "nor", 0x98000000, "c,a,b" },
+{ "nor", 0x99000000, "c,a,i" },
+{ "or", 0x92000000, "c,a,b" },
+{ "or", 0x93000000, "c,a,i" },
+{ "orn", 0xaa000000, "c,a,b" },
+{ "orn", 0xab000000, "c,a,i" },
+
+/* The description of "setip" in Chapter 8 ("instruction set") of the user's
+   manual claims that these are absolute register numbers.  But section
+   7.2.1 explains that they are not.  The latter is correct, so print
+   these normally ("lr0", "lr5", etc.).  */
+{ "setip", 0x9e000000, "c,a,b" },
+
+{ "sll", 0x80000000, "c,a,b" },
+{ "sll", 0x81000000, "c,a,i" },
+{ "sqrt", 0xe5000000, "c,a,f" },
+{ "sra", 0x86000000, "c,a,b" },
+{ "sra", 0x87000000, "c,a,i" },
+{ "srl", 0x82000000, "c,a,b" },
+{ "srl", 0x83000000, "c,a,i" },
+{ "store", 0x1e000000, "e,n,a,b" },
+{ "store", 0x1f000000, "e,n,a,i" },
+{ "storel", 0x0e000000, "e,n,a,b" },
+{ "storel", 0x0f000000, "e,n,a,i" },
+{ "storem", 0x3e000000, "e,n,a,b" },
+{ "storem", 0x3f000000, "e,n,a,i" },
+{ "sub", 0x24000000, "c,a,b" },
+{ "sub", 0x25000000, "c,a,i" },
+{ "subc", 0x2c000000, "c,a,b" },
+{ "subc", 0x2d000000, "c,a,i" },
+{ "subcs", 0x28000000, "c,a,b" },
+{ "subcs", 0x29000000, "c,a,i" },
+{ "subcu", 0x2a000000, "c,a,b" },
+{ "subcu", 0x2b000000, "c,a,i" },
+{ "subr", 0x34000000, "c,a,b" },
+{ "subr", 0x35000000, "c,a,i" },
+{ "subrc", 0x3c000000, "c,a,b" },
+{ "subrc", 0x3d000000, "c,a,i" },
+{ "subrcs", 0x38000000, "c,a,b" },
+{ "subrcs", 0x39000000, "c,a,i" },
+{ "subrcu", 0x3a000000, "c,a,b" },
+{ "subrcu", 0x3b000000, "c,a,i" },
+{ "subrs", 0x30000000, "c,a,b" },
+{ "subrs", 0x31000000, "c,a,i" },
+{ "subru", 0x32000000, "c,a,b" },
+{ "subru", 0x33000000, "c,a,i" },
+{ "subs", 0x20000000, "c,a,b" },
+{ "subs", 0x21000000, "c,a,i" },
+{ "subu", 0x22000000, "c,a,b" },
+{ "subu", 0x23000000, "c,a,i" },
+{ "xnor", 0x96000000, "c,a,b" },
+{ "xnor", 0x97000000, "c,a,i" },
+{ "xor", 0x94000000, "c,a,b" },
+{ "xor", 0x95000000, "c,a,i" },
+
+{ "", 0x0, "" }		/* Dummy entry, not included in NUM_OPCODES.  This
+			   lets code examine entry i+1 without checking
+			   if we've run off the end of the table.  */
+};
+
+CONST unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);
+
+/*
+ * $Log: a29k.h,v $
+ * Revision 1.1  1995/10/18 08:39:09  deraadt
+ * Initial revision
+ *
+ * Revision 1.1  1993/10/02 21:00:40  pk
+ * GNU gas 1.92.3 based assembler supporting PIC code (for i386 and sparc).
+ *
+ * Revision 1.2  1992/02/29  17:10:43  rich
+ * various smallish fixes from mail archives
+ *
+ * Revision 1.1.1.1  1992/02/24  02:34:30  rich
+ * devo fork
+ *
+ * Revision 1.1  1991/12/01  02:22:19  sac
+ * Initial revision
+ *
+ * Revision 1.5  1991/11/07  16:59:19  sac
+ * Fixed encoding of mtacc instruction.
+ *
+ * Revision 1.4  1991/08/06  07:20:27  rich
+ * Fixing CONST declarations.
+ *
+ * Revision 1.3  1991/08/05  22:31:05  rich
+ * *** empty log message ***
+ *
+ * Revision 1.2  1991/07/15  23:34:04  steve
+ * *** empty log message ***
+ *
+ * Revision 1.1  1991/05/19  00:19:33  rich
+ * Initial revision
+ *
+ * Revision 1.1.1.1  1991/04/04  18:15:23  rich
+ * new gas main line
+ *
+ * Revision 1.1  1991/04/04  18:15:23  rich
+ * Initial revision
+ *
+ * Revision 1.2  1991/03/30  17:13:19  rich
+ * num_opcodes now unsigned.  Also, added rcsid and log.
+ *
+ *
+ */
+
+/* end of a29k-opcode.h */
diff --git a/gnu/usr.bin/gas/opcode/h8300.h b/gnu/usr.bin/gas/opcode/h8300.h
new file mode 100644
index 00000000000..f4702a8f2f1
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/h8300.h
@@ -0,0 +1,266 @@
+/* Opcode table for the H8-300
+   Copyright (C) 1991,1992 Free Software Foundation.
+   Written by Steve Chamberlain, sac@cygnus.com.
+
+This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+typedef int op_type;
+
+#define Hex0	0
+#define Hex1 	1
+#define Hex2 	2
+#define Hex3 	3
+#define Hex4 	4
+#define Hex5 	5
+#define Hex6 	6
+#define Hex7 	7
+#define Hex8 	8
+#define Hex9 	9
+#define HexA 	10
+#define HexB 	11
+#define HexC 	12
+#define HexD 	13
+#define HexE 	14
+#define HexF 	15
+#define START  		0x20
+#define KBIT 		0x21		/* K is #1, or #2, yielding 0x0 or 0x8 */
+#define IMM3 		0x22		/* bit number */
+#define RD8 		0x23		/* 8 bit reg as 2nd op  */
+#define RD16 		0x24		/* 16 bit reg as 2nd op */
+#define RS8 		0x25		/* 8 bit reg as 1st op */
+#define RS16 		0x26		/* 16 bit reg 1st op */
+#define IMM8 		0x27		/* constant which fits into 8 bits */
+#define IMM16 		0x28		/* constant which fits into 16 bits */
+#define CCR 		0x29		/* CCR reg */
+#define ABS8SRC 	0x2a		/* abs 8 address mode */
+#define ABS8DST		0x2b		/* abs 8 address mode */
+#define DISP8 		0x2c		/* pc rel displacement */
+#define ABS16SRC 	0x2d		/* abs 16 address mode */
+#define ABS16OR8SRC 	0x2e		/* abs 16 address mode, but could be abs 8 */
+#define ABS16DST 	0x2f		/* abs 16 address mode */
+#define ABS16OR8DST 	0x30		/* abs 16 address mode */
+#define DISPSRC 	0x31		/* @(r:16) address mode src */
+#define DISPDST 	0x32		/* @(r:16) address mode dst*/
+#define DISPREG 	0x33		/* register from DISP address mode */
+#define RDDEC 		0x34		/* @-rn mode */
+#define RSINC 		0x35		/* @rn+ mode */
+#define RDIND 		0x36		/* @R mode dst */
+#define RSIND 		0x37		/* @R mode src */
+#define MEMIND 		0x38		/* @@abs8 mode */
+#define ABS16ORREL8SRC	0x39          	/* abs 16bit or pcrel */
+#define IGNORE 		0x3a
+#define B30  		0x40 		/* bit 3 must be low */
+#define B31  		0x80		/* bit 3 must be high */
+#define E      		0x81		/* End of list */
+
+
+
+struct code 
+{
+  op_type nib[9];
+} ;
+
+struct arg 
+{
+  op_type nib[3];
+} ;
+
+struct h8_opcode 
+{
+    char *name;
+    struct arg args;
+    struct code data;
+    char length;
+    char noperands;
+    char idx;
+    char size;
+    
+};
+
+
+
+
+
+#ifdef DEFINE_TABLE
+
+#define BITOP(imm, name, op00, op01,op10,op11, op20,op21)\
+{  name,	{imm,RD8,E},	{op00, op01, imm, RD8,E}},\
+{  name,	{imm,RDIND,E},	{op10, op11, RDIND, 0, op00,op01, imm, 0,E}},\
+{  name,	{imm,ABS8DST,E},{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}
+
+#define EBITOP(imm, name, op00, op01,op10,op11, op20,op21)\
+   BITOP(imm, name, op00+1, op01, op10,op11, op20,op21),\
+   BITOP(RS8,  name, op00, op01, op10,op11, op20,op21)
+
+#define WTWOP(name, op1, op2) \
+{ name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E}}
+
+#define BRANCH(name, op) \
+{ name,{DISP8,E}, { Hex4, op, DISP8,IGNORE,E }}
+
+#define SOP(name) \
+{  name 
+#define EOP   }
+
+
+#define TWOOP(name, op1, op2,op3) \
+{ name, {IMM8, RD8,E},	{ op1, RD8, IMM8,IGNORE,E}},\
+{ name, {RS8, RD8, E},	{ op2, op3, RS8, RD8 ,E}} 
+
+#define UNOP(name, op1, op2) \
+{ name, {RS8, E}, { op1, op2, 0, RS8, E}}
+
+#define UNOP3(name, op1, op2, op3) \
+{ name , {RS8, E}, {op1, op2, op3, RS8, E}}
+
+struct h8_opcode h8_opcodes[] 
+= 
+{
+  TWOOP("add.b", Hex8, Hex0,Hex8),
+  WTWOP("add.w", Hex0, Hex9),
+  SOP("adds"), {KBIT,RD16|B30, E}, {Hex0, HexB, KBIT, RD16|B30, E} EOP,
+  TWOOP("addx", Hex9,Hex0,HexE),
+  TWOOP("and", HexE,Hex1,Hex6),
+  SOP("andc"),  {IMM8, CCR, E}, { Hex0, Hex6, IMM8,IGNORE, E} EOP,
+  BITOP(IMM3|B30, "band", Hex7, Hex6, Hex7, HexC, Hex7, HexE),
+  BRANCH("bra", Hex0),
+  BRANCH("bt", Hex0),
+  BRANCH("brn", Hex1),
+  BRANCH("bf", Hex1),
+  BRANCH("bhi", Hex2),
+  BRANCH("bls", Hex3),
+  BRANCH("bcc", Hex4),
+  BRANCH("bhs", Hex4),
+  BRANCH("bcs", Hex5),
+  BRANCH("blo", Hex5),
+  BRANCH("bne", Hex6),
+  BRANCH("beq", Hex7),
+  BRANCH("bvc", Hex8),
+  BRANCH("bvs", Hex9),
+  BRANCH("bpl", HexA),
+  BRANCH("bmi", HexB),
+  BRANCH("bge", HexC),
+  BRANCH("blt", HexD),
+  BRANCH("bgt", HexE),
+  BRANCH("ble", HexF),
+  EBITOP(IMM3|B30,"bclr", Hex6, Hex2, Hex7, HexD, Hex7, HexF),
+  BITOP(IMM3|B31,"biand", Hex7, Hex6, Hex7, HexC, Hex7, HexE),
+  BITOP(IMM3|B31, "bild", Hex7, Hex7,Hex7, HexC, Hex7, HexE),
+  BITOP(IMM3|B31, "bior", Hex7, Hex4,Hex7, HexC, Hex7, HexE),
+  BITOP(IMM3|B31, "bist", Hex6, Hex7,Hex7, HexD, Hex7, HexE),
+  BITOP(IMM3|B31, "bixor", Hex7, Hex5,Hex7, HexC, Hex7, HexE),
+  BITOP(IMM3|B30, "bld", Hex7, Hex7,Hex7, HexC, Hex7, HexE),
+  EBITOP(IMM3|B30,"bnot", Hex6, Hex1, Hex7, HexD, Hex7, HexF),
+  BITOP(IMM3|B30,"bor", Hex7, Hex4,Hex7, HexC, Hex7, HexE),
+  EBITOP(IMM3|B30,"bset", Hex6, Hex0,Hex7, HexD, Hex7, HexF),
+  SOP("bsr"),{DISP8, E},{ Hex5, Hex5, DISP8,IGNORE, E}, EOP,
+  BITOP(IMM3|B30, "bst", Hex6, Hex7,Hex7, HexD, Hex7, HexF),
+  EBITOP(IMM3|B30, "btst", Hex6, Hex3,Hex7, HexC, Hex7, HexE),
+  BITOP(IMM3|B30, "bxor", Hex7,Hex5,Hex7, HexC, Hex7, HexE),
+  TWOOP( "cmp.b",HexA, Hex1, HexC),
+  WTWOP( "cmp.w",Hex1,HexD),
+  UNOP( "daa",Hex0, HexF),
+  UNOP( "das",Hex1, HexF),
+  UNOP( "dec",Hex1, HexA),
+  SOP("divxu"),{RS8, RD16|B30, E}, { Hex5, Hex1, RS8, RD16|B30, E} EOP,
+  SOP("eepmov"),{ E}, {Hex7, HexB, Hex5, HexC, Hex5, Hex9, Hex8, HexF,E} EOP,
+  UNOP( "inc", Hex0, HexA),
+  SOP("jmp"),{RSIND|B30, E}, {Hex5, Hex9, RSIND|B30, Hex0, E} EOP,
+  SOP("jmp"),{ABS16ORREL8SRC, E}, {Hex5, HexA, Hex0, Hex0, ABS16ORREL8SRC, IGNORE,IGNORE,IGNORE,E} EOP,
+  SOP("jmp"),{MEMIND, E}, {Hex5, HexB, MEMIND,IGNORE, E} EOP,
+  SOP("jsr"),{RSIND|B30, E}, {Hex5, HexD, RSIND|B30, Hex0, E} EOP,
+  SOP("jsr"),{ABS16ORREL8SRC, E}, {Hex5, HexE, Hex0, Hex0,
+			      ABS16ORREL8SRC,IGNORE,IGNORE,IGNORE, E} EOP,
+  SOP("jsr"),{MEMIND, E}, {Hex5, HexF, MEMIND, IGNORE,E} EOP,
+  SOP("ldc"),{IMM8, CCR, E}, { Hex0, Hex7, IMM8,IGNORE, E} EOP,
+  SOP("ldc"),{RS8, CCR, E}, { Hex0, Hex3, Hex0, RS8, E} EOP,
+  SOP("mov.b"),{RS8, RD8, E}, { Hex0, HexC, RS8, RD8, E} EOP,
+  SOP("mov.b"),{IMM8, RD8, E}, { HexF, RD8, IMM8,IGNORE, E} EOP,
+  SOP("mov.b"),{RSIND|B30,RD8, E}, { Hex6, Hex8, RSIND|B30, RD8, E} EOP,
+  SOP("mov.b"),{DISPSRC,RD8, E}, { Hex6, HexE, DISPREG|B30, RD8,
+				    DISPSRC, IGNORE, IGNORE, IGNORE, E} EOP,
+  SOP("mov.b"),{RSINC|B30, RD8, E}, { Hex6, HexC, RSINC|B30, RD8, E} EOP,
+  SOP("mov.b"),{ABS16OR8SRC, RD8, E}, { Hex6, HexA, Hex0, RD8,ABS16OR8SRC,
+				      IGNORE,IGNORE,IGNORE,E} EOP,
+  SOP("mov.b"),{ABS8SRC, RD8, E}, { Hex2, RD8, ABS8SRC,IGNORE, E} EOP,
+  SOP("mov.b"),{RS8, RDIND|B30, E}, { Hex6, Hex8, RDIND|B31, RS8, E} EOP,
+  SOP("mov.b"),{RS8, DISPDST, E}, { Hex6, HexE, DISPREG|B31,
+				     RS8,DISPDST, IGNORE, IGNORE, IGNORE, E} EOP,
+  SOP("mov.b"),{RS8, RDDEC|B31, E}, { Hex6, HexC, RDDEC|B31, RS8, E} EOP,
+  SOP( "mov.b"),{RS8, ABS16OR8DST, E}, { Hex6, HexA, Hex8, RS8,
+				       ABS16OR8DST,IGNORE,IGNORE,IGNORE, E} EOP,
+  SOP( "mov.b"),{RS8, ABS8DST, E}, { Hex3, RS8, ABS8DST,IGNORE, E} EOP,
+  SOP( "mov.w"),{RS16|B30, RD16|B30, E},{ Hex0, HexD, RS16|B30,
+					   RD16|B30, E} EOP,
+  SOP("mov.w"),{IMM16, RD16|B30, E}, { Hex7, Hex9, Hex0, RD16|B30,
+					IMM16,IGNORE,IGNORE,IGNORE, E} EOP,
+  SOP("mov.w"),{RSIND|B30,RD16|B30, E},{ Hex6, Hex9, RSIND|B30,
+					  RD16|B30, E} EOP,
+  SOP("mov.w"),{DISPSRC,RD16|B30, E}, { Hex6, HexF, DISPREG|B30,
+					 RD16|B30, DISPSRC, IGNORE, IGNORE, IGNORE,E} EOP,
+  SOP("mov.w"),{RSINC|B30, RD16|B30, E}, { Hex6, HexD, RSINC|B30,
+ RD16|B30, E}EOP,
+  SOP("mov.w"), {ABS16SRC, RD16|B30, E}, { Hex6, HexB, Hex0,
+					  RD16|B30,ABS16SRC,IGNORE,IGNORE,IGNORE, E} EOP,
+SOP("mov.w"),  {RS16|B30, RDIND|B30, E},{ Hex6, Hex9, RDIND|B31,
+					   RS16|B30, E} EOP,
+SOP("mov.w"), {RS16|B30, DISPDST, E}, { Hex6, HexF, DISPREG|B31,
+					 RS16|B30,DISPDST, IGNORE,IGNORE,IGNORE,E} EOP,
+SOP("mov.w"), {RS16|B30, RDDEC|B30, E},{ Hex6, HexD, RDDEC|B31,
+					  RS16|B30, E} EOP,
+SOP("mov.w"), {RS16|B30, ABS16DST, E}, { Hex6, HexB, Hex8, RS16|B30,
+					  ABS16DST, IGNORE, IGNORE, IGNORE, E} EOP,
+SOP("movfpe"), {ABS16SRC, RD8, E}, { Hex6, HexA, Hex4, RD8,
+				      ABS16SRC,IGNORE,IGNORE,IGNORE, E} EOP,
+SOP("movtpe"), {RS8, ABS16DST, E}, { Hex6, HexA, HexC, RS8,
+				      ABS16DST,IGNORE,IGNORE,IGNORE,
+				      E} EOP,
+SOP("mulxu"), {RS8, RD16|B30, E}, { Hex5, Hex0, RS8, RD16|B30, E} EOP,
+SOP( "neg"), {RS8, E},  { Hex1, Hex7, Hex8, RS8, E} EOP,
+SOP( "nop"), {E},  { Hex0, Hex0, Hex0, Hex0,E} EOP,
+SOP( "not"), {RS8,E},  { Hex1, Hex7, Hex0, RS8,E} EOP,
+TWOOP("or", HexC, Hex1, Hex4),
+SOP( "orc"), {IMM8, CCR,E}, { Hex0, Hex4, IMM8,IGNORE,E} EOP,
+SOP( "pop"), {RS16|B30,E},  { Hex6, HexD, Hex7, RS16|B30,E} EOP,
+SOP( "push"), {RS16|B30,E},  { Hex6, HexD, HexF, RS16|B30,E} EOP,
+ UNOP3( "rotl",Hex1, Hex2,Hex8),
+ UNOP3( "rotr",Hex1, Hex3, Hex8),
+ UNOP3( "rotxl",Hex1, Hex2, Hex0),
+ UNOP3( "rotxr",Hex1, Hex3, Hex0),
+SOP("rte"), {E},  { Hex5, Hex6, Hex7, Hex0,E} EOP,
+SOP("rts"), {E},  { Hex5, Hex4, Hex7, Hex0,E} EOP,
+ UNOP3( "shal", Hex1, Hex0, Hex8),
+ UNOP3( "shar", Hex1, Hex1, Hex8),
+ UNOP3( "shll", Hex1, Hex0, Hex0),
+ UNOP3( "shlr", Hex1, Hex1, Hex0),
+SOP("sleep"), {E},  { Hex0, Hex1, Hex8, Hex0,E} EOP,
+SOP("stc"), {CCR, RD8,E}, { Hex0, Hex2, Hex0, RD8,E} EOP,
+SOP("sub.b"), {RS8,RD8,E}, { Hex1, Hex8, RS8, RD8,E} EOP,
+SOP("sub.w"), {RS16|B30, RD16|B30,E},  {Hex1, Hex9, RS16|B30,RD16|B30,E} EOP,
+SOP("subs"), {KBIT,RD16|B30,E}, { Hex1, HexB, KBIT, RD16|B30,E} EOP,
+ TWOOP("subx",HexB, Hex1, HexE),
+ TWOOP("xor", HexD, Hex1, Hex5), 
+SOP("xorc"), {IMM8, CCR,E}, { Hex0, Hex5, IMM8,IGNORE,E} EOP,
+ 0
+};
+#else
+extern struct h8_opcode h8_opcodes[] ;
+#endif
+
+
+
+
diff --git a/gnu/usr.bin/gas/opcode/i386.h b/gnu/usr.bin/gas/opcode/i386.h
new file mode 100644
index 00000000000..7507408d5bf
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/i386.h
@@ -0,0 +1,835 @@
+/* i386-opcode.h -- Intel 80386 opcode table
+   Copyright (C) 1989, 1991, Free Software Foundation.
+
+This file is part of GAS, the GNU Assembler.
+
+GAS is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GAS is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+   
+/* $Id: i386.h,v 1.1 1995/10/18 08:39:09 deraadt Exp $ */
+
+static const template i386_optab[] = {
+
+#define _ None
+/* move instructions */
+{ "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 },
+{ "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 },
+{ "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 },
+{ "mov", 2, 0xc6, _,  W|Modrm,  Imm, Reg|Mem, 0 },
+{ "mov", 2, 0x8c, _, D|Modrm,  SReg3|SReg2, Reg16|Mem16, 0 },
+/* move to/from control debug registers */
+{ "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0},
+{ "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0},
+{ "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0},
+
+/* move with sign extend */
+/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
+   conflict with the "movs" string move instruction.  Thus,
+   {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg16|Reg32, 0},
+   is not kosher; we must seperate the two instructions. */
+{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg32, 0},
+{"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg16, 0},
+{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
+
+/* move with zero extend */
+{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
+{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
+
+/* push instructions */
+{"push", 1, 0x50, _, ShortForm, WordReg,0,0 },
+{"push", 1, 0xff, 0x6,  Modrm, WordReg|WordMem, 0, 0 },
+{"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0},
+{"push", 1, 0x68, _, NoModrm, Imm16|Imm32, 0, 0},
+{"push", 1, 0x06, _,  Seg2ShortForm, SReg2,0,0 },
+{"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 },
+/* push all */
+{"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 },
+
+/* pop instructions */
+{"pop", 1, 0x58, _, ShortForm, WordReg,0,0 },
+{"pop", 1, 0x8f, 0x0,  Modrm, WordReg|WordMem, 0, 0 },
+#define POP_SEG_SHORT 0x7
+{"pop", 1, 0x07, _,  Seg2ShortForm, SReg2,0,0 },
+{"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 },
+/* pop all */
+{"popa", 0, 0x61, _, NoModrm, 0, 0, 0 },
+
+/* xchg exchange instructions
+   xchg commutes:  we allow both operand orders */
+{"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 },
+{"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 },
+{"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 },
+{"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 },
+
+/* in/out from ports */
+{"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 },
+{"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 },
+{"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 },
+{"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 },
+
+#if 0
+{"inb",  1, 0xe4, _, NoModrm, Imm8, 0, 0 },
+{"inb",  1, 0xec, _, NoModrm, WordMem, 0, 0 },
+{"inw",  1, 0x66e5, _, NoModrm, Imm8, 0, 0 },
+{"inw",  1, 0x66ed, _, NoModrm, WordMem, 0, 0 },
+{"outb", 1, 0xe6, _, NoModrm, Imm8, 0, 0 },
+{"outb", 1, 0xee, _, NoModrm, WordMem, 0, 0 },
+{"outw", 1, 0x66e7, _, NoModrm, Imm8, 0, 0 },
+{"outw", 1, 0x66ef, _, NoModrm, WordMem, 0, 0 },
+#endif
+
+/* load effective address */
+{"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 },
+
+/* load segment registers from memory */
+{"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0},
+{"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0},
+{"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0},
+{"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0},
+{"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0},
+
+/* flags register instructions */
+{"clc", 0, 0xf8, _, NoModrm, 0, 0, 0},
+{"cld", 0, 0xfc, _, NoModrm, 0, 0, 0},
+{"cli", 0, 0xfa, _, NoModrm, 0, 0, 0},
+{"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0},
+{"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0},
+{"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0},
+{"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0},
+{"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0},
+{"popf", 0, 0x9d, _, NoModrm, 0, 0, 0},
+{"stc", 0, 0xf9, _, NoModrm, 0, 0, 0},
+{"std", 0, 0xfd, _, NoModrm, 0, 0, 0},
+{"sti", 0, 0xfb, _, NoModrm, 0, 0, 0},
+
+{"add", 2, 0x0,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"add", 2, 0x83, 0,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"add", 2, 0x4,  _,  W|NoModrm, Imm,  Acc,    0},
+{"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0},
+
+{"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0},
+{"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0},
+
+{"sub", 2, 0x28,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"sub", 2, 0x83, 5,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"sub", 2, 0x2c,  _,  W|NoModrm, Imm,  Acc,    0},
+{"sub", 2, 0x80, 5,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0},
+{"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0},
+
+{"sbb", 2, 0x18,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"sbb", 2, 0x83, 3,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"sbb", 2, 0x1c,  _,  W|NoModrm, Imm,  Acc,    0},
+{"sbb", 2, 0x80, 3,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"cmp", 2, 0x38,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"cmp", 2, 0x83, 7,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"cmp", 2, 0x3c,  _,  W|NoModrm, Imm,  Acc,    0},
+{"cmp", 2, 0x80, 7,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0},
+{"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0},
+{"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0},
+{"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0},
+
+{"and", 2, 0x20,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"and", 2, 0x83, 4,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"and", 2, 0x24,  _,  W|NoModrm, Imm,  Acc,    0},
+{"and", 2, 0x80, 4,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"or", 2, 0x08,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"or", 2, 0x83, 1,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"or", 2, 0x0c,  _,  W|NoModrm, Imm,  Acc,    0},
+{"or", 2, 0x80, 1,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"xor", 2, 0x30,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"xor", 2, 0x83, 6,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"xor", 2, 0x34,  _,  W|NoModrm, Imm,  Acc,    0},
+{"xor", 2, 0x80, 6,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"adc", 2, 0x10,  _, DW|Modrm, Reg, Reg|Mem, 0},
+{"adc", 2, 0x83, 2,  Modrm, Imm8S, WordReg|WordMem, 0},
+{"adc", 2, 0x14,  _,  W|NoModrm, Imm,  Acc,    0},
+{"adc", 2, 0x80, 2,  W|Modrm, Imm, Reg|Mem, 0},
+
+{"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0},
+{"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0},
+
+{"aaa", 0, 0x37, _, NoModrm, 0, 0, 0},
+{"aas", 0, 0x3f, _, NoModrm, 0, 0, 0},
+{"daa", 0, 0x27, _, NoModrm, 0, 0, 0},
+{"das", 0, 0x2f, _, NoModrm, 0, 0, 0},
+{"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0},
+{"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0},
+
+/* conversion insns */
+/* conversion:  intel naming */
+{"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0},
+{"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0},
+{"cwde", 0, 0x98, _, NoModrm, 0, 0, 0},
+{"cdq", 0, 0x99, _, NoModrm, 0, 0, 0},
+/*  att naming */
+{"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0},
+{"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0},
+{"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0},
+{"cltd", 0, 0x99, _, NoModrm, 0, 0, 0},
+
+/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
+   expanding 64-bit multiplies, and *cannot* be selected to accomplish
+   'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
+   These multiplies can only be selected with single opearnd forms. */
+{"mul",  1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0},
+{"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0},
+
+
+
+
+/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
+   These instructions are exceptions:  'imul $2, %eax, %ecx' would put
+   '%eax' in the reg field and '%ecx' in the regmem field if we did not
+   switch them. */
+{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
+{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg},
+{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg},
+/*
+  imul with 2 operands mimicks imul with 3 by puting register both
+  in i.rm.reg & i.rm.regmem fields
+*/
+{"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0},
+{"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0},
+{"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0},
+{"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0},
+{"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0},
+{"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0},
+
+{"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0},
+{"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0},
+{"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0},
+
+{"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0},
+{"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0},
+{"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0},
+
+{"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0},
+{"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0},
+{"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0},
+
+{"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0},
+{"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0},
+{"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0},
+
+{"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
+{"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
+{"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
+{"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
+{"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
+{"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
+
+{"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem},
+{"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
+
+{"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0},
+{"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0},
+{"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0},
+
+{"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem},
+{"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
+
+{"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0},
+{"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0},
+{"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0},
+{"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0},
+
+/* control transfer instructions */
+#define CALL_PC_RELATIVE 0xe8
+{"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0},
+{"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0},
+#define CALL_FAR_IMMEDIATE 0x9a
+{"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Abs32, 0},
+{"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0},
+
+#define JUMP_PC_RELATIVE 0xeb
+{"jmp", 1, 0xeb, _, Jump, Disp, 0, 0},
+{"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0},
+#define JUMP_FAR_IMMEDIATE 0xea
+{"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0},
+{"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0},
+
+{"ret", 0, 0xc3, _, NoModrm, 0, 0, 0},
+{"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0},
+{"lret", 0, 0xcb, _, NoModrm, 0, 0, 0},
+{"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0},
+{"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0},
+{"leave", 0, 0xc9, _, NoModrm, 0, 0, 0},
+
+/* conditional jumps */
+{"jo", 1, 0x70, _, Jump, Disp, 0, 0},
+
+{"jno", 1, 0x71, _, Jump, Disp, 0, 0},
+
+{"jb", 1, 0x72, _, Jump, Disp, 0, 0},
+{"jc", 1, 0x72, _, Jump, Disp, 0, 0},
+{"jnae", 1, 0x72, _, Jump, Disp, 0, 0},
+
+{"jnb", 1, 0x73, _, Jump, Disp, 0, 0},
+{"jnc", 1, 0x73, _, Jump, Disp, 0, 0},
+{"jae", 1, 0x73, _, Jump, Disp, 0, 0},
+
+{"je", 1, 0x74, _, Jump, Disp, 0, 0},
+{"jz", 1, 0x74, _, Jump, Disp, 0, 0},
+
+{"jne", 1, 0x75, _, Jump, Disp, 0, 0},
+{"jnz", 1, 0x75, _, Jump, Disp, 0, 0},
+
+{"jbe", 1, 0x76, _, Jump, Disp, 0, 0},
+{"jna", 1, 0x76, _, Jump, Disp, 0, 0},
+
+{"jnbe", 1, 0x77, _, Jump, Disp, 0, 0},
+{"ja", 1, 0x77, _, Jump, Disp, 0, 0},
+
+{"js", 1, 0x78, _, Jump, Disp, 0, 0},
+
+{"jns", 1, 0x79, _, Jump, Disp, 0, 0},
+
+{"jp", 1, 0x7a, _, Jump, Disp, 0, 0},
+{"jpe", 1, 0x7a, _, Jump, Disp, 0, 0},
+
+{"jnp", 1, 0x7b, _, Jump, Disp, 0, 0},
+{"jpo", 1, 0x7b, _, Jump, Disp, 0, 0},
+
+{"jl", 1, 0x7c, _, Jump, Disp, 0, 0},
+{"jnge", 1, 0x7c, _, Jump, Disp, 0, 0},
+
+{"jnl", 1, 0x7d, _, Jump, Disp, 0, 0},
+{"jge", 1, 0x7d, _, Jump, Disp, 0, 0},
+
+{"jle", 1, 0x7e, _, Jump, Disp, 0, 0},
+{"jng", 1, 0x7e, _, Jump, Disp, 0, 0},
+
+{"jnle", 1, 0x7f, _, Jump, Disp, 0, 0},
+{"jg", 1, 0x7f, _, Jump, Disp, 0, 0},
+
+/* these turn into pseudo operations when disp is larger than 8 bits */
+#define IS_JUMP_ON_CX_ZERO(o) \
+  (o == 0x67e3)
+#define IS_JUMP_ON_ECX_ZERO(o) \
+  (o == 0xe3)
+
+{"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0},
+{"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0},
+
+#define IS_LOOP_ECX_TIMES(o) \
+  (o == 0xe2 || o == 0xe1 || o == 0xe0)
+
+{"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0},
+
+{"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0},
+{"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0},
+
+{"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0},
+{"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0},
+
+/* set byte on flag instructions */
+{"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setc", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
+{"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
+{"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setnc", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
+{"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
+{"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
+{"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
+{"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
+{"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
+{"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
+{"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
+{"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
+{"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
+{"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
+{"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
+
+{"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
+{"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
+
+#define IS_STRING_INSTRUCTION(o) \
+  ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
+   (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
+   (o) == 0xd7)
+
+/* string manipulation */
+{"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0},
+{"scmp", 0, 0xa6, _, W|NoModrm, 0, 0, 0},
+{"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0},
+{"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0},
+{"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0},
+{"slod", 0, 0xac, _, W|NoModrm, 0, 0, 0},
+{"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0},
+{"smov", 0, 0xa4, _, W|NoModrm, 0, 0, 0},
+{"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0},
+{"ssca", 0, 0xae, _, W|NoModrm, 0, 0, 0},
+{"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0},
+{"ssto", 0, 0xaa, _, W|NoModrm, 0, 0, 0},
+{"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0},
+
+/* bit manipulation */
+{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
+{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
+{"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0},
+{"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0},
+{"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0},
+{"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0},
+{"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0},
+{"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0},
+{"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0},
+{"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0},
+
+/* interrupts & op. sys insns */
+/* See i386.c for conversion of 'int $3' into the special int 3 insn. */
+#define INT_OPCODE 0xcd
+#define INT3_OPCODE 0xcc
+{"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0},
+{"int3", 0, 0xcc, _, NoModrm, 0, 0, 0},
+{"into", 0, 0xce, _, NoModrm, 0, 0, 0},
+{"iret", 0, 0xcf, _, NoModrm, 0, 0, 0},
+
+{"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0},
+{"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0},
+
+{"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0},
+{"wait", 0, 0x9b, _, NoModrm, 0, 0, 0},
+/* nop is actually 'xchgl %eax, %eax' */
+{"nop", 0, 0x90, _, NoModrm, 0, 0, 0},
+
+/* protection control */
+{"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0},
+{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
+{"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0},
+{"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0},
+{"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0},
+{"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0},
+{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
+{"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0},
+
+{"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0},
+{"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0},
+{"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0},
+{"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0},
+{"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0},
+
+{"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0},
+{"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0},
+
+/* floating point instructions */
+
+/* load */
+{"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0},           /* %st0 <-- mem float */
+{"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0},           /* %st0 <-- mem word */
+{"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0},           /* %st0 <-- mem double */
+{"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0},           /* %st0 <-- mem dword */
+{"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0},           /* %st0 <-- mem qword */
+{"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0},           /* %st0 <-- mem efloat */
+{"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0},           /* %st0 <-- mem bcd */
+
+/* store (no pop) */
+{"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0},           /* %st0 --> mem float */
+{"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0},           /* %st0 --> mem dword */
+{"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0},           /* %st0 --> mem double */
+{"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0},           /* %st0 --> mem word */
+
+/* store (with pop) */
+{"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0},           /* %st0 --> mem float */
+{"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0},           /* %st0 --> mem word */
+{"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0},           /* %st0 --> mem double */
+{"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
+{"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0},           /* %st0 --> mem dword */
+{"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0},           /* %st0 --> mem qword */
+{"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0},           /* %st0 --> mem efloat */
+{"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0},           /* %st0 --> mem bcd */
+
+/* exchange %st<n> with %st0 */
+{"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0},
+
+/* comparison (without pop) */
+{"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
+{"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float  */
+{"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word  */ 
+{"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double  */
+{"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
+{"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
+
+/* comparison (with pop) */
+{"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
+{"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float  */
+{"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word  */ 
+{"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double  */
+{"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
+{"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
+{"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
+
+/* unordered comparison (with pop) */
+{"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0},
+{"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0},
+{"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
+
+{"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0},   /* test %st0 */
+{"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0},   /* examine %st0 */
+
+/* load constants into %st0 */
+{"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0},   /* %st0 <-- 1.0 */
+{"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0},   /* %st0 <-- log2(10) */
+{"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0},   /* %st0 <-- log2(e) */
+{"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0},   /* %st0 <-- pi */
+{"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0},   /* %st0 <-- log10(2) */
+{"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0},   /* %st0 <-- ln(2) */
+{"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0},   /* %st0 <-- 0.0 */
+
+/* arithmetic */
+
+/* add */
+{"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0},
+{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
+{"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */
+{"faddp", 1, 0xdec0, _, ShortForm, FloatReg, 0, 0},
+{"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
+{"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */
+{"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0},
+{"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0},
+{"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0},
+{"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0},
+
+/* sub */
+/* Note:  intel has decided that certain of these operations are reversed
+   in assembler syntax. */
+{"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0},
+{"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0},
+{"fsubp", 1, 0xdee0, _, ShortForm, FloatReg, 0, 0},
+{"fsubp", 2, 0xdee0, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0},
+{"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0},
+{"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0},
+{"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0},
+{"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0},
+
+/* sub reverse */
+{"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0},
+{"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0},
+{"fsubrp", 1, 0xdee8, _, ShortForm, FloatReg, 0, 0},
+{"fsubrp", 2, 0xdee8, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0},
+{"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0},
+{"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0},
+{"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0},
+{"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0},
+
+/* mul */
+{"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0},
+{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
+{"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0},
+{"fmulp", 1, 0xdec8, _, ShortForm, FloatReg, 0, 0},
+{"fmulp", 2, 0xdec8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
+{"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0},
+{"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0},
+{"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0},
+{"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0},
+{"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0},
+
+/* div */
+/* Note:  intel has decided that certain of these operations are reversed
+   in assembler syntax. */
+{"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0},
+{"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0},
+{"fdivp", 1, 0xdef0, _, ShortForm, FloatReg, 0, 0},
+{"fdivp", 2, 0xdef0, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0},
+{"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0},
+{"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0},
+{"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0},
+{"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0},
+
+/* div reverse */
+{"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0},
+{"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0},
+{"fdivrp", 1, 0xdef8, _, ShortForm, FloatReg, 0, 0},
+{"fdivrp", 2, 0xdef8, _, ShortForm, FloatReg, FloatAcc, 0},
+#ifdef NON_BROKEN_OPCODES
+{"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
+#else
+{"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
+#endif
+{"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0},
+{"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0},
+{"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0},
+{"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0},
+{"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0},
+
+{"f2xm1", 0,   0xd9f0, _, NoModrm, 0, 0, 0},
+{"fyl2x", 0,   0xd9f1, _, NoModrm, 0, 0, 0},
+{"fptan", 0,   0xd9f2, _, NoModrm, 0, 0, 0},
+{"fpatan", 0,  0xd9f3, _, NoModrm, 0, 0, 0},
+{"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0},
+{"fprem1", 0,  0xd9f5, _, NoModrm, 0, 0, 0},
+{"fdecstp", 0,  0xd9f6, _, NoModrm, 0, 0, 0},
+{"fincstp", 0,  0xd9f7, _, NoModrm, 0, 0, 0},
+{"fprem", 0,   0xd9f8, _, NoModrm, 0, 0, 0},
+{"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0},
+{"fsqrt", 0,   0xd9fa, _, NoModrm, 0, 0, 0},
+{"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0},
+{"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0},
+{"fscale", 0,  0xd9fd, _, NoModrm, 0, 0, 0},
+{"fsin", 0,    0xd9fe, _, NoModrm, 0, 0, 0},
+{"fcos", 0,    0xd9ff, _, NoModrm, 0, 0, 0},
+
+{"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0},
+{"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0},
+
+/* processor control */
+{"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
+{"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
+{"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0},
+{"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
+{"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
+{"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
+{"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
+{"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
+{"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
+{"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
+{"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
+{"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
+{"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
+/*
+ We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
+ instructions;  i'm not sure how to add them or how they are different.
+ My 386/387 book offers no details about this.
+*/
+{"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
+{"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
+{"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0},
+{"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
+{"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
+{"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0},
+
+{"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0},
+{"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0},
+{"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0},
+
+/*
+  opcode prefixes; we allow them as seperate insns too
+  (see prefix table below)
+*/
+{"aword", 0, 0x67, _, NoModrm, 0, 0, 0},
+{"addr16", 0, 0x67, _, NoModrm, 0, 0, 0},
+{"word", 0, 0x66, _, NoModrm, 0, 0, 0},
+{"data16", 0, 0x66, _, NoModrm, 0, 0, 0},
+{"lock", 0, 0xf0, _, NoModrm, 0, 0, 0},
+{"cs", 0, 0x2e, _, NoModrm, 0, 0, 0},
+{"ds", 0, 0x3e, _, NoModrm, 0, 0, 0},
+{"es", 0, 0x26, _, NoModrm, 0, 0, 0},
+{"fs", 0, 0x64, _, NoModrm, 0, 0, 0},
+{"gs", 0, 0x65, _, NoModrm, 0, 0, 0},
+{"ss", 0, 0x36, _, NoModrm, 0, 0, 0},
+{"rep", 0, 0xf3, _, NoModrm, 0, 0, 0},
+{"repe", 0, 0xf3, _, NoModrm, 0, 0, 0},
+{ "repne", 0, 0xf2, _, NoModrm, 0, 0, 0},
+{"repz", 0, 0xf3, _, NoModrm, 0, 0, 0},
+{ "repnz", 0, 0xf2, _, NoModrm, 0, 0, 0},
+
+/* 486 extensions */
+{"bswap", 1, 0x0fc8, _, ShortForm, Reg32,0,0 },
+{"xadd", 2, 0x0fc0, _, DW|Modrm, Reg, Reg|Mem, 0 },
+{"cmpxchg", 2, 0x0fb0, _, DW|Modrm, Reg, Reg|Mem, 0 },
+{"invd", 0, 0x0f08, _, NoModrm, 0, 0, 0},
+{"wbinvd", 0, 0x0f09, _, NoModrm, 0, 0, 0},
+{"invlpg", 1, 0x0f01, 7, Modrm, Mem, 0, 0},
+
+/* Pentium extensions */
+{"cpuid", 0, 0x0fa2, _, NoModrm, 0, 0, 0},
+
+{"", 0, 0, 0, 0, 0, 0, 0}	/* sentinal */
+};
+#undef _
+
+static const template *i386_optab_end 
+  = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
+
+/* 386 register table */
+
+static const reg_entry i386_regtab[] = {
+  /* 8 bit regs */
+  {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
+  {"bl", Reg8, 3},
+  {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
+  /* 16 bit regs */
+  {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
+  {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
+  /* 32 bit regs */
+  {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
+  {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
+  /* segment registers */
+  {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
+  {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
+  /* control registers */
+  {"cr0", Control, 0},   {"cr2", Control, 2},   {"cr3", Control, 3},
+  /* debug registers */
+  {"db0", Debug, 0},   {"db1", Debug, 1},   {"db2", Debug, 2},
+  {"db3", Debug, 3},   {"db6", Debug, 6},   {"db7", Debug, 7},
+  {"dr0", Debug, 0},   {"dr1", Debug, 1},   {"dr2", Debug, 2},
+  {"dr3", Debug, 3},   {"dr6", Debug, 6},   {"dr7", Debug, 7},
+  /* test registers */
+  {"tr6", Test, 6}, {"tr7", Test, 7},
+  /* float registers */
+  {"st(0)", FloatReg|FloatAcc, 0},
+  {"st", FloatReg|FloatAcc, 0},
+  {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 
+  {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 
+  {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
+};
+
+#define MAX_REG_NAME_SIZE 8	/* for parsing register names from input */
+
+static const reg_entry *i386_regtab_end
+  = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
+
+/* segment stuff */
+static const seg_entry cs = { "cs", 0x2e };
+static const seg_entry ds = { "ds", 0x3e };
+static const seg_entry ss = { "ss", 0x36 };
+static const seg_entry es = { "es", 0x26 };
+static const seg_entry fs = { "fs", 0x64 };
+static const seg_entry gs = { "gs", 0x65 };
+static const seg_entry null = { "", 0x0 };
+
+/*
+  This table is used to store the default segment register implied by all
+  possible memory addressing modes.
+  It is indexed by the mode & modrm entries of the modrm byte as follows:
+      index = (mode<<3) | modrm;
+*/
+static const seg_entry *one_byte_segment_defaults[] = {
+  /* mode 0 */
+  &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
+  /* mode 1 */
+  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
+  /* mode 2 */
+  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
+  /* mode 3 --- not a memory reference; never referenced */
+};
+
+static const seg_entry *two_byte_segment_defaults[] = {
+  /* mode 0 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 1 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 2 */
+  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  /* mode 3 --- not a memory reference; never referenced */
+};
+
+static const prefix_entry i386_prefixtab[] = {
+  { "addr16", 0x67 },		/* address size prefix ==> 16bit addressing
+				 * (How is this useful?) */
+#define WORD_PREFIX_OPCODE 0x66
+  { "data16", 0x66 },		/* operand size prefix */
+  { "lock", 0xf0 },		/* bus lock prefix */
+  { "wait", 0x9b },		/* wait for coprocessor */
+  { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
+  { "es", 0x26 }, { "fs", 0x64 },
+  { "gs", 0x65 }, { "ss", 0x36 },
+/* REPE & REPNE used to detect rep/repne with a non-string instruction */
+#define REPNE 0xf2
+#define REPE  0xf3
+  { "rep", 0xf3 }, { "repe", 0xf3 }, { "repz", 0xf3 }, /* repeat string instructions */
+  { "repne", 0xf2 }, { "repnz", 0xf2 }
+};
+
+static const prefix_entry *i386_prefixtab_end
+  = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
+
+/* end of i386-opcode.h */
diff --git a/gnu/usr.bin/gas/opcode/i860.h b/gnu/usr.bin/gas/opcode/i860.h
new file mode 100644
index 00000000000..0842786d349
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/i860.h
@@ -0,0 +1,495 @@
+/* Table of opcodes for the i860.
+   Copyright (C) 1989 Free Software Foundation, Inc.
+
+This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+
+GAS/GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GAS/GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS or GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+/*
+ * Structure of an opcode table entry.
+ */
+struct i860_opcode
+{
+    const char *name;
+    unsigned long match;	/* Bits that must be set.  */
+    unsigned long lose;	/* Bits that must not be set.  */
+    const char *args;
+    /* Nonzero if this is a possible expand-instruction.  */
+    char expand;
+};
+
+enum expand_type
+{
+    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
+};
+
+/*
+   All i860 opcodes are 32 bits, except for the pseudoinstructions
+   and the operations utilizing a 32-bit address expression, an
+   unsigned 32-bit constant, or a signed 32-bit constant.
+   These opcodes are expanded into a two-instruction sequence for
+   any situation where the immediate operand does not fit in 32 bits.
+   In the case of the add and subtract operations the expansion is
+   to a three-instruction sequence (ex: orh, or, adds).  In cases
+   where the address is to be relocated, the instruction is
+   expanded to handle the worse case, this could be optimized at
+   the final link if the actual address were known.
+
+   The pseudoinstructions are:  mov, fmov, pmov, nop, and fnop.
+   These instructions are implemented as a one or two instruction
+   sequence of other operations.
+
+   The match component is a mask saying which bits must match a
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing one character
+   for each operand of the instruction.
+
+Kinds of operands:
+   #    Number used by optimizer.  It is ignored.
+   1    src1 integer register.
+   2    src2 integer register.
+   d    dest register.
+   c	ctrlreg control register.
+   i    16 bit immediate.
+   I    16 bit immediate, aligned.
+   5    5 bit immediate.
+   l    lbroff 26 bit PC relative immediate.
+   r    sbroff 16 bit PC relative immediate.
+   s	split 16 bit immediate.
+   S	split 16 bit immediate, aligned.
+   e    src1 floating point register.
+   f    src2 floating point register.
+   g    dest floating point register.
+
+*/
+
+/* The order of the opcodes in this table is significant:
+   
+   * The assembler requires that all instances of the same mnemonic must be
+   consecutive.  If they aren't, the assembler will bomb at runtime.
+
+   * The disassembler should not care about the order of the opcodes.  */
+
+static struct i860_opcode i860_opcodes[] =
+{
+
+/* REG-Format Instructions */
+{ "ld.c",	0x30000000, 0xcc000000, "c,d", 0 },	/* ld.c csrc2,idest */
+{ "ld.b",	0x00000000, 0xfc000000, "1(2),d", 0 },	/* ld.b isrc1(isrc2),idest */
+{ "ld.b",	0x04000000, 0xf8000000, "I(2),d", E_ADDR },	/* ld.b #const(isrc2),idest */
+{ "ld.s",	0x10000000, 0xec000001, "1(2),d", 0 },	/* ld.s isrc1(isrc2),idest */
+{ "ld.s",	0x14000001, 0xe8000000, "I(2),d", E_ADDR },	/* ld.s #const(isrc2),idest */
+{ "ld.l",	0x10000001, 0xec000000, "1(2),d", 0 },	/* ld.l isrc1(isrc2),idest */
+{ "ld.l",	0x14000001, 0xe8000000, "I(2),d", E_ADDR },	/* ld.l #const(isrc2),idest */
+
+{ "st.c",	0x38000000, 0xc4000000, "1,c", 0 },	/* st.c isrc1ni,csrc2 */
+{ "st.b",	0x0c000000, 0xf0000000, "1,S(2)", E_ADDR },	/* st.b isrc1ni,#const(isrc2) */
+{ "st.s",	0x1c000000, 0xe0000000, "1,S(2)", E_ADDR },	/* st.s isrc1ni,#const(isrc2) */
+{ "st.l",	0x1c000001, 0xe0000000, "1,S(2)", E_ADDR },	/* st.l isrc1ni,#const(isrc2) */
+
+{ "ixfr",	0x08000000, 0xf4000000, "1,g", 0 },	/* ixfr isrc1ni,fdest */
+
+{ "fld.l",	0x20000002, 0xdc000001, "1(2),g", 0 },	/* fld.l isrc1(isrc2),fdest */
+{ "fld.l",	0x24000002, 0xd8000001, "i(2),g", E_ADDR },	/* fld.l #const(isrc2),fdest */
+{ "fld.l",	0x20000003, 0xdc000000, "1(2)++,g", 0 },	/* fld.l isrc1(isrc2)++,fdest */
+{ "fld.l",	0x24000003, 0xd8000000, "i(2)++,g", E_ADDR },	/* fld.l #const(isrc2)++,fdest */
+{ "fld.d",	0x20000000, 0xdc000007, "1(2),g", 0 },	/* fld.d isrc1(isrc2),fdest */
+{ "fld.d",	0x24000000, 0xd8000007, "i(2),g", E_ADDR },	/* fld.d #const(isrc2),fdest */
+{ "fld.d",	0x20000001, 0xdc000006, "1(2)++,g", 0 },	/* fld.d isrc1(isrc2)++,fdest */
+{ "fld.d",	0x24000001, 0xd8000006, "i(2)++,g", E_ADDR },	/* fld.d #const(isrc2)++,fdest */
+{ "fld.q",	0x20000004, 0xdc000003, "1(2),g", 0 },	/* fld.q isrc1(isrc2),fdest */
+{ "fld.q",	0x24000004, 0xd8000003, "i(2),g", E_ADDR },	/* fld.q #const(isrc2),fdest */
+{ "fld.q",	0x20000005, 0xdc000002, "1(2)++,g", 0 },	/* fld.q isrc1(isrc2)++,fdest */
+{ "fld.q",	0x24000005, 0xd8000002, "i(2)++,g", E_ADDR },	/* fld.q #const(isrc2)++,fdest */
+
+{ "pfld.l",	0x60000000, 0x9c000003, "1(2),g", 0 },	/* pfld.l isrc1(isrc2),fdest */
+{ "pfld.l",	0x64000000, 0x98000003, "i(2),g", E_ADDR },	/* pfld.l #const(isrc2),fdest */
+{ "pfld.l",	0x60000001, 0x9c000002, "1(2)++,g", 0 },	/* pfld.l isrc1(isrc2)++,fdest */
+{ "pfld.l",	0x64000001, 0x98000002, "i(2)++,g", E_ADDR },	/* pfld.l #const(isrc2)++,fdest */
+{ "pfld.d",	0x60000000, 0x9c000007, "1(2),g", 0 },	/* pfld.d isrc1(isrc2),fdest */
+{ "pfld.d",	0x64000000, 0x98000007, "i(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
+{ "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
+{ "pfld.d",	0x64000001, 0x98000006, "i(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
+
+{ "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
+{ "fst.l",	0x2c000002, 0xd0000001, "g,i(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
+{ "fst.l",	0x28000003, 0xd4000000, "g,1(2)++", 0 },	/* fst.l fdest,isrc1(isrc2)++ */
+{ "fst.l",	0x2c000003, 0xd0000000, "g,i(2)++", E_ADDR },	/* fst.l fdest,#const(isrc2)++ */
+{ "fst.d",	0x28000000, 0xd4000007, "g,1(2)", 0 },	/* fst.d fdest,isrc1(isrc2) */
+{ "fst.d",	0x2c000000, 0xd0000007, "g,i(2)", E_ADDR },	/* fst.d fdest,#const(isrc2) */
+{ "fst.d",	0x28000001, 0xd4000006, "g,1(2)++", 0 },	/* fst.d fdest,isrc1(isrc2)++ */
+{ "fst.d",	0x2c000001, 0xd0000006, "g,i(2)++", E_ADDR },	/* fst.d fdest,#const(isrc2)++ */
+{ "fst.q",	0x28000004, 0xd4000003, "g,1(2)", 0 },	/* fst.q fdest,isrc1(isrc2) */
+{ "fst.q",	0x2c000004, 0xd0000003, "g,i(2)", E_ADDR },	/* fst.q fdest,#const(isrc2) */
+{ "fst.q",	0x28000005, 0xd4000002, "g,1(2)++", 0 },	/* fst.q fdest,isrc1(isrc2)++ */
+{ "fst.q",	0x2c000005, 0xd0000002, "g,i(2)++", E_ADDR },	/* fst.q fdest,#const(isrc2)++ */
+
+{ "pst.d",	0x3c000000, 0xc0000007, "g,i(2)", E_ADDR },	/* pst.d fdest,#const(isrc2) */
+{ "pst.d",	0x3c000001, 0xc0000006, "g,i(2)++", E_ADDR },	/* pst.d fdest,#const(isrc2)++ */
+
+{ "addu",	0x80000000, 0x7c000000, "1,2,d", 0 },	/* addu isrc1,isrc2,idest */
+{ "addu",	0x84000000, 0x78000000, "i,2,d", E_S32 },	/* addu #const,isrc2,idest */
+{ "adds",	0x90000000, 0x6c000000, "1,2,d", 0 },	/* adds isrc1,isrc2,idest */
+{ "adds",	0x94000000, 0x68000000, "i,2,d", E_S32 },	/* adds #const,isrc2,idest */
+{ "subu",	0x88000000, 0x74000000, "1,2,d", 0 },	/* subu isrc1,isrc2,idest */
+{ "subu",	0x8c000000, 0x70000000, "i,2,d", E_S32 },	/* subu #const,isrc2,idest */
+{ "subs",	0x98000000, 0x64000000, "1,2,d", 0 },	/* subs isrc1,isrc2,idest */
+{ "subs",	0x9c000000, 0x60000000, "i,2,d", E_S32 },	/* subs #const,isrc2,idest */
+
+{ "shl",	0xa0000000, 0x5c000000, "1,2,d", 0 },	/* shl isrc1,isrc2,idest */
+{ "shl",	0xa4000000, 0x58000000, "i,2,d", 0 },	/* shl #const,isrc2,idest */
+{ "shr",	0xa8000000, 0x54000000, "1,2,d", 0 },	/* shr isrc1,isrc2,idest */
+{ "shr",	0xac000000, 0x50000000, "i,2,d", 0 },	/* shr #const,isrc2,idest */
+{ "shrd",	0xb0000000, 0x4c000000, "1,2,d", 0 },	/* shrd isrc1,isrc2,idest */
+{ "shra",	0xb8000000, 0x44000000, "1,2,d", 0 },	/* shra isrc1,isrc2,idest */
+{ "shra",	0xbc000000, 0x40000000, "i,2,d", 0 },	/* shra #const,isrc2,idest */
+
+{ "mov",	0xa0000000, 0x5c00f800, "2,d", 0 },	/* shl r0,isrc2,idest */
+{ "mov",	0x94000000, 0x69e00000, "i,d", E_MOV },	/* adds #const,r0,idest */
+{ "nop",	0xa0000000, 0x5ffff800, "", 0 },	/* shl r0,r0,r0 */
+{ "fnop",	0xb0000000, 0x4ffff800, "", 0 },	/* shrd r0,r0,r0 */
+
+{ "trap",	0x44000000, 0xb8000000, "1,2,d", 0 },	/* trap isrc1ni,isrc2,idest */
+
+{ "flush",	0x34000000, 0xc81f0001, "i(2)", E_ADDR },	/* flush #const(isrc2) */
+{ "flush",	0x34000001, 0xc81f0000, "i(2)++", E_ADDR },	/* flush #const(isrc2)++ */
+
+{ "and",	0xc0000000, 0x3c000000, "1,2,d", 0 },	/* and isrc1,isrc2,idest */
+{ "and",	0xc4000000, 0x38000000, "i,2,d", E_AND },	/* and #const,isrc2,idest */
+{ "andh",	0xc8000000, 0x34000000, "1,2,d", 0 },	/* andh isrc1,isrc2,idest */
+{ "andh",	0xcc000000, 0x30000000, "i,2,d", 0 },	/* andh #const,isrc2,idest */
+{ "andnot",	0xd0000000, 0x2c000000, "1,2,d", 0 },	/* andnot isrc1,isrc2,idest */
+{ "andnot",	0xd4000000, 0x28000000, "i,2,d", E_U32 },	/* andnot #const,isrc2,idest */
+{ "andnoth",	0xd8000000, 0x24000000, "1,2,d", 0 },	/* andnoth isrc1,isrc2,idest */
+{ "andnoth",	0xdc000000, 0x20000000, "i,2,d", 0 },	/* andnoth #const,isrc2,idest */
+{ "or",		0xe0000000, 0x1c000000, "1,2,d", 0 },	/* or isrc1,isrc2,idest */
+{ "or",		0xe4000000, 0x18000000, "i,2,d", E_U32 },	/* or #const,isrc2,idest */
+{ "orh",	0xe8000000, 0x14000000, "1,2,d", 0 },	/* orh isrc1,isrc2,idest */
+{ "orh",	0xec000000, 0x10000000, "i,2,d", 0 },	/* orh #const,isrc2,idest */
+{ "xor",	0xf0000000, 0x0c000000, "1,2,d", 0 },	/* xor isrc1,isrc2,idest */
+{ "xor",	0xf4000000, 0x08000000, "i,2,d", E_U32 },	/* xor #const,isrc2,idest */
+{ "xorh",	0xf8000000, 0x04000000, "1,2,d", 0 },	/* xorh isrc1,isrc2,idest */
+{ "xorh",	0xfc000000, 0x00000000, "i,2,d", 0 },	/* xorh #const,isrc2,idest */
+
+{ "bte",	0x58000000, 0xa4000000, "1,2,s", 0 },	/* bte isrc1s,isrc2,sbroff */
+{ "bte",	0x5c000000, 0xa0000000, "5,2,s", 0 },	/* bte #const5,isrc2,sbroff */
+{ "btne",	0x50000000, 0xac000000, "1,2,s", 0 },	/* btne isrc1s,isrc2,sbroff */
+{ "btne",	0x54000000, 0xa8000000, "5,2,s", 0 },	/* btne #const5,isrc2,sbroff */
+{ "bla",	0xb4000000, 0x48000000, "1,2,s", E_DELAY },	/* bla isrc1s,isrc2,sbroff */
+{ "bri",	0x40000000, 0xbc000000, "1", E_DELAY },	/* bri isrc1ni */
+
+/* Core Escape Instruction Format */
+{ "lock",	0x4c000001, 0xb000001e, "", 0 },	/* lock set BL in dirbase */
+{ "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
+{ "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
+{ "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
+
+/* CTRL-Format Instructions */
+{ "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
+{ "call",	0x6c000000, 0x90000000, "l", E_DELAY },	/* call lbroff */
+{ "bc",		0x70000000, 0x8c000000, "l", 0 },	/* bc lbroff */
+{ "bc.t",	0x74000000, 0x88000000, "l", E_DELAY },	/* bc.t lbroff */
+{ "bnc",	0x78000000, 0x84000000, "l", 0 },	/* bnc lbroff */
+{ "bnc.t",	0x7c000000, 0x80000000, "l", E_DELAY },	/* bnc.t lbroff */
+
+/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */
+{ "r2p1.ss",	0x48000400, 0xb40003ff, "e,f,g", 0 },
+{ "r2p1.sd",	0x48000480, 0xb400037f, "e,f,g", 0 },
+{ "r2p1.dd",	0x48000580, 0xb400027f, "e,f,g", 0 },
+{ "r2pt.ss",	0x48000401, 0xb40003fe, "e,f,g", 0 },
+{ "r2pt.sd",	0x48000481, 0xb400037e, "e,f,g", 0 },
+{ "r2pt.dd",	0x48000581, 0xb400027e, "e,f,g", 0 },
+{ "r2ap1.ss",	0x48000402, 0xb40003fd, "e,f,g", 0 },
+{ "r2ap1.sd",	0x48000482, 0xb400037d, "e,f,g", 0 },
+{ "r2ap1.dd",	0x48000582, 0xb400027d, "e,f,g", 0 },
+{ "r2apt.ss",	0x48000403, 0xb40003fc, "e,f,g", 0 },
+{ "r2apt.sd",	0x48000483, 0xb400037c, "e,f,g", 0 },
+{ "r2apt.dd",	0x48000583, 0xb400027c, "e,f,g", 0 },
+{ "i2p1.ss",	0x48000404, 0xb40003fb, "e,f,g", 0 },
+{ "i2p1.sd",	0x48000484, 0xb400037b, "e,f,g", 0 },
+{ "i2p1.dd",	0x48000584, 0xb400027b, "e,f,g", 0 },
+{ "i2pt.ss",	0x48000405, 0xb40003fa, "e,f,g", 0 },
+{ "i2pt.sd",	0x48000485, 0xb400037a, "e,f,g", 0 },
+{ "i2pt.dd",	0x48000585, 0xb400027a, "e,f,g", 0 },
+{ "i2ap1.ss",	0x48000406, 0xb40003f9, "e,f,g", 0 },
+{ "i2ap1.sd",	0x48000486, 0xb4000379, "e,f,g", 0 },
+{ "i2ap1.dd",	0x48000586, 0xb4000279, "e,f,g", 0 },
+{ "i2apt.ss",	0x48000407, 0xb40003f8, "e,f,g", 0 },
+{ "i2apt.sd",	0x48000487, 0xb4000378, "e,f,g", 0 },
+{ "i2apt.dd",	0x48000587, 0xb4000278, "e,f,g", 0 },
+{ "rat1p2.ss",	0x48000408, 0xb40003f7, "e,f,g", 0 },
+{ "rat1p2.sd",	0x48000488, 0xb4000377, "e,f,g", 0 },
+{ "rat1p2.dd",	0x48000588, 0xb4000277, "e,f,g", 0 },
+{ "m12apm.ss",	0x48000409, 0xb40003f6, "e,f,g", 0 },
+{ "m12apm.sd",	0x48000489, 0xb4000376, "e,f,g", 0 },
+{ "m12apm.dd",	0x48000589, 0xb4000276, "e,f,g", 0 },
+{ "ra1p2.ss",	0x4800040a, 0xb40003f5, "e,f,g", 0 },
+{ "ra1p2.sd",	0x4800048a, 0xb4000375, "e,f,g", 0 },
+{ "ra1p2.dd",	0x4800058a, 0xb4000275, "e,f,g", 0 },
+{ "m12ttpa.ss",	0x4800040b, 0xb40003f4, "e,f,g", 0 },
+{ "m12ttpa.sd",	0x4800048b, 0xb4000374, "e,f,g", 0 },
+{ "m12ttpa.dd",	0x4800058b, 0xb4000274, "e,f,g", 0 },
+{ "iat1p2.ss",	0x4800040c, 0xb40003f3, "e,f,g", 0 },
+{ "iat1p2.sd",	0x4800048c, 0xb4000373, "e,f,g", 0 },
+{ "iat1p2.dd",	0x4800058c, 0xb4000273, "e,f,g", 0 },
+{ "m12tpm.ss",	0x4800040d, 0xb40003f2, "e,f,g", 0 },
+{ "m12tpm.sd",	0x4800048d, 0xb4000372, "e,f,g", 0 },
+{ "m12tpm.dd",	0x4800058d, 0xb4000272, "e,f,g", 0 },
+{ "ia1p2.ss",	0x4800040e, 0xb40003f1, "e,f,g", 0 },
+{ "ia1p2.sd",	0x4800048e, 0xb4000371, "e,f,g", 0 },
+{ "ia1p2.dd",	0x4800058e, 0xb4000271, "e,f,g", 0 },
+{ "m12tpa.ss",	0x4800040f, 0xb40003f0, "e,f,g", 0 },
+{ "m12tpa.sd",	0x4800048f, 0xb4000370, "e,f,g", 0 },
+{ "m12tpa.dd",	0x4800058f, 0xb4000270, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */
+{ "r2s1.ss",	0x48000410, 0xb40003ef, "e,f,g", 0 },
+{ "r2s1.sd",	0x48000490, 0xb400036f, "e,f,g", 0 },
+{ "r2s1.dd",	0x48000590, 0xb400026f, "e,f,g", 0 },
+{ "r2st.ss",	0x48000411, 0xb40003ee, "e,f,g", 0 },
+{ "r2st.sd",	0x48000491, 0xb400036e, "e,f,g", 0 },
+{ "r2st.dd",	0x48000591, 0xb400026e, "e,f,g", 0 },
+{ "r2as1.ss",	0x48000412, 0xb40003ed, "e,f,g", 0 },
+{ "r2as1.sd",	0x48000492, 0xb400036d, "e,f,g", 0 },
+{ "r2as1.dd",	0x48000592, 0xb400026d, "e,f,g", 0 },
+{ "r2ast.ss",	0x48000413, 0xb40003ec, "e,f,g", 0 },
+{ "r2ast.sd",	0x48000493, 0xb400036c, "e,f,g", 0 },
+{ "r2ast.dd",	0x48000593, 0xb400026c, "e,f,g", 0 },
+{ "i2s1.ss",	0x48000414, 0xb40003eb, "e,f,g", 0 },
+{ "i2s1.sd",	0x48000494, 0xb400036b, "e,f,g", 0 },
+{ "i2s1.dd",	0x48000594, 0xb400026b, "e,f,g", 0 },
+{ "i2st.ss",	0x48000415, 0xb40003ea, "e,f,g", 0 },
+{ "i2st.sd",	0x48000495, 0xb400036a, "e,f,g", 0 },
+{ "i2st.dd",	0x48000595, 0xb400026a, "e,f,g", 0 },
+{ "i2as1.ss",	0x48000416, 0xb40003e9, "e,f,g", 0 },
+{ "i2as1.sd",	0x48000496, 0xb4000369, "e,f,g", 0 },
+{ "i2as1.dd",	0x48000596, 0xb4000269, "e,f,g", 0 },
+{ "i2ast.ss",	0x48000417, 0xb40003e8, "e,f,g", 0 },
+{ "i2ast.sd",	0x48000497, 0xb4000368, "e,f,g", 0 },
+{ "i2ast.dd",	0x48000597, 0xb4000268, "e,f,g", 0 },
+{ "rat1s2.ss",	0x48000418, 0xb40003e7, "e,f,g", 0 },
+{ "rat1s2.sd",	0x48000498, 0xb4000367, "e,f,g", 0 },
+{ "rat1s2.dd",	0x48000598, 0xb4000267, "e,f,g", 0 },
+{ "m12asm.ss",	0x48000419, 0xb40003e6, "e,f,g", 0 },
+{ "m12asm.sd",	0x48000499, 0xb4000366, "e,f,g", 0 },
+{ "m12asm.dd",	0x48000599, 0xb4000266, "e,f,g", 0 },
+{ "ra1s2.ss",	0x4800041a, 0xb40003e5, "e,f,g", 0 },
+{ "ra1s2.sd",	0x4800049a, 0xb4000365, "e,f,g", 0 },
+{ "ra1s2.dd",	0x4800059a, 0xb4000265, "e,f,g", 0 },
+{ "m12ttsa.ss",	0x4800041b, 0xb40003e4, "e,f,g", 0 },
+{ "m12ttsa.sd",	0x4800049b, 0xb4000364, "e,f,g", 0 },
+{ "m12ttsa.dd",	0x4800059b, 0xb4000264, "e,f,g", 0 },
+{ "iat1s2.ss",	0x4800041c, 0xb40003e3, "e,f,g", 0 },
+{ "iat1s2.sd",	0x4800049c, 0xb4000363, "e,f,g", 0 },
+{ "iat1s2.dd",	0x4800059c, 0xb4000263, "e,f,g", 0 },
+{ "m12tsm.ss",	0x4800041d, 0xb40003e2, "e,f,g", 0 },
+{ "m12tsm.sd",	0x4800049d, 0xb4000362, "e,f,g", 0 },
+{ "m12tsm.dd",	0x4800059d, 0xb4000262, "e,f,g", 0 },
+{ "ia1s2.ss",	0x4800041e, 0xb40003e1, "e,f,g", 0 },
+{ "ia1s2.sd",	0x4800049e, 0xb4000361, "e,f,g", 0 },
+{ "ia1s2.dd",	0x4800059e, 0xb4000261, "e,f,g", 0 },
+{ "m12tsa.ss",	0x4800041f, 0xb40003e0, "e,f,g", 0 },
+{ "m12tsa.sd",	0x4800049f, 0xb4000360, "e,f,g", 0 },
+{ "m12tsa.dd",	0x4800059f, 0xb4000260, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */
+{ "mr2p1.ss",	0x48000000, 0xb40007ff, "e,f,g", 0 },
+{ "mr2p1.sd",	0x48000080, 0xb400077f, "e,f,g", 0 },
+{ "mr2p1.dd",	0x48000180, 0xb400067f, "e,f,g", 0 },
+{ "mr2pt.ss",	0x48000001, 0xb40007fe, "e,f,g", 0 },
+{ "mr2pt.sd",	0x48000081, 0xb400077e, "e,f,g", 0 },
+{ "mr2pt.dd",	0x48000181, 0xb400067e, "e,f,g", 0 },
+{ "mr2mp1.ss",	0x48000002, 0xb40007fd, "e,f,g", 0 },
+{ "mr2mp1.sd",	0x48000082, 0xb400077d, "e,f,g", 0 },
+{ "mr2mp1.dd",	0x48000182, 0xb400067d, "e,f,g", 0 },
+{ "mr2mpt.ss",	0x48000003, 0xb40007fc, "e,f,g", 0 },
+{ "mr2mpt.sd",	0x48000083, 0xb400077c, "e,f,g", 0 },
+{ "mr2mpt.dd",	0x48000183, 0xb400067c, "e,f,g", 0 },
+{ "mi2p1.ss",	0x48000004, 0xb40007fb, "e,f,g", 0 },
+{ "mi2p1.sd",	0x48000084, 0xb400077b, "e,f,g", 0 },
+{ "mi2p1.dd",	0x48000184, 0xb400067b, "e,f,g", 0 },
+{ "mi2pt.ss",	0x48000005, 0xb40007fa, "e,f,g", 0 },
+{ "mi2pt.sd",	0x48000085, 0xb400077a, "e,f,g", 0 },
+{ "mi2pt.dd",	0x48000185, 0xb400067a, "e,f,g", 0 },
+{ "mi2mp1.ss",	0x48000006, 0xb40007f9, "e,f,g", 0 },
+{ "mi2mp1.sd",	0x48000086, 0xb4000779, "e,f,g", 0 },
+{ "mi2mp1.dd",	0x48000186, 0xb4000679, "e,f,g", 0 },
+{ "mi2mpt.ss",	0x48000007, 0xb40007f8, "e,f,g", 0 },
+{ "mi2mpt.sd",	0x48000087, 0xb4000778, "e,f,g", 0 },
+{ "mi2mpt.dd",	0x48000187, 0xb4000678, "e,f,g", 0 },
+{ "mrmt1p2.ss",	0x48000008, 0xb40007f7, "e,f,g", 0 },
+{ "mrmt1p2.sd",	0x48000088, 0xb4000777, "e,f,g", 0 },
+{ "mrmt1p2.dd",	0x48000188, 0xb4000677, "e,f,g", 0 },
+{ "mm12mpm.ss",	0x48000009, 0xb40007f6, "e,f,g", 0 },
+{ "mm12mpm.sd",	0x48000089, 0xb4000776, "e,f,g", 0 },
+{ "mm12mpm.dd",	0x48000189, 0xb4000676, "e,f,g", 0 },
+{ "mrm1p2.ss",	0x4800000a, 0xb40007f5, "e,f,g", 0 },
+{ "mrm1p2.sd",	0x4800008a, 0xb4000775, "e,f,g", 0 },
+{ "mrm1p2.dd",	0x4800018a, 0xb4000675, "e,f,g", 0 },
+{ "mm12ttpm.ss",0x4800000b, 0xb40007f4, "e,f,g", 0 },
+{ "mm12ttpm.sd",0x4800008b, 0xb4000774, "e,f,g", 0 },
+{ "mm12ttpm.dd",0x4800018b, 0xb4000674, "e,f,g", 0 },
+{ "mimt1p2.ss",	0x4800000c, 0xb40007f3, "e,f,g", 0 },
+{ "mimt1p2.sd",	0x4800008c, 0xb4000773, "e,f,g", 0 },
+{ "mimt1p2.dd",	0x4800018c, 0xb4000673, "e,f,g", 0 },
+{ "mm12tpm.ss",	0x4800000d, 0xb40007f2, "e,f,g", 0 },
+{ "mm12tpm.sd",	0x4800008d, 0xb4000772, "e,f,g", 0 },
+{ "mm12tpm.dd",	0x4800018d, 0xb4000672, "e,f,g", 0 },
+{ "mim1p2.ss",	0x4800000e, 0xb40007f1, "e,f,g", 0 },
+{ "mim1p2.sd",	0x4800008e, 0xb4000771, "e,f,g", 0 },
+{ "mim1p2.dd",	0x4800018e, 0xb4000671, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */
+{ "mr2s1.ss",	0x48000010, 0xb40007ef, "e,f,g", 0 },
+{ "mr2s1.sd",	0x48000090, 0xb400076f, "e,f,g", 0 },
+{ "mr2s1.dd",	0x48000190, 0xb400066f, "e,f,g", 0 },
+{ "mr2st.ss",	0x48000011, 0xb40007ee, "e,f,g", 0 },
+{ "mr2st.sd",	0x48000091, 0xb400076e, "e,f,g", 0 },
+{ "mr2st.dd",	0x48000191, 0xb400066e, "e,f,g", 0 },
+{ "mr2ms1.ss",	0x48000012, 0xb40007ed, "e,f,g", 0 },
+{ "mr2ms1.sd",	0x48000092, 0xb400076d, "e,f,g", 0 },
+{ "mr2ms1.dd",	0x48000192, 0xb400066d, "e,f,g", 0 },
+{ "mr2mst.ss",	0x48000013, 0xb40007ec, "e,f,g", 0 },
+{ "mr2mst.sd",	0x48000093, 0xb400076c, "e,f,g", 0 },
+{ "mr2mst.dd",	0x48000193, 0xb400066c, "e,f,g", 0 },
+{ "mi2s1.ss",	0x48000014, 0xb40007eb, "e,f,g", 0 },
+{ "mi2s1.sd",	0x48000094, 0xb400076b, "e,f,g", 0 },
+{ "mi2s1.dd",	0x48000194, 0xb400066b, "e,f,g", 0 },
+{ "mi2st.ss",	0x48000015, 0xb40007ea, "e,f,g", 0 },
+{ "mi2st.sd",	0x48000095, 0xb400076a, "e,f,g", 0 },
+{ "mi2st.dd",	0x48000195, 0xb400066a, "e,f,g", 0 },
+{ "mi2ms1.ss",	0x48000016, 0xb40007e9, "e,f,g", 0 },
+{ "mi2ms1.sd",	0x48000096, 0xb4000769, "e,f,g", 0 },
+{ "mi2ms1.dd",	0x48000196, 0xb4000669, "e,f,g", 0 },
+{ "mi2mst.ss",	0x48000017, 0xb40007e8, "e,f,g", 0 },
+{ "mi2mst.sd",	0x48000097, 0xb4000768, "e,f,g", 0 },
+{ "mi2mst.dd",	0x48000197, 0xb4000668, "e,f,g", 0 },
+{ "mrmt1s2.ss",	0x48000018, 0xb40007e7, "e,f,g", 0 },
+{ "mrmt1s2.sd",	0x48000098, 0xb4000767, "e,f,g", 0 },
+{ "mrmt1s2.dd",	0x48000198, 0xb4000667, "e,f,g", 0 },
+{ "mm12msm.ss",	0x48000019, 0xb40007e6, "e,f,g", 0 },
+{ "mm12msm.sd",	0x48000099, 0xb4000766, "e,f,g", 0 },
+{ "mm12msm.dd",	0x48000199, 0xb4000666, "e,f,g", 0 },
+{ "mrm1s2.ss",	0x4800001a, 0xb40007e5, "e,f,g", 0 },
+{ "mrm1s2.sd",	0x4800009a, 0xb4000765, "e,f,g", 0 },
+{ "mrm1s2.dd",	0x4800019a, 0xb4000665, "e,f,g", 0 },
+{ "mm12ttsm.ss",0x4800001b, 0xb40007e4, "e,f,g", 0 },
+{ "mm12ttsm.sd",0x4800009b, 0xb4000764, "e,f,g", 0 },
+{ "mm12ttsm.dd",0x4800019b, 0xb4000664, "e,f,g", 0 },
+{ "mimt1s2.ss",	0x4800001c, 0xb40007e3, "e,f,g", 0 },
+{ "mimt1s2.sd",	0x4800009c, 0xb4000763, "e,f,g", 0 },
+{ "mimt1s2.dd",	0x4800019c, 0xb4000663, "e,f,g", 0 },
+{ "mm12tsm.ss",	0x4800001d, 0xb40007e2, "e,f,g", 0 },
+{ "mm12tsm.sd",	0x4800009d, 0xb4000762, "e,f,g", 0 },
+{ "mm12tsm.dd",	0x4800019d, 0xb4000662, "e,f,g", 0 },
+{ "mim1s2.ss",	0x4800001e, 0xb40007e1, "e,f,g", 0 },
+{ "mim1s2.sd",	0x4800009e, 0xb4000761, "e,f,g", 0 },
+{ "mim1s2.dd",	0x4800019e, 0xb4000661, "e,f,g", 0 },
+
+
+{ "fmul.ss",	0x48000020, 0xb40007df, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "fmul.sd",	0x480000a0, 0xb400075f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "fmul.dd",	0x480001a0, 0xb400065f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.ss",	0x48000420, 0xb40003df, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.sd",	0x480004a0, 0xb400035f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.dd",	0x480005a0, 0xb400025f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul3.dd",	0x480005a4, 0xb400025b, "e,f,g", 0 },	/* pfmul3.p fsrc1,fsrc2,fdest */
+{ "fmlow.dd",	0x480001a1, 0xb400065e, "e,f,g", 0 },	/* fmlow.dd fsrc1,fsrc2,fdest */
+{ "frcp.ss",	0x48000022, 0xb40007dd, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frcp.sd",	0x480000a2, 0xb400075d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frcp.dd",	0x480001a2, 0xb400065d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frsqr.ss",	0x48000023, 0xb40007dc, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "frsqr.sd",	0x480000a3, 0xb400075c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "frsqr.dd",	0x480001a3, 0xb400065c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "fadd.ss",	0x48000030, 0xb40007cf, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "fadd.sd",	0x480000b0, 0xb400074f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "fadd.dd",	0x480001b0, 0xb400064f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.ss",	0x48000430, 0xb40003cf, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.sd",	0x480004b0, 0xb400034f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.dd",	0x480005b0, 0xb400024f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "fsub.ss",	0x48000031, 0xb40007ce, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "fsub.sd",	0x480000b1, 0xb400074e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "fsub.dd",	0x480001b1, 0xb400064e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.ss",	0x48000431, 0xb40003ce, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.sd",	0x480004b1, 0xb400034e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.dd",	0x480005b1, 0xb400024e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "fix.ss",	0x48000032, 0xb40007cd, "e,g", 0 },	/* fix.p fsrc1,fdest */
+{ "fix.sd",	0x480000b2, 0xb400074d, "e,g", 0 },	/* fix.p fsrc1,fdest */
+{ "fix.dd",	0x480001b2, 0xb400064d, "e,g", 0 },	/* fix.p fsrc1,fdest */
+{ "pfix.ss",	0x48000432, 0xb40003cd, "e,g", 0 },	/* pfix.p fsrc1,fdest */
+{ "pfix.sd",	0x480004b2, 0xb400034d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
+{ "pfix.dd",	0x480005b2, 0xb400024d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
+{ "famov.ss",	0x48000033, 0xb40007cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.ds",	0x48000133, 0xb40006cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.sd",	0x480000b3, 0xb400074c, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.dd",	0x480001b3, 0xb400064c, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "pfamov.ss",	0x48000433, 0xb40003cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.ds",	0x48000533, 0xb40002cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.sd",	0x480004b3, 0xb400034c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.dd",	0x480005b3, 0xb400024c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+/* pfgt has R bit cleared; pfle has R bit set */
+{ "pfgt.ss",	0x48000434, 0xb40003cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
+{ "pfgt.sd",	0x48000434, 0xb40003cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
+{ "pfgt.dd",	0x48000534, 0xb40002cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
+/* pfgt has R bit cleared; pfle has R bit set */
+{ "pfle.ss",	0x480004b4, 0xb400034b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
+{ "pfle.sd",	0x480004b4, 0xb400034b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
+{ "pfle.dd",	0x480005b4, 0xb400024b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
+{ "ftrunc.ss",	0x4800003a, 0xb40007c5, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
+{ "ftrunc.sd",	0x480000ba, 0xb4000745, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
+{ "ftrunc.dd",	0x480001ba, 0xb4000645, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
+{ "pftrunc.ss",	0x4800043a, 0xb40003c5, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
+{ "pftrunc.sd",	0x480004ba, 0xb4000345, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
+{ "pftrunc.dd",	0x480005ba, 0xb4000245, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
+{ "fxfr",	0x48000040, 0xb40007bf, "e,d", 0 },	/* fxfr fsrc1,idest */
+{ "fiadd.ss",	0x48000049, 0xb40007b6, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
+{ "fiadd.dd",	0x480001c9, 0xb4000636, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
+{ "pfiadd.ss",	0x48000449, 0xb40003b6, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
+{ "pfiadd.dd",	0x480005c9, 0xb4000236, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
+{ "fisub.ss",	0x4800004d, 0xb40007b2, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
+{ "fisub.dd",	0x480001cd, 0xb4000632, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
+{ "pfisub.ss",	0x4800044d, 0xb40003b2, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
+{ "pfisub.dd",	0x480005cd, 0xb4000232, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
+{ "fzchkl",	0x48000057, 0xb40007a8, "e,f,g", 0 },	/* fzchkl fsrc1,fsrc2,fdest */
+{ "pfzchkl",	0x48000457, 0xb40003a8, "e,f,g", 0 },	/* pfzchkl fsrc1,fsrc2,fdest */
+{ "fzchks",	0x4800005f, 0xb40007a0, "e,f,g", 0 },	/* fzchks fsrc1,fsrc2,fdest */
+{ "pfzchks",	0x4800045f, 0xb40003a0, "e,f,g", 0 },	/* pfzchks fsrc1,fsrc2,fdest */
+{ "faddp",	0x48000050, 0xb40007af, "e,f,g", 0 },	/* faddp fsrc1,fsrc2,fdest */
+{ "pfaddp",	0x48000450, 0xb40003af, "e,f,g", 0 },	/* pfaddp fsrc1,fsrc2,fdest */
+{ "faddz",	0x48000051, 0xb40007ae, "e,f,g", 0 },	/* faddz fsrc1,fsrc2,fdest */
+{ "pfaddz",	0x48000451, 0xb40003ae, "e,f,g", 0 },	/* pfaddz fsrc1,fsrc2,fdest */
+{ "form",	0x4800005a, 0xb40007a5, "e,g", 0 },	/* form fsrc1,fdest */
+{ "pform",	0x4800045a, 0xb40003a5, "e,g", 0 },	/* pform fsrc1,fdest */
+
+/* Floating point pseudo-instructions */
+{ "fmov.ss",	0x48000049, 0xb7e007b6, "e,g", 0 },	/* fiadd.ss fsrc1,f0,fdest */
+{ "fmov.dd",	0x480001c9, 0xb7e00636, "e,g", 0 },	/* fiadd.dd fsrc1,f0,fdest */
+{ "fmov.sd",	0x480000b0, 0xb7e0074f, "e,g", 0 },	/* fadd.sd fsrc1,f0,fdest */
+{ "fmov.ds",	0x48000130, 0xb7e006cf, "e,g", 0 },	/* fadd.ds fsrc1,f0,fdest */
+{ "pfmov.ds",	0x48000530, 0xb73002cf, "e,g", 0 },	/* pfadd.ds fsrc1,f0,fdest */
+{ "pfmov.dd",	0x480005c9, 0xb7e00236, "e,g", 0 },	/* pfiadd.dd fsrc1,f0,fdest */
+
+
+};
+
+#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))
+
+
diff --git a/gnu/usr.bin/gas/opcode/i960.h b/gnu/usr.bin/gas/opcode/i960.h
new file mode 100644
index 00000000000..3be57356c7a
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/i960.h
@@ -0,0 +1,434 @@
+/* Basic 80960 instruction formats.
+ *
+ * The 'COJ' instructions are actually COBR instructions with the 'b' in
+ * the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if necessary:
+ * if the displacement will not fit in 13 bits, the assembler will replace them
+ * with the corresponding compare and branch instructions.
+ *
+ * All of the 'MEMn' instructions are the same format; the 'n' in the name
+ * indicates the default index scale factor (the size of the datum operated on).
+ *
+ * The FBRA formats are not actually an instruction format.  They are the
+ * "convenience directives" for branching on floating-point comparisons,
+ * each of which generates 2 instructions (a 'bno' and one other branch).
+ *
+ * The CALLJ format is not actually an instruction format.  It indicates that
+ * the instruction generated (a CTRL-format 'call') should have its relocation
+ * specially flagged for link-time replacement with a 'bal' or 'calls' if
+ * appropriate.
+ */ 
+
+/* $Id: i960.h,v 1.1 1995/10/18 08:39:09 deraadt Exp $ */
+
+#define CTRL	0
+#define COBR	1
+#define COJ	2
+#define REG	3
+#define MEM1	4
+#define MEM2	5
+#define MEM4	6
+#define MEM8	7
+#define MEM12	8
+#define MEM16	9
+#define FBRA	10
+#define CALLJ	11
+
+/* Masks for the mode bits in REG format instructions */
+#define M1		0x0800
+#define M2		0x1000
+#define M3		0x2000
+
+/* Generate the 12-bit opcode for a REG format instruction by placing the 
+ * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
+ * 7-10.
+ */
+
+#define REG_OPC(opc)	((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
+
+/* Generate a template for a REG format instruction:  place the opcode bits
+ * in the appropriate fields and OR in mode bits for the operands that will not
+ * be used.  I.e.,
+ *		set m1=1, if src1 will not be used
+ *		set m2=1, if src2 will not be used
+ *		set m3=1, if dst  will not be used
+ *
+ * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
+ * The information is also useful to us because some 1-operand REG instructions
+ * use the src1 field, others the dst field; and some 2-operand REG instructions
+ * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
+ */
+#define R_0(opc)	( REG_OPC(opc) | M1 | M2 | M3 )	/* No operands      */
+#define R_1(opc)	( REG_OPC(opc) | M2 | M3 )	/* 1 operand: src1  */
+#define R_1D(opc)	( REG_OPC(opc) | M1 | M2 )	/* 1 operand: dst   */
+#define R_2(opc)	( REG_OPC(opc) | M3 )		/* 2 ops: src1/src2 */
+#define R_2D(opc)	( REG_OPC(opc) | M2 )		/* 2 ops: src1/dst  */
+#define R_3(opc)	( REG_OPC(opc) )		/* 3 operands       */
+
+/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
+ *
+ * Interpret names as follows:
+ *	R:   global or local register only
+ *	RS:  global, local, or (if target allows) special-function register only
+ *	RL:  global or local register, or integer literal
+ *	RSL: global, local, or (if target allows) special-function register;
+ *		or integer literal
+ *	F:   global, local, or floating-point register
+ *	FL:  global, local, or floating-point register; or literal (including
+ *		floating point)
+ *
+ * A number appended to a name indicates that registers must be aligned,
+ * as follows:
+ *	2: register number must be multiple of 2
+ *	4: register number must be multiple of 4
+ */
+
+#define SFR	0x10		/* Mask for the "sfr-OK" bit */
+#define LIT	0x08		/* Mask for the "literal-OK" bit */
+#define FP	0x04		/* Mask for "floating-point-OK" bit */
+
+/* This macro ors the bits together.  Note that 'align' is a mask
+ * for the low 0, 1, or 2 bits of the register number, as appropriate.
+ */
+#define OP(align,lit,fp,sfr)	( align | lit | fp | sfr )
+
+#define R	OP( 0, 0,   0,  0   )
+#define RS	OP( 0, 0,   0,  SFR )
+#define RL	OP( 0, LIT, 0,  0   )
+#define RSL	OP( 0, LIT, 0,  SFR )
+#define F	OP( 0, 0,   FP, 0   )
+#define FL	OP( 0, LIT, FP, 0   )
+#define R2	OP( 1, 0,   0,  0   )
+#define RL2	OP( 1, LIT, 0,  0   )
+#define F2	OP( 1, 0,   FP, 0   )
+#define FL2	OP( 1, LIT, FP, 0   )
+#define R4	OP( 3, 0,   0,  0   )
+#define RL4	OP( 3, LIT, 0,  0   )
+#define F4	OP( 3, 0,   FP, 0   )
+#define FL4	OP( 3, LIT, FP, 0   )
+
+#define M	0x7f	/* Memory operand (MEMA & MEMB format instructions) */
+
+/* Macros to extract info from the register operand descriptor byte 'od'.
+ */
+#define SFR_OK(od)	(od & SFR)	/* TRUE if sfr operand allowed */
+#define LIT_OK(od)	(od & LIT)	/* TRUE if literal operand allowed */
+#define FP_OK(od)	(od & FP)	/* TRUE if floating-point op allowed */
+#define REG_ALIGN(od,n)	((od & 0x3 & n) == 0)
+					/* TRUE if reg #n is properly aligned */
+#define MEMOP(od)	(od == M)	/* TRUE if operand is a memory operand*/
+
+/* Description of a single i80960 instruction */
+struct i960_opcode {
+	long opcode;	/* 32 bits, constant fields filled in, rest zeroed */
+	char *name;	/* Assembler mnemonic				   */
+	short iclass;	/* Class: see #defines below			   */
+	char format;	/* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ	   */
+	char num_ops;	/* Number of operands				   */
+	char operand[3];/* Operand descriptors; same order as assembler instr */
+};
+
+/* Classes of 960 intructions:
+ *	- each instruction falls into one class.
+ *	- each target architecture supports one or more classes.
+ *
+ * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
+ */
+#define I_BASE	0x01	/* 80960 base instruction set	*/
+#define I_CX	0x02	/* 80960Cx instruction		*/
+#define I_DEC	0x04	/* Decimal instruction		*/
+#define I_FP	0x08	/* Floating point instruction	*/
+#define I_KX	0x10	/* 80960Kx instruction		*/
+#define I_MIL	0x20	/* Military instruction		*/
+#define I_CASIM	0x40	/* CA simulator instruction	*/
+
+/******************************************************************************
+ *
+ *		TABLE OF i960 INSTRUCTION DESCRIPTIONS
+ *
+ ******************************************************************************/
+
+const struct i960_opcode i960_opcodes[] = {
+
+	/* if a CTRL instruction has an operand, it's always a displacement */
+
+	{ 0x09000000,	"callj",	I_BASE,	CALLJ, 	1 },/*default=='call'*/
+	{ 0x08000000,	"b",		I_BASE,	CTRL, 	1 },
+	{ 0x09000000,	"call",		I_BASE,	CTRL, 	1 },
+	{ 0x0a000000,	"ret",		I_BASE,	CTRL, 	0 },
+	{ 0x0b000000,	"bal",		I_BASE,	CTRL, 	1 },
+	{ 0x10000000,	"bno",		I_BASE,	CTRL, 	1 },
+	{ 0x10000000,	"bf",		I_BASE,	CTRL, 	1 }, /* same as bno */
+	{ 0x10000000,	"bru",		I_BASE,	CTRL, 	1 }, /* same as bno */
+	{ 0x11000000,	"bg",		I_BASE,	CTRL, 	1 },
+	{ 0x11000000,	"brg",		I_BASE,	CTRL, 	1 }, /* same as bg */
+	{ 0x12000000,	"be",		I_BASE,	CTRL, 	1 },
+	{ 0x12000000,	"bre",		I_BASE,	CTRL, 	1 }, /* same as be */
+	{ 0x13000000,	"bge",		I_BASE,	CTRL, 	1 },
+	{ 0x13000000,	"brge",		I_BASE,	CTRL, 	1 }, /* same as bge */
+	{ 0x14000000,	"bl",		I_BASE,	CTRL, 	1 },
+	{ 0x14000000,	"brl",		I_BASE,	CTRL, 	1 }, /* same as bl */
+	{ 0x15000000,	"bne",		I_BASE,	CTRL, 	1 },
+	{ 0x15000000,	"brlg",		I_BASE,	CTRL, 	1 }, /* same as bne */
+	{ 0x16000000,	"ble",		I_BASE,	CTRL, 	1 },
+	{ 0x16000000,	"brle",		I_BASE,	CTRL, 	1 }, /* same as ble */
+	{ 0x17000000,	"bo",		I_BASE,	CTRL, 	1 },
+	{ 0x17000000,	"bt",		I_BASE,	CTRL, 	1 }, /* same as bo */
+	{ 0x17000000,	"bro",		I_BASE,	CTRL, 	1 }, /* same as bo */
+	{ 0x18000000,	"faultno",	I_BASE,	CTRL, 	0 },
+	{ 0x18000000,	"faultf",	I_BASE,	CTRL, 	0 }, /*same as faultno*/
+	{ 0x19000000,	"faultg",	I_BASE,	CTRL, 	0 },
+	{ 0x1a000000,	"faulte",	I_BASE,	CTRL, 	0 },
+	{ 0x1b000000,	"faultge",	I_BASE,	CTRL, 	0 },
+	{ 0x1c000000,	"faultl",	I_BASE,	CTRL, 	0 },
+	{ 0x1d000000,	"faultne",	I_BASE,	CTRL, 	0 },
+	{ 0x1e000000,	"faultle",	I_BASE,	CTRL, 	0 },
+	{ 0x1f000000,	"faulto",	I_BASE,	CTRL, 	0 },
+	{ 0x1f000000,	"faultt",	I_BASE,	CTRL, 	0 }, /* syn for faulto */
+
+	{ 0x01000000,	"syscall",	I_CASIM,CTRL, 	0 },
+
+	/* If a COBR (or COJ) has 3 operands, the last one is always a
+	 * displacement and does not appear explicitly in the table.
+	 */
+
+	{ 0x20000000,	"testno",	I_BASE,	COBR,	1, R		},
+	{ 0x21000000,	"testg",	I_BASE,	COBR,	1, R		},
+	{ 0x22000000,	"teste",	I_BASE,	COBR,	1, R		},
+	{ 0x23000000,	"testge",	I_BASE,	COBR,	1, R		},
+	{ 0x24000000,	"testl",	I_BASE,	COBR,	1, R		},
+	{ 0x25000000,	"testne",	I_BASE,	COBR,	1, R		},
+	{ 0x26000000,	"testle",	I_BASE,	COBR,	1, R		},
+	{ 0x27000000,	"testo",	I_BASE,	COBR,	1, R		},
+	{ 0x30000000,	"bbc",		I_BASE,	COBR,	3, RL, RS	},
+	{ 0x31000000,	"cmpobg",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x32000000,	"cmpobe",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x33000000,	"cmpobge",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x34000000,	"cmpobl",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x35000000,	"cmpobne",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x36000000,	"cmpoble",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x37000000,	"bbs",		I_BASE,	COBR,	3, RL, RS	},
+	{ 0x38000000,	"cmpibno",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x39000000,	"cmpibg",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3a000000,	"cmpibe",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3b000000,	"cmpibge",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3c000000,	"cmpibl",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3d000000,	"cmpibne",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3e000000,	"cmpible",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x3f000000,	"cmpibo",	I_BASE,	COBR,	3, RL, RS	},
+	{ 0x31000000,	"cmpojg",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x32000000,	"cmpoje",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x33000000,	"cmpojge",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x34000000,	"cmpojl",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x35000000,	"cmpojne",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x36000000,	"cmpojle",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x38000000,	"cmpijno",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x39000000,	"cmpijg",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3a000000,	"cmpije",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3b000000,	"cmpijge",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3c000000,	"cmpijl",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3d000000,	"cmpijne",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3e000000,	"cmpijle",	I_BASE,	COJ,	3, RL, RS	},
+	{ 0x3f000000,	"cmpijo",	I_BASE,	COJ,	3, RL, RS	},
+
+	{ 0x80000000,	"ldob",		I_BASE,	MEM1,	2, M,  R	},
+	{ 0x82000000,	"stob",		I_BASE,	MEM1,	2, R , M	},
+	{ 0x84000000,	"bx",		I_BASE,	MEM1,	1, M		},
+	{ 0x85000000,	"balx",		I_BASE,	MEM1,	2, M,  R	},
+	{ 0x86000000,	"callx",	I_BASE,	MEM1,	1, M		},
+	{ 0x88000000,	"ldos",		I_BASE,	MEM2,	2, M,  R	},
+	{ 0x8a000000,	"stos",		I_BASE,	MEM2,	2, R , M	},
+	{ 0x8c000000,	"lda",		I_BASE,	MEM1,	2, M,  R	},
+	{ 0x90000000,	"ld",		I_BASE,	MEM4,	2, M,  R	},
+	{ 0x92000000,	"st",		I_BASE,	MEM4,	2, R , M	},
+	{ 0x98000000,	"ldl",		I_BASE,	MEM8,	2, M,  R2	},
+	{ 0x9a000000,	"stl",		I_BASE,	MEM8,	2, R2 ,M	},
+	{ 0xa0000000,	"ldt",		I_BASE,	MEM12,	2, M,  R4	},
+	{ 0xa2000000,	"stt",		I_BASE,	MEM12,	2, R4 ,M	},
+	{ 0xb0000000,	"ldq",		I_BASE,	MEM16,	2, M,  R4	},
+	{ 0xb2000000,	"stq",		I_BASE,	MEM16,	2, R4 ,M	},
+	{ 0xc0000000,	"ldib",		I_BASE,	MEM1,	2, M,  R	},
+	{ 0xc2000000,	"stib",		I_BASE,	MEM1,	2, R , M	},
+	{ 0xc8000000,	"ldis",		I_BASE,	MEM2,	2, M,  R	},
+	{ 0xca000000,	"stis",		I_BASE,	MEM2,	2, R , M	},
+
+	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x581),	"and",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x587),	"or",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, RSL,RS	},
+	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, RSL,RSL	},
+	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, RSL,RSL	},
+	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, RSL,RSL	},
+	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, RSL,RSL	},
+	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, RSL,RSL	},
+	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, RSL,RSL	},
+	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, RSL,RS	},
+	{ R_2D(0x5dc),	"movl",		I_BASE,	REG,	2, RL2,R2	},
+	{ R_2D(0x5ec),	"movt",		I_BASE,	REG,	2, RL4,R4	},
+	{ R_2D(0x5fc),	"movq",		I_BASE,	REG,	2, RL4,R4	},
+	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, RS, RSL,R	},
+	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, RS, RSL,RS	},
+	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, RSL,RS	},
+	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, RSL,RS	},
+	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, RSL,RSL,R	},
+	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, RSL,RSL,R	},
+	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, RSL,RSL,R	},
+	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, RSL		},
+	{ R_0(0x66b),	"mark",		I_BASE,	REG,	0,		},
+	{ R_0(0x66c),	"fmark",	I_BASE,	REG,	0,		},
+	{ R_0(0x66d),	"flushreg",	I_BASE,	REG,	0,		},
+	{ R_0(0x66f),	"syncf",	I_BASE,	REG,	0,		},
+	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, RSL,RSL,R2	},
+	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, RSL,RL2,RS	},
+	{ R_2D(0x672),	"cvtadr",	I_CASIM,REG, 	2, RL, R2	},
+	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, RSL,RSL,RS	},
+
+	/* Floating-point instructions */
+
+	{ R_2D(0x674),	"cvtir",	I_FP,	REG,	2, RL, F	},
+	{ R_2D(0x675),	"cvtilr",	I_FP,	REG,	2, RL, F	},
+	{ R_3(0x676),	"scalerl",	I_FP,	REG,	3, RL, FL2,F2	},
+	{ R_3(0x677),	"scaler",	I_FP,	REG,	3, RL, FL, F	},
+	{ R_3(0x680),	"atanr",	I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x681),	"logepr",	I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x682),	"logr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x683),	"remr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_2(0x684),	"cmpor",	I_FP,	REG,	2, FL, FL	},
+	{ R_2(0x685),	"cmpr",		I_FP,	REG,	2, FL, FL	},
+	{ R_2D(0x688),	"sqrtr",	I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x689),	"expr",		I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x68a),	"logbnr",	I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x68b),	"roundr",	I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x68c),	"sinr",		I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x68d),	"cosr",		I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x68e),	"tanr",		I_FP,	REG,	2, FL, F	},
+	{ R_1(0x68f),	"classr",	I_FP,	REG,	1, FL		},
+	{ R_3(0x690),	"atanrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x691),	"logeprl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x692),	"logrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x693),	"remrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_2(0x694),	"cmporl",	I_FP,	REG,	2, FL2,FL2	},
+	{ R_2(0x695),	"cmprl",	I_FP,	REG,	2, FL2,FL2	},
+	{ R_2D(0x698),	"sqrtrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x699),	"exprl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x69a),	"logbnrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x69b),	"roundrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x69c),	"sinrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x69d),	"cosrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x69e),	"tanrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_1(0x69f),	"classrl",	I_FP,	REG,	1, FL2		},
+	{ R_2D(0x6c0),	"cvtri",	I_FP,	REG,	2, FL, R	},
+	{ R_2D(0x6c1),	"cvtril",	I_FP,	REG,	2, FL, R2	},
+	{ R_2D(0x6c2),	"cvtzri",	I_FP,	REG,	2, FL, R	},
+	{ R_2D(0x6c3),	"cvtzril",	I_FP,	REG,	2, FL, R2	},
+	{ R_2D(0x6c9),	"movr",		I_FP,	REG,	2, FL, F	},
+	{ R_2D(0x6d9),	"movrl",	I_FP,	REG,	2, FL2,F2	},
+	{ R_2D(0x6e1),	"movre",	I_FP,	REG,	2, FL4,F4	},
+	{ R_3(0x6e2),	"cpysre",	I_FP,	REG,	3, FL4,FL4,F4	},
+	{ R_3(0x6e3),	"cpyrsre",	I_FP,	REG,	3, FL4,FL4,F4	},
+	{ R_3(0x78b),	"divr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x78c),	"mulr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x78d),	"subr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x78f),	"addr",		I_FP,	REG,	3, FL, FL, F	},
+	{ R_3(0x79b),	"divrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x79c),	"mulrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x79d),	"subrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+	{ R_3(0x79f),	"addrl",	I_FP,	REG,	3, FL2,FL2,F2	},
+
+	/* These are the floating point branch instructions.  Each actually
+	 * generates 2 branch instructions:  the first a CTRL instruction with
+	 * the indicated opcode, and the second a 'bno'.
+	 */
+
+	{ 0x12000000,	"brue",		I_FP,	FBRA, 	1	},
+	{ 0x11000000,	"brug",		I_FP,	FBRA, 	1	},
+	{ 0x13000000,	"bruge",	I_FP,	FBRA, 	1	},
+	{ 0x14000000,	"brul",		I_FP,	FBRA, 	1	},
+	{ 0x16000000,	"brule",	I_FP,	FBRA, 	1	},
+	{ 0x15000000,	"brulg",	I_FP,	FBRA, 	1	},
+
+
+	/* Decimal instructions */
+
+	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, RSL,RSL,RS	},
+	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, RSL,RS	},
+
+
+	/* KX extensions */
+
+	{ R_2(0x600),	"synmov",	I_KX,	REG,	2, R,  R	},
+	{ R_2(0x601),	"synmovl",	I_KX,	REG,	2, R,  R	},
+	{ R_2(0x602),	"synmovq",	I_KX,	REG,	2, R,  R	},
+	{ R_2D(0x615),	"synld",	I_KX,	REG,	2, R,  R	},
+
+
+	/* MC extensions */
+
+	{ R_3(0x603),	"cmpstr",	I_MIL,	REG,	3, R,  R,  RL	},
+	{ R_3(0x604),	"movqstr",	I_MIL,	REG,	3, R,  R,  RL	},
+	{ R_3(0x605),	"movstr",	I_MIL,	REG,	3, R,  R,  RL	},
+	{ R_2D(0x613),	"inspacc",	I_MIL,	REG,	2, R,  R	},
+	{ R_2D(0x614),	"ldphy",	I_MIL,	REG,	2, R,  R	},
+	{ R_3(0x617),	"fill",		I_MIL,	REG,	3, R,  RL, RL	},
+	{ R_2D(0x646),	"condrec",	I_MIL,	REG,	2, R,  R	},
+	{ R_2D(0x656),	"receive",	I_MIL,	REG,	2, R,  R	},
+	{ R_3(0x662),	"send",		I_MIL,	REG,	3, R,  RL, R	},
+	{ R_1(0x663),	"sendserv",	I_MIL,	REG,	1, R		},
+	{ R_1(0x664),	"resumprcs",	I_MIL,	REG,	1, R		},
+	{ R_1(0x665),	"schedprcs",	I_MIL,	REG,	1, R		},
+	{ R_0(0x666),	"saveprcs",	I_MIL,	REG,	0,		},
+	{ R_1(0x668),	"condwait",	I_MIL,	REG,	1, R		},
+	{ R_1(0x669),	"wait",		I_MIL,	REG,	1, R		},
+	{ R_1(0x66a),	"signal",	I_MIL,	REG,	1, R		},
+	{ R_1D(0x673),	"ldtime",	I_MIL,	REG,	1, R2		},
+
+
+	/* CX extensions */
+
+	{ R_3(0x5d8),	"eshro",	I_CX,	REG,	3, RSL,RSL,RS	},
+	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, RSL,RSL,RL	},
+	{ R_3(0x631),	"udma",		I_CX,	REG,	0		},
+	{ R_3(0x659),	"sysctl",	I_CX,	REG,	3, RSL,RSL,RL	},
+
+
+	/* END OF TABLE */
+
+	{ 0,		NULL,		0,	0 }
+};
+
+ /* end of i960-opcode.h */
diff --git a/gnu/usr.bin/gas/opcode/m68k.h b/gnu/usr.bin/gas/opcode/m68k.h
new file mode 100644
index 00000000000..2df55725bab
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/m68k.h
@@ -0,0 +1,1998 @@
+/* Opcode table for m680[01234]0/m6888[12]/m68851.
+   Copyright (C) 1989, 1991 Free Software Foundation.
+
+This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+Both GDB and GAS are free software; you can redistribute and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB and GAS are distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB or GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+/* These are used as bit flags for arch below. */
+
+enum m68k_architecture {
+	m68000 = 0x01,
+	m68008 = m68000, /* synonym for -m68000.  otherwise unused. */
+	m68010 = 0x02,
+	m68020 = 0x04,
+	m68030 = 0x08,
+	m68040 = 0x10,
+	m68881 = 0x20,
+	m68882 = m68881, /* synonym for -m68881.  otherwise unused. */
+	m68851 = 0x40,
+
+ /* handy aliases */
+	m68040up = m68040,
+	m68030up = (m68030 | m68040up),
+	m68020up = (m68020 | m68030up),
+	m68010up = (m68010 | m68020up),
+	m68000up = (m68000 | m68010up),
+
+	mfloat = (m68881 | m68882 | m68040),
+	mmmu   = (m68851 | m68030 | m68040)
+}; /* enum m68k_architecture */
+
+ /* note that differences in addressing modes that aren't distinguished
+    in the following table are handled explicitly by gas. */
+
+struct m68k_opcode {
+  char *name;
+  unsigned long opcode;
+  unsigned long  match;
+  char *args;
+  enum m68k_architecture arch;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and is as much longer as necessary to
+   hold the operands it has.
+
+   The match component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing two characters
+   for each operand of the instruction.  The first specifies
+   the kind of operand; the second, the place it is stored.  */
+
+/* Kinds of operands:
+   D  data register only.  Stored as 3 bits.
+   A  address register only.  Stored as 3 bits.
+   a  address register indirect only.  Stored as 3 bits.
+   R  either kind of register.  Stored as 4 bits.
+   F  floating point coprocessor register only.   Stored as 3 bits.
+   O  an offset (or width): immediate data 0-31 or data register.
+      Stored as 6 bits in special format for BF... insns.
+   +  autoincrement only.  Stored as 3 bits (number of the address register).
+   -  autodecrement only.  Stored as 3 bits (number of the address register).
+   Q  quick immediate data.  Stored as 3 bits.
+      This matches an immediate operand only when value is in range 1 .. 8.
+   M  moveq immediate data.  Stored as 8 bits.
+      This matches an immediate operand only when value is in range -128..127
+   T  trap vector immediate data.  Stored as 4 bits.
+
+   k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
+      a three bit register offset, depending on the field type.
+
+   #  immediate data.  Stored in special places (b, w or l)
+      which say how many bits to store.
+   ^  immediate data for floating point instructions.   Special places
+      are offset by 2 bytes from '#'...
+   B  pc-relative address, converted to an offset
+      that is treated as immediate data.
+   d  displacement and register.  Stores the register as 3 bits
+      and stores the displacement in the entire second word.
+
+   C  the CCR.  No need to store it; this is just for filtering validity.
+   S  the SR.  No need to store, just as with CCR.
+   U  the USP.  No need to store, just as with CCR.
+
+   I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
+      extracted from the 'd' field of word one, which means that an extended
+      coprocessor opcode can be skipped using the 'i' place, if needed.
+
+   s  System Control register for the floating point coprocessor.
+   S  List of system control registers for floating point coprocessor.
+
+   J  Misc register for movec instruction, stored in 'j' format.
+	Possible values:
+	0x000	SFC	Source Function Code reg	[40, 30, 20, 10]
+	0x001	DFC	Data Function Code reg		[40, 30, 20, 10]
+	0x002	CACR	Cache Control Register		[40, 30, 20]
+	0x800	USP	User Stack Pointer		[40, 30, 20, 10]
+	0x801	VBR	Vector Base reg			[40, 30, 20, 10]
+	0x802	CAAR	Cache Address Register		[    30, 20]
+	0x803	MSP	Master Stack Pointer		[40, 30, 20]
+	0x804	ISP	Interrupt Stack Pointer		[40, 30, 20]
+	0x003	TC	MMU Translation Control		[40]
+	0x004	ITT0	Instruction Transparent
+				Translation reg 0	[40]
+	0x005	ITT1	Instruction Transparent
+				Translation reg 1	[40]
+	0x006	DTT0	Data Transparent
+				Translation reg 0	[40]
+	0x007	DTT1	Data Transparent
+				Translation reg 1	[40]
+	0x805	MMUSR	MMU Status reg			[40]
+	0x806	URP	User Root Pointer		[40]
+	0x807	SRP	Supervisor Root Pointer		[40]
+
+    L  Register list of the type d0-d7/a0-a7 etc.
+       (New!  Improved!  Can also hold fp0-fp7, as well!)
+       The assembler tries to see if the registers match the insn by
+       looking at where the insn wants them stored.
+
+    l  Register list like L, but with all the bits reversed.
+       Used for going the other way. . .
+
+    c  cache identifier which may be "nc" for no cache, "ic"
+       for instruction cache, "dc" for data cache, or "bc"
+       for both caches.  Used in cinv and cpush.  Always
+       stored in position "d".
+
+ They are all stored as 6 bits using an address mode and a register number;
+ they differ in which addressing modes they match.
+
+   *  all					(modes 0-6,7.*)
+   ~  alterable memory				(modes 2-6,7.0,7.1)(not 0,1,7.~)
+   %  alterable					(modes 0-6,7.0,7.1)(not 7.~)
+   ;  data					(modes 0,2-6,7.*)(not 1)
+   @  data, but not immediate			(modes 0,2-6,7.? ? ?)(not 1,7.?)  This may really be ;, the 68020 book says it is
+   !  control					(modes 2,5,6,7.*-)(not 0,1,3,4,7.4)
+   &  alterable control				(modes 2,5,6,7.0,7.1)(not 0,1,7.? ? ?)
+   $  alterable data				(modes 0,2-6,7.0,7.1)(not 1,7.~)
+   ?  alterable control, or data register	(modes 0,2,5,6,7.0,7.1)(not 1,3,4,7.~)
+   /  control, or data register			(modes 0,2,5,6,7.0,7.1,7.2,7.3)(not 1,3,4,7.4)
+*/
+
+/* JF: for the 68851 */
+/*
+   I didn't use much imagination in choosing the 
+   following codes, so many of them aren't very
+   mnemonic. -rab
+
+   P  pmmu register
+	Possible values:
+	000	TC	Translation Control reg
+	100	CAL	Current Access Level
+	101	VAL	Validate Access Level
+	110	SCC	Stack Change Control
+	111	AC	Access Control
+
+   W  wide pmmu registers
+	Possible values:
+	001	DRP	Dma Root Pointer
+	010	SRP	Supervisor Root Pointer
+	011	CRP	Cpu Root Pointer
+
+   f	function code register
+	0	SFC
+	1	DFC
+
+   V	VAL register only
+
+   X	BADx, BACx
+	100	BAD	Breakpoint Acknowledge Data
+	101	BAC	Breakpoint Acknowledge Control
+
+   Y	PSR
+   Z	PCSR
+
+   |	memory 		(modes 2-6, 7.*)
+
+*/
+
+/* Places to put an operand, for non-general operands:
+   s  source, low bits of first word.
+   d  dest, shifted 9 in first word
+   1  second word, shifted 12
+   2  second word, shifted 6
+   3  second word, shifted 0
+   4  third word, shifted 12
+   5  third word, shifted 6
+   6  third word, shifted 0
+   7  second word, shifted 7
+   8  second word, shifted 10
+   D  store in both place 1 and place 3; for divul and divsl.
+   B  first word, low byte, for branch displacements
+   W  second word (entire), for branch displacements
+   L  second and third words (entire), for branch displacements (also overloaded for move16)
+   b  second word, low byte
+   w  second word (entire) [variable word/long branch offset for dbra]
+   l  second and third word (entire)
+   g  variable branch offset for bra and similar instructions.
+      The place to store depends on the magnitude of offset.
+   t  store in both place 7 and place 8; for floating point operations
+   c  branch offset for cpBcc operations.
+      The place to store is word two if bit six of word one is zero,
+      and words two and three if bit six of word one is one.
+   i  Increment by two, to skip over coprocessor extended operands.   Only
+      works with the 'I' format.
+   k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
+      Also used for dynamic fmovem instruction.
+   C  floating point coprocessor constant - 7 bits.  Also used for static
+      K-factors...
+   j  Movec register #, stored in 12 low bits of second word.
+
+ Places to put operand, for general operands:
+   d  destination, shifted 6 bits in first word
+   b  source, at low bit of first word, and immediate uses one byte
+   w  source, at low bit of first word, and immediate uses two bytes
+   l  source, at low bit of first word, and immediate uses four bytes
+   s  source, at low bit of first word.
+      Used sometimes in contexts where immediate is not allowed anyway.
+   f  single precision float, low bit of 1st word, immediate uses 4 bytes
+   F  double precision float, low bit of 1st word, immediate uses 8 bytes
+   x  extended precision float, low bit of 1st word, immediate uses 12 bytes
+   p  packed float, low bit of 1st word, immediate uses 12 bytes
+*/
+
+#define one(x) ((x) << 16)
+#define two(x, y) (((x) << 16) + y)
+
+/*
+	*** DANGER WILL ROBINSON ***
+
+   The assembler requires that all instances of the same mnemonic must be
+   consecutive.  If they aren't, the assembler will bomb at runtime
+ */
+struct m68k_opcode m68k_opcodes[] =
+{
+{"abcd",	one(0140400),		one(0170770), "DsDd", m68000up },
+{"abcd",	one(0140410),		one(0170770), "-s-d", m68000up },
+
+		/* Add instructions */
+{"addal",	one(0150700),		one(0170700), "*lAd", m68000up },
+{"addaw",	one(0150300),		one(0170700), "*wAd", m68000up },
+{"addib",	one(0003000),		one(0177700), "#b$b", m68000up },
+{"addil",	one(0003200),		one(0177700), "#l$l", m68000up },
+{"addiw",	one(0003100),		one(0177700), "#w$w", m68000up },
+{"addqb",	one(0050000),		one(0170700), "Qd$b", m68000up },
+{"addql",	one(0050200),		one(0170700), "Qd%l", m68000up },
+{"addqw",	one(0050100),		one(0170700), "Qd%w", m68000up },
+
+{"addb",	one(0050000),		one(0170700), "Qd$b", m68000up },	/* addq written as add */
+{"addb",	one(0003000),		one(0177700), "#b$b", m68000up },	/* addi written as add */
+{"addb",	one(0150000),		one(0170700), ";bDd", m68000up },	/* addb <ea>,	Dd */
+{"addb",	one(0150400),		one(0170700), "Dd~b", m68000up },	/* addb Dd,	<ea> */
+
+{"addw",	one(0050100),		one(0170700), "Qd%w", m68000up },	/* addq written as add */
+{"addw",	one(0003100),		one(0177700), "#w$w", m68000up },	/* addi written as add */
+{"addw",	one(0150300),		one(0170700), "*wAd", m68000up },	/* adda written as add */
+{"addw",	one(0150100),		one(0170700), "*wDd", m68000up },	/* addw <ea>,	Dd */
+{"addw",	one(0150500),		one(0170700), "Dd~w", m68000up },	/* addw Dd,	<ea> */
+
+{"addl",	one(0050200),		one(0170700), "Qd%l", m68000up },	/* addq written as add */
+{"addl",	one(0003200),		one(0177700), "#l$l", m68000up },	/* addi written as add */
+{"addl",	one(0150700),		one(0170700), "*lAd", m68000up },	/* adda written as add */
+{"addl",	one(0150200),		one(0170700), "*lDd", m68000up },	/* addl <ea>,	Dd */
+{"addl",	one(0150600),		one(0170700), "Dd~l", m68000up },	/* addl Dd,	<ea> */
+
+{"addxb",	one(0150400),		one(0170770), "DsDd", m68000up },
+{"addxb",	one(0150410),		one(0170770), "-s-d", m68000up },
+{"addxl",	one(0150600),		one(0170770), "DsDd", m68000up },
+{"addxl",	one(0150610),		one(0170770), "-s-d", m68000up },
+{"addxw",	one(0150500),		one(0170770), "DsDd", m68000up },
+{"addxw",	one(0150510),		one(0170770), "-s-d", m68000up },
+
+{"andib",	one(0001000),		one(0177700), "#b$b", m68000up },
+{"andib",	one(0001074),		one(0177777), "#bCb", m68000up },	/* andi to ccr */
+{"andiw",	one(0001100),		one(0177700), "#w$w", m68000up },
+{"andiw",	one(0001174),		one(0177777), "#wSw", m68000up },	/* andi to sr */
+{"andil",	one(0001200),		one(0177700), "#l$l", m68000up },
+
+{"andb",	one(0001000),		one(0177700), "#b$b", m68000up },	/* andi written as or */
+{"andb",	one(0001074),		one(0177777), "#bCb", m68000up },	/* andi to ccr */
+{"andb",	one(0140000),		one(0170700), ";bDd", m68000up },	/* memory to register */
+{"andb",	one(0140400),		one(0170700), "Dd~b", m68000up },	/* register to memory */
+{"andw",	one(0001100),		one(0177700), "#w$w", m68000up },	/* andi written as or */
+{"andw",	one(0001174),		one(0177777), "#wSw", m68000up },	/* andi to sr */
+{"andw",	one(0140100),		one(0170700), ";wDd", m68000up },	/* memory to register */
+{"andw",	one(0140500),		one(0170700), "Dd~w", m68000up },	/* register to memory */
+{"andl",	one(0001200),		one(0177700), "#l$l", m68000up },	/* andi written as or */
+{"andl",	one(0140200),		one(0170700), ";lDd", m68000up },	/* memory to register */
+{"andl",	one(0140600),		one(0170700), "Dd~l", m68000up },	/* register to memory */
+
+{"aslb",	one(0160400),		one(0170770), "QdDs", m68000up },
+{"aslb",	one(0160440),		one(0170770), "DdDs", m68000up },
+{"asll",	one(0160600),		one(0170770), "QdDs", m68000up },
+{"asll",	one(0160640),		one(0170770), "DdDs", m68000up },
+{"aslw",	one(0160500),		one(0170770), "QdDs", m68000up },
+{"aslw",	one(0160540),		one(0170770), "DdDs", m68000up },
+{"aslw",	one(0160700),		one(0177700), "~s",   m68000up },	/* Shift memory */
+{"asrb",	one(0160000),		one(0170770), "QdDs", m68000up },
+{"asrb",	one(0160040),		one(0170770), "DdDs", m68000up },
+{"asrl",	one(0160200),		one(0170770), "QdDs", m68000up },
+{"asrl",	one(0160240),		one(0170770), "DdDs", m68000up },
+{"asrw",	one(0160100),		one(0170770), "QdDs", m68000up },
+{"asrw",	one(0160140),		one(0170770), "DdDs", m68000up },
+{"asrw",	one(0160300),		one(0177700), "~s",   m68000up },	/* Shift memory */
+
+/* Fixed-size branches with 16-bit offsets */
+
+{"bhi",		one(0061000),		one(0177777), "BW", m68000up },
+{"bls",		one(0061400),		one(0177777), "BW", m68000up },
+{"bcc",		one(0062000),		one(0177777), "BW", m68000up },
+{"bcs",		one(0062400),		one(0177777), "BW", m68000up },
+{"bne",		one(0063000),		one(0177777), "BW", m68000up },
+{"beq",		one(0063400),		one(0177777), "BW", m68000up },
+{"bvc",		one(0064000),		one(0177777), "BW", m68000up },
+{"bvs",		one(0064400),		one(0177777), "BW", m68000up },
+{"bpl",		one(0065000),		one(0177777), "BW", m68000up },
+{"bmi",		one(0065400),		one(0177777), "BW", m68000up },
+{"bge",		one(0066000),		one(0177777), "BW", m68000up },
+{"blt",		one(0066400),		one(0177777), "BW", m68000up },
+{"bgt",		one(0067000),		one(0177777), "BW", m68000up },
+{"ble",		one(0067400),		one(0177777), "BW", m68000up },
+{"bra",		one(0060000),		one(0177777), "BW", m68000up },
+{"bsr",		one(0060400),		one(0177777), "BW", m68000up },
+
+/* Fixed-size branches with short (byte) offsets */
+
+{"bhis",	one(0061000),		one(0177400), "BB", m68000up },
+{"blss",	one(0061400),		one(0177400), "BB", m68000up },
+{"bccs",	one(0062000),		one(0177400), "BB", m68000up },
+{"bcss",	one(0062400),		one(0177400), "BB", m68000up },
+{"bnes",	one(0063000),		one(0177400), "BB", m68000up },
+{"beqs",	one(0063400),		one(0177400), "BB", m68000up },
+{"bvcs",	one(0064000),		one(0177400), "BB", m68000up },
+{"bvss",	one(0064400),		one(0177400), "BB", m68000up },
+{"bpls",	one(0065000),		one(0177400), "BB", m68000up },
+{"bmis",	one(0065400),		one(0177400), "BB", m68000up },
+{"bges",	one(0066000),		one(0177400), "BB", m68000up },
+{"blts",	one(0066400),		one(0177400), "BB", m68000up },
+{"bgts",	one(0067000),		one(0177400), "BB", m68000up },
+{"bles",	one(0067400),		one(0177400), "BB", m68000up },
+{"bras",	one(0060000),		one(0177400), "BB", m68000up },
+{"bsrs",	one(0060400),		one(0177400), "BB", m68000up },
+
+/* Fixed-size branches with long (32-bit) offsets */
+
+{"bhil",	one(0061377),		one(0177777), "BL", m68020up },
+{"blsl",	one(0061777),		one(0177777), "BL", m68020up },
+{"bccl",	one(0062377),		one(0177777), "BL", m68020up },
+{"bcsl",	one(0062777),		one(0177777), "BL", m68020up },
+{"bnel",	one(0063377),		one(0177777), "BL", m68020up },
+{"beql",	one(0063777),		one(0177777), "BL", m68020up },
+{"bvcl",	one(0064377),		one(0177777), "BL", m68020up },
+{"bvsl",	one(0064777),		one(0177777), "BL", m68020up },
+{"bpll",	one(0065377),		one(0177777), "BL", m68020up },
+{"bmil",	one(0065777),		one(0177777), "BL", m68020up },
+{"bgel",	one(0066377),		one(0177777), "BL", m68020up },
+{"bltl",	one(0066777),		one(0177777), "BL", m68020up },
+{"bgtl",	one(0067377),		one(0177777), "BL", m68020up },
+{"blel",	one(0067777),		one(0177777), "BL", m68020up },
+{"bral",	one(0060377),		one(0177777), "BL", m68020up },
+{"bsrl",	one(0060777),		one(0177777), "BL", m68020up },
+
+/* We now return you to our regularly scheduled instruction set */
+
+{"bchg",	one(0000500),		one(0170700),		"Dd$s", m68000up },
+{"bchg",	one(0004100),		one(0177700),		"#b$s", m68000up },
+{"bclr",	one(0000600),		one(0170700),		"Dd$s", m68000up },
+{"bclr",	one(0004200),		one(0177700),		"#b$s", m68000up },
+
+{"bfchg",	two(0165300, 0),	two(0177700, 0170000),	"?sO2O3",   m68020up },
+{"bfclr",	two(0166300, 0),	two(0177700, 0170000),	"?sO2O3",   m68020up },
+{"bfexts",	two(0165700, 0),	two(0177700, 0100000),	"/sO2O3D1", m68020up },
+{"bfextu",	two(0164700, 0),	two(0177700, 0100000),	"/sO2O3D1", m68020up },
+{"bfffo",	two(0166700, 0),	two(0177700, 0100000),	"/sO2O3D1", m68020up },
+{"bfins",	two(0167700, 0),	two(0177700, 0100000),	"D1?sO2O3", m68020up },
+{"bfset",	two(0167300, 0),	two(0177700, 0170000),	"?sO2O3",   m68020up },
+{"bftst",	two(0164300, 0),	two(0177700, 0170000),	"/sO2O3",   m68020up },
+{"bkpt",	one(0044110),		one(0177770),		"Qs",       m68020up },
+
+{"bset",	one(0000700),		one(0170700),		"Dd$s", m68000up },
+{"bset",	one(0004300),		one(0177700),		"#b$s", m68000up },
+{"btst",	one(0000400),		one(0170700),		"Dd@s", m68000up },
+{"btst",	one(0004000),		one(0177700),		"#b@s", m68000up },
+
+
+{"callm",	one(0003300),		one(0177700),		"#b!s", m68020 },
+
+{"cas2l",	two(0007374, 0),	two(0177777, 0107070),	"D3D6D2D5R1R4", m68020up }, /* JF FOO really a 3 word ins */
+{"cas2w",	two(0006374, 0),	two(0177777, 0107070),	"D3D6D2D5R1R4", m68020up }, /* JF ditto */
+{"casb",	two(0005300, 0),	two(0177700, 0177070),	"D3D2~s", m68020up },
+{"casl",	two(0007300, 0),	two(0177700, 0177070),	"D3D2~s", m68020up },
+{"casw",	two(0006300, 0),	two(0177700, 0177070),	"D3D2~s", m68020up },
+
+/*  {"chk",	one(0040600),		one(0170700),		";wDd"}, JF FOO this looks wrong */
+{"chk2b",	two(0000300, 0004000),	two(0177700, 07777),	"!sR1", m68020up },
+{"chk2l",	two(0002300, 0004000),	two(0177700, 07777),	"!sR1", m68020up },
+{"chk2w",	two(0001300, 0004000),	two(0177700, 07777),	"!sR1", m68020up },
+{"chkl",	one(0040400),		one(0170700),		";lDd", m68000up },
+{"chkw",	one(0040600),		one(0170700),		";wDd", m68000up },
+
+#define SCOPE_LINE (0x1 << 3)
+#define SCOPE_PAGE (0x2 << 3)
+#define SCOPE_ALL  (0x3 << 3)
+{"cinva",	one(0xf400|SCOPE_ALL),  one(0xff38), "ce",   m68040 },
+{"cinvl",	one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040 },
+{"cinvp",	one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040 },
+
+{"cpusha",	one(0xf420|SCOPE_ALL),  one(0xff38), "ce",   m68040 },
+{"cpushl",	one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040 },
+{"cpushp",	one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040 },
+
+#undef SCOPE_LINE
+#undef SCOPE_PAGE
+#undef SCOPE_ALL
+
+{"clrb",	one(0041000),		one(0177700),		"$s", m68000up },
+{"clrl",	one(0041200),		one(0177700),		"$s", m68000up },
+{"clrw",	one(0041100),		one(0177700),		"$s", m68000up },
+
+{"cmp2b",	two(0000300, 0),	two(0177700, 07777),	"!sR1", m68020up },
+{"cmp2l",	two(0002300, 0),	two(0177700, 07777),	"!sR1", m68020up },
+{"cmp2w",	two(0001300, 0),	two(0177700, 07777),	"!sR1", m68020up },
+{"cmpal",	one(0130700),		one(0170700),		"*lAd", m68000up },
+{"cmpaw",	one(0130300),		one(0170700),		"*wAd", m68000up },
+{"cmpib",	one(0006000),		one(0177700),		"#b;b", m68000up },
+{"cmpil",	one(0006200),		one(0177700),		"#l;l", m68000up },
+{"cmpiw",	one(0006100),		one(0177700),		"#w;w", m68000up },
+{"cmpb",	one(0006000),		one(0177700),		"#b;b", m68000up },	/* cmpi written as cmp */
+{"cmpb",	one(0130000),		one(0170700),		";bDd", m68000up },
+{"cmpw",	one(0006100),		one(0177700),		"#w;w", m68000up },
+{"cmpw",	one(0130100),		one(0170700),		"*wDd", m68000up },
+{"cmpw",	one(0130300),		one(0170700),		"*wAd", m68000up },	/* cmpa written as cmp */
+{"cmpl",	one(0006200),		one(0177700),		"#l;l", m68000up },
+{"cmpl",	one(0130200),		one(0170700),		"*lDd", m68000up },
+{"cmpl",	one(0130700),		one(0170700),		"*lAd", m68000up },
+{"cmpmb",	one(0130410),		one(0170770),		"+s+d", m68000up },
+{"cmpml",	one(0130610),		one(0170770),		"+s+d", m68000up },
+{"cmpmw",	one(0130510),		one(0170770),		"+s+d", m68000up },
+
+{"dbcc",	one(0052310),		one(0177770),		"DsBw", m68000up },
+{"dbcs",	one(0052710),		one(0177770),		"DsBw", m68000up },
+{"dbeq",	one(0053710),		one(0177770),		"DsBw", m68000up },
+{"dbf",		one(0050710),		one(0177770),		"DsBw", m68000up },
+{"dbge",	one(0056310),		one(0177770),		"DsBw", m68000up },
+{"dbgt",	one(0057310),		one(0177770),		"DsBw", m68000up },
+{"dbhi",	one(0051310),		one(0177770),		"DsBw", m68000up },
+{"dble",	one(0057710),		one(0177770),		"DsBw", m68000up },
+{"dbls",	one(0051710),		one(0177770),		"DsBw", m68000up },
+{"dblt",	one(0056710),		one(0177770),		"DsBw", m68000up },
+{"dbmi",	one(0055710),		one(0177770),		"DsBw", m68000up },
+{"dbne",	one(0053310),		one(0177770),		"DsBw", m68000up },
+{"dbpl",	one(0055310),		one(0177770),		"DsBw", m68000up },
+{"dbra",	one(0050710),		one(0177770),		"DsBw", m68000up },
+{"dbt",		one(0050310),		one(0177770),		"DsBw", m68000up },
+{"dbvc",	one(0054310),		one(0177770),		"DsBw", m68000up },
+{"dbvs",	one(0054710),		one(0177770),		"DsBw", m68000up },
+
+{"divsl",	two(0046100, 0006000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"divsl",	two(0046100, 0004000),	two(0177700, 0107770),	";lDD", m68020up },
+{"divsll",	two(0046100, 0004000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"divsw",	one(0100700),		one(0170700),		";wDd", m68000up },
+{"divs",	one(0100700),		one(0170700),		";wDd", m68000up },
+{"divul",	two(0046100, 0002000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"divul",	two(0046100, 0000000),	two(0177700, 0107770),	";lDD", m68020up },
+{"divull",	two(0046100, 0000000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"divuw",	one(0100300),		one(0170700),		";wDd", m68000up },
+{"divu",	one(0100300),		one(0170700),		";wDd", m68000up },
+{"eorb",	one(0005000),		one(0177700),		"#b$s", m68000up },	/* eori written as or */
+{"eorb",	one(0005074),		one(0177777),		"#bCs", m68000up },	/* eori to ccr */
+{"eorb",	one(0130400),		one(0170700),		"Dd$s", m68000up },	/* register to memory */
+{"eorib",	one(0005000),		one(0177700),		"#b$s", m68000up },
+{"eorib",	one(0005074),		one(0177777),		"#bCs", m68000up },	/* eori to ccr */
+{"eoril",	one(0005200),		one(0177700),		"#l$s", m68000up },
+{"eoriw",	one(0005100),		one(0177700),		"#w$s", m68000up },
+{"eoriw",	one(0005174),		one(0177777),		"#wSs", m68000up },	/* eori to sr */
+{"eorl",	one(0005200),		one(0177700),		"#l$s", m68000up },
+{"eorl",	one(0130600),		one(0170700),		"Dd$s", m68000up },
+{"eorw",	one(0005100),		one(0177700),		"#w$s", m68000up },
+{"eorw",	one(0005174),		one(0177777),		"#wSs", m68000up },	/* eori to sr */
+{"eorw",	one(0130500),		one(0170700),		"Dd$s", m68000up },
+
+{"exg",		one(0140500),		one(0170770),		"DdDs", m68000up },
+{"exg",		one(0140510),		one(0170770),		"AdAs", m68000up },
+{"exg",		one(0140610),		one(0170770),		"DdAs", m68000up },
+{"exg",		one(0140610),		one(0170770),		"AsDd", m68000up },
+
+{"extw",	one(0044200),		one(0177770),		"Ds", m68000up },
+{"extl",	one(0044300),		one(0177770),		"Ds", m68000up },
+{"extbl",	one(0044700),		one(0177770),		"Ds", m68020up },
+{"extb.l",	one(0044700),		one(0177770),		"Ds", m68020up }, /* Not sure we should support this one */
+
+/* float stuff starts here */
+{"fabsb",	two(0xF000, 0x5818),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fabsd",	two(0xF000, 0x5418),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fabsl",	two(0xF000, 0x4018),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fabsp",	two(0xF000, 0x4C18),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fabss",	two(0xF000, 0x4418),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fabsw",	two(0xF000, 0x5018),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fabsx",	two(0xF000, 0x0018),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fabsx",	two(0xF000, 0x4818),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fabsx",	two(0xF000, 0x0018),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+/* FIXME-NOW: The '040 book that I have claims that these should be
+   coded exactly like fadd.  In fact, the table of opmodes calls them
+   fadd, fsadd, fdadd.  That can't be right.  If someone can give me the
+   right encoding, I'll fix it.  By induction, I *think* the right
+   encoding is 38 & 3c, but I'm not sure.
+
+   in the mean time, if you know the encoding for the opmode field, you
+   can replace all of the "38),"'s and "3c),"'s below with the corrected
+   values and these guys should then just work.  xoxorich. 31Aug91 */
+{"fsabsb",	two(0xF000, 0x5858),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fsabsd",	two(0xF000, 0x5458),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fsabsl",	two(0xF000, 0x4058),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fsabsp",	two(0xF000, 0x4C58),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fsabss",	two(0xF000, 0x4458),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fsabsw",	two(0xF000, 0x5058),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fsabsx",	two(0xF000, 0x0058),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fsabsx",	two(0xF000, 0x4858),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fsabsx",	two(0xF000, 0x0058),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fdabsb",	two(0xF000, 0x585c),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040},
+{"fdabsd",	two(0xF000, 0x545c),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040},
+{"fdabsl",	two(0xF000, 0x405c),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040},
+{"fdabsp",	two(0xF000, 0x4C5c),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040},
+{"fdabss",	two(0xF000, 0x445c),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040},
+{"fdabsw",	two(0xF000, 0x505c),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040},
+{"fdabsx",	two(0xF000, 0x005c),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040},
+{"fdabsx",	two(0xF000, 0x485c),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040},
+{"fdabsx",	two(0xF000, 0x005c),	two(0xF1C0, 0xE07F),	"IiFt",   m68040},
+
+{"facosb",	two(0xF000, 0x581C),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"facosd",	two(0xF000, 0x541C),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"facosl",	two(0xF000, 0x401C),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"facosp",	two(0xF000, 0x4C1C),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"facoss",	two(0xF000, 0x441C),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"facosw",	two(0xF000, 0x501C),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"facosx",	two(0xF000, 0x001C),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"facosx",	two(0xF000, 0x481C),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"facosx",	two(0xF000, 0x001C),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"faddb",	two(0xF000, 0x5822),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"faddd",	two(0xF000, 0x5422),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"faddl",	two(0xF000, 0x4022),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"faddp",	two(0xF000, 0x4C22),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fadds",	two(0xF000, 0x4422),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"faddw",	two(0xF000, 0x5022),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"faddx",	two(0xF000, 0x0022),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"faddx",	two(0xF000, 0x4822),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"faddx",	two(0xF000, 0x0022),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF removed */
+{"fsaddb",	two(0xF000, 0x5862),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fsaddd",	two(0xF000, 0x5462),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fsaddl",	two(0xF000, 0x4062),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fsaddp",	two(0xF000, 0x4C62),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fsadds",	two(0xF000, 0x4462),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fsaddw",	two(0xF000, 0x5062),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fsaddx",	two(0xF000, 0x0062),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fsaddx",	two(0xF000, 0x4862),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"fsaddx",	two(0xF000, 0x0062),	two(0xF1C0, 0xE07F),	"IiFt", m68040 }, JF removed */
+{"fdaddb",	two(0xF000, 0x5866),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fdaddd",	two(0xF000, 0x5466),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fdaddl",	two(0xF000, 0x4066),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fdaddp",	two(0xF000, 0x4C66),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fdadds",	two(0xF000, 0x4466),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fdaddw",	two(0xF000, 0x5066),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fdaddx",	two(0xF000, 0x0066),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fdaddx",	two(0xF000, 0x4866),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"faddx",	two(0xF000, 0x0066),	two(0xF1C0, 0xE07F),	"IiFt", m68040 }, JF removed */
+
+{"fasinb",	two(0xF000, 0x580C),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fasind",	two(0xF000, 0x540C),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fasinl",	two(0xF000, 0x400C),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fasinp",	two(0xF000, 0x4C0C),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fasins",	two(0xF000, 0x440C),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fasinw",	two(0xF000, 0x500C),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fasinx",	two(0xF000, 0x000C),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fasinx",	two(0xF000, 0x480C),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fasinx",	two(0xF000, 0x000C),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fatanb",	two(0xF000, 0x580A),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fatand",	two(0xF000, 0x540A),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fatanl",	two(0xF000, 0x400A),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fatanp",	two(0xF000, 0x4C0A),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fatans",	two(0xF000, 0x440A),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fatanw",	two(0xF000, 0x500A),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fatanx",	two(0xF000, 0x000A),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fatanx",	two(0xF000, 0x480A),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fatanx",	two(0xF000, 0x000A),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fatanhb",	two(0xF000, 0x580D),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fatanhd",	two(0xF000, 0x540D),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fatanhl",	two(0xF000, 0x400D),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fatanhp",	two(0xF000, 0x4C0D),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fatanhs",	two(0xF000, 0x440D),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fatanhw",	two(0xF000, 0x500D),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fatanhx",	two(0xF000, 0x000D),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fatanhx",	two(0xF000, 0x480D),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fatanhx",	two(0xF000, 0x000D),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+/* Fixed-size Float branches */
+
+{"fbeq",	one(0xF081),		one(0xF1BF),		"IdBW", mfloat },
+{"fbf",		one(0xF080),		one(0xF1BF),		"IdBW", mfloat },
+{"fbge",	one(0xF093),		one(0xF1BF),		"IdBW", mfloat },
+{"fbgl",	one(0xF096),		one(0xF1BF),		"IdBW", mfloat },
+{"fbgle",	one(0xF097),		one(0xF1BF),		"IdBW", mfloat },
+{"fbgt",	one(0xF092),		one(0xF1BF),		"IdBW", mfloat },
+{"fble",	one(0xF095),		one(0xF1BF),		"IdBW", mfloat },
+{"fblt",	one(0xF094),		one(0xF1BF),		"IdBW", mfloat },
+{"fbne",	one(0xF08E),		one(0xF1BF),		"IdBW", mfloat },
+{"fbnge",	one(0xF09C),		one(0xF1BF),		"IdBW", mfloat },
+{"fbngl",	one(0xF099),		one(0xF1BF),		"IdBW", mfloat },
+{"fbngle",	one(0xF098),		one(0xF1BF),		"IdBW", mfloat },
+{"fbngt",	one(0xF09D),		one(0xF1BF),		"IdBW", mfloat },
+{"fbnle",	one(0xF09A),		one(0xF1BF),		"IdBW", mfloat },
+{"fbnlt",	one(0xF09B),		one(0xF1BF),		"IdBW", mfloat },
+{"fboge",	one(0xF083),		one(0xF1BF),		"IdBW", mfloat },
+{"fbogl",	one(0xF086),		one(0xF1BF),		"IdBW", mfloat },
+{"fbogt",	one(0xF082),		one(0xF1BF),		"IdBW", mfloat },
+{"fbole",	one(0xF085),		one(0xF1BF),		"IdBW", mfloat },
+{"fbolt",	one(0xF084),		one(0xF1BF),		"IdBW", mfloat },
+{"fbor",	one(0xF087),		one(0xF1BF),		"IdBW", mfloat },
+{"fbseq",	one(0xF091),		one(0xF1BF),		"IdBW", mfloat },
+{"fbsf",	one(0xF090),		one(0xF1BF),		"IdBW", mfloat },
+{"fbsne",	one(0xF09E),		one(0xF1BF),		"IdBW", mfloat },
+{"fbst",	one(0xF09F),		one(0xF1BF),		"IdBW", mfloat },
+{"fbt",		one(0xF08F),		one(0xF1BF),		"IdBW", mfloat },
+{"fbueq",	one(0xF089),		one(0xF1BF),		"IdBW", mfloat },
+{"fbuge",	one(0xF08B),		one(0xF1BF),		"IdBW", mfloat },
+{"fbugt",	one(0xF08A),		one(0xF1BF),		"IdBW", mfloat },
+{"fbule",	one(0xF08D),		one(0xF1BF),		"IdBW", mfloat },
+{"fbult",	one(0xF08C),		one(0xF1BF),		"IdBW", mfloat },
+{"fbun",	one(0xF088),		one(0xF1BF),		"IdBW", mfloat },
+
+/* Float branches -- long (32-bit) displacements */
+
+{"fbeql",	one(0xF081),		one(0xF1BF),		"IdBC", mfloat },
+{"fbfl",	one(0xF080),		one(0xF1BF),		"IdBC", mfloat },
+{"fbgel",	one(0xF093),		one(0xF1BF),		"IdBC", mfloat },
+{"fbgll",	one(0xF096),		one(0xF1BF),		"IdBC", mfloat },
+{"fbglel",	one(0xF097),		one(0xF1BF),		"IdBC", mfloat },
+{"fbgtl",	one(0xF092),		one(0xF1BF),		"IdBC", mfloat },
+{"fblel",	one(0xF095),		one(0xF1BF),		"IdBC", mfloat },
+{"fbltl",	one(0xF094),		one(0xF1BF),		"IdBC", mfloat },
+{"fbnel",	one(0xF08E),		one(0xF1BF),		"IdBC", mfloat },
+{"fbngel",	one(0xF09C),		one(0xF1BF),		"IdBC", mfloat },
+{"fbngll",	one(0xF099),		one(0xF1BF),		"IdBC", mfloat },
+{"fbnglel",	one(0xF098),		one(0xF1BF),		"IdBC", mfloat },
+{"fbngtl",	one(0xF09D),		one(0xF1BF),		"IdBC", mfloat },
+{"fbnlel",	one(0xF09A),		one(0xF1BF),		"IdBC", mfloat },
+{"fbnltl",	one(0xF09B),		one(0xF1BF),		"IdBC", mfloat },
+{"fbogel",	one(0xF083),		one(0xF1BF),		"IdBC", mfloat },
+{"fbogll",	one(0xF086),		one(0xF1BF),		"IdBC", mfloat },
+{"fbogtl",	one(0xF082),		one(0xF1BF),		"IdBC", mfloat },
+{"fbolel",	one(0xF085),		one(0xF1BF),		"IdBC", mfloat },
+{"fboltl",	one(0xF084),		one(0xF1BF),		"IdBC", mfloat },
+{"fborl",	one(0xF087),		one(0xF1BF),		"IdBC", mfloat },
+{"fbseql",	one(0xF091),		one(0xF1BF),		"IdBC", mfloat },
+{"fbsfl",	one(0xF090),		one(0xF1BF),		"IdBC", mfloat },
+{"fbsnel",	one(0xF09E),		one(0xF1BF),		"IdBC", mfloat },
+{"fbstl",	one(0xF09F),		one(0xF1BF),		"IdBC", mfloat },
+{"fbtl",	one(0xF08F),		one(0xF1BF),		"IdBC", mfloat },
+{"fbueql",	one(0xF089),		one(0xF1BF),		"IdBC", mfloat },
+{"fbugel",	one(0xF08B),		one(0xF1BF),		"IdBC", mfloat },
+{"fbugtl",	one(0xF08A),		one(0xF1BF),		"IdBC", mfloat },
+{"fbulel",	one(0xF08D),		one(0xF1BF),		"IdBC", mfloat },
+{"fbultl",	one(0xF08C),		one(0xF1BF),		"IdBC", mfloat },
+{"fbunl",	one(0xF088),		one(0xF1BF),		"IdBC", mfloat },
+
+{"fcmpb",	two(0xF000, 0x5838),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fcmpd",	two(0xF000, 0x5438),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fcmpl",	two(0xF000, 0x4038),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fcmpp",	two(0xF000, 0x4C38),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fcmps",	two(0xF000, 0x4438),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fcmpw",	two(0xF000, 0x5038),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fcmpx",	two(0xF000, 0x0038),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fcmpx",	two(0xF000, 0x4838),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fcmpx",	two(0xF000, 0x0038),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF removed */
+
+{"fcosb",	two(0xF000, 0x581D),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fcosd",	two(0xF000, 0x541D),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fcosl",	two(0xF000, 0x401D),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fcosp",	two(0xF000, 0x4C1D),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fcoss",	two(0xF000, 0x441D),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fcosw",	two(0xF000, 0x501D),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fcosx",	two(0xF000, 0x001D),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fcosx",	two(0xF000, 0x481D),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fcosx",	two(0xF000, 0x001D),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fcoshb",	two(0xF000, 0x5819),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fcoshd",	two(0xF000, 0x5419),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fcoshl",	two(0xF000, 0x4019),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fcoshp",	two(0xF000, 0x4C19),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fcoshs",	two(0xF000, 0x4419),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fcoshw",	two(0xF000, 0x5019),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fcoshx",	two(0xF000, 0x0019),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fcoshx",	two(0xF000, 0x4819),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fcoshx",	two(0xF000, 0x0019),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fdbeq",	two(0xF048, 0x0001),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbf",	two(0xF048, 0x0000),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbge",	two(0xF048, 0x0013),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbgl",	two(0xF048, 0x0016),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbgle",	two(0xF048, 0x0017),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbgt",	two(0xF048, 0x0012),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdble",	two(0xF048, 0x0015),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdblt",	two(0xF048, 0x0014),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbne",	two(0xF048, 0x000E),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbnge",	two(0xF048, 0x001C),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbngl",	two(0xF048, 0x0019),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbngle",	two(0xF048, 0x0018),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbngt",	two(0xF048, 0x001D),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbnle",	two(0xF048, 0x001A),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbnlt",	two(0xF048, 0x001B),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdboge",	two(0xF048, 0x0003),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbogl",	two(0xF048, 0x0006),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbogt",	two(0xF048, 0x0002),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbole",	two(0xF048, 0x0005),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbolt",	two(0xF048, 0x0004),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbor",	two(0xF048, 0x0007),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbseq",	two(0xF048, 0x0011),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbsf",	two(0xF048, 0x0010),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbsne",	two(0xF048, 0x001E),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbst",	two(0xF048, 0x001F),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbt",	two(0xF048, 0x000F),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbueq",	two(0xF048, 0x0009),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbuge",	two(0xF048, 0x000B),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbugt",	two(0xF048, 0x000A),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbule",	two(0xF048, 0x000D),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbult",	two(0xF048, 0x000C),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+{"fdbun",	two(0xF048, 0x0008),	two(0xF1F8, 0xFFFF),	"IiDsBw", mfloat },
+
+{"fdivb",	two(0xF000, 0x5820),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fdivd",	two(0xF000, 0x5420),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fdivl",	two(0xF000, 0x4020),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fdivp",	two(0xF000, 0x4C20),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fdivs",	two(0xF000, 0x4420),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fdivw",	two(0xF000, 0x5020),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fdivx",	two(0xF000, 0x0020),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fdivx",	two(0xF000, 0x4820),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fdivx",	two(0xF000, 0x0020),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF */
+
+{"fsdivb",	two(0xF000, 0x5860),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fsdivd",	two(0xF000, 0x5460),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fsdivl",	two(0xF000, 0x4060),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fsdivp",	two(0xF000, 0x4C60),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fsdivs",	two(0xF000, 0x4460),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fsdivw",	two(0xF000, 0x5060),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fsdivx",	two(0xF000, 0x0060),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fsdivx",	two(0xF000, 0x4860),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"fsdivx",	two(0xF000, 0x0060),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 }, JF */
+
+{"fddivb",	two(0xF000, 0x5864),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fddivd",	two(0xF000, 0x5464),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fddivl",	two(0xF000, 0x4064),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fddivp",	two(0xF000, 0x4C64),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fddivs",	two(0xF000, 0x4464),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fddivw",	two(0xF000, 0x5064),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fddivx",	two(0xF000, 0x0064),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fddivx",	two(0xF000, 0x4864),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"fddivx",	two(0xF000, 0x0064),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 }, JF */
+
+{"fetoxb",	two(0xF000, 0x5810),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fetoxd",	two(0xF000, 0x5410),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fetoxl",	two(0xF000, 0x4010),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fetoxp",	two(0xF000, 0x4C10),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fetoxs",	two(0xF000, 0x4410),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fetoxw",	two(0xF000, 0x5010),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fetoxx",	two(0xF000, 0x0010),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fetoxx",	two(0xF000, 0x4810),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fetoxx",	two(0xF000, 0x0010),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fetoxm1b",	two(0xF000, 0x5808),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fetoxm1d",	two(0xF000, 0x5408),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fetoxm1l",	two(0xF000, 0x4008),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fetoxm1p",	two(0xF000, 0x4C08),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fetoxm1s",	two(0xF000, 0x4408),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fetoxm1w",	two(0xF000, 0x5008),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fetoxm1x",	two(0xF000, 0x0008),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fetoxm1x",	two(0xF000, 0x4808),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fetoxm1x",	two(0xF000, 0x0008),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fgetexpb",	two(0xF000, 0x581E),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fgetexpd",	two(0xF000, 0x541E),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fgetexpl",	two(0xF000, 0x401E),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fgetexpp",	two(0xF000, 0x4C1E),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fgetexps",	two(0xF000, 0x441E),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fgetexpw",	two(0xF000, 0x501E),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fgetexpx",	two(0xF000, 0x001E),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fgetexpx",	two(0xF000, 0x481E),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fgetexpx",	two(0xF000, 0x001E),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fgetmanb",	two(0xF000, 0x581F),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fgetmand",	two(0xF000, 0x541F),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fgetmanl",	two(0xF000, 0x401F),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fgetmanp",	two(0xF000, 0x4C1F),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fgetmans",	two(0xF000, 0x441F),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fgetmanw",	two(0xF000, 0x501F),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fgetmanx",	two(0xF000, 0x001F),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fgetmanx",	two(0xF000, 0x481F),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fgetmanx",	two(0xF000, 0x001F),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fintb",	two(0xF000, 0x5801),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fintd",	two(0xF000, 0x5401),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fintl",	two(0xF000, 0x4001),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fintp",	two(0xF000, 0x4C01),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fints",	two(0xF000, 0x4401),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fintw",	two(0xF000, 0x5001),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fintx",	two(0xF000, 0x0001),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fintx",	two(0xF000, 0x4801),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fintx",	two(0xF000, 0x0001),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fintrzb",	two(0xF000, 0x5803),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fintrzd",	two(0xF000, 0x5403),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fintrzl",	two(0xF000, 0x4003),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fintrzp",	two(0xF000, 0x4C03),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fintrzs",	two(0xF000, 0x4403),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fintrzw",	two(0xF000, 0x5003),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fintrzx",	two(0xF000, 0x0003),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fintrzx",	two(0xF000, 0x4803),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fintrzx",	two(0xF000, 0x0003),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"flog10b",	two(0xF000, 0x5815),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"flog10d",	two(0xF000, 0x5415),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"flog10l",	two(0xF000, 0x4015),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"flog10p",	two(0xF000, 0x4C15),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"flog10s",	two(0xF000, 0x4415),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"flog10w",	two(0xF000, 0x5015),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"flog10x",	two(0xF000, 0x0015),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"flog10x",	two(0xF000, 0x4815),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"flog10x",	two(0xF000, 0x0015),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"flog2b",	two(0xF000, 0x5816),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"flog2d",	two(0xF000, 0x5416),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"flog2l",	two(0xF000, 0x4016),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"flog2p",	two(0xF000, 0x4C16),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"flog2s",	two(0xF000, 0x4416),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"flog2w",	two(0xF000, 0x5016),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"flog2x",	two(0xF000, 0x0016),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"flog2x",	two(0xF000, 0x4816),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"flog2x",	two(0xF000, 0x0016),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"flognb",	two(0xF000, 0x5814),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"flognd",	two(0xF000, 0x5414),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"flognl",	two(0xF000, 0x4014),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"flognp",	two(0xF000, 0x4C14),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"flogns",	two(0xF000, 0x4414),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"flognw",	two(0xF000, 0x5014),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"flognx",	two(0xF000, 0x0014),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"flognx",	two(0xF000, 0x4814),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"flognx",	two(0xF000, 0x0014),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"flognp1b",	two(0xF000, 0x5806),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"flognp1d",	two(0xF000, 0x5406),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"flognp1l",	two(0xF000, 0x4006),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"flognp1p",	two(0xF000, 0x4C06),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"flognp1s",	two(0xF000, 0x4406),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"flognp1w",	two(0xF000, 0x5006),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"flognp1x",	two(0xF000, 0x0006),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"flognp1x",	two(0xF000, 0x4806),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"flognp1x",	two(0xF000, 0x0006),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fmodb",	two(0xF000, 0x5821),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fmodd",	two(0xF000, 0x5421),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fmodl",	two(0xF000, 0x4021),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fmodp",	two(0xF000, 0x4C21),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fmods",	two(0xF000, 0x4421),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fmodw",	two(0xF000, 0x5021),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fmodx",	two(0xF000, 0x0021),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fmodx",	two(0xF000, 0x4821),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fmodx",	two(0xF000, 0x0021),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF */
+
+{"fmoveb",	two(0xF000, 0x5800),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmoveb",	two(0xF000, 0x7800),	two(0xF1C0, 0xFC7F),	"IiF7@b", mfloat },		/* fmove from fp<n> to <ea> */
+{"fmoved",	two(0xF000, 0x5400),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmoved",	two(0xF000, 0x7400),	two(0xF1C0, 0xFC7F),	"IiF7@F", mfloat },		/* fmove from fp<n> to <ea> */
+{"fmovel",	two(0xF000, 0x4000),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmovel",	two(0xF000, 0x6000),	two(0xF1C0, 0xFC7F),	"IiF7@l", mfloat },		/* fmove from fp<n> to <ea> */
+/* Warning:  The addressing modes on these are probably not right:
+   esp, Areg direct is only allowed for FPI */
+		/* fmove.l from/to system control registers: */
+{"fmovel",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"Iis8@s", mfloat },
+{"fmovel",	two(0xF000, 0x8000),	two(0xF1C0, 0xE3FF),	"Ii*ls8", mfloat },
+
+/* {"fmovel",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"Iis8@s", mfloat },
+{"fmovel",	two(0xF000, 0x8000),	two(0xF2C0, 0xE3FF),	"Ii*ss8", mfloat }, */
+
+{"fmovep",	two(0xF000, 0x4C00),	two(0xF1C0, 0xFC7F),	"Ii;pF7",   mfloat },		/* fmove from <ea> to fp<n> */
+{"fmovep",	two(0xF000, 0x6C00),	two(0xF1C0, 0xFC00),	"IiF7@pkC", mfloat },		/* fmove.p with k-factors: */
+{"fmovep",	two(0xF000, 0x7C00),	two(0xF1C0, 0xFC0F),	"IiF7@pDk", mfloat },		/* fmove.p with k-factors: */
+
+{"fmoves",	two(0xF000, 0x4400),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmoves",	two(0xF000, 0x6400),	two(0xF1C0, 0xFC7F),	"IiF7@f", mfloat },		/* fmove from fp<n> to <ea> */
+{"fmovew",	two(0xF000, 0x5000),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmovew",	two(0xF000, 0x7000),	two(0xF1C0, 0xFC7F),	"IiF7@w", mfloat },		/* fmove from fp<n> to <ea> */
+{"fmovex",	two(0xF000, 0x0000),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmovex",	two(0xF000, 0x4800),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },		/* fmove from <ea> to fp<n> */
+{"fmovex",	two(0xF000, 0x6800),	two(0xF1C0, 0xFC7F),	"IiF7@x", mfloat },		/* fmove from fp<n> to <ea> */
+/* JF removed {"fmovex",	two(0xF000, 0x0000),	two(0xF1C0, 0xE07F),	"IiFt", mfloat }, / * fmove from <ea> to fp<n> */
+
+{"fsmoveb",	two(0xF000, 0x5840),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmoved",	two(0xF000, 0x5440),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmovel",	two(0xF000, 0x4040),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmoves",	two(0xF000, 0x4440),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmovew",	two(0xF000, 0x5040),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmovex",	two(0xF000, 0x0040),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fsmovex",	two(0xF000, 0x4840),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 }, /* fmove from <ea> to fp<n> */
+/* JF removed {"fsmovex",	two(0xF000, 0x0040),	two(0xF1C0, 0xE07F),	"IiFt", m68040 }, / * fmove from <ea> to fp<n> */
+
+{"fdmoveb",	two(0xF000, 0x5844),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmoved",	two(0xF000, 0x5444),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmovel",	two(0xF000, 0x4044),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmoves",	two(0xF000, 0x4444),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmovew",	two(0xF000, 0x5044),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmovex",	two(0xF000, 0x0044),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 }, /* fmove from <ea> to fp<n> */
+{"fdmovex",	two(0xF000, 0x4844),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 }, /* fmove from <ea> to fp<n> */
+/* JF removed {"fdmovex",	two(0xF000, 0x0044),	two(0xF1C0, 0xE07F),	"IiFt", m68040 }, / * fmove from <ea> to fp<n> */
+
+{"fmovecrx",	two(0xF000, 0x5C00),	two(0xF1FF, 0xFC00),	"Ii#CF7", mfloat },		/* fmovecr.x #ccc, FPn */
+{"fmovecr",	two(0xF000, 0x5C00),	two(0xF1FF, 0xFC00),	"Ii#CF7", mfloat },
+
+/* Other fmovemx.  */
+{"fmovemx", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, /* reg to control,	static and dynamic: */
+{"fmovemx", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, /* from control to reg, static and dynamic: */
+
+{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, /* to control, static and dynamic: */
+{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, /* to control, static and dynamic: */
+
+{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, /* from control, static and dynamic: */
+{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, /* from control, static and dynamic: */
+
+{"fmovemx", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, /* reg to autodecrement, static and dynamic */
+{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, /* to autodecrement, static and dynamic */
+{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, /* to autodecrement, static and dynamic */
+
+{"fmovemx", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, /* from autoinc to reg, static and dynamic: */
+{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, /* from autoincrement, static and dynamic: */
+{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, /* from autoincrement, static and dynamic: */
+
+{"fmoveml",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"IiL8@s", mfloat },
+{"fmoveml",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"Ii#8@s", mfloat },
+{"fmoveml",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"Iis8@s", mfloat },
+
+{"fmoveml",	two(0xF000, 0x8000),	two(0xF2C0, 0xE3FF),	"Ii*sL8", mfloat },
+{"fmoveml",	two(0xF000, 0x8000),	two(0xF1C0, 0xE3FF),	"Ii*s#8", mfloat },
+{"fmoveml",	two(0xF000, 0x8000),	two(0xF1C0, 0xE3FF),	"Ii*ss8", mfloat },
+
+/* fmovemx with register lists */
+{"fmovem",	two(0xF020, 0xE000),	two(0xF1F8, 0xFF00),	"IdL3-s", mfloat }, /* to autodec, static & dynamic */
+{"fmovem",	two(0xF000, 0xF000),	two(0xF1C0, 0xFF00),	"Idl3&s", mfloat }, /* to control, static and dynamic */
+{"fmovem",	two(0xF018, 0xD000),	two(0xF1F8, 0xFF00),	"Id+sl3", mfloat }, /* from autoinc, static & dynamic */
+{"fmovem",	two(0xF000, 0xD000),	two(0xF1C0, 0xFF00),	"Id&sl3", mfloat }, /* from control, static and dynamic */
+
+	/* Alternate mnemonics for GNU as and GNU CC */
+{"fmovem",	two(0xF020, 0xE000),	two(0xF1F8, 0xFF00),	"Id#3-s", mfloat }, /* to autodecrement, static and dynamic */
+{"fmovem",	two(0xF020, 0xE800),	two(0xF1F8, 0xFF8F),	"IiDk-s", mfloat }, /* to autodecrement, static and dynamic */
+
+{"fmovem",	two(0xF000, 0xF000),	two(0xF1C0, 0xFF00),	"Id#3&s", mfloat }, /* to control, static and dynamic: */
+{"fmovem",	two(0xF000, 0xF800),	two(0xF1C0, 0xFF8F),	"IiDk&s", mfloat }, /* to control, static and dynamic: */
+
+{"fmovem",	two(0xF018, 0xD000),	two(0xF1F8, 0xFF00),	"Id+s#3", mfloat }, /* from autoincrement, static and dynamic: */
+{"fmovem",	two(0xF018, 0xD800),	two(0xF1F8, 0xFF8F),	"Ii+sDk", mfloat }, /* from autoincrement, static and dynamic: */
+  
+{"fmovem",	two(0xF000, 0xD000),	two(0xF1C0, 0xFF00),	"Id&s#3", mfloat }, /* from control, static and dynamic: */
+{"fmovem",	two(0xF000, 0xD800),	two(0xF1C0, 0xFF8F),	"Ii&sDk", mfloat }, /* from control, static and dynamic: */
+
+/* fmoveml a FP-control register */
+{"fmovem",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"Iis8@s", mfloat },
+{"fmovem",	two(0xF000, 0x8000),	two(0xF1C0, 0xE3FF),	"Ii*ss8", mfloat },
+
+/* fmoveml a FP-control reglist */
+{"fmovem",	two(0xF000, 0xA000),	two(0xF1C0, 0xE3FF),	"IiL8@s", mfloat },
+{"fmovem",	two(0xF000, 0x8000),	two(0xF2C0, 0xE3FF),	"Ii*sL8", mfloat },
+
+{"fmulb",	two(0xF000, 0x5823),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fmuld",	two(0xF000, 0x5423),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fmull",	two(0xF000, 0x4023),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fmulp",	two(0xF000, 0x4C23),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fmuls",	two(0xF000, 0x4423),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fmulw",	two(0xF000, 0x5023),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fmulx",	two(0xF000, 0x0023),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fmulx",	two(0xF000, 0x4823),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fmulx",	two(0xF000, 0x0023),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF */
+
+{"fsmulb",	two(0xF000, 0x5863),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fsmuld",	two(0xF000, 0x5463),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fsmull",	two(0xF000, 0x4063),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fsmulp",	two(0xF000, 0x4C63),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fsmuls",	two(0xF000, 0x4463),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fsmulw",	two(0xF000, 0x5063),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fsmulx",	two(0xF000, 0x0063),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fsmulx",	two(0xF000, 0x4863),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"fsmulx",	two(0xF000, 0x0063),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 }, JF */
+
+{"fdmulb",	two(0xF000, 0x5867),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fdmuld",	two(0xF000, 0x5467),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fdmull",	two(0xF000, 0x4067),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fdmulp",	two(0xF000, 0x4C67),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fdmuls",	two(0xF000, 0x4467),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fdmulw",	two(0xF000, 0x5067),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fdmulx",	two(0xF000, 0x0067),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fdmulx",	two(0xF000, 0x4867),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+/* {"dfmulx",	two(0xF000, 0x0067),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 }, JF */
+
+{"fnegb",	two(0xF000, 0x581A),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fnegd",	two(0xF000, 0x541A),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fnegl",	two(0xF000, 0x401A),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fnegp",	two(0xF000, 0x4C1A),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fnegs",	two(0xF000, 0x441A),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fnegw",	two(0xF000, 0x501A),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fnegx",	two(0xF000, 0x001A),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fnegx",	two(0xF000, 0x481A),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fnegx",	two(0xF000, 0x001A),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fsnegb",	two(0xF000, 0x585A),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fsnegd",	two(0xF000, 0x545A),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fsnegl",	two(0xF000, 0x405A),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fsnegp",	two(0xF000, 0x4C5A),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fsnegs",	two(0xF000, 0x445A),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fsnegw",	two(0xF000, 0x505A),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fsnegx",	two(0xF000, 0x005A),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fsnegx",	two(0xF000, 0x485A),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fsnegx",	two(0xF000, 0x005A),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fdnegb",	two(0xF000, 0x585E),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fdnegd",	two(0xF000, 0x545E),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fdnegl",	two(0xF000, 0x405E),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fdnegp",	two(0xF000, 0x4C5E),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fdnegs",	two(0xF000, 0x445E),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fdnegw",	two(0xF000, 0x505E),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fdnegx",	two(0xF000, 0x005E),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fdnegx",	two(0xF000, 0x485E),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fdnegx",	two(0xF000, 0x005E),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fnop",	two(0xF280, 0x0000),	two(0xFFFF, 0xFFFF),	"Ii", mfloat },
+
+{"fremb",	two(0xF000, 0x5825),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fremd",	two(0xF000, 0x5425),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"freml",	two(0xF000, 0x4025),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fremp",	two(0xF000, 0x4C25),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"frems",	two(0xF000, 0x4425),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fremw",	two(0xF000, 0x5025),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fremx",	two(0xF000, 0x0025),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fremx",	two(0xF000, 0x4825),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fremx",	two(0xF000, 0x0025),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF */
+
+{"frestore",	one(0xF140),		one(0xF1C0),		"Id&s", mfloat },
+{"frestore",	one(0xF158),		one(0xF1F8),		"Id+s", mfloat },
+{"fsave",	one(0xF100),		one(0xF1C0),		"Id&s", mfloat },
+{"fsave",	one(0xF120),		one(0xF1F8),		"Id-s", mfloat },
+
+{"fscaleb",	two(0xF000, 0x5826),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fscaled",	two(0xF000, 0x5426),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fscalel",	two(0xF000, 0x4026),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fscalep",	two(0xF000, 0x4C26),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fscales",	two(0xF000, 0x4426),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fscalew",	two(0xF000, 0x5026),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fscalex",	two(0xF000, 0x0026),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fscalex",	two(0xF000, 0x4826),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+/* {"fscalex",	two(0xF000, 0x0026),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat }, JF */
+
+/* $ is necessary to prevent the assembler from using PC-relative.
+   If @ were used, "label: fseq label" could produce "ftrapeq",
+   because "label" became "pc@label".  */
+{"fseq",	two(0xF040, 0x0001),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsf",		two(0xF040, 0x0000),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsge",	two(0xF040, 0x0013),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsgl",	two(0xF040, 0x0016),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsgle",	two(0xF040, 0x0017),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsgt",	two(0xF040, 0x0012),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsle",	two(0xF040, 0x0015),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fslt",	two(0xF040, 0x0014),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsne",	two(0xF040, 0x000E),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsnge",	two(0xF040, 0x001C),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsngl",	two(0xF040, 0x0019),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsngle",	two(0xF040, 0x0018),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsngt",	two(0xF040, 0x001D),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsnle",	two(0xF040, 0x001A),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsnlt",	two(0xF040, 0x001B),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsoge",	two(0xF040, 0x0003),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsogl",	two(0xF040, 0x0006),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsogt",	two(0xF040, 0x0002),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsole",	two(0xF040, 0x0005),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsolt",	two(0xF040, 0x0004),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsor",	two(0xF040, 0x0007),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsseq",	two(0xF040, 0x0011),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fssf",	two(0xF040, 0x0010),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fssne",	two(0xF040, 0x001E),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsst",	two(0xF040, 0x001F),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fst",		two(0xF040, 0x000F),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsueq",	two(0xF040, 0x0009),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsuge",	two(0xF040, 0x000B),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsugt",	two(0xF040, 0x000A),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsule",	two(0xF040, 0x000D),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsult",	two(0xF040, 0x000C),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+{"fsun",	two(0xF040, 0x0008),	two(0xF1C0, 0xFFFF),	"Ii$s", mfloat },
+
+{"fsgldivb",	two(0xF000, 0x5824),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsgldivd",	two(0xF000, 0x5424),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsgldivl",	two(0xF000, 0x4024),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsgldivp",	two(0xF000, 0x4C24),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsgldivs",	two(0xF000, 0x4424),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsgldivw",	two(0xF000, 0x5024),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsgldivx",	two(0xF000, 0x0024),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsgldivx",	two(0xF000, 0x4824),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsgldivx",	two(0xF000, 0x0024),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fsglmulb",	two(0xF000, 0x5827),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsglmuld",	two(0xF000, 0x5427),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsglmull",	two(0xF000, 0x4027),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsglmulp",	two(0xF000, 0x4C27),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsglmuls",	two(0xF000, 0x4427),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsglmulw",	two(0xF000, 0x5027),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsglmulx",	two(0xF000, 0x0027),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsglmulx",	two(0xF000, 0x4827),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsglmulx",	two(0xF000, 0x0027),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fsinb",	two(0xF000, 0x580E),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsind",	two(0xF000, 0x540E),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsinl",	two(0xF000, 0x400E),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsinp",	two(0xF000, 0x4C0E),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsins",	two(0xF000, 0x440E),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsinw",	two(0xF000, 0x500E),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsinx",	two(0xF000, 0x000E),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsinx",	two(0xF000, 0x480E),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsinx",	two(0xF000, 0x000E),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fsinhb",	two(0xF000, 0x5802),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsinhd",	two(0xF000, 0x5402),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsinhl",	two(0xF000, 0x4002),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsinhp",	two(0xF000, 0x4C02),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsinhs",	two(0xF000, 0x4402),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsinhw",	two(0xF000, 0x5002),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsinhx",	two(0xF000, 0x0002),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsinhx",	two(0xF000, 0x4802),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsinhx",	two(0xF000, 0x0002),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fsincosb",	two(0xF000, 0x5830),	two(0xF1C0, 0xFC78),	"Ii;bF3F7", mfloat },
+{"fsincosd",	two(0xF000, 0x5430),	two(0xF1C0, 0xFC78),	"Ii;FF3F7", mfloat },
+{"fsincosl",	two(0xF000, 0x4030),	two(0xF1C0, 0xFC78),	"Ii;lF3F7", mfloat },
+{"fsincosp",	two(0xF000, 0x4C30),	two(0xF1C0, 0xFC78),	"Ii;pF3F7", mfloat },
+{"fsincoss",	two(0xF000, 0x4430),	two(0xF1C0, 0xFC78),	"Ii;fF3F7", mfloat },
+{"fsincosw",	two(0xF000, 0x5030),	two(0xF1C0, 0xFC78),	"Ii;wF3F7", mfloat },
+{"fsincosx",	two(0xF000, 0x0030),	two(0xF1C0, 0xE078),	"IiF8F3F7", mfloat },
+{"fsincosx",	two(0xF000, 0x4830),	two(0xF1C0, 0xFC78),	"Ii;xF3F7", mfloat },
+
+{"fsqrtb",	two(0xF000, 0x5804),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsqrtd",	two(0xF000, 0x5404),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsqrtl",	two(0xF000, 0x4004),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsqrtp",	two(0xF000, 0x4C04),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsqrts",	two(0xF000, 0x4404),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsqrtw",	two(0xF000, 0x5004),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsqrtx",	two(0xF000, 0x0004),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsqrtx",	two(0xF000, 0x4804),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsqrtx",	two(0xF000, 0x0004),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fssqrtb",	two(0xF000, 0x5841),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fssqrtd",	two(0xF000, 0x5441),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fssqrtl",	two(0xF000, 0x4041),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fssqrtp",	two(0xF000, 0x4C41),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fssqrts",	two(0xF000, 0x4441),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fssqrtw",	two(0xF000, 0x5041),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fssqrtx",	two(0xF000, 0x0041),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fssqrtx",	two(0xF000, 0x4841),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fssqrtx",	two(0xF000, 0x0041),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fdsqrtb",	two(0xF000, 0x5845),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fdsqrtd",	two(0xF000, 0x5445),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fdsqrtl",	two(0xF000, 0x4045),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fdsqrtp",	two(0xF000, 0x4C45),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fdsqrts",	two(0xF000, 0x4445),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fdsqrtw",	two(0xF000, 0x5045),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fdsqrtx",	two(0xF000, 0x0045),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fdsqrtx",	two(0xF000, 0x4845),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fdsqrtx",	two(0xF000, 0x0045),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fsubb",	two(0xF000, 0x5828),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"fsubd",	two(0xF000, 0x5428),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"fsubl",	two(0xF000, 0x4028),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"fsubp",	two(0xF000, 0x4C28),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"fsubs",	two(0xF000, 0x4428),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"fsubw",	two(0xF000, 0x5028),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"fsubx",	two(0xF000, 0x0028),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"fsubx",	two(0xF000, 0x4828),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"fsubx",	two(0xF000, 0x0028),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"fssubb",	two(0xF000, 0x5868),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fssubd",	two(0xF000, 0x5468),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fssubl",	two(0xF000, 0x4068),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fssubp",	two(0xF000, 0x4C68),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fssubs",	two(0xF000, 0x4468),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fssubw",	two(0xF000, 0x5068),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fssubx",	two(0xF000, 0x0068),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fssubx",	two(0xF000, 0x4868),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fssubx",	two(0xF000, 0x0068),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"fdsubb",	two(0xF000, 0x586c),	two(0xF1C0, 0xFC7F),	"Ii;bF7", m68040 },
+{"fdsubd",	two(0xF000, 0x546c),	two(0xF1C0, 0xFC7F),	"Ii;FF7", m68040 },
+{"fdsubl",	two(0xF000, 0x406c),	two(0xF1C0, 0xFC7F),	"Ii;lF7", m68040 },
+{"fdsubp",	two(0xF000, 0x4C6c),	two(0xF1C0, 0xFC7F),	"Ii;pF7", m68040 },
+{"fdsubs",	two(0xF000, 0x446c),	two(0xF1C0, 0xFC7F),	"Ii;fF7", m68040 },
+{"fdsubw",	two(0xF000, 0x506c),	two(0xF1C0, 0xFC7F),	"Ii;wF7", m68040 },
+{"fdsubx",	two(0xF000, 0x006c),	two(0xF1C0, 0xE07F),	"IiF8F7", m68040 },
+{"fdsubx",	two(0xF000, 0x486c),	two(0xF1C0, 0xFC7F),	"Ii;xF7", m68040 },
+{"fdsubx",	two(0xF000, 0x006c),	two(0xF1C0, 0xE07F),	"IiFt",   m68040 },
+
+{"ftanb",	two(0xF000, 0x580F),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"ftand",	two(0xF000, 0x540F),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"ftanl",	two(0xF000, 0x400F),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"ftanp",	two(0xF000, 0x4C0F),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"ftans",	two(0xF000, 0x440F),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"ftanw",	two(0xF000, 0x500F),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"ftanx",	two(0xF000, 0x000F),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"ftanx",	two(0xF000, 0x480F),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"ftanx",	two(0xF000, 0x000F),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"ftanhb",	two(0xF000, 0x5809),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"ftanhd",	two(0xF000, 0x5409),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"ftanhl",	two(0xF000, 0x4009),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"ftanhp",	two(0xF000, 0x4C09),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"ftanhs",	two(0xF000, 0x4409),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"ftanhw",	two(0xF000, 0x5009),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"ftanhx",	two(0xF000, 0x0009),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"ftanhx",	two(0xF000, 0x4809),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"ftanhx",	two(0xF000, 0x0009),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"ftentoxb",	two(0xF000, 0x5812),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"ftentoxd",	two(0xF000, 0x5412),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"ftentoxl",	two(0xF000, 0x4012),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"ftentoxp",	two(0xF000, 0x4C12),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"ftentoxs",	two(0xF000, 0x4412),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"ftentoxw",	two(0xF000, 0x5012),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"ftentoxx",	two(0xF000, 0x0012),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"ftentoxx",	two(0xF000, 0x4812),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"ftentoxx",	two(0xF000, 0x0012),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+{"ftrapeq",	two(0xF07C, 0x0001),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapf",	two(0xF07C, 0x0000),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapge",	two(0xF07C, 0x0013),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapgl",	two(0xF07C, 0x0016),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapgle",	two(0xF07C, 0x0017),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapgt",	two(0xF07C, 0x0012),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftraple",	two(0xF07C, 0x0015),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftraplt",	two(0xF07C, 0x0014),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapne",	two(0xF07C, 0x000E),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapnge",	two(0xF07C, 0x001C),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapngl",	two(0xF07C, 0x0019),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapngle",	two(0xF07C, 0x0018),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapngt",	two(0xF07C, 0x001D),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapnle",	two(0xF07C, 0x001A),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapnlt",	two(0xF07C, 0x001B),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapoge",	two(0xF07C, 0x0003),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapogl",	two(0xF07C, 0x0006),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapogt",	two(0xF07C, 0x0002),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapole",	two(0xF07C, 0x0005),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapolt",	two(0xF07C, 0x0004),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapor",	two(0xF07C, 0x0007),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapseq",	two(0xF07C, 0x0011),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapsf",	two(0xF07C, 0x0010),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapsne",	two(0xF07C, 0x001E),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapst",	two(0xF07C, 0x001F),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapt",	two(0xF07C, 0x000F),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapueq",	two(0xF07C, 0x0009),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapuge",	two(0xF07C, 0x000B),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapugt",	two(0xF07C, 0x000A),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapule",	two(0xF07C, 0x000D),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapult",	two(0xF07C, 0x000C),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+{"ftrapun",	two(0xF07C, 0x0008),	two(0xF1FF, 0xFFFF),	"Ii", mfloat },
+        
+{"ftrapeqw",	two(0xF07A, 0x0001),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapfw",	two(0xF07A, 0x0000),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapgew",	two(0xF07A, 0x0013),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapglw",	two(0xF07A, 0x0016),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapglew",	two(0xF07A, 0x0017),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapgtw",	two(0xF07A, 0x0012),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftraplew",	two(0xF07A, 0x0015),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapltw",	two(0xF07A, 0x0014),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapnew",	two(0xF07A, 0x000E),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapngew",	two(0xF07A, 0x001C),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapnglw",	two(0xF07A, 0x0019),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapnglew",	two(0xF07A, 0x0018),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapngtw",	two(0xF07A, 0x001D),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapnlew",	two(0xF07A, 0x001A),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapnltw",	two(0xF07A, 0x001B),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapogew",	two(0xF07A, 0x0003),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapoglw",	two(0xF07A, 0x0006),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapogtw",	two(0xF07A, 0x0002),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapolew",	two(0xF07A, 0x0005),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapoltw",	two(0xF07A, 0x0004),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftraporw",	two(0xF07A, 0x0007),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapseqw",	two(0xF07A, 0x0011),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapsfw",	two(0xF07A, 0x0010),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapsnew",	two(0xF07A, 0x001E),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapstw",	two(0xF07A, 0x001F),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftraptw",	two(0xF07A, 0x000F),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapueqw",	two(0xF07A, 0x0009),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapugew",	two(0xF07A, 0x000B),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapugtw",	two(0xF07A, 0x000A),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapulew",	two(0xF07A, 0x000D),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapultw",	two(0xF07A, 0x000C),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+{"ftrapunw",	two(0xF07A, 0x0008),	two(0xF1FF, 0xFFFF),	"Ii^w", mfloat },
+
+{"ftrapeql",	two(0xF07B, 0x0001),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapfl",	two(0xF07B, 0x0000),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapgel",	two(0xF07B, 0x0013),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapgll",	two(0xF07B, 0x0016),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapglel",	two(0xF07B, 0x0017),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapgtl",	two(0xF07B, 0x0012),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftraplel",	two(0xF07B, 0x0015),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapltl",	two(0xF07B, 0x0014),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapnel",	two(0xF07B, 0x000E),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapngel",	two(0xF07B, 0x001C),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapngll",	two(0xF07B, 0x0019),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapnglel",	two(0xF07B, 0x0018),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapngtl",	two(0xF07B, 0x001D),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapnlel",	two(0xF07B, 0x001A),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapnltl",	two(0xF07B, 0x001B),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapogel",	two(0xF07B, 0x0003),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapogll",	two(0xF07B, 0x0006),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapogtl",	two(0xF07B, 0x0002),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapolel",	two(0xF07B, 0x0005),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapoltl",	two(0xF07B, 0x0004),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftraporl",	two(0xF07B, 0x0007),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapseql",	two(0xF07B, 0x0011),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapsfl",	two(0xF07B, 0x0010),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapsnel",	two(0xF07B, 0x001E),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapstl",	two(0xF07B, 0x001F),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftraptl",	two(0xF07B, 0x000F),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapueql",	two(0xF07B, 0x0009),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapugel",	two(0xF07B, 0x000B),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapugtl",	two(0xF07B, 0x000A),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapulel",	two(0xF07B, 0x000D),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapultl",	two(0xF07B, 0x000C),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+{"ftrapunl",	two(0xF07B, 0x0008),	two(0xF1FF, 0xFFFF),	"Ii^l", mfloat },
+
+{"ftstb",	two(0xF000, 0x583A),	two(0xF1C0, 0xFC7F),	"Ii;b", mfloat },
+{"ftstd",	two(0xF000, 0x543A),	two(0xF1C0, 0xFC7F),	"Ii;F", mfloat },
+{"ftstl",	two(0xF000, 0x403A),	two(0xF1C0, 0xFC7F),	"Ii;l", mfloat },
+{"ftstp",	two(0xF000, 0x4C3A),	two(0xF1C0, 0xFC7F),	"Ii;p", mfloat },
+{"ftsts",	two(0xF000, 0x443A),	two(0xF1C0, 0xFC7F),	"Ii;f", mfloat },
+{"ftstw",	two(0xF000, 0x503A),	two(0xF1C0, 0xFC7F),	"Ii;w", mfloat },
+{"ftstx",	two(0xF000, 0x003A),	two(0xF1C0, 0xE07F),	"IiF8", mfloat },
+{"ftstx",	two(0xF000, 0x483A),	two(0xF1C0, 0xFC7F),	"Ii;x", mfloat },
+
+{"ftwotoxb",	two(0xF000, 0x5811),	two(0xF1C0, 0xFC7F),	"Ii;bF7", mfloat },
+{"ftwotoxd",	two(0xF000, 0x5411),	two(0xF1C0, 0xFC7F),	"Ii;FF7", mfloat },
+{"ftwotoxl",	two(0xF000, 0x4011),	two(0xF1C0, 0xFC7F),	"Ii;lF7", mfloat },
+{"ftwotoxp",	two(0xF000, 0x4C11),	two(0xF1C0, 0xFC7F),	"Ii;pF7", mfloat },
+{"ftwotoxs",	two(0xF000, 0x4411),	two(0xF1C0, 0xFC7F),	"Ii;fF7", mfloat },
+{"ftwotoxw",	two(0xF000, 0x5011),	two(0xF1C0, 0xFC7F),	"Ii;wF7", mfloat },
+{"ftwotoxx",	two(0xF000, 0x0011),	two(0xF1C0, 0xE07F),	"IiF8F7", mfloat },
+{"ftwotoxx",	two(0xF000, 0x4811),	two(0xF1C0, 0xFC7F),	"Ii;xF7", mfloat },
+{"ftwotoxx",	two(0xF000, 0x0011),	two(0xF1C0, 0xE07F),	"IiFt",   mfloat },
+
+/* Variable-sized float branches */
+
+{"fjeq",	one(0xF081),		one(0xF1FF),		"IdBc", mfloat },
+{"fjf",		one(0xF080),		one(0xF1FF),		"IdBc", mfloat },
+{"fjge",	one(0xF093),		one(0xF1FF),		"IdBc", mfloat },
+{"fjgl",	one(0xF096),		one(0xF1FF),		"IdBc", mfloat },
+{"fjgle",	one(0xF097),		one(0xF1FF),		"IdBc", mfloat },
+{"fjgt",	one(0xF092),		one(0xF1FF),		"IdBc", mfloat },
+{"fjle",	one(0xF095),		one(0xF1FF),		"IdBc", mfloat },
+{"fjlt",	one(0xF094),		one(0xF1FF),		"IdBc", mfloat },
+{"fjne",	one(0xF08E),		one(0xF1FF),		"IdBc", mfloat },
+{"fjnge",	one(0xF09C),		one(0xF1FF),		"IdBc", mfloat },
+{"fjngl",	one(0xF099),		one(0xF1FF),		"IdBc", mfloat },
+{"fjngle",	one(0xF098),		one(0xF1FF),		"IdBc", mfloat },
+{"fjngt",	one(0xF09D),		one(0xF1FF),		"IdBc", mfloat },
+{"fjnle",	one(0xF09A),		one(0xF1FF),		"IdBc", mfloat },
+{"fjnlt",	one(0xF09B),		one(0xF1FF),		"IdBc", mfloat },
+{"fjoge",	one(0xF083),		one(0xF1FF),		"IdBc", mfloat },
+{"fjogl",	one(0xF086),		one(0xF1FF),		"IdBc", mfloat },
+{"fjogt",	one(0xF082),		one(0xF1FF),		"IdBc", mfloat },
+{"fjole",	one(0xF085),		one(0xF1FF),		"IdBc", mfloat },
+{"fjolt",	one(0xF084),		one(0xF1FF),		"IdBc", mfloat },
+{"fjor",	one(0xF087),		one(0xF1FF),		"IdBc", mfloat },
+{"fjseq",	one(0xF091),		one(0xF1FF),		"IdBc", mfloat },
+{"fjsf",	one(0xF090),		one(0xF1FF),		"IdBc", mfloat },
+{"fjsne",	one(0xF09E),		one(0xF1FF),		"IdBc", mfloat },
+{"fjst",	one(0xF09F),		one(0xF1FF),		"IdBc", mfloat },
+{"fjt",		one(0xF08F),		one(0xF1FF),		"IdBc", mfloat },
+{"fjueq",	one(0xF089),		one(0xF1FF),		"IdBc", mfloat },
+{"fjuge",	one(0xF08B),		one(0xF1FF),		"IdBc", mfloat },
+{"fjugt",	one(0xF08A),		one(0xF1FF),		"IdBc", mfloat },
+{"fjule",	one(0xF08D),		one(0xF1FF),		"IdBc", mfloat },
+{"fjult",	one(0xF08C),		one(0xF1FF),		"IdBc", mfloat },
+{"fjun",	one(0xF088),		one(0xF1FF),		"IdBc", mfloat },
+/* float stuff ends here */
+
+{"illegal",	one(0045374),		one(0177777),		"",     m68000up },
+{"jmp",		one(0047300),		one(0177700),		"!s",   m68000up },
+{"jsr",		one(0047200),		one(0177700),		"!s",   m68000up },
+{"lea",		one(0040700),		one(0170700),		"!sAd", m68000up },
+{"linkw",	one(0047120),		one(0177770),		"As#w", m68000up },
+{"linkl",	one(0044010),		one(0177770),		"As#l", m68020up },
+{"link",	one(0047120),		one(0177770),		"As#w", m68000up },
+{"link",	one(0044010),		one(0177770),		"As#l", m68020up },
+
+{"lslb",	one(0160410),		one(0170770),		"QdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lslb",	one(0160450),		one(0170770),		"DdDs", m68000up },	/* lsrb Dd,	Ds */
+{"lslw",	one(0160510),		one(0170770),		"QdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lslw",	one(0160550),		one(0170770),		"DdDs", m68000up },	/* lsrb Dd,	Ds */
+{"lslw",	one(0161700),		one(0177700),		"~s",   m68000up },	/* Shift memory */
+{"lsll",	one(0160610),		one(0170770),		"QdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lsll",	one(0160650),		one(0170770),		"DdDs", m68000up },	/* lsrb Dd,	Ds */
+
+{"lsrb",	one(0160010),		one(0170770),		"QdDs", m68000up }, /* lsrb #Q,	Ds */
+{"lsrb",	one(0160050),		one(0170770),		"DdDs", m68000up },	/* lsrb Dd,	Ds */
+{"lsrl",	one(0160210),		one(0170770),		"QdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lsrl",	one(0160250),		one(0170770),		"DdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lsrw",	one(0160110),		one(0170770),		"QdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lsrw",	one(0160150),		one(0170770),		"DdDs", m68000up },	/* lsrb #Q,	Ds */
+{"lsrw",	one(0161300),		one(0177700),		"~s",   m68000up },	/* Shift memory */
+
+{"moveal",	one(0020100),		one(0170700),		"*lAd", m68000up },
+{"moveaw",	one(0030100),		one(0170700),		"*wAd", m68000up },
+{"moveb",	one(0010000),		one(0170000),		";b$d", m68000up },	/* move */
+{"movel",	one(0070000),		one(0170400),		"MsDd", m68000up },	/* moveq written as move */
+{"movel",	one(0020000),		one(0170000),		"*l$d", m68000up },
+{"movel",	one(0020100),		one(0170700),		"*lAd", m68000up },
+{"movel",	one(0047140),		one(0177770),		"AsUd", m68000up },	/* move to USP */
+{"movel",	one(0047150),		one(0177770),		"UdAs", m68000up },	/* move from USP */
+
+{"movec",	one(0047173),		one(0177777),		"R1Jj", m68010up },
+{"movec",	one(0047173),		one(0177777),		"R1#j", m68010up },
+{"movec",	one(0047172),		one(0177777),		"JjR1", m68010up },
+{"movec",	one(0047172),		one(0177777),		"#jR1", m68010up },
+
+/* JF added these next four for the assembler */
+{"moveml",	one(0044300),		one(0177700),		"Lw&s", m68000up },	/* movem reg to mem. */
+{"moveml",	one(0044340),		one(0177770),		"lw-s", m68000up },	/* movem reg to autodecrement. */
+{"moveml",	one(0046300),		one(0177700),		"!sLw", m68000up },	/* movem mem to reg. */
+{"moveml",	one(0046330),		one(0177770),		"+sLw", m68000up },	/* movem autoinc to reg. */
+
+{"moveml",	one(0044300),		one(0177700),		"#w&s", m68000up },	/* movem reg to mem. */
+{"moveml",	one(0044340),		one(0177770),		"#w-s", m68000up },	/* movem reg to autodecrement. */
+{"moveml",	one(0046300),		one(0177700),		"!s#w", m68000up },	/* movem mem to reg. */
+{"moveml",	one(0046330),		one(0177770),		"+s#w", m68000up },	/* movem autoinc to reg. */
+
+/* JF added these next four for the assembler */
+{"movemw",	one(0044200),		one(0177700),		"Lw&s", m68000up },	/* movem reg to mem. */
+{"movemw",	one(0044240),		one(0177770),		"lw-s", m68000up },	/* movem reg to autodecrement. */
+{"movemw",	one(0046200),		one(0177700),		"!sLw", m68000up },	/* movem mem to reg. */
+{"movemw",	one(0046230),		one(0177770),		"+sLw", m68000up },	/* movem autoinc to reg. */
+
+{"movemw",	one(0044200),		one(0177700),		"#w&s", m68000up },	/* movem reg to mem. */
+{"movemw",	one(0044240),		one(0177770),		"#w-s", m68000up },	/* movem reg to autodecrement. */
+{"movemw",	one(0046200),		one(0177700),		"!s#w", m68000up },	/* movem mem to reg. */
+{"movemw",	one(0046230),		one(0177770),		"+s#w", m68000up },	/* movem autoinc to reg. */
+
+{"movepl",	one(0000510),		one(0170770),		"dsDd", m68000up },	/* memory to register */
+{"movepl",	one(0000710),		one(0170770),		"Ddds", m68000up },	/* register to memory */
+{"movepw",	one(0000410),		one(0170770),		"dsDd", m68000up },	/* memory to register */
+{"movepw",	one(0000610),		one(0170770),		"Ddds", m68000up },	/* register to memory */
+{"moveq",	one(0070000),		one(0170400),		"MsDd", m68000up },
+{"movew",	one(0030000),		one(0170000),		"*w$d", m68000up },
+{"movew",	one(0030100),		one(0170700),		"*wAd", m68000up },	/* movea,	written as move */
+{"movew",	one(0040300),		one(0177700),		"Ss$s", m68000up },	/* Move from sr */
+{"movew",	one(0041300),		one(0177700),		"Cs$s", m68010up },	/* Move from ccr */
+{"movew",	one(0042300),		one(0177700),		";wCd", m68000up },	/* move to ccr */
+{"movew",	one(0043300),		one(0177700),		";wSd", m68000up },	/* move to sr */
+
+{"movesb",	two(0007000, 0),	two(0177700, 07777),	"~sR1", m68010up },	 /* moves from memory */
+{"movesb",	two(0007000, 04000),	two(0177700, 07777),	"R1~s", m68010up },	 /* moves to memory */
+{"movesl",	two(0007200, 0),	two(0177700, 07777),	"~sR1", m68010up },	 /* moves from memory */
+{"movesl",	two(0007200, 04000),	two(0177700, 07777),	"R1~s", m68010up },	 /* moves to memory */
+{"movesw",	two(0007100, 0),	two(0177700, 07777),	"~sR1", m68010up },	 /* moves from memory */
+{"movesw",	two(0007100, 04000),	two(0177700, 07777),	"R1~s", m68010up },	 /* moves to memory */
+
+{"move16",	two(0xf620, 0x8000),	two(0xfff8, 0x8fff),	"+s+1", m68040 },
+{"move16",	one(0xf600),	one(0xfff8),	"+s_L", m68040 },
+{"move16",	one(0xf608),	one(0xfff8),	"_L+s", m68040 },
+{"move16",	one(0xf610),	one(0xfff8),	"as_L", m68040 },
+{"move16",	one(0xf618),	one(0xfff8),	"_Las", m68040 },
+
+{"mulsl",	two(0046000, 004000),	two(0177700, 0107770),	";lD1", m68020up },
+{"mulsl",	two(0046000, 006000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"mulsw",	one(0140700),		one(0170700),		";wDd", m68000up },
+{"muls",	one(0140700),		one(0170700),		";wDd", m68000up },
+{"mulul",	two(0046000, 000000),	two(0177700, 0107770),	";lD1", m68020up },
+{"mulul",	two(0046000, 002000),	two(0177700, 0107770),	";lD3D1", m68020up },
+{"muluw",	one(0140300),		one(0170700),		";wDd", m68000up },
+{"mulu",	one(0140300),		one(0170700),		";wDd", m68000up },
+{"nbcd",	one(0044000),		one(0177700),		"$s", m68000up },
+{"negb",	one(0042000),		one(0177700),		"$s", m68000up },
+{"negl",	one(0042200),		one(0177700),		"$s", m68000up },
+{"negw",	one(0042100),		one(0177700),		"$s", m68000up },
+{"negxb",	one(0040000),		one(0177700),		"$s", m68000up },
+{"negxl",	one(0040200),		one(0177700),		"$s", m68000up },
+{"negxw",	one(0040100),		one(0177700),		"$s", m68000up },
+{"nop",		one(0047161),		one(0177777),		"", m68000up },
+{"notb",	one(0043000),		one(0177700),		"$s", m68000up },
+{"notl",	one(0043200),		one(0177700),		"$s", m68000up },
+{"notw",	one(0043100),		one(0177700),		"$s", m68000up },
+
+{"orb",		one(0000000),		one(0177700),		"#b$s", m68000up },	/* ori written as or */
+{"orb",		one(0000074),		one(0177777),		"#bCs", m68000up },	/* ori to ccr */
+{"orb",		one(0100000),		one(0170700),		";bDd", m68000up },	/* memory to register */
+{"orb",		one(0100400),		one(0170700),		"Dd~s", m68000up },	/* register to memory */
+{"orib",	one(0000000),		one(0177700),		"#b$s", m68000up },
+{"orib",	one(0000074),		one(0177777),		"#bCs", m68000up },	/* ori to ccr */
+{"oril",	one(0000200),		one(0177700),		"#l$s", m68000up },
+{"oriw",	one(0000100),		one(0177700),		"#w$s", m68000up },
+{"oriw",	one(0000174),		one(0177777),		"#wSs", m68000up },	/* ori to sr */
+{"orl",		one(0000200),		one(0177700),		"#l$s", m68000up },
+{"orl",		one(0100200),		one(0170700),		";lDd", m68000up },	/* memory to register */
+{"orl",		one(0100600),		one(0170700),		"Dd~s", m68000up },	/* register to memory */
+{"orw",		one(0000100),		one(0177700),		"#w$s", m68000up },
+{"orw",		one(0000174),		one(0177777),		"#wSs", m68000up },	/* ori to sr */
+{"orw",		one(0100100),		one(0170700),		";wDd", m68000up },	/* memory to register */
+{"orw",		one(0100500),		one(0170700),		"Dd~s", m68000up },	/* register to memory */
+
+{"pack",	one(0100500),		one(0170770),		"DsDd#w", m68020up },	/* pack Ds,	Dd,	#w */
+{"pack",	one(0100510),		one(0170770),		"-s-d#w", m68020up },	/* pack -(As),	-(Ad),	#w */
+
+#ifndef NO_68851
+{"pbac",	one(0xf0c7),		one(0xffbf),		"Bc", m68851 },
+{"pbacw",	one(0xf087),		one(0xffbf),		"Bc", m68851 },
+{"pbas",	one(0xf0c6),		one(0xffbf),		"Bc", m68851 },
+{"pbasw",	one(0xf086),		one(0xffbf),		"Bc", m68851 },
+{"pbbc",	one(0xf0c1),		one(0xffbf),		"Bc", m68851 },
+{"pbbcw",	one(0xf081),		one(0xffbf),		"Bc", m68851 },
+{"pbbs",	one(0xf0c0),		one(0xffbf),		"Bc", m68851 },
+{"pbbsw",	one(0xf080),		one(0xffbf),		"Bc", m68851 },
+{"pbcc",	one(0xf0cf),		one(0xffbf),		"Bc", m68851 },
+{"pbccw",	one(0xf08f),		one(0xffbf),		"Bc", m68851 },
+{"pbcs",	one(0xf0ce),		one(0xffbf),		"Bc", m68851 },
+{"pbcsw",	one(0xf08e),		one(0xffbf),		"Bc", m68851 },
+{"pbgc",	one(0xf0cd),		one(0xffbf),		"Bc", m68851 },
+{"pbgcw",	one(0xf08d),		one(0xffbf),		"Bc", m68851 },
+{"pbgs",	one(0xf0cc),		one(0xffbf),		"Bc", m68851 },
+{"pbgsw",	one(0xf08c),		one(0xffbf),		"Bc", m68851 },
+{"pbic",	one(0xf0cb),		one(0xffbf),		"Bc", m68851 },
+{"pbicw",	one(0xf08b),		one(0xffbf),		"Bc", m68851 },
+{"pbis",	one(0xf0ca),		one(0xffbf),		"Bc", m68851 },
+{"pbisw",	one(0xf08a),		one(0xffbf),		"Bc", m68851 },
+{"pblc",	one(0xf0c3),		one(0xffbf),		"Bc", m68851 },
+{"pblcw",	one(0xf083),		one(0xffbf),		"Bc", m68851 },
+{"pbls",	one(0xf0c2),		one(0xffbf),		"Bc", m68851 },
+{"pblsw",	one(0xf082),		one(0xffbf),		"Bc", m68851 },
+{"pbsc",	one(0xf0c5),		one(0xffbf),		"Bc", m68851 },
+{"pbscw",	one(0xf085),		one(0xffbf),		"Bc", m68851 },
+{"pbss",	one(0xf0c4),		one(0xffbf),		"Bc", m68851 },
+{"pbssw",	one(0xf084),		one(0xffbf),		"Bc", m68851 },
+{"pbwc",	one(0xf0c9),		one(0xffbf),		"Bc", m68851 },
+{"pbwcw",	one(0xf089),		one(0xffbf),		"Bc", m68851 },
+{"pbws",	one(0xf0c8),		one(0xffbf),		"Bc", m68851 },
+{"pbwsw",	one(0xf088),		one(0xffbf),		"Bc", m68851 },
+
+{"pdbac",	two(0xf048, 0x0007),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbas",	two(0xf048, 0x0006),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbbc",	two(0xf048, 0x0001),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbbs",	two(0xf048, 0x0000),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbcc",	two(0xf048, 0x000f),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbcs",	two(0xf048, 0x000e),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbgc",	two(0xf048, 0x000d),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbgs",	two(0xf048, 0x000c),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbic",	two(0xf048, 0x000b),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbis",	two(0xf048, 0x000a),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdblc",	two(0xf048, 0x0003),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbls",	two(0xf048, 0x0002),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbsc",	two(0xf048, 0x0005),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbss",	two(0xf048, 0x0004),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbwc",	two(0xf048, 0x0009),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+{"pdbws",	two(0xf048, 0x0008),	two(0xfff8, 0xffff),	"DsBw", m68851 },
+#endif /* NO_68851 */
+
+{"pea",		one(0044100),		one(0177700),		"!s", m68000up },
+
+#ifndef NO_68851
+{"pflusha",	two(0xf000, 0x2400),	two(0xffff, 0xffff),	"",		m68030 | m68851 },
+{"pflusha",	one(0xf518),		one(0xfff8), 		"",		m68040 },
+
+{"pflush",	two(0xf000, 0x3010),	two(0xffc0, 0xfe10),	"T3T9",		m68030 | m68851 },
+{"pflush",	two(0xf000, 0x3810),	two(0xffc0, 0xfe10),	"T3T9&s",	m68030 | m68851 },
+{"pflush",	two(0xf000, 0x3008),	two(0xffc0, 0xfe18),	"D3T9",		m68030 | m68851 },
+{"pflush",	two(0xf000, 0x3808),	two(0xffc0, 0xfe18),	"D3T9&s",	m68030 | m68851 },
+{"pflush",	two(0xf000, 0x3000),	two(0xffc0, 0xfe1e),	"f3T9",		m68030 | m68851 },
+{"pflush",	two(0xf000, 0x3800),	two(0xffc0, 0xfe1e),	"f3T9&s",	m68030 | m68851 },
+{"pflush",	one(0xf508),		one(0xfff8), 		"as",		m68040 },
+{"pflush",	one(0xf508),		one(0xfff8), 		"As",		m68040 },
+{"pflushan",	one(0xf510),		one(0xfff8),		"",		m68040 },
+{"pflushn",	one(0xf500),		one(0xfff8),		"as",		m68040 },
+{"pflushn",	one(0xf500),		one(0xfff8),		"As",		m68040 },
+
+{"pflushr",	two(0xf000, 0xa000),	two(0xffc0, 0xffff),	"|s",		m68851 },
+
+{"pflushs",	two(0xf000, 0x3410),	two(0xfff8, 0xfe10),	"T3T9",		m68851 },
+{"pflushs",	two(0xf000, 0x3c10),	two(0xfff8, 0xfe00),	"T3T9&s",	m68851 },
+{"pflushs",	two(0xf000, 0x3408),	two(0xfff8, 0xfe18),	"D3T9",		m68851 },
+{"pflushs",	two(0xf000, 0x3c08),	two(0xfff8, 0xfe18),	"D3T9&s",	m68851 },
+{"pflushs",	two(0xf000, 0x3400),	two(0xfff8, 0xfe1e),	"f3T9",		m68851 },
+{"pflushs",	two(0xf000, 0x3c00),	two(0xfff8, 0xfe1e),	"f3T9&s",	m68851 },
+
+{"ploadr",	two(0xf000, 0x2210),	two(0xffc0, 0xfff0),	"T3&s",	m68030 | m68851 },
+{"ploadr",	two(0xf000, 0x2208),	two(0xffc0, 0xfff8),	"D3&s",	m68030 | m68851 },
+{"ploadr",	two(0xf000, 0x2200),	two(0xffc0, 0xfffe),	"f3&s",	m68030 | m68851 },
+{"ploadw",	two(0xf000, 0x2010),	two(0xffc0, 0xfff0),	"T3&s",	m68030 | m68851 },
+{"ploadw",	two(0xf000, 0x2008),	two(0xffc0, 0xfff8),	"D3&s",	m68030 | m68851 },
+{"ploadw",	two(0xf000, 0x2000),	two(0xffc0, 0xfffe),	"f3&s",	m68030 | m68851 },
+
+/* TC, CRP, DRP, SRP, CAL, VAL, SCC, AC */
+{"pmove",	two(0xf000, 0x4000),	two(0xffc0, 0xe3ff),	"*sP8",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x4200),	two(0xffc0, 0xe3ff),	"P8%s",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x4000),	two(0xffc0, 0xe3ff),	"|sW8",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x4200),	two(0xffc0, 0xe3ff),	"W8~s",	m68030 | m68851 },
+
+/* BADx, BACx */
+{"pmove",	two(0xf000, 0x6200),	two(0xffc0, 0xe3e3),	"*sX3",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x6000),	two(0xffc0, 0xe3e3),	"X3%s",	m68030 | m68851 },
+
+/* PSR, PCSR */
+/* {"pmove",	two(0xf000, 0x6100),	two(oxffc0, oxffff),	"*sZ8",	m68030 | m68851 }, */
+{"pmove",	two(0xf000, 0x6000),	two(0xffc0, 0xffff),	"*sY8",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x6200),	two(0xffc0, 0xffff),	"Y8%s",	m68030 | m68851 },
+{"pmove",	two(0xf000, 0x6600),	two(0xffc0, 0xffff),	"Z8%s",	m68030 | m68851 },
+
+{"prestore",	one(0xf140),		one(0xffc0),		"&s", m68851 },
+{"prestore",	one(0xf158),		one(0xfff8),		"+s", m68851 },
+{"psave",	one(0xf100),		one(0xffc0),		"&s", m68851 },
+{"psave",	one(0xf100),		one(0xffc0),		"+s", m68851 },
+
+{"psac",	two(0xf040, 0x0007),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psas",	two(0xf040, 0x0006),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psbc",	two(0xf040, 0x0001),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psbs",	two(0xf040, 0x0000),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"pscc",	two(0xf040, 0x000f),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"pscs",	two(0xf040, 0x000e),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psgc",	two(0xf040, 0x000d),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psgs",	two(0xf040, 0x000c),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psic",	two(0xf040, 0x000b),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psis",	two(0xf040, 0x000a),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"pslc",	two(0xf040, 0x0003),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psls",	two(0xf040, 0x0002),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"pssc",	two(0xf040, 0x0005),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psss",	two(0xf040, 0x0004),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"pswc",	two(0xf040, 0x0009),	two(0xffc0, 0xffff),	"@s", m68851 },
+{"psws",	two(0xf040, 0x0008),	two(0xffc0, 0xffff),	"@s", m68851 },
+
+{"ptestr",	two(0xf000, 0x8210),	two(0xffc0, 0xe3f0),	"T3&sQ8",	m68030 | m68851 },
+{"ptestr",	two(0xf000, 0x8310),	two(0xffc0, 0xe310),	"T3&sQ8A9",	m68030 | m68851 },
+{"ptestr",	two(0xf000, 0x8208),	two(0xffc0, 0xe3f8),	"D3&sQ8",	m68030 | m68851 },
+{"ptestr",	two(0xf000, 0x8308),	two(0xffc0, 0xe318),	"D3&sQ8A9",	m68030 | m68851 },
+{"ptestr",	two(0xf000, 0x8200),	two(0xffc0, 0xe3fe),	"f3&sQ8",	m68030 | m68851 },
+{"ptestr",	two(0xf000, 0x8300),	two(0xffc0, 0xe31e),	"f3&sQ8A9",	m68030 | m68851 },
+
+{"ptestr",	one(0xf568),		one(0xfff8),		"as",		m68040 },
+
+{"ptestw",	two(0xf000, 0x8010),	two(0xffc0, 0xe3f0),	"T3&sQ8",	m68030 | m68851 },
+{"ptestw",	two(0xf000, 0x8110),	two(0xffc0, 0xe310),	"T3&sQ8A9",	m68030 | m68851 },
+{"ptestw",	two(0xf000, 0x8008),	two(0xffc0, 0xe3f8),	"D3&sQ8",	m68030 | m68851 },
+{"ptestw",	two(0xf000, 0x8108),	two(0xffc0, 0xe318),	"D3&sQ8A9",	m68030 | m68851 },
+{"ptestw",	two(0xf000, 0x8000),	two(0xffc0, 0xe3fe),	"f3&sQ8",	m68030 | m68851 },
+{"ptestw",	two(0xf000, 0x8100),	two(0xffc0, 0xe31e),	"f3&sQ8A9",	m68030 | m68851 },
+
+{"ptestw",	one(0xf548),		one(0xfff8),		"as",		m68040 },
+
+{"ptrapacw",	two(0xf07a, 0x0007),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapacl",	two(0xf07b, 0x0007),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapac",	two(0xf07c, 0x0007),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapasw",	two(0xf07a, 0x0006),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapasl",	two(0xf07b, 0x0006),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapas",	two(0xf07c, 0x0006),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapbcw",	two(0xf07a, 0x0001),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapbcl",	two(0xf07b, 0x0001),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapbc",	two(0xf07c, 0x0001),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapbsw",	two(0xf07a, 0x0000),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapbsl",	two(0xf07b, 0x0000),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapbs",	two(0xf07c, 0x0000),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapccw",	two(0xf07a, 0x000f),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapccl",	two(0xf07b, 0x000f),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapcc",	two(0xf07c, 0x000f),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapcsw",	two(0xf07a, 0x000e),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapcsl",	two(0xf07b, 0x000e),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapcs",	two(0xf07c, 0x000e),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapgcw",	two(0xf07a, 0x000d),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapgcl",	two(0xf07b, 0x000d),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapgc",	two(0xf07c, 0x000d),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapgsw",	two(0xf07a, 0x000c),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapgsl",	two(0xf07b, 0x000c),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapgs",	two(0xf07c, 0x000c),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapicw",	two(0xf07a, 0x000b),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapicl",	two(0xf07b, 0x000b),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapic",	two(0xf07c, 0x000b),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapisw",	two(0xf07a, 0x000a),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapisl",	two(0xf07b, 0x000a),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapis",	two(0xf07c, 0x000a),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptraplcw",	two(0xf07a, 0x0003),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptraplcl",	two(0xf07b, 0x0003),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptraplc",	two(0xf07c, 0x0003),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptraplsw",	two(0xf07a, 0x0002),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptraplsl",	two(0xf07b, 0x0002),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapls",	two(0xf07c, 0x0002),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapscw",	two(0xf07a, 0x0005),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapscl",	two(0xf07b, 0x0005),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapsc",	two(0xf07c, 0x0005),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapssw",	two(0xf07a, 0x0004),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapssl",	two(0xf07b, 0x0004),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapss",	two(0xf07c, 0x0004),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapwcw",	two(0xf07a, 0x0009),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapwcl",	two(0xf07b, 0x0009),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapwc",	two(0xf07c, 0x0009),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"ptrapwsw",	two(0xf07a, 0x0008),	two(0xffff, 0xffff),	"#w", m68851 },
+{"ptrapwsl",	two(0xf07b, 0x0008),	two(0xffff, 0xffff),	"#l", m68851 },
+{"ptrapws",	two(0xf07c, 0x0008),	two(0xffff, 0xffff),	"",   m68851 },
+
+{"pvalid",	two(0xf000, 0x2800),	two(0xffc0, 0xffff),	"Vs&s", m68851 },
+{"pvalid",	two(0xf000, 0x2c00),	two(0xffc0, 0xfff8),	"A3&s", m68851 },
+
+#endif /* NO_68851 */
+
+{"reset",	one(0047160),		one(0177777),		"", m68000up },
+
+{"rolb",	one(0160430),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"rolb",	one(0160470),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"roll",	one(0160630),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"roll",	one(0160670),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"rolw",	one(0160530),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"rolw",	one(0160570),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"rolw",	one(0163700),		one(0177700),		"~s",   m68000up },	/* Rotate memory */
+{"rorb",	one(0160030),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"rorb",	one(0160070),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"rorl",	one(0160230),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"rorl",	one(0160270),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"rorw",	one(0160130),		one(0170770),		"QdDs", m68000up },	/* rorb #Q,	Ds */
+{"rorw",	one(0160170),		one(0170770),		"DdDs", m68000up },	/* rorb Dd,	Ds */
+{"rorw",	one(0163300),		one(0177700),		"~s",   m68000up },	/* Rotate memory */
+
+{"roxlb",	one(0160420),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxlb",	one(0160460),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxll",	one(0160620),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxll",	one(0160660),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxlw",	one(0160520),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxlw",	one(0160560),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxlw",	one(0162700),		one(0177700),		"~s",   m68000up },	/* Rotate memory */
+{"roxrb",	one(0160020),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxrb",	one(0160060),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxrl",	one(0160220),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxrl",	one(0160260),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxrw",	one(0160120),		one(0170770),		"QdDs", m68000up },	/* roxrb #Q,	Ds */
+{"roxrw",	one(0160160),		one(0170770),		"DdDs", m68000up },	/* roxrb Dd,	Ds */
+{"roxrw",	one(0162300),		one(0177700),		"~s",   m68000up },	/* Rotate memory */
+
+{"rtd",		one(0047164),		one(0177777),		"#w", m68010up },
+{"rte",		one(0047163),		one(0177777),		"",   m68000up },
+{"rtm",		one(0003300),		one(0177760),		"Rs", m68020 },
+{"rtr",		one(0047167),		one(0177777),		"",   m68000up },
+{"rts",		one(0047165),		one(0177777),		"",   m68000up },
+
+{"sbcd",	one(0100400),		one(0170770),		"DsDd", m68000up },
+{"sbcd",	one(0100410),		one(0170770),		"-s-d", m68000up },
+
+{"scc",		one(0052300),		one(0177700),		"$s", m68000up },
+{"scs",		one(0052700),		one(0177700),		"$s", m68000up },
+{"seq",		one(0053700),		one(0177700),		"$s", m68000up },
+{"sf",		one(0050700),		one(0177700),		"$s", m68000up },
+{"sge",		one(0056300),		one(0177700),		"$s", m68000up },
+{"sfge",	one(0056300),		one(0177700),		"$s", m68000up },
+{"sgt",		one(0057300),		one(0177700),		"$s", m68000up },
+{"sfgt",	one(0057300),		one(0177700),		"$s", m68000up },
+{"shi",		one(0051300),		one(0177700),		"$s", m68000up },
+{"sle",		one(0057700),		one(0177700),		"$s", m68000up },
+{"sfle",	one(0057700),		one(0177700),		"$s", m68000up },
+{"sls",		one(0051700),		one(0177700),		"$s", m68000up },
+{"slt",		one(0056700),		one(0177700),		"$s", m68000up },
+{"sflt",	one(0056700),		one(0177700),		"$s", m68000up },
+{"smi",		one(0055700),		one(0177700),		"$s", m68000up },
+{"sne",		one(0053300),		one(0177700),		"$s", m68000up },
+{"sfneq",	one(0053300),		one(0177700),		"$s", m68000up },
+{"spl",		one(0055300),		one(0177700),		"$s", m68000up },
+{"st",		one(0050300),		one(0177700),		"$s", m68000up },
+{"svc",		one(0054300),		one(0177700),		"$s", m68000up },
+{"svs",		one(0054700),		one(0177700),		"$s", m68000up },
+
+{"stop",	one(0047162),		one(0177777),		"#w", m68000up },
+
+{"subal",	one(0110700),		one(0170700),		"*lAd", m68000up },
+{"subaw",	one(0110300),		one(0170700),		"*wAd", m68000up },
+{"subb",	one(0050400),		one(0170700),		"Qd%s", m68000up },	/* subq written as sub */
+{"subb",	one(0002000),		one(0177700),		"#b$s", m68000up },	/* subi written as sub */
+{"subb",	one(0110000),		one(0170700),		";bDd", m68000up },	/* subb ? ?,	Dd */
+{"subb",	one(0110400),		one(0170700),		"Dd~s", m68000up },	/* subb Dd,	? ? */
+{"subib",	one(0002000),		one(0177700),		"#b$s", m68000up },
+{"subil",	one(0002200),		one(0177700),		"#l$s", m68000up },
+{"subiw",	one(0002100),		one(0177700),		"#w$s", m68000up },
+{"subl",	one(0050600),		one(0170700),		"Qd%s", m68000up },
+{"subl",	one(0002200),		one(0177700),		"#l$s", m68000up },
+{"subl",	one(0110700),		one(0170700),		"*lAd", m68000up },
+{"subl",	one(0110200),		one(0170700),		"*lDd", m68000up },
+{"subl",	one(0110600),		one(0170700),		"Dd~s", m68000up },
+{"subqb",	one(0050400),		one(0170700),		"Qd%s", m68000up },
+{"subql",	one(0050600),		one(0170700),		"Qd%s", m68000up },
+{"subqw",	one(0050500),		one(0170700),		"Qd%s", m68000up },
+{"subw",	one(0050500),		one(0170700),		"Qd%s", m68000up },
+{"subw",	one(0002100),		one(0177700),		"#w$s", m68000up },
+{"subw",	one(0110100),		one(0170700),		"*wDd", m68000up },
+{"subw",	one(0110300),		one(0170700),		"*wAd", m68000up },	/* suba written as sub */
+{"subw",	one(0110500),		one(0170700),		"Dd~s", m68000up },
+{"subxb",	one(0110400),		one(0170770),		"DsDd", m68000up },	/* subxb Ds,	Dd */
+{"subxb",	one(0110410),		one(0170770),		"-s-d", m68000up },	/* subxb -(As),	-(Ad) */
+{"subxl",	one(0110600),		one(0170770),		"DsDd", m68000up },
+{"subxl",	one(0110610),		one(0170770),		"-s-d", m68000up },
+{"subxw",	one(0110500),		one(0170770),		"DsDd", m68000up },
+{"subxw",	one(0110510),		one(0170770),		"-s-d", m68000up },
+
+{"swap",	one(0044100),		one(0177770),		"Ds", m68000up },
+	
+{"tas",		one(0045300),		one(0177700),		"$s", m68000up },
+{"trap",	one(0047100),		one(0177760),		"Ts", m68000up },
+
+{"trapcc",	one(0052374),		one(0177777),		"", m68020up },
+{"trapcs",	one(0052774),		one(0177777),		"", m68020up },
+{"trapeq",	one(0053774),		one(0177777),		"", m68020up },
+{"trapf",	one(0050774),		one(0177777),		"", m68020up },
+{"trapge",	one(0056374),		one(0177777),		"", m68020up },
+{"trapgt",	one(0057374),		one(0177777),		"", m68020up },
+{"traphi",	one(0051374),		one(0177777),		"", m68020up },
+{"traple",	one(0057774),		one(0177777),		"", m68020up },
+{"trapls",	one(0051774),		one(0177777),		"", m68020up },
+{"traplt",	one(0056774),		one(0177777),		"", m68020up },
+{"trapmi",	one(0055774),		one(0177777),		"", m68020up },
+{"trapne",	one(0053374),		one(0177777),		"", m68020up },
+{"trappl",	one(0055374),		one(0177777),		"", m68020up },
+{"trapt",	one(0050374),		one(0177777),		"", m68020up },
+{"trapvc",	one(0054374),		one(0177777),		"", m68020up },
+{"trapvs",	one(0054774),		one(0177777),		"", m68020up },
+
+{"trapcc.w",	one(0052372),		one(0177777),		"", m68020up },
+{"trapcs.w",	one(0052772),		one(0177777),		"", m68020up },
+{"trapeq.w",	one(0053772),		one(0177777),		"", m68020up },
+{"trapf.w",	one(0050772),		one(0177777),		"", m68020up },
+{"trapge.w",	one(0056372),		one(0177777),		"", m68020up },
+{"trapgt.w",	one(0057372),		one(0177777),		"", m68020up },
+{"traphi.w",	one(0051372),		one(0177777),		"", m68020up },
+{"traple.w",	one(0057772),		one(0177777),		"", m68020up },
+{"trapls.w",	one(0051772),		one(0177777),		"", m68020up },
+{"traplt.w",	one(0056772),		one(0177777),		"", m68020up },
+{"trapmi.w",	one(0055772),		one(0177777),		"", m68020up },
+{"trapne.w",	one(0053372),		one(0177777),		"", m68020up },
+{"trappl.w",	one(0055372),		one(0177777),		"", m68020up },
+{"trapt.w",	one(0050372),		one(0177777),		"", m68020up },
+{"trapvc.w",	one(0054372),		one(0177777),		"", m68020up },
+{"trapvs.w",	one(0054772),		one(0177777),		"", m68020up },
+
+{"trapcc.l",	one(0052373),		one(0177777),		"", m68020up },
+{"trapcs.l",	one(0052773),		one(0177777),		"", m68020up },
+{"trapeq.l",	one(0053773),		one(0177777),		"", m68020up },
+{"trapf.l",	one(0050773),		one(0177777),		"", m68020up },
+{"trapge.l",	one(0056373),		one(0177777),		"", m68020up },
+{"trapgt.l",	one(0057373),		one(0177777),		"", m68020up },
+{"traphi.l",	one(0051373),		one(0177777),		"", m68020up },
+{"traple.l",	one(0057773),		one(0177777),		"", m68020up },
+{"trapls.l",	one(0051773),		one(0177777),		"", m68020up },
+{"traplt.l",	one(0056773),		one(0177777),		"", m68020up },
+{"trapmi.l",	one(0055773),		one(0177777),		"", m68020up },
+{"trapne.l",	one(0053373),		one(0177777),		"", m68020up },
+{"trappl.l",	one(0055373),		one(0177777),		"", m68020up },
+{"trapt.l",	one(0050373),		one(0177777),		"", m68020up },
+{"trapvc.l",	one(0054373),		one(0177777),		"", m68020up },
+{"trapvs.l",	one(0054773),		one(0177777),		"", m68020up },
+
+{"trapv",	one(0047166),		one(0177777),		"", m68000up },
+
+{"tstb",	one(0045000),		one(0177700),		";b", m68000up },
+{"tstw",	one(0045100),		one(0177700),		"*w", m68000up },
+{"tstl",	one(0045200),		one(0177700),		"*l", m68000up },
+
+{"unlk",	one(0047130),		one(0177770),		"As", m68000up },
+{"unpk",	one(0100600),		one(0170770),		"DsDd#w", m68020up },
+{"unpk",	one(0100610),		one(0170770),		"-s-d#w", m68020up },
+
+/* Variable-sized branches */
+
+{"jbsr",	one(0060400),		one(0177400),		"Bg", m68000up },
+{"jbsr",	one(0047200),		one(0177700),		"!s", m68000up },
+#ifdef	PIC
+{"jbsr",	one(0060400),		one(0177400),		"Bg  ", m68020up },
+#endif	/* PIC */
+
+{"jra",		one(0060000),		one(0177400),		"Bg", m68000up },
+{"jra",		one(0047300),		one(0177700),		"!s", m68000up },
+#ifdef	PIC
+{"jra",		one(0060000),		one(0177400),		"Bg  ", m68000up },
+#endif	/* PIC */
+
+{"jhi",		one(0061000),		one(0177400),		"Bg", m68000up },
+{"jls",		one(0061400),		one(0177400),		"Bg", m68000up },
+{"jcc",		one(0062000),		one(0177400),		"Bg", m68000up },
+{"jfnlt",	one(0062000),		one(0177400),		"Bg", m68000up }, /* apparently a sun alias */
+{"jcs",		one(0062400),		one(0177400),		"Bg", m68000up },
+{"jne",		one(0063000),		one(0177400),		"Bg", m68000up },
+{"jeq",		one(0063400),		one(0177400),		"Bg", m68000up },
+{"jfeq",	one(0063400),		one(0177400),		"Bg", m68000up }, /* apparently a sun alias */
+{"jvc",		one(0064000),		one(0177400),		"Bg", m68000up },
+{"jvs",		one(0064400),		one(0177400),		"Bg", m68000up },
+{"jpl",		one(0065000),		one(0177400),		"Bg", m68000up },
+{"jmi",		one(0065400),		one(0177400),		"Bg", m68000up },
+{"jge",		one(0066000),		one(0177400),		"Bg", m68000up },
+{"jlt",		one(0066400),		one(0177400),		"Bg", m68000up },
+{"jgt",		one(0067000),		one(0177400),		"Bg", m68000up },
+{"jle",		one(0067400),		one(0177400),		"Bg", m68000up },
+{"jfngt",	one(0067400),		one(0177400),		"Bg", m68000up }, /* apparently a sun alias */
+
+/* aliases */
+
+{"movql",	one(0070000),		one(0170400),		"MsDd", m68000up },
+{"moveql",	one(0070000),		one(0170400),		"MsDd", m68000up },
+{"moval",	one(0020100),		one(0170700),		"*lAd", m68000up },
+{"movaw",	one(0030100),		one(0170700),		"*wAd", m68000up },
+{"movb",	one(0010000),		one(0170000),		";b$d", m68000up },	/* mov */
+{"movl",	one(0070000),		one(0170400),		"MsDd", m68000up },	/* movq written as mov */
+{"movl",	one(0020000),		one(0170000),		"*l$d", m68000up },
+{"movl",	one(0020100),		one(0170700),		"*lAd", m68000up },
+{"movl",	one(0047140),		one(0177770),		"AsUd", m68000up },	/* mov to USP */
+{"movl",	one(0047150),		one(0177770),		"UdAs", m68000up },	/* mov from USP */
+{"movc",	one(0047173),		one(0177777),		"R1Jj", m68010up },
+{"movc",	one(0047173),		one(0177777),		"R1#j", m68010up },
+{"movc",	one(0047172),		one(0177777),		"JjR1", m68010up },
+{"movc",	one(0047172),		one(0177777),		"#jR1", m68010up },
+{"movml",	one(0044300),		one(0177700),		"#w&s", m68000up },	/* movm reg to mem. */
+{"movml",	one(0044340),		one(0177770),		"#w-s", m68000up },	/* movm reg to autodecrement. */
+{"movml",	one(0046300),		one(0177700),		"!s#w", m68000up },	/* movm mem to reg. */
+{"movml",	one(0046330),		one(0177770),		"+s#w", m68000up },	/* movm autoinc to reg. */
+{"movml",	one(0044300),		one(0177700),		"Lw&s", m68000up },	/* movm reg to mem. */
+{"movml",	one(0044340),		one(0177770),		"lw-s", m68000up },	/* movm reg to autodecrement. */
+{"movml",	one(0046300),		one(0177700),		"!sLw", m68000up },	/* movm mem to reg. */
+{"movml",	one(0046330),		one(0177770),		"+sLw", m68000up },	/* movm autoinc to reg. */
+{"movmw",	one(0044200),		one(0177700),		"#w&s", m68000up },	/* movm reg to mem. */
+{"movmw",	one(0044240),		one(0177770),		"#w-s", m68000up },	/* movm reg to autodecrement. */
+{"movmw",	one(0046200),		one(0177700),		"!s#w", m68000up },	/* movm mem to reg. */
+{"movmw",	one(0046230),		one(0177770),		"+s#w", m68000up },	/* movm autoinc to reg. */
+{"movmw",	one(0044200),		one(0177700),		"Lw&s", m68000up },	/* movm reg to mem. */
+{"movmw",	one(0044240),		one(0177770),		"lw-s", m68000up },	/* movm reg to autodecrement. */
+{"movmw",	one(0046200),		one(0177700),		"!sLw", m68000up },	/* movm mem to reg. */
+{"movmw",	one(0046230),		one(0177770),		"+sLw", m68000up },	/* movm autoinc to reg. */
+{"movpl",	one(0000510),		one(0170770),		"dsDd", m68000up },	/* memory to register */
+{"movpl",	one(0000710),		one(0170770),		"Ddds", m68000up },	/* register to memory */
+{"movpw",	one(0000410),		one(0170770),		"dsDd", m68000up },	/* memory to register */
+{"movpw",	one(0000610),		one(0170770),		"Ddds", m68000up },	/* register to memory */
+{"movq",	one(0070000),		one(0170400),		"MsDd", m68000up },
+{"movw",	one(0030000),		one(0170000),		"*w$d", m68000up },
+{"movw",	one(0030100),		one(0170700),		"*wAd", m68000up },	/* mova,	written as mov */
+{"movw",	one(0040300),		one(0177700),		"Ss$s", m68000up },	/* Move from sr */
+{"movw",	one(0041300),		one(0177700),		"Cs$s", m68010up },	/* Move from ccr */
+{"movw",	one(0042300),		one(0177700),		";wCd", m68000up },	/* mov to ccr */
+{"movw",	one(0043300),		one(0177700),		";wSd", m68000up },	/* mov to sr */
+
+{"movsb",	two(0007000, 0),	two(0177700, 07777),	"~sR1", m68010up },
+{"movsb",	two(0007000, 04000),	two(0177700, 07777),	"R1~s", m68010up },
+{"movsl",	two(0007200, 0),	two(0177700, 07777),	"~sR1", m68010up },
+{"movsl",	two(0007200, 04000),	two(0177700, 07777),	"R1~s", m68010up },
+{"movsw",	two(0007100, 0),	two(0177700, 07777),	"~sR1", m68010up },
+{"movsw",	two(0007100, 04000),	two(0177700, 07777),	"R1~s", m68010up },
+
+};
+
+int numopcodes=sizeof(m68k_opcodes)/sizeof(m68k_opcodes[0]);
+
+struct m68k_opcode *endop = m68k_opcodes+sizeof(m68k_opcodes)/sizeof(m68k_opcodes[0]);
+
+/*
+ * Local Variables:
+ * fill-column: 131
+ * End:
+ */
+
+/* end of m68k-opcode.h */
diff --git a/gnu/usr.bin/gas/opcode/m88k.h b/gnu/usr.bin/gas/opcode/m88k.h
new file mode 100644
index 00000000000..5f685b90fc8
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/m88k.h
@@ -0,0 +1,282 @@
+/* m88k-opcode.h -- Instruction information for the Motorola 88000
+   Contributed by Devon Bowen of Buffalo University
+   and Torbjorn Granlund of the Swedish Institute of Computer Science.
+   Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
+
+This file is part of GAS, the GNU Assembler.
+
+GAS is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GAS is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+/*
+  Character codes for op_spec field below.
+  Reserved for direct matching: x , [ ]
+
+  d = GRF Destination register (21:5)
+  1 = Source register 1 (16:5)
+  2 = Source register 2 (0:5)
+  3 = Both source registers (same value) (0:5 and 16:5)
+  I = IMM16 (0:16)
+  b = bit field spec. (0:10)
+  p = 16 bit pc displ. (0:16)
+  P = 26 bit pc displ. (0:26)
+  B = bb0/bb1 condition (21:5)
+  M = bcnd condition (21:5)
+  f = fcr (5:6)
+  c = cr (5:6)
+  V = VEC9 (0:9)
+  ? = Give warning for this insn/operand combination
+ */
+
+/* instruction descriptor structure */
+
+struct m88k_opcode
+{
+  unsigned int	opcode;
+  char		*name;
+  char		*op_spec;
+};
+
+/* and introducing... the Motorola 88100 instruction sets... */
+
+/* These macros may seem silly, but they are in preparation
+   for future versions of the 88000 family.  */
+
+#define _MC88100(OPCODE,MNEM,OP_SPEC) {OPCODE,MNEM,OP_SPEC},
+#define _MC88xxx(OPCODE,MNEM,OP_SPEC) {OPCODE,MNEM,OP_SPEC},
+
+/* Equal mnemonics must be adjacent.
+   More specific operand specification must go before more general.
+   For example, "d,1,2" must go before "d,1,I" as a register for s2
+   would otherwise be considered a variable name.  */
+
+static struct m88k_opcode m88k_opcodes[] =
+{
+  /*  Opcode     Mnemonic         Opspec */
+
+  _MC88xxx(0xf4007000, "add",		"d,1,2")
+  _MC88xxx(0x70000000, "add",		"d,1,I")
+  _MC88xxx(0xf4007200, "add.ci",	"d,1,2")
+  _MC88xxx(0xf4007300, "add.cio",	"d,1,2")
+  _MC88xxx(0xf4007100, "add.co",	"d,1,2")
+  _MC88xxx(0xf4006000, "addu",		"d,1,2")
+  _MC88xxx(0x60000000, "addu",		"d,1,I")
+  _MC88xxx(0xf4006200, "addu.ci",	"d,1,2")
+  _MC88xxx(0xf4006300, "addu.cio",	"d,1,2")
+  _MC88xxx(0xf4006100, "addu.co",	"d,1,2")
+  _MC88xxx(0xf4004000, "and",		"d,1,2")
+  _MC88xxx(0x40000000, "and",		"d,1,I")
+  _MC88xxx(0xf4004400, "and.c",		"d,1,2")
+  _MC88xxx(0x44000000, "and.u",		"d,1,I")
+  _MC88xxx(0xd0000000, "bb0",		"B,1,p")
+  _MC88xxx(0xd4000000, "bb0.n",		"B,1,p")
+  _MC88xxx(0xd8000000, "bb1",		"B,1,p")
+  _MC88xxx(0xdc000000, "bb1.n",		"B,1,p")
+  _MC88xxx(0xe8000000, "bcnd",		"M,1,p")
+  _MC88xxx(0xec000000, "bcnd.n",	"M,1,p")
+  _MC88xxx(0xc0000000, "br",		"P")
+  _MC88xxx(0xc4000000, "br.n",		"P")
+  _MC88xxx(0xc8000000, "bsr",		"P")
+  _MC88xxx(0xcc000000, "bsr.n",		"P")
+  _MC88xxx(0xf4008000, "clr",		"d,1,2")
+  _MC88xxx(0xf0008000, "clr",		"d,1,b")
+  _MC88xxx(0xf4007c00, "cmp",		"d,1,2")
+  _MC88xxx(0x7c000000, "cmp",		"d,1,I")
+  _MC88xxx(0xf4007800, "div",		"d,1,2")
+  _MC88xxx(0x78000000, "div",		"d,1,I")
+  _MC88xxx(0xf4007800, "divs",		"d,1,2")
+  _MC88xxx(0x78000000, "divs",		"d,1,I")
+  _MC88xxx(0xf4006800, "divu",		"d,1,2")
+  _MC88xxx(0x68000000, "divu",		"d,1,I")
+  _MC88xxx(0xf4009000, "ext",		"d,1,2")
+  _MC88xxx(0xf0009000, "ext",		"d,1,b")
+  _MC88xxx(0xf4009800, "extu",		"d,1,2")
+  _MC88xxx(0xf0009800, "extu",		"d,1,b")
+  _MC88xxx(0x84002800, "fadd.sss",	"d,1,2")
+  _MC88xxx(0x84002880, "fadd.ssd",	"d,1,2")
+  _MC88xxx(0x84002a00, "fadd.sds",	"d,1,2")
+  _MC88xxx(0x84002a80, "fadd.sdd",	"d,1,2")
+  _MC88xxx(0x84002820, "fadd.dss",	"d,1,2")
+  _MC88xxx(0x840028a0, "fadd.dsd",	"d,1,2")
+  _MC88xxx(0x84002a20, "fadd.dds",	"d,1,2")
+  _MC88xxx(0x84002aa0, "fadd.ddd",	"d,1,2")
+  _MC88xxx(0x84003a80, "fcmp.sdd",	"d,1,2")
+  _MC88xxx(0x84003a00, "fcmp.sds",	"d,1,2")
+  _MC88xxx(0x84003880, "fcmp.ssd",	"d,1,2")
+  _MC88xxx(0x84003800, "fcmp.sss",	"d,1,2")
+  _MC88xxx(0x84007000, "fdiv.sss",	"d,1,2")
+  _MC88xxx(0x84007080, "fdiv.ssd",	"d,1,2")
+  _MC88xxx(0x84007200, "fdiv.sds",	"d,1,2")
+  _MC88xxx(0x84007280, "fdiv.sdd",	"d,1,2")
+  _MC88xxx(0x84007020, "fdiv.dss",	"d,1,2")
+  _MC88xxx(0x840070a0, "fdiv.dsd",	"d,1,2")
+  _MC88xxx(0x84007220, "fdiv.dds",	"d,1,2")
+  _MC88xxx(0x840072a0, "fdiv.ddd",	"d,1,2")
+  _MC88xxx(0xf400ec00, "ff0",		"d,2")
+  _MC88xxx(0xf400e800, "ff1",		"d,2")
+  _MC88xxx(0x80004800, "fldcr",		"d,f")
+  _MC88xxx(0x84002020, "flt.ds",	"d,2")
+  _MC88xxx(0x84002000, "flt.ss",	"d,2")
+  _MC88xxx(0x84000000, "fmul.sss",	"d,1,2")
+  _MC88xxx(0x84000080, "fmul.ssd",	"d,1,2")
+  _MC88xxx(0x84000200, "fmul.sds",	"d,1,2")
+  _MC88xxx(0x84000280, "fmul.sdd",	"d,1,2")
+  _MC88xxx(0x84000020, "fmul.dss",	"d,1,2")
+  _MC88xxx(0x840000a0, "fmul.dsd",	"d,1,2")
+  _MC88xxx(0x84000220, "fmul.dds",	"d,1,2")
+  _MC88xxx(0x840002a0, "fmul.ddd",	"d,1,2")
+  _MC88xxx(0x80008800, "fstcr",		"3,f")
+  _MC88xxx(0x84003000, "fsub.sss",	"d,1,2")
+  _MC88xxx(0x84003080, "fsub.ssd",	"d,1,2")
+  _MC88xxx(0x84003200, "fsub.sds",	"d,1,2")
+  _MC88xxx(0x84003280, "fsub.sdd",	"d,1,2")
+  _MC88xxx(0x84003020, "fsub.dss",	"d,1,2")
+  _MC88xxx(0x840030a0, "fsub.dsd",	"d,1,2")
+  _MC88xxx(0x84003220, "fsub.dds",	"d,1,2")
+  _MC88xxx(0x840032a0, "fsub.ddd",	"d,1,2")
+  _MC88xxx(0x8000c800, "fxcr",		"d,3,f")
+  _MC88xxx(0x8400fc01, "illop1",	"")
+  _MC88xxx(0x8400fc02, "illop2",	"")
+  _MC88xxx(0x8400fc03, "illop3",	"")
+  _MC88xxx(0x84004880, "int.sd",	"d,2")
+  _MC88xxx(0x84004800, "int.ss",	"d,2")
+  _MC88xxx(0xf400c000, "jmp",		"2")
+  _MC88xxx(0xf400c400, "jmp.n",		"2")
+  _MC88xxx(0xf400c800, "jsr",		"2")
+  _MC88xxx(0xf400cc00, "jsr.n",		"2")
+  _MC88xxx(0xf4001400, "ld",		"d,1,2")
+  _MC88xxx(0xf4001600, "ld",		"d,1[2]")
+  _MC88xxx(0x14000000, "ld",		"d,1,I")
+  _MC88xxx(0xf4001e00, "ld.b",		"d,1[2]")
+  _MC88xxx(0xf4001c00, "ld.b",		"d,1,2")
+  _MC88xxx(0x1c000000, "ld.b",		"d,1,I")
+  _MC88xxx(0xf4001d00, "ld.b.usr",	"d,1,2")
+  _MC88xxx(0xf4001f00, "ld.b.usr",	"d,1[2]")
+  _MC88xxx(0xf4000e00, "ld.bu",		"d,1[2]")
+  _MC88xxx(0xf4000c00, "ld.bu",		"d,1,2")
+  _MC88xxx(0x0c000000, "ld.bu",		"d,1,I")
+  _MC88xxx(0xf4000d00, "ld.bu.usr",	"d,1,2")
+  _MC88xxx(0xf4000f00, "ld.bu.usr",	"d,1[2]")
+  _MC88xxx(0xf4001200, "ld.d",		"d,1[2]")
+  _MC88xxx(0xf4001000, "ld.d",		"d,1,2")
+  _MC88xxx(0x10000000, "ld.d",		"d,1,I")
+  _MC88xxx(0xf4001100, "ld.d.usr",	"d,1,2")
+  _MC88xxx(0xf4001300, "ld.d.usr",	"d,1[2]")
+  _MC88xxx(0xf4001a00, "ld.h",		"d,1[2]")
+  _MC88xxx(0xf4001800, "ld.h",		"d,1,2")
+  _MC88xxx(0x18000000, "ld.h",		"d,1,I")
+  _MC88xxx(0xf4001900, "ld.h.usr",	"d,1,2")
+  _MC88xxx(0xf4001b00, "ld.h.usr",	"d,1[2]")
+  _MC88xxx(0xf4000a00, "ld.hu",		"d,1[2]")
+  _MC88xxx(0xf4000800, "ld.hu",		"d,1,2")
+  _MC88xxx(0x08000000, "ld.hu",		"d,1,I")
+  _MC88xxx(0xf4000900, "ld.hu.usr",	"d,1,2")
+  _MC88xxx(0xf4000b00, "ld.hu.usr",	"d,1[2]")
+  _MC88xxx(0xf4001500, "ld.usr",	"d,1,2")
+  _MC88xxx(0xf4001700, "ld.usr",	"d,1[2]")
+  _MC88xxx(0xf4003600, "lda",		"d,1[2]")
+  _MC88xxx(0xf4006000, "lda",		"?d,1,2")	/* Output addu */
+  _MC88xxx(0x60000000, "lda",		"?d,1,I")	/* Output addu */
+  _MC88xxx(0xf4006000, "lda.b",		"?d,1[2]")	/* Output addu */
+  _MC88xxx(0xf4006000, "lda.b",		"?d,1,2")	/* Output addu */
+  _MC88xxx(0x60000000, "lda.b",		"?d,1,I")	/* Output addu */
+  _MC88xxx(0xf4003200, "lda.d",		"d,1[2]")
+  _MC88xxx(0xf4006000, "lda.d",		"?d,1,2")	/* Output addu */
+  _MC88xxx(0x60000000, "lda.d",		"?d,1,I")	/* Output addu */
+  _MC88xxx(0xf4003a00, "lda.h",		"d,1[2]")
+  _MC88xxx(0xf4006000, "lda.h",		"?d,1,2")	/* Output addu */
+  _MC88xxx(0x60000000, "lda.h",		"?d,1,I")	/* Output addu */
+  _MC88xxx(0x80004000, "ldcr",		"d,c")
+  _MC88xxx(0xf400a000, "mak",		"d,1,2")
+  _MC88xxx(0xf000a000, "mak",		"d,1,b")
+  _MC88xxx(0x48000000, "mask",		"d,1,I")
+  _MC88xxx(0x4c000000, "mask.u",	"d,1,I")
+  _MC88xxx(0xf4006c00, "mul",		"d,1,2")
+  _MC88xxx(0x6c000000, "mul",		"d,1,I")
+  _MC88xxx(0xf4006c00, "mulu",		"d,1,2")	/* synonym for mul */
+  _MC88xxx(0x6c000000, "mulu",		"d,1,I") 	/* synonym for mul */
+  _MC88xxx(0x84005080, "nint.sd",	"d,2")
+  _MC88xxx(0x84005000, "nint.ss",	"d,2")
+  _MC88xxx(0xf4005800, "or",		"d,1,2")
+  _MC88xxx(0x58000000, "or",		"d,1,I")
+  _MC88xxx(0xf4005c00, "or.c",		"d,1,2")
+  _MC88xxx(0x5c000000, "or.u",		"d,1,I")
+  _MC88xxx(0xf000a800, "rot",		"d,1,b")
+  _MC88xxx(0xf400a800, "rot",		"d,1,2")
+  _MC88xxx(0xf400fc00, "rte",		"")
+  _MC88xxx(0xf4008800, "set",		"d,1,2")
+  _MC88xxx(0xf0008800, "set",		"d,1,b")
+  _MC88xxx(0xf4002600, "st",		"d,1[2]")
+  _MC88xxx(0xf4002400, "st",		"d,1,2")
+  _MC88xxx(0x24000000, "st",		"d,1,I")
+  _MC88xxx(0xf4002e00, "st.b",		"d,1[2]")
+  _MC88xxx(0xf4002c00, "st.b",		"d,1,2")
+  _MC88xxx(0x2c000000, "st.b",		"d,1,I")
+  _MC88xxx(0xf4002d00, "st.b.usr",	"d,1,2")
+  _MC88xxx(0xf4002f00, "st.b.usr",	"d,1[2]")
+  _MC88xxx(0xf4002200, "st.d",		"d,1[2]")
+  _MC88xxx(0xf4002000, "st.d",		"d,1,2")
+  _MC88xxx(0x20000000, "st.d",		"d,1,I")
+  _MC88xxx(0xf4002100, "st.d.usr",	"d,1,2")
+  _MC88xxx(0xf4002300, "st.d.usr",	"d,1[2]")
+  _MC88xxx(0xf4002a00, "st.h",		"d,1[2]")
+  _MC88xxx(0xf4002800, "st.h",		"d,1,2")
+  _MC88xxx(0x28000000, "st.h",		"d,1,I")
+  _MC88xxx(0xf4002900, "st.h.usr",	"d,1,2")
+  _MC88xxx(0xf4002b00, "st.h.usr",	"d,1[2]")
+  _MC88xxx(0xf4002500, "st.usr",	"d,1,2")
+  _MC88xxx(0xf4002700, "st.usr",	"d,1[2]")
+  _MC88xxx(0x80008000, "stcr",		"3,c")
+  _MC88xxx(0xf4007400, "sub",		"d,1,2")
+  _MC88xxx(0x74000000, "sub",		"d,1,I")
+  _MC88xxx(0xf4007600, "sub.ci",	"d,1,2")
+  _MC88xxx(0xf4007700, "sub.cio",	"d,1,2")
+  _MC88xxx(0xf4007500, "sub.co",	"d,1,2")
+  _MC88xxx(0xf4006400, "subu",		"d,1,2")
+  _MC88xxx(0x64000000, "subu",		"d,1,I")
+  _MC88xxx(0xf4006600, "subu.ci",	"d,1,2")
+  _MC88xxx(0xf4006700, "subu.cio",	"d,1,2")
+  _MC88xxx(0xf4006500, "subu.co",	"d,1,2")
+  _MC88xxx(0xf000d000, "tb0",		"B,1,V")
+  _MC88xxx(0xf000d800, "tb1",		"B,1,V")
+  _MC88xxx(0xf400f800, "tbnd",		"1,2")
+  _MC88xxx(0xf8000000, "tbnd",		"1,I")
+  _MC88xxx(0xf000e800, "tcnd",		"M,1,V")
+  _MC88xxx(0x84005880, "trnc.sd",	"d,2")
+  _MC88xxx(0x84005800, "trnc.ss",	"d,2")
+  _MC88xxx(0x8000c000, "xcr",		"d,1,c")
+  _MC88xxx(0xf4000600, "xmem",		"d,1[2]")
+  _MC88xxx(0xf4000400, "xmem",		"d,1,2")
+  _MC88100(0x04000000, "xmem",		"?d,1,I")
+  _MC88xxx(0xf4000200, "xmem.bu",	"d,1[2]")
+  _MC88xxx(0xf4000000, "xmem.bu",	"d,1,2")
+  _MC88100(0x00000000, "xmem.bu",	"?d,1,I")
+  _MC88xxx(0xf4000300, "xmem.bu.usr",	"d,1[2]")
+  _MC88xxx(0xf4000100, "xmem.bu.usr",	"d,1,2")
+  _MC88100(0x00000100, "xmem.bu.usr",	"?d,1,I")
+  _MC88xxx(0xf4000700, "xmem.usr",	"d,1[2]")
+  _MC88xxx(0xf4000500, "xmem.usr",	"d,1,2")
+  _MC88100(0x04000100, "xmem.usr",	"?d,1,I")
+  _MC88xxx(0xf4005000, "xor",		"d,1,2")
+  _MC88xxx(0x50000000, "xor",		"d,1,I")
+  _MC88xxx(0xf4005400, "xor.c",		"d,1,2")
+  _MC88xxx(0x54000000, "xor.u",		"d,1,I")
+  _MC88xxx(0x00000000, "",	    0)
+};
+
+#define NUMOPCODES ((sizeof m88k_opcodes)/(sizeof m88k_opcodes[0]))
diff --git a/gnu/usr.bin/gas/opcode/mips.h b/gnu/usr.bin/gas/opcode/mips.h
new file mode 100644
index 00000000000..a65678a941d
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/mips.h
@@ -0,0 +1,363 @@
+/* Mips opcde list for GDB, the GNU debugger.
+   Copyright (C) 1989 Free Software Foundation, Inc.
+   Contributed by Nobuyuki Hikichi(hikichi@sra.junet)
+   Made to work for little-endian machines, and debugged
+   by Per Bothner (bothner@cs.wisc.edu).
+   Many fixes contributed by Frank Yellin (fy@lucid.com).
+
+This file is part of GDB.
+
+GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#if BITS_BIG_ENDIAN
+#define BIT_FIELDS_2(a,b) a;b;
+#define BIT_FIELDS_4(a,b,c,d) a;b;c;d;
+#define BIT_FIELDS_6(a,b,c,d,e,f) a;b;c;d;e;f;
+#else
+#define BIT_FIELDS_2(a,b) b;a;
+#define BIT_FIELDS_4(a,b,c,d) d;c;b;a;
+#define BIT_FIELDS_6(a,b,c,d,e,f) f;e;d;c;b;a;
+#endif
+
+struct op_i_fmt
+{
+BIT_FIELDS_4(
+  unsigned op : 6,
+  unsigned rs : 5,
+  unsigned rt : 5,
+  unsigned immediate : 16)
+};
+
+struct op_j_fmt
+{
+BIT_FIELDS_2(
+  unsigned op : 6,
+  unsigned target : 26)
+};
+
+struct op_r_fmt
+{
+BIT_FIELDS_6(
+  unsigned op : 6,
+  unsigned rs : 5,
+  unsigned rt : 5,
+  unsigned rd : 5,
+  unsigned shamt : 5,
+  unsigned funct : 6)
+};
+
+
+struct fop_i_fmt
+{
+BIT_FIELDS_4(
+  unsigned op : 6,
+  unsigned rs : 5,
+  unsigned rt : 5,
+  unsigned immediate : 16)
+};
+
+struct op_b_fmt
+{
+BIT_FIELDS_4(
+  unsigned op : 6,
+  unsigned rs : 5,
+  unsigned rt : 5,
+  short delta : 16)
+};
+
+struct fop_r_fmt
+{
+BIT_FIELDS_6(
+  unsigned op : 6,
+  unsigned fmt : 5,
+  unsigned ft : 5,
+  unsigned fs : 5,
+  unsigned fd : 5,
+  unsigned funct : 6)
+};
+
+struct mips_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long match;
+  char *args;
+  int bdelay; /* Nonzero if delayed branch.  */
+};
+
+/* args format;
+
+   "s" rs: source register specifier
+   "t" rt: target register
+   "i" immediate
+   "a" target address
+   "c" branch condition
+   "d" rd: destination register specifier
+   "h" shamt: shift amount
+   "f" funct: function field
+
+  for fpu
+   "S" fs source 1 register
+   "T" ft source 2 register
+   "D" distination register
+*/
+
+#define one(x) (x << 26)
+#define op_func(x, y) ((x << 26) | y)
+#define op_cond(x, y) ((x << 26) | (y << 16))
+#define op_rs_func(x, y, z) ((x << 26) | (y << 21) | z)
+#define op_rs_b11(x, y, z) ((x << 26) | (y << 21) | z)
+#define op_o16(x, y) ((x << 26) | (y << 16))
+#define op_bc(x, y, z) ((x << 26) | (y << 21) | (z << 16))
+
+struct mips_opcode mips_opcodes[] = 
+{
+/* These first opcodes are special cases of the ones in the comments */
+  {"nop",	0,		0xffffffff,	     /*li*/	"", 0},
+  {"li",	op_bc(9,0,0),	op_bc(0x3f,31,0),    /*addiu*/	"t,j", 0},
+  {"b",		one(4),		0xffff0000,	     /*beq*/	"b", 1},
+  {"move",	op_func(0, 33),	op_cond(0x3f,31)|0x7ff,/*addu*/	"d,s", 0},
+
+  {"sll",	op_func(0, 0),	op_func(0x3f, 0x3f),		"d,t,h", 0},
+  {"srl",	op_func(0, 2),	op_func(0x3f, 0x3f),		"d,t,h", 0},
+  {"sra",	op_func(0, 3),	op_func(0x3f, 0x3f),		"d,t,h", 0},
+  {"sllv",	op_func(0, 4),	op_func(0x3f, 0x7ff),		"d,t,s", 0},
+  {"srlv",	op_func(0, 6),	op_func(0x3f, 0x7ff),		"d,t,s", 0},
+  {"srav",	op_func(0, 7),	op_func(0x3f, 0x7ff),		"d,t,s", 0},
+  {"jr",	op_func(0, 8),	op_func(0x3f, 0x1fffff),	"s", 1},
+  {"jalr",	op_func(0, 9),	op_func(0x3f, 0x1f07ff),	"d,s", 1},
+  {"syscall",	op_func(0, 12),	op_func(0x3f, 0x3f),		"", 0},
+  {"break",	op_func(0, 13),	op_func(0x3f, 0x3f),		"", 0},
+  {"mfhi",      op_func(0, 16), op_func(0x3f, 0x03ff07ff),      "d", 0},
+  {"mthi",      op_func(0, 17), op_func(0x3f, 0x1fffff),        "s", 0},
+  {"mflo",      op_func(0, 18), op_func(0x3f, 0x03ff07ff),      "d", 0},
+  {"mtlo",      op_func(0, 19), op_func(0x3f, 0x1fffff),        "s", 0},
+  {"mult",	op_func(0, 24),	op_func(0x3f, 0xffff),		"s,t", 0},
+  {"multu",	op_func(0, 25),	op_func(0x3f, 0xffff),		"s,t", 0},
+  {"div",	op_func(0, 26),	op_func(0x3f, 0xffff),		"s,t", 0},
+  {"divu",	op_func(0, 27),	op_func(0x3f, 0xffff),		"s,t", 0},
+  {"add",	op_func(0, 32),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"addu",	op_func(0, 33),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"sub",	op_func(0, 34),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"subu",	op_func(0, 35),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"and",	op_func(0, 36),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"or",	op_func(0, 37),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"xor",	op_func(0, 38),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"nor",	op_func(0, 39),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"slt",	op_func(0, 42),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+  {"sltu",	op_func(0, 43),	op_func(0x3f, 0x7ff),		"d,s,t", 0},
+
+  {"bltz",	op_cond (1, 0),	op_cond(0x3f, 0x1f),		"s,b", 1},
+  {"bgez",	op_cond (1, 1),	op_cond(0x3f, 0x1f),		"s,b", 1},
+  {"bltzal",	op_cond (1, 16),op_cond(0x3f, 0x1f),		"s,b", 1},
+  {"bgezal",	op_cond (1, 17),op_cond(0x3f, 0x1f),		"s,b", 1},
+
+
+  {"j",		one(2),		one(0x3f),			"a", 1},
+  {"jal",	one(3),		one(0x3f),			"a", 1},
+  {"beq",	one(4),		one(0x3f),			"s,t,b", 1},
+  {"bne",	one(5),		one(0x3f),			"s,t,b", 1},
+  {"blez",	one(6),		one(0x3f) | 0x1f0000,		"s,b", 1},
+  {"bgtz",	one(7),		one(0x3f) | 0x1f0000,		"s,b", 1},
+  {"addi",	one(8),		one(0x3f),			"t,s,j", 0},
+  {"addiu",	one(9),		one(0x3f),			"t,s,j", 0},
+  {"slti",	one(10),	one(0x3f),			"t,s,j", 0},
+  {"sltiu",	one(11),	one(0x3f),			"t,s,j", 0},
+  {"andi",	one(12),	one(0x3f),			"t,s,i", 0},
+  {"ori",	one(13),	one(0x3f),			"t,s,i", 0},
+  {"xori",	one(14),	one(0x3f),			"t,s,i", 0},
+	/* rs field is don't care field? */
+  {"lui",	one(15),	one(0x3f),			"t,i", 0},
+
+/* co processor 0 instruction */
+  {"mfc0",	op_rs_b11 (16, 0, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"cfc0",	op_rs_b11 (16, 2, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"mtc0",	op_rs_b11 (16, 4, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"ctc0",	op_rs_b11 (16, 6, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+
+  {"bc0f",	op_o16(16, 0x100),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc0f",	op_o16(16, 0x180),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc0t",	op_o16(16, 0x101),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc0t",	op_o16(16, 0x181),	op_o16(0x3f, 0x3ff),	"b", 1},
+
+  {"tlbr",	op_rs_func(16, 0x10, 1), ~0, "", 0},
+  {"tlbwi",	op_rs_func(16, 0x10, 2), ~0, "", 0},
+  {"tlbwr",	op_rs_func(16, 0x10, 6), ~0, "", 0},
+  {"tlbp",	op_rs_func(16, 0x10, 8), ~0, "", 0},
+  {"rfe",	op_rs_func(16, 0x10, 16), ~0, "", 0},
+
+  {"mfc1",	op_rs_b11 (17, 0, 0),	op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
+  {"cfc1",	op_rs_b11 (17, 2, 0),	op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
+  {"mtc1",	op_rs_b11 (17, 4, 0),	op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
+  {"ctc1",	op_rs_b11 (17, 6, 0),	op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
+
+  {"bc1f",	op_o16(17, 0x100),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc1f",	op_o16(17, 0x180),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc1t",	op_o16(17, 0x101),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc1t",	op_o16(17, 0x181),	op_o16(0x3f, 0x3ff),	"b", 1},
+
+/* fpu instruction */
+  {"add.s",	op_rs_func(17, 0x10, 0),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"add.d",	op_rs_func(17, 0x11, 0),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"sub.s",	op_rs_func(17, 0x10, 1),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"sub.d",	op_rs_func(17, 0x11, 1),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"mul.s",	op_rs_func(17, 0x10, 2),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"mul.d",	op_rs_func(17, 0x11, 2),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"div.s",	op_rs_func(17, 0x10, 3),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"div.d",	op_rs_func(17, 0x11, 3),
+			op_rs_func(0x3f, 0x1f, 0x3f),	"D,S,T", 0},
+  {"abs.s",	op_rs_func(17, 0x10, 5),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"abs.d",	op_rs_func(17, 0x11, 5),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"mov.s",	op_rs_func(17, 0x10, 6),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"mov.d",	op_rs_func(17, 0x11, 6),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"neg.s",	op_rs_func(17, 0x10, 7),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"neg.d",	op_rs_func(17, 0x11, 7),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.s.s",	op_rs_func(17, 0x10, 32),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.s.d",	op_rs_func(17, 0x11, 32),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.s.w",	op_rs_func(17, 0x14, 32),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.d.s",	op_rs_func(17, 0x10, 33),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.d.d",	op_rs_func(17, 0x11, 33),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.d.w",	op_rs_func(17, 0x14, 33),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.w.s",	op_rs_func(17, 0x10, 36),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"cvt.w.d",	op_rs_func(17, 0x11, 36),
+			op_rs_func(0x3f, 0x1f, 0x1f003f),	"D,S", 0},
+  {"c.f.s",	op_rs_func(17, 0x10, 48),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.f.d",	op_rs_func(17, 0x11, 48),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.un.s",	op_rs_func(17, 0x10, 49),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.un.d",	op_rs_func(17, 0x11, 49),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.eq.s",	op_rs_func(17, 0x10, 50),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.eq.d",	op_rs_func(17, 0x11, 50),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ueq.s",	op_rs_func(17, 0x10, 51),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ueq.d",	op_rs_func(17, 0x11, 51),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.olt.s",	op_rs_func(17, 0x10, 52),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.olt.d",	op_rs_func(17, 0x11, 52),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ult.s",	op_rs_func(17, 0x10, 53),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ult.d",	op_rs_func(17, 0x11, 53),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ole.s",	op_rs_func(17, 0x10, 54),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ole.d",	op_rs_func(17, 0x11, 54),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ule.s",	op_rs_func(17, 0x10, 55),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ule.d",	op_rs_func(17, 0x11, 55),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.sf.s",	op_rs_func(17, 0x10, 56),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.sf.d",	op_rs_func(17, 0x11, 56),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngle.s",	op_rs_func(17, 0x10, 57),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngle.d",	op_rs_func(17, 0x11, 57),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.seq.s",	op_rs_func(17, 0x10, 58),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.seq.d",	op_rs_func(17, 0x11, 58),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngl.s",	op_rs_func(17, 0x10, 59),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngl.d",	op_rs_func(17, 0x11, 59),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.lt.s",	op_rs_func(17, 0x10, 60),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.lt.d",	op_rs_func(17, 0x11, 60),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.nge.s",	op_rs_func(17, 0x10, 61),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.nge.d",	op_rs_func(17, 0x11, 61),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.le.s",	op_rs_func(17, 0x10, 62),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.le.d",	op_rs_func(17, 0x11, 62),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngt.s",	op_rs_func(17, 0x10, 63),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+  {"c.ngt.d",	op_rs_func(17, 0x11, 63),
+			op_rs_func(0x3f, 0x1f, 0x7ff),	"S,T", 0},
+
+/* co processor 2 instruction */
+  {"mfc2",	op_rs_b11 (18, 0, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"cfc2",	op_rs_b11 (18, 2, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"mtc2",	op_rs_b11 (18, 4, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"ctc2",	op_rs_b11 (18, 6, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"bc2f",	op_o16(18, 0x100),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc2f",	op_o16(18, 0x180),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc2f",	op_o16(18, 0x101),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc2t",	op_o16(18, 0x181),	op_o16(0x3f, 0x3ff),	"b", 1},
+
+/* co processor 3 instruction */
+  {"mtc3",	op_rs_b11 (19, 0, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"cfc3",	op_rs_b11 (19, 2, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"mtc3",	op_rs_b11 (19, 4, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"ctc3",	op_rs_b11 (19, 6, 0),	op_rs_b11(0x3f, 0x1f, 0x1ffff),	"t,d", 0},
+  {"bc3f",	op_o16(19, 0x100),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc3f",	op_o16(19, 0x180),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc3t",	op_o16(19, 0x101),	op_o16(0x3f, 0x3ff),	"b", 1},
+  {"bc3t",	op_o16(19, 0x181),	op_o16(0x3f, 0x3ff),	"b", 1},
+
+  {"lb",	one(32),	one(0x3f),		"t,j(s)", 0},
+  {"lh",	one(33),	one(0x3f),		"t,j(s)", 0},
+  {"lwl",	one(34),	one(0x3f),		"t,j(s)", 0},
+  {"lw",	one(35),	one(0x3f),		"t,j(s)", 0},
+  {"lbu",	one(36),	one(0x3f),		"t,j(s)", 0},
+  {"lhu",	one(37),	one(0x3f),		"t,j(s)", 0},
+  {"lwr",	one(38),	one(0x3f),		"t,j(s)", 0},
+  {"sb",	one(40),	one(0x3f),		"t,j(s)", 0},
+  {"sh",	one(41),	one(0x3f),		"t,j(s)", 0},
+  {"swl",	one(42),	one(0x3f),		"t,j(s)", 0},
+  {"swr",       one(46),        one(0x3f),              "t,j(s)", 0},
+  {"sw",	one(43),	one(0x3f),		"t,j(s)", 0},
+  {"lwc0",	one(48),	one(0x3f),		"t,j(s)", 0},
+/* for fpu */
+  {"lwc1",	one(49),	one(0x3f),		"T,j(s)", 0},
+  {"lwc2",	one(50),	one(0x3f),		"t,j(s)", 0},
+  {"lwc3",	one(51),	one(0x3f),		"t,j(s)", 0},
+  {"swc0",	one(56),	one(0x3f),		"t,j(s)", 0},
+/* for fpu */
+  {"swc1",	one(57),	one(0x3f),		"T,j(s)", 0},
+  {"swc2",	one(58),	one(0x3f),		"t,j(s)", 0},
+  {"swc3",	one(59),	one(0x3f),		"t,j(s)", 0},
+};
diff --git a/gnu/usr.bin/gas/opcode/np1.h b/gnu/usr.bin/gas/opcode/np1.h
new file mode 100644
index 00000000000..654682570fa
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/np1.h
@@ -0,0 +1,422 @@
+/* Print GOULD NPL instructions for GDB, the GNU debugger.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction. */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...
+*/
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+struct gld_opcode gld_opcodes[] =
+{
+{ "lb",		0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lbs",	0xec080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lh",		0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lw",		0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ld",		0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "li",		0xf8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lpa",	0x50080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "la",		0x50000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lbp",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lhp",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lwp",	0x90000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ldp",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lf",		0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr",	0xbc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lwbr",	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0xdc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "zmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stbp",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sthp",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stwp",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stdp",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lil",	0xf80b0000,	0xfc7f0000,	"r,D",		4 },
+{ "lwsl1",	0xec000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl2",	0xfc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl3",	0xfc080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "lvb",	0xb0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvh",	0xb0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "lvw",	0xb0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvd",	0xb0000002,	0xfc080002,	"v,xOA,X",	4 },
+{ "liv",	0x3c040000,	0xfc0f0000,	"v,R",		2 },
+{ "livf",	0x3c080000,	0xfc0f0000,	"v,R",		2 },
+{ "stvb",	0xd0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvh",	0xd0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "stvw",	0xd0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvd",	0xd0000002,	0xfc080002,	"v,xOA,X",	4 },
+
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnd",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trabs",	0x2c010000,	0xfc0f0000,	"r,R",		2 },
+{ "trabsd",	0x2c090000,	0xfc0f0000,	"r,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "xcr",	0x28040000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcr",	0x2c060000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcrd",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "trbr",	0x28030000,	0xfc0f0000,	"b,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "tbrbr",	0x28010000,	0xfc0f0000,	"b,B",		2 },
+
+{ "trvv",	0x28050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvn",	0x2c050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvnd",	0x2c0d0000,	0xfc0f0000,	"v,V",		2 },
+{ "trvab",	0x2c070000,	0xfc0f0000,	"v,V",		2 },
+{ "trvabd",	0x2c0f0000,	0xfc0f0000,	"v,V",		2 },
+{ "cmpv",	0x14060000,	0xfc0f0000,	"v,V",		2 },
+{ "expv",	0x14070000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvlt",	0x10030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvle",	0x10040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvgt",	0x14030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvge",	0x14040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvveq",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvne",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvrlt",	0x100d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrle",	0x100e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrgt",	0x140d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrge",	0x140e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvreq",	0x100f0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrne",	0x140f0000,	0xfc0f0000,	"v,R",		2 },
+{ "trvr",	0x140b0000,	0xfc0f0000,	"r,V",		2 },
+{ "trrv",	0x140c0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "bu",		0x40000000,	0xff880000,	"xOA,X",	4 },
+{ "bns",	0x70080000,	0xff880000,	"xOA,X",	4 },
+{ "bnco",	0x70880000,	0xff880000,	"xOA,X",	4 },
+{ "bge",	0x71080000,	0xff880000,	"xOA,X",	4 },
+{ "bne",	0x71880000,	0xff880000,	"xOA,X",	4 },
+{ "bunge",	0x72080000,	0xff880000,	"xOA,X",	4 },
+{ "bunle",	0x72880000,	0xff880000,	"xOA,X",	4 },
+{ "bgt",	0x73080000,	0xff880000,	"xOA,X",	4 },
+{ "bnany",	0x73880000,	0xff880000,	"xOA,X",	4 },
+{ "bs"	,	0x70000000,	0xff880000,	"xOA,X",	4 },
+{ "bco",	0x70800000,	0xff880000,	"xOA,X",	4 },
+{ "blt",	0x71000000,	0xff880000,	"xOA,X",	4 },
+{ "beq",	0x71800000,	0xff880000,	"xOA,X",	4 },
+{ "buge",	0x72000000,	0xff880000,	"xOA,X",	4 },
+{ "bult",	0x72800000,	0xff880000,	"xOA,X",	4 },
+{ "ble",	0x73000000,	0xff880000,	"xOA,X",	4 },
+{ "bany",	0x73800000,	0xff880000,	"xOA,X",	4 },
+{ "brlnk",	0x44000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bib",	0x48000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bih",	0x48080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "biw",	0x4c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bid",	0x4c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivb",	0x60000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivh",	0x60080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivw",	0x64000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivd",	0x64080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsb",	0x68000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsh",	0x68080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsw",	0x6c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsd",	0x6c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "camb",	0x80080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camh",	0x80000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x80000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "card",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "ci",		0xf8050000,	0xfc7f0000,	"r,I",		4 },
+{ "chkbnd",	0x5c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "cavv",	0x10010000,	0xfc0f0000,	"v,V",		2 },
+{ "cavr",	0x10020000,	0xfc0f0000,	"v,R",		2 },
+{ "cavvd",	0x10090000,	0xfc0f0000,	"v,V",		2 },
+{ "cavrd",	0x100b0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "ani",	0xf8080000,	0xfc7f0000,	"r,I",		4 },
+{ "ormb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "oi",		0xf8090000,	0xfc7f0000,	"r,I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eoi",	0xf80a0000,	0xfc7f0000,	"r,I",		4 },
+
+{ "anvv",	0x04010000,	0xfc0f0000,	"v,V",		2 },
+{ "anvr",	0x04020000,	0xfc0f0000,	"v,R",		2 },
+{ "orvv",	0x08010000,	0xfc0f0000,	"v,V",		2 },
+{ "orvr",	0x08020000,	0xfc0f0000,	"v,R",		2 },
+{ "eovv",	0x0c010000,	0xfc0f0000,	"v,V",		2 },
+{ "eovr",	0x0c020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sacz",	0x100c0000,	0xfc0f0000,	"r,R",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "sda",	0x3c030000,	0xfc0f0000,	"r,R",		2 },
+{ "sdl",	0x3c020000,	0xfc0f0000,	"r,R",		2 },
+{ "sdc",	0x3c010000,	0xfc0f0000,	"r,R",		2 },
+{ "sdad",	0x3c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sdld",	0x3c0a0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "svda",	0x3c070000,	0xfc0f0000,	"v,R",		2 },
+{ "svdl",	0x3c060000,	0xfc0f0000,	"v,R",		2 },
+{ "svdc",	0x3c050000,	0xfc0f0000,	"v,R",		2 },
+{ "svdad",	0x3c0e0000,	0xfc0f0000,	"v,R",		2 },
+{ "svdld",	0x3c0d0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sbm",	0xac080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbm",	0xac000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbm",	0xa8080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "incmb",	0xa0000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmh",	0xa0080000,	0xfc080000,	"xOA,X",	4 },
+{ "incmw",	0xa4000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmd",	0xa4080000,	0xfc080000,	"xOA,X",	4 },
+{ "sbmd",	0x7c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zbmd",	0x7c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "tbmd",	0x78080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "ssm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zsm",	0x9c000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tsm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+
+{ "admb",	0xc8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admh",	0xc8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xc8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xc8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adi",	0xf8010000,	0xfc0f0000,	"r,I",		4 },
+{ "sumb",	0xcc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumh",	0xcc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xcc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "sui",	0xf8020000,	0xfc0f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprd",	0x3c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpi",	0xf8030000,	0xfc0f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvi",	0xf8040000,	0xfc0f0000,	"r,I",		4 },
+{ "exs",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+
+{ "advv",	0x30000000,	0xfc0f0000,	"v,V",		2 },
+{ "advvd",	0x30080000,	0xfc0f0000,	"v,V",		2 },
+{ "adrv",	0x34000000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvd",	0x34080000,	0xfc0f0000,	"v,R",		2 },
+{ "suvv",	0x30010000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvd",	0x30090000,	0xfc0f0000,	"v,V",		2 },
+{ "surv",	0x34010000,	0xfc0f0000,	"v,R",		2 },
+{ "survd",	0x34090000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvv",	0x30020000,	0xfc0f0000,	"v,V",		2 },
+{ "mprv",	0x34020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "surfw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "surfd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "rfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "rfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "rrfw",	0x0c0e0000,	0xfc0f0000,	"r",		2 },
+{ "rrfd",	0x0c0f0000,	0xfc0f0000,	"r",		2 },
+
+{ "advvfw",	0x30040000,	0xfc0f0000,	"v,V",		2 },
+{ "advvfd",	0x300c0000,	0xfc0f0000,	"v,V",		2 },
+{ "adrvfw",	0x34040000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvfd",	0x340c0000,	0xfc0f0000,	"v,R",		2 },
+{ "suvvfw",	0x30050000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvfd",	0x300d0000,	0xfc0f0000,	"v,V",		2 },
+{ "survfw",	0x34050000,	0xfc0f0000,	"v,R",		2 },
+{ "survfd",	0x340d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvvfw",	0x30060000,	0xfc0f0000,	"v,V",		2 },
+{ "mpvvfd",	0x300e0000,	0xfc0f0000,	"v,V",		2 },
+{ "mprvfw",	0x34060000,	0xfc0f0000,	"v,R",		2 },
+{ "mprvfd",	0x340e0000,	0xfc0f0000,	"v,R",		2 },
+{ "rvfw",	0x30070000,	0xfc0f0000,	"v",		2 },
+{ "rvfd",	0x300f0000,	0xfc0f0000,	"v",		2 },
+
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "cfpds",	0x3c090000,	0xfc0f0000,	"r,R",		2 },
+
+{ "fltvw",	0x080d0000,	0xfc0f0000,	"v,V",		2 },
+{ "fltvd",	0x080f0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvw",	0x080c0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvd",	0x080e0000,	0xfc0f0000,	"v,V",		2 },
+{ "cfpvds",	0x0c0d0000,	0xfc0f0000,	"v,V",		2 },
+
+{ "orvrn",	0x000a0000,	0xfc0f0000,	"r,V",		2 },
+{ "andvrn",	0x00080000,	0xfc0f0000,	"r,V",		2 },
+{ "frsteq",	0x04090000,	0xfc0f0000,	"r,V",		2 },
+{ "sigma",	0x0c080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmad",	0x0c0a0000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmf",	0x08080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmfd",	0x080a0000,	0xfc0f0000,	"r,V",		2 },
+{ "prodf",	0x04080000,	0xfc0f0000,	"r,V",		2 },
+{ "prodfd",	0x040a0000,	0xfc0f0000,	"r,V",		2 },
+{ "maxv",	0x10080000,	0xfc0f0000,	"r,V",		2 },
+{ "maxvd",	0x100a0000,	0xfc0f0000,	"r,V",		2 },
+{ "minv",	0x14080000,	0xfc0f0000,	"r,V",		2 },
+{ "minvd",	0x140a0000,	0xfc0f0000,	"r,V",		2 },
+
+{ "lpsd",	0xf0000000,	0xfc080000,	"xOA,X",	4 },
+{ "ldc",	0xf0080000,	0xfc080000,	"xOA,X",	4 },
+{ "spm",	0x040c0000,	0xfc0f0000,	"r",		2 },
+{ "rpm",	0x040d0000,	0xfc0f0000,	"r",		2 },
+{ "tritr",	0x00070000,	0xfc0f0000,	"r",		2 },
+{ "trrit",	0x00060000,	0xfc0f0000,	"r",		2 },
+{ "rpswt",	0x04080000,	0xfc0f0000,	"r",		2 },
+{ "exr",	0xf8070000,	0xfc0f0000,	"",		4 },
+{ "halt",	0x00000000,	0xfc0f0000,	"",		2 },
+{ "wait",	0x00010000,	0xfc0f0000,	"",		2 },
+{ "nop",	0x00020000,	0xfc0f0000,	"",		2 },
+{ "eiae",	0x00030000,	0xfc0f0000,	"",		2 },
+{ "efae",	0x000d0000,	0xfc0f0000,	"",		2 },
+{ "diae",	0x000e0000,	0xfc0f0000,	"",		2 },
+{ "dfae",	0x000f0000,	0xfc0f0000,	"",		2 },
+{ "spvc",	0xf8060000,	0xfc0f0000,	"r,T,N",	4 },
+{ "rdsts",	0x00090000,	0xfc0f0000,	"r",		2 },
+{ "setcpu",	0x000c0000,	0xfc0f0000,	"r",		2 },
+{ "cmc",	0x000b0000,	0xfc0f0000,	"r",		2 },
+{ "trrcu",	0x00040000,	0xfc0f0000,	"r",		2 },
+{ "attnio",	0x00050000,	0xfc0f0000,	"",		2 },
+{ "fudit",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "break",	0x28090000,	0xfc0f0000,	"",		2 },
+{ "frzss",	0x280a0000,	0xfc0f0000,	"",		2 },
+{ "ripi",	0x04040000,	0xfc0f0000,	"r,R",		2 },
+{ "xcp",	0x04050000,	0xfc0f0000,	"r",		2 },
+{ "block",	0x04060000,	0xfc0f0000,	"",		2 },
+{ "unblock",	0x04070000,	0xfc0f0000,	"",		2 },
+{ "trsc",	0x08060000,	0xfc0f0000,	"r,R",		2 },
+{ "tscr",	0x08070000,	0xfc0f0000,	"r,R",		2 },
+{ "fq",		0x04080000,	0xfc0f0000,	"r",		2 },
+{ "flupte",	0x2c080000,	0xfc0f0000,	"r",		2 },
+{ "rviu",	0x040f0000,	0xfc0f0000,	"",		2 },
+{ "ldel",	0x280c0000,	0xfc0f0000,	"r,R",		2 },
+{ "ldu",	0x280d0000,	0xfc0f0000,	"r,R",		2 },
+{ "stdecc",	0x280b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trpc",	0x08040000,	0xfc0f0000,	"r",		2 },
+{ "tpcr",	0x08050000,	0xfc0f0000,	"r",		2 },
+{ "ghalt",	0x0c050000,	0xfc0f0000,	"r",		2 },
+{ "grun",	0x0c040000,	0xfc0f0000,	"",		2 },
+{ "tmpr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "trmp",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "trrve",	0x28060000,	0xfc0f0000,	"r",		2 },
+{ "trver",	0x28070000,	0xfc0f0000,	"r",		2 },
+{ "trvlr",	0x280f0000,	0xfc0f0000,	"r",		2 },
+
+{ "linkfl",	0x18000000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbl",	0x18020000,	0xfc0f0000,	"r,R",		2 },
+{ "linkfp",	0x18010000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbp",	0x18030000,	0xfc0f0000,	"r,R",		2 },
+{ "linkpl",	0x18040000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkl",	0x18080000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkp",	0x18090000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktl",	0x180a0000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktp",	0x180b0000,	0xfc0f0000,	"r,R",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		 		sizeof(gld_opcodes[0]);
diff --git a/gnu/usr.bin/gas/opcode/ns32k.h b/gnu/usr.bin/gas/opcode/ns32k.h
new file mode 100644
index 00000000000..2a7621a9ca3
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/ns32k.h
@@ -0,0 +1,491 @@
+/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
+   Copyright (C) 1987 Free Software Foundation, Inc.
+
+This file is part of GAS, the GNU Assembler.
+
+GAS is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GAS is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+
+#ifdef TE_SEQUENT
+#define DEF_MODEC 20
+#define DEF_MODEL 21
+#endif
+
+#ifndef DEF_MODEC
+#define DEF_MODEC 20
+#endif
+
+#ifndef DEF_MODEL
+#define DEF_MODEL 20
+#endif
+/*
+   After deciding the instruction entry (via hash.c) the instruction parser
+   will try to match the operands after the instruction to the required set
+   given in the entry operandfield. Every operand will result in a change in
+   the opcode or the addition of data to the opcode.
+   The operands in the source instruction are checked for inconsistent
+   semantics.
+ 
+	F : 32 bit float	general form
+	L : 64 bit float	    "
+	B : byte		    "
+	W : word		    "
+	D : double-word		    "
+	Q : quad-word		    "
+	A : double-word		gen-address-form ie no regs allowed
+	d : displacement
+	b : displacement - pc relative addressing  acb
+	p : displacement - pc relative addressing  br bcond bsr cxp
+	q : quick
+	i : immediate (8 bits)
+	    This is not a standard ns32k operandtype, it is used to build
+	    instructions like    svc arg1,arg2
+	    Svc is the instruction SuperVisorCall and is sometimes used to
+	    call OS-routines from usermode. Some args might be handy!
+	r : register number (3 bits)
+	O : setcfg instruction optionslist
+	C : cinv instruction optionslist
+	S : stringinstruction optionslist
+	U : registerlist	save,enter
+	u : registerlist	restore,exit
+	M : mmu register
+	P : cpu register
+	g : 3:rd operand of inss or exts instruction
+	G : 4:th operand of inss or exts instruction
+	    Those operands are encoded in the same byte.
+	    This byte is placed last in the instruction.
+	f : operand of sfsr
+	H : sequent-hack for bsr (Warning)
+
+column	1 	instructions
+	2 	number of bits in opcode.
+	3 	number of bits in opcode explicitly
+		determined by the instruction type.
+	4 	opcodeseed, the number we build our opcode
+		from.
+	5 	operandtypes, used by operandparser.
+	6 	size in bytes of immediate
+*/
+struct ns32k_opcode {
+  char *name;
+  unsigned char opcode_id_size; /* not used by the assembler */
+  unsigned char opcode_size;
+  unsigned long opcode_seed;
+  char *operands;
+  unsigned char im_size;	/* not used by dissassembler */
+  char *default_args;		/* default to those args when none given */
+  char default_modec;		/* default to this addr-mode when ambigous
+				   ie when the argument of a general addr-mode
+				   is a plain constant */
+  char default_model;		/* is a plain label */
+};
+
+#ifdef comment
+/* This section was from the gdb version of this file. */
+
+#ifndef ns32k_opcodeT
+#define ns32k_opcodeT int
+#endif /* no ns32k_opcodeT */
+
+struct not_wot			/* ns32k opcode table: wot to do with this */
+				/* particular opcode */
+{
+  int obits;		/* number of opcode bits */
+  int ibits;		/* number of instruction bits */
+  ns32k_opcodeT	code;	/* op-code (may be > 8 bits!) */
+  char *args;		/* how to compile said opcode */
+};
+
+struct not			/* ns32k opcode text */
+{
+  char *            name;	/* opcode name: lowercase string  [key]  */
+  struct not_wot    detail;	/* rest of opcode table          [datum] */
+};
+
+/* Instructions look like this:
+    
+   basic instruction--1, 2, or 3 bytes
+   index byte for operand A, if operand A is indexed--1 byte
+   index byte for operand B, if operand B is indexed--1 byte
+   addressing extension for operand A
+   addressing extension for operand B
+   implied operands
+
+   Operand A is the operand listed first in the following opcode table.
+   Operand B is the operand listed second in the following opcode table.
+   All instructions have at most 2 general operands, so this is enough.
+   The implied operands are associated with operands other than A and B.
+
+   Each operand has a digit and a letter.
+   
+   The digit gives the position in the assembly language.  The letter,
+   one of the following, tells us what kind of operand it is.  */
+
+/* F : 32 bit float
+ * L : 64 bit float
+ * B : byte
+ * W : word
+ * D : double-word
+ * Q : quad-word
+ * d : displacement
+ * q : quick
+ * i : immediate (8 bits)
+ * r : register number (3 bits)
+ * p : displacement - pc relative addressing
+*/
+
+
+#endif /* comment */
+
+static const struct ns32k_opcode ns32k_opcodes[]=
+{
+  { "absf",	14,24,	0x35be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absl",	14,24,	0x34be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absb",	14,24,	0x304e, "1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absw",	14,24,	0x314e, "1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absd",	14,24,	0x334e, "1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbb",	 7,16,	0x4c,	"2B1q3p",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbw",	 7,16,	0x4d,	"2W1q3p",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbd",	 7,16,	0x4f,	"2D1q3p",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addf",	14,24,	0x01be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addl",	14,24,	0x00be, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addb",	 6,16,	0x00,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addw",	 6,16,	0x01,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addd",	 6,16,	0x03,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcb",	 6,16,	0x10,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcw",	 6,16,	0x11,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcd",	 6,16,	0x13,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpb",	14,24,	0x3c4e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpw",	14,24,	0x3d4e,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpd",	14,24,	0x3f4e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqb",	 7,16,	0x0c,	"2B1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqw",	 7,16,	0x0d,	"2W1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqd",	 7,16,	0x0f,	"2D1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addr",	 6,16,	0x27,	"1A2D",		4,	"",	21,21	},
+  { "adjspb",	11,16,	0x057c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "adjspw",	11,16,	0x057d,	"1W", 		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "adjspd",	11,16,	0x057f,	"1D", 		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andb",	 6,16,	0x28,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andw",	 6,16,	0x29,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andd",	 6,16,	0x2b,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashb",	14,24,	0x044e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashw",	14,24,	0x054e,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashd",	14,24,	0x074e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "beq",	 8,8,	0x0a,	"1p",		0,	"",	21,21	},
+  { "bne",	 8,8,	0x1a,	"1p",		0,	"",	21,21	},
+  { "bcs",	 8,8,	0x2a,	"1p",		0,	"",	21,21	},
+  { "bcc",	 8,8,	0x3a,	"1p",		0,	"",	21,21	},
+  { "bhi",	 8,8,	0x4a,	"1p",		0,	"",	21,21	},
+  { "bls",	 8,8,	0x5a,	"1p",		0,	"",	21,21	},
+  { "bgt",	 8,8,	0x6a,	"1p",		0,	"",	21,21	},
+  { "ble",	 8,8,	0x7a,	"1p",		0,	"",	21,21	},
+  { "bfs",	 8,8,	0x8a,	"1p",		0,	"",	21,21	},
+  { "bfc",	 8,8,	0x9a,	"1p",		0,	"",	21,21	},
+  { "blo",	 8,8,	0xaa,	"1p",		0,	"",	21,21	},
+  { "bhs",	 8,8,	0xba,	"1p",		0,	"",	21,21	},
+  { "blt",	 8,8,	0xca,	"1p",		0,	"",	21,21	},
+  { "bge",	 8,8,	0xda,	"1p",		0,	"",	21,21	},
+  { "but",	 8,8,	0xea,	"1p",		0,	"",	21,21	},
+  { "buf",	 8,8,	0xfa,	"1p",		0,	"",	21,21	},
+  { "bicb",	 6,16,	0x08,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicw",	 6,16,	0x09,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicd",	 6,16,	0x0b,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicpsrb",	11,16,	0x17c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicpsrw",	11,16,	0x17d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bispsrb",	11,16,	0x37c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bispsrw",	11,16,	0x37d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bpt",	 8,8,	0xf2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "br",	 8,8,	0xea,	"1p",		0,	"",	21,21	},
+#ifdef TE_SEQUENT
+  { "bsr",	 8,8,	0x02,	"1H",		0,	"",	21,21	},
+#else
+  { "bsr",	 8,8,	0x02,	"1p",		0,	"",	21,21	},
+#endif
+  { "caseb",	11,16,	0x77c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "casew",	11,16,	0x77d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cased",	11,16,	0x77f,	"1D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitb",	14,24,	0x084e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitw",	14,24,	0x094e,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitd",	14,24,	0x0b4e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitib",	14,24,	0x0c4e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitiw",	14,24,	0x0d4e,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitid",	14,24,	0x0f4e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkb",	11,24,	0x0ee,	"2A3B1r",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkw",	11,24,	0x1ee,	"2A3W1r",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkd",	11,24,	0x3ee,	"2A3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cinv",	14,24,	0x271e,	"2D1C",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpf",	14,24,	0x09be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpl",	14,24,	0x08be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpb",	 6,16,	0x04,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpw",	 6,16,	0x05,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpd",	 6,16,	0x07,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmb",	14,24,	0x04ce,	"1A2A3b",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmw",	14,24,	0x05ce,	"1A2A3b",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmd",	14,24,	0x07ce,	"1A2A3b",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqb",	 7,16,	0x1c,	"2B1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqw",	 7,16,	0x1d,	"2W1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqd",	 7,16,	0x1f,	"2D1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsb",	16,24,	0x040e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsw",	16,24,	0x050e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsd",	16,24,	0x070e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpst",	16,24,	0x840e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "comb",	14,24,	0x344e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "comw",	14,24,	0x354e,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "comd",	14,24,	0x374e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cvtp",	11,24,	0x036e,	"2A3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cxp",	 8,8,	0x22,	"1p",		0,	"",	21,21	},
+  { "cxpd",	11,16,	0x07f,	"1A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deib",	14,24,	0x2cce,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deiw",	14,24,	0x2dce,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deid",	14,24,	0x2fce,	"1D2Q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "dia",	 8,8,	0xc2,	"",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divf",	14,24,	0x21be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divl",	14,24,	0x20be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divb",	14,24,	0x3cce,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divw",	14,24,	0x3dce,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divd",	14,24,	0x3fce,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "enter",	 8,8,	0x82,	"1U2d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "exit",	 8,8,	0x92,	"1u",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extb",	11,24,	0x02e,	"2D3B1r4d",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extw",	11,24,	0x12e,	"2D3W1r4d",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extd",	11,24,	0x32e,	"2D3D1r4d",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsb",	14,24,	0x0cce,	"1D2B3g4G",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsw",	14,24,	0x0dce,	"1D2W3g4G",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsd",	14,24,	0x0fce,	"1D2D3g4G",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsb",	14,24,	0x046e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsw",	14,24,	0x056e,	"1W2B",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsd",	14,24,	0x076e,	"1D2B",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "flag",	 8,8,	0xd2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfb",	14,24,	0x3c3e,	"1F2B",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfw",	14,24,	0x3d3e,	"1F2W",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfd",	14,24,	0x3f3e,	"1F2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorlb",	14,24,	0x383e,	"1L2B",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorlw",	14,24,	0x393e,	"1L2W",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorld",	14,24,	0x3b3e,	"1L2D",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitb",	14,24,	0x384e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitw",	14,24,	0x394e,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitd",	14,24,	0x3b4e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexb",	11,24,	0x42e,	"2B3B1r",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexw",	11,24,	0x52e,	"2W3W1r",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexd",	11,24,	0x72e,	"2D3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insb",	11,24,	0x0ae,	"2B3B1r4d",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insw",	11,24,	0x1ae,	"2W3W1r4d",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insd",	11,24,	0x3ae,	"2D3D1r4d",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssb",	14,24,	0x08ce,	"1B2D3g4G",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssw",	14,24,	0x09ce,	"1W2D3g4G",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssd",	14,24,	0x0bce,	"1D2D3g4G",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "jsr",	11,16,	0x67f,	"1A",		4,	"",	21,21	},
+  { "jump",	11,16,	0x27f,	"1A",		4,	"",	21,21	},
+  { "lfsr",	19,24,	0x00f3e,"1D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lmr",	15,24,	0x0b1e,	"2D1M",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprb",	 7,16,	0x6c,	"2B1P",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprw",	 7,16,	0x6d,	"2W1P",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprd",	 7,16,	0x6f,	"2D1P",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshb",	14,24,	0x144e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshw",	14,24,	0x154e,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshd",	14,24,	0x174e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meib",	14,24,	0x24ce,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meiw",	14,24,	0x25ce,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meid",	14,24,	0x27ce,	"1D2Q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modb",	14,24,	0x38ce,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modw",	14,24,	0x39ce,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modd",	14,24,	0x3bce,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movf",	14,24,	0x05be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movl",	14,24,	0x04be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movb",	 6,16,	0x14,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movw",	 6,16,	0x15,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movd",	 6,16,	0x17,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movbf",	14,24,	0x043e,	"1B2F",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movwf",	14,24,	0x053e,	"1W2F",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movdf",	14,24,	0x073e,	"1D2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movbl",	14,24,	0x003e,	"1B2L",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movwl",	14,24,	0x013e,	"1W2L",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movdl",	14,24,	0x033e,	"1D2L",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movfl",	14,24,	0x1b3e,	"1F2L",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movlf",	14,24,	0x163e,	"1L2F",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmb",	14,24,	0x00ce,	"1A2A3b",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmw",	14,24,	0x01ce,	"1A2A3b",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmd",	14,24,	0x03ce,	"1A2A3b",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqb",	 7,16,	0x5c,	"2B1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqw",	 7,16,	0x5d,	"2B1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqd",	 7,16,	0x5f,	"2B1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsb",	16,24,	0x000e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsw",	16,24,	0x010e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsd",	16,24,	0x030e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movst",	16,24,	0x800e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsub",	14,24,	0x0cae,	"1A2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsuw",	14,24,	0x0dae,	"1A2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsud",	14,24,	0x0fae,	"1A2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusb",	14,24,	0x1cae,	"1A2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusw",	14,24,	0x1dae,	"1A2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusd",	14,24,	0x1fae,	"1A2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxbd",	14,24,	0x1cce,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxwd",	14,24,	0x1dce,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxbw",	14,24,	0x10ce,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzbd",	14,24,	0x18ce,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzwd",	14,24,	0x19ce,	"1W2D",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzbw",	14,24,	0x14ce,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulf",	14,24,	0x31be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mull",	14,24,	0x30be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulb",	14,24,	0x20ce, "1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulw",	14,24,	0x21ce, "1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "muld",	14,24,	0x23ce, "1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negf",	14,24,	0x15be, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negl",	14,24,	0x14be, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negb",	14,24,	0x204e, "1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negw",	14,24,	0x214e, "1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negd",	14,24,	0x234e, "1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "nop",	 8,8,	0xa2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notb",	14,24,	0x244e, "1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notw",	14,24,	0x254e, "1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notd",	14,24,	0x274e, "1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "orb",	 6,16,	0x18,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "orw",	 6,16,	0x19,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ord",	 6,16,	0x1b,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quob",	14,24,	0x30ce,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quow",	14,24,	0x31ce,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quod",	14,24,	0x33ce,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rdval",	19,24,	0x0031e,"1A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remb",	14,24,	0x34ce,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remw",	14,24,	0x35ce,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remd",	14,24,	0x37ce,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "restore",	 8,8,	0x72,	"1u",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ret",	 8,8,	0x12,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "reti",	 8,8,	0x52,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rett",	 8,8,	0x42,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotb",	14,24,	0x004e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotw",	14,24,	0x014e,	"1B2W",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotd",	14,24,	0x034e,	"1B2D",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfb",	14,24,	0x243e,	"1F2B",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfw",	14,24,	0x253e,	"1F2W",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfd",	14,24,	0x273e,	"1F2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundlb",	14,24,	0x203e,	"1L2B",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundlw",	14,24,	0x213e,	"1L2W",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundld",	14,24,	0x233e,	"1L2D",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rxp",	 8,8,	0x32,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqb",	11,16,	0x3c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqw",	11,16,	0x3d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqd",	11,16,	0x3f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sneb",	11,16,	0xbc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "snew",	11,16,	0xbd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sned",	11,16,	0xbf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsb",	11,16,	0x13c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsw",	11,16,	0x13d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsd",	11,16,	0x13f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccb",	11,16,	0x1bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccw",	11,16,	0x1bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccd",	11,16,	0x1bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shib",	11,16,	0x23c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shiw",	11,16,	0x23d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shid",	11,16,	0x23f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsb",	11,16,	0x2bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsw",	11,16,	0x2bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsd",	11,16,	0x2bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtb",	11,16,	0x33c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtw",	11,16,	0x33d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtd",	11,16,	0x33f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sleb",	11,16,	0x3bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slew",	11,16,	0x3bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sled",	11,16,	0x3bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsb",	11,16,	0x43c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsw",	11,16,	0x43d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsd",	11,16,	0x43f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcb",	11,16,	0x4bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcw",	11,16,	0x4bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcd",	11,16,	0x4bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slob",	11,16,	0x53c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slow",	11,16,	0x53d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slod",	11,16,	0x53f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsb",	11,16,	0x5bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsw",	11,16,	0x5bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsd",	11,16,	0x5bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltb",	11,16,	0x63c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltw",	11,16,	0x63d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltd",	11,16,	0x63f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgeb",	11,16,	0x6bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgew",	11,16,	0x6bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sged",	11,16,	0x6bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutb",	11,16,	0x73c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutw",	11,16,	0x73d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutd",	11,16,	0x73f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufb",	11,16,	0x7bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufw",	11,16,	0x7bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufd",	11,16,	0x7bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "save",	 8,8,	0x62,	"1U",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitb",    14,24,	0x184e,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitw",	14,24,	0x194e,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitd",	14,24,	0x1b4e,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitib",	14,24,	0x1c4e,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitiw",	14,24,	0x1d4e,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitid",	14,24,	0x1f4e,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "setcfg",	15,24,	0x0b0e,	"1O",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsr",	14,24,	0x373e,	"1f",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "skpsb",	16,24,	0x0c0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpsw",	16,24,	0x0d0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpsd",	16,24,	0x0f0e, "1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpst",	16,24,	0x8c0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "smr",	15,24,	0x0f1e,	"2D1M",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprb",	 7,16,	0x2c,	"2B1P",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprw",	 7,16,	0x2d,	"2W1P",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprd",	 7,16,	0x2f,	"2D1P",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subf",	14,24,	0x11be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subl",	14,24,	0x10be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subb",	 6,16,	0x20,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subw",	 6,16,	0x21,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subd",	 6,16,	0x23,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcb",	 6,16,	0x30,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcw",	 6,16,	0x31,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcd",	 6,16,	0x33,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpb",	14,24,	0x2c4e,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpw",	14,24,	0x2d4e,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpd",	14,24,	0x2f4e,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+#ifdef NS32K_SVC_IMMED_OPERANDS
+  { "svc",	 8,8,	0xe2,	"2i1i",		1,	"",	DEF_MODEC,DEF_MODEL	}, /* not really, but unix uses it */
+#else
+  { "svc",	 8,8,	0xe2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+#endif
+  { "tbitb",	 6,16,	0x34,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "tbitw",	 6,16,	0x35,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "tbitd",	 6,16,	0x37,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfb",	14,24,	0x2c3e,	"1F2B",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfw",	14,24,	0x2d3e,	"1F2W",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfd",	14,24,	0x2f3e,	"1F2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "trunclb",	14,24,	0x283e,	"1L2B",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "trunclw",	14,24,	0x293e,	"1L2W",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncld",	14,24,	0x2b3e,	"1L2D",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "wait",	 8,8,	0xb2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "wrval",	19,24,	0x0071e,"1A",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xorb",	 6,16,	0x38,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xorw",	 6,16,	0x39,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xord",	 6,16,	0x3b,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+#if defined(NS32381)	/* I'm not too sure of these */
+  { "dotf",	14,24,  0x0dfe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "dotl",	14,24,  0x0cfe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "logbf",	14,24,  0x15fe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "logbl",	14,24,  0x14fe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "polyf",	14,24,  0x09fe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "polyl",	14,24,  0x08fe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scalbf",	14,24,  0x11fe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scalbl",	14,24,  0x10fe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+#endif
+};
+
+static const int numopcodes=sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
+
+static const struct ns32k_opcode *endop = ns32k_opcodes+sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
+
+#define MAX_ARGS 4
+#define ARG_LEN 50
+
diff --git a/gnu/usr.bin/gas/opcode/pn.h b/gnu/usr.bin/gas/opcode/pn.h
new file mode 100644
index 00000000000..fde4764c02c
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/pn.h
@@ -0,0 +1,282 @@
+/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
+   Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction. */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...
+*/
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+struct gld_opcode gld_opcodes[] =
+{
+{ "abm",	0xa0080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "abr",	0x18080000,	0xfc0c0000,	"r,f",		2 },
+{ "aci",	0xfc770000,	0xfc7f8000,	"r,I",		4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adi",	0xc8010000,	0xfc7f0000,	"r,I",		4 },
+{ "admb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "admh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrm",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+{ "ai", 	0xfc030000,	0xfc07ffff,	"I",		4 },
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bcf",	0xf0000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bct",	0xec000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bei",	0x00060000,	0xffff0000,	"",		2 },
+{ "bft",	0xf0000000,	0xff880000,	"xOA,X",	4 },
+{ "bib",	0xf4000000,	0xfc780000,	"r,xOA",	4 },
+{ "bid",	0xf4600000,	0xfc780000,	"r,xOA",	4 },
+{ "bih",	0xf4200000,	0xfc780000,	"r,xOA",	4 },
+{ "biw",	0xf4400000,	0xfc780000,	"r,xOA",	4 },
+{ "bl", 	0xf8800000,	0xff880000,	"xOA,X",	4 },
+{ "bsub",	0x5c080000,	0xff8f0000,	"",		2 },
+{ "bsubm",	0x28080000,	0xfc080000,	"",		4 },
+{ "bu", 	0xec000000,	0xff880000,	"xOA,X",	4 },
+{ "call",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "callm",	0x5c080000,	0xff880000,	"",		4 },
+{ "camb",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "camh",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x90000000,	0xfc080000,	"r.xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "cd", 	0xfc060000,	0xfc070000,	"r,f",		4 },
+{ "cea",	0x000f0000,	0xffff0000,	"",		2 },
+{ "ci", 	0xc8050000,	0xfc7f0000,	"r,I",		4 },
+{ "cmc",	0x040a0000,	0xfc7f0000,	"r",		2 },
+{ "cmmb",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmmd",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "cmmh",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "cmmw",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmr",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "daci",	0xfc7f0000,	0xfc7f8000,	"r,I",		4 },
+{ "dae",	0x000e0000,	0xffff0000,	"",		2 },
+{ "dai",	0xfc040000,	0xfc07ffff,	"I",		4 },
+{ "dci",	0xfc6f0000,	0xfc7f8000,	"r,I",		4 },
+{ "di", 	0xfc010000,	0xfc07ffff,	"I",		4 },
+{ "dvfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "dvfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvi",	0xc8040000,	0xfc7f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvrfd",	0x380c0000,	0xfc0f0000,	"r,R",		4 },
+{ "dvrfw",	0x38040000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "eae",	0x00080000,	0xffff0000,	"",		2 },
+{ "eci",	0xfc670000,	0xfc7f8080,	"r,I",		4 },
+{ "ecwcs",	0xfc4f0000,	0xfc7f8000,	"",		4 },
+{ "ei", 	0xfc000000,	0xfc07ffff,	"I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eorm",	0x0c080000,	0xfc0f0000,	"r,R",		2 },
+{ "es", 	0x00040000,	0xfc7f0000,	"r",		2 },
+{ "exm",	0xa8000000,	0xff880000,	"xOA,X",	4 },
+{ "exr",	0xc8070000,	0xfc7f0000,	"r",		2 },
+{ "exrr",	0xc8070002,	0xfc7f0002,	"r",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "grio",	0xfc3f0000,	0xfc7f8000,	"r,I",		4 },
+{ "halt",	0x00000000,	0xffff0000,	"",		2 },
+{ "hio",	0xfc370000,	0xfc7f8000,	"r,I",		4 },
+{ "jwcs",	0xfa080000,	0xff880000,	"xOA,X",	4 },
+{ "la", 	0x50000000,	0xfc000000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lb", 	0xac080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lcs", 	0x00030000,	0xfc7f0000,	"r",		2 },
+{ "ld", 	0xac000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lear", 	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lf", 	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr", 	0xcc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lh", 	0xac000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "li", 	0xc8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lmap",	0x2c070000,	0xfc7f0000,	"r",		2 },
+{ "lmb",	0xb0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lmd",	0xb0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lmh",	0xb0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lmw",	0xb0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnd",	0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnh",	0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnw",	0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lpsd",	0xf9800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lpsdcm",	0xfa800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lw", 	0xac000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwbr", 	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpi",	0xc8030000,	0xfc7f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "nop",	0x00020000,	0xffff0000,	"",		2 },
+{ "ormb",	0x88080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0x88000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "ormh",	0x88000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0x88000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "orrm",	0x08080000,	0xfc0f0000,	"r,R",		2 },
+{ "rdsts",	0x00090000,	0xfc7f0000,	"r",		2 },
+{ "return",	0x280e0000,	0xfc7f0000,	"",		2 },
+{ "ri", 	0xfc020000,	0xfc07ffff,	"I",		4 },
+{ "rnd",	0x00050000,	0xfc7f0000,	"r",		2 },
+{ "rpswt",	0x040b0000,	0xfc7f0000,	"r",		2 },
+{ "rschnl",	0xfc2f0000,	0xfc7f8000,	"r,I",		4 },
+{ "rsctl",	0xfc470000,	0xfc7f8000,	"r,I",		4 },
+{ "rwcs",	0x000b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sacz",	0x10080000,	0xfc0f0000,	"r,R",		2 },
+{ "sbm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "sbr",	0x18000000,	0xfc0c0000,	"r,f",		4 },
+{ "sea",	0x000d0000,	0xffff0000,	"",		2 },
+{ "setcpu",	0x2c090000,	0xfc7f0000,	"r",		2 },
+{ "sio",	0xfc170000,	0xfc7f8000,	"r,I",		4 },
+{ "sipu",	0x000a0000,	0xffff0000,	"",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "smc",	0x04070000,	0xfc070000,	"",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stpio",	0xfc270000,	0xfc7f8000,	"r,I",		4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sufd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sufw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sui",	0xc8020000,	0xfc7f0000,	"r,I",		4 },
+{ "sumb",	0xbc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xbc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sumh",	0xbc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surm",	0x3c080000,	0xfc0f0000,	"r,R",		2 },
+{ "svc",	0xc8060000,	0xffff0000,	"",		4 },
+{ "tbm",	0xa4080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbr",	0x180c0000,	0xfc0c0000,	"r,f",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "tccr",	0x28040000,	0xfc7f0000,	"",		2 },
+{ "td", 	0xfc050000,	0xfc070000,	"r,f",		4 },
+{ "tio",	0xfc1f0000,	0xfc7f8000,	"r,I",		4 },
+{ "tmapr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "tpcbr",	0x280c0000,	0xfc7f0000,	"r",		2 },
+{ "trbr",	0x2c010000,	0xfc0f0000,	"b,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "trcc",	0x28050000,	0xfc7f0000,	"",		2 },
+{ "trcm",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnm",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trrm",	0x2c080000,	0xfc0f0000,	"r,R",		2 },
+{ "trsc",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "trsw",	0x28000000,	0xfc7f0000,	"r",		2 },
+{ "tscr",	0x2c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "uei",	0x00070000,	0xffff0000,	"",		2 },
+{ "wait",	0x00010000,	0xffff0000,	"",		2 },
+{ "wcwcs",	0xfc5f0000,	0xfc7f8000,	"",		4 },
+{ "wwcs",	0x000c0000,	0xfc0f0000,	"r,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "xcr",	0x2c050000,	0xfc0f0000,	"r,R",		2 },
+{ "xcrm",	0x2c0d0000,	0xfc0f0000,	"r,R",		2 },
+{ "zbm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbr",	0x18040000,	0xfc0c0000,	"r,f",		2 },
+{ "zmb",	0xf8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xf8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "zmh",	0xf8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xf8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zr", 	0x0c000000,	0xfc0f0000,	"r",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		sizeof(gld_opcodes[0]);
diff --git a/gnu/usr.bin/gas/opcode/pyr.h b/gnu/usr.bin/gas/opcode/pyr.h
new file mode 100644
index 00000000000..06632b8d919
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/pyr.h
@@ -0,0 +1,287 @@
+/* pyramid.opcode.h -- gdb initial attempt. */
+
+/* pyramid opcode table: wot to do with this
+   particular opcode */
+
+struct pyr_datum
+{
+  char              nargs;
+  char *            args;	/* how to compile said opcode */
+  unsigned long     mask;	/* Bit vector: which operand modes are valid
+				   for this opcode */
+  unsigned char     code;	/* op-code (always 6(?) bits */
+};
+
+typedef struct pyr_insn_format {
+    unsigned int mode :4;
+    unsigned int operator :8;
+    unsigned int index_scale :2;
+    unsigned int index_reg :6;
+    unsigned int operand_1 :6;
+    unsigned int operand_2:6;
+} pyr_insn_format;
+	
+
+/* We store four bytes of opcode for all opcodes.
+   Pyramid is sufficiently RISCy that:
+      - insns are always an integral number of words;
+      - the length of any insn can be told from the first word of
+        the insn. (ie, if there are zero, one, or two words of
+	immediate operand/offset).
+
+   
+   The args component is a string containing two characters for each
+   operand of the instruction.  The first specifies the kind of operand;
+   the second, the place it is stored. */
+
+/* Kinds of operands:
+   mask	 assembler syntax	description
+   0x0001:  movw Rn,Rn		register to register
+   0x0002:  movw K,Rn		quick immediate to register
+   0x0004:  movw I,Rn		long immediate to register
+   0x0008:  movw (Rn),Rn	register indirect to register
+   	    movw (Rn)[x],Rn	register indirect to register
+   0x0010:  movw I(Rn),Rn	offset register indirect to register
+   	    movw I(Rn)[x],Rn	offset register indirect, indexed, to register
+
+   0x0020:  movw Rn,(Rn)	register to register indirect                
+   0x0040:  movw K,(Rn)		quick immediate to register indirect         
+   0x0080:  movw I,(Rn)		long immediate to register indirect          
+   0x0100:  movw (Rn),(Rn)	register indirect to-register indirect       
+   0x0100:  movw (Rn),(Rn)	register indirect to-register indirect       
+   0x0200:  movw I(Rn),(Rn)	register indirect+offset to register indirect
+   0x0200:  movw I(Rn),(Rn)	register indirect+offset to register indirect
+
+   0x0400:  movw Rn,I(Rn)	register to register indirect+offset
+   0x0800:  movw K,I(Rn)	quick immediate to register indirect+offset
+   0x1000:  movw I,I(Rn)	long immediate to register indirect+offset
+   0x1000:  movw (Rn),I(Rn)	register indirect to-register indirect+offset
+   0x1000:  movw I(Rn),I(Rn)	register indirect+offset to register indirect
+   					+offset
+   0x0000:  (irregular)		???
+   
+
+   Each insn has a four-bit field encoding the type(s) of its operands.
+*/
+
+/* Some common combinations
+   */
+
+/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
+#define GEN_TO_REG (31)
+
+#define	UNKNOWN ((unsigned long)-1)
+#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
+
+#define CONVERT (1|8|0x10|0x20|0x200)
+
+#define K_TO_REG (2)
+#define I_TO_REG (4)
+#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
+#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+
+struct pyr_opcode		/* pyr opcode text */
+{
+  char *            name;	/* opcode name: lowercase string  [key]  */
+  struct pyr_datum  datum;	/* rest of opcode table          [datum] */
+};
+
+#define pyr_how args
+#define pyr_nargs nargs
+#define pyr_mask mask
+#define pyr_name name
+
+struct pyr_opcode pyr_opcodes[] =
+{
+  {"movb",	{ 2, "", UNKNOWN,		0x11}, },
+  {"movh",	{ 2, "", UNKNOWN,		0x12} },
+  {"movw",	{ 2, "", ANY,			0x10} },
+  {"movl",	{ 2, "", ANY,			0x13} },
+  {"mnegw",	{ 2, "", (0x1|0x8|0x10),	0x14} },
+  {"mnegf",	{ 2, "", 0x1,			0x15} },
+  {"mnegd",	{ 2, "", 0x1,			0x16} },
+  {"mcomw",	{ 2, "", (0x1|0x8|0x10),	0x17} },
+  {"mabsw",	{ 2, "", (0x1|0x8|0x10),	0x18} },
+  {"mabsf",	{ 2, "", 0x1,			0x19} },
+  {"mabsd",	{ 2, "", 0x1,			0x1a} },
+  {"mtstw",	{ 2, "", (0x1|0x8|0x10),	0x1c} },
+  {"mtstf",	{ 2, "", 0x1,			0x1d} },
+  {"mtstd",	{ 2, "", 0x1,			0x1e} },
+  {"mova",	{ 2, "", 0x8|0x10,		0x1f} },
+  {"movzbw",	{ 2, "", (0x1|0x8|0x10),	0x20} },
+  {"movzhw",	{ 2, "", (0x1|0x8|0x10),	0x21} },
+				/* 2 insns out of order here */
+  {"movbl",	{ 2, "", 1,			0x4f} },
+  {"filbl",	{ 2, "", 1,			0x4e} },
+
+  {"cvtbw",	{ 2, "", CONVERT,		0x22} },
+  {"cvthw",	{ 2, "", CONVERT,		0x23} },
+  {"cvtwb",	{ 2, "", CONVERT,		0x24} },
+  {"cvtwh",	{ 2, "", CONVERT,		0x25} },
+  {"cvtwf",	{ 2, "", CONVERT,		0x26} },
+  {"cvtwd",	{ 2, "", CONVERT,		0x27} },
+  {"cvtfw",	{ 2, "", CONVERT,		0x28} },
+  {"cvtfd",	{ 2, "", CONVERT,		0x29} },
+  {"cvtdw",	{ 2, "", CONVERT,		0x2a} },
+  {"cvtdf",	{ 2, "", CONVERT,		0x2b} },
+
+  {"addw",	{ 2, "", GEN_TO_REG,		0x40} },
+  {"addwc",	{ 2, "", GEN_TO_REG,		0x41} },
+  {"subw",	{ 2, "", GEN_TO_REG,		0x42} },
+  {"subwb",	{ 2, "", GEN_TO_REG,		0x43} },
+  {"rsubw",	{ 2, "", GEN_TO_REG,		0x44} },
+  {"mulw",	{ 2, "", GEN_TO_REG,		0x45} },
+  {"emul",	{ 2, "", GEN_TO_REG,		0x47} },
+  {"umulw",	{ 2, "", GEN_TO_REG,		0x46} },
+  {"divw",	{ 2, "", GEN_TO_REG,		0x48} },
+  {"ediv",	{ 2, "", GEN_TO_REG,		0x4a} },
+  {"rdivw",	{ 2, "", GEN_TO_REG,		0x4b} },
+  {"udivw",	{ 2, "", GEN_TO_REG,		0x49} },
+  {"modw",	{ 2, "", GEN_TO_REG,		0x4c} },
+  {"umodw",	{ 2, "", GEN_TO_REG,		0x4d} },
+
+
+  {"addf",	{ 2, "", 1,			0x50} },
+  {"addd",	{ 2, "", 1,			0x51} },
+  {"subf",	{ 2, "", 1,			0x52} },
+  {"subd",	{ 2, "", 1,			0x53} },
+  {"mulf",	{ 2, "", 1,			0x56} },
+  {"muld",	{ 2, "", 1,			0x57} },
+  {"divf",	{ 2, "", 1,			0x58} },
+  {"divd",	{ 2, "", 1,			0x59} },
+
+
+  {"cmpb",	{ 2, "", UNKNOWN,		0x61} },
+  {"cmph",	{ 2, "", UNKNOWN,		0x62} },
+  {"cmpw",	{ 2, "", UNKNOWN,		0x60} },
+  {"ucmpb",	{ 2, "", UNKNOWN,		0x66} },
+  /* WHY no "ucmph"??? */
+  {"ucmpw",	{ 2, "", UNKNOWN,		0x65} },
+  {"xchw",	{ 2, "", UNKNOWN,		0x0f} },
+
+
+  {"andw",	{ 2, "", GEN_TO_REG,		0x30} },
+  {"orw",	{ 2, "", GEN_TO_REG,		0x31} },
+  {"xorw",	{ 2, "", GEN_TO_REG,		0x32} },
+  {"bicw",	{ 2, "", GEN_TO_REG,		0x33} },
+  {"lshlw",	{ 2, "", GEN_TO_REG,		0x38} },
+  {"ashlw",	{ 2, "", GEN_TO_REG,		0x3a} },
+  {"ashll",	{ 2, "", GEN_TO_REG,		0x3c} },
+  {"ashrw",	{ 2, "", GEN_TO_REG,		0x3b} },
+  {"ashrl",	{ 2, "", GEN_TO_REG,		0x3d} },
+  {"rotlw",	{ 2, "", GEN_TO_REG,		0x3e} },
+  {"rotrw",	{ 2, "", GEN_TO_REG,		0x3f} },
+
+  /* push and pop insns are "going away next release". */
+  {"pushw",	{ 2, "", GEN_TO_REG,		0x0c} },
+  {"popw",	{ 2, "", (0x1|0x8|0x10),	0x0d} },
+  {"pusha",	{ 2, "", (0x8|0x10),		0x0e} },
+
+  {"bitsw",	{ 2, "", UNKNOWN,		0x35} },
+  {"bitcw",	{ 2, "", UNKNOWN,		0x36} },
+  /* some kind of ibra/dbra insns??*/
+  {"icmpw",	{ 2, "", UNKNOWN,		0x67} },
+  {"dcmpw",	{ 2, "", (1|4|0x20|0x80|0x400|0x1000),	0x69} },/*FIXME*/
+  {"acmpw",	{ 2, "", 1,			0x6b} },
+
+  /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
+     insn with a 2nd op of tr14.   The assembler will have to grok this.  */
+  {"call",	{ 2, "", GEN_TO_REG,		0x04} },
+  {"call",	{ 1, "", GEN_TO_REG,		0x04} },
+
+  {"callk",	{ 1, "", UNKNOWN,		0x06} },/* system call?*/
+  /* Ret is usually written as a 0-op insn, but gets disassembled as a
+     1-op insn. The operand is always tr15. */
+  {"ret",	{ 0, "", UNKNOWN,		0x09} },
+  {"ret",	{ 1, "", UNKNOWN,		0x09} },
+  {"adsf",	{ 2, "", (1|2|4),		0x08} },
+  {"retd",	{ 2, "", UNKNOWN,		0x0a} },
+  {"btc",	{ 2, "", UNKNOWN,		0x01} },
+  {"bfc",	{ 2, "", UNKNOWN,		0x02} },
+  /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
+  {"jump",	{ 1, "", UNKNOWN,		0x00} },
+  {"btp",	{ 2, "", UNKNOWN,		0xf00} },
+  /* read control-stack pointer is another 1-or-2 operand insn. */
+  {"rcsp",	{ 2, "", UNKNOWN,		0x01f} },
+  {"rcsp",	{ 1, "", UNKNOWN,		0x01f} }
+};
+
+/* end: pyramid.opcode.h */
+/* One day I will have to take the time to find out what operands
+   are valid for these insns, and guess at what they mean.
+
+   I can't imagine what the "I???" insns (iglob, etc) do.
+
+   the arithmetic-sounding insns ending in "p" sound awfully like BCD
+   arithmetic insns:
+   	dshlp -> Decimal SHift Left Packed
+	dshrp -> Decimal SHift Right Packed
+   and cvtlp would be convert long to packed.
+   I have no idea how the operands are interpreted; but having them be
+   a long register with (address, length) of an in-memory packed BCD operand
+   would not be surprising.
+   They are unlikely to be a packed bcd string: 64 bits of long give
+   is only 15 digits+sign, which isn't enough for COBOL.
+ */ 
+#if 0
+  {"wcsp",	{ 2, "", UNKNOWN,		0x00} }, /*write csp?*/
+  /* The OSx Operating System Porting Guide claims SSL does things
+     with tr12 (a register reserved to it) to do with static block-structure
+     references.  SSL=Set Static Link?  It's "Going away next release". */
+  {"ssl",	{ 2, "", UNKNOWN,		0x00} },
+  {"ccmps",	{ 2, "", UNKNOWN,		0x00} },
+  {"lcd",	{ 2, "", UNKNOWN,		0x00} },
+  {"uemul",	{ 2, "", UNKNOWN,		0x00} }, /*unsigned emul*/
+  {"srf",	{ 2, "", UNKNOWN,		0x00} }, /*Gidget time???*/
+  {"mnegp",	{ 2, "", UNKNOWN,		0x00} }, /move-neg phys?*/
+  {"ldp",	{ 2, "", UNKNOWN,		0x00} }, /*load phys?*/
+  {"ldti",	{ 2, "", UNKNOWN,		0x00} },
+  {"ldb",	{ 2, "", UNKNOWN,		0x00} },
+  {"stp",	{ 2, "", UNKNOWN,		0x00} },
+  {"stti",	{ 2, "", UNKNOWN,		0x00} },
+  {"stb",	{ 2, "", UNKNOWN,		0x00} },
+  {"stu",	{ 2, "", UNKNOWN,		0x00} },
+  {"addp",	{ 2, "", UNKNOWN,		0x00} },
+  {"subp",	{ 2, "", UNKNOWN,		0x00} },
+  {"mulp",	{ 2, "", UNKNOWN,		0x00} },
+  {"divp",	{ 2, "", UNKNOWN,		0x00} },
+  {"dshlp",	{ 2, "", UNKNOWN,		0x00} },  /* dec shl packed? */
+  {"dshrp",	{ 2, "", UNKNOWN,		0x00} }, /* dec shr packed? */
+  {"movs",	{ 2, "", UNKNOWN,		0x00} }, /*move (string?)?*/
+  {"cmpp",	{ 2, "", UNKNOWN,		0x00} }, /* cmp phys?*/
+  {"cmps",	{ 2, "", UNKNOWN,		0x00} }, /* cmp (string?)?*/
+  {"cvtlp",	{ 2, "", UNKNOWN,		0x00} }, /* cvt long to p??*/
+  {"cvtpl",	{ 2, "", UNKNOWN,		0x00} }, /* cvt p to l??*/
+  {"dintr",	{ 2, "", UNKNOWN,		0x00} }, /* ?? intr ?*/
+  {"rphysw",	{ 2, "", UNKNOWN,		0x00} }, /* read phys word?*/
+  {"wphysw",	{ 2, "", UNKNOWN,		0x00} }, /* write phys word?*/
+  {"cmovs",	{ 2, "", UNKNOWN,		0x00} },
+  {"rsubw",	{ 2, "", UNKNOWN,		0x00} },
+  {"bicpsw",	{ 2, "", UNKNOWN,		0x00} }, /* clr bit in psw? */
+  {"bispsw",	{ 2, "", UNKNOWN,		0x00} }, /* set bit in psw? */
+  {"eio",	{ 2, "", UNKNOWN,		0x00} }, /* ?? ?io ? */
+  {"callp",	{ 2, "", UNKNOWN,		0x00} }, /* call phys?*/
+  {"callr",	{ 2, "", UNKNOWN,		0x00} },
+  {"lpcxt",	{ 2, "", UNKNOWN,		0x00} }, /*load proc context*/
+  {"rei",	{ 2, "", UNKNOWN,		0x00} }, /*ret from intrpt*/
+  {"rport",	{ 2, "", UNKNOWN,		0x00} }, /*read-port?*/
+  {"rtod",	{ 2, "", UNKNOWN,		0x00} }, /*read-time-of-day?*/
+  {"ssi",	{ 2, "", UNKNOWN,		0x00} },
+  {"vtpa",	{ 2, "", UNKNOWN,		0x00} }, /*virt-to-phys-addr?*/
+  {"wicl",	{ 2, "", UNKNOWN,		0x00} }, /* write icl ? */
+  {"wport",	{ 2, "", UNKNOWN,		0x00} }, /*write-port?*/
+  {"wtod",	{ 2, "", UNKNOWN,		0x00} }, /*write-time-of-day?*/
+  {"flic",	{ 2, "", UNKNOWN,		0x00} },
+  {"iglob",	{ 2, "", UNKNOWN,		0x00} }, /* I global? */
+  {"iphys",	{ 2, "", UNKNOWN,		0x00} }, /* I physical? */
+  {"ipid",	{ 2, "", UNKNOWN,		0x00} }, /* I pid? */
+  {"ivect",	{ 2, "", UNKNOWN,		0x00} }, /* I vector? */
+  {"lamst",	{ 2, "", UNKNOWN,		0x00} },
+  {"tio",	{ 2, "", UNKNOWN,		0x00} },
+#endif
diff --git a/gnu/usr.bin/gas/opcode/sparc.h b/gnu/usr.bin/gas/opcode/sparc.h
new file mode 100644
index 00000000000..38ae9a4f7ae
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/sparc.h
@@ -0,0 +1,885 @@
+
+/* Table of opcodes for the sparc.
+	Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
+
+This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+the GNU Binutils.
+
+GAS/GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GAS/GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS or GDB; see the file COPYING.	If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.	*/
+
+/*
+ * $Id: sparc.h,v 1.1 1995/10/18 08:39:10 deraadt Exp $
+ */
+
+ /* FIXME-someday: perhaps the ,a's and such should be embedded in the
+    instruction's name rather than the args.  This would make gas faster, pinsn
+    slower, but would mess up some macros a bit.  xoxorich. */
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+/*
+ * Structure of an opcode table entry.
+ */
+enum sparc_architecture {
+	v6 = 0,
+	v7,
+	v8,
+};
+
+static const char *architecture_pname[] = {
+	"v6",
+	"v7",
+	"v8",
+	NULL,
+};
+
+struct sparc_opcode {
+	const char *name;
+	unsigned long match;	/* Bits that must be set. */
+	unsigned long lose;	/* Bits that must not be set. */
+	const char *args;
+ /* This was called "delayed" in versions before the flags. */
+	char flags;
+	enum sparc_architecture architecture;
+};
+
+#define	F_DELAYED	1	/* Delayed branch */
+#define	F_ALIAS		2	/* Alias for a "real" instruction */
+
+/*
+
+All sparc opcodes are 32 bits, except for the `set' instruction (really a
+macro), which is 64 bits. It is handled as a special case.
+
+The match component is a mask saying which bits must match a particular
+opcode in order for an instruction to be an instance of that opcode.
+
+The args component is a string containing one character for each operand of the
+instruction.
+
+Kinds of operands:
+	#	Number used by optimizer.	It is ignored.
+	1	rs1 register.
+	2	rs2 register.
+	d	rd register.
+	e	frs1 floating point register.
+	v	frs1 floating point register (double/even).
+	V	frs1 floating point register (quad/multiple of 4).
+	f	frs2 floating point register.
+	B	frs2 floating point register (double/even).
+	R	frs2 floating point register (quad/multiple of 4).
+	g	frsd floating point register.
+	H	frsd floating point register (double/even).
+	J	frsd floating point register (quad/multiple of 4).
+	b	crs1 coprocessor register
+	c	crs2 coprocessor register
+	D	crsd coprocessor register
+	m	alternate space register (asr) in rd
+	M	alternate space register (asr) in rs1
+	h	22 high bits.
+	i	13 bit Immediate.
+	n	22 bit immediate.
+	l	22 bit PC relative immediate.
+	L	30 bit PC relative immediate.
+	a	Annul.	The annul bit is set.
+	A	Alternate address space. Stored as 8 bits.
+	C	Coprocessor state register.
+	F	floating point state register.
+	p	Processor state register.
+	q	Floating point queue.
+	r	Single register that is both rs1 and rsd.
+	Q	Coprocessor queue.
+	S	Special case.
+	x	Single register that is both rs2 and rsd.
+	t	Trap base register.
+	w	Window invalid mask register.
+	y	Y register.
+
+The following chars are unused: (note: ,[] are used as punctuation)
+[oOX3450]
+
+*/
+
+/* The order of the opcodes in this table is significant:
+	
+	* The assembler requires that all instances of the same mnemonic must
+	be consecutive.	If they aren't, the assembler will bomb at runtime.
+
+	* The disassembler should not care about the order of the opcodes.
+
+*/
+
+#define OP2(x)		(((x)&0x7) << 22) /* op2 field of format2 insns */
+#define OP3(x)		(((x)&0x3f) << 19) /* op3 field of format3 insns */
+#define OP(x)		(((x)&0x3) << 30) /* op field of all insns */
+#define OPF(x)		(((x)&0x1ff) << 5) /* opf field of float insns */
+#define F3F(x, y, z)	(OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
+#define F3I(x)		(((x)&0x1) << 13) /* immediate field of format 3 insns */
+#define F2(x, y)	(OP(x) | OP2(y)) /* format 2 insns */
+#define F3(x, y, z)	(OP(x) | OP3(y) | F3I(z)) /* format3 insns */
+#define F1(x)		(OP(x))
+#define DISP30(x)	((x)&0x3fffffff)
+#define ASI(x)		(((x)&0xff) << 5) /* asi field of format3 insns */
+#define RS2(x)		((x)&0x1f) /* rs2 field */
+#define SIMM13(x)	((x)&0x1fff) /* simm13 field */
+#define RD(x)		(((x)&0x1f) << 25) /* destination register field */
+#define RS1(x)		(((x)&0x1f) << 14) /* rs1 field */
+#define ASI_RS2(x)	(SIMM13(x))
+
+#define ANNUL	(1<<29)
+#define	IMMED	F3I(1)
+#define RD_G0	RD(~0)
+#define	RS1_G0	RS1(~0)
+#define	RS2_G0	RS2(~0)
+
+#define COND(x)		(((x)&0xf)<<25)
+
+#define CONDA	(COND(0x8))
+#define CONDCC	(COND(0xd))
+#define CONDCS	(COND(0x5))
+#define CONDE	(COND(0x1))
+#define CONDG	(COND(0xa))
+#define CONDGE	(COND(0xb))
+#define CONDGU	(COND(0xc))
+#define CONDL	(COND(0x3))
+#define CONDLE	(COND(0x2))
+#define CONDLEU	(COND(0x4))
+#define CONDN	(COND(0x0))
+#define CONDNE	(COND(0x9))
+#define CONDNEG	(COND(0x6))
+#define CONDPOS	(COND(0xe))
+#define CONDVC	(COND(0xf))
+#define CONDVS	(COND(0x7))
+
+#define CONDNZ	CONDNE
+#define CONDZ	CONDE
+#define CONDGEU	CONDCC
+#define CONDLU	CONDCS
+
+#define FCONDA		(COND(0x8))
+#define FCONDE		(COND(0x9))
+#define FCONDG		(COND(0x6))
+#define FCONDGE		(COND(0xb))
+#define FCONDL		(COND(0x4))
+#define FCONDLE		(COND(0xd))
+#define FCONDLG		(COND(0x2))
+#define FCONDN		(COND(0x0))
+#define FCONDNE		(COND(0x1))
+#define FCONDO		(COND(0xf))
+#define FCONDU		(COND(0x7))
+#define FCONDUE		(COND(0xa))
+#define FCONDUG		(COND(0x5))
+#define FCONDUGE	(COND(0xc))
+#define FCONDUL		(COND(0x3))
+#define FCONDULE	(COND(0xe))
+
+#define FCONDNZ	FCONDNE
+#define FCONDZ	FCONDE
+
+
+static const struct sparc_opcode sparc_opcodes[] = {
+
+{ "ld",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0),		"[1+2],d", 0, v6 },
+{ "ld",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,	"[1],d", 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[1+i],d", 0, v6 },
+{ "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[i+1],d", 0, v6 },
+{ "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* ld [rs1+0],d */
+{ "ld",	F3(3, 0x20, 0), F3(~3, ~0x20, ~0),		"[1+2],g", 0, v6 },
+{ "ld",	F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,	"[1],g", 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1),		"[1+i],g", 0, v6 },
+{ "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1),		"[i+1],g", 0, v6 },
+{ "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,	"[i],g", 0, v6 },
+{ "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),	"[1],g", 0, v6 }, /* ld [rs1+0],d */
+{ "ld",	F3(3, 0x21, 0), F3(~3, ~0x21, ~0),		"[1+2],F", 0, v6 },
+{ "ld",	F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0,	"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1),		"[1+i],F", 0, v6 },
+{ "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1),		"[i+1],F", 0, v6 },
+{ "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0,	"[i],F", 0, v6 },
+{ "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0),	"[1],F", 0, v6 }, /* ld [rs1+0],d */
+{ "ld",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0),		"[1+2],D", 0, v6 },
+{ "ld",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,	"[1],D", 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[1+i],D", 0, v6 },
+{ "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[i+1],D", 0, v6 },
+{ "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,	"[i],D", 0, v6 },
+{ "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),	"[1],D", 0, v6 }, /* ld [rs1+0],d */
+{ "ld",	F3(3, 0x31, 0), F3(~3, ~0x31, ~0),		"[1+2],C", 0, v6 },
+{ "ld",	F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,	"[1],C", 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1),		"[1+i],C", 0, v6 },
+{ "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1),		"[i+1],C", 0, v6 },
+{ "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,	"[i],C", 0, v6 },
+{ "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),	"[1],C", 0, v6 }, /* ld [rs1+0],d */
+
+
+
+{ "lda",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0),		"[1+2]A,d", 0, v6 },
+{ "lda",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
+
+{ "ldd",	F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "ldd",	F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1),		"[1+i],d", 0, v6 },
+{ "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1),		"[i+1],d", 0, v6 },
+{ "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* ldd [rs1+0],d */
+{ "ldd",	F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),	"[1+2],g", 0, v6 },
+{ "ldd",	F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),	"[1],g", 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1),		"[1+i],g", 0, v6 },
+{ "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1),		"[i+1],g", 0, v6 },
+{ "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,	"[i],g", 0, v6 },
+{ "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),	"[1],g", 0, v6 }, /* ldd [rs1+0],d */
+{ "ldd",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),	"[1+2],D", 0, v6 },
+{ "ldd",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),	"[1],D", 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[1+i],D", 0, v6 },
+{ "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[i+1],D", 0, v6 },
+{ "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,	"[i],D", 0, v6 },
+{ "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),	"[1],D", 0, v6 }, /* ldd [rs1+0],d */
+{ "ldsb",	F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "ldsb",	F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
+{ "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1),		"[1+i],d", 0, v6 },
+{ "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1),		"[i+1],d", 0, v6 },
+{ "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* ldsb [rs1+0],d */
+{ "ldsh",	F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
+{ "ldsh",	F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),		"[1+i],d", 0, v6 },
+{ "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),		"[i+1],d", 0, v6 },
+{ "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* ldsh [rs1+0],d */
+{ "ldstub",	F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "ldstub",	F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
+{ "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),		"[1+i],d", 0, v6 },
+{ "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),		"[i+1],d", 0, v6 },
+{ "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ldub",	F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "ldub",	F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
+{ "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1),		"[1+i],d", 0, v6 },
+{ "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1),		"[i+1],d", 0, v6 },
+{ "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* ldub [rs1+0],d */
+{ "lduh",	F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),	"[1+2],d", 0, v6 },
+{ "lduh",	F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),	"[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
+{ "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1),		"[1+i],d", 0, v6 },
+{ "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1),		"[i+1],d", 0, v6 },
+{ "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,	"[i],d", 0, v6 },
+{ "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),	"[1],d", 0, v6 }, /* lduh [rs1+0],d */
+
+
+{ "ldda",	F3(3, 0x13, 0), F3(~3, ~0x13, ~0),		"[1+2]A,d", 0, v6 },
+{ "ldda",	F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
+{ "ldsba",	F3(3, 0x19, 0), F3(~3, ~0x19, ~0),		"[1+2]A,d", 0, v6 },
+{ "ldsba",	F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
+{ "ldsha",	F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),		"[1+2]A,d", 0, v6 },
+{ "ldsha",	F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
+{ "ldstuba",	F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),		"[1+2]A,d", 0, v6 },
+{ "ldstuba",	F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
+{ "lduba",	F3(3, 0x11, 0), F3(~3, ~0x11, ~0),		"[1+2]A,d", 0, v6 },
+{ "lduba",	F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
+{ "lduha",	F3(3, 0x12, 0), F3(~3, ~0x12, ~0),		"[1+2]A,d", 0, v6 },
+{ "lduha",	F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,	"[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
+
+{ "st",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),		"d,[1+2]", 0, v6 },
+{ "st",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),		"d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),			"d,[1+i]", 0, v6 },
+{ "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),			"d,[i+1]", 0, v6 },
+{ "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,		"d,[i]", 0, v6 },
+{ "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),		"d,[1]", 0, v6 }, /* st d,[rs1+0] */
+{ "st",	F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),		"g,[1+2]", 0, v6 },
+{ "st",	F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),		"g,[1]", 0, v6 }, /* st d[rs1+%g0] */
+{ "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1),			"g,[1+i]", 0, v6 },
+{ "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1),			"g,[i+1]", 0, v6 },
+{ "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,		"g,[i]", 0, v6 },
+{ "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),		"g,[1]", 0, v6 }, /* st d,[rs1+0] */
+{ "st",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),		"D,[1+2]", 0, v6 },
+{ "st",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),		"D,[1]", 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),			"D,[1+i]", 0, v6 },
+{ "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),			"D,[i+1]", 0, v6 },
+{ "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,		"D,[i]", 0, v6 },
+{ "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),		"D,[1]", 0, v6 }, /* st d,[rs1+0] */
+{ "st",	F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),		"C,[1+2]", 0, v6 },
+{ "st",	F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),		"C,[1]", 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1),			"C,[1+i]", 0, v6 },
+{ "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1),			"C,[i+1]", 0, v6 },
+{ "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,		"C,[i]", 0, v6 },
+{ "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),		"C,[1]", 0, v6 }, /* st d,[rs1+0] */
+
+{ "st",	F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),	"F,[1+2]", 0, v6 },
+{ "st",	F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),	"F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,		"F,[1+i]", 0, v6 },
+{ "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,		"F,[i+1]", 0, v6 },
+{ "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,		"F,[i]", 0, v6 },
+{ "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|SIMM13(~0),		"F,[1]", 0, v6 }, /* st d,[rs1+0] */
+
+
+
+
+{ "sta",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0),		"d,[1+2]A", 0, v6 },
+{ "sta",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),	"d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
+
+
+
+
+{ "stb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),	"d,[1+2]", 0, v6 },
+{ "stb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),	"d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
+{ "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[1+i]", 0, v6 },
+{ "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[i+1]", 0, v6 },
+{ "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,	"d,[i]", 0, v6 },
+{ "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),	"d,[1]", 0, v6 }, /* stb d,[rs1+0] */
+
+
+
+{ "stba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0),		"d,[1+2]A", 0, v6 },
+{ "stba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),	"d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
+
+
+
+{ "std",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),	"d,[1+2]", 0, v6 },
+{ "std",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),	"d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[1+i]", 0, v6 },
+{ "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[i+1]", 0, v6 },
+{ "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,	"d,[i]", 0, v6 },
+{ "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),	"d,[1]", 0, v6 }, /* std d,[rs1+0] */
+{ "std",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),	"q,[1+2]", 0, v6 },
+{ "std",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),	"q,[1]", 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"q,[1+i]", 0, v6 },
+{ "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"q,[i+1]", 0, v6 },
+{ "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,	"q,[i]", 0, v6 },
+{ "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),	"q,[1]", 0, v6 }, /* std d,[rs1+0] */
+{ "std",	F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),	"g,[1+2]", 0, v6 },
+{ "std",	F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),	"g,[1]", 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1),		"g,[1+i]", 0, v6 },
+{ "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1),		"g,[i+1]", 0, v6 },
+{ "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,	"g,[i]", 0, v6 },
+{ "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),	"g,[1]", 0, v6 }, /* std d,[rs1+0] */
+{ "std",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),	"Q,[1+2]", 0, v6 },
+{ "std",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),	"Q,[1]", 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"Q,[1+i]", 0, v6 },
+{ "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"Q,[i+1]", 0, v6 },
+{ "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,	"Q,[i]", 0, v6 },
+{ "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),	"Q,[1]", 0, v6 }, /* std d,[rs1+0] */
+{ "std",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),	"D,[1+2]", 0, v6 },
+{ "std",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),	"D,[1]", 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"D,[1+i]", 0, v6 },
+{ "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"D,[i+1]", 0, v6 },
+{ "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,	"D,[i]", 0, v6 },
+{ "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),	"D,[1]", 0, v6 }, /* std d,[rs1+0] */
+
+{ "stda",	F3(3, 0x17, 0), F3(~3, ~0x17, ~0),		"d,[1+2]A", 0, v6 },
+{ "stda",	F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),	"d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
+
+{ "sth",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),	"d,[1+2]", 0, v6 },
+{ "sth",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),	"d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
+{ "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[1+i]", 0, v6 },
+{ "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[i+1]", 0, v6 },
+{ "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,	"d,[i]", 0, v6 },
+{ "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),	"d,[1]", 0, v6 }, /* sth d,[+] */
+
+
+
+{ "stha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0),		"d,[1+2]A", 0, v6 },
+{ "stha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),	"d,[1]A", 0, v6 }, /* stha ,[+%] */
+
+
+
+
+
+{ "swap",	F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),	"[1+2],d", 0, v7 },
+{ "swap",	F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),	"[1],d", 0, v7 }, /* swap [rs1+%g0],d */
+{ "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),		"[1+i],d", 0, v7 },
+{ "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),		"[i+1],d", 0, v7 },
+{ "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,	"[i],d", 0, v7 },
+{ "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),	"[1],d", 0, v7 }, /* swap [rs1+0],d */
+
+{ "swapa",	F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),		"[1+2]A,d", 0, v7 },
+{ "swapa",	F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),	"[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
+
+{ "restore",	F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),			"1,2,d", 0, v6 },
+{ "restore",	F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"", 0, v6 }, /* restore %g0,%g0,%g0 */
+{ "restore",	F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),				"1,i,d", 0, v6 },
+{ "restore",	F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),	"", 0, v6 }, /* restore %g0,0,%g0 */
+
+{ "rett",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),	"1+2", F_DELAYED, v6 }, /* rett rs1+rs2 */
+{ "rett",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),	"1", F_DELAYED, v6 },	/* rett rs1,%g0 */
+{ "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,	"1+i", F_DELAYED, v6 }, /* rett rs1+X */
+{ "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,	"i+1", F_DELAYED, v6 }, /* rett X+rs1 */
+{ "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,"i", F_DELAYED, v6 }, /* rett X+rs1 */
+{ "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,	"i", F_DELAYED, v6 },	/* rett X */
+{ "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),	"1", F_DELAYED, v6 },	/* rett rs1+0 */
+
+{ "save",	F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "save",	F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),		"1,i,d", 0, v6 },
+
+{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),	       "", F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
+{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
+
+{ "jmpl",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),	"1+2,d", F_DELAYED, v6 },
+{ "jmpl",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),	"1,d", F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
+{ "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),	"1,d", F_DELAYED, v6 }, /* jmpl rs1+0,d */
+{ "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,	"i,d", F_DELAYED, v6 }, /* jmpl %g0+i,d */
+{ "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1),		"1+i,d", F_DELAYED, v6 },
+{ "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1),		"i+1,d", F_DELAYED, v6 },
+{ "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,	"i,d", F_DELAYED, v6 },
+
+ /* The 1<<12 is a long story.  It is necessary.  For more info, please contact rich@cygnus.com */
+{ "sll",	F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|ASI(~0),	"1,2,d", 0, v6 },
+{ "sll",	F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12),		"1,i,d", 0, v6 },
+{ "sra",	F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0),	"1,2,d", 0, v6 },
+{ "sra",	F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12),		"1,i,d", 0, v6 },
+{ "srl",	F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0),	"1,2,d", 0, v6 },
+{ "srl",	F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12),		"1,i,d", 0, v6 },
+
+
+
+{ "mulscc",	F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "mulscc",	F3(2, 0x24, 1), F3(~2, ~0x24, ~1),		"1,i,d", 0, v6 },
+
+{ "clr",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"d", F_ALIAS, v6 }, /* or %g0,%g0,d */
+{ "clr",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),		"d", F_ALIAS, v6 }, /* or %g0,0,d	*/
+{ "clr",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),		"[1+2]", F_ALIAS, v6 },
+{ "clr",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),		"[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
+{ "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,			"[1+i]", F_ALIAS, v6 },
+{ "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,			"[i+1]", F_ALIAS, v6 },
+{ "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,		"[i]", F_ALIAS, v6 },
+{ "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),		"[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
+
+{ "clrb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),	"[1+2]", F_ALIAS, v6 },
+{ "clrb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),	"[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
+{ "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,		"[1+i]", F_ALIAS, v6 },
+{ "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,		"[i+1]", F_ALIAS, v6 },
+{ "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,	"[i]", F_ALIAS, v6 },
+
+{ "clrh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),	"[1+2]", F_ALIAS, v6 },
+{ "clrh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),	"[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
+{ "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,		"[1+i]", F_ALIAS, v6 },
+{ "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,		"[i+1]", F_ALIAS, v6 },
+{ "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,	"[i]", F_ALIAS, v6 },
+
+{ "orcc",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "orcc",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1),		"1,i,d", 0, v6 },
+{ "orcc",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1),		"i,1,d", 0, v6 },
+
+{ "orncc",	F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "orncc",	F3(2, 0x16, 1), F3(~2, ~0x16, ~1),		"1,i,d", 0, v6 },
+{ "orncc",	F3(2, 0x16, 1), F3(~2, ~0x16, ~1),		"i,1,d", 0, v6 },
+
+{ "orn",	F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "orn",	F3(2, 0x06, 1), F3(~2, ~0x06, ~1),		"1,i,d", 0, v6 },
+{ "orn",	F3(2, 0x06, 1), F3(~2, ~0x06, ~1),		"i,1,d", 0, v6 },
+
+{ "tst",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),	"1", 0, v6 }, /* orcc rs1, %g0, %g0 */
+{ "tst",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0),	"2", 0, v6 }, /* orcc %g0, rs2, %g0 */
+{ "tst",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),	"1", 0, v6 }, /* orcc rs1, 0, %g0 */
+
+{ "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|ASI(~0),		"1,2,m", 0, v8 }, /* wr r,r,%asrX */
+{ "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),	"1,2,y", 0, v6 }, /* wr r,r,%y */
+{ "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1),			"1,i,m", 0, v8 }, /* wr r,i,%asrX */
+{ "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1)|RD_G0,		"1,i,y", 0, v6 }, /* wr r,i,%y */
+{ "wr",	F3(2, 0x31, 0),		F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),	"1,2,p", 0, v6 }, /* wr r,r,%psr */
+{ "wr",	F3(2, 0x31, 1),		F3(~2, ~0x31, ~1)|RD_G0,		"1,i,p", 0, v6 }, /* wr r,i,%psr */
+{ "wr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),	"1,2,w", 0, v6 }, /* wr r,r,%wim */
+{ "wr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1)|RD_G0,		"1,i,w", 0, v6 }, /* wr r,i,%wim */
+{ "wr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),	"1,2,t", 0, v6 }, /* wr r,r,%tbr */
+{ "wr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1)|RD_G0,		"1,i,t", 0, v6 }, /* wr r,i,%tbr */
+
+
+{ "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|SIMM13(~0),		"M,d", 0, v8 }, /* rd %asr1,r */
+{ "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),	"y,d", 0, v6 }, /* rd %y,r */
+{ "rd",	F3(2, 0x2b, 0),			F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),	"t,d", 0, v6 }, /* rd %tbr,r */
+
+{ "rd",	F3(2, 0x29, 0),			F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),	"p,d", 0, v6 }, /* rd %psr,r */
+{ "rd",	F3(2, 0x2a, 0),			F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),	"w,d", 0, v6 }, /* rd %wim,r */
+
+{ "mov",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|ASI(~0),		"1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
+{ "mov",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),	"1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
+{ "mov",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1),			"1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
+{ "mov",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1)|RD_G0,		"1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
+{ "mov",	F3(2, 0x31, 0),		F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),	"1,2,p", F_ALIAS, v6 }, /* wr r,r,%psr */
+{ "mov",	F3(2, 0x31, 1),		F3(~2, ~0x31, ~1)|RD_G0,		"1,i,p", F_ALIAS, v6 }, /* wr r,i,%psr */
+{ "mov",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),	"1,2,w", F_ALIAS, v6 }, /* wr r,r,%wim */
+{ "mov",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1)|RD_G0,		"1,i,w", F_ALIAS, v6 }, /* wr r,i,%wim */
+{ "mov",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),	"1,2,t", F_ALIAS, v6 }, /* wr r,r,%tbr */
+{ "mov",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1)|RD_G0,		"1,i,t", F_ALIAS, v6 }, /* wr r,i,%tbr */
+
+{ "mov",	F3(2, 0x28, 0),		 F3(~2, ~0x28, ~0)|SIMM13(~0),			"M,d", F_ALIAS, v8 }, /* rd %asr1,r */
+{ "mov",	F3(2, 0x28, 0),		 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),		"y,d", F_ALIAS, v6 }, /* rd %y,r */
+{ "mov",	F3(2, 0x29, 0),		 F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),		"p,d", F_ALIAS, v6 }, /* rd %psr,r */
+{ "mov",	F3(2, 0x2a, 0),		 F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),		"w,d", F_ALIAS, v6 }, /* rd %wim,r */
+{ "mov",	F3(2, 0x2b, 0),		 F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),		"t,d", F_ALIAS, v6 }, /* rd %tbr,r */
+
+{ "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),	"1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
+{ "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1),		"i,y", F_ALIAS, v6 },
+{ "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),	"1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
+{ "mov",	F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0),	"1,p", F_ALIAS, v6 }, /* wr rs1,%g0,%psr */
+{ "mov",	F3(2, 0x31, 1), F3(~2, ~0x31, ~1),		"i,p", F_ALIAS, v6 },
+{ "mov",	F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0),	"1,p", F_ALIAS, v6 }, /* wr rs1,0,%psr */
+{ "mov",	F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0),	"1,w", F_ALIAS, v6 }, /* wr rs1,%g0,%wim */
+{ "mov",	F3(2, 0x32, 1), F3(~2, ~0x32, ~1),		"i,w", F_ALIAS, v6 },
+{ "mov",	F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0),	"1,w", F_ALIAS, v6 }, /* wr rs1,0,%wim */
+{ "mov",	F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0),	"1,t", F_ALIAS, v6 }, /* wr rs1,%g0,%tbr */
+{ "mov",	F3(2, 0x33, 1), F3(~2, ~0x33, ~1),		"i,t", F_ALIAS, v6 },
+{ "mov",	F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0),	"1,t", F_ALIAS, v6 }, /* wr rs1,0,%tbr */
+
+{ "mov",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),	"2,d", 0, v6 }, /* or %g0,rs2,d */
+{ "mov",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,		"i,d", 0, v6 }, /* or %g0,i,d	*/
+{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),		"1,d", 0, v6 }, /* or rs1,%g0,d   */
+{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),		"1,d", 0, v6 }, /* or rs1,0,d */
+
+{ "or",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "or",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"1,i,d", 0, v6 },
+{ "or",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"i,1,d", 0, v6 },
+
+{ "bset",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),	"2,r", F_ALIAS, v6 },	/* or rd,rs2,rd */
+{ "bset",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"i,r", F_ALIAS, v6 },	/* or rd,i,rd */
+
+{ "andn",	F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "andn",	F3(2, 0x05, 1), F3(~2, ~0x05, ~1),		"1,i,d", 0, v6 },
+{ "andn",	F3(2, 0x05, 1), F3(~2, ~0x05, ~1),		"i,1,d", 0, v6 },
+
+{ "andncc",	F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "andncc",	F3(2, 0x15, 1), F3(~2, ~0x15, ~1),		"1,i,d", 0, v6 },
+{ "andncc",	F3(2, 0x15, 1), F3(~2, ~0x15, ~1),		"i,1,d", 0, v6 },
+
+{ "bclr",	F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),	"2,r", F_ALIAS, v6 },	/* andn rd,rs2,rd */
+{ "bclr",	F3(2, 0x05, 1), F3(~2, ~0x05, ~1),		"i,r", F_ALIAS, v6 },	/* andn rd,i,rd */
+
+{ "cmp",	F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),	"1,2", 0, v6 },	/* subcc rs1,rs2,%g0 */
+{ "cmp",	F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,		"1,i", 0, v6 },	/* subcc rs1,i,%g0 */
+
+{ "sub",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "sub",	F3(2, 0x04, 1), F3(~2, ~0x04, ~1),		"1,i,d", 0, v6 },
+
+{ "subcc",	F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "subcc",	F3(2, 0x14, 1), F3(~2, ~0x14, ~1),		"1,i,d", 0, v6 },
+
+{ "subx",	F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "subx",	F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),		"1,i,d", 0, v6 },
+
+{ "subxcc",	F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "subxcc",	F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),		"1,i,d", 0, v6 },
+
+{ "and",	F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "and",	F3(2, 0x01, 1), F3(~2, ~0x01, ~1),		"1,i,d", 0, v6 },
+{ "and",	F3(2, 0x01, 1), F3(~2, ~0x01, ~1),		"i,1,d", 0, v6 },
+
+{ "andcc",	F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "andcc",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1),		"1,i,d", 0, v6 },
+{ "andcc",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1),		"i,1,d", 0, v6 },
+
+{ "dec",	F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },	/* sub rd,1,rd */
+{ "dec",	F3(2, 0x04, 1),		    F3(~2, ~0x04, ~1),		     "i,r", F_ALIAS, v6 },	/* sub rd,i,rd */
+{ "deccc",	F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },	/* subcc rd,1,rd */
+{ "deccc",	F3(2, 0x14, 1),		    F3(~2, ~0x14, ~1),		     "i,r", F_ALIAS, v6 },	/* subcc rd,i,rd */
+{ "inc",	F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },	/* add rs1,1,rsd */
+{ "inc",	F3(2, 0x00, 1),		    F3(~2, ~0x00, ~1),		     "i,r", F_ALIAS, v6 },	/* add rs1,i,rsd */
+{ "inccc",	F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },	/* addcc rd,1,rd */
+{ "inccc",	F3(2, 0x10, 1),		    F3(~2, ~0x10, ~1),		     "i,r", F_ALIAS, v6 },	/* addcc rd,i,rd */
+
+{ "btst",	F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 },	/* andcc rs1,rs2,%g0 */
+{ "btst",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },	/* andcc rs1,i,%g0 */
+
+{ "neg",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
+{ "neg",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "x", F_ALIAS, v6 }, /* sub %g0,rd,rd */
+
+{ "add",	F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "add",	F3(2, 0x00, 1), F3(~2, ~0x00, ~1),		"1,i,d", 0, v6 },
+{ "add",	F3(2, 0x00, 1), F3(~2, ~0x00, ~1),		"i,1,d", 0, v6 },
+{ "addcc",	F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "addcc",	F3(2, 0x10, 1), F3(~2, ~0x10, ~1),		"1,i,d", 0, v6 },
+{ "addcc",	F3(2, 0x10, 1), F3(~2, ~0x10, ~1),		"i,1,d", 0, v6 },
+{ "addx",	F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "addx",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"1,i,d", 0, v6 },
+{ "addx",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"i,1,d", 0, v6 },
+{ "addxcc",	F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "addxcc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"1,i,d", 0, v6 },
+{ "addxcc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"i,1,d", 0, v6 },
+
+{ "smul",	F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"1,i,d", 0, v8 },
+{ "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"i,1,d", 0, v8 },
+{ "smulcc",	F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "smulcc",	F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),		"1,i,d", 0, v8 },
+{ "smulcc",	F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),		"i,1,d", 0, v8 },
+{ "umul",	F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "umul",	F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),		"1,i,d", 0, v8 },
+{ "umul",	F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),		"i,1,d", 0, v8 },
+{ "umulcc",	F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "umulcc",	F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),		"1,i,d", 0, v8 },
+{ "umulcc",	F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),		"i,1,d", 0, v8 },
+{ "sdiv",	F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "sdiv",	F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),		"1,i,d", 0, v8 },
+{ "sdiv",	F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),		"i,1,d", 0, v8 },
+{ "sdivcc",	F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "sdivcc",	F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),		"1,i,d", 0, v8 },
+{ "sdivcc",	F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),		"i,1,d", 0, v8 },
+{ "udiv",	F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "udiv",	F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),		"1,i,d", 0, v8 },
+{ "udiv",	F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),		"i,1,d", 0, v8 },
+{ "udivcc",	F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),	"1,2,d", 0, v8 },
+{ "udivcc",	F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),		"1,i,d", 0, v8 },
+{ "udivcc",	F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),		"i,1,d", 0, v8 },
+
+{ "call",	F1(0x1), F1(~0x1), "L", F_DELAYED, v6 },
+{ "call",	F1(0x1), F1(~0x1), "L,#", F_DELAYED, v6 },
+{ "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_DELAYED, v6 }, /* jmpl rs1+%g0, %o7 */
+{ "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_DELAYED, v6 },
+
+{ "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf),
+"1+2", F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
+{ "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf),
+"1+2,#", F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
+
+{ "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
+"1+i", F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
+{ "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
+"1+i,#", F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
+{ "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
+"i+1", F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
+{ "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
+"i+1,#", F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
+
+/* Conditional instructions.
+
+   Because this part of the table was such a mess earlier, I have
+   macrofied it so that all the branches and traps are generated from
+   a single-line description of each condition value.  John Gilmore. */
+
+/* Define branches -- one annulled, one without, etc. */
+#define br(opcode, mask, lose, flags) \
+ { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), v6 }, \
+ { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), v6 }
+
+
+/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
+#define tr(opcode, mask, lose, flags) \
+ { opcode, (mask)|IMMED, (lose)|RS1_G0,		"i",     (flags), v6 }, /* %g0 + imm */ \
+ { opcode, (mask)|IMMED, (lose),		"1+i",   (flags), v6 }, /* rs1 + imm */ \
+ { opcode, (mask), IMMED|(lose),		"1+2",   (flags), v6 }, /* rs1 + rs2 */ \
+ { opcode, (mask), IMMED|(lose)|RS2_G0,		"1",     (flags), v6 } /* rs1 + %g0 */
+
+/* Define both branches and traps based on condition mask */
+#define cond(bop, top, mask, flags) \
+  br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
+  tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), (flags))
+
+/* Define all the conditions, all the branches, all the traps.  */
+
+cond ("b",	"t",    CONDA, 0),
+cond ("ba",	"ta",   CONDA, F_ALIAS), /* for nothing */
+cond ("bcc",	"tcc",  CONDCC, 0),
+cond ("bcs",	"tcs",  CONDCS, 0),
+cond ("be",	"te",   CONDE, 0),
+cond ("beq",	"teq",  CONDE, F_ALIAS), /* for be */
+cond ("bg",	"tg",   CONDG, 0),
+cond ("bgt",	"tgt",   CONDG, F_ALIAS),
+cond ("bge",	"tge",  CONDGE, 0),
+cond ("bgeu",	"tgeu", CONDGEU, F_ALIAS), /* for cc */
+cond ("bgu",	"tgu",  CONDGU, 0),
+cond ("bl",	"tl",   CONDL, 0),
+cond ("blt",	"tlt",   CONDL, F_ALIAS),
+cond ("ble",	"tle",  CONDLE, 0),
+cond ("bleu",	"tleu", CONDLEU, 0),
+cond ("blu",	"tlu",  CONDLU, F_ALIAS), /* for cs */
+cond ("bn",	"tn",   CONDN, 0),
+cond ("bne",	"tne",  CONDNE, 0),
+cond ("bneg",	"tneg", CONDNEG, 0),
+cond ("bnz",	"tnz",  CONDNZ, F_ALIAS), /* for ne */
+cond ("bpos",	"tpos", CONDPOS, 0),
+cond ("bvc",	"tvc",  CONDVC, 0),
+cond ("bvs",	"tvs",  CONDVS, 0),
+cond ("bz",	"tz",   CONDZ, F_ALIAS), /* for e */
+
+#undef cond
+#undef br
+#undef tr
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#define brfc(opcode, mask, lose, flags) \
+ { opcode, (mask), ANNUL|(lose), "l",    flags|F_DELAYED, v6 }, \
+ { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, v6 }
+
+
+#define condfc(fop, cop, mask, flags) \
+  brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
+  brfc(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags) \
+
+condfc("fb",	"cb",	 0x8, 0),
+condfc("fba",	"cba",	 0x8, F_ALIAS),
+condfc("fbe",	"cb0",	 0x9, 0),
+condfc("fbg",	"cb2",	 0x6, 0),
+condfc("fbge",	"cb02",	 0xb, 0),
+condfc("fbl",	"cb1",	 0x4, 0),
+condfc("fble",	"cb01",	 0xd, 0),
+condfc("fblg",	"cb12",	 0x2, 0),
+condfc("fbn",	"cbn",	 0x0, 0),
+condfc("fbne",	"cb123", 0x1, 0),
+condfc("fbo",	"cb012", 0xf, 0),
+condfc("fbu",	"cb3",	 0x7, 0),
+condfc("fbue",	"cb03",	 0xa, 0),
+condfc("fbug",	"cb23",	 0x5, 0),
+condfc("fbuge",	"cb023", 0xc, 0),
+condfc("fbul",	"cb13",	 0x3, 0),
+condfc("fbule",	"cb013", 0xe, 0),
+
+#undef condfc
+#undef brfc
+
+{ "jmp",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),	"1+2", F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
+{ "jmp",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),	"1", F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
+{ "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,		"1+i", F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
+{ "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,		"i+1", F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
+{ "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,	"i", F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
+
+{ "nop",	F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
+
+{ "set",	F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 },
+
+{ "sethi",	F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
+
+{ "taddcc",	F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "taddcc",	F3(2, 0x20, 1), F3(~2, ~0x20, ~1),		"1,i,d", 0, v6 },
+{ "taddcc",	F3(2, 0x20, 1), F3(~2, ~0x20, ~1),		"i,1,d", 0, v6 },
+{ "taddcctv",	F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "taddcctv",	F3(2, 0x22, 1), F3(~2, ~0x22, ~1),		"1,i,d", 0, v6 },
+{ "taddcctv",	F3(2, 0x22, 1), F3(~2, ~0x22, ~1),		"i,1,d", 0, v6 },
+
+{ "tsubcc",	F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "tsubcc",	F3(2, 0x21, 1), F3(~2, ~0x21, ~1),		"1,i,d", 0, v6 },
+{ "tsubcctv",	F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "tsubcctv",	F3(2, 0x23, 1), F3(~2, ~0x23, ~1),		"1,i,d", 0, v6 },
+
+{ "unimp",	F2(0x0, 0x0), 0xffc00000, "n", 0, v6 },
+
+{ "iflush",	F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),	"1+2", 0, v6 },
+{ "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"1+i", 0, v6 },
+{ "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"i+1", 0, v6 },
+{ "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,	"i", 0, v6 },
+
+{ "xnor",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "xnor",	F3(2, 0x07, 1), F3(~2, ~0x07, ~1),		"1,i,d", 0, v6 },
+{ "xnor",	F3(2, 0x07, 1), F3(~2, ~0x07, ~1),		"i,1,d", 0, v6 },
+{ "xnorcc",	F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "xnorcc",	F3(2, 0x17, 1), F3(~2, ~0x17, ~1),		"1,i,d", 0, v6 },
+{ "xnorcc",	F3(2, 0x17, 1), F3(~2, ~0x17, ~1),		"i,1,d", 0, v6 },
+{ "xor",	F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "xor",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"1,i,d", 0, v6 },
+{ "xor",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"i,1,d", 0, v6 },
+{ "xorcc",	F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),	"1,2,d", 0, v6 },
+{ "xorcc",	F3(2, 0x13, 1), F3(~2, ~0x13, ~1),		"1,i,d", 0, v6 },
+{ "xorcc",	F3(2, 0x13, 1), F3(~2, ~0x13, ~1),		"i,1,d", 0, v6 },
+
+{ "not",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
+{ "not",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
+
+{ "btog",	F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),	"2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
+{ "btog",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
+
+{ "fpop1",	F3F(2, 0x34, 0), F3F(~2, ~0x34, ~1), "[1+2],d", 0, v6 },
+{ "fpop2",	F3F(2, 0x35, 0), F3F(~2, ~0x35, ~1), "[1+2],d", 0, v6 },
+
+/* float-start */
+{ "fdtoi",	F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", 0, v6 },
+{ "fstoi",	F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", 0, v6 },
+
+ /* all of these conversions are confused and probably wrong. */
+{ "fitod",	F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", 0, v6 },
+{ "fitos",	F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", 0, v6 },
+
+{ "fitoq",	F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", 0, v8 },
+
+
+{ "fdtoq",	F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", 0, v8 },
+{ "fdtos",	F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", 0, v6 },
+{ "fqtod",	F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", 0, v8 },
+{ "fqtos",	F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", 0, v8 },
+{ "fstod",	F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", 0, v6 },
+{ "fstoq",	F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", 0, v8 },
+
+
+
+
+
+{ "fqtoi",	F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", 0, v8 },
+
+
+{ "fdivd",	F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", 0, v6 },
+{ "fdivq",	F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", 0, v8 },
+{ "fdivs",	F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", 0, v6 },
+{ "fmuld",	F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", 0, v6 },
+{ "fmulq",	F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", 0, v8 },
+{ "fmuls",	F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", 0, v6 },
+
+{ "fdmulq",	F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", 0, v8 },
+{ "fsmuld",	F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", 0, v8 },
+
+{ "fsqrtd",	F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", 0, v7 },
+{ "fsqrtq",	F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", 0, v8 },
+{ "fsqrts",	F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", 0, v7 },
+
+{ "fabsq",	F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", 0, v6 },
+{ "fabss",	F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", 0, v6 },
+{ "fmovq",	F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", 0, v6 },
+{ "fmovs",	F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", 0, v6 },
+{ "fnegq",	F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", 0, v6 },
+{ "fnegs",	F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", 0, v6 },
+
+
+{ "faddd",	F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", 0, v6 },
+{ "faddq",	F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", 0, v8 },
+{ "fadds",	F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", 0, v6 },
+{ "fsubd",	F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", 0, v6 },
+{ "fsubq",	F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", 0, v8 },
+{ "fsubs",	F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", 0, v6 },
+
+#define CMPFCC(x)	(((x)&0x3)<<25)
+
+{ "fcmpd",	          F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RS1_G0, "v,B",   0, v6 },
+{ "fcmped",	          F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RS1_G0, "v,B",   0, v6 },
+{ "fcmpeq",	          F3F(2, 0x34, 0x057),            F3F(~2, ~0x34, ~0x057),	 "V,R", 0, v8 },
+{ "fcmpes",	          F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RS1_G0, "e,f",   0, v6 },
+{ "fcmpq",	          F3F(2, 0x34, 0x053),            F3F(~2, ~0x34, ~0x053),	 "V,R", 0, v8 },
+{ "fcmps",	          F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RS1_G0, "e,f",   0, v6 },
+
+{ "cpop1",	F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", 0, v6 },
+{ "cpop2",	F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", 0, v6 },
+    
+
+
+};
+
+#define NUMOPCODES ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]))
+
+/*
+ * Local Variables:
+ * fill-column: 131
+ * comment-column: 0
+ * End:
+ */
+
+/* end of sparc-opcode.h */
diff --git a/gnu/usr.bin/gas/opcode/tahoe.h b/gnu/usr.bin/gas/opcode/tahoe.h
new file mode 100644
index 00000000000..27099a4db08
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/tahoe.h
@@ -0,0 +1,247 @@
+/* tahoe-opcode.h - tahoe-specific
+ * Not part of GAS yet
+ *
+ * Ported by the State University of New York at Buffalo by the Distributed
+ * Computer Systems Lab, Department of Computer Science, 1991. (And by Dale
+ * Wiles who was unemployed at the time.)
+ */
+
+struct tot_wot                  /* tahoe opcode table: wot to do with this */
+                                /* particular opcode */
+{
+  char *args;			/* how to compile said opcode */
+  tahoe_opcodeT code;		/* The opcode. */
+};
+
+struct tot                      /* tahoe opcode text */
+{
+  char *name;			/* opcode name: lowercase string  [key]  */
+  struct tot_wot detail;	/* rest of opcode table          [datum] */
+};
+
+static struct tot
+totstrs[] =
+{
+{    "halt",	{"",			0x00	} },
+{    "sinf",    {"",                    0x05    } },
+{    "ldf",     {"rl",                  0x06    } },
+{    "ldd",     {"rq",                  0x07    } },
+{    "addb2",	{"rbmb",		0x08	} },
+{    "movb",	{"rbwb",		0x09	} },
+{    "addw2",	{"rwmw",		0x0a	} },
+{    "movw",	{"rwww",		0x0b	} },
+{    "addl2",	{"rlml",		0x0c	} },
+{    "movl",	{"rlwl",		0x0d	} },
+{    "bbs",	{"rlvlbw",		0x0e	} },
+{    "nop",     {"",                    0x10    } },
+{    "brb",	{"bb",			0x11	} },
+{    "brw",	{"bw",			0x13	} },
+{    "cosf",    {"",                    0x15    } },
+{    "lnf",     {"rl",                  0x16    } },
+{    "lnd",     {"rq",                  0x17    } },
+{    "addb3",	{"rbrbwb",		0x18	} },
+  /* cmpb is wrong in the "offical" (what a joke!) text. It's not "rbwb" */
+{    "cmpb",	{"rbrb",		0x19	} }, 
+{    "addw3",	{"rwrwww",		0x1a	} },
+  /* cmpw is wrong in the "offical" text. It's not "rwww" */
+{    "cmpw",	{"rwrw",		0x1b	} },
+{    "addl3",	{"rlrlwl",		0x1c	} },
+  /* cmpl is wrong in the "offical" text. It's not "rlwl" */
+{    "cmpl",	{"rlrl",		0x1d	} },
+{    "bbc",	{"rlvlbw",		0x1e	} },
+{    "rei",	{"",			0x20	} },
+{    "bneq",	{"bb",			0x21	} },
+{    "bnequ",	{"bb",			0x21	} },
+{    "cvtwl",	{"rwwl",		0x23	} },
+{    "stf",     {"wl",                  0x26    } },
+{    "std",     {"wq",                  0x27    } },
+{    "subb2",	{"rbmb",		0x28	} },
+{    "mcomb",	{"rbwb",		0x29	} },
+{    "subw2",	{"rwmw",		0x2a	} },
+{    "mcomw",	{"rwww",		0x2b	} },
+{    "subl2",   {"rlml",                0x2c    } },
+{    "mcoml",   {"rlwl",                0x2d    } },
+{    "emul",	{"rlrlrlwq",		0x2e	} },
+{    "aoblss",	{"rlmlbw",		0x2f	} },
+{    "bpt",	{"",			0x30	} },
+{    "beql",	{"bb",			0x31	} },
+{    "beqlu",	{"bb",			0x31	} },
+{    "cvtwb",	{"rwwb",		0x33	} },
+{    "logf",    {"",                    0x35    } },
+{    "cmpf",    {"rl",                  0x36    } },
+{    "cmpd",    {"rq",                  0x37    } },
+{    "subb3",	{"rbrbwb",		0x38	} },
+{    "bitb",	{"rbrb",		0x39	} },
+{    "subw3",	{"rwrwww",		0x3a	} },
+{    "bitw",	{"rwrw",		0x3b	} },
+{    "subl3",	{"rlrlwl",		0x3c	} },
+{    "bitl",	{"rlrl",		0x3d	} },
+{    "ediv",	{"rlrqwlwl",		0x3e	} },
+{    "aobleq",	{"rlmlbw",		0x3f	} },
+{    "ret",	{"",			0x40	} },
+{    "bgtr",	{"bb",			0x41	} },
+{    "sqrtf",   {"",                    0x45    } },
+{    "cmpf2",   {"rlrl",                0x46    } },
+{    "cmpd2",   {"rqrq",                0x47    } },
+{    "shll",    {"rbrlwl",              0x48    } },
+{    "clrb",	{"wb",			0x49	} },
+{    "shlq",	{"rbrqwq",		0x4a	} },
+{    "clrw",	{"ww",			0x4b	} },
+{    "mull2",	{"rlml",		0x4c	} },
+{    "clrl",	{"wl",			0x4d	} },
+{    "shal",    {"rbrlwl",		0x4e	} },
+{    "bleq",	{"bb",			0x51	} },
+{    "expf",    {"",                    0x55    } },
+{    "tstf",    {"",                    0x56    } },
+{    "tstd",    {"",                    0x57    } },
+{    "shrl",    {"rbrlwl",		0x58	} },
+{    "tstb",	{"rb",			0x59	} },
+{    "shrq",    {"rbrqwq",		0x5a	} },
+{    "tstw",	{"rw",			0x5b	} },
+{    "mull3",	{"rlrlwl",		0x5c	} },
+{    "tstl",	{"rl",			0x5d	} },
+{    "shar",	{"rbrlwl",		0x5e	} },
+{    "bbssi",	{"rlmlbw",		0x5f	} },
+{    "ldpctx",	{"",			0x60	} },
+{    "pushd",   {"",                    0x67    } },
+{    "incb",	{"mb",			0x69	} },
+{    "incw",	{"mw",			0x6b	} },
+{    "divl2",	{"rlml",		0x6c	} },
+{    "incl",	{"ml",			0x6d	} },
+{    "cvtlb",	{"rlwb",		0x6f	} },
+{    "svpctx",	{"",			0x70	} },
+{    "jmp",	{"ab",			0x71	} },
+{    "cvlf",    {"rl",                  0x76    } },
+{    "cvld",    {"rl",                  0x77    } },
+{    "decb",	{"mb",			0x79	} },
+{    "decw",	{"mw",			0x7b	} },
+{    "divl3",	{"rlrlwl",		0x7c	} },
+{    "decl",	{"ml",			0x7d	} },
+{    "cvtlw",	{"rlww",		0x7f	} },
+{    "bgeq",	{"bb",			0x81	} },
+{    "movs2",	{"abab",		0x82	} },
+{    "cvfl",    {"wl",                  0x86    } },
+{    "cvdl",    {"wl",                  0x87    } },
+{    "orb2",	{"rbmb",		0x88	} },
+{    "cvtbl",	{"rbwl",		0x89	} },
+{    "orw2",	{"rwmw",		0x8a	} },
+{    "bispsw",	{"rw",			0x8b	} },
+{    "orl2",    {"rlml",                0x8c    } },
+{    "adwc",	{"rlml",		0x8d	} },
+{    "adda", 	{"rlml",		0x8e	} },
+{    "blss",	{"bb",			0x91	} },
+{    "cmps2",   {"abab",		0x92	} },
+{    "ldfd",    {"rl",                  0x97    } },
+{    "orb3",	{"rbrbwb",		0x98	} },
+{    "cvtbw",	{"rbww",		0x99	} },
+{    "orw3",   	{"rwrwww",		0x9a	} },
+{    "bicpsw",	{"rw",			0x9b	} },
+{    "orl3",    {"rlrlwl",              0x9c    } },
+{    "sbwc",	{"rlml",		0x9d	} },
+{    "suba",    {"rlml",                0x9e    } },
+{    "bgtru",	{"bb",			0xa1	} },
+{    "cvdf",    {"",                    0xa6    } },
+{    "andb2",   {"rbmb",		0xa8    } },
+{    "movzbl",	{"rbwl",		0xa9	} },
+{    "andw2",   {"rwmw",		0xaa    } },
+{    "loadr",   {"rwal",		0xab	} },
+{    "andl2",   {"rlml",		0xac    } },
+{    "mtpr",	{"rlrl",		0xad	} },
+{    "ffs",	{"rlwl",		0xae	} },
+{    "blequ",	{"bb",			0xb1	} },
+{    "negf",    {"",                    0xb6    } },
+{    "negd",    {"",                    0xb7    } },
+{    "andb3",   {"rbrbwb",              0xb8    } },
+{    "movzbw",	{"rbww",		0xb9	} },
+{    "andw3",   {"rwrwww",		0xba    } },
+{    "storer",  {"rwal",                0xbb    } },
+{    "andl3",   {"rlrlwl",		0xbc    } },
+{    "mfpr",	{"rlwl",		0xbd	} },
+{    "ffc",	{"rlwl",		0xbe	} },
+{    "calls",	{"rbab",		0xbf	} },
+{    "prober",	{"rbabrl",		0xc0	} },
+{    "bvc",	{"bb",			0xc1	} },
+{    "movs3",	{"ababrw",		0xc2	} },
+{    "movzwl",	{"rwwl",		0xc3	} },
+{    "addf",    {"rl",                  0xc6    } },
+{    "addd",    {"rq",                  0xc7    } },
+{    "xorb2",   {"rbmb",                0xc8    } },
+{    "movob",   {"rbwb",                0xc9    } },
+{    "xorw2",   {"rwmw",                0xca    } },
+{    "movow",   {"rwww",                0xcb	} },
+{    "xorl2",	{"rlml",                0xcc    } },
+{    "movpsl",  {"wl",                  0xcd    } },
+{    "kcall",   {"rw",			0xcf	} },
+{    "probew",  {"rbabrl",		0xd0	} },
+{    "bvs",     {"bb",			0xd1	} },
+{    "cmps3",   {"ababrw",		0xd2	} },
+{    "subf",    {"rq",                  0xd6    } },
+{    "subd",    {"rq",                  0xd7    } },
+{    "xorb3",	{"rbrbwb",		0xd8	} },
+{    "pushb",   {"rb",			0xd9	} },
+{    "xorw3",	{"rwrwww",		0xda	} },
+{    "pushw",   {"rw", 			0xdb	} },
+{    "xorl3",	{"rlrlwl",		0xdc	} },
+{    "pushl",	{"rl",			0xdd	} },
+{    "insque",	{"abab",		0xe0	} },
+{    "bcs",	{"bb",			0xe1	} },
+{    "bgequ",	{"bb",			0xe1	} },
+{    "mulf",    {"rq",                  0xe6    } },
+{    "muld",    {"rq",                  0xe7    } },
+{    "mnegb",	{"rbwb",		0xe8	} },
+{    "movab",	{"abwl",		0xe9	} },
+{    "mnegw",	{"rwww",		0xea	} },
+{    "movaw",	{"awwl",		0xeb	} },
+{    "mnegl",	{"rlwl",		0xec	} },
+{    "moval",	{"alwl",		0xed	} },
+{    "remque",	{"ab",  		0xf0	} },
+{    "bcc",	{"bb",			0xf1	} },
+{    "blssu",	{"bb",			0xf1	} },
+{    "divf",    {"rq",                  0xf6    } },
+{    "divd",    {"rq",                  0xf7    } },
+  /* movblk is really "alalrw" but 'as' won't accept it,
+     'cc' and 'gcc' also produce code this way. */
+{    "movblk",  {"",                    0xf8	} },
+{    "pushab",	{"ab",			0xf9	} },
+{    "pushaw",	{"aw",			0xfb	} },
+{    "casel",	{"rlrlrl",		0xfc	} },
+{    "pushal",	{"al",			0xfd	} },
+{    "callf",	{"rbab",		0xfe	} },
+{      "",   ""          } /* empty is end sentinel */
+};
+
+/* These are synthetic instructions, where the assembler will munge
+   the addressings modes for you. */
+static struct tot
+synthetic_totstrs[] =
+{
+{    "jr",	{"b-",			0x11	} },
+{    "jbr",	{"b-",			0x11	} },
+
+{    "jneq",	{"b?",			0x21	} },
+{    "jnequ",	{"b?",			0x21	} },
+{    "jeql",	{"b?",			0x31	} },
+{    "jeqlu",	{"b?",			0x31	} },
+{    "jgtr",	{"b?",			0x41	} },
+{    "jleq",	{"b?",			0x51	} },
+{    "jgeq",	{"b?",			0x81	} },
+{    "jlss",	{"b?",			0x91	} },
+{    "jgtru",	{"b?",			0xa1	} },
+{    "jlequ",	{"b?",			0xb1	} },
+{    "jvc",	{"b?",			0xc1	} },
+{    "jvs",     {"b?",			0xd1	} },
+{    "jcs",	{"b?",			0xe1	} },
+{    "jgequ",	{"b?",			0xe1	} },
+{    "jcc",	{"b?",			0xf1	} },
+{    "jlssu",	{"b?",			0xf1	} },
+
+{    "jbs",	{"rlvlb!",		0x0e	} },
+{    "jbc",	{"rlvlb!",		0x1e	} },
+
+{    "aojlss",	{"rlmlb:",		0x2f	} },
+{    "jaoblss",	{"rlmlb:",		0x2f	} },
+{    "aojleq",	{"rlmlb:",		0x3f	} },
+{    "jaobleq",	{"rlmlb:",		0x3f	} },
+{    "jbssi",	{"rlmlb:",		0x5f	} },
+  {      "",   ""          } /* empty is end sentinel */
+};
diff --git a/gnu/usr.bin/gas/opcode/vax.h b/gnu/usr.bin/gas/opcode/vax.h
new file mode 100644
index 00000000000..d604e3f9c65
--- /dev/null
+++ b/gnu/usr.bin/gas/opcode/vax.h
@@ -0,0 +1,382 @@
+/* Vax opcde list.
+   Copyright (C) 1989, Free Software Foundation, Inc.
+
+This file is part of GDB and GAS.
+
+GDB and GAS are free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB and GAS are distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB or GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#ifndef vax_opcodeT
+#define vax_opcodeT int
+#endif /* no vax_opcodeT */
+
+struct vot_wot			/* vax opcode table: wot to do with this */
+				/* particular opcode */
+{
+  char *            args;	/* how to compile said opcode */
+  vax_opcodeT       code;	/* op-code (may be > 8 bits!) */
+};
+
+struct vot			/* vax opcode text */
+{
+  char *            name;	/* opcode name: lowercase string  [key]  */
+  struct vot_wot    detail;	/* rest of opcode table          [datum] */
+};
+
+#define vot_how args
+#define vot_code code
+#define vot_detail detail
+#define vot_name name
+
+static const struct vot
+votstrs[] =
+{
+{    "halt",	{"",			0x00	} },
+{    "nop",	{"",			0x01	} },
+{    "rei",	{"",			0x02	} },
+{    "bpt",	{"",			0x03	} },
+{    "ret",	{"",			0x04	} },
+{    "rsb",	{"",			0x05	} },
+{    "ldpctx",	{"",			0x06	} },
+{    "svpctx",	{"",			0x07	} },
+{    "cvtps",	{"rwabrwab",		0x08	} },
+{    "cvtsp",	{"rwabrwab",		0x09	} },
+{    "index",	{"rlrlrlrlrlwl",	0x0a	} },
+{    "crc",	{"abrlrwab",		0x0b	} },
+{    "prober",	{"rbrwab",		0x0c	} },
+{    "probew",	{"rbrwab",	        0x0d	} },
+{    "insque",	{"abab",		0x0e	} },
+{    "remque",	{"abwl",		0x0f	} },
+{    "bsbb",	{"bb",			0x10	} },
+{    "brb",	{"bb",			0x11	} },
+{    "bneq",	{"bb",			0x12	} },
+{    "bnequ",	{"bb",			0x12	} },
+{    "beql",	{"bb",			0x13	} },
+{    "beqlu",	{"bb",			0x13	} },
+{    "bgtr",	{"bb",			0x14	} },
+{    "bleq",	{"bb",			0x15	} },
+{    "jsb",	{"ab",			0x16	} },
+{    "jmp",	{"ab",			0x17	} },
+{    "bgeq",	{"bb",			0x18	} },
+{    "blss",	{"bb",			0x19	} },
+{    "bgtru",	{"bb",			0x1a	} },
+{    "blequ",	{"bb",			0x1b	} },
+{    "bvc",	{"bb",			0x1c	} },
+{    "bvs",	{"bb",			0x1d	} },
+{    "bcc",	{"bb",			0x1e	} },
+{    "bgequ",	{"bb",			0x1e	} },
+{    "blssu",	{"bb",			0x1f	} },
+{    "bcs",	{"bb",			0x1f	} },
+{    "addp4",	{"rwabrwab",		0x20	} },
+{    "addp6",	{"rwabrwabrwab",	0x21	} },
+{    "subp4",	{"rwabrwab",		0x22	} },
+{    "subp6",	{"rwabrwabrwab",	0x23	} },
+{    "cvtpt",	{"rwababrwab",		0x24	} },
+{    "mulp",	{"rwabrwabrwab",	0x25	} },
+{    "cvttp",	{"rwababrwab",		0x26	} },
+{    "divp",	{"rwabrwabrwab",	0x27	} },
+{    "movc3",	{"rwabab",		0x28	} },
+{    "cmpc3",	{"rwabab",		0x29	} },
+{    "scanc",	{"rwababrb",		0x2a	} },
+{    "spanc",	{"rwababrb",		0x2b	} },
+{    "movc5",	{"rwabrbrwab",		0x2c	} },
+{    "cmpc5",	{"rwabrbrwab",		0x2d	} },
+{    "movtc",	{"rwabrbabrwab",	0x2e	} },
+{    "movtuc",	{"rwabrbabrwab",	0x2f	} },
+{    "bsbw",	{"bw",			0x30	} },
+{    "brw",	{"bw",			0x31	} },
+{    "cvtwl",	{"rwwl",		0x32	} },
+{    "cvtwb",	{"rwwb",		0x33	} },
+{    "movp",	{"rwabab",		0x34	} },
+{    "cmpp3",	{"rwabab",		0x35	} },
+{    "cvtpl",	{"rwabwl",		0x36	} },
+{    "cmpp4",	{"rwabrwab",		0x37	} },
+{    "editpc",	{"rwababab",		0x38	} },
+{    "matchc",	{"rwabrwab",		0x39	} },
+{    "locc",	{"rbrwab",		0x3a	} },
+{    "skpc",	{"rbrwab",		0x3b	} },
+{    "movzwl",	{"rwwl",		0x3c	} },
+{    "acbw",	{"rwrwmwbw",		0x3d	} },
+{    "movaw",	{"awwl",		0x3e	} },
+{    "pushaw",	{"aw",			0x3f	} },
+{    "addf2",	{"rfmf",		0x40	} },
+{    "addf3",	{"rfrfwf",		0x41	} },
+{    "subf2",	{"rfmf",		0x42	} },
+{    "subf3",	{"rfrfwf",		0x43	} },
+{    "mulf2",	{"rfmf",		0x44	} },
+{    "mulf3",	{"rfrfwf",		0x45	} },
+{    "divf2",	{"rfmf",		0x46	} },
+{    "divf3",	{"rfrfwf",		0x47	} },
+{    "cvtfb",	{"rfwb",		0x48	} },
+{    "cvtfw",	{"rfww",		0x49	} },
+{    "cvtfl",	{"rfwl",		0x4a	} },
+{    "cvtrfl",	{"rfwl",		0x4b	} },
+{    "cvtbf",	{"rbwf",		0x4c	} },
+{    "cvtwf",	{"rwwf",		0x4d	} },
+{    "cvtlf",	{"rlwf",		0x4e	} },
+{    "acbf",	{"rfrfmfbw",		0x4f	} },
+{    "movf",	{"rfwf",		0x50	} },
+{    "cmpf",	{"rfrf",		0x51	} },
+{    "mnegf",	{"rfwf",		0x52	} },
+{    "tstf",	{"rf",			0x53	} },
+{    "emodf",	{"rfrbrfwlwf",		0x54	} },
+{    "polyf",	{"rfrwab",		0x55	} },
+{    "cvtfd",	{"rfwd",		0x56	} },
+                                        /* opcode 57 is not defined yet */
+{    "adawi",	{"rwmw",		0x58	} },
+                                        /* opcode 59 is not defined yet */
+                                        /* opcode 5a is not defined yet */
+                                        /* opcode 5b is not defined yet */
+{    "insqhi",	{"abaq",		0x5c	} },
+{    "insqti",	{"abaq",		0x5d	} },
+{    "remqhi",	{"aqwl",		0x5e	} },
+{    "remqti",	{"aqwl",		0x5f	} },
+{    "addd2",	{"rdmd",		0x60	} },
+{    "addd3",	{"rdrdwd",		0x61	} },
+{    "subd2",	{"rdmd",		0x62	} },
+{    "subd3",	{"rdrdwd",		0x63	} },
+{    "muld2",	{"rdmd",		0x64	} },
+{    "muld3",	{"rdrdwd",		0x65	} },
+{    "divd2",	{"rdmd",		0x66	} },
+{    "divd3",	{"rdrdwd",		0x67	} },
+{    "cvtdb",	{"rdwb",		0x68	} },
+{    "cvtdw",	{"rdww",		0x69	} },
+{    "cvtdl",	{"rdwl",		0x6a	} },
+{    "cvtrdl",	{"rdwl",		0x6b	} },
+{    "cvtbd",	{"rbwd",		0x6c	} },
+{    "cvtwd",	{"rwwd",		0x6d	} },
+{    "cvtld",	{"rlwd",		0x6e	} },
+{    "acbd",	{"rdrdmdbw",		0x6f	} },
+{    "movd",	{"rdwd",		0x70	} },
+{    "cmpd",	{"rdrd",		0x71	} },
+{    "mnegd",	{"rdwd",		0x72	} },
+{    "tstd",	{"rd",			0x73	} },
+{    "emodd",	{"rdrbrdwlwd",		0x74	} },
+{    "polyd",	{"rdrwab",		0x75	} },
+{    "cvtdf",	{"rdwf",		0x76	} },
+                                        /* opcode 77 is not defined yet */
+{    "ashl",	{"rbrlwl",		0x78	} },
+{    "ashq",	{"rbrqwq",		0x79	} },
+{    "emul",	{"rlrlrlwq",		0x7a	} },
+{    "ediv",	{"rlrqwlwl",		0x7b	} },
+{    "clrd",	{"wd",			0x7c	} },
+{    "clrg",	{"wg",			0x7c	} },
+{    "clrq",	{"wd",			0x7c	} },
+{    "movq",	{"rqwq",		0x7d	} },
+{    "movaq",	{"aqwl",		0x7e	} },
+{    "movad",	{"adwl",		0x7e	} },
+{    "pushaq",	{"aq",			0x7f	} },
+{    "pushad",	{"ad",			0x7f	} },
+{    "addb2",	{"rbmb",		0x80	} },
+{    "addb3",	{"rbrbwb",		0x81	} },
+{    "subb2",	{"rbmb",		0x82	} },
+{    "subb3",	{"rbrbwb",		0x83	} },
+{    "mulb2",	{"rbmb",		0x84	} },
+{    "mulb3",	{"rbrbwb",		0x85	} },
+{    "divb2",	{"rbmb",		0x86	} },
+{    "divb3",	{"rbrbwb",		0x87	} },
+{    "bisb2",	{"rbmb",		0x88	} },
+{    "bisb3",	{"rbrbwb",		0x89	} },
+{    "bicb2",	{"rbmb",		0x8a	} },
+{    "bicb3",	{"rbrbwb",		0x8b	} },
+{    "xorb2",	{"rbmb",		0x8c	} },
+{    "xorb3",	{"rbrbwb",		0x8d	} },
+{    "mnegb",	{"rbwb",		0x8e	} },
+{    "caseb",	{"rbrbrb",		0x8f	} },
+{    "movb",	{"rbwb",		0x90	} },
+{    "cmpb",	{"rbrb",		0x91	} },
+{    "mcomb",	{"rbwb",		0x92	} },
+{    "bitb",	{"rbrb",		0x93	} },
+{    "clrb",	{"wb",			0x94	} },
+{    "tstb",	{"rb",			0x95	} },
+{    "incb",	{"mb",			0x96	} },
+{    "decb",	{"mb",			0x97	} },
+{    "cvtbl",	{"rbwl",		0x98	} },
+{    "cvtbw",	{"rbww",		0x99	} },
+{    "movzbl",	{"rbwl",		0x9a	} },
+{    "movzbw",	{"rbww",		0x9b	} },
+{    "rotl",	{"rbrlwl",		0x9c	} },
+{    "acbb",	{"rbrbmbbw",		0x9d	} },
+{    "movab",	{"abwl",		0x9e	} },
+{    "pushab",	{"ab",			0x9f	} },
+{    "addw2",	{"rwmw",		0xa0	} },
+{    "addw3",	{"rwrwww",		0xa1	} },
+{    "subw2",	{"rwmw",		0xa2	} },
+{    "subw3",	{"rwrwww",		0xa3	} },
+{    "mulw2",	{"rwmw",		0xa4	} },
+{    "mulw3",	{"rwrwww",		0xa5	} },
+{    "divw2",	{"rwmw",		0xa6	} },
+{    "divw3",	{"rwrwww",		0xa7	} },
+{    "bisw2",	{"rwmw",		0xa8	} },
+{    "bisw3",	{"rwrwww",		0xa9	} },
+{    "bicw2",	{"rwmw",		0xaa	} },
+{    "bicw3",	{"rwrwww",		0xab	} },
+{    "xorw2",	{"rwmw",		0xac	} },
+{    "xorw3",	{"rwrwww",		0xad	} },
+{    "mnegw",	{"rwww",		0xae	} },
+{    "casew",	{"rwrwrw",		0xaf	} },
+{    "movw",	{"rwww",		0xb0	} },
+{    "cmpw",	{"rwrw",		0xb1	} },
+{    "mcomw",	{"rwww",		0xb2	} },
+{    "bitw",	{"rwrw",		0xb3	} },
+{    "clrw",	{"ww",			0xb4	} },
+{    "tstw",	{"rw",			0xb5	} },
+{    "incw",	{"mw",			0xb6	} },
+{    "decw",	{"mw",			0xb7	} },
+{    "bispsw",	{"rw",			0xb8	} },
+{    "bicpsw",	{"rw",			0xb9	} },
+{    "popr",	{"rw",			0xba	} },
+{    "pushr",	{"rw",			0xbb	} },
+{    "chmk",	{"rw",			0xbc	} },
+{    "chme",	{"rw",			0xbd	} },
+{    "chms",	{"rw",			0xbe	} },
+{    "chmu",	{"rw",			0xbf	} },
+{    "addl2",	{"rlml",		0xc0	} },
+{    "addl3",	{"rlrlwl",		0xc1	} },
+{    "subl2",	{"rlml",		0xc2	} },
+{    "subl3",	{"rlrlwl",		0xc3	} },
+{    "mull2",	{"rlml",		0xc4	} },
+{    "mull3",	{"rlrlwl",		0xc5	} },
+{    "divl2",	{"rlml",		0xc6	} },
+{    "divl3",	{"rlrlwl",		0xc7	} },
+{    "bisl2",	{"rlml",		0xc8	} },
+{    "bisl3",	{"rlrlwl",		0xc9	} },
+{    "bicl2",	{"rlml",		0xca	} },
+{    "bicl3",	{"rlrlwl",		0xcb	} },
+{    "xorl2",	{"rlml",		0xcc	} },
+{    "xorl3",	{"rlrlwl",		0xcd	} },
+{    "mnegl",	{"rlwl",		0xce	} },
+{    "casel",	{"rlrlrl",		0xcf	} },
+{    "movl",	{"rlwl",		0xd0	} },
+{    "cmpl",	{"rlrl",		0xd1	} },
+{    "mcoml",	{"rlwl",		0xd2	} },
+{    "bitl",	{"rlrl",		0xd3	} },
+{    "clrf",	{"wf",			0xd4	} },
+{    "clrl",	{"wl",			0xd4	} },
+{    "tstl",	{"rl",			0xd5	} },
+{    "incl",	{"ml",			0xd6	} },
+{    "decl",	{"ml",			0xd7	} },
+{    "adwc",	{"rlml",		0xd8	} },
+{    "sbwc",	{"rlml",		0xd9	} },
+{    "mtpr",	{"rlrl",		0xda	} },
+{    "mfpr",	{"rlwl",		0xdb	} },
+{    "movpsl",	{"wl",			0xdc	} },
+{    "pushl",	{"rl",			0xdd	} },
+{    "moval",	{"alwl",		0xde	} },
+{    "movaf",	{"afwl",		0xde	} },
+{    "pushal",	{"al",			0xdf	} },
+{    "pushaf",	{"af",			0xdf	} },
+{    "bbs",	{"rlabbb",		0xe0	} },
+{    "bbc",	{"rlabbb",		0xe1	} },
+{    "bbss",	{"rlabbb",		0xe2	} },
+{    "bbcs",	{"rlabbb",		0xe3	} },
+{    "bbsc",	{"rlabbb",		0xe4	} },
+{    "bbcc",	{"rlabbb",		0xe5	} },
+{    "bbssi",	{"rlabbb",		0xe6	} },
+{    "bbcci",	{"rlabbb",		0xe7	} },
+{    "blbs",	{"rlbb",		0xe8	} },
+{    "blbc",	{"rlbb",		0xe9	} },
+{    "ffs",	{"rlrbvbwl",		0xea	} },
+{    "ffc",	{"rlrbvbwl",		0xeb	} },
+{    "cmpv",	{"rlrbvbrl",		0xec	} },
+{    "cmpzv",	{"rlrbvbrl",		0xed	} },
+{    "extv",	{"rlrbvbwl",		0xee	} },
+{    "extzv",	{"rlrbvbwl",		0xef	} },
+{    "insv",	{"rlrlrbvb",		0xf0	} },
+{    "acbl",	{"rlrlmlbw",		0xf1	} },
+{    "aoblss",	{"rlmlbb",		0xf2	} },
+{    "aobleq",	{"rlmlbb",		0xf3	} },
+{    "sobgeq",	{"mlbb",		0xf4	} },
+{    "sobgtr",	{"mlbb",		0xf5	} },
+{    "cvtlb",	{"rlwb",		0xf6	} },
+{    "cvtlw",	{"rlww",		0xf7	} },
+{    "ashp",	{"rbrwabrbrwab",	0xf8	} },
+{    "cvtlp",	{"rlrwab",		0xf9	} },
+{    "callg",	{"abab",		0xfa	} },
+{    "calls",	{"rlab",		0xfb	} },
+{    "xfc",	{"",			0xfc	} },
+                                        /* undefined opcodes here */
+{    "cvtdh",	{"rdwh",		0x32fd	} },
+{    "cvtgf",	{"rgwh",		0x33fd	} },
+{    "addg2",	{"rgmg",		0x40fd	} },
+{    "addg3",	{"rgrgwg",		0x41fd	} },
+{    "subg2",	{"rgmg",		0x42fd	} },
+{    "subg3",	{"rgrgwg",		0x43fd	} },
+{    "mulg2",	{"rgmg",		0x44fd	} },
+{    "mulg3",	{"rgrgwg",		0x45fd	} },
+{    "divg2",	{"rgmg",		0x46fd	} },
+{    "divg3",	{"rgrgwg",		0x47fd	} },
+{    "cvtgb",	{"rgwb",		0x48fd	} },
+{    "cvtgw",	{"rgww",		0x49fd	} },
+{    "cvtgl",	{"rgwl",		0x4afd	} },
+{    "cvtrgl",	{"rgwl",		0x4bfd	} },
+{    "cvtbg",	{"rbwg",		0x4cfd	} },
+{    "cvtwg",	{"rwwg",		0x4dfd	} },
+{    "cvtlg",	{"rlwg",		0x4efd	} },
+{    "acbg",	{"rgrgmgbw",		0x4ffd	} },
+{    "movg",	{"rgwg",		0x50fd	} },
+{    "cmpg",	{"rgrg",		0x51fd	} },
+{    "mnegg",	{"rgwg",		0x52fd	} },
+{    "tstg",	{"rg",			0x53fd	} },
+{    "emodg",	{"rgrwrgwlwg",		0x54fd	} },
+{    "polyg",	{"rgrwab",		0x55fd	} },
+{    "cvtgh",	{"rgwh",		0x56fd	} },
+                                        /* undefined opcodes here */
+{    "addh2",	{"rhmh",		0x60fd	} },
+{    "addh3",	{"rhrhwh",		0x61fd	} },
+{    "subh2",	{"rhmh",		0x62fd	} },
+{    "subh3",	{"rhrhwh",		0x63fd	} },
+{    "mulh2",	{"rhmh",		0x64fd	} },
+{    "mulh3",	{"rhrhwh",		0x65fd	} },
+{    "divh2",	{"rhmh",		0x66fd	} },
+{    "divh3",	{"rhrhwh",		0x67fd	} },
+{    "cvthb",	{"rhwb",		0x68fd	} },
+{    "cvthw",	{"rhww",		0x69fd	} },
+{    "cvthl",	{"rhwl",		0x6afd	} },
+{    "cvtrhl",	{"rhwl",		0x6bfd	} },
+{    "cvtbh",	{"rbwh",		0x6cfd	} },
+{    "cvtwh",	{"rwwh",		0x6dfd	} },
+{    "cvtlh",	{"rlwh",		0x6efd	} },
+{    "acbh",	{"rhrhmhbw",		0x6ffd	} },
+{    "movh",	{"rhwh",		0x70fd	} },
+{    "cmph",	{"rhrh",		0x71fd	} },
+{    "mnegh",	{"rhwh",		0x72fd	} },
+{    "tsth",	{"rh",			0x73fd	} },
+{    "emodh",	{"rhrwrhwlwh",		0x74fd	} },
+{    "polyh",	{"rhrwab",		0x75fd	} },
+{    "cvthg",	{"rhwg",		0x76fd	} },
+                                        /* undefined opcodes here */
+{    "clrh",	{"wh",			0x7cfd	} },
+{    "clro",	{"wo",			0x7cfd	} },
+{    "movo",	{"rowo",		0x7dfd	} },
+{    "movah",	{"ahwl",		0x7efd	} },
+{    "movao",	{"aowl",		0x7efd	} },
+{    "pushah",	{"ah",			0x7ffd	} },
+{    "pushao",	{"ao",			0x7ffd	} },
+                                        /* undefined opcodes here */
+{    "cvtfh",	{"rfwh",		0x98fd	} },
+{    "cvtfg",	{"rfwg",		0x99fd	} },
+                                        /* undefined opcodes here */
+{    "cvthf",	{"rhwf",		0xf6fd	} },
+{    "cvthd",	{"rhwd",		0xf7fd	} },
+                                        /* undefined opcodes here */
+{    "bugl",	{"rl",			0xfdff	} },
+{    "bugw",	{"rw",			0xfeff	} },
+                                        /* undefined opcodes here */
+
+{      ""       ,   ""          } /* empty is end sentinel */
+
+};				/* votstrs */
+
+/* end: vax.opcode.h */