FSF GCC version 2.7.2

4 files changed, 4271 insertions, 0 deletions

diff --git a/gnu/usr.bin/gcc/config/fx80/fx80.c b/gnu/usr.bin/gcc/config/fx80/fx80.c
new file mode 100644
index 00000000000..a87be41e5e8
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/fx80/fx80.c
@@ -0,0 +1,300 @@
+/* Subroutines for insn-output.c for Alliant FX computers.
+   Copyright (C) 1989,1991 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* Some output-actions in alliant.md need these.  */
+#include <stdio.h>
+#include "config.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+
+/* Index into this array by (register number >> 3) to find the
+   smallest class which contains that register.  */
+enum reg_class regno_reg_class[]
+  = { DATA_REGS, ADDR_REGS, FP_REGS };
+
+static rtx find_addr_reg ();
+
+char *
+output_btst (operands, countop, dataop, insn, signpos)
+     rtx *operands;
+     rtx countop, dataop;
+     rtx insn;
+     int signpos;
+{
+  operands[0] = countop;
+  operands[1] = dataop;
+
+  if (GET_CODE (countop) == CONST_INT)
+    {
+      register int count = INTVAL (countop);
+      /* If COUNT is bigger than size of storage unit in use,
+	 advance to the containing unit of same size.  */
+      if (count > signpos)
+	{
+	  int offset = (count & ~signpos) / 8;
+	  count = count & signpos;
+	  operands[1] = dataop = adj_offsettable_operand (dataop, offset);
+	}
+      if (count == signpos)
+	cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
+      else
+	cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
+
+      /* These three statements used to use next_insns_test_no...
+	 but it appears that this should do the same job.  */
+      if (count == 31
+	  && next_insn_tests_no_inequality (insn))
+	return "tst%.l %1";
+      if (count == 15
+	  && next_insn_tests_no_inequality (insn))
+	return "tst%.w %1";
+      if (count == 7
+	  && next_insn_tests_no_inequality (insn))
+	return "tst%.b %1";
+
+      cc_status.flags = CC_NOT_NEGATIVE;
+    }
+  return "btst %0,%1";
+}
+
+/* Return the best assembler insn template
+   for moving operands[1] into operands[0] as a fullword.  */
+
+static char *
+singlemove_string (operands)
+     rtx *operands;
+{
+  if (operands[1] != const0_rtx)
+    return "mov%.l %1,%0";
+  if (! ADDRESS_REG_P (operands[0]))
+    return "clr%.l %0";
+  return "sub%.l %0,%0";
+}
+
+/* Output assembler code to perform a doubleword move insn
+   with operands OPERANDS.  */
+
+char *
+output_move_double (operands)
+     rtx *operands;
+{
+  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
+  rtx latehalf[2];
+  rtx addreg0 = 0, addreg1 = 0;
+
+  /* First classify both operands.  */
+
+  if (REG_P (operands[0]))
+    optype0 = REGOP;
+  else if (offsettable_memref_p (operands[0]))
+    optype0 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    optype0 = POPOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    optype0 = PUSHOP;
+  else if (GET_CODE (operands[0]) == MEM)
+    optype0 = MEMOP;
+  else
+    optype0 = RNDOP;
+
+  if (REG_P (operands[1]))
+    optype1 = REGOP;
+  else if (CONSTANT_P (operands[1]))
+    optype1 = CNSTOP;
+  else if (offsettable_memref_p (operands[1]))
+    optype1 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
+    optype1 = POPOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+    optype1 = PUSHOP;
+  else if (GET_CODE (operands[1]) == MEM)
+    optype1 = MEMOP;
+  else
+    optype1 = RNDOP;
+
+  /* Check for the cases that the operand constraints are not
+     supposed to allow to happen.  Abort if we get one,
+     because generating code for these cases is painful.  */
+
+  if (optype0 == RNDOP || optype1 == RNDOP)
+    abort ();
+
+  /* If one operand is decrementing and one is incrementing
+     decrement the former register explicitly
+     and change that operand into ordinary indexing.  */
+
+  if (optype0 == PUSHOP && optype1 == POPOP)
+    {
+      operands[0] = XEXP (XEXP (operands[0], 0), 0);
+      output_asm_insn ("subq%.l %#8,%0", operands);
+      operands[0] = gen_rtx (MEM, DImode, operands[0]);
+      optype0 = OFFSOP;
+    }
+  if (optype0 == POPOP && optype1 == PUSHOP)
+    {
+      operands[1] = XEXP (XEXP (operands[1], 0), 0);
+      output_asm_insn ("subq%.l %#8,%1", operands);
+      operands[1] = gen_rtx (MEM, DImode, operands[1]);
+      optype1 = OFFSOP;
+    }
+
+  /* If an operand is an unoffsettable memory ref, find a register
+     we can increment temporarily to make it refer to the second word.  */
+
+  if (optype0 == MEMOP)
+    addreg0 = find_addr_reg (XEXP (operands[0], 0));
+
+  if (optype1 == MEMOP)
+    addreg1 = find_addr_reg (XEXP (operands[1], 0));
+
+  /* Ok, we can do one word at a time.
+     Normally we do the low-numbered word first,
+     but if either operand is autodecrementing then we
+     do the high-numbered word first.
+
+     In either case, set up in LATEHALF the operands to use
+     for the high-numbered word and in some cases alter the
+     operands in OPERANDS to be suitable for the low-numbered word.  */
+
+  if (optype0 == REGOP)
+    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+  else if (optype0 == OFFSOP)
+    latehalf[0] = adj_offsettable_operand (operands[0], 4);
+  else
+    latehalf[0] = operands[0];
+
+  if (optype1 == REGOP)
+    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  else if (optype1 == OFFSOP)
+    latehalf[1] = adj_offsettable_operand (operands[1], 4);
+  else if (optype1 == CNSTOP)
+    {
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	split_double (operands[1], &operands[1], &latehalf[1]);
+      else if (CONSTANT_P (operands[1]))
+	{
+	  latehalf[1] = operands[1];
+	  operands[1] = const0_rtx;
+	}
+    }
+  else
+    latehalf[1] = operands[1];
+
+  /* If insn is effectively movd N(sp),-(sp) then we will do the
+     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
+     for the low word as well, to compensate for the first decrement of sp.  */
+  if (optype0 == PUSHOP
+      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
+      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
+    operands[1] = latehalf[1];
+
+  /* If one or both operands autodecrementing,
+     do the two words, high-numbered first.  */
+
+  /* Likewise,  the first move would clobber the source of the second one,
+     do them in the other order.  This happens only for registers;
+     such overlap can't happen in memory unless the user explicitly
+     sets it up, and that is an undefined circumstance.  */
+
+  if (optype0 == PUSHOP || optype1 == PUSHOP
+      || (optype0 == REGOP && optype1 == REGOP
+	  && REGNO (operands[0]) == REGNO (latehalf[1])))
+    {
+      /* Make any unoffsettable addresses point at high-numbered word.  */
+      if (addreg0)
+	output_asm_insn ("addql %#4,%0", &addreg0);
+      if (addreg1)
+	output_asm_insn ("addql %#4,%0", &addreg1);
+
+      /* Do that word.  */
+      output_asm_insn (singlemove_string (latehalf), latehalf);
+
+      /* Undo the adds we just did.  */
+      if (addreg0)
+	output_asm_insn ("subql %#4,%0", &addreg0);
+      if (addreg1)
+	output_asm_insn ("subql %#4,%0", &addreg1);
+
+      /* Do low-numbered word.  */
+      return singlemove_string (operands);
+    }
+
+  /* Normal case: do the two words, low-numbered first.  */
+
+  output_asm_insn (singlemove_string (operands), operands);
+
+  /* Make any unoffsettable addresses point at high-numbered word.  */
+  if (addreg0)
+    output_asm_insn ("addql %#4,%0", &addreg0);
+  if (addreg1)
+    output_asm_insn ("addql %#4,%0", &addreg1);
+
+  /* Do that word.  */
+  output_asm_insn (singlemove_string (latehalf), latehalf);
+
+  /* Undo the adds we just did.  */
+  if (addreg0)
+    output_asm_insn ("subql %#4,%0", &addreg0);
+  if (addreg1)
+    output_asm_insn ("subql %#4,%0", &addreg1);
+
+  return "";
+}
+
+/* Return a REG that occurs in ADDR with coefficient 1.
+   ADDR can be effectively incremented by incrementing REG.  */
+
+static rtx
+find_addr_reg (addr)
+     rtx addr;
+{
+  while (GET_CODE (addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (addr, 0)) == REG)
+	addr = XEXP (addr, 0);
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 0)))
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 1)))
+	addr = XEXP (addr, 0);
+      else
+	abort ();
+    }
+  if (GET_CODE (addr) == REG)
+    return addr;
+  abort ();
+}
+
+int
+standard_SunFPA_constant_p (x)
+     rtx x;
+{
+  return( 0 );
+}
+
diff --git a/gnu/usr.bin/gcc/config/fx80/fx80.h b/gnu/usr.bin/gcc/config/fx80/fx80.h
new file mode 100644
index 00000000000..82797fbb402
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/fx80/fx80.h
@@ -0,0 +1,1447 @@
+/* Definitions of target machine for GNU compiler.  Alliant FX version.
+   Copyright (C) 1989, 1993, 1994, 1995 Free Software Foundation, Inc.
+   Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
+   and Joe Weening (weening@gang-of-four.stanford.edu).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* This file is based on m68k.h, simplified by removing support for
+   the Sun FPA and other things not applicable to the Alliant.  Some
+   remnants of these features remain.  */
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)"
+
+/* Print subsidiary information on the compiler version in use.  */
+
+#define TARGET_VERSION fprintf (stderr, " (Alliant)");
+
+/* Run-time compilation parameters selecting different hardware
+   subsets.  The Alliant IP is an mc68020.  (Older mc68010-based IPs
+   are no longer supported.)  The Alliant CE is 68020-compatible, and
+   also has floating point, vector and concurrency instructions.
+
+   Although the IP doesn't have floating point, it emulates it in the
+   operating system.  Using this generally is faster than running code
+   compiled with -msoft-float, because the soft-float code still uses
+   (simulated) FP registers and ends up emulating several fmove{s,d}
+   instructions per call.  So I don't recommend using soft-float for
+   any Alliant code.  -- JSW
+*/
+
+extern int target_flags;
+
+/* Macros used in the machine description to test the flags.  */
+
+/* Compile for a 68020 (not a 68000 or 68010).  */
+#define TARGET_68020 (target_flags & 1)
+/* Compile CE insns for floating point (not library calls).  */
+#define TARGET_CE (target_flags & 2)
+/* Compile using 68020 bitfield insns.  */
+#define TARGET_BITFIELD (target_flags & 4)
+/* Compile with 16-bit `int'.  */
+#define TARGET_SHORT (target_flags & 040)
+
+/* Default 3 means compile 68020 and CE instructions.  We don't use
+   bitfield instructions because there appears to be a bug in the
+   implementation of bfins on the CE.  */
+
+#define TARGET_DEFAULT 3
+
+/* Define __HAVE_CE__ in preprocessor according to the -m flags.
+   This will control the use of inline FP insns in certain macros.
+   Also inform the program which CPU this is for.  */
+
+#if TARGET_DEFAULT & 02
+
+/* -mce is the default */
+#define CPP_SPEC \
+"%{!msoft-float:-D__HAVE_CE__ }\
+%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
+
+#else
+
+/* -msoft-float is the default */
+#define CPP_SPEC \
+"%{mce:-D__HAVE_CE__ }\
+%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
+
+#endif
+
+/* Link with libg.a when debugging, for dbx's sake.  */
+
+#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
+
+/* Make the linker remove temporary labels, since the Alliant assembler
+   doesn't.  */
+
+#define LINK_SPEC "-X"
+
+/* Every structure or union's size must be a multiple of 2 bytes.  */
+
+#define STRUCTURE_SIZE_BOUNDARY 16
+
+/* This is BSD, so it wants DBX format.  */
+
+#define DBX_DEBUGGING_INFO
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES  \
+  { { "68020", 5},				\
+    { "c68020", 5},				\
+    { "bitfield", 4},				\
+    { "68000", -7},				\
+    { "c68000", -7},				\
+    { "soft-float", -2},			\
+    { "nobitfield", -4},			\
+    { "short", 040},				\
+    { "noshort", -040},				\
+    { "", TARGET_DEFAULT}}
+
+/* target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is true for 68020 insns such as bfins and bfexts.
+   We make it true always by avoiding using the single-bit insns
+   except in special cases with constant bit numbers.  */
+#define BITS_BIG_ENDIAN 1
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+/* That is true on the 68000.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+/* For 68000 we can decide arbitrarily
+   since there are no machine instructions for them.  */
+#define WORDS_BIG_ENDIAN 0
+
+/* number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 16
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 16
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 16
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 16
+
+/* Set this non-zero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* Define number of bits in most basic integer type.
+   (If undefined, default is BITS_PER_WORD).  */
+
+#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
+
+/* Define these to avoid dependence on meaning of `int'.
+   Note that WCHAR_TYPE_SIZE is used in cexp.y,
+   where TARGET_SHORT is not available.  */
+
+#define WCHAR_TYPE "long int"
+#define WCHAR_TYPE_SIZE 32
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+   For the Alliant, we give the data registers numbers 0-7,
+   the address registers numbers 010-017,
+   and the floating point registers numbers 020-027.  */
+#define FIRST_PSEUDO_REGISTER 24
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+   On the Alliant, these are a0 (argument pointer),
+   a6 (frame pointer) and a7 (stack pointer).  */
+#define FIXED_REGISTERS  \
+ {0, 0, 0, 0, 0, 0, 0, 0, \
+  1, 0, 0, 0, 0, 0, 1, 1, \
+  0, 0, 0, 0, 0, 0, 0, 0  }
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.
+   The Alliant calling sequence allows a function to use any register,
+   so we include them all here.  */
+
+#define CALL_USED_REGISTERS \
+ {1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1  }
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On the Alliant, ordinary registers hold 32 bits worth;
+   for the FP registers, a single register is always enough for
+   any floating-point value.  */
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE)	\
+   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   On the Alliant, the cpu registers can hold any mode but the FP registers
+   can hold only floating point.  */
+#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
+  ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
+   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2)			\
+   (((MODE1) == SFmode || (MODE1) == DFmode		\
+     || (MODE1) == SCmode || (MODE1) == DCmode)		\
+       == ((MODE2) == SFmode || (MODE2) == DFmode	\
+	   || (MODE2) == SCmode || (MODE2) == DCmode))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* m68000 pc isn't overloaded on a register.  */
+/* #define PC_REGNUM  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 14
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+/* Set for now on Alliant until we find a way to make this work with
+   their calling sequence.  */
+#define FRAME_POINTER_REQUIRED 1
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM  8 
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM 10
+
+/* Register in which address to store a structure value
+   is passed to a function.  */
+#define STRUCT_VALUE_REGNUM 9
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+/* The Alliant has three kinds of registers, so eight classes would be
+   a complete set.  One of them is not needed.  */
+
+enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS,
+  ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+ { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS",  \
+   "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS \
+{					\
+ 0,		/* NO_REGS */		\
+ 0x00ff0000,	/* FP_REGS */		\
+ 0x000000ff,	/* DATA_REGS */		\
+ 0x00ff00ff,	/* DATA_OR_FP_REGS */	\
+ 0x0000ff00,	/* ADDR_REGS */		\
+ 0x0000ffff,	/* GENERAL_REGS */	\
+ 0x00ffffff	/* ALL_REGS */		\
+}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+extern enum reg_class regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
+
+/* The class value for index registers, and the one for base regs.  */
+
+#define INDEX_REG_CLASS GENERAL_REGS
+#define BASE_REG_CLASS ADDR_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) \
+  ((C) == 'a' ? ADDR_REGS :			\
+   ((C) == 'd' ? DATA_REGS :			\
+    ((C) == 'f' ? FP_REGS :			\
+     NO_REGS)))
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+
+   For the 68000, `I' is used for the range 1 to 8
+   allowed as immediate shift counts and in addq.
+   `J' is used for the range of signed numbers that fit in 16 bits.
+   `K' is for numbers that moveq can't handle.
+   `L' is for range -8 to -1, range of values that can be added with subq.  */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
+  ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 :    \
+   (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF :	\
+   (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 :	\
+   (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.
+   On the 68000 series, use a data reg if possible when the
+   value is a constant in the range where moveq could be used
+   and we ensure that QImodes are reloaded into data regs.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)  \
+  ((GET_CODE (X) == CONST_INT			\
+    && (unsigned) (INTVAL (X) + 0x80) < 0x100	\
+    && (CLASS) != ADDR_REGS)			\
+   ? DATA_REGS					\
+   : GET_MODE (X) == QImode			\
+   ? DATA_REGS					\
+   : (CLASS))
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+/* On the 68000, this is the size of MODE in words,
+   except in the FP regs, where a single reg is always enough.  */
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+ ((CLASS) == FP_REGS ? 1 \
+  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Moves between fp regs and other regs are two insns.  */
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
+  ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS)	\
+    || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS))	\
+   ? 4 : 2)
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* The Alliant uses -fcaller-saves by default.  */
+#define DEFAULT_CALLER_SAVES
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+#define STARTING_FRAME_OFFSET -4
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.
+   On the 68000, sp@- in a byte insn really pushes a word.  */
+#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL) 0
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack. 
+
+   On the Alliant we define this as SIZE and make the calling sequence
+   (in alliant.md) pop the args.  This wouldn't be necessary if we
+   could add to the pending stack adjustment the size of the argument
+   descriptors that are pushed after the arguments.  */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+/* On the Alliant the return value is in FP0 if real, else D0.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)  \
+  (TREE_CODE (VALTYPE) == REAL_TYPE \
+   ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
+   : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+/* On the Alliant the return value is in FP0 if real, else D0.  The
+   Alliant library functions for floating-point emulation return their
+   values both in FP0 and in D0/D1.  But since not all libgcc functions
+   return the results of these directly, we cannot assume that D0/D1
+   contain the values we expect on return from a libgcc function.  */
+
+#define LIBCALL_VALUE(MODE)  \
+  (((MODE) == DFmode || (MODE) == SFmode) \
+   ? gen_rtx (REG, MODE, 16) \
+   : gen_rtx (REG, MODE, 0))
+
+/* 1 if N is a possible register number for a function value.
+   On the Alliant, D0 and FP0 are the only registers thus used.
+   (No need to mention D1 when used as a pair with D0.)  */
+
+#define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0)
+
+/* Define this if PCC uses the nonreentrant convention for returning
+   structure and union values.  */
+
+#define PCC_STATIC_STRUCT_RETURN
+
+/* 1 if N is a possible register number for function argument passing.
+   On the Alliant, no registers are used in this way.  */
+
+#define FUNCTION_ARG_REGNO_P(N) 0
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the Alliant, this is a single integer, which is a number of bytes
+   of arguments scanned so far.  */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On the Alliant, the offset starts at 0.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME)	\
+ ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) += ((MODE) != BLKmode			\
+	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
+	    : (int_size_in_bytes (TYPE) + 3) & ~3))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+/* On the Alliant all args are pushed.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.
+   The Alliant uses caller-saves, so this macro is very simple.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE)     \
+{ int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4;	\
+  if (frame_pointer_needed)					\
+    {								\
+      if (fsize < 0x8000)					\
+	fprintf(FILE,"\tlinkw a6,#%d\n", -fsize);		\
+      else if (TARGET_68020)					\
+	fprintf(FILE,"\tlinkl a6,#%d\n", -fsize);		\
+      else							\
+	fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize);  \
+      fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }}
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)  \
+  fprintf (FILE, "\tjbsr __mcount_\n")
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer!
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE) \
+{ if (frame_pointer_needed)					\
+    fprintf (FILE, "\tunlk a6\n");				\
+  fprintf (FILE, "\trts\n"); }
+
+/* Store in the variable DEPTH the initial difference between the
+   frame pointer reg contents and the stack pointer reg contents,
+   as of the start of the function body.  This depends on the layout
+   of the fixed parts of the stack frame and on how registers are saved.  */
+
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
+{								\
+  int regno;							\
+  int offset = -4;						\
+  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
+      offset += 12;						\
+  for (regno = 0; regno < 16; regno++)				\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
+      offset += 4;						\
+  (DEPTH) = offset - ((get_frame_size () + 3) & -4);		\
+}
+
+/* Addressing modes, and classification of registers for them.  */
+
+#define HAVE_POST_INCREMENT
+/* #define HAVE_POST_DECREMENT */
+
+#define HAVE_PRE_DECREMENT
+/* #define HAVE_PRE_INCREMENT */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
+#define REGNO_OK_FOR_DATA_P(REGNO) \
+((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
+#define REGNO_OK_FOR_FP_P(REGNO) \
+(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
+
+/* Now macros that check whether X is a register and also,
+   strictly, whether it is in a specified class.
+
+   These macros are specific to the 68000, and may be used only
+   in code for printing assembler insns and in conditions for
+   define_optimization.  */
+
+/* 1 if X is a data register.  */
+
+#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
+
+/* 1 if X is an fp register.  */
+
+#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
+
+/* 1 if X is an address register  */
+
+#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)   \
+  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
+   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
+   || GET_CODE (X) == HIGH)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+/* Alliant FP instructions don't take immediate operands, so this
+   forces them into memory.  */
+#define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
+
+#define INDIRECTABLE_1_ADDRESS_P(X)  \
+  (CONSTANT_ADDRESS_P (X)						\
+   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
+   || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)		\
+       && REG_P (XEXP (X, 0))						\
+       && REG_OK_FOR_BASE_P (XEXP (X, 0)))				\
+   || (GET_CODE (X) == PLUS						\
+       && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0))	\
+       && GET_CODE (XEXP (X, 1)) == CONST_INT				\
+       && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
+
+#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
+{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
+
+#define GO_IF_INDEXABLE_BASE(X, ADDR)	\
+{ if (GET_CODE (X) == LABEL_REF) goto ADDR;				\
+  if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
+
+#define GO_IF_INDEXING(X, ADDR)	\
+{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0)))		\
+    { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); }			\
+  if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1)))		\
+    { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
+
+#define GO_IF_INDEXED_ADDRESS(X, ADDR)	 \
+{ GO_IF_INDEXING (X, ADDR);						\
+  if (GET_CODE (X) == PLUS)						\
+    { if (GET_CODE (XEXP (X, 1)) == CONST_INT				\
+	  && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)		\
+	{ rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); }	\
+      if (GET_CODE (XEXP (X, 0)) == CONST_INT				\
+	  && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)		\
+	{ rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
+
+#define LEGITIMATE_INDEX_REG_P(X)   \
+  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
+   || (GET_CODE (X) == SIGN_EXTEND			\
+       && GET_CODE (XEXP (X, 0)) == REG			\
+       && GET_MODE (XEXP (X, 0)) == HImode		\
+       && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
+
+#define LEGITIMATE_INDEX_P(X)   \
+   (LEGITIMATE_INDEX_REG_P (X)				\
+    || (TARGET_68020 && GET_CODE (X) == MULT		\
+	&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0))		\
+	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
+	&& (INTVAL (XEXP (X, 1)) == 2			\
+	    || INTVAL (XEXP (X, 1)) == 4		\
+	    || INTVAL (XEXP (X, 1)) == 8)))
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
+{ GO_IF_NONINDEXED_ADDRESS (X, ADDR);			\
+  GO_IF_INDEXED_ADDRESS (X, ADDR); }
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   For the 68000, we handle X+REG by loading X into a register R and
+   using R+REG.  R will go in an address reg and indexing will be used.
+   However, if REG is a broken-out memory address or multiplication,
+   nothing needs to be done because REG can certainly go in an address reg.  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   \
+{ register int ch = (X) != (OLDX);					\
+  if (GET_CODE (X) == PLUS)						\
+    { if (GET_CODE (XEXP (X, 0)) == MULT)				\
+	ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0);		\
+      if (GET_CODE (XEXP (X, 1)) == MULT)				\
+	ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0);		\
+      if (ch && GET_CODE (XEXP (X, 1)) == REG				\
+	  && GET_CODE (XEXP (X, 0)) == REG)				\
+	goto WIN;							\
+      if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); }		\
+      if (GET_CODE (XEXP (X, 0)) == REG					\
+	       || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND		\
+		   && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG		\
+		   && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode))	\
+	{ register rtx temp = gen_reg_rtx (Pmode);			\
+	  register rtx val = force_operand (XEXP (X, 1), 0);		\
+	  emit_move_insn (temp, val);					\
+	  XEXP (X, 1) = temp;						\
+	  goto WIN; }							\
+      else if (GET_CODE (XEXP (X, 1)) == REG				\
+	       || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND		\
+		   && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG		\
+		   && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode))	\
+	{ register rtx temp = gen_reg_rtx (Pmode);			\
+	  register rtx val = force_operand (XEXP (X, 0), 0);		\
+	  emit_move_insn (temp, val);					\
+	  XEXP (X, 0) = temp;						\
+	  goto WIN; }}}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+   On the 68000, only predecrement and postincrement address depend thus
+   (the amount of decrement or increment being the length of the operand).  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
+ if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE HImode
+
+/* Define this if the tablejump instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+#define CASE_VECTOR_PC_RELATIVE
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 1
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Define this if zero-extension is slow (more than one real instruction).  */
+#define SLOW_ZERO_EXTEND
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+/* Define this to be nonzero if shift instructions ignore all but the low-order
+   few bits. */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+
+#define STORE_FLAG_VALUE -1
+
+/* When a prototype says `char' or `short', really pass an `int'.  */
+#define PROMOTE_PROTOTYPES
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* A function address in a call instruction
+   is a byte address (for indexing purposes)
+   so give the MEM rtx a byte's mode.  */
+#define FUNCTION_MODE QImode
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:						\
+    /* Constant zero is super cheap due to clr instruction.  */	\
+    if (RTX == const0_rtx) return 0;				\
+    if ((unsigned) INTVAL (RTX) < 077) return 1;		\
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+    return 3;							\
+  case CONST_DOUBLE:						\
+    return 5;
+
+/* Check a `double' value for validity for a particular machine mode.
+   This is defined to avoid crashes outputting certain constants.  */
+
+#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW)				\
+  if (OVERFLOW)								\
+    (D) = 3.4028234663852890e+38;					\
+  else if ((MODE) == SFmode)						\
+    { 									\
+      if ((d) > 3.4028234663852890e+38)					\
+	(OVERFLOW) = 1, (D) = 3.4028234663852890e+38;			\
+      else if ((D) < -3.4028234663852890e+38)				\
+	(OVERFLOW) = 1, (D) = -3.4028234663852890e+38;			\
+      else if (((D) > 0) && ((D) < 1.1754943508222873e-38))		\
+	(OVERFLOW) = 1, (D) = 0.0;					\
+      else if (((d) < 0) && ((d) > -1.1754943508222873e-38))		\
+	(OVERFLOW) = 1, (D) = 0.0;					\
+    }
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  */
+
+/* On the Alliant, floating-point instructions do not modify the
+   ordinary CC register.  Only fcmp and ftest instructions modify the
+   floating-point CC register.  We should actually keep track of what
+   both kinds of CC registers contain, but for now we only consider
+   the most recent instruction that has set either register.  */
+
+/* Set if the cc value came from a floating point test, so a floating
+   point conditional branch must be output.  */
+#define CC_IN_FP 04000
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+/* On the 68000, all the insns to store in an address register
+   fail to set the cc's.  However, in some cases these instructions
+   can make it possibly invalid to use the saved cc's.  In those
+   cases we clear out some or all of the saved cc's so they won't be used.  */
+
+#define NOTICE_UPDATE_CC(EXP, INSN) \
+{								\
+  if (GET_CODE (EXP) == SET)					\
+    { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP)))	    \
+	{ if (cc_status.value1					\
+	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
+	    cc_status.value1 = 0;				\
+	  if (cc_status.value2					\
+	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
+	    cc_status.value2 = 0; }				\
+      else if (GET_CODE (SET_SRC (EXP)) == MOD			\
+	       || GET_CODE (SET_SRC (EXP)) == UMOD		\
+	       || (GET_CODE (SET_SRC (EXP)) == TRUNCATE		\
+		   && (GET_CODE (XEXP (SET_SRC (EXP))) == MOD	\
+		       || GET_CODE (XEXP (SET_SRC (EXP))) == UMOD)))	\
+	/* The swap insn produces cc's that don't correspond to the 	\
+	   result.  */						\
+        CC_STATUS_INIT;						\
+      else if (SET_DEST (EXP) != cc0_rtx				\
+	       && (FP_REG_P (SET_SRC (EXP))			\
+		   || GET_CODE (SET_SRC (EXP)) == FIX		\
+		   || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \
+		   || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \
+	{ CC_STATUS_INIT; }					\
+      /* A pair of move insns doesn't produce a useful overall cc.  */ \
+      else if (!FP_REG_P (SET_DEST (EXP))			\
+	       && !FP_REG_P (SET_SRC (EXP))			\
+	       && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4	\
+	       && (GET_CODE (SET_SRC (EXP)) == REG		\
+		   || GET_CODE (SET_SRC (EXP)) == MEM		\
+		   || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\
+	{ CC_STATUS_INIT; }					\
+      else if (GET_CODE (SET_SRC (EXP)) == CALL)		\
+	{ CC_STATUS_INIT; }					\
+      else if (XEXP (EXP, 0) != pc_rtx)				\
+	{ cc_status.flags = 0;					\
+	  cc_status.value1 = XEXP (EXP, 0);			\
+	  cc_status.value2 = XEXP (EXP, 1); } }			\
+  else if (GET_CODE (EXP) == PARALLEL				\
+	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET)		\
+    {								\
+      if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0)))	\
+	CC_STATUS_INIT;						\
+      else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx)		\
+	{ cc_status.flags = 0;					\
+	  cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0);	\
+	  cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } }	\
+  else CC_STATUS_INIT;						\
+  if (cc_status.value2 != 0					\
+      && ADDRESS_REG_P (cc_status.value2)			\
+      && GET_MODE (cc_status.value2) == QImode)			\
+    CC_STATUS_INIT;						\
+  if (cc_status.value2 != 0)					\
+    switch (GET_CODE (cc_status.value2))			\
+      { case PLUS: case MINUS: case MULT:			\
+	case DIV: case UDIV: case MOD: case UMOD: case NEG:	\
+	case ASHIFT:  case ASHIFTRT: case LSHIFTRT:		\
+	case ROTATE: case ROTATERT:				\
+	  if (GET_MODE (cc_status.value2) != VOIDmode)		\
+	    cc_status.flags |= CC_NO_OVERFLOW;			\
+	  break;						\
+	case ZERO_EXTEND:					\
+	  /* (SET r1 (ZERO_EXTEND r2)) on this machine
+	     ends with a move insn moving r2 in r2's mode.
+	     Thus, the cc's are set for r2.
+	     This can set N bit spuriously. */			\
+	  cc_status.flags |= CC_NOT_NEGATIVE; }			\
+  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
+      && cc_status.value2					\
+      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
+    cc_status.value2 = 0;					\
+  if ((cc_status.value1 && FP_REG_P (cc_status.value1))		\
+       || (cc_status.value2 && FP_REG_P (cc_status.value2)))	\
+    cc_status.flags = CC_IN_FP; }
+
+#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
+{ if (cc_prev_status.flags & CC_IN_FP)			\
+    return FLOAT;						\
+  if (cc_prev_status.flags & CC_NO_OVERFLOW)			\
+    return NO_OV;						\
+  return NORMAL; }
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.  */
+
+#define ASM_FILE_START(FILE)	\
+  fprintf (FILE, "#NO_APP\n");
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON "#APP\n"
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF "#NO_APP\n"
+
+/* Output before read-only data.  */
+
+#define TEXT_SECTION_ASM_OP ".text"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP ".data"
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",	\
+ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
+
+/* How to renumber registers for dbx and gdb.
+   On the Sun-3, the floating point registers have numbers
+   18 to 25, not 16 to 23 as they do in the compiler.  */
+/* (On the Alliant, dbx isn't working yet at all.  */
+
+#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
+  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* This is how to output a reference to a user-level label named NAME.
+   `assemble_name' uses this.  */
+
+#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
+  fprintf (FILE, "_%s", NAME)
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
+do { union { double d; long v[2];} tem;			\
+     tem.d = (VALUE);					\
+     fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]);	\
+   } while (0)
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
+do { union { float f; long l;} tem;			\
+     tem.f = (VALUE);					\
+     fprintf (FILE, "\t.long 0x%x\n", tem.l);	\
+   } while (0)
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( fprintf (FILE, "\t.long "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.word "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.byte "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_ASCII(FILE,PTR,SIZE)               \
+do { int i; unsigned char *pp = (unsigned char *) (PTR);	\
+  fprintf((FILE), "\t.byte %d", (unsigned int)*pp++);		\
+  for (i = 1; i < (SIZE); ++i, ++pp) {				\
+    if ((i % 8) == 0)						\
+      fprintf((FILE), "\n\t.byte %d", (unsigned int) *pp);	\
+    else							\
+      fprintf((FILE), ",%d", (unsigned int) *pp); }		\
+  fprintf ((FILE), "\n");       } while (0)
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+/* This is how to output an insn to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute.
+   (The 68000 does not use such vectors,
+   but we must define this macro anyway.)  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.long L%d\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)  \
+  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) == 1)			\
+    fprintf (FILE, "\t.even\n");	\
+  else if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %dn", (LOG));	
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t. = . + %u\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs ("\t.comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%u\n", (ROUNDED)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
+( fputs ("\t.lcomm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%u\n", (ROUNDED)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.
+
+   On the Alliant, we use several CODE characters:
+   '.' for dot needed in Motorola-style opcode names.
+   '-' for an operand pushing on the stack:
+       sp@-, -(sp) or -(%sp) depending on the style of syntax.
+   '+' for an operand pushing on the stack:
+       sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
+   '@' for a reference to the top word on the stack:
+       sp@, (sp) or (%sp) depending on the style of syntax.
+   '#' for an immediate operand prefix (# in MIT and Motorola syntax
+       but & in SGS syntax).
+   '!' for the cc register (used in an `and to cc' insn).
+
+   'b' for byte insn (no effect, on the Sun; this is for the ISI).
+   'd' to force memory addressing to be absolute, not relative.
+   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
+   'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
+       or print pair of registers as rx:ry.  */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
+  ((CODE) == '.' || (CODE) == '#' || (CODE) == '-'			\
+   || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
+
+#define PRINT_OPERAND(FILE, X, CODE)  \
+{ int i;								\
+  if (CODE == '.') ;							\
+  else if (CODE == '#') fprintf (FILE, "#");				\
+  else if (CODE == '-') fprintf (FILE, "sp@-");				\
+  else if (CODE == '+') fprintf (FILE, "sp@+");				\
+  else if (CODE == '@') fprintf (FILE, "sp@");				\
+  else if (CODE == '!') fprintf (FILE, "cc");				\
+  else if ((X)  == 0  ) ;						\
+  else if (GET_CODE (X) == REG)						\
+    { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode)	\
+        fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
+      else								\
+        fprintf (FILE, "%s", reg_names[REGNO (X)]);			\
+    }									\
+  else if (GET_CODE (X) == MEM)						\
+    {									\
+      output_address (XEXP (X, 0));					\
+      if (CODE == 'd' && ! TARGET_68020					\
+	  && CONSTANT_ADDRESS_P (XEXP (X, 0))				\
+	  && !(GET_CODE (XEXP (X, 0)) == CONST_INT			\
+	       && INTVAL (XEXP (X, 0)) < 0x8000				\
+	       && INTVAL (XEXP (X, 0)) >= -0x8000))			\
+	fprintf (FILE, ":l");						\
+    }									\
+  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
+    { union { double d; int i[2]; } u;					\
+      union { float f; int i; } u1;					\
+      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
+      u1.f = u.d;							\
+      if (CODE == 'f')							\
+        fprintf (FILE, "#0r%.9g", u1.f);				\
+      else								\
+        fprintf (FILE, "#0x%x", u1.i); }				\
+  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)	\
+    { union { double d; int i[2]; } u;					\
+      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
+      fprintf (FILE, "#0r%.20g", u.d); }				\
+  else { putc ('#', FILE); output_addr_const (FILE, X); }}
+
+/* Note that this contains a kludge that knows that the only reason
+   we have an address (plus (label_ref...) (reg...))
+   is in the insn before a tablejump, and we know that m68k.md
+   generates a label LInnn: on such an insn.  */
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
+{ register rtx reg1, reg2, breg, ireg;					\
+  register rtx addr = ADDR;						\
+  static char *sz = ".BW.L...D";					\
+  rtx offset;								\
+  switch (GET_CODE (addr))						\
+    {									\
+    case REG:								\
+      fprintf (FILE, "%s@", reg_names[REGNO (addr)]);			\
+      break;								\
+    case PRE_DEC:							\
+      fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);	\
+      break;								\
+    case POST_INC:							\
+      fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);	\
+      break;								\
+    case PLUS:								\
+      reg1 = 0;	reg2 = 0;						\
+      ireg = 0;	breg = 0;						\
+      offset = 0;							\
+      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
+	{								\
+	  offset = XEXP (addr, 0);					\
+	  addr = XEXP (addr, 1);					\
+	}								\
+      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
+	{								\
+	  offset = XEXP (addr, 1);					\
+	  addr = XEXP (addr, 0);					\
+	}								\
+      if (GET_CODE (addr) != PLUS) ;					\
+      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
+	{								\
+	  reg1 = XEXP (addr, 0);					\
+	  addr = XEXP (addr, 1);					\
+	}								\
+      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
+	{								\
+	  reg1 = XEXP (addr, 1);					\
+	  addr = XEXP (addr, 0);					\
+	}								\
+      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
+	{								\
+	  reg1 = XEXP (addr, 0);					\
+	  addr = XEXP (addr, 1);					\
+	}								\
+      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
+	{								\
+	  reg1 = XEXP (addr, 1);					\
+	  addr = XEXP (addr, 0);					\
+	}								\
+      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
+	{								\
+	  reg1 = XEXP (addr, 0);					\
+	  addr = XEXP (addr, 1);					\
+	}								\
+      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
+	{								\
+	  reg1 = XEXP (addr, 1);					\
+	  addr = XEXP (addr, 0);					\
+	}								\
+      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
+	  || GET_CODE (addr) == SIGN_EXTEND)				\
+	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
+/*  for OLD_INDEXING							\
+      else if (GET_CODE (addr) == PLUS)					\
+	{								\
+	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
+	    {								\
+	      reg2 = XEXP (addr, 0);					\
+	      addr = XEXP (addr, 1);					\
+	    }								\
+	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
+	    {								\
+	      reg2 = XEXP (addr, 1);					\
+	      addr = XEXP (addr, 0);					\
+	    }								\
+	}								\
+  */									\
+      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
+      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
+		    || GET_CODE (reg1) == MULT))			\
+	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
+	{ breg = reg2; ireg = reg1; }					\
+      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
+	{ breg = reg1; ireg = reg2; }					\
+      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
+        { int scale = 1;						\
+	  if (GET_CODE (ireg) == MULT)					\
+	    { scale = INTVAL (XEXP (ireg, 1));				\
+	      ireg = XEXP (ireg, 0); }					\
+	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
+	    fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W",			\
+		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
+		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
+		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
+	  else								\
+	    fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L",			\
+		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
+		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
+		     reg_names[REGNO (ireg)]);				\
+	  fprintf (FILE, ":%c", sz[scale]);				\
+	  putc (']', FILE);						\
+	  break; }							\
+      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
+        { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]",			\
+		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
+		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
+		   reg_names[REGNO (breg)]);				\
+	  break; }							\
+      if (ireg != 0 || breg != 0)					\
+	{ int scale = 1;						\
+	  if (breg == 0)						\
+	    abort ();							\
+	  if (addr && GET_CODE (addr) == LABEL_REF) abort ();		\
+	  fprintf (FILE, "%s@", reg_names[REGNO (breg)]);		\
+	  if (addr != 0) {						\
+            putc( '(', FILE );						\
+	    output_addr_const (FILE, addr);				\
+            if (ireg != 0) {						\
+              if (GET_CODE(addr) == CONST_INT) {			\
+                int size_of = 1, val = INTVAL(addr);			\
+                if (val < -0x8000 || val >= 0x8000)			\
+                   size_of = 4;   					\
+                else if (val < -0x80 || val >= 0x80)			\
+                   size_of = 2;						\
+                fprintf(FILE, ":%c", sz[size_of]);			\
+              }        							\
+              else							\
+                fprintf(FILE, ":L"); } 					\
+            putc( ')', FILE ); }					\
+	  if (ireg != 0) {						\
+	    putc ('[', FILE);						\
+	    if (ireg != 0 && GET_CODE (ireg) == MULT)			\
+	      { scale = INTVAL (XEXP (ireg, 1));			\
+	        ireg = XEXP (ireg, 0); }				\
+	    if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
+	      fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]);	\
+	    else if (ireg != 0)						\
+	      fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]);		\
+	    fprintf (FILE, ":%c", sz[scale]);				\
+	    putc (']', FILE);						\
+          }								\
+	  break;							\
+	}								\
+      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
+	{ fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]",			\
+		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
+		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
+		   reg_names[REGNO (reg1)]);				\
+	  break; }							\
+    default:								\
+      if (GET_CODE (addr) == CONST_INT					\
+	  && INTVAL (addr) < 0x8000					\
+	  && INTVAL (addr) >= -0x8000)					\
+	fprintf (FILE, "%d:W", INTVAL (addr));				\
+      else								\
+        output_addr_const (FILE, addr);					\
+    }}
+
+/*
+Local variables:
+version-control: t
+End:
+*/
+
diff --git a/gnu/usr.bin/gcc/config/fx80/fx80.md b/gnu/usr.bin/gcc/config/fx80/fx80.md
new file mode 100644
index 00000000000..641ba9aea80
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/fx80/fx80.md
@@ -0,0 +1,2485 @@
+;;- Machine description for GNU C compiler for Alliant FX systems
+;;  Copyright (C) 1989, 1994 Free Software Foundation, Inc.
+;;  Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
+;;  and Joe Weening (weening@gang-of-four.stanford.edu).
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+
+;;- instruction definitions
+
+;;- @@The original PO technology requires these to be ordered by speed,
+;;- @@    so that assigner will pick the fastest.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;- When naming insn's (operand 0 of define_insn) be careful about using
+;;- names from other targets machine descriptions.
+
+;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
+;;- updates for most instructions.
+
+;;- Operand classes for the register allocator:
+;;- 'a' one of the address registers can be used.
+;;- 'd' one of the data registers can be used.
+;;- 'f' one of the CE floating point registers can be used
+;;- 'r' either a data or an address register can be used.
+
+;;- Immediate integer operand constraints:
+;;- 'I'  1 .. 8
+;;- 'J'  -32768 .. 32767
+;;- 'K'  -128 .. 127
+;;- 'L'  -8 .. -1
+
+;;- Some remnants of constraint codes for the m68k ('x','y','G','H')
+;;- may remain in the insn definitions.
+
+;;- Some of these insn's are composites of several Alliant op codes.
+;;- The assembler (or final @@??) insures that the appropriate one is
+;;- selected.
+
+;; We don't want to allow a constant operand for test insns because
+;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
+;; be folded while optimizing anyway.
+
+(define_insn "tstsi"
+  [(set (cc0)
+	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
+  ""
+  "*
+{
+  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
+    return \"tst%.l %0\";
+  /* If you think that the 68020 does not support tstl a0,
+     reread page B-167 of the 68020 manual more carefully.  */
+  /* On an address reg, cmpw may replace cmpl.  */
+  return \"cmp%.w %#0,%0\";
+}")
+
+(define_insn "tsthi"
+  [(set (cc0)
+	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
+  ""
+  "*
+{
+  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
+    return \"tst%.w %0\";
+  return \"cmp%.w %#0,%0\";
+}")
+
+(define_insn "tstqi"
+  [(set (cc0)
+	(match_operand:QI 0 "nonimmediate_operand" "dm"))]
+  ""
+  "tst%.b %0")
+
+(define_insn "tstsf"
+  [(set (cc0)
+	(match_operand:SF 0 "nonimmediate_operand" "fm"))]
+  "TARGET_CE"
+  "*
+{
+  cc_status.flags = CC_IN_FP;
+  return \"ftest%.s %0\";
+}")
+
+(define_insn "tstdf"
+  [(set (cc0)
+	(match_operand:DF 0 "nonimmediate_operand" "fm"))]
+  "TARGET_CE"
+  "*
+{
+  cc_status.flags = CC_IN_FP;
+  return \"ftest%.d %0\";
+}")
+
+;; compare instructions.
+
+;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
+(define_insn "cmpsi"
+  [(set (cc0)
+	(compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
+		 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    return \"cmpm%.l %1,%0\";
+  if (REG_P (operands[1])
+      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+    {
+      cc_status.flags |= CC_REVERSED;
+      return \"cmp%.l %d0,%d1\"; 
+    }
+  return \"cmp%.l %d1,%d0\";
+}")
+
+(define_insn "cmphi"
+  [(set (cc0)
+	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m")
+		 (match_operand:HI 1 "general_operand" "d,rnm,m,n")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    return \"cmpm%.w %1,%0\";
+  if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
+      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+    { cc_status.flags |= CC_REVERSED;
+      return \"cmp%.w %d0,%d1\"; 
+    }
+  return \"cmp%.w %d1,%d0\";
+}")
+
+(define_insn "cmpqi"
+  [(set (cc0)
+	(compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
+		 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    return \"cmpm%.b %1,%0\";
+  if (REG_P (operands[1])
+      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+    {
+      cc_status.flags |= CC_REVERSED;
+      return \"cmp%.b %d0,%d1\";
+    }
+  return \"cmp%.b %d1,%d0\";
+}")
+
+(define_insn "cmpdf"
+  [(set (cc0)
+	(compare (match_operand:DF 0 "nonimmediate_operand" "f,m")
+		 (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
+  "TARGET_CE"
+  "*
+{
+  cc_status.flags = CC_IN_FP;
+  if (FP_REG_P (operands[0]))
+    return \"fcmp%.d %1,%0\";
+  cc_status.flags |= CC_REVERSED;
+  return \"fcmp%.d %0,%1\";
+}")
+
+(define_insn "cmpsf"
+  [(set (cc0)
+	(compare (match_operand:SF 0 "nonimmediate_operand" "f,m")
+		 (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
+  "TARGET_CE"
+  "*
+{
+  cc_status.flags = CC_IN_FP;
+  if (FP_REG_P (operands[0]))
+    return \"fcmp%.s %1,%0\";
+  cc_status.flags |= CC_REVERSED;
+  return \"fcmp%.s %0,%1\";
+}")
+
+;; Recognizers for btst instructions.
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+			    (const_int 1)
+			    (minus:SI (const_int 7)
+				      (match_operand:SI 1 "general_operand" "di"))))]
+  ""
+  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+			    (const_int 1)
+			    (minus:SI (const_int 31)
+				      (match_operand:SI 1 "general_operand" "di"))))]
+  ""
+  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
+
+;; The following two patterns are like the previous two
+;; except that they use the fact that bit-number operands
+;; are automatically masked to 3 or 5 bits.
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+			    (const_int 1)
+			    (minus:SI (const_int 7)
+				      (and:SI
+				       (match_operand:SI 1 "general_operand" "d")
+				       (const_int 7)))))]
+  ""
+  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+			    (const_int 1)
+			    (minus:SI (const_int 31)
+				      (and:SI
+				       (match_operand:SI 1 "general_operand" "d")
+				       (const_int 31)))))]
+  ""
+  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
+
+;; Nonoffsettable mem refs are ok in this one pattern
+;; since we don't try to adjust them.
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
+			    (const_int 1)
+			    (match_operand:SI 1 "general_operand" "i")))]
+  "GET_CODE (operands[1]) == CONST_INT
+   && (unsigned) INTVAL (operands[1]) < 8"
+  "*
+{
+  operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
+  return output_btst (operands, operands[1], operands[0], insn, 7);
+}")
+
+
+(define_insn ""
+  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
+			    (const_int 1)
+			    (match_operand:SI 1 "general_operand" "i")))]
+  "GET_CODE (operands[1]) == CONST_INT"
+  "*
+{
+  if (GET_CODE (operands[0]) == MEM)
+    {
+      operands[0] = adj_offsettable_operand (operands[0],
+					     INTVAL (operands[1]) / 8);
+      operands[1] = gen_rtx (CONST_INT, VOIDmode, 
+			     7 - INTVAL (operands[1]) % 8);
+      return output_btst (operands, operands[1], operands[0], insn, 7);
+    }
+  operands[1] = gen_rtx (CONST_INT, VOIDmode,
+			 31 - INTVAL (operands[1]));
+  return output_btst (operands, operands[1], operands[0], insn, 31);
+}")
+
+
+;; move instructions
+
+;; A special case in which it is not desirable
+;; to reload the constant into a data register.
+(define_insn ""
+  [(set (match_operand:SI 0 "push_operand" "=m")
+	(match_operand:SI 1 "general_operand" "J"))]
+  "GET_CODE (operands[1]) == CONST_INT
+   && INTVAL (operands[1]) >= -0x8000
+   && INTVAL (operands[1]) < 0x8000"
+  "*
+{
+  if (operands[1] == const0_rtx)
+    return \"clr%.l %0\";
+  return \"pea %a1\";
+}")
+
+;This is never used.
+;(define_insn "swapsi"
+;  [(set (match_operand:SI 0 "general_operand" "r")
+;	(match_operand:SI 1 "general_operand" "r"))
+;   (set (match_dup 1) (match_dup 0))]
+;  ""
+;  "exg %1,%0")
+
+;; Special case of fullword move when source is zero.
+;; The reason this is special is to avoid loading a zero
+;; into a data reg with moveq in order to store it elsewhere.
+   
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=a,g")
+	(const_int 0))]
+  ""
+  "@
+   sub%.l %0,%0
+   clr%.l %0")
+
+;; General case of fullword move.  The register constraints
+;; force integer constants in range for a moveq to be reloaded
+;; if they are headed for memory.
+(define_insn "movsi"
+  ;; Notes: make sure no alternative allows g vs g.
+  ;; We don't allow f-regs since fixed point cannot go in them.
+  ;; We do allow y and x regs since fixed point is allowed in them.
+  [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
+	(match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    {
+      if (operands[1] == const0_rtx
+	  && (DATA_REG_P (operands[0])
+	      || GET_CODE (operands[0]) == MEM))
+	return \"clr%.l %0\";
+      else if (DATA_REG_P (operands[0])
+	       && INTVAL (operands[1]) < 128
+	       && INTVAL (operands[1]) >= -128)
+	return \"moveq %1,%0\";
+      else if (ADDRESS_REG_P (operands[0])
+	       && INTVAL (operands[1]) < 0x8000
+	       && INTVAL (operands[1]) >= -0x8000)
+	return \"mov%.w %1,%0\";
+      else if (push_operand (operands[0], SImode)
+	       && INTVAL (operands[1]) < 0x8000
+	       && INTVAL (operands[1]) >= -0x8000)
+        return \"pea %a1\";
+    }
+  else if ((GET_CODE (operands[1]) == SYMBOL_REF
+	    || GET_CODE (operands[1]) == CONST)
+	   && push_operand (operands[0], SImode))
+    return \"pea %a1\";
+  else if ((GET_CODE (operands[1]) == SYMBOL_REF
+	    || GET_CODE (operands[1]) == CONST)
+	   && ADDRESS_REG_P (operands[0]))
+    return \"lea %a1,%0\";
+  return \"mov%.l %1,%0\";
+}")
+
+(define_insn "movhi"
+  [(set (match_operand:HI 0 "general_operand" "=g")
+	(match_operand:HI 1 "general_operand" "g"))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == CONST_INT)
+    {
+      if (operands[1] == const0_rtx
+	  && (DATA_REG_P (operands[0])
+	      || GET_CODE (operands[0]) == MEM))
+	return \"clr%.w %0\";
+      else if (DATA_REG_P (operands[0])
+	       && INTVAL (operands[1]) < 128
+	       && INTVAL (operands[1]) >= -128)
+        {
+	  return \"moveq %1,%0\";
+	}
+      else if (INTVAL (operands[1]) < 0x8000
+	       && INTVAL (operands[1]) >= -0x8000)
+	return \"mov%.w %1,%0\";
+    }
+  else if (CONSTANT_P (operands[1]))
+    return \"mov%.l %1,%0\";
+  /* Recognize the insn before a tablejump, one that refers
+     to a table of offsets.  Such an insn will need to refer
+     to a label on the insn.  So output one.  Use the label-number
+     of the table of offsets to generate this label.  */
+  if (GET_CODE (operands[1]) == MEM
+      && GET_CODE (XEXP (operands[1], 0)) == PLUS
+      && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
+	  || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
+      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
+      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
+    {
+      rtx labelref;
+      if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
+	labelref = XEXP (XEXP (operands[1], 0), 0);
+      else
+	labelref = XEXP (XEXP (operands[1], 0), 1);
+      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
+				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
+    }
+  return \"mov%.w %1,%0\";
+}")
+
+(define_insn "movstricthi"
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
+	(match_operand:HI 1 "general_operand" "rmn"))]
+  ""
+  "*
+{
+  if (operands[1] == const0_rtx)
+    return \"clr%.w %0\";
+  return \"mov%.w %1,%0\";
+}")
+
+(define_insn "movqi"
+  [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
+	(match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
+  ""
+  "*
+{
+  rtx xoperands[4];
+  if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
+    {
+      xoperands[1] = operands[1];
+      xoperands[2]
+        = gen_rtx (MEM, QImode,
+		   gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
+      xoperands[3] = stack_pointer_rtx;
+      /* Just pushing a byte puts it in the high byte of the halfword.  */
+      /* We must put it in the low half, the second byte.  */
+      output_asm_insn (\"subq%.w %#2,%3\;mov%.b %1,%2\", xoperands);
+      return \"mov%.w %+,%0\";
+    }
+  if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
+    {
+      xoperands[0] = operands[0];
+      xoperands[1] = operands[1];
+      xoperands[2]
+        = gen_rtx (MEM, QImode,
+		   gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
+      xoperands[3] = stack_pointer_rtx;
+      output_asm_insn (\"mov%.w %1,%-\;mov%.b %2,%0\;addq%.w %#2,%3\", xoperands);
+      return \"\";
+    }
+  if (operands[1] == const0_rtx)
+    return \"clr%.b %0\";
+  if (GET_CODE (operands[1]) == CONST_INT
+      && INTVAL (operands[1]) == -1)
+    return \"st %0\";
+  if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
+    return \"mov%.l %1,%0\";
+  if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
+    return \"mov%.w %1,%0\";
+  return \"mov%.b %1,%0\";
+}")
+
+(define_insn "movstrictqi"
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
+	(match_operand:QI 1 "general_operand" "dmn"))]
+  ""
+  "*
+{
+  if (operands[1] == const0_rtx)
+    return \"clr%.b %0\";
+  return \"mov%.b %1,%0\";
+}")
+
+;; Floating-point moves on a CE are faster using an FP register than
+;; with movl instructions.  (Especially for double floats, but also
+;; for single floats, even though it takes an extra instruction.)  But
+;; on an IP, the FP registers are simulated and so should be avoided.
+;; We do this by using define_expand for movsf and movdf, and using
+;; different constraints for each target type.  The constraints for
+;; TARGET_CE allow general registers because they sometimes need to
+;; hold floats, but they are not preferable.
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "nonimmediate_operand" ""))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "general_operand" "=f,m,!*r,!f*m")
+	(match_operand:SF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))]
+  "TARGET_CE"
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return \"fmove%.s %1,%0\";
+      if (REG_P (operands[1]))
+	return \"mov%.l %1,%-\;fmove%.s %+,%0\";
+      return \"fmove%.s %1,%0\";
+    }
+  if (FP_REG_P (operands[1]))
+    {
+      if (REG_P (operands[0]))
+	return \"fmove%.s %1,%-\;mov%.l %+,%0\";
+      return \"fmove%.s %1,%0\";
+    }
+  return \"mov%.l %1,%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "general_operand" "=frm")
+	(match_operand:SF 1 "nonimmediate_operand" "frm"))]
+  "!TARGET_CE"
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return \"fmove%.s %1,%0\";
+      if (REG_P (operands[1]))
+	return \"mov%.l %1,%-\;fmove%.s %+,%0\";
+      return \"fmove%.s %1,%0\";
+    }
+  if (FP_REG_P (operands[1]))
+    {
+      if (REG_P (operands[0]))
+	return \"fmove%.s %1,%-\;mov%.l %+,%0\";
+      return \"fmove%.s %1,%0\";
+    }
+  return \"mov%.l %1,%0\";
+}")
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+	(match_operand:DF 1 "nonimmediate_operand" ""))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand" "=f,m,!*r,!f*m")
+	(match_operand:DF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))]
+  "TARGET_CE"
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return \"fmove%.d %1,%0\";
+      if (REG_P (operands[1]))
+	{
+	  rtx xoperands[2];
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+	  output_asm_insn (\"mov%.l %1,%-\", xoperands);
+	  output_asm_insn (\"mov%.l %1,%-\", operands);
+	  return \"fmove%.d %+,%0\";
+	}
+      return \"fmove%.d %1,%0\";
+    }
+  else if (FP_REG_P (operands[1]))
+    {
+      if (REG_P (operands[0]))
+	{
+	  output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands);
+	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  return \"mov%.l %+,%0\";
+	}
+      return \"fmove%.d %1,%0\";
+    }
+  return output_move_double (operands);
+}")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand" "=frm")
+	(match_operand:DF 1 "nonimmediate_operand" "frm"))]
+  "!TARGET_CE"
+  "*
+{
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+	return \"fmove%.d %1,%0\";
+      if (REG_P (operands[1]))
+	{
+	  rtx xoperands[2];
+	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+	  output_asm_insn (\"mov%.l %1,%-\", xoperands);
+	  output_asm_insn (\"mov%.l %1,%-\", operands);
+	  return \"fmove%.d %+,%0\";
+	}
+      return \"fmove%.d %1,%0\";
+    }
+  else if (FP_REG_P (operands[1]))
+    {
+      if (REG_P (operands[0]))
+	{
+	  output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands);
+	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  return \"mov%.l %+,%0\";
+	}
+      return \"fmove%.d %1,%0\";
+    }
+  return output_move_double (operands);
+}")
+
+(define_insn "movdi"
+  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>")
+	(match_operand:DI 1 "general_operand" "r,m,roi<>"))]
+  ""
+  "*
+{
+  return output_move_double (operands);
+}
+")
+
+;; This goes after the move instructions
+;; because the move instructions are better (require no spilling)
+;; when they can apply.  It goes before the add/sub insns
+;; so we will prefer it to them.
+
+(define_insn "pushasi"
+  [(set (match_operand:SI 0 "push_operand" "=m")
+	(match_operand:SI 1 "address_operand" "p"))]
+  ""
+  "pea %a1")
+
+;; truncation instructions
+(define_insn "truncsiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm,d")
+	(truncate:QI
+	 (match_operand:SI 1 "general_operand" "doJ,i")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == REG)
+    return \"mov%.l %1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    operands[1] = adj_offsettable_operand (operands[1], 3);
+  return \"mov%.b %1,%0\";
+}")
+
+(define_insn "trunchiqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm,d")
+	(truncate:QI
+	 (match_operand:HI 1 "general_operand" "doJ,i")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == REG
+      && (GET_CODE (operands[1]) == MEM
+	  || GET_CODE (operands[1]) == CONST_INT))
+    return \"mov%.w %1,%0\";
+  if (GET_CODE (operands[0]) == REG)
+    return \"mov%.l %1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    operands[1] = adj_offsettable_operand (operands[1], 1);
+  return \"mov%.b %1,%0\";
+}")
+
+(define_insn "truncsihi2"
+  [(set (match_operand:HI 0 "general_operand" "=dm,d")
+	(truncate:HI
+	 (match_operand:SI 1 "general_operand" "roJ,i")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[0]) == REG)
+    return \"mov%.l %1,%0\";
+  if (GET_CODE (operands[1]) == MEM)
+    operands[1] = adj_offsettable_operand (operands[1], 2);
+  return \"mov%.w %1,%0\";
+}")
+
+;; zero extension instructions
+
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(const_int 0))
+   (set (strict_low_part (subreg:HI (match_dup 0) 0))
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "operands[1] = make_safe_from (operands[1], operands[0]);")
+
+(define_expand "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(const_int 0))
+   (set (strict_low_part (subreg:QI (match_dup 0) 0))
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "operands[1] = make_safe_from (operands[1], operands[0]);")
+
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(const_int 0))
+   (set (strict_low_part (subreg:QI (match_dup 0) 0))
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  " operands[1] = make_safe_from (operands[1], operands[0]); ")
+
+;; Patterns to recognize zero-extend insns produced by the combiner.
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=do<>")
+	(zero_extend:SI
+	 (match_operand:HI 1 "nonimmediate_operand" "rm")))]
+  ""
+  "*
+{
+  if (DATA_REG_P (operands[0]))
+    {
+      if (GET_CODE (operands[1]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[1]))
+	return \"and%.l %#0xFFFF,%0\";
+      if (reg_mentioned_p (operands[0], operands[1]))
+        return \"mov%.w %1,%0\;and%.l %#0xFFFF,%0\";
+      return \"clr%.l %0\;mov%.w %1,%0\";
+    }
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    return \"mov%.w %1,%0\;clr%.w %0\";
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    return \"clr%.w %0\;mov%.w %1,%0\";
+  else
+    {
+      output_asm_insn (\"clr%.w %0\", operands);
+      operands[0] = adj_offsettable_operand (operands[0], 2);
+      return \"mov%.w %1,%0\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=do<>")
+	(zero_extend:HI
+	 (match_operand:QI 1 "nonimmediate_operand" "dm")))]
+  ""
+  "*
+{
+  if (DATA_REG_P (operands[0]))
+    {
+      if (GET_CODE (operands[1]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[1]))
+	return \"and%.w %#0xFF,%0\";
+      if (reg_mentioned_p (operands[0], operands[1]))
+        return \"mov%.b %1,%0\;and%.w %#0xFF,%0\";
+      return \"clr%.w %0\;mov%.b %1,%0\";
+    }
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    {
+      if (REGNO (XEXP (XEXP (operands[0], 0), 0))
+	  == STACK_POINTER_REGNUM)
+	return \"clr%.w %-\;mov%.b %1,%0\";
+      else
+	return \"mov%.b %1,%0\;clr%.b %0\";
+    }
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    return \"clr%.b %0\;mov%.b %1,%0\";
+  else
+    {
+      output_asm_insn (\"clr%.b %0\", operands);
+      operands[0] = adj_offsettable_operand (operands[0], 1);
+      return \"mov%.b %1,%0\";
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=do<>")
+	(zero_extend:SI
+	 (match_operand:QI 1 "nonimmediate_operand" "dm")))]
+  ""
+  "*
+{
+  if (DATA_REG_P (operands[0]))
+    {
+      if (GET_CODE (operands[1]) == REG
+	  && REGNO (operands[0]) == REGNO (operands[1]))
+	return \"and%.l %#0xFF,%0\";
+      if (reg_mentioned_p (operands[0], operands[1]))
+        return \"mov%.b %1,%0\;and%.l %#0xFF,%0\";
+      return \"clr%.l %0\;mov%.b %1,%0\";
+    }
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    {
+      operands[0] = XEXP (XEXP (operands[0], 0), 0);
+      return \"clr%.l %0@-\;mov%.b %1,%0@(3)\";
+    }
+  else if (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    {
+      operands[0] = XEXP (XEXP (operands[0], 0), 0);
+      return \"clr%.l %0@+\;mov%.b %1,%0@(-1)\";
+    }
+  else
+    {
+      output_asm_insn (\"clr%.l %0\", operands);
+      operands[0] = adj_offsettable_operand (operands[0], 3);
+      return \"mov%.b %1,%0\";
+    }
+}")
+
+;; sign extension instructions
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "=*d,a")
+	(sign_extend:SI
+	 (match_operand:HI 1 "nonimmediate_operand" "0,rmn")))]
+  ""
+  "@
+   ext%.l %0
+   mov%.w %1,%0")
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(sign_extend:HI
+	 (match_operand:QI 1 "nonimmediate_operand" "0")))]
+  ""
+  "ext%.w %0")
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(sign_extend:SI
+	 (match_operand:QI 1 "nonimmediate_operand" "0")))]
+  "TARGET_68020"
+  "extb%.l %0")
+
+;; Conversions between float and double.
+
+(define_insn "extendsfdf2"
+  [(set (match_operand:DF 0 "general_operand" "=f,m")
+	(float_extend:DF
+	  (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
+  "TARGET_CE"
+  "fmovesd %1,%0")
+
+(define_insn "truncdfsf2"
+  [(set (match_operand:SF 0 "general_operand" "=f,m")
+	(float_truncate:SF
+	  (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
+  "TARGET_CE"
+  "fmoveds %1,%0")
+
+;; Conversion between fixed point and floating point.
+;; Note that among the fix-to-float insns
+;; the ones that start with SImode come first.
+;; That is so that an operand that is a CONST_INT
+;; (and therefore lacks a specific machine mode).
+;; will be recognized as SImode (which is always valid)
+;; rather than as QImode or HImode.
+
+(define_insn "floatsisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmovels %1,%0")
+
+(define_insn "floatsidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmoveld %1,%0")
+
+(define_insn "floathisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float:SF (match_operand:HI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmovews %1,%0")
+
+(define_insn "floathidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float:DF (match_operand:HI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmovewd %1,%0")
+
+(define_insn "floatqisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float:SF (match_operand:QI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmovebs %1,%0")
+
+(define_insn "floatqidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float:DF (match_operand:QI 1 "nonimmediate_operand" "dm")))]
+  "TARGET_CE"
+  "fmovebd %1,%0")
+
+;; Float-to-fix conversion insns.
+
+(define_insn "fix_truncsfqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm")
+	(fix:QI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovesb %1,%0")
+
+(define_insn "fix_truncsfhi2"
+  [(set (match_operand:HI 0 "general_operand" "=dm")
+	(fix:HI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovesw %1,%0")
+
+(define_insn "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=dm")
+	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovesl %1,%0")
+
+(define_insn "fix_truncdfqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm")
+	(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovedb %1,%0")
+
+(define_insn "fix_truncdfhi2"
+  [(set (match_operand:HI 0 "general_operand" "=dm")
+	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovedw %1,%0")
+
+(define_insn "fix_truncdfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=dm")
+	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
+  "TARGET_CE"
+  "fmovedl %1,%0")
+
+;; add instructions
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a")
+	(plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK")
+		 (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))]
+  ""
+  "*
+{
+  if (! operands_match_p (operands[0], operands[1]))
+    {
+      if (!ADDRESS_REG_P (operands[1]))
+	{
+	  rtx tmp = operands[1];
+
+	  operands[1] = operands[2];
+	  operands[2] = tmp;
+	}
+
+      /* These insns can result from reloads to access
+	 stack slots over 64k from the frame pointer.  */
+      if (GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
+        return \"mov%.l %2,%0\;add%.l %1,%0\";
+      if (GET_CODE (operands[2]) == REG)
+	return \"lea %1@[%2:L:B],%0\";
+      else
+	return \"lea %1@(%c2),%0\";
+    }
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      if (INTVAL (operands[2]) > 0
+	  && INTVAL (operands[2]) <= 8)
+	return (ADDRESS_REG_P (operands[0])
+		? \"addq%.w %2,%0\"
+		: \"addq%.l %2,%0\");
+      if (INTVAL (operands[2]) < 0
+	  && INTVAL (operands[2]) >= -8)
+        {
+	  operands[2] = gen_rtx (CONST_INT, VOIDmode,
+			         - INTVAL (operands[2]));
+	  return (ADDRESS_REG_P (operands[0])
+		  ? \"subq%.w %2,%0\"
+		  : \"subq%.l %2,%0\");
+	}
+      if (ADDRESS_REG_P (operands[0])
+	  && INTVAL (operands[2]) >= -0x8000
+	  && INTVAL (operands[2]) < 0x8000)
+	return \"add%.w %2,%0\";
+    }
+  return \"add%.l %2,%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=a")
+	(plus:SI (match_operand:SI 1 "general_operand" "0")
+		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))]
+  ""
+  "add%.w %2,%0")
+
+(define_insn "addhi3"
+  [(set (match_operand:HI 0 "general_operand" "=mr,mr,m,r")
+	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
+		 (match_operand:HI 2 "general_operand" "I,L,dn,rmn")))]
+  ""
+  "@
+   addq%.w %2,%0
+   subq%.w #%n2,%0
+   add%.w %2,%0
+   add%.w %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(plus:HI (match_dup 0)
+		 (match_operand:HI 1 "general_operand" "dn,rmn")))]
+  ""
+  "add%.w %1,%0")
+
+(define_insn "addqi3"
+  [(set (match_operand:QI 0 "general_operand" "=md,mr,m,d")
+	(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
+		 (match_operand:QI 2 "general_operand" "I,L,dn,dmn")))]
+  ""
+  "@
+   addq%.b %2,%0
+   subq%.b #%n2,%0
+   add%.b %2,%0
+   add%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(plus:QI (match_dup 0)
+		 (match_operand:QI 1 "general_operand" "dn,dmn")))]
+  ""
+  "add%.b %1,%0")
+
+(define_insn "adddf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%f")
+		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fadd%.d %2,%1,%0")
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%f")
+		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fadd%.s %2,%1,%0")
+
+;; subtract instructions
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")
+	(minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
+		  (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
+  ""
+  "*
+{
+  if (! operands_match_p (operands[0], operands[1]))
+    {
+      if (operands_match_p (operands[0], operands[2]))
+	{
+	  if (GET_CODE (operands[1]) == CONST_INT)
+	    {
+	      if (INTVAL (operands[1]) > 0
+		  && INTVAL (operands[1]) <= 8)
+		return \"subq%.l %1,%0\;neg%.l %0\";
+	    }
+	  return \"sub%.l %1,%0\;neg%.l %0\";
+	}
+      /* This case is matched by J, but negating -0x8000
+         in an lea would give an invalid displacement.
+	 So do this specially.  */
+      if (INTVAL (operands[2]) == -0x8000)
+	return \"mov%.l %1,%0\;sub%.l %2,%0\";
+      return \"lea %1@(%n2),%0\";
+    }
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      if (INTVAL (operands[2]) > 0
+	  && INTVAL (operands[2]) <= 8)
+	return \"subq%.l %2,%0\";
+      if (ADDRESS_REG_P (operands[0])
+	  && INTVAL (operands[2]) >= -0x8000
+	  && INTVAL (operands[2]) < 0x8000)
+	return \"sub%.w %2,%0\";
+    }
+  return \"sub%.l %2,%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=a")
+	(minus:SI (match_operand:SI 1 "general_operand" "0")
+		  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))]
+  ""
+  "sub%.w %2,%0")
+
+(define_insn "subhi3"
+  [(set (match_operand:HI 0 "general_operand" "=m,r")
+	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
+		  (match_operand:HI 2 "general_operand" "dn,rmn")))]
+  ""
+  "sub%.w %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
+	(minus:HI (match_dup 0)
+		  (match_operand:HI 1 "general_operand" "dn,rmn")))]
+  ""
+  "sub%.w %1,%0")
+
+(define_insn "subqi3"
+  [(set (match_operand:QI 0 "general_operand" "=m,d")
+	(minus:QI (match_operand:QI 1 "general_operand" "0,0")
+		  (match_operand:QI 2 "general_operand" "dn,dmn")))]
+  ""
+  "sub%.b %2,%0")
+
+(define_insn ""
+  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
+	(minus:QI (match_dup 0)
+		  (match_operand:QI 1 "general_operand" "dn,dmn")))]
+  ""
+  "sub%.b %1,%0")
+
+(define_insn "subdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+	(minus:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m")
+		  (match_operand:DF 2 "nonimmediate_operand" "f,m,f")))]
+  "TARGET_CE"
+  "@
+   fsub%.d %2,%1,%0
+   fsub%.d %2,%1,%0
+   frsub%.d %1,%2,%0")
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
+	(minus:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m")
+		  (match_operand:SF 2 "nonimmediate_operand" "f,m,f")))]
+  "TARGET_CE"
+  "@
+   fsub%.s %2,%1,%0
+   fsub%.s %2,%1,%0
+   frsub%.s %1,%2,%0")
+
+;; multiply instructions
+
+(define_insn "mulhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(mult:HI (match_operand:HI 1 "general_operand" "%0")
+		 (match_operand:HI 2 "general_operand" "dmn")))]
+  ""
+  "muls %2,%0")
+
+(define_insn "mulhisi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0"))
+		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
+  ""
+  "muls %2,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0"))
+		 (match_operand:SI 2 "const_int_operand" "n")))]
+  ""
+  "muls %2,%0")
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(mult:SI (match_operand:SI 1 "general_operand" "%0")
+		 (match_operand:SI 2 "general_operand" "dmsK")))]
+  "TARGET_68020"
+  "muls%.l %2,%0")
+
+(define_insn "umulhisi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(mult:SI (zero_extend:SI
+		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
+		 (zero_extend:SI
+		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
+  ""
+  "mulu %2,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(mult:SI (zero_extend:SI
+		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
+		 (match_operand:SI 2 "const_int_operand" "n")))]
+  ""
+  "mulu %2,%0")
+
+(define_insn "muldf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%f")
+		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fmul%.d %2,%1,%0")
+
+(define_insn "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%f")
+		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fmul%.s %2,%1,%0")
+
+;; divide instructions
+
+(define_insn "divhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(div:HI (match_operand:HI 1 "general_operand" "0")
+		(match_operand:HI 2 "general_operand" "dmn")))]
+  ""
+  "extl %0\;divs %2,%0")
+
+(define_insn "divhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI
+	 (div:SI
+	  (match_operand:SI 1 "general_operand" "0")
+	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+  ""
+  "divs %2,%0")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0")
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
+  ""
+  "divs %2,%0")
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(div:SI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:SI 2 "general_operand" "dmsK")))]
+  "TARGET_68020"
+  "divs%.l %2,%0,%0")
+
+(define_insn "udivhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(udiv:HI (match_operand:HI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "dmn")))]
+  ""
+  "and%.l %#0xFFFF,%0\;divu %2,%0")
+
+(define_insn "udivhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI
+	 (udiv:SI
+	  (match_operand:SI 1 "general_operand" "0")
+	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+  ""
+  "divu %2,%0")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
+			      (match_operand:HI 2 "const_int_operand" "n"))))]
+  ""
+  "divu %2,%0")
+
+(define_insn "udivsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "dmsK")))]
+  "TARGET_68020"
+  "divu%.l %2,%0,%0")
+
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+	(div:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m")
+		(match_operand:DF 2 "nonimmediate_operand" "f,m,f")))]
+  "TARGET_CE"
+  "@
+   fdiv%.d %2,%1,%0
+   fdiv%.d %2,%1,%0
+   frdiv%.d %1,%2,%0")
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
+	(div:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m")
+		(match_operand:SF 2 "nonimmediate_operand" "f,m,f")))]
+  "TARGET_CE"
+  "@
+   fdiv%.s %2,%1,%0
+   fdiv%.s %2,%1,%0
+   frdiv%.s %1,%2,%0")
+
+;; Remainder instructions.
+
+(define_insn "modhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(mod:HI (match_operand:HI 1 "general_operand" "0")
+		(match_operand:HI 2 "general_operand" "dmn")))]
+  ""
+  "extl %0\;divs %2,%0\;swap %0")
+
+(define_insn "modhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI
+	 (mod:SI
+	  (match_operand:SI 1 "general_operand" "0")
+	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+  ""
+  "divs %2,%0\;swap %0")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0")
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
+  ""
+  "divs %2,%0\;swap %0")
+
+(define_insn "umodhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(umod:HI (match_operand:HI 1 "general_operand" "0")
+		 (match_operand:HI 2 "general_operand" "dmn")))]
+  ""
+  "and%.l %#0xFFFF,%0\;divu %2,%0\;swap %0")
+
+(define_insn "umodhisi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI
+	 (umod:SI
+	  (match_operand:SI 1 "general_operand" "0")
+	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+  ""
+  "divu %2,%0\;swap %0")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0")
+			      (match_operand:SI 2 "const_int_operand" "n"))))]
+  ""
+  "divu %2,%0\;swap %0")
+
+(define_insn "divmodsi4"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(div:SI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:SI 2 "general_operand" "dmsK")))
+   (set (match_operand:SI 3 "general_operand" "=d")
+	(mod:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_68020"
+  "divs%.l %2,%0,%3")
+
+(define_insn "udivmodsi4"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_operand" "dmsK")))
+   (set (match_operand:SI 3 "general_operand" "=d")
+	(umod:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_68020"
+  "divu%.l %2,%0,%3")
+
+;; logical-and instructions
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "general_operand" "=m,d")
+	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
+		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
+      && (DATA_REG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+    { 
+      if (GET_CODE (operands[0]) != REG)
+        operands[0] = adj_offsettable_operand (operands[0], 2);
+      operands[2] = gen_rtx (CONST_INT, VOIDmode,
+			     INTVAL (operands[2]) & 0xffff);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      if (operands[2] == const0_rtx)
+        return \"clr%.w %0\";
+      return \"and%.w %2,%0\";
+    }
+  return \"and%.l %2,%0\";
+}")
+
+(define_insn "andhi3"
+  [(set (match_operand:HI 0 "general_operand" "=m,d")
+	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
+		(match_operand:HI 2 "general_operand" "dn,dmn")))]
+  ""
+  "and%.w %2,%0")
+
+(define_insn "andqi3"
+  [(set (match_operand:QI 0 "general_operand" "=m,d")
+	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
+		(match_operand:QI 2 "general_operand" "dn,dmn")))]
+  ""
+  "and%.b %2,%0")
+
+
+;; inclusive-or instructions
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "general_operand" "=m,d")
+	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
+		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
+  ""
+  "*
+{
+  register int logval;
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) >> 16 == 0
+      && (DATA_REG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+    { 
+      if (GET_CODE (operands[0]) != REG)
+        operands[0] = adj_offsettable_operand (operands[0], 2);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      return \"or%.w %2,%0\";
+    }
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
+      && (DATA_REG_P (operands[0])
+	  || offsettable_memref_p (operands[0])))
+    { 
+      if (DATA_REG_P (operands[0]))
+	operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
+      else
+        {
+	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+	  operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
+	}
+      return \"bset %1,%0\";
+    }
+  return \"or%.l %2,%0\";
+}")
+
+(define_insn "iorhi3"
+  [(set (match_operand:HI 0 "general_operand" "=m,d")
+	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
+		(match_operand:HI 2 "general_operand" "dn,dmn")))]
+  ""
+  "or%.w %2,%0")
+
+(define_insn "iorqi3"
+  [(set (match_operand:QI 0 "general_operand" "=m,d")
+	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
+		(match_operand:QI 2 "general_operand" "dn,dmn")))]
+  ""
+  "or%.b %2,%0")
+
+;; xor instructions
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "general_operand" "=do,m")
+	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
+		(match_operand:SI 2 "general_operand" "di,dKs")))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) >> 16 == 0
+      && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
+    { 
+      if (! DATA_REG_P (operands[0]))
+	operands[0] = adj_offsettable_operand (operands[0], 2);
+      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
+      CC_STATUS_INIT;
+      return \"eor%.w %2,%0\";
+    }
+  return \"eor%.l %2,%0\";
+}")
+
+(define_insn "xorhi3"
+  [(set (match_operand:HI 0 "general_operand" "=dm")
+	(xor:HI (match_operand:HI 1 "general_operand" "%0")
+		(match_operand:HI 2 "general_operand" "dn")))]
+  ""
+  "eor%.w %2,%0")
+
+(define_insn "xorqi3"
+  [(set (match_operand:QI 0 "general_operand" "=dm")
+	(xor:QI (match_operand:QI 1 "general_operand" "%0")
+		(match_operand:QI 2 "general_operand" "dn")))]
+  ""
+  "eor%.b %2,%0")
+
+;; negation instructions
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "general_operand" "=dm")
+	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
+  ""
+  "neg%.l %0")
+
+(define_insn "neghi2"
+  [(set (match_operand:HI 0 "general_operand" "=dm")
+	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
+  ""
+  "neg%.w %0")
+
+(define_insn "negqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm")
+	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
+  ""
+  "neg%.b %0")
+
+(define_insn "negsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(neg:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fneg%.s %1,%0")
+
+(define_insn "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fneg%.d %1,%0")
+
+;; Absolute value instructions
+
+(define_insn "abssf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(abs:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fabs%.s %1,%0")
+
+(define_insn "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fabs%.d %1,%0")
+
+;; Square root instructions
+
+(define_insn "sqrtsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fsqrt%.s %1,%0")
+
+(define_insn "sqrtdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
+  "TARGET_CE"
+  "fsqrt%.d %1,%0")
+
+;; one complement instructions
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "general_operand" "=dm")
+	(not:SI (match_operand:SI 1 "general_operand" "0")))]
+  ""
+  "not%.l %0")
+
+(define_insn "one_cmplhi2"
+  [(set (match_operand:HI 0 "general_operand" "=dm")
+	(not:HI (match_operand:HI 1 "general_operand" "0")))]
+  ""
+  "not%.w %0")
+
+(define_insn "one_cmplqi2"
+  [(set (match_operand:QI 0 "general_operand" "=dm")
+	(not:QI (match_operand:QI 1 "general_operand" "0")))]
+  ""
+  "not%.b %0")
+
+
+;; arithmetic shift instructions
+;; We don't need the shift memory by 1 bit instruction
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(ashift:SI (match_operand:SI 1 "general_operand" "0")
+		   (match_operand:SI 2 "general_operand" "dI")))]
+  ""
+  "asl%.l %2,%0")
+
+(define_insn "ashlhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(ashift:HI (match_operand:HI 1 "general_operand" "0")
+		   (match_operand:HI 2 "general_operand" "dI")))]
+  ""
+  "asl%.w %2,%0")
+
+(define_insn "ashlqi3"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(ashift:QI (match_operand:QI 1 "general_operand" "0")
+		   (match_operand:QI 2 "general_operand" "dI")))]
+  ""
+  "asl%.b %2,%0")
+
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "general_operand" "dI")))]
+  ""
+  "asr%.l %2,%0")
+
+(define_insn "ashrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "general_operand" "dI")))]
+  ""
+  "asr%.w %2,%0")
+
+(define_insn "ashrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "general_operand" "dI")))]
+  ""
+  "asr%.b %2,%0")
+
+;; logical shift instructions
+
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "general_operand" "dI")))]
+  ""
+  "lsr%.l %2,%0")
+
+(define_insn "lshrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "general_operand" "dI")))]
+  ""
+  "lsr%.w %2,%0")
+
+(define_insn "lshrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "general_operand" "dI")))]
+  ""
+  "lsr%.b %2,%0")
+
+;; rotate instructions
+
+(define_insn "rotlsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(rotate:SI (match_operand:SI 1 "general_operand" "0")
+		   (match_operand:SI 2 "general_operand" "dI")))]
+  ""
+  "rol%.l %2,%0")
+
+(define_insn "rotlhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(rotate:HI (match_operand:HI 1 "general_operand" "0")
+		   (match_operand:HI 2 "general_operand" "dI")))]
+  ""
+  "rol%.w %2,%0")
+
+(define_insn "rotlqi3"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(rotate:QI (match_operand:QI 1 "general_operand" "0")
+		   (match_operand:QI 2 "general_operand" "dI")))]
+  ""
+  "rol%.b %2,%0")
+
+(define_insn "rotrsi3"
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
+		     (match_operand:SI 2 "general_operand" "dI")))]
+  ""
+  "ror%.l %2,%0")
+
+(define_insn "rotrhi3"
+  [(set (match_operand:HI 0 "general_operand" "=d")
+	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
+		     (match_operand:HI 2 "general_operand" "dI")))]
+  ""
+  "ror%.w %2,%0")
+
+(define_insn "rotrqi3"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
+		     (match_operand:QI 2 "general_operand" "dI")))]
+  ""
+  "ror%.b %2,%0")
+
+;; Special cases of bit-field insns which we should
+;; recognize in preference to the general case.
+;; These handle aligned 8-bit and 16-bit fields,
+;; which can usually be done with move instructions.
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
+			 (match_operand:SI 1 "const_int_operand" "i")
+			 (match_operand:SI 2 "const_int_operand" "i"))
+	(match_operand:SI 3 "general_operand" "d"))]
+  "TARGET_68020 && TARGET_BITFIELD
+   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
+   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
+   && (GET_CODE (operands[0]) == REG
+       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
+  "*
+{
+  if (REG_P (operands[0]))
+    {
+      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
+        return \"bfins %3,[%c2,%c1]%0\";
+    }
+  else
+    operands[0]
+      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
+
+  if (GET_CODE (operands[3]) == MEM)
+    operands[3] = adj_offsettable_operand (operands[3],
+					   (32 - INTVAL (operands[1])) / 8);
+  if (INTVAL (operands[1]) == 8)
+    return \"mov%.b %3,%0\";
+  return \"mov%.w %3,%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=&d")
+	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+			 (match_operand:SI 2 "const_int_operand" "i")
+			 (match_operand:SI 3 "const_int_operand" "i")))]
+  "TARGET_68020 && TARGET_BITFIELD
+   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
+   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
+   && (GET_CODE (operands[1]) == REG
+       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
+  "*
+{
+  if (REG_P (operands[1]))
+    {
+      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
+	return \"bfextu [%c3,%c2]%1,%0\";
+    }
+  else
+    operands[1]
+      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+
+  output_asm_insn (\"clrl %0\", operands);
+  if (GET_CODE (operands[0]) == MEM)
+    operands[0] = adj_offsettable_operand (operands[0],
+					   (32 - INTVAL (operands[1])) / 8);
+  if (INTVAL (operands[2]) == 8)
+    return \"mov%.b %1,%0\";
+  return \"mov%.w %1,%0\";
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+			 (match_operand:SI 2 "const_int_operand" "i")
+			 (match_operand:SI 3 "const_int_operand" "i")))]
+  "TARGET_68020 && TARGET_BITFIELD
+   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
+   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
+   && (GET_CODE (operands[1]) == REG
+       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
+  "*
+{
+  if (REG_P (operands[1]))
+    {
+      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
+	return \"bfexts [%c3,%c2]%1,%0\";
+    }
+  else
+    operands[1]
+      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
+
+  if (INTVAL (operands[2]) == 8)
+    return \"mov%.b %1,%0\;extb%.l %0\";
+  return \"mov%.w %1,%0\;ext%.l %0\";
+}")
+
+;; Bit field instructions, general cases.
+;; "o,d" constraint causes a nonoffsettable memref to match the "o"
+;; so that its address is reloaded.
+
+(define_insn "extv"
+  [(set (match_operand:SI 0 "general_operand" "=d,d")
+	(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
+			 (match_operand:SI 2 "general_operand" "di,di")
+			 (match_operand:SI 3 "general_operand" "di,di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "bfexts [%c3,%c2]%1,%0")
+
+(define_insn "extzv"
+  [(set (match_operand:SI 0 "general_operand" "=d,d")
+	(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
+			 (match_operand:SI 2 "general_operand" "di,di")
+			 (match_operand:SI 3 "general_operand" "di,di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "bfextu [%c3,%c2]%1,%0")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
+			 (match_operand:SI 1 "general_operand" "di,di")
+			 (match_operand:SI 2 "general_operand" "di,di"))
+        (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
+		(match_operand:SI 3 "const_int_operand" "i,i")))]
+  "TARGET_68020 && TARGET_BITFIELD
+   && (INTVAL (operands[3]) == -1
+       || (GET_CODE (operands[1]) == CONST_INT
+           && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
+  "*
+{
+  CC_STATUS_INIT;
+  return \"bfchg [%c2,%c1]%0\";
+}")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
+			 (match_operand:SI 1 "general_operand" "di,di")
+			 (match_operand:SI 2 "general_operand" "di,di"))
+	(const_int 0))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  CC_STATUS_INIT;
+  return \"bfclr [%c2,%c1]%0\";
+}")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
+			 (match_operand:SI 1 "general_operand" "di,di")
+			 (match_operand:SI 2 "general_operand" "di,di"))
+	(const_int -1))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  CC_STATUS_INIT;
+  return \"bfset [%c2,%c1]%0\";
+}")
+
+(define_insn "insv"
+  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
+			 (match_operand:SI 1 "general_operand" "di,di")
+			 (match_operand:SI 2 "general_operand" "di,di"))
+	(match_operand:SI 3 "general_operand" "d,d"))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "bfins %3,[%c2,%c1]%0")
+
+;; Now recognize bit field insns that operate on registers
+;; (or at least were intended to do so).
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+			 (match_operand:SI 2 "general_operand" "di")
+			 (match_operand:SI 3 "general_operand" "di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "bfexts [%c3,%c2]%1,%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+			 (match_operand:SI 2 "general_operand" "di")
+			 (match_operand:SI 3 "general_operand" "di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "bfextu [%c3,%c2]%1,%0")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
+	(const_int 0))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  CC_STATUS_INIT;
+  return \"bfclr [%c2,%c1]%0\";
+}")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
+	(const_int -1))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  CC_STATUS_INIT;
+  return \"bfset [%c2,%c1]%0\";
+}")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
+	(match_operand:SI 3 "general_operand" "d"))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  return \"bfins %3,[%c2,%c1]%0\";
+}")
+
+;; Special patterns for optimizing bit-field instructions.
+
+(define_insn ""
+  [(set (cc0)
+	(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+			 (match_operand:SI 1 "const_int_operand" "i")
+			 (match_operand:SI 2 "general_operand" "di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  if (operands[1] == const1_rtx
+      && GET_CODE (operands[2]) == CONST_INT)
+    {    
+      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+      return output_btst (operands,
+			  gen_rtx (CONST_INT, VOIDmode,
+				   width - INTVAL (operands[2])),
+			  operands[0],
+			  insn, 1000);
+      /* Pass 1000 as SIGNPOS argument so that btst will
+         not think we are testing the sign bit for an `and'
+	 and assume that nonzero implies a negative result.  */
+    }
+  if (INTVAL (operands[1]) != 32)
+    cc_status.flags = CC_NOT_NEGATIVE;
+  return \"bftst [%c2,%c1]%0\";
+}")
+
+;;; now handle the register cases
+(define_insn ""
+  [(set (cc0)
+	(zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
+			 (match_operand:SI 1 "const_int_operand" "i")
+			 (match_operand:SI 2 "general_operand" "di")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "*
+{
+  if (operands[1] == const1_rtx
+      && GET_CODE (operands[2]) == CONST_INT)
+    {    
+      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+      return output_btst (operands,
+			  gen_rtx (CONST_INT, VOIDmode,
+				   width - INTVAL (operands[2])),
+			  operands[0],
+			  insn, 1000);
+      /* Pass 1000 as SIGNPOS argument so that btst will
+         not think we are testing the sign bit for an `and'
+	 and assume that nonzero implies a negative result.  */
+    }
+  if (INTVAL (operands[1]) != 32)
+    cc_status.flags = CC_NOT_NEGATIVE;
+  return \"bftst [%c2,%c1]%0\";
+}")
+
+
+(define_insn "seq"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(eq:QI (cc0) (const_int 0)))]
+  ""
+  "*
+  cc_status = cc_prev_status;
+  OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
+")
+
+(define_insn "sne"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(ne:QI (cc0) (const_int 0)))]
+  ""
+  "*
+  cc_status = cc_prev_status;
+  OUTPUT_JUMP (\"sne %0\", \"fsneq %0\", \"sne %0\");
+")
+
+(define_insn "sgt"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(gt:QI (cc0) (const_int 0)))]
+  ""
+  "*
+  cc_status = cc_prev_status;
+  OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", \"and%.b %#0xc,%!\;sgt %0\");
+")
+
+(define_insn "sgtu"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(gtu:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     return \"shi %0\"; ")
+
+(define_insn "slt"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(lt:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
+
+(define_insn "sltu"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(ltu:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     return \"scs %0\"; ")
+
+(define_insn "sge"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(ge:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
+
+(define_insn "sgeu"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(geu:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     return \"scc %0\"; ")
+
+(define_insn "sle"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(le:QI (cc0) (const_int 0)))]
+  ""
+  "*
+  cc_status = cc_prev_status;
+  OUTPUT_JUMP (\"sle %0\", \"fsle %0\", \"and%.b %#0xc,%!\;sle %0\");
+")
+
+(define_insn "sleu"
+  [(set (match_operand:QI 0 "general_operand" "=d")
+	(leu:QI (cc0) (const_int 0)))]
+  ""
+  "* cc_status = cc_prev_status;
+     return \"sls %0\"; ")
+
+;; Basic conditional jump instructions.
+
+(define_insn "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\");
+}")
+
+(define_insn "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\");
+}")
+
+(define_insn "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jgt %l0\", \"fbgt %l0\", \"and%.b %#0xc,%!\;jgt %l0\");
+")
+
+(define_insn "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  return \"jhi %l0\";
+")
+
+(define_insn "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jlt %l0\", \"fblt %l0\", \"jmi %l0\");
+")
+
+(define_insn "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  return \"jcs %l0\";
+")
+
+(define_insn "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jge %l0\", \"fbge %l0\", \"jpl %l0\");
+")
+
+(define_insn "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  return \"jcc %l0\";
+")
+
+(define_insn "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jle %l0\", \"fble %l0\", \"and%.b %#0xc,%!\;jle %l0\");
+")
+
+(define_insn "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+  return \"jls %l0\";
+")
+
+;; Negated conditional jump instructions.
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\");
+}")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\");
+}")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jle %l0\", \"fbngt %l0\", \"and%.b %#0xc,%!\;jle %l0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  return \"jls %l0\";
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jge %l0\", \"fbnlt %l0\", \"jpl %l0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  return \"jcc %l0\";
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jlt %l0\", \"fbnge %l0\", \"jmi %l0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  return \"jcs %l0\";
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  OUTPUT_JUMP (\"jgt %l0\", \"fbnle %l0\", \"and%.b %#0xc,%!\;jgt %l0\");
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+  return \"jhi %l0\";
+")
+
+;; Subroutines of "casesi".
+
+(define_expand "casesi_1"
+  [(set (match_operand:SI 3 "general_operand" "")
+	(plus:SI (match_operand:SI 0 "general_operand" "")
+		 ;; Note operand 1 has been negated!
+		 (match_operand:SI 1 "immediate_operand" "")))
+   (set (cc0) (compare (match_operand:SI 2 "nonimmediate_operand" "")
+		       (match_dup 3)))
+   (set (pc) (if_then_else (ltu (cc0) (const_int 0))
+			   (label_ref (match_operand 4 "" "")) (pc)))]
+  ""
+  "")
+
+(define_expand "casesi_2"
+  [(set (match_operand:HI 0 "" "") (mem:HI (match_operand:SI 1 "" "")))
+   ;; The USE here is so that at least one jump-insn will refer to the label,
+   ;; to keep it alive in jump_optimize.
+   (parallel [(set (pc)
+		   (plus:SI (pc) (sign_extend:SI (match_dup 0))))
+	      (use (label_ref (match_operand 2 "" "")))])]
+  ""
+  "")
+
+;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 the maximum;
+;; operand 3 is CODE_LABEL for the table;
+;; operand 4 is the CODE_LABEL to go to if index out of range.
+(define_expand "casesi"
+  ;; We don't use these for generating the RTL, but we must describe
+  ;; the operands here.
+  [(match_operand:HI 0 "general_operand" "")
+   (match_operand:SI 1 "immediate_operand" "")
+   (match_operand:SI 2 "general_operand" "")
+   (match_operand 3 "" "")
+   (match_operand 4 "" "")]
+  ""
+  "
+{
+  rtx table_elt_addr;
+  rtx index_diff;
+
+  operands[1] = negate_rtx (SImode, operands[1]);
+  index_diff = gen_reg_rtx (SImode);
+  /* Emit the first few insns.  */
+  emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2],
+			   index_diff, operands[4]));
+  /* Construct a memory address.  This may emit some insns.  */
+  table_elt_addr
+    = memory_address_noforce
+        (HImode,
+	 gen_rtx (PLUS, Pmode,
+		  gen_rtx (MULT, Pmode, index_diff,
+			   gen_rtx (CONST_INT, VOIDmode, 2)),
+		  gen_rtx (LABEL_REF, VOIDmode, operands[3])));
+  /* Emit the last few insns.  */
+  emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3]));
+  DONE;
+}")
+
+;; Recognize one of the insns resulting from casesi_2.
+(define_insn ""
+  [(set (pc)
+	(plus:SI (pc)
+		 (sign_extend:SI (match_operand:HI 0 "general_operand" "r"))))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "*
+  return \"jmp pc@(2:B)[%0:W:B]\";
+")
+
+;; Unconditional and other jump instructions
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+  return \"jra %l0\";
+")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	 (ne (match_operand:HI 0 "general_operand" "d,m,g")
+	     (const_int 0))
+	 (label_ref (match_operand 1 "" ""))
+	 (pc)))
+   (set (match_dup 0)
+	(plus:HI (match_dup 0)
+		 (const_int -1)))]
+  ""
+  "@
+   dbra %0,%l1
+   subq%.w %#1,%0\;jcc %l1
+   subq%.w %#1,%0\;cmp%.w %#-1,%0\;jne %l1")
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	 (ne (match_operand:SI 0 "general_operand" "d,m,g")
+	     (const_int 0))
+	 (label_ref (match_operand 1 "" ""))
+	 (pc)))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))]
+  ""
+  "@
+   dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jcc %l1
+   subq%.l %#1,%0\;jcc %l1
+   subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1")
+
+;; dbra patterns that use REG_NOTES info generated by strength_reduce.
+
+(define_insn "decrement_and_branch_until_zero"
+  [(set (pc)
+	(if_then_else
+	  (ge (match_operand:SI 0 "general_operand" "d,m,g")
+	      (const_int 1))
+	  (label_ref (match_operand 1 "" ""))
+	  (pc)))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))]
+  "find_reg_note (insn, REG_NONNEG, 0)"
+  "@
+   dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1
+   subq%.l %#1,%0\;jcc %l1
+   subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1")
+
+;; Call subroutine with no return value.
+(define_insn "call"
+  [(call (match_operand:QI 0 "memory_operand" "o")
+	 (match_operand:SI 1 "general_operand" "g"))]
+  ""
+  "*
+{
+  rtx xoperands[2];
+  int size = XINT(operands[1],0);
+
+  if (size == 0) 
+    output_asm_insn (\"sub%.l a0,a0\;jbsr %0\", operands);
+  else
+  {
+    xoperands[1] = gen_rtx (CONST_INT, VOIDmode, size/4);
+    output_asm_insn (\"mov%.l sp,a0\;pea %a1\", xoperands);
+    output_asm_insn (\"jbsr %0\", operands);
+    size = size + 4;
+    xoperands[1] = gen_rtx (CONST_INT, VOIDmode, size);
+    if (size <= 8)
+      output_asm_insn (\"addq%.l %1,sp\", xoperands);
+    else if (size < 0x8000)
+      output_asm_insn (\"add%.w %1,sp\", xoperands);
+    else
+      output_asm_insn (\"add%.l %1,sp\", xoperands);
+  }
+  return \"mov%.l a6@(-4),a0\";
+}")
+
+;; Call subroutine, returning value in operand 0
+;; (which must be a hard register).
+(define_insn "call_value"
+  [(set (match_operand 0 "" "=rf")
+	(call (match_operand:QI 1 "memory_operand" "o")
+	      (match_operand:SI 2 "general_operand" "g")))]
+  ""
+  "*
+{
+  rtx xoperands[3];
+  int size = XINT(operands[2],0);
+
+  if (size == 0)
+    output_asm_insn(\"sub%.l a0,a0\;jbsr %1\", operands);
+  else
+  {
+    xoperands[2] = gen_rtx (CONST_INT, VOIDmode, size/4);
+    output_asm_insn (\"mov%.l sp,a0\;pea %a2\", xoperands);
+    output_asm_insn (\"jbsr %1\", operands);
+    size = size + 4;
+    xoperands[2] = gen_rtx (CONST_INT, VOIDmode, size);
+    if (size <= 8)
+      output_asm_insn (\"addq%.l %2,sp\", xoperands);
+    else if (size < 0x8000)
+      output_asm_insn (\"add%.w %2,sp\", xoperands);
+    else
+      output_asm_insn (\"add%.l %2,sp\", xoperands);
+  }
+  return \"mov%.l a6@(-4),a0\";
+}")
+
+;; Call subroutine returning any type.
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+		    (const_int 0))
+	      (match_operand 1 "" "")
+	      (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
+
+  /* The optimizer does not know that the call sets the function value
+     registers we stored in the result block.  We avoid problems by
+     claiming that all hard registers are used and clobbered at this
+     point.  */
+  emit_insn (gen_blockage ());
+
+  DONE;
+}")
+
+;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
+;; all of memory.  This blocks insns from being moved across this point.
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  "")
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop")
+
+;; This should not be used unless the add/sub insns can't be.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=a")
+	(match_operand:QI 1 "address_operand" "p"))]
+  ""
+  "lea %a1,%0")
+
+;; This is the first machine-dependent peephole optimization.
+;; It is useful when a floating value is returned from a function call
+;; and then is moved into an FP register.
+;; But it is mainly intended to test the support for these optimizations.
+
+;Not applicable to Alliant -- floating results are returned in fp0
+;(define_peephole
+;  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
+;   (set (match_operand:DF 0 "register_operand" "f")
+;	(match_operand:DF 1 "register_operand" "ad"))]
+;  "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
+;  "*
+;{
+;  rtx xoperands[2];
+;  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+;  output_asm_insn (\"mov%.l %1,%@\", xoperands);
+;  output_asm_insn (\"mov%.l %1,%-\", operands);
+;  return \"fmove%.d %+,%0\";
+;}
+;")
diff --git a/gnu/usr.bin/gcc/config/fx80/xm-fx80.h b/gnu/usr.bin/gcc/config/fx80/xm-fx80.h
new file mode 100644
index 00000000000..178d76253f5
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/fx80/xm-fx80.h
@@ -0,0 +1,39 @@
+/* Configuration for GNU C-compiler for Alliant FX computers.
+   Copyright (C) 1989, 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33