FSF GCC version 2.7.2

6 files changed, 6378 insertions, 0 deletions

diff --git a/gnu/usr.bin/gcc/config/sh/lib1funcs.asm b/gnu/usr.bin/gcc/config/sh/lib1funcs.asm
new file mode 100644
index 00000000000..6d8d3e8ffb4
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/lib1funcs.asm
@@ -0,0 +1,955 @@
+/* Copyright (C) 1994, 1995 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+
+
+!! libgcc1 routines for the Hitachi SH cpu.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+#ifdef L_ashiftrt
+	.global	___ashiftrt_r4_0
+	.global	___ashiftrt_r4_1
+	.global	___ashiftrt_r4_2
+	.global	___ashiftrt_r4_3
+	.global	___ashiftrt_r4_4
+	.global	___ashiftrt_r4_5
+	.global	___ashiftrt_r4_6
+	.global	___ashiftrt_r4_7
+	.global	___ashiftrt_r4_8
+	.global	___ashiftrt_r4_9
+	.global	___ashiftrt_r4_10
+	.global	___ashiftrt_r4_11
+	.global	___ashiftrt_r4_12
+	.global	___ashiftrt_r4_13
+	.global	___ashiftrt_r4_14
+	.global	___ashiftrt_r4_15
+	.global	___ashiftrt_r4_16
+	.global	___ashiftrt_r4_17
+	.global	___ashiftrt_r4_18
+	.global	___ashiftrt_r4_19
+	.global	___ashiftrt_r4_20
+	.global	___ashiftrt_r4_21
+	.global	___ashiftrt_r4_22
+	.global	___ashiftrt_r4_23
+	.global	___ashiftrt_r4_24
+	.global	___ashiftrt_r4_25
+	.global	___ashiftrt_r4_26
+	.global	___ashiftrt_r4_27
+	.global	___ashiftrt_r4_28
+	.global	___ashiftrt_r4_29
+	.global	___ashiftrt_r4_30
+	.global	___ashiftrt_r4_31
+	.global	___ashiftrt_r4_32
+
+	.align	1
+___ashiftrt_r4_32:
+___ashiftrt_r4_31:
+	rotcl	r4
+	rts
+	subc	r4,r4
+
+___ashiftrt_r4_30:
+	shar	r4
+___ashiftrt_r4_29:
+	shar	r4
+___ashiftrt_r4_28:
+	shar	r4
+___ashiftrt_r4_27:
+	shar	r4
+___ashiftrt_r4_26:
+	shar	r4
+___ashiftrt_r4_25:
+	shar	r4
+___ashiftrt_r4_24:
+	shlr16	r4
+	shlr8	r4
+	rts
+	exts.b	r4,r4
+
+___ashiftrt_r4_23:
+	shar	r4
+___ashiftrt_r4_22:
+	shar	r4
+___ashiftrt_r4_21:
+	shar	r4
+___ashiftrt_r4_20:
+	shar	r4
+___ashiftrt_r4_19:
+	shar	r4
+___ashiftrt_r4_18:
+	shar	r4
+___ashiftrt_r4_17:
+	shar	r4
+___ashiftrt_r4_16:
+	shlr16	r4
+	rts
+	exts.w	r4,r4
+
+___ashiftrt_r4_15:
+	shar	r4
+___ashiftrt_r4_14:
+	shar	r4
+___ashiftrt_r4_13:
+	shar	r4
+___ashiftrt_r4_12:
+	shar	r4
+___ashiftrt_r4_11:
+	shar	r4
+___ashiftrt_r4_10:
+	shar	r4
+___ashiftrt_r4_9:
+	shar	r4
+___ashiftrt_r4_8:
+	shar	r4
+___ashiftrt_r4_7:
+	shar	r4
+___ashiftrt_r4_6:
+	shar	r4
+___ashiftrt_r4_5:
+	shar	r4
+___ashiftrt_r4_4:
+	shar	r4
+___ashiftrt_r4_3:
+	shar	r4
+___ashiftrt_r4_2:
+	shar	r4
+___ashiftrt_r4_1:
+	rts
+	shar	r4
+
+___ashiftrt_r4_0:
+	rts
+	nop
+#endif
+
+#ifdef L_ashiftrt_n
+
+!
+! ___ashrsi3
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+
+	.global	___ashrsi3
+	.align	2
+___ashrsi3:
+	mov	#31,r0
+	cmp/hi	r0,r5
+	bt	L_ashrsi3_31
+	mova	L_ashrsi3_table,r0
+	mov.b	@(r0,r5),r5
+	add	r5,r0		! Change to braf when gas is fixed
+	jmp	@r0
+	mov	r4,r0
+
+L_ashrsi3_table:
+	.byte		L_ashrsi3_0-L_ashrsi3_table
+	.byte		L_ashrsi3_1-L_ashrsi3_table
+	.byte		L_ashrsi3_2-L_ashrsi3_table
+	.byte		L_ashrsi3_3-L_ashrsi3_table
+	.byte		L_ashrsi3_4-L_ashrsi3_table
+	.byte		L_ashrsi3_5-L_ashrsi3_table
+	.byte		L_ashrsi3_6-L_ashrsi3_table
+	.byte		L_ashrsi3_7-L_ashrsi3_table
+	.byte		L_ashrsi3_8-L_ashrsi3_table
+	.byte		L_ashrsi3_9-L_ashrsi3_table
+	.byte		L_ashrsi3_10-L_ashrsi3_table
+	.byte		L_ashrsi3_11-L_ashrsi3_table
+	.byte		L_ashrsi3_12-L_ashrsi3_table
+	.byte		L_ashrsi3_13-L_ashrsi3_table
+	.byte		L_ashrsi3_14-L_ashrsi3_table
+	.byte		L_ashrsi3_15-L_ashrsi3_table
+	.byte		L_ashrsi3_16-L_ashrsi3_table
+	.byte		L_ashrsi3_17-L_ashrsi3_table
+	.byte		L_ashrsi3_18-L_ashrsi3_table
+	.byte		L_ashrsi3_19-L_ashrsi3_table
+	.byte		L_ashrsi3_20-L_ashrsi3_table
+	.byte		L_ashrsi3_21-L_ashrsi3_table
+	.byte		L_ashrsi3_22-L_ashrsi3_table
+	.byte		L_ashrsi3_23-L_ashrsi3_table
+	.byte		L_ashrsi3_24-L_ashrsi3_table
+	.byte		L_ashrsi3_25-L_ashrsi3_table
+	.byte		L_ashrsi3_26-L_ashrsi3_table
+	.byte		L_ashrsi3_27-L_ashrsi3_table
+	.byte		L_ashrsi3_28-L_ashrsi3_table
+	.byte		L_ashrsi3_29-L_ashrsi3_table
+	.byte		L_ashrsi3_30-L_ashrsi3_table
+	.byte		L_ashrsi3_31-L_ashrsi3_table
+
+L_ashrsi3_31:
+	rotcl	r0
+	rts
+	subc	r0,r0
+
+L_ashrsi3_30:
+	shar	r0
+L_ashrsi3_29:
+	shar	r0
+L_ashrsi3_28:
+	shar	r0
+L_ashrsi3_27:
+	shar	r0
+L_ashrsi3_26:
+	shar	r0
+L_ashrsi3_25:
+	shar	r0
+L_ashrsi3_24:
+	shlr16	r0
+	shlr8	r0
+	rts
+	exts.b	r0,r0
+
+L_ashrsi3_23:
+	shar	r0
+L_ashrsi3_22:
+	shar	r0
+L_ashrsi3_21:
+	shar	r0
+L_ashrsi3_20:
+	shar	r0
+L_ashrsi3_19:
+	shar	r0
+L_ashrsi3_18:
+	shar	r0
+L_ashrsi3_17:
+	shar	r0
+L_ashrsi3_16:
+	shlr16	r0
+	rts
+	exts.w	r0,r0
+
+L_ashrsi3_15:
+	shar	r0
+L_ashrsi3_14:
+	shar	r0
+L_ashrsi3_13:
+	shar	r0
+L_ashrsi3_12:
+	shar	r0
+L_ashrsi3_11:
+	shar	r0
+L_ashrsi3_10:
+	shar	r0
+L_ashrsi3_9:
+	shar	r0
+L_ashrsi3_8:
+	shar	r0
+L_ashrsi3_7:
+	shar	r0
+L_ashrsi3_6:
+	shar	r0
+L_ashrsi3_5:
+	shar	r0
+L_ashrsi3_4:
+	shar	r0
+L_ashrsi3_3:
+	shar	r0
+L_ashrsi3_2:
+	shar	r0
+L_ashrsi3_1:
+	rts
+	shar	r0
+
+L_ashrsi3_0:
+	rts
+	nop
+
+#endif
+
+#ifdef L_ashiftlt
+
+!
+! ___ashlsi3
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	___ashlsi3
+	.align	2
+___ashlsi3:
+	mov	#31,r0
+	cmp/hi	r0,r5
+	bt	L_ashlsi3_32
+	mova	L_ashlsi3_table,r0
+	mov.b	@(r0,r5),r5
+	add	r5,r0		! Change to braf when gas is fixed
+	jmp	@r0
+	mov	r4,r0
+
+L_ashlsi3_table:
+	.byte		L_ashlsi3_0-L_ashlsi3_table
+	.byte		L_ashlsi3_1-L_ashlsi3_table
+	.byte		L_ashlsi3_2-L_ashlsi3_table
+	.byte		L_ashlsi3_3-L_ashlsi3_table
+	.byte		L_ashlsi3_4-L_ashlsi3_table
+	.byte		L_ashlsi3_5-L_ashlsi3_table
+	.byte		L_ashlsi3_6-L_ashlsi3_table
+	.byte		L_ashlsi3_7-L_ashlsi3_table
+	.byte		L_ashlsi3_8-L_ashlsi3_table
+	.byte		L_ashlsi3_9-L_ashlsi3_table
+	.byte		L_ashlsi3_10-L_ashlsi3_table
+	.byte		L_ashlsi3_11-L_ashlsi3_table
+	.byte		L_ashlsi3_12-L_ashlsi3_table
+	.byte		L_ashlsi3_13-L_ashlsi3_table
+	.byte		L_ashlsi3_14-L_ashlsi3_table
+	.byte		L_ashlsi3_15-L_ashlsi3_table
+	.byte		L_ashlsi3_16-L_ashlsi3_table
+	.byte		L_ashlsi3_17-L_ashlsi3_table
+	.byte		L_ashlsi3_18-L_ashlsi3_table
+	.byte		L_ashlsi3_19-L_ashlsi3_table
+	.byte		L_ashlsi3_20-L_ashlsi3_table
+	.byte		L_ashlsi3_21-L_ashlsi3_table
+	.byte		L_ashlsi3_22-L_ashlsi3_table
+	.byte		L_ashlsi3_23-L_ashlsi3_table
+	.byte		L_ashlsi3_24-L_ashlsi3_table
+	.byte		L_ashlsi3_25-L_ashlsi3_table
+	.byte		L_ashlsi3_26-L_ashlsi3_table
+	.byte		L_ashlsi3_27-L_ashlsi3_table
+	.byte		L_ashlsi3_28-L_ashlsi3_table
+	.byte		L_ashlsi3_29-L_ashlsi3_table
+	.byte		L_ashlsi3_30-L_ashlsi3_table
+	.byte		L_ashlsi3_31-L_ashlsi3_table
+
+L_ashlsi3_6:
+	shll2	r0
+L_ashlsi3_4:
+	shll2	r0
+L_ashlsi3_2:
+	rts
+	shll2	r0
+
+L_ashlsi3_7:
+	shll2	r0
+L_ashlsi3_5:
+	shll2	r0
+L_ashlsi3_3:
+	shll2	r0
+L_ashlsi3_1:
+	rts
+	shll	r0
+
+L_ashlsi3_14:
+	shll2	r0
+L_ashlsi3_12:
+	shll2	r0
+L_ashlsi3_10:
+	shll2	r0
+L_ashlsi3_8:
+	rts
+	shll8	r0
+
+L_ashlsi3_15:
+	shll2	r0
+L_ashlsi3_13:
+	shll2	r0
+L_ashlsi3_11:
+	shll2	r0
+L_ashlsi3_9:
+	shll8	r0
+	rts
+	shll	r0
+
+L_ashlsi3_22:
+	shll2	r0
+L_ashlsi3_20:
+	shll2	r0
+L_ashlsi3_18:
+	shll2	r0
+L_ashlsi3_16:
+	rts
+	shll16	r0
+
+L_ashlsi3_23:
+	shll2	r0
+L_ashlsi3_21:
+	shll2	r0
+L_ashlsi3_19:
+	shll2	r0
+L_ashlsi3_17:
+	shll16	r0
+	rts
+	shll	r0
+
+L_ashlsi3_30:
+	shll2	r0
+L_ashlsi3_28:
+	shll2	r0
+L_ashlsi3_26:
+	shll2	r0
+L_ashlsi3_24:
+	shll16	r0
+	rts
+	shll8	r0
+
+L_ashlsi3_31:
+	shll2	r0
+L_ashlsi3_29:
+	shll2	r0
+L_ashlsi3_27:
+	shll2	r0
+L_ashlsi3_25:
+	shll16	r0
+	shll8	r0
+	rts
+	shll	r0
+
+L_ashlsi3_32:
+	rts
+	mov	#0,r0
+
+L_ashlsi3_0:
+	rts
+	nop
+
+#endif
+
+#ifdef L_lshiftrt
+
+!
+! ___lshrsi3
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	___lshrsi3
+	.align	2
+___lshrsi3:
+	mov	#31,r0
+	cmp/hi	r0,r5
+	bt	L_lshrsi3_32
+	mova	L_lshrsi3_table,r0
+	mov.b	@(r0,r5),r5
+	add	r5,r0		! Change to braf when gas is fixed
+	jmp	@r0
+	mov	r4,r0
+
+L_lshrsi3_table:
+	.byte		L_lshrsi3_0-L_lshrsi3_table
+	.byte		L_lshrsi3_1-L_lshrsi3_table
+	.byte		L_lshrsi3_2-L_lshrsi3_table
+	.byte		L_lshrsi3_3-L_lshrsi3_table
+	.byte		L_lshrsi3_4-L_lshrsi3_table
+	.byte		L_lshrsi3_5-L_lshrsi3_table
+	.byte		L_lshrsi3_6-L_lshrsi3_table
+	.byte		L_lshrsi3_7-L_lshrsi3_table
+	.byte		L_lshrsi3_8-L_lshrsi3_table
+	.byte		L_lshrsi3_9-L_lshrsi3_table
+	.byte		L_lshrsi3_10-L_lshrsi3_table
+	.byte		L_lshrsi3_11-L_lshrsi3_table
+	.byte		L_lshrsi3_12-L_lshrsi3_table
+	.byte		L_lshrsi3_13-L_lshrsi3_table
+	.byte		L_lshrsi3_14-L_lshrsi3_table
+	.byte		L_lshrsi3_15-L_lshrsi3_table
+	.byte		L_lshrsi3_16-L_lshrsi3_table
+	.byte		L_lshrsi3_17-L_lshrsi3_table
+	.byte		L_lshrsi3_18-L_lshrsi3_table
+	.byte		L_lshrsi3_19-L_lshrsi3_table
+	.byte		L_lshrsi3_20-L_lshrsi3_table
+	.byte		L_lshrsi3_21-L_lshrsi3_table
+	.byte		L_lshrsi3_22-L_lshrsi3_table
+	.byte		L_lshrsi3_23-L_lshrsi3_table
+	.byte		L_lshrsi3_24-L_lshrsi3_table
+	.byte		L_lshrsi3_25-L_lshrsi3_table
+	.byte		L_lshrsi3_26-L_lshrsi3_table
+	.byte		L_lshrsi3_27-L_lshrsi3_table
+	.byte		L_lshrsi3_28-L_lshrsi3_table
+	.byte		L_lshrsi3_29-L_lshrsi3_table
+	.byte		L_lshrsi3_30-L_lshrsi3_table
+	.byte		L_lshrsi3_31-L_lshrsi3_table
+
+L_lshrsi3_6:
+	shlr2	r0
+L_lshrsi3_4:
+	shlr2	r0
+L_lshrsi3_2:
+	rts
+	shlr2	r0
+
+L_lshrsi3_7:
+	shlr2	r0
+L_lshrsi3_5:
+	shlr2	r0
+L_lshrsi3_3:
+	shlr2	r0
+L_lshrsi3_1:
+	rts
+	shlr	r0
+
+L_lshrsi3_14:
+	shlr2	r0
+L_lshrsi3_12:
+	shlr2	r0
+L_lshrsi3_10:
+	shlr2	r0
+L_lshrsi3_8:
+	rts
+	shlr8	r0
+
+L_lshrsi3_15:
+	shlr2	r0
+L_lshrsi3_13:
+	shlr2	r0
+L_lshrsi3_11:
+	shlr2	r0
+L_lshrsi3_9:
+	shlr8	r0
+	rts
+	shlr	r0
+
+L_lshrsi3_22:
+	shlr2	r0
+L_lshrsi3_20:
+	shlr2	r0
+L_lshrsi3_18:
+	shlr2	r0
+L_lshrsi3_16:
+	rts
+	shlr16	r0
+
+L_lshrsi3_23:
+	shlr2	r0
+L_lshrsi3_21:
+	shlr2	r0
+L_lshrsi3_19:
+	shlr2	r0
+L_lshrsi3_17:
+	shlr16	r0
+	rts
+	shlr	r0
+
+L_lshrsi3_30:
+	shlr2	r0
+L_lshrsi3_28:
+	shlr2	r0
+L_lshrsi3_26:
+	shlr2	r0
+L_lshrsi3_24:
+	shlr16	r0
+	rts
+	shlr8	r0
+
+L_lshrsi3_31:
+	shlr2	r0
+L_lshrsi3_29:
+	shlr2	r0
+L_lshrsi3_27:
+	shlr2	r0
+L_lshrsi3_25:
+	shlr16	r0
+	shlr8	r0
+	rts
+	shlr	r0
+
+L_lshrsi3_32:
+	rts
+	mov	#0,r0
+
+L_lshrsi3_0:
+	rts
+	nop
+
+#endif
+
+#ifdef L_movstr
+	.text
+! done all the large groups, do the remainder
+
+! jump to movstr+
+done:
+	add	#64,r5
+	mova	___movstrSI0,r0
+	shll2	r6
+	add	r6,r0
+	jmp	@r0
+	add	#64,r4
+	.align	4
+	.global	___movstrSI64
+___movstrSI64:
+	mov.l	@(60,r5),r0
+	mov.l	r0,@(60,r4)
+	.global	___movstrSI60
+___movstrSI60:
+	mov.l	@(56,r5),r0
+	mov.l	r0,@(56,r4)
+	.global	___movstrSI56
+___movstrSI56:
+	mov.l	@(52,r5),r0
+	mov.l	r0,@(52,r4)
+	.global	___movstrSI52
+___movstrSI52:
+	mov.l	@(48,r5),r0
+	mov.l	r0,@(48,r4)
+	.global	___movstrSI48
+___movstrSI48:
+	mov.l	@(44,r5),r0
+	mov.l	r0,@(44,r4)
+	.global	___movstrSI44
+___movstrSI44:
+	mov.l	@(40,r5),r0
+	mov.l	r0,@(40,r4)
+	.global	___movstrSI40
+___movstrSI40:
+	mov.l	@(36,r5),r0
+	mov.l	r0,@(36,r4)
+	.global	___movstrSI36
+___movstrSI36:
+	mov.l	@(32,r5),r0
+	mov.l	r0,@(32,r4)
+	.global	___movstrSI32
+___movstrSI32:
+	mov.l	@(28,r5),r0
+	mov.l	r0,@(28,r4)
+	.global	___movstrSI28
+___movstrSI28:
+	mov.l	@(24,r5),r0
+	mov.l	r0,@(24,r4)
+	.global	___movstrSI24
+___movstrSI24:
+	mov.l	@(20,r5),r0
+	mov.l	r0,@(20,r4)
+	.global	___movstrSI20
+___movstrSI20:
+	mov.l	@(16,r5),r0
+	mov.l	r0,@(16,r4)
+	.global	___movstrSI16
+___movstrSI16:
+	mov.l	@(12,r5),r0
+	mov.l	r0,@(12,r4)
+	.global	___movstrSI12
+___movstrSI12:
+	mov.l	@(8,r5),r0
+	mov.l	r0,@(8,r4)
+	.global	___movstrSI8
+___movstrSI8:
+	mov.l	@(4,r5),r0
+	mov.l	r0,@(4,r4)
+	.global	___movstrSI4
+___movstrSI4:
+	mov.l	@(0,r5),r0
+	mov.l	r0,@(0,r4)
+___movstrSI0:
+	rts
+	or	r0,r0,r0
+
+	.align	4
+
+	.global	___movstr
+___movstr:
+	mov.l	@(60,r5),r0
+	mov.l	r0,@(60,r4)
+
+	mov.l	@(56,r5),r0
+	mov.l	r0,@(56,r4)
+
+	mov.l	@(52,r5),r0
+	mov.l	r0,@(52,r4)
+
+	mov.l	@(48,r5),r0
+	mov.l	r0,@(48,r4)
+
+	mov.l	@(44,r5),r0
+	mov.l	r0,@(44,r4)
+
+	mov.l	@(40,r5),r0
+	mov.l	r0,@(40,r4)
+
+	mov.l	@(36,r5),r0
+	mov.l	r0,@(36,r4)
+
+	mov.l	@(32,r5),r0
+	mov.l	r0,@(32,r4)
+
+	mov.l	@(28,r5),r0
+	mov.l	r0,@(28,r4)
+
+	mov.l	@(24,r5),r0
+	mov.l	r0,@(24,r4)
+
+	mov.l	@(20,r5),r0
+	mov.l	r0,@(20,r4)
+
+	mov.l	@(16,r5),r0
+	mov.l	r0,@(16,r4)
+
+	mov.l	@(12,r5),r0
+	mov.l	r0,@(12,r4)
+
+	mov.l	@(8,r5),r0
+	mov.l	r0,@(8,r4)
+
+	mov.l	@(4,r5),r0
+	mov.l	r0,@(4,r4)
+
+	mov.l	@(0,r5),r0
+	mov.l	r0,@(0,r4)
+
+	add	#-16,r6
+	cmp/pl	r6
+	bf	done
+
+	add	#64,r5
+	bra	___movstr
+	add	#64,r4
+#endif
+
+#ifdef L_mulsi3
+
+
+	.global	___mulsi3
+
+! r4 =       aabb
+! r5 =       ccdd
+! r0 = aabb*ccdd  via partial products
+!
+! if aa == 0 and cc = 0
+! r0 = bb*dd
+!
+! else
+! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
+!
+
+___mulsi3:
+	mulu    r4,r5		! multiply the lsws  macl=bb*dd
+	mov     r5,r3		! r3 = ccdd
+	swap.w  r4,r2		! r2 = bbaa
+	xtrct   r2,r3		! r3 = aacc
+	tst  	r3,r3		! msws zero ?
+	bf      hiset
+	rts			! yes - then we have the answer
+	sts     macl,r0
+
+hiset:	sts	macl,r0		! r0 = bb*dd
+	mulu	r2,r5		| brewing macl = aa*dd
+	sts	macl,r1
+	mulu	r3,r4		| brewing macl = cc*bb
+	sts	macl,r2
+	add	r1,r2
+	shll16	r2
+	rts
+	add	r2,r0
+
+
+#endif
+#ifdef L_sdivsi3
+	.title "SH DIVIDE"
+!! 4 byte integer Divide code for the Hitachi SH
+!!
+!! Steve Chamberlain
+!! sac@cygnus.com
+!!
+!!
+
+!! args in r4 and r5, result in r0 clobber r1,r2,r3
+
+	.global	___sdivsi3
+___sdivsi3:
+	mov	r4,r1
+	mov	r5,r0
+
+	tst	r0,r0
+	bt	div0
+	mov	#0,r2
+	div0s	r2,r1
+	subc	r3,r3
+	subc	r2,r1
+	div0s	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	div1	r0,r3
+	rotcl	r1
+	addc	r2,r1
+	rts
+	mov	r1,r0
+
+
+div0:	rts
+	mov	#0,r0
+
+#endif
+#ifdef L_udivsi3
+
+	.title "SH DIVIDE"
+!! 4 byte integer Divide code for the Hitachi SH
+!!
+!! Steve Chamberlain
+!! sac@cygnus.com
+!!
+!!
+
+!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
+	.global	___udivsi3
+
+___udivsi3:
+longway:
+	mov	#0,r0
+	div0u
+	! get one bit from the msb of the numerator into the T
+	! bit and divide it by whats in r5.  Put the answer bit
+	! into the T bit so it can come out again at the bottom
+
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+shortway:
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+
+vshortway:
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4 ; div1 r5,r0
+	rotcl	r4
+ret:	rts
+	mov	r4,r0
+
+#endif
diff --git a/gnu/usr.bin/gcc/config/sh/sh.c b/gnu/usr.bin/gcc/config/sh/sh.c
new file mode 100644
index 00000000000..bbb708c10a1
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/sh.c
@@ -0,0 +1,1959 @@
+/* Output routines for GCC for Hitachi Super-H.
+   Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Contributed by Steve Chamberlain (sac@cygnus.com).
+   Improved by Jim Wilson (wilson@cygnus.com).  */
+
+#include "config.h"
+
+#include <stdio.h>
+
+#include "rtl.h"
+#include "tree.h"
+#include "flags.h"
+#include "insn-flags.h"
+#include "expr.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "output.h"
+
+#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
+#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
+
+/* ??? The pragma interrupt support will not work for SH3.  */
+/* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
+   output code for the next function appropriate for an interrupt handler.  */
+int pragma_interrupt;
+
+/* This is set by #pragma trapa, and is similar to the above, except that
+   the compiler doesn't emit code to preserve all registers.  */
+static int pragma_trapa;
+
+/* This is used for communication between SETUP_INCOMING_VARARGS and
+   sh_expand_prologue.  */
+int current_function_anonymous_args;
+
+/* Global variables from toplev.c and final.c that are used within, but
+   not declared in any header file.  */
+extern char *version_string;
+extern int *insn_addresses;
+
+/* Global variables for machine-dependent things. */
+
+/* Which cpu are we scheduling for.  */
+enum processor_type sh_cpu;
+
+/* Saved operands from the last compare to use when we generate an scc
+   or bcc insn.  */
+
+rtx sh_compare_op0;
+rtx sh_compare_op1;
+
+/* Provides the class number of the smallest class containing
+   reg number.  */
+
+int regno_reg_class[FIRST_PSEUDO_REGISTER] =
+{
+  R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+  GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
+  MAC_REGS, MAC_REGS,
+};
+
+/* Provide reg_class from a letter such as appears in the machine
+   description.  */
+
+enum reg_class reg_class_from_letter[] =
+{
+  /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
+  /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
+  /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
+  /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
+  /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
+  /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ MAC_REGS,
+  /* y */ NO_REGS, /* z */ R0_REGS
+};
+
+/* Print the operand address in x to the stream.  */
+
+void
+print_operand_address (stream, x)
+     FILE *stream;
+     rtx x;
+{
+  switch (GET_CODE (x))
+    {
+    case REG:
+      fprintf (stream, "@%s", reg_names[REGNO (x)]);
+      break;
+
+    case PLUS:
+      {
+	rtx base = XEXP (x, 0);
+	rtx index = XEXP (x, 1);
+
+	switch (GET_CODE (index))
+	  {
+	  case CONST_INT:
+	    fprintf (stream, "@(%d,%s)", INTVAL (index),
+		     reg_names[REGNO (base)]);
+	    break;
+
+	  case REG:
+	    fprintf (stream, "@(r0,%s)",
+		     reg_names[MAX (REGNO (base), REGNO (index))]);
+	    break;
+
+	  default:
+	    debug_rtx (x);
+	    abort ();
+	  }
+      }
+      break;
+
+    case PRE_DEC:
+      fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
+      break;
+
+    case POST_INC:
+      fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
+      break;
+
+    default:
+      output_addr_const (stream, x);
+      break;
+    }
+}
+
+/* Print operand x (an rtx) in assembler syntax to file stream
+   according to modifier code.
+
+   '.'  print a .s if insn needs delay slot
+   '@'  print rte or rts depending upon pragma interruptness
+   '#'  output a nop if there is nothing to put in the delay slot
+   'O'  print a constant without the #
+   'R'  print the LSW of a dp value - changes if in little endian
+   'S'  print the MSW of a dp value - changes if in little endian
+   'T'  print the next word of a dp value - same as 'R' in big endian mode.  */
+
+void
+print_operand (stream, x, code)
+     FILE *stream;
+     rtx x;
+     int code;
+{
+  switch (code)
+    {
+    case '.':
+      if (final_sequence
+	  && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+	fprintf (stream, ".s");
+      break;
+    case '@':
+      if (pragma_interrupt)
+	fprintf (stream, "rte");
+      else
+	fprintf (stream, "rts");
+      break;
+    case '#':
+      /* Output a nop if there's nothing in the delay slot.  */
+      if (dbr_sequence_length () == 0)
+	fprintf (stream, "\n\tnop");
+      break;
+    case 'O':
+      output_addr_const (stream, x);
+      break;
+    case 'R':
+      fputs (reg_names[REGNO (x) + LSW], (stream));
+      break;
+    case 'S':
+      fputs (reg_names[REGNO (x) + MSW], (stream));
+      break;
+    case 'T':
+      /* Next word of a double.  */
+      switch (GET_CODE (x))
+	{
+	case REG:
+	  fputs (reg_names[REGNO (x) + 1], (stream));
+	  break;
+	case MEM:
+	  print_operand_address (stream,
+				 XEXP (adj_offsettable_operand (x, 4), 0));
+	  break;
+	}
+      break;
+    default:
+      switch (GET_CODE (x))
+	{
+	case REG:
+	  fputs (reg_names[REGNO (x)], (stream));
+	  break;
+	case MEM:
+	  output_address (XEXP (x, 0));
+	  break;
+	default:
+	  fputc ('#', stream);
+	  output_addr_const (stream, x);
+	  break;
+	}
+      break;
+    }
+}
+
+/* Emit code to perform a block move.  Choose the best method.
+
+   OPERANDS[0] is the destination.
+   OPERANDS[1] is the source.
+   OPERANDS[2] is the size.
+   OPERANDS[3] is the alignment safe to use.  */
+
+int
+expand_block_move (operands)
+     rtx *operands;
+{
+  int align = INTVAL (operands[3]);
+  int constp = (GET_CODE (operands[2]) == CONST_INT);
+  int bytes = (constp ? INTVAL (operands[2]) : 0);
+
+  /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
+     alignment, or if it isn't a multiple of 4 bytes, then fail.  */
+  if (! constp || align < 4 || (bytes % 4 != 0))
+    return 0;
+
+  if (bytes < 64)
+    {
+      char entry[30];
+      tree entry_name;
+      rtx func_addr_rtx;
+      rtx r4 = gen_rtx (REG, SImode, 4);
+      rtx r5 = gen_rtx (REG, SImode, 5);
+
+      sprintf (entry, "__movstrSI%d", bytes);
+      entry_name = get_identifier (entry);
+
+      func_addr_rtx
+	= copy_to_mode_reg (Pmode,
+			    gen_rtx (SYMBOL_REF, Pmode,
+				     IDENTIFIER_POINTER (entry_name)));
+      emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
+      emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
+      emit_insn (gen_block_move_real (func_addr_rtx));
+      return 1;
+    }
+
+  /* This is the same number of bytes as a memcpy call, but to a different
+     less common function name, so this will occasionally use more space.  */
+  if (! TARGET_SMALLCODE)
+    {
+      tree entry_name;
+      rtx func_addr_rtx;
+      int final_switch, while_loop;
+      rtx r4 = gen_rtx (REG, SImode, 4);
+      rtx r5 = gen_rtx (REG, SImode, 5);
+      rtx r6 = gen_rtx (REG, SImode, 6);
+
+      entry_name = get_identifier ("__movstr");
+      func_addr_rtx
+	= copy_to_mode_reg (Pmode,
+			    gen_rtx (SYMBOL_REF, Pmode,
+				     IDENTIFIER_POINTER (entry_name)));
+      emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
+      emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
+
+      /* r6 controls the size of the move.  16 is decremented from it
+	 for each 64 bytes moved.  Then the negative bit left over is used
+	 as an index into a list of move instructions.  e.g., a 72 byte move
+	 would be set up with size(r6) = 14, for one iteration through the
+	 big while loop, and a switch of -2 for the last part.  */
+
+      final_switch = 16 - ((bytes / 4) % 16);
+      while_loop = ((bytes / 4) / 16 - 1) * 16;
+      emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
+      emit_insn (gen_block_lump_real (func_addr_rtx));
+      return 1;
+    }
+
+  return 0;
+}
+
+/* Prepare operands for a move define_expand; specifically, one of the
+   operands must be in a register.  */
+
+int
+prepare_move_operands (operands, mode)
+     rtx operands[];
+     enum machine_mode mode;
+{
+  /* Copy the source to a register if both operands aren't registers.  */
+  if (! reload_in_progress && ! reload_completed
+      && ! register_operand (operands[0], mode)
+      && ! register_operand (operands[1], mode))
+    operands[1] = copy_to_mode_reg (mode, operands[1]);
+
+  return 0;
+}
+
+/* Prepare the operands for an scc instruction; make sure that the
+   compare has been done.  */
+rtx
+prepare_scc_operands (code)
+     enum rtx_code code;
+{
+  rtx t_reg = gen_rtx (REG, SImode, T_REG);
+  enum rtx_code oldcode = code;
+  enum machine_mode mode;
+
+  /* First need a compare insn.  */
+  switch (code)
+    {
+    case NE:
+      /* It isn't possible to handle this case.  */
+      abort ();
+    case LT:
+      code = GT;
+      break;
+    case LE:
+      code = GE;
+      break;
+    case LTU:
+      code = GTU;
+      break;
+    case LEU:
+      code = GEU;
+      break;
+    }
+  if (code != oldcode)
+    {
+      rtx tmp = sh_compare_op0;
+      sh_compare_op0 = sh_compare_op1;
+      sh_compare_op1 = tmp;
+    }
+
+  mode = GET_MODE (sh_compare_op0);
+  if (mode == VOIDmode)
+    mode = GET_MODE (sh_compare_op1);
+
+  sh_compare_op0 = force_reg (mode, sh_compare_op0);
+  if (code != EQ && code != NE
+      && (sh_compare_op1 != const0_rtx
+	  || code == GTU  || code == GEU || code == LTU || code == LEU))
+    sh_compare_op1 = force_reg (mode, sh_compare_op1);
+
+  emit_insn (gen_rtx (SET, VOIDmode, t_reg,
+		      gen_rtx (code, SImode, sh_compare_op0,
+			       sh_compare_op1)));
+
+  return t_reg;
+}
+
+/* Called from the md file, set up the operands of a compare instruction.  */
+
+void
+from_compare (operands, code)
+     rtx *operands;
+     int code;
+{
+  if (code != EQ && code != NE)
+    {
+      /* Force args into regs, since we can't use constants here.  */
+      sh_compare_op0 = force_reg (SImode, sh_compare_op0);
+      if (sh_compare_op1 != const0_rtx
+	  || code == GTU  || code == GEU || code == LTU || code == LEU)
+	sh_compare_op1 = force_reg (SImode, sh_compare_op1);
+    }
+  operands[1] = sh_compare_op0;
+  operands[2] = sh_compare_op1;
+}
+
+/* Functions to output assembly code.  */
+
+/* Return a sequence of instructions to perform DI or DF move.
+
+   Since the SH cannot move a DI or DF in one instruction, we have
+   to take care when we see overlapping source and dest registers.  */
+
+char *
+output_movedouble (insn, operands, mode)
+     rtx insn;
+     rtx operands[];
+     enum machine_mode mode;
+{
+  rtx dst = operands[0];
+  rtx src = operands[1];
+
+  if (GET_CODE (dst) == MEM
+      && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
+    return "mov.l	%T1,%0\n\tmov.l	%1,%0";
+
+  if (register_operand (dst, mode)
+      && register_operand (src, mode))
+    {
+      if (REGNO (src) == MACH_REG)
+	return "sts	mach,%S0\n\tsts	macl,%R0";
+
+      /* When mov.d r1,r2 do r2->r3 then r1->r2;
+         when mov.d r1,r0 do r1->r0 then r2->r1.  */
+
+      if (REGNO (src) + 1 == REGNO (dst))
+	return "mov	%T1,%T0\n\tmov	%1,%0";
+      else
+	return "mov	%1,%0\n\tmov	%T1,%T0";
+    }
+  else if (GET_CODE (src) == CONST_INT)
+    {
+      if (INTVAL (src) < 0)
+	output_asm_insn ("mov	#-1,%S0", operands);
+      else
+	output_asm_insn ("mov	#0,%S0", operands);
+
+      return "mov	%1,%R0";
+    }
+  else if (GET_CODE (src) == MEM)
+    {
+      int ptrreg = -1;
+      int dreg = REGNO (dst);
+      rtx inside = XEXP (src, 0);
+
+      if (GET_CODE (inside) == REG)
+	ptrreg = REGNO (inside);
+      else if (GET_CODE (inside) == SUBREG)
+	ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
+      else if (GET_CODE (inside) == PLUS)
+	{
+	  ptrreg = REGNO (XEXP (inside, 0));
+	  /* ??? A r0+REG address shouldn't be possible here, because it isn't
+	     an offsettable address.  Unfortunately, offsettable addresses use
+	     QImode to check the offset, and a QImode offsettable address
+	     requires r0 for the other operand, which is not currently
+	     supported, so we can't use the 'o' constraint.
+	     Thus we must check for and handle r0+REG addresses here.
+	     We punt for now, since this is likely very rare.  */
+	  if (GET_CODE (XEXP (inside, 1)) == REG)
+	    abort ();
+	}
+      else if (GET_CODE (inside) == LABEL_REF)
+	return "mov.l	%1,%0\n\tmov.l	%1+4,%T0";
+      else if (GET_CODE (inside) == POST_INC)
+	return "mov.l	%1,%0\n\tmov.l	%1,%T0";
+      else
+	abort ();
+
+      /* Work out the safe way to copy.  Copy into the second half first.  */
+      if (dreg == ptrreg)
+	return "mov.l	%T1,%T0\n\tmov.l	%1,%0";
+    }
+
+  return "mov.l	%1,%0\n\tmov.l	%T1,%T0";
+}
+
+/* Print an instruction which would have gone into a delay slot after
+   another instruction, but couldn't because the other instruction expanded
+   into a sequence where putting the slot insn at the end wouldn't work.  */
+
+static void
+print_slot (insn)
+     rtx insn;
+{
+  final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
+
+  INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
+}
+
+/* We can't tell if we need a register as a scratch for the jump
+   until after branch shortening, and then it's too late to allocate a
+   register the 'proper' way.  These instruction sequences are rare
+   anyway, so to avoid always using a reg up from our limited set, we'll
+   grab one when we need one on output.  */
+
+/* ??? Should fix compiler so that using a clobber scratch in jump
+   instructions works, and then this will be unnecessary.  */
+
+char *
+output_far_jump (insn, op)
+     rtx insn;
+     rtx op;
+{
+  rtx thislab = gen_label_rtx ();
+
+  /* Output the delay slot insn first if any.  */
+  if (dbr_sequence_length ())
+    print_slot (final_sequence);
+
+  output_asm_insn ("mov.l	r13,@-r15", 0);
+  output_asm_insn ("mov.l	%O0,r13", &thislab);
+  output_asm_insn ("jmp	@r13", 0);
+  output_asm_insn ("mov.l	@r15+,r13", 0);
+  output_asm_insn (".align	2", 0);
+  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (thislab));
+  output_asm_insn (".long	%O0", &op);
+  return "";
+}
+
+/* Local label counter, used for constants in the pool and inside
+   pattern branches.  */
+
+static int lf = 100;
+
+/* Output code for ordinary branches.  */
+
+char *
+output_branch (logic, insn, operands)
+     int logic;
+     rtx insn;
+     rtx *operands;
+{
+  int label = lf++;
+
+  switch (get_attr_length (insn))
+    {
+    case 2:
+      /* A branch with an unfilled delay slot.  */
+    case 4:
+      /* Simple branch in range -252..+258 bytes */
+      return logic ? "bt%.	%l0" : "bf%.	%l0";
+
+    case 6:
+      /* A branch with an unfilled delay slot.  */
+    case 8:
+      /* Branch in range -4092..+4098 bytes.  */
+      {
+	/* The call to print_slot will clobber the operands.  */
+	rtx op0 = operands[0];
+
+	/* If the instruction in the delay slot is annulled (true), then
+	   there is no delay slot where we can put it now.  The only safe
+	   place for it is after the label.  */
+
+	if (final_sequence)
+	  {
+	    fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
+		     INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
+		     ? "" : ".s", label);
+	    if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+	      print_slot (final_sequence);
+	  }
+	else
+	  fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
+
+	output_asm_insn ("bra	%l0", &op0);
+	fprintf (asm_out_file, "\tnop\n");
+	fprintf (asm_out_file, "LF%d:\n", label);
+
+	if (final_sequence
+	    && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+	  print_slot (final_sequence);
+      }
+      return "";
+
+    case 16:
+      /* A branch with an unfilled delay slot.  */
+    case 18:
+      /* Branches a long way away.  */
+      {
+	/* The call to print_slot will clobber the operands.  */
+	rtx op0 = operands[0];
+
+	/* If the instruction in the delay slot is annulled (true), then
+	   there is no delay slot where we can put it now.  The only safe
+	   place for it is after the label.  */
+
+	if (final_sequence)
+	  {
+	    fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
+		     INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
+		     ? "" : ".s", label);
+	    if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+	      print_slot (final_sequence);
+	  }
+	else
+	  fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
+
+	output_far_jump (insn, op0);
+	fprintf (asm_out_file, "LF%d:\n", label);
+
+	if (final_sequence
+	    && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+	  print_slot (final_sequence);
+      }
+      return "";
+    }
+  return "bad";
+}
+
+/* A copy of the option structure defined in toplev.c.  */
+
+struct option
+{
+  char *string;
+  int *variable;
+  int on_value;
+};
+
+/* Output a single output option string NAME to FILE, without generating
+   lines longer than MAX.  */
+
+static int
+output_option (file, sep, type, name, indent, pos, max)
+     FILE *file;
+     char *sep;
+     char *type;
+     char *name;
+     char *indent;
+     int pos;
+     int max;
+{
+  if (strlen (sep) + strlen (type) + strlen (name) + pos > max)
+    {
+      fprintf (file, indent);
+      return fprintf (file, "%s%s", type, name);
+    }
+  return pos + fprintf (file, "%s%s%s", sep, type, name);
+}
+
+/* A copy of the target_switches variable in toplev.c.  */
+
+static struct
+{
+  char *name;
+  int value;
+} m_options[] = TARGET_SWITCHES;
+
+/* Output all options to the assembly language file.  */
+
+static void
+output_options (file, f_options, f_len, W_options, W_len,
+		pos, max, sep, indent, term)
+     FILE *file;
+     struct option *f_options;
+     struct option *W_options;
+     int f_len, W_len;
+     int pos;
+     int max;
+     char *sep;
+     char *indent;
+     char *term;
+{
+  register int j;
+
+  if (optimize)
+    pos = output_option (file, sep, "-O", "", indent, pos, max);
+  if (write_symbols != NO_DEBUG)
+    pos = output_option (file, sep, "-g", "", indent, pos, max);
+  if (profile_flag)
+    pos = output_option (file, sep, "-p", "", indent, pos, max);
+  if (profile_block_flag)
+    pos = output_option (file, sep, "-a", "", indent, pos, max);
+
+  for (j = 0; j < f_len; j++)
+    if (*f_options[j].variable == f_options[j].on_value)
+      pos = output_option (file, sep, "-f", f_options[j].string,
+			   indent, pos, max);
+
+  for (j = 0; j < W_len; j++)
+    if (*W_options[j].variable == W_options[j].on_value)
+      pos = output_option (file, sep, "-W", W_options[j].string,
+			   indent, pos, max);
+
+  for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
+    if (m_options[j].name[0] != '\0'
+	&& m_options[j].value > 0
+	&& ((m_options[j].value & target_flags)
+	    == m_options[j].value))
+      pos = output_option (file, sep, "-m", m_options[j].name,
+			   indent, pos, max);
+
+  fprintf (file, term);
+}
+
+/* Output to FILE the start of the assembler file.  */
+
+void
+output_file_start (file, f_options, f_len, W_options, W_len)
+     FILE *file;
+     struct option *f_options;
+     struct option *W_options;
+     int f_len, W_len;
+{
+  register int pos;
+
+  output_file_directive (file, main_input_filename);
+
+  /* Switch to the data section so that the coffsem symbol and the
+     gcc2_compiled. symbol aren't in the text section.  */
+  data_section ();
+
+  pos = fprintf (file, "\n! Hitachi SH cc1 (%s) arguments:", version_string);
+  output_options (file, f_options, f_len, W_options, W_len,
+		  pos, 75, " ", "\n! ", "\n\n");
+
+  if (TARGET_LITTLE_ENDIAN)
+    fprintf (file, "\t.little\n");
+}
+
+/* Actual number of instructions used to make a shift by N.  */
+static char ashiftrt_insns[] =
+  { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
+
+/* Left shift and logical right shift are the same.  */
+static char shift_insns[]    =
+  { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
+
+/* Individual shift amounts needed to get the above length sequences.
+   One bit right shifts clobber the T bit, so when possible, put one bit
+   shifts in the middle of the sequence, so the ends are eligible for
+   branch delay slots.  */
+static short shift_amounts[32][5] = {
+  {0}, {1}, {2}, {2, 1},
+  {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
+  {8}, {8, 1}, {8, 2}, {8, 1, 2},
+  {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
+  {16}, {16, 1}, {16, 2}, {16, 1, 2},
+  {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
+  {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
+  {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
+
+/* This is used in length attributes in sh.md to help compute the length
+   of arbitrary constant shift instructions.  */
+
+int
+shift_insns_rtx (insn)
+     rtx insn;
+{
+  rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
+  int shift_count = INTVAL (XEXP (set_src, 1));
+  enum rtx_code shift_code = GET_CODE (set_src);
+
+  switch (shift_code)
+    {
+    case ASHIFTRT:
+      return ashiftrt_insns[shift_count];
+    case LSHIFTRT:
+    case ASHIFT:
+      return shift_insns[shift_count];
+    default:
+      abort();
+    }
+}
+
+/* Return the cost of a shift.  */
+
+int
+shiftcosts (x)
+     rtx x;
+{
+  int value = INTVAL (XEXP (x, 1));
+
+  /* If shift by a non constant, then this will be expensive.  */
+  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+    {
+      if (TARGET_SH3)
+	return 2;
+      /* If not an sh3 then we don't even have an instruction for it.  */
+      return 20;
+    }
+
+  /* Otherwise, return the true cost in instructions.  */
+  if (GET_CODE (x) == ASHIFTRT)
+    return ashiftrt_insns[value];
+  else
+    return shift_insns[value];
+}
+
+/* Return the cost of an AND operation.  */
+
+int
+andcosts (x)
+     rtx x;
+{
+  int i;
+
+  /* Anding with a register is a single cycle and instruction.  */
+  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+    return 1;
+
+  i = INTVAL (XEXP (x, 1));
+  /* These constants are single cycle extu.[bw] instructions.  */
+  if (i == 0xff || i == 0xffff)
+    return 1;
+  /* Constants that can be used in an and immediate instruction is a single
+     cycle, but this requires r0, so make it a little more expensive.  */
+  if (CONST_OK_FOR_L (i))
+    return 2;
+  /* Constants that can be loaded with a mov immediate and an and.
+     This case is probably unnecessary.  */
+  if (CONST_OK_FOR_I (i))
+    return 2;
+  /* Any other constants requires a 2 cycle pc-relative load plus an and.
+     This case is probably unnecessary.  */
+  return 3;
+}
+
+/* Return the cost of a multiply.  */
+int
+multcosts (x)
+     rtx x;
+{
+  if (TARGET_SH2)
+    {
+      /* We have a mul insn, so we can never take more than the mul and the
+	 read of the mac reg, but count more because of the latency and extra
+	 reg usage.  */
+      if (TARGET_SMALLCODE)
+	return 2;
+      return 3;
+    }
+
+  /* If we're aiming at small code, then just count the number of
+     insns in a multiply call sequence.  */
+  if (TARGET_SMALLCODE)
+    return 5;
+
+  /* Otherwise count all the insns in the routine we'd be calling too.  */
+  return 20;
+}
+
+/* Code to expand a shift.  */
+
+void
+gen_ashift (type, n, reg)
+     int type;
+     int n;
+     rtx reg;
+{
+  /* Negative values here come from the shift_amounts array.  */
+  if (n < 0)
+    {
+      if (type == ASHIFT)
+	type = LSHIFTRT;
+      else
+	type = ASHIFT;
+      n = -n;
+    }
+
+  switch (type)
+    {
+    case ASHIFTRT:
+      emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
+      break;
+    case LSHIFTRT:
+      if (n == 1)
+	emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
+      else
+	emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
+      break;
+    case ASHIFT:
+      emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
+      break;
+    }
+}
+
+/* Output RTL to split a constant shift into its component SH constant
+   shift instructions.  */
+   
+/* ??? For SH3, should reject constant shifts when slower than loading the
+   shift count into a register?  */
+
+int
+gen_shifty_op (code, operands)
+     int code;
+     rtx *operands;
+{
+  int value = INTVAL (operands[2]);
+  int max, i;
+
+  if (value == 31)
+    {
+      if (code == LSHIFTRT)
+	{
+	  emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
+	  emit_insn (gen_movt (operands[0]));
+	  return;
+	}
+      else if (code == ASHIFT)
+	{
+	  /* There is a two instruction sequence for 31 bit left shifts,
+	     but it requires r0.  */
+	  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
+	    {
+	      emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
+	      emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
+	      return;
+	    }
+	}
+    }
+
+  max = shift_insns[value];
+  for (i = 0; i < max; i++)
+    gen_ashift (code, shift_amounts[value][i], operands[0]);
+}
+
+/* Output RTL for an arithmetic right shift.  */
+
+/* ??? Rewrite to use super-optimizer sequences.  */
+
+int
+expand_ashiftrt (operands)
+     rtx *operands;
+{
+  rtx wrk;
+  char func[18];
+  tree func_name;
+  int value;
+
+  if (TARGET_SH3 && GET_CODE (operands[2]) != CONST_INT)
+    {
+      rtx count = copy_to_mode_reg (SImode, operands[2]);
+      emit_insn (gen_negsi2 (count, count));
+      emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
+      return 1;
+    }
+  if (GET_CODE (operands[2]) != CONST_INT)
+    return 0;
+
+  value = INTVAL (operands[2]);
+
+  if (value == 31)
+    {
+      emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
+      return 1;
+    }
+  else if (value >= 16 && value <= 19)
+    {
+      wrk = gen_reg_rtx (SImode);
+      emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
+      value -= 16;
+      while (value--)
+	gen_ashift (ASHIFTRT, 1, wrk);
+      emit_move_insn (operands[0], wrk);
+      return 1;
+    }
+  /* Expand a short sequence inline, longer call a magic routine.  */
+  else if (value <= 5)
+    {
+      wrk = gen_reg_rtx (SImode);
+      emit_move_insn (wrk, operands[1]);
+      while (value--)
+	gen_ashift (ASHIFTRT, 1, wrk);
+      emit_move_insn (operands[0], wrk);
+      return 1;
+    }
+
+  wrk = gen_reg_rtx (Pmode);
+
+  /* Load the value into an arg reg and call a helper.  */
+  emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
+  sprintf (func, "__ashiftrt_r4_%d", value);
+  func_name = get_identifier (func);
+  emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
+				IDENTIFIER_POINTER (func_name)));
+  emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
+  emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
+  return 1;
+}
+
+/* The SH cannot load a large constant into a register, constants have to
+   come from a pc relative load.  The reference of a pc relative load
+   instruction must be less than 1k infront of the instruction.  This
+   means that we often have to dump a constant inside a function, and
+   generate code to branch around it.
+
+   It is important to minimize this, since the branches will slow things
+   down and make things bigger.
+
+   Worst case code looks like:
+
+   mov.l L1,rn
+   bra   L2
+   nop
+   align
+   L1:   .long value
+   L2:
+   ..
+
+   mov.l L3,rn
+   bra   L4
+   nop
+   align
+   L3:   .long value
+   L4:
+   ..
+
+   We fix this by performing a scan before scheduling, which notices which
+   instructions need to have their operands fetched from the constant table
+   and builds the table.
+
+   The algorithm is:
+
+   scan, find an instruction which needs a pcrel move.  Look forward, find the
+   last barrier which is within MAX_COUNT bytes of the requirement.
+   If there isn't one, make one.  Process all the instructions between
+   the find and the barrier.
+
+   In the above example, we can tell that L3 is within 1k of L1, so
+   the first move can be shrunk from the 3 insn+constant sequence into
+   just 1 insn, and the constant moved to L3 to make:
+
+   mov.l        L1,rn
+   ..
+   mov.l        L3,rn
+   bra          L4
+   nop
+   align
+   L3:.long value
+   L4:.long value
+
+   Then the second move becomes the target for the shortening process.  */
+
+typedef struct
+{
+  rtx value;			/* Value in table.  */
+  rtx label;			/* Label of value.  */
+  enum machine_mode mode;	/* Mode of value.  */
+} pool_node;
+
+/* The maximum number of constants that can fit into one pool, since
+   the pc relative range is 0...1020 bytes and constants are at least 4
+   bytes long.  */
+
+#define MAX_POOL_SIZE (1020/4)
+static pool_node pool_vector[MAX_POOL_SIZE];
+static int pool_size;
+
+/* ??? If we need a constant in HImode which is the truncated value of a
+   constant we need in SImode, we could combine the two entries thus saving
+   two bytes.  Is this common enough to be worth the effort of implementing
+   it?  */
+
+/* ??? This stuff should be done at the same time that we shorten branches.
+   As it is now, we must assume that all branches are the maximum size, and
+   this causes us to almost always output constant pools sooner than
+   necessary.  */
+
+/* Add a constant to the pool and return its label.  */
+
+static rtx
+add_constant (x, mode)
+     rtx x;
+     enum machine_mode mode;
+{
+  int i;
+  rtx lab;
+
+  /* First see if we've already got it.  */
+  for (i = 0; i < pool_size; i++)
+    {
+      if (x->code == pool_vector[i].value->code
+	  && mode == pool_vector[i].mode)
+	{
+	  if (x->code == CODE_LABEL)
+	    {
+	      if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
+		continue;
+	    }
+	  if (rtx_equal_p (x, pool_vector[i].value))
+	    return pool_vector[i].label;
+	}
+    }
+
+  /* Need a new one.  */
+  pool_vector[pool_size].value = x;
+  lab = gen_label_rtx ();
+  pool_vector[pool_size].mode = mode;
+  pool_vector[pool_size].label = lab;
+  pool_size++;
+  return lab;
+}
+
+/* Output the literal table.  */
+
+static void
+dump_table (scan)
+     rtx scan;
+{
+  int i;
+  int need_align = 1;
+
+  /* Do two passes, first time dump out the HI sized constants.  */
+
+  for (i = 0; i < pool_size; i++)
+    {
+      pool_node *p = &pool_vector[i];
+
+      if (p->mode == HImode)
+	{
+	  if (need_align)
+	    {
+	      scan = emit_insn_after (gen_align_2 (), scan);
+	      need_align = 0;
+	    }
+	  scan = emit_label_after (p->label, scan);
+	  scan = emit_insn_after (gen_consttable_2 (p->value), scan);
+	}
+    }
+
+  need_align = 1;
+
+  for (i = 0; i < pool_size; i++)
+    {
+      pool_node *p = &pool_vector[i];
+
+      switch (p->mode)
+	{
+	case HImode:
+	  break;
+	case SImode:
+	  if (need_align)
+	    {
+	      need_align = 0;
+	      scan = emit_label_after (gen_label_rtx (), scan);
+	      scan = emit_insn_after (gen_align_4 (), scan);
+	    }
+	  scan = emit_label_after (p->label, scan);
+	  scan = emit_insn_after (gen_consttable_4 (p->value), scan);
+	  break;
+	case DImode:
+	  if (need_align)
+	    {
+	      need_align = 0;
+	      scan = emit_label_after (gen_label_rtx (), scan);
+	      scan = emit_insn_after (gen_align_4 (), scan);
+	    }
+	  scan = emit_label_after (p->label, scan);
+	  scan = emit_insn_after (gen_consttable_8 (p->value), scan);
+	  break;
+	default:
+	  abort ();
+	  break;
+	}
+    }
+
+  scan = emit_insn_after (gen_consttable_end (), scan);
+  scan = emit_barrier_after (scan);
+  pool_size = 0;
+}
+
+/* Return non-zero if constant would be an ok source for a
+   mov.w instead of a mov.l.  */
+
+static int
+hi_const (src)
+     rtx src;
+{
+  return (GET_CODE (src) == CONST_INT
+	  && INTVAL (src) >= -32768
+	  && INTVAL (src) <= 32767);
+}
+
+/* Non-zero if the insn is a move instruction which needs to be fixed.  */
+
+/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
+   CONST_DOUBLE input value is CONST_OK_FOR_I.  For a SFmode move, we don't
+   need to fix it if the input value is CONST_OK_FOR_I.  */
+
+static int
+broken_move (insn)
+     rtx insn;
+{
+  if (GET_CODE (insn) == INSN
+      && GET_CODE (PATTERN (insn)) == SET
+      /* We can load any 8 bit value if we don't care what the high
+	 order bits end up as.  */
+      && GET_MODE (SET_DEST (PATTERN (insn))) != QImode
+      && CONSTANT_P (SET_SRC (PATTERN (insn)))
+      && (GET_CODE (SET_SRC (PATTERN (insn))) != CONST_INT
+	  || ! CONST_OK_FOR_I (INTVAL (SET_SRC (PATTERN (insn))))))
+    return 1;
+
+  return 0;
+}
+
+/* Find the last barrier from insn FROM which is close enough to hold the
+   constant pool.  If we can't find one, then create one near the end of
+   the range.  */
+
+/* ??? It would be good to put constant pool tables between a case jump and
+   the jump table.  This fails for two reasons.  First, there is no
+   barrier after the case jump.  This is a bug in the casesi pattern.
+   Second, inserting the table here may break the mova instruction that
+   loads the jump table address, by moving the jump table too far away.
+   We fix that problem by never outputting the constant pool between a mova
+   and its label.  */
+
+static rtx
+find_barrier (from)
+     rtx from;
+{
+  int count_si = 0;
+  int count_hi = 0;
+  int found_hi = 0;
+  int found_si = 0;
+  rtx found_barrier = 0;
+  rtx found_mova = 0;
+
+  /* For HImode: range is 510, add 4 because pc counts from address of
+     second instruction after this one, subtract 2 for the jump instruction
+     that we may need to emit before the table.  This gives 512.
+     For SImode: range is 1020, add 4 because pc counts from address of
+     second instruction after this one, subtract 2 in case pc is 2 byte
+     aligned, subtract 2 for the jump instruction that we may need to emit
+     before the table.  This gives 1020.  */
+  while (from && count_si < 1020 && count_hi < 512)
+    {
+      int inc = get_attr_length (from);
+
+      if (GET_CODE (from) == BARRIER)
+	found_barrier = from;
+
+      if (broken_move (from))
+	{
+	  rtx src = SET_SRC (PATTERN (from));
+
+	  if (hi_const (src))
+	    {
+	      found_hi = 1;
+	      /* We put the short constants before the long constants, so
+		 we must count the length of short constants in the range
+		 for the long constants.  */
+	      /* ??? This isn't optimal, but is easy to do.  */
+	      if (found_si)
+		count_si += 2;
+	    }
+	  else
+	    found_si = 1;
+	}
+
+      if (GET_CODE (from) == INSN
+	  && GET_CODE (PATTERN (from)) == SET
+	  && GET_CODE (SET_SRC (PATTERN (from))) == UNSPEC
+	  && XINT (SET_SRC (PATTERN (from)), 1) == 1)
+	found_mova = from;
+      else if (GET_CODE (from) == JUMP_INSN
+	       && (GET_CODE (PATTERN (from)) == ADDR_VEC
+		   || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
+	found_mova = 0;
+
+      if (found_si)
+	count_si += inc;
+      if (found_hi)
+	count_hi += inc;
+      from = NEXT_INSN (from);
+    }
+
+  /* Insert the constant pool table before the mova instruction, to prevent
+     the mova label reference from going out of range.  */
+  if (found_mova)
+    from = found_mova;
+
+  if (! found_barrier)
+    {
+      /* We didn't find a barrier in time to dump our stuff,
+	 so we'll make one.  */
+      rtx label = gen_label_rtx ();
+
+      /* If we exceeded the range, then we must back up over the last
+	 instruction we looked at.  Otherwise, we just need to undo the
+	 NEXT_INSN at the end of the loop.  */
+      if (count_hi > 512 || count_si > 1020)
+	from = PREV_INSN (PREV_INSN (from));
+      else
+	from = PREV_INSN (from);
+
+      /* Walk back to be just before any jump or label.
+	 Putting it before a label reduces the number of times the branch
+	 around the constant pool table will be hit.  Putting it before
+	 a jump makes it more likely that the bra delay slot will be
+	 filled.  */
+      while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
+	     || GET_CODE (from) == CODE_LABEL)
+	from = PREV_INSN (from);
+
+      from = emit_jump_insn_after (gen_jump (label), from);
+      JUMP_LABEL (from) = label;
+      LABEL_NUSES (label) = 1;
+      found_barrier = emit_barrier_after (from);
+      emit_label_after (label, found_barrier);
+    }
+
+  return found_barrier;
+}
+
+/* Exported to toplev.c.
+
+   Scan the function looking for move instructions which have to be changed to
+   pc-relative loads and insert the literal tables.  */
+
+void
+machine_dependent_reorg (first)
+     rtx first;
+{
+  rtx insn;
+
+  for (insn = first; insn; insn = NEXT_INSN (insn))
+    {
+      if (broken_move (insn))
+	{
+	  rtx scan;
+	  /* Scan ahead looking for a barrier to stick the constant table
+	     behind.  */
+	  rtx barrier = find_barrier (insn);
+
+	  /* Now find all the moves between the points and modify them.  */
+	  for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
+	    {
+	      if (broken_move (scan))
+		{
+		  rtx pat = PATTERN (scan);
+		  rtx src = SET_SRC (pat);
+		  rtx dst = SET_DEST (pat);
+		  enum machine_mode mode = GET_MODE (dst);
+		  rtx lab;
+		  rtx newinsn;
+		  rtx newsrc;
+
+		  if (mode == SImode && hi_const (src))
+		    {
+		      int offset = 0;
+
+		      mode = HImode;
+		      while (GET_CODE (dst) == SUBREG)
+			{
+			  offset += SUBREG_WORD (dst);
+			  dst = SUBREG_REG (dst);
+			}
+		      dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
+		    }
+
+		  lab = add_constant (src, mode);
+		  newsrc = gen_rtx (MEM, mode,
+				    gen_rtx (LABEL_REF, VOIDmode, lab));
+		  RTX_UNCHANGING_P (newsrc) = 1;
+		  newinsn = emit_insn_after (gen_rtx (SET, VOIDmode,
+						      dst, newsrc), scan);
+
+		  delete_insn (scan);
+		  scan = newinsn;
+		}
+	    }
+	  dump_table (barrier);
+	}
+    }
+}
+
+/* Dump out instruction addresses, which is useful for debugging the
+   constant pool table stuff.  */
+
+/* ??? This is unnecessary, and probably should be deleted.  This makes
+   the insn_addresses declaration above unnecessary.  */
+
+/* ??? The addresses printed by this routine for insns are nonsense for
+   insns which are inside of a sequence where none of the inner insns have
+   variable length.  This is because the second pass of shorten_branches
+   does not bother to update them.  */
+
+void
+final_prescan_insn (insn, opvec, noperands)
+     rtx insn;
+     rtx *opvec;
+     int noperands;
+{
+  if (TARGET_DUMPISIZE)
+    fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
+}
+
+/* Dump out any constants accumulated in the final pass.  These will
+   will only be labels.  */
+
+char *
+output_jump_label_table ()
+{
+  int i;
+
+  if (pool_size)
+    {
+      fprintf (asm_out_file, "\t.align 2\n");
+      for (i = 0; i < pool_size; i++)
+	{
+	  pool_node *p = &pool_vector[i];
+
+	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
+				     CODE_LABEL_NUMBER (p->label));
+	  output_asm_insn (".long	%O0", &p->value);
+	}
+      pool_size = 0;
+    }
+
+  return "";
+}
+
+/* A full frame looks like:
+
+   arg-5
+   arg-4
+   [ if current_function_anonymous_args
+   arg-3
+   arg-2
+   arg-1
+   arg-0 ]
+   saved-fp
+   saved-r10
+   saved-r11
+   saved-r12
+   saved-pr
+   local-n
+   ..
+   local-1
+   local-0        <- fp points here.  */
+
+/* Number of bytes pushed for anonymous args, used to pass information
+   between expand_prologue and expand_epilogue.  */
+
+static int extra_push;
+
+/* Adjust the stack and return the number of bytes taken to do it.  */
+
+static void
+output_stack_adjust (size, reg)
+     int size;
+     rtx reg;
+{
+  if (size)
+    {
+      rtx val = GEN_INT (size);
+      rtx insn;
+
+      if (! CONST_OK_FOR_I (size))
+	{
+	  rtx reg = gen_rtx (REG, SImode, 3);
+	  emit_insn (gen_movsi (reg, val));
+	  val = reg;
+	}
+
+      insn = gen_addsi3 (reg, reg, val);
+      emit_insn (insn);
+    }
+}
+
+/* Output RTL to push register RN onto the stack.  */
+
+static void
+push (rn)
+     int rn;
+{
+  rtx x;
+  x = emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
+  REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
+			   gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
+}
+
+/* Output RTL to pop register RN from the stack.  */
+
+static void
+pop (rn)
+     int rn;
+{
+  rtx x;
+  x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
+  REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
+			   gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
+}
+
+/* Generate code to push the regs specified in the mask, and return
+   the number of bytes the insns take.  */
+
+static void
+push_regs (mask)
+     int mask;
+{
+  int i;
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    if (mask & (1 << i))
+      push (i);
+}
+
+/* Work out the registers which need to be saved, both as a mask and a
+   count.
+
+   If doing a pragma interrupt function, then push all regs used by the
+   function, and if we call another function (we can tell by looking at PR),
+   make sure that all the regs it clobbers are safe too.  */
+
+static int
+calc_live_regs (count_ptr)
+     int *count_ptr;
+{
+  int reg;
+  int live_regs_mask = 0;
+  int count = 0;
+
+  for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
+    {
+      if (pragma_interrupt && ! pragma_trapa)
+	{
+	  /* Need to save all the regs ever live.  */
+	  if ((regs_ever_live[reg]
+	       || (call_used_regs[reg] && regs_ever_live[PR_REG]))
+	      && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
+	      && reg != T_REG && reg != GBR_REG)
+	    {
+	      live_regs_mask |= 1 << reg;
+	      count++;
+	    }
+	}
+      else
+	{
+	  /* Only push those regs which are used and need to be saved.  */
+	  if (regs_ever_live[reg] && ! call_used_regs[reg])
+	    {
+	      live_regs_mask |= (1 << reg);
+	      count++;
+	    }
+	}
+    }
+
+  *count_ptr = count;
+  return live_regs_mask;
+}
+
+/* Code to generate prologue and epilogue sequences */
+
+void
+sh_expand_prologue ()
+{
+  int live_regs_mask;
+  int d, i;
+  live_regs_mask = calc_live_regs (&d);
+
+  /* We have pretend args if we had an object sent partially in registers
+     and partially on the stack, e.g. a large structure.  */
+  output_stack_adjust (-current_function_pretend_args_size, stack_pointer_rtx);
+
+  extra_push = 0;
+
+  /* This is set by SETUP_VARARGS to indicate that this is a varargs
+     routine.  Clear it here so that the next function isn't affected.  */
+  if (current_function_anonymous_args)
+    {
+      current_function_anonymous_args = 0;
+
+      /* Push arg regs as if they'd been provided by caller in stack.  */
+      for (i = 0; i < NPARM_REGS; i++)
+	{
+	  int rn = NPARM_REGS + FIRST_PARM_REG - i - 1;
+	  if (i > (NPARM_REGS - current_function_args_info
+		   - current_function_varargs))
+	    break;
+	  push (rn);
+	  extra_push += 4;
+	}
+    }
+  push_regs (live_regs_mask);
+  output_stack_adjust (-get_frame_size (), stack_pointer_rtx);
+
+  if (frame_pointer_needed)
+    emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
+}
+
+void
+sh_expand_epilogue ()
+{
+  int live_regs_mask;
+  int d, i;
+
+  live_regs_mask = calc_live_regs (&d);
+
+  if (frame_pointer_needed)
+    {
+      /* We deliberately make the add dependent on the frame_pointer,
+	 to ensure that instruction scheduling won't move the stack pointer
+	 adjust before instructions reading from the frame.  This can fail
+	 if there is an interrupt which then writes to the stack.  */
+      output_stack_adjust (get_frame_size (), frame_pointer_rtx);
+      emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
+    }
+  else
+    output_stack_adjust (get_frame_size (), stack_pointer_rtx);
+
+  /* Pop all the registers.  */
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      int j = (FIRST_PSEUDO_REGISTER - 1) - i;
+      if (live_regs_mask & (1 << j))
+	pop (j);
+    }
+
+  output_stack_adjust (extra_push + current_function_pretend_args_size,
+		       stack_pointer_rtx);
+}
+
+/* Clear variables at function end.  */
+
+void
+function_epilogue (stream, size)
+     FILE *stream;
+     int size;
+{
+  pragma_interrupt = pragma_trapa = 0;
+}
+
+/* Define the offset between two registers, one to be eliminated, and
+   the other its replacement, at the start of a routine.  */
+
+int
+initial_elimination_offset (from, to)
+     int from;
+     int to;
+{
+  int regs_saved;
+  int total_saved_regs_space;
+  int total_auto_space = get_frame_size ();
+
+  calc_live_regs (&regs_saved);
+  total_saved_regs_space = (regs_saved) * 4;
+
+  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+    return total_saved_regs_space + total_auto_space;
+
+  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    return total_saved_regs_space + total_auto_space;
+
+  /* Initial gap between fp and sp is 0.  */
+  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    return 0;
+
+  abort ();
+}
+
+/* Handle machine specific pragmas to be semi-compatible with Hitachi
+   compiler.  */
+
+int
+handle_pragma (file)
+     FILE *file;
+{
+  int c;
+  char pbuf[200];
+  int psize = 0;
+
+  c = getc (file);
+  while (c == ' ' || c == '\t')
+    c = getc (file);
+
+  if (c == '\n' || c == EOF)
+    return c;
+
+  while (psize < sizeof (pbuf) - 1 && c != '\n')
+    {
+      pbuf[psize++] = c;
+      if (psize == 9 && strncmp (pbuf, "interrupt", 9) == 0)
+	{
+	  pragma_interrupt = 1;
+	  return ' ';
+	}
+      if (psize == 5 && strncmp (pbuf, "trapa", 5) == 0)
+	{
+	  pragma_interrupt = pragma_trapa = 1;
+	  return ' ';
+	}
+      c = getc (file);
+    }
+  return c;
+}
+
+/* Predicates used by the templates.  */
+
+/* Returns 1 if OP is MACL, MACH or PR.  The input must be a REG rtx.
+   Used only in general_movsrc_operand.  */
+
+int
+system_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (REGNO (op))
+    {
+    case PR_REG:
+    case MACL_REG:
+    case MACH_REG:
+      return 1;
+    }
+  return 0;
+}
+
+/* Returns 1 if OP can be source of a simple move operation.
+   Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
+   invalid as are subregs of system registers.  */
+
+int
+general_movsrc_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == MEM)
+    {
+      rtx inside = XEXP (op, 0);
+      if (GET_CODE (inside) == CONST)
+	inside = XEXP (inside, 0);
+
+      if (GET_CODE (inside) == LABEL_REF)
+	return 1;
+
+      if (GET_CODE (inside) == PLUS
+	  && GET_CODE (XEXP (inside, 0)) == LABEL_REF
+	  && GET_CODE (XEXP (inside, 1)) == CONST_INT)
+	return 1;
+
+      /* Only post inc allowed.  */
+      if (GET_CODE (inside) == PRE_DEC)
+	return 0;
+    }
+
+  if ((mode == QImode || mode == HImode)
+      && (GET_CODE (op) == SUBREG
+	  && GET_CODE (XEXP (op, 0)) == REG
+	  && system_reg_operand (XEXP (op, 0), mode)))
+    return 0;
+
+  return general_operand (op, mode);
+}
+
+/* Returns 1 if OP can be a destination of a move.
+   Same as general_operand, but no preinc allowed.  */
+
+int
+general_movdst_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  /* Only pre dec allowed.  */
+  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
+    return 0;
+
+  return general_operand (op, mode);
+}
+
+/* Returns 1 if OP is a normal arithmetic register.  */
+
+int
+arith_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (register_operand (op, mode))
+    {
+      if (GET_CODE (op) == REG)
+	return (REGNO (op) != T_REG
+		&& REGNO (op) != PR_REG
+		&& REGNO (op) != MACH_REG
+		&& REGNO (op) != MACL_REG);
+      return 1;
+    }
+  return 0;
+}
+
+/* Returns 1 if OP is a valid source operand for an arithmetic insn.  */
+
+int
+arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (arith_reg_operand (op, mode))
+    return 1;
+
+  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
+    return 1;
+
+  return 0;
+}
+
+/* Returns 1 if OP is a valid source operand for a compare insn.  */
+
+int
+arith_reg_or_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (arith_reg_operand (op, mode))
+    return 1;
+
+  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
+    return 1;
+
+  return 0;
+}
+
+/* Returns 1 if OP is a valid source operand for a logical operation.  */
+
+int
+logical_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (arith_reg_operand (op, mode))
+    return 1;
+
+  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
+    return 1;
+
+  return 0;
+}
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+rtx
+sh_function_arg (cum, mode, type, named)
+     CUMULATIVE_ARGS cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  if (named)
+    {
+      int rr = (ROUND_REG (cum, mode));
+
+      if (rr < NPARM_REGS)
+	return ((type == 0 || ! TREE_ADDRESSABLE (type))
+		? gen_rtx (REG, mode, FIRST_PARM_REG + rr) : 0);
+    }
+  return 0;
+}
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.
+   Any arg that starts in the first 4 regs but won't entirely fit in them
+   needs partial registers on the SH.  */
+
+int
+sh_function_arg_partial_nregs (cum, mode, type, named)
+     CUMULATIVE_ARGS cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  if (cum < NPARM_REGS)
+    {
+      if ((type == 0 || ! TREE_ADDRESSABLE (type))
+	  && (cum + (mode == BLKmode
+		     ? ROUND_ADVANCE (int_size_in_bytes (type))
+		     : ROUND_ADVANCE (GET_MODE_SIZE (mode))) - NPARM_REGS > 0))
+	return NPARM_REGS - cum;
+    }
+  return 0;
+}
+
+/* Return non-zero if REG is not used after INSN.
+   We assume REG is a reload reg, and therefore does
+   not live past labels or calls or jumps.  */
+int
+reg_unused_after (reg, insn)
+     rtx reg;
+     rtx insn;
+{
+  enum rtx_code code;
+  rtx set;
+
+  /* If the reg is set by this instruction, then it is safe for our
+     case.  Disregard the case where this is a store to memory, since
+     we are checking a register used in the store address.  */
+  set = single_set (insn);
+  if (set && GET_CODE (SET_DEST (set)) != MEM
+      && reg_overlap_mentioned_p (reg, SET_DEST (set)))
+    return 1;
+
+  while (insn = NEXT_INSN (insn))
+    {
+      code = GET_CODE (insn);
+
+#if 0
+      /* If this is a label that existed before reload, then the register
+	 if dead here.  However, if this is a label added by reorg, then
+	 the register may still be live here.  We can't tell the difference,
+	 so we just ignore labels completely.  */
+      if (code == CODE_LABEL)
+	return 1;
+      /* else */
+#endif
+
+      /* If this is a sequence, we must handle them all at once.
+	 We could have for instance a call that sets the target register,
+	 and a insn in a delay slot that uses the register.  In this case,
+	 we must return 0.  */
+      if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
+	{
+	  int i;
+	  int retval = 0;
+
+	  for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
+	    {
+	      rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
+	      rtx set = single_set (this_insn);
+
+	      if (GET_CODE (this_insn) == CALL_INSN)
+		code = CALL_INSN;
+
+	      if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
+		return 0;
+	      if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
+		{
+		  if (GET_CODE (SET_DEST (set)) != MEM)
+		    retval = 1;
+		  else
+		    return 0;
+		}
+	      if (set == 0
+		  && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
+		return 0;
+	    }
+	  if (retval == 1)
+	    return 1;
+	}
+      else if (GET_RTX_CLASS (code) == 'i')
+	{
+	  rtx set = single_set (insn);
+
+	  if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
+	    return 0;
+	  if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
+	    return GET_CODE (SET_DEST (set)) != MEM;
+	  if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
+	    return 0;
+	}
+
+      if (code == CALL_INSN && call_used_regs[REGNO (reg)])
+	return 1;
+    }
+  return 1;
+}
diff --git a/gnu/usr.bin/gcc/config/sh/sh.h b/gnu/usr.bin/gcc/config/sh/sh.h
new file mode 100644
index 00000000000..3b670149722
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/sh.h
@@ -0,0 +1,1448 @@
+/* Definitions of target machine for GNU compiler for Hitachi Super-H.
+   Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
+   Contributed by Steve Chamberlain (sac@cygnus.com).
+   Improved by Jim Wilson (wilson@cygnus.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+#define TARGET_VERSION \
+  fputs (" (Hitachi SH)", stderr);
+
+/* Generate SDB debugging information.  */
+
+#define SDB_DEBUGGING_INFO
+
+/* Output DBX (stabs) debugging information if doing -gstabs.  */
+
+#define DBX_DEBUGGING_INFO
+
+/* Generate SDB debugging information by default.  */
+
+#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
+
+#define SDB_DELIM ";"
+
+#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
+
+#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
+
+#define ASM_SPEC  "%{ml:-little}"
+
+#define LINK_SPEC "%{ml:-m shl}"
+
+/* We can not debug without a frame pointer.  */
+/* #define CAN_DEBUG_WITHOUT_FP */
+
+#define CONDITIONAL_REGISTER_USAGE				\
+  /* Hitachi saves and restores mac registers on call.  */	\
+  if (TARGET_HITACHI)						\
+   {								\
+     call_used_regs[MACH_REG] = 0;				\
+     call_used_regs[MACL_REG] = 0;				\
+  }
+
+/* ??? Need to write documentation for all SH options and add it to the
+   invoke.texi file.  */
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+#define ISIZE_BIT      	(1<<1)
+#define DALIGN_BIT     	(1<<6)
+#define SH0_BIT	       	(1<<7)
+#define SH1_BIT	       	(1<<8)
+#define SH2_BIT	       	(1<<9)
+#define SH3_BIT	       	(1<<10)
+#define SPACE_BIT 	(1<<13)
+#define BIGTABLE_BIT  	(1<<14)
+#define HITACHI_BIT     (1<<22)
+#define PADSTRUCT_BIT  (1<<28)
+#define LITTLE_ENDIAN_BIT (1<<29)
+
+/* Nonzero if we should dump out instruction size info.  */
+#define TARGET_DUMPISIZE  (target_flags & ISIZE_BIT)
+
+/* Nonzero to align doubles on 64 bit boundaries.  */
+#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
+
+/* Nonzero if we should generate code using type 0 insns.  */
+/* ??? Is there such a thing as SH0?  If not, we should delete all
+   references to it.  */
+#define TARGET_SH0 (target_flags & SH0_BIT)
+
+/* Nonzero if we should generate code using type 1 insns.  */
+#define TARGET_SH1 (target_flags & SH1_BIT)
+
+/* Nonzero if we should generate code using type 2 insns.  */
+#define TARGET_SH2 (target_flags & SH2_BIT)
+
+/* Nonzero if we should generate code using type 3 insns.  */
+#define TARGET_SH3 (target_flags & SH3_BIT)
+
+/* Nonzero if we should generate smaller code rather than faster code.  */
+#define TARGET_SMALLCODE   (target_flags & SPACE_BIT)
+
+/* Nonzero to use long jump tables.  */
+#define TARGET_BIGTABLE     (target_flags & BIGTABLE_BIT)
+
+/* Nonzero if using Hitachi's calling convention.  */
+#define TARGET_HITACHI 		(target_flags & HITACHI_BIT)
+
+/* Nonzero if padding structures to a multiple of 4 bytes.  This is
+   incompatible with Hitachi's compiler, and gives unusual structure layouts
+   which confuse programmers.
+   ??? This option is not useful, but is retained in case there are people
+   who are still relying on it.  It may be deleted in the future.  */
+#define TARGET_PADSTRUCT       (target_flags & PADSTRUCT_BIT)
+
+/* Nonzero if generating code for a little endian SH.  */
+#define TARGET_LITTLE_ENDIAN     (target_flags & LITTLE_ENDIAN_BIT)
+
+#define TARGET_SWITCHES  			\
+{ {"0",	        SH0_BIT},			\
+  {"1",	        SH1_BIT},			\
+  {"2",	        SH2_BIT},			\
+  {"3",	        SH3_BIT|SH2_BIT},		\
+  {"3l",        SH3_BIT|SH2_BIT|LITTLE_ENDIAN_BIT},	\
+  {"b",		-LITTLE_ENDIAN_BIT},  		\
+  {"bigtable", 	BIGTABLE_BIT},			\
+  {"dalign",  	DALIGN_BIT},			\
+  {"hitachi",	HITACHI_BIT},			\
+  {"isize", 	ISIZE_BIT},			\
+  {"l",		LITTLE_ENDIAN_BIT},  		\
+  {"padstruct", PADSTRUCT_BIT},    		\
+  {"space", 	SPACE_BIT},			\
+  {"",   	TARGET_DEFAULT} 		\
+}
+
+#define TARGET_DEFAULT  (0)
+
+#define OVERRIDE_OPTIONS 					\
+do {								\
+  sh_cpu = CPU_SH0;						\
+  if (TARGET_SH1)						\
+    sh_cpu = CPU_SH1;						\
+  if (TARGET_SH2)						\
+    sh_cpu = CPU_SH2;						\
+  if (TARGET_SH3)						\
+    sh_cpu = CPU_SH3;						\
+								\
+  /* We *MUST* always define optimize since we *HAVE* to run	\
+     shorten branches to get correct code.  */			\
+  /* ??? This is obsolete, since now shorten branches is no	\
+     longer required by the SH, and is always run once even	\
+     when not optimizing.  Changing this now might be		\
+     confusing though.  */					\
+  optimize = 1;							\
+  flag_delayed_branch = 1;					\
+								\
+  /* But never run scheduling before reload, since that can	\
+     break global alloc, and generates slower code anyway due	\
+     to the pressure on R0.  */					\
+  flag_schedule_insns = 0;					\
+} while (0)
+
+/* Target machine storage layout.  */
+
+/* Define to use software floating point emulator for REAL_ARITHMETIC and
+   decimal <-> binary conversion.  */
+#define REAL_ARITHMETIC
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.  */
+
+#define BITS_BIG_ENDIAN  0
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+
+/* Define this to set the endianness to use in libgcc2.c, which can
+   not depend on target_flags.  */
+#if defined(__LITTLE_ENDIAN__)
+#define LIBGCC2_WORDS_BIG_ENDIAN 0
+#else
+#define LIBGCC2_WORDS_BIG_ENDIAN 1
+#endif
+
+/* Number of bits in an addressable storage unit.  */
+#define BITS_PER_UNIT  8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD  32
+#define MAX_BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD	4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE  32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY  	32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY  32
+
+/* Allocation boundary (in *bits*) for the code of a function.
+   32 bit alignment is faster, because instructions are always fetched as a
+   pair from a longword boundary.  */
+/* ??? Perhaps also define ASM_OUTPUT_ALIGN_CODE and/or ASM_OUTPUT_LOOP_ALIGN
+   so as to align jump targets and/or loops to 4 byte boundaries when not
+   optimizing for space?  */
+#define FUNCTION_BOUNDARY  (TARGET_SMALLCODE ? 16 : 32)
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY  32
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT  (TARGET_ALIGN_DOUBLE ? 64 : 32)
+
+/* The best alignment to use in cases where we have a choice.  */
+#define FASTEST_ALIGNMENT 32
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)	\
+  ((TREE_CODE (EXP) == STRING_CST	\
+    && (ALIGN) < FASTEST_ALIGNMENT)	\
+    ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Number of bits which any structure or union's size must be a
+   multiple of.  Each structure or union's size is rounded up to a
+   multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
+
+/* Set this nonzero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* Standard register usage.  */
+
+/* Register allocation for the Hitachi calling convention:
+
+        r0		arg return
+	r1..r3          scratch
+	r4..r7		args in
+	r8..r13		call saved
+	r14		frame pointer/call saved
+	r15		stack pointer
+	ap		arg pointer (doesn't really exist, always eliminated)
+	pr		subroutine return address
+	t               t bit
+	mach		multiply/accumulate result, high part
+	macl		multiply/accumulate result, low part.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+
+#define AP_REG   16
+#define PR_REG   17
+#define T_REG    18
+#define GBR_REG  19
+#define MACH_REG 20
+#define MACL_REG 21
+#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
+
+#define FIRST_PSEUDO_REGISTER 22
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+
+   Mach register is fixed 'cause it's only 10 bits wide for SH1.
+   It is 32 bits wide for SH2.  */
+
+#define FIXED_REGISTERS  	\
+  { 0,  0,  0,  0, 		\
+    0,  0,  0,  0, 		\
+    0,  0,  0,  0, 		\
+    0,  0,  0,  1, 		\
+    1,  1,  1,  1, 		\
+    1,  1}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+
+#define CALL_USED_REGISTERS 	\
+   { 1,  1,  1,  1,		\
+     1,  1,  1,  1, 		\
+     0,  0,  0,  0,		\
+     0,  0,  0,  1,		\
+     1,  0,  1,  1,		\
+     1,  1}
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On the SH regs are UNITS_PER_WORD bits wide.  */
+
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+   (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   We can allow any mode in any general register.  The special registers
+   only allow SImode.  Don't allow any mode in the PR.  */
+
+#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
+  (SPECIAL_REG (REGNO) ? (MODE) == SImode	\
+   : (REGNO) == PR_REG ? 0			\
+   : 1)
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+  ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* Define this if the program counter is overloaded on a register.  */
+/* #define PC_REGNUM		15*/
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM	15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM	14
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms may be accessed
+   via the stack pointer) in functions that seem suitable.  */
+
+#define FRAME_POINTER_REQUIRED	0
+
+/* Definitions for register eliminations.
+
+   We have two registers that can be eliminated on the SH.  First, the
+   frame pointer register can often be eliminated in favor of the stack
+   pointer register.  Secondly, the argument pointer register can always be
+   eliminated; it is replaced with either the stack or frame pointer.  */
+
+/* This is an array of structures.  Each structure initializes one pair
+   of eliminable registers.  The "from" register number is given first,
+   followed by "to".  Eliminations of the same "from" register are listed
+   in order of preference.  */
+
+#define ELIMINABLE_REGS				\
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM},}
+
+/* Given FROM and TO register numbers, say whether this elimination
+   is allowed.  */
+#define CAN_ELIMINATE(FROM, TO) \
+  (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
+
+/* Define the offset between two registers, one to be eliminated, and the other
+   its replacement, at the start of a routine.  */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+  OFFSET = initial_elimination_offset (FROM, TO)
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM	16
+
+/* Register in which the static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM	13
+
+/* The register in which a struct value address is passed.  */
+
+#define STRUCT_VALUE_REGNUM 2
+
+/* If the structure value address is not passed in a register, define
+   `STRUCT_VALUE' as an expression returning an RTX for the place
+   where the address is passed.  If it returns 0, the address is
+   passed as an "invisible" first argument.  */
+
+/*#define STRUCT_VALUE ((rtx)0)*/
+
+/* Don't default to pcc-struct-return, because we have already specified
+   exactly how to return structures in the RETURN_IN_MEMORY macro.  */
+
+#define DEFAULT_PCC_STRUCT_RETURN 0
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+/* The SH has two sorts of general registers, R0 and the rest.  R0 can
+   be used as the destination of some of the arithmetic ops. There are
+   also some special purpose registers; the T bit register, the
+   Procedure Return Register and the Multiply Accumulate Registers.  */
+
+enum reg_class
+{
+  NO_REGS,
+  R0_REGS,
+  PR_REGS,
+  T_REGS,
+  MAC_REGS,
+  GENERAL_REGS,
+  ALL_REGS,
+  LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES  (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.  */
+#define REG_CLASS_NAMES	\
+{			\
+  "NO_REGS",		\
+  "R0_REGS",		\
+  "PR_REGS",		\
+  "T_REGS",		\
+  "MAC_REGS",		\
+  "GENERAL_REGS",	\
+  "ALL_REGS",		\
+}
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS	\
+{				\
+  0x000000,  /* NO_REGS      */	\
+  0x000001,  /* R0_REGS      */	\
+  0x020000,  /* PR_REGS      */	\
+  0x040000,  /* T_REGS       */	\
+  0x300000,  /* MAC_REGS     */	\
+  0x01FFFF,  /* GENERAL_REGS */	\
+  0x37FFFF   /* ALL_REGS     */	\
+}
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+extern int regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
+
+/* When defined, the compiler allows registers explicitly used in the
+   rtl to be used as spill registers but prevents the compiler from
+   extending the lifetime of these registers.  */
+
+#define SMALL_REGISTER_CLASSES
+
+/* The order in which register should be allocated.  */
+#define REG_ALLOC_ORDER \
+  { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS  R0_REGS
+#define BASE_REG_CLASS	 GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine
+   description.  */
+extern enum reg_class reg_class_from_letter[];
+
+#define REG_CLASS_FROM_LETTER(C) \
+   ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
+
+/* The letters I, J, K, L and M in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+	I: arithmetic operand -127..128, as used in add, sub, etc
+	K: shift operand 1,2,8 or 16
+	L: logical operand 0..255, as used in and, or, etc.
+	M: constant 1
+	N: constant 0  */
+
+#define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
+#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
+#define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>=    0 && ((int)(VALUE)) <= 255)
+#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
+#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
+#define CONST_OK_FOR_LETTER_P(VALUE, C)		\
+     ((C) == 'I' ? CONST_OK_FOR_I (VALUE)	\
+    : (C) == 'K' ? CONST_OK_FOR_K (VALUE)	\
+    : (C) == 'L' ? CONST_OK_FOR_L (VALUE)	\
+    : (C) == 'M' ? CONST_OK_FOR_M (VALUE)	\
+    : (C) == 'N' ? CONST_OK_FOR_N (VALUE)	\
+    : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.
+
+   On SH this is the size of MODE in words.  */
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+     ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define the number of registers that can hold parameters.
+   These three macros are used only in other macro definitions below.  */
+#define NPARM_REGS 4
+#define FIRST_PARM_REG 4
+#define FIRST_RET_REG  0
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/*  Define this macro if the addresses of local variable slots are at
+    negative offsets from the frame pointer.
+
+    The SH only has positive indexes, so grow the frame up.  */
+/* #define FRAME_GROWS_DOWNWARD */
+
+/* Offset from the frame pointer to the first local variable slot to
+   be allocated.  */
+#define STARTING_FRAME_OFFSET  0
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.  */
+#define PUSH_ROUNDING(NPUSHED)  (((NPUSHED) + 3) & ~3)
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL)  0
+
+/* Value is the number of byte of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.
+
+   On the SH, the caller does not pop any of its arguments that were passed
+   on the stack.  */
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)  0
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+#define LIBCALL_VALUE(MODE)	gen_rtx (REG, MODE, FIRST_RET_REG)
+
+/* 1 if N is a possible register number for a function value.
+   On the SH, only r0 can return results.  */
+#define FUNCTION_VALUE_REGNO_P(REGNO)	((REGNO) == FIRST_RET_REG)
+
+/* 1 if N is a possible register number for function argument passing.  */
+
+#define FUNCTION_ARG_REGNO_P(REGNO) \
+  ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On SH, this is a single integer, which is a number of words
+   of arguments scanned so far (including the invisible argument,
+   if any, which holds the structure-value-address).
+   Thus NARGREGS or more means all following args should go on the stack.  */
+
+#define CUMULATIVE_ARGS  int
+
+#define ROUND_ADVANCE(SIZE) \
+  ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Round a register number up to a proper boundary for an arg of mode
+   MODE.
+
+   The SH doesn't care about double alignment, so we only
+   round doubles to even regs when asked to explicitly.  */
+
+#define ROUND_REG(X, MODE) 					\
+  ((TARGET_ALIGN_DOUBLE 					\
+   && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) 		\
+   ? ((X) + ((X) & 1)) : (X))
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On SH, the offset always starts at 0: the first parm reg is always
+   the same reg.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
+  ((CUM) = 0)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be
+   available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) = (ROUND_REG ((CUM), (MODE))			\
+	   + ((MODE) != BLKmode				\
+	      ? ROUND_ADVANCE (GET_MODE_SIZE (MODE))	\
+	      : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On SH the first args are normally in registers
+   and the rest are pushed.  Any arg that starts within the first
+   NPARM_REGS words is at least partially passed in a register unless
+   its data type forbids.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+  sh_function_arg (CUM, MODE, TYPE, NAMED)
+
+extern struct rtx_def *sh_function_arg();
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.
+
+   We sometimes split args.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+  sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
+
+extern int current_function_anonymous_args;
+
+/* Perform any needed actions needed for a function that is receiving a
+   variable number of arguments.  */
+
+#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
+  current_function_anonymous_args = 1;
+
+/* Call the function profiler with a given profile label.  */
+
+#define FUNCTION_PROFILER(STREAM,LABELNO)			\
+{								\
+	fprintf(STREAM, "	trapa	#5\n");			\
+ 	fprintf(STREAM, "	.align	2\n");			\
+	fprintf(STREAM, "	.long	LP%d\n", (LABELNO));	\
+}
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+/* Generate the assembly code for function exit
+   Just dump out any accumulated constant table.  */
+
+#define FUNCTION_EPILOGUE(STREAM, SIZE)  function_epilogue (STREAM, SIZE)
+
+/* Output assembler code for a block containing the constant parts
+   of a trampoline, leaving space for the variable parts.
+
+   On the SH, the trampoline looks like
+   1 0000 D301     		mov.l	l1,r3
+   2 0002 DD02     	   	mov.l	l2,r13
+   3 0004 4D2B     		jmp	@r13
+   4 0006 200B     		or	r0,r0
+   5 0008 00000000 	l1:  	.long   function
+   6 000c 00000000 	l2:	.long   area  */
+#define TRAMPOLINE_TEMPLATE(FILE)  		\
+{						\
+  fprintf ((FILE), "	.word	0xd301\n");	\
+  fprintf ((FILE), "	.word	0xdd02\n");	\
+  fprintf ((FILE), "	.word	0x4d2b\n");	\
+  fprintf ((FILE), "	.word	0x200b\n");	\
+  fprintf ((FILE), "	.long	0\n");		\
+  fprintf ((FILE), "	.long	0\n");		\
+}
+
+/* Length in units of the trampoline for entering a nested function.  */
+#define TRAMPOLINE_SIZE  16
+
+/* Alignment required for a trampoline in units.  */
+#define TRAMPOLINE_ALIGN  4
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
+{									\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)),	\
+		  (CXT));						\
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)),	\
+		  (FNADDR));						\
+}
+
+/* Addressing modes, and classification of registers for them.  */
+#define HAVE_POST_INCREMENT  1
+/*#define HAVE_PRE_INCREMENT   1*/
+/*#define HAVE_POST_DECREMENT  1*/
+#define HAVE_PRE_DECREMENT   1
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+  ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+  ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
+
+/* Maximum number of registers that can appear in a valid memory
+   address.  */
+
+#define MAX_REGS_PER_ADDRESS 2
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)	(GET_CODE (X) == LABEL_REF)
+
+/* Nonzero if the constant value X is a legitimate general operand.  */
+
+/* ??? Should modify this to accept CONST_DOUBLE, and then modify the
+   constant pool table code to fix loads of CONST_DOUBLEs.  If that doesn't
+   work well, then we can at least handle simple CONST_DOUBLEs here
+   such as 0.0.  */
+#define LEGITIMATE_CONSTANT_P(X)	(GET_CODE(X) != CONST_DOUBLE)
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.  */
+
+#define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
+#define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) \
+  (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) \
+  (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+
+/* Nonzero if X/OFFSET is a hard reg that can be used as an index
+   or if X is a pseudo reg.  */
+#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
+  ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) \
+  REGNO_OK_FOR_BASE_P (REGNO (X))
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) \
+  REGNO_OK_FOR_INDEX_P (REGNO (X))
+
+/* Nonzero if X/OFFSET is a hard reg that can be used as an index.  */
+#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
+  (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
+
+#endif
+
+/* The 'Q' constraint is a pc relative load operand.  */
+#define EXTRA_CONSTRAINT_Q(OP)                          		\
+  (GET_CODE (OP) == MEM && 						\
+   ((GET_CODE (XEXP (OP, 0)) == LABEL_REF)				\
+    || (GET_CODE (XEXP (OP, 0)) == CONST                		\
+	&& GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS 			\
+	&& GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF	\
+	&& GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
+
+#define EXTRA_CONSTRAINT(OP, C)		\
+  ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP)	\
+   : 0)
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
+
+#define BASE_REGISTER_RTX_P(X)				\
+  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))	\
+   || (GET_CODE (X) == SUBREG				\
+       && GET_CODE (SUBREG_REG (X)) == REG		\
+       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+
+/* Since this must be r0, which is a single register class, we must check
+   SUBREGs more carefully, to be sure that we don't accept one that extends
+   outside the class.  */
+#define INDEX_REGISTER_RTX_P(X)				\
+  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
+   || (GET_CODE (X) == SUBREG				\
+       && GET_CODE (SUBREG_REG (X)) == REG		\
+       && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
+
+/* Jump to LABEL if X is a valid address RTX.  This must also take
+   REG_OK_STRICT into account when deciding about valid registers, but it uses
+   the above macros so we are in luck.
+
+   Allow  REG
+	  REG+disp
+	  REG+r0
+	  REG++
+	  --REG  */
+
+/* The SH allows a displacement in a QI or HI amode, but only when the
+   other operand is R0. GCC doesn't handle this very well, so we forgo
+   all of that.
+
+   A legitimate index for a QI or HI is 0, SI can be any number 0..63,
+   DI can be any number 0..60.  */
+
+#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL)  			\
+  do {									\
+    if (GET_CODE (OP) == CONST_INT) 					\
+      {									\
+	if (MODE_DISP_OK_4 (OP, MODE))  goto LABEL;		      	\
+	if (MODE_DISP_OK_8 (OP, MODE))  goto LABEL;		      	\
+      }									\
+  } while(0)
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)			\
+{									\
+  if (BASE_REGISTER_RTX_P (X))						\
+    goto LABEL;								\
+  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)	\
+	   && BASE_REGISTER_RTX_P (XEXP (X, 0)))			\
+    goto LABEL;								\
+  else if (GET_CODE (X) == PLUS)					\
+    {									\
+      rtx xop0 = XEXP (X, 0);						\
+      rtx xop1 = XEXP (X, 1);						\
+      if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0))	\
+	GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL);			\
+      if (GET_MODE_SIZE (MODE) <= 4)					\
+	{								\
+	  if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
+	    goto LABEL;							\
+	  if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
+	    goto LABEL;							\
+	}								\
+    }									\
+}
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.  */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)			\
+{									\
+  if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC)		\
+    goto LABEL;								\
+}
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
+
+/* Define this if the tablejump instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+#define CASE_VECTOR_PC_RELATIVE
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR  FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR  TRUNC_DIV_EXPR
+
+/* 'char' is signed by default.  */
+#define DEFAULT_SIGNED_CHAR  1
+
+/* The type of size_t unsigned int.  */
+#define SIZE_TYPE "unsigned int"
+
+#define WCHAR_TYPE "short unsigned int"
+#define WCHAR_TYPE_SIZE 16
+
+/* Don't cse the address of the function being compiled.  */
+/*#define NO_RECURSIVE_FUNCTION_CSE 1*/
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Define if operations between registers always perform the operation
+   on the full register even if a narrower mode is specified.  */
+#define WORD_REGISTER_OPERATIONS
+
+/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
+   will either zero-extend or sign-extend.  The value of this macro should
+   be the code that says which one of the two operations is implicitly
+   done, NIL if none.  */
+#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
+
+/* Define this if zero-extension is slow (more than one real instruction).
+   On the SH, it's only one instruction.  */
+/* #define SLOW_ZERO_EXTEND */
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+
+#define STORE_FLAG_VALUE 1
+
+/* Immediate shift counts are truncated by the output routines (or was it
+   the assembler?).  Shift counts in a register are truncated by SH.  Note
+   that the native compiler puts too large (> 32) immediate shift counts
+   into a register and shifts by the register, letting the SH decide what
+   to do instead of doing that itself.  */
+/* ??? This is defined, but the library routines in lib1funcs.asm do not
+   truncate the shift count.  This may result in incorrect results for
+   unusual cases.  Truncating the shift counts in the library routines would
+   make them faster.  However, the SH3 has hardware shifts that do not
+   truncate, so it appears that we need to leave this undefined for correct
+   SH3 code.  We can still using truncation in the library routines though to
+   make them faster.  */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* All integers have the same format so truncation is easy.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1
+
+/* Define this if addresses of constant functions
+   shouldn't be put through pseudo regs where they can be cse'd.
+   Desirable on machines where ordinary constants are expensive
+   but a CALL with constant address is cheap.  */
+/*#define NO_FUNCTION_CSE 1*/
+
+/* Chars and shorts should be passed as ints.  */
+#define PROMOTE_PROTOTYPES 1
+
+/* The machine modes of pointers and functions.  */
+#define Pmode  SImode
+#define FUNCTION_MODE  Pmode
+
+/* The relative costs of various types of constants.  Note that cse.c defines
+   REG = 1, SUBREG = 2, any node = (2 + sum of subnodes).  */
+
+#define CONST_COSTS(RTX, CODE, OUTER_CODE)	\
+  case CONST_INT:				\
+    if (INTVAL (RTX) == 0)			\
+      return 0;					\
+    else if (CONST_OK_FOR_I (INTVAL (RTX)))	\
+      return 1;					\
+    else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
+	     && CONST_OK_FOR_L (INTVAL (RTX)))	\
+      return 1;					\
+    else					\
+      return 8;					\
+  case CONST: 					\
+  case LABEL_REF:				\
+  case SYMBOL_REF:				\
+    return 5;					\
+  case CONST_DOUBLE:				\
+      return 10;
+
+#define RTX_COSTS(X, CODE, OUTER_CODE)			\
+  case AND:						\
+    return COSTS_N_INSNS (andcosts (X));		\
+  case MULT:						\
+    return COSTS_N_INSNS (multcosts (X));		\
+  case ASHIFT:						\
+  case ASHIFTRT:					\
+  case LSHIFTRT:					\
+    return COSTS_N_INSNS (shiftcosts (X)) ;		\
+  case DIV:						\
+  case UDIV:						\
+  case MOD:						\
+  case UMOD:						\
+    return COSTS_N_INSNS (20);				\
+  case FLOAT:						\
+  case FIX:						\
+    return 100;
+
+/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
+   are actually function calls with some special constraints on arguments
+   and register usage.
+
+   These macros tell reorg that the references to arguments and
+   register clobbers for insns of type sfunc do not appear to happen
+   until after the millicode call.  This allows reorg to put insns
+   which set the argument registers into the delay slot of the millicode
+   call -- thus they act more like traditional CALL_INSNs.
+
+   get_attr_type will try to recognize the given insn, so make sure to
+   filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
+   in particular.  */
+
+#define INSN_SETS_ARE_DELAYED(X) 		\
+  ((GET_CODE (X) == INSN			\
+    && GET_CODE (PATTERN (X)) != SEQUENCE	\
+    && GET_CODE (PATTERN (X)) != USE		\
+    && GET_CODE (PATTERN (X)) != CLOBBER	\
+    && get_attr_type (X) == TYPE_SFUNC))
+
+#define INSN_REFERENCES_ARE_DELAYED(X) 		\
+  ((GET_CODE (X) == INSN			\
+    && GET_CODE (PATTERN (X)) != SEQUENCE	\
+    && GET_CODE (PATTERN (X)) != USE		\
+    && GET_CODE (PATTERN (X)) != CLOBBER	\
+    && get_attr_type (X) == TYPE_SFUNC))
+
+/* Compute extra cost of moving data between one register class
+   and another.
+
+   On the SH it is hard to move into the T reg, but simple to load
+   from it.  */
+
+#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
+	(((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
+
+/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option?  This
+   would be so that people would slow memory systems could generate
+   different code that does fewer memory accesses.  */
+
+/* Assembler output control.  */
+
+/* The text to go at the start of the assembler file.  */
+#define ASM_FILE_START(STREAM) 						\
+  output_file_start (STREAM, f_options,					\
+		     sizeof f_options / sizeof f_options[0],		\
+		     W_options, sizeof W_options / sizeof W_options[0]);
+
+#define ASM_FILE_END(STREAM)
+
+#define ASM_APP_ON  		""
+#define ASM_APP_OFF  		""
+#define FILE_ASM_OP 		"\t.file\n"
+#define IDENT_ASM_OP 		"\t.ident\n"
+
+/* How to change between sections.  */
+
+#define TEXT_SECTION_ASM_OP  		"\t.text"
+#define DATA_SECTION_ASM_OP  		"\t.data"
+#define CTORS_SECTION_ASM_OP 		"\t.section\t.ctors\n"
+#define DTORS_SECTION_ASM_OP 		"\t.section\t.dtors\n"
+#define EXTRA_SECTIONS 			in_ctors, in_dtors
+#define EXTRA_SECTION_FUNCTIONS					\
+void								\
+ctors_section()							\
+{								\
+  if (in_section != in_ctors)					\
+    {								\
+      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);	\
+      in_section = in_ctors;					\
+    }								\
+}								\
+void								\
+dtors_section()							\
+{								\
+  if (in_section != in_dtors)					\
+    {								\
+      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);	\
+      in_section = in_dtors;					\
+    }								\
+}
+
+/* A C statement to output something to the assembler file to switch to section
+   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
+   define this macro in such cases.  */
+
+#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
+   do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
+
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
+   do { ctors_section();  fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
+
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
+   do {  dtors_section();  fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
+
+#undef DO_GLOBAL_CTORS_BODY
+
+#define DO_GLOBAL_CTORS_BODY			\
+{						\
+  typedef (*pfunc)();				\
+  extern pfunc __ctors[];			\
+  extern pfunc __ctors_end[];			\
+  pfunc *p;					\
+  for (p = __ctors_end; p > __ctors; )		\
+    {						\
+      (*--p)();					\
+    }						\
+}
+
+#undef DO_GLOBAL_DTORS_BODY
+#define DO_GLOBAL_DTORS_BODY			\
+{						\
+  typedef (*pfunc)();				\
+  extern pfunc __dtors[];			\
+  extern pfunc __dtors_end[];			\
+  pfunc *p;					\
+  for (p = __dtors; p < __dtors_end; p++)	\
+    {						\
+      (*p)();					\
+    }						\
+}
+
+#define ASM_OUTPUT_REG_PUSH(file, v) \
+  fprintf (file, "\tmov.l	r%s,-@r15\n", v);
+
+#define ASM_OUTPUT_REG_POP(file, v) \
+  fprintf (file, "\tmov.l	@r15+,r%s\n", v);
+
+/* The assembler's names for the registers.  RFP need not always be used as
+   the Real framepointer; it can also be used as a normal general register.
+   Note that the name `fp' is horribly misleading since `fp' is in fact only
+   the argument-and-return-context pointer.  */
+#define REGISTER_NAMES  				\
+{				                   	\
+  "r0", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7", 	\
+  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",	\
+  "ap", "pr", "t",  "gbr", "mach","macl" 		\
+}
+
+/* DBX register number for a given compiler register number.  */
+#define DBX_REGISTER_NUMBER(REGNO)  (REGNO)
+
+/* Output a label definition.  */
+#define ASM_OUTPUT_LABEL(FILE,NAME) \
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", LOG)
+
+/* Output a function label definition.  */
+#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
+    ASM_OUTPUT_LABEL(STREAM, NAME)
+
+/* Output a globalising directive for a label.  */
+#define ASM_GLOBALIZE_LABEL(STREAM,NAME)	\
+  (fprintf (STREAM, "\t.global\t"),		\
+   assemble_name (STREAM, NAME),		\
+   fputc ('\n',STREAM))
+
+/* Output a reference to a label.  */
+#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
+  fprintf (STREAM, "_%s", NAME)
+
+/* Make an internal label into a string.  */
+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
+  sprintf (STRING, "*%s%d", PREFIX, NUM)
+
+/* Output an internal label definition.  */
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE)	    */
+
+/* Construct a private name.  */
+#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER)	\
+  ((OUTVAR) = (char *) alloca (strlen (NAME) + 10),	\
+   sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
+
+/* Jump tables must be 32 bit aligned, no matter the size of the element.  */
+#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
+  fprintf (STREAM, "\t.align 2\n%s%d:\n",  PREFIX, NUM);
+
+/* Output a relative address table.  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL)  			\
+  if (TARGET_BIGTABLE) 							\
+    fprintf (STREAM, "\t.long	L%d-L%d\n", VALUE,REL); 		\
+  else									\
+    fprintf (STREAM, "\t.word	L%d-L%d\n", VALUE,REL); 		\
+
+/* Output an absolute table element.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE)  				\
+  if (TARGET_BIGTABLE) 							\
+    fprintf (STREAM, "\t.long	L%d\n", VALUE); 			\
+  else									\
+    fprintf (STREAM, "\t.word	L%d\n", VALUE); 			\
+
+/* Output various types of constants.  */
+
+/* This is how to output an assembler line defining a `double'.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
+do { char dstr[30];					\
+     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
+     fprintf (FILE, "\t.double %s\n", dstr);		\
+   } while (0)
+
+/* This is how to output an assembler line defining a `float' constant.  */
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
+do { char dstr[30];					\
+     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
+     fprintf (FILE, "\t.float %s\n", dstr);		\
+   } while (0)
+
+#define ASM_OUTPUT_INT(STREAM, EXP)  	\
+  (fprintf (STREAM, "\t.long\t"),      	\
+   output_addr_const (STREAM, (EXP)),  	\
+   fputc ('\n', STREAM))
+
+#define ASM_OUTPUT_SHORT(STREAM, EXP)	\
+  (fprintf (STREAM, "\t.short\t"),	\
+   output_addr_const (STREAM, (EXP)),	\
+   fputc ('\n', STREAM))
+
+#define ASM_OUTPUT_CHAR(STREAM, EXP)  	\
+  (fprintf (STREAM, "\t.byte\t"),      	\
+   output_addr_const (STREAM, (EXP)),  	\
+   fputc ('\n', STREAM))
+
+#define ASM_OUTPUT_BYTE(STREAM, VALUE)  	\
+  fprintf (STREAM, "\t.byte\t%d\n", VALUE)  	\
+
+/* This is how to output an assembler line
+   that says to advance the location counter by SIZE bytes.  */
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE) \
+  fprintf (FILE, "\t.space %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
+( fputs ("\t.comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
+( fputs ("\t.lcomm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* The assembler's parentheses characters.  */
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Target characters.  */
+#define TARGET_BELL	007
+#define TARGET_BS	010
+#define TARGET_TAB	011
+#define TARGET_NEWLINE	012
+#define TARGET_VT	013
+#define TARGET_FF	014
+#define TARGET_CR	015
+
+/* Only perform branch elimination (by making instructions conditional) if
+   we're optimizing.  Otherwise it's of no use anyway.  */
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
+  final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+
+#define PRINT_OPERAND(STREAM, X, CODE)  print_operand (STREAM, X, CODE)
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+#define PRINT_OPERAND_ADDRESS(STREAM,X)  print_operand_address (STREAM, X)
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
+  ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
+
+extern struct rtx_def *sh_compare_op0;
+extern struct rtx_def *sh_compare_op1;
+extern struct rtx_def *prepare_scc_operands();
+
+/* Which processor to schedule for.  The elements of the enumeration must
+   match exactly the cpu attribute in the sh.md file.  */
+
+enum processor_type {
+  PROCESSOR_SH0,
+  PROCESSOR_SH1,
+  PROCESSOR_SH2,
+  PROCESSOR_SH3
+};
+
+#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
+extern enum processor_type sh_cpu;
+
+/* Declare functions defined in sh.c and used in templates.  */
+
+extern char *output_branch();
+extern char *output_shift();
+extern char *output_movedouble();
+extern char *output_movepcrel();
+extern char *output_jump_label_table();
+extern char *output_far_jump();
+
+#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
+
+/* Generate calls to memcpy, memcmp and memset.  */
+
+#define TARGET_MEM_FUNCTIONS
+
+#define HANDLE_PRAGMA(finput) return handle_pragma (finput)
+
+/* Set when processing a function with pragma interrupt turned on.  */
+
+extern int pragma_interrupt;
+
+#define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
+
+/* Instructions with unfilled delay slots take up an extra two bytes for
+   the nop in the delay slot.  */
+
+#define ADJUST_INSN_LENGTH(X, LENGTH)				\
+  if (((GET_CODE (X) == INSN					\
+	&& GET_CODE (PATTERN (X)) != SEQUENCE			\
+	&& GET_CODE (PATTERN (X)) != USE			\
+	&& GET_CODE (PATTERN (X)) != CLOBBER)			\
+       || GET_CODE (X) == CALL_INSN				\
+       || (GET_CODE (X) == JUMP_INSN				\
+	   && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC		\
+	   && GET_CODE (PATTERN (X)) != ADDR_VEC))		\
+      && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES)	\
+   LENGTH += 2;
+
+/* Enable a bug fix for the shorten_branches pass.  */
+#define SHORTEN_WITH_ADJUST_INSN_LENGTH
+
+/* Define the codes that are matched by predicates in sh.c.  */
+#define PREDICATE_CODES \
+  {"arith_reg_operand", {SUBREG, REG}},					\
+  {"arith_operand", {SUBREG, REG, CONST_INT}},				\
+  {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
+  {"logical_operand", {SUBREG, REG, CONST_INT}},			\
+  {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}},		\
+  {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
+
+/* Define this macro if it is advisable to hold scalars in registers
+   in a wider mode than that declared by the program.  In such cases, 
+   the value is constrained to be within the bounds of the declared
+   type, but kept valid in the wider mode.  The signedness of the
+   extension may differ from that of the type.
+
+   Leaving the unsignedp unchanged gives better code than always setting it
+   to 0.  This is despite the fact that we have only signed char and short
+   load instructions.  */
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+  if (GET_MODE_CLASS (MODE) == MODE_INT			\
+      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)		\
+    MODE = SImode;
+
+/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
+   extensions applied to char/short functions arguments.  Defining
+   PROMOTE_FUNCTION_RETURN does the same for function returns.  */
+
+#define PROMOTE_FUNCTION_ARGS
+#define PROMOTE_FUNCTION_RETURN
+
+/* ??? Define ACCUMULATE_OUTGOING_ARGS?  This is more efficient than pushing
+   and poping arguments.  However, we do have push/pop instructions, and
+   rather limited offsets (4 bits) in load/store instructions, so it isn't
+   clear if this would give better code.  If implemented, should check for
+   compatibility problems.  */
+
+/* ??? Define ADJUST_COSTS?  */
+
+/* For the sake of libgcc2.c, indicate target supports atexit.  */
+#define HAVE_ATEXIT
diff --git a/gnu/usr.bin/gcc/config/sh/sh.md b/gnu/usr.bin/gcc/config/sh/sh.md
new file mode 100644
index 00000000000..cfe968e9e33
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/sh.md
@@ -0,0 +1,1943 @@
+;;- Machine description for the Hitachi SH.
+;;  Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
+;;  Contributed by Steve Chamberlain (sac@cygnus.com).
+;;  Improved by Jim Wilson (wilson@cygnus.com).
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+
+;; ??? Should prepend a * to all pattern names which are not used.
+;; This will make the compiler smaller, and rebuilds after changes faster.
+
+;; ??? Should be enhanced to include support for many more GNU superoptimizer
+;; sequences.  Especially the sequences for arithmetic right shifts.
+
+;; ??? Should check all DImode patterns for consistency and usefulness.
+
+;; ??? Should add support for using BSR for short function calls.
+
+;; ??? The MAC.W and MAC.L instructions are not supported.  There is no
+;; way to generate them.
+
+;; ??? The BSR instruction is not supported.  It might be possible to
+;; generate it by keeping track of function sizes (and hence relative
+;; addresses), and then using it only if the target is earlier in the same
+;; file, and is within range.  Better would be assembler/linker relaxing,
+;; but that is much harder.
+
+;; ??? The cmp/str instruction is not supported.  Perhaps it can be used
+;; for a str* inline function.
+
+;; Special constraints for SH machine description:
+;;
+;;    t -- T
+;;    x -- mac
+;;    l -- pr
+;;    z -- r0
+;;
+;; Special formats used for outputting SH instructions:
+;;
+;;   %.  --  print a .s if insn needs delay slot
+;;   %@  --  print rte/rts if is/isn't an interrupt function
+;;   %#  --  output a nop if there is nothing to put in the delay slot
+;;   %O  --  print a constant without the #
+;;   %R  --  print the lsw reg of a double
+;;   %S  --  print the msw reg of a double
+;;   %T  --  print next word of a double REG or MEM
+;;
+;; Special predicates:
+;;
+;;  arith_operand          -- operand is valid source for arithmetic op
+;;  arith_reg_operand      -- operand is valid register for arithmetic op
+;;  general_movdst_operand -- operand is valid move destination
+;;  general_movsrc_operand -- operand is valid move source
+;;  logical_operand        -- operand is valid source for logical op
+;; -------------------------------------------------------------------------
+;; Attributes
+;; -------------------------------------------------------------------------
+
+; Target CPU.
+
+(define_attr "cpu" "sh0,sh1,sh2,sh3"
+  (const (symbol_ref "sh_cpu_attr")))
+
+;;
+;; cbranch	conditional branch instructions
+;; jump		unconditional jumps
+;; arith	ordinary arithmetic
+;; load		from memory
+;; store	to memory
+;; move		register to register
+;; smpy		word precision integer multiply
+;; dmpy		longword or doublelongword precision integer multiply
+;; return	rts
+;; pload	load of pr reg, which can't be put into delay slot of rts
+;; pstore	store of pr reg, which can't be put into delay slot of jsr
+;; pcload	pc relative load of constant value
+;; rte		return from exception
+;; sfunc	special function call with known used registers
+;; call		function call
+
+(define_attr "type"
+ "cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pstore,pcload,rte,sfunc,call"
+  (const_string "other"))
+
+; If a conditional branch destination is within -252..258 bytes away
+; from the instruction it can be 2 bytes long.  Something in the
+; range -4090..4100 bytes can be 6 bytes long.  All other conditional
+; branches are 16 bytes long.
+
+; An unconditional jump in the range -4092..4098 can be 2 bytes long.
+; Otherwise, it must be 14 bytes long.
+
+; All other instructions are two bytes long by default.
+
+; All positive offsets have an adjustment added, which is the number of bytes
+; difference between this instruction length and the next larger instruction
+; length.  This is because shorten_branches starts with the largest
+; instruction size and then tries to reduce them.
+
+(define_attr "length" ""
+  (cond [(eq_attr "type" "cbranch")
+	 (if_then_else (and (ge (minus (match_dup 0) (pc))
+				(const_int -252))
+			    (le (minus (match_dup 0) (pc))
+				(const_int 262)))
+		       (const_int 2)
+		       (if_then_else (and (ge (minus (match_dup 0) (pc))
+					      (const_int -4090))
+					  (le (minus (match_dup 0) (pc))
+					      (const_int 4110)))
+				     (const_int 6)
+				     (const_int 16)))
+
+	 (eq_attr "type" "jump")
+	 (if_then_else (and (ge (minus (match_dup 0) (pc))
+				(const_int -4092))
+			    (le (minus (match_dup 0) (pc))
+				(const_int 4110)))
+		       (const_int 2)
+		       (const_int 14))
+	 ] (const_int 2)))
+
+;; (define_function_unit {name} {num-units} {n-users} {test}
+;;                       {ready-delay} {issue-delay} [{conflict-list}])
+
+;; ??? These are probably not correct.
+(define_function_unit "memory" 1 0 (eq_attr "type" "load,pcload,pload") 2 2)
+(define_function_unit "mpy"    1 0 (eq_attr "type" "smpy") 2 2)
+(define_function_unit "mpy"    1 0 (eq_attr "type" "dmpy") 3 3)
+
+; Definitions for filling branch delay slots.
+
+(define_attr "needs_delay_slot" "yes,no" (const_string "no"))
+
+(define_attr "hit_stack" "yes,no" (const_string "no"))
+
+(define_attr "interrupt_function" "no,yes"
+  (const (symbol_ref "pragma_interrupt")))
+
+(define_attr "in_delay_slot" "yes,no"
+  (cond [(eq_attr "type" "cbranch") (const_string "no")
+	 (eq_attr "type" "pcload") (const_string "no")
+	 (eq_attr "needs_delay_slot" "yes") (const_string "no")
+	 (eq_attr "length" "2") (const_string "yes")
+	 ] (const_string "no")))
+
+(define_delay
+  (eq_attr "needs_delay_slot" "yes")
+  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
+
+;; On the SH and SH2, the rte instruction reads the return pc from the stack,
+;; and thus we can't put a pop instruction in its delay slot.
+;; ??? On the SH3, the rte instruction does not use the stack, so a pop
+;; instruction can go in the delay slot.
+
+;; Since a normal return (rts) implicitly uses the PR register,
+;; we can't allow PR register loads in an rts delay slot.
+
+(define_delay
+  (eq_attr "type" "return")
+  [(and (eq_attr "in_delay_slot" "yes")
+	(ior (and (eq_attr "interrupt_function" "no")
+		  (eq_attr "type" "!pload"))
+	     (and (eq_attr "interrupt_function" "yes")
+		  (eq_attr "hit_stack" "no")))) (nil) (nil)])
+
+;; Since a call implicitly uses the PR register, we can't allow
+;; a PR register store in a jsr delay slot.
+
+(define_delay
+  (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
+  [(and (eq_attr "in_delay_slot" "yes")
+	(eq_attr "type" "!pstore")) (nil) (nil)])
+
+;; Say that we have annulled true branches, since this gives smaller and
+;; faster code when branches are predicted as not taken.
+
+;; ??? Branches which are out-of-range actually have two delay slots,
+;; the first is either always executed or else annulled false, and the
+;; second is always annulled false.  Handling these differently from
+;; in range branches would give better code.
+
+(define_delay
+  (and (eq_attr "type" "cbranch")
+       (eq_attr "cpu" "sh2,sh3"))
+  [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
+
+;; -------------------------------------------------------------------------
+;; SImode signed integer comparisons
+;; -------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(eq:SI (reg:SI 18)
+	       (const_int 1)))]
+  ""
+  "movt	%0")
+
+;; ??? This combiner pattern does not work, because combine does not combine
+;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
+;; defined.  Perhaps use a pseudo-reg for the T bit?
+
+(define_insn ""
+  [(set (reg:SI 18)
+	(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
+		       (match_operand:SI 1 "arith_operand" "L,r"))
+	       (const_int 0)))]
+  ""
+  "tst	%1,%0")
+
+;; ??? Perhaps should only accept reg/constant if the register is reg 0.
+;; That would still allow reload to create cmpi instructions, but would
+;; perhaps allow forcing the constant into a register when that is better.
+;; Probably should use r0 for mem/imm compares, but force constant into a
+;; register for pseudo/imm compares.
+
+(define_insn "cmpeqsi_t"
+  [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
+			   (match_operand:SI 1 "arith_operand" "N,rI,r")))]
+  ""
+  "@
+	tst	%0,%0
+	cmp/eq	%1,%0
+	cmp/eq	%1,%0")
+
+(define_insn "cmpgtsi_t"
+  [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
+			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
+  ""
+  "@
+	cmp/gt	%1,%0
+	cmp/pl	%0")
+
+(define_insn "cmpgesi_t"
+  [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
+			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
+  ""
+  "@
+	cmp/ge	%1,%0
+	cmp/pz	%0")
+
+;; -------------------------------------------------------------------------
+;; SImode unsigned integer comparisons
+;; -------------------------------------------------------------------------
+
+(define_insn "cmpgeusi_t"
+  [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
+			    (match_operand:SI 1 "arith_reg_operand" "r")))]
+  ""
+  "cmp/hs	%1,%0")
+
+(define_insn "cmpgtusi_t"
+  [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
+			    (match_operand:SI 1 "arith_reg_operand" "r")))]
+  ""
+  "cmp/hi	%1,%0")
+
+;; We save the compare operands in the cmpxx patterns and use them when
+;; we generate the branch.
+
+(define_expand "cmpsi"
+  [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
+			     (match_operand:SI 1 "arith_operand" "")))]
+  ""
+  "
+{
+  sh_compare_op0 = operands[0];
+  sh_compare_op1 = operands[1];
+  DONE;
+}")
+
+;; -------------------------------------------------------------------------
+;; Addition instructions
+;; -------------------------------------------------------------------------
+
+;; ??? This should be a define expand.
+
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
+		 (match_operand:DI 2 "arith_reg_operand" "r")))
+   (clobber (reg:SI 18))]
+  ""
+  "clrt\;addc	%R2,%R0\;addc	%S2,%S0"
+  [(set_attr "length" "6")])
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(plus:SI (match_operand:SI 1 "arith_operand" "%0")
+		 (match_operand:SI 2 "arith_operand" "rI")))]
+  ""
+  "add	%2,%0"
+  [(set_attr "type" "arith")])
+
+;; -------------------------------------------------------------------------
+;; Subtraction instructions
+;; -------------------------------------------------------------------------
+
+;; ??? This should be a define expand.
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
+		 (match_operand:DI 2 "arith_reg_operand" "r")))
+   (clobber (reg:SI 18))]
+  ""
+  "clrt\;subc	%R2,%R0\;subc	%S2,%S0"
+  [(set_attr "length" "6")])
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		  (match_operand:SI 2 "arith_reg_operand" "r")))]
+  ""
+  "sub	%2,%0"
+  [(set_attr "type" "arith")])
+
+;; -------------------------------------------------------------------------
+;; Division instructions
+;; -------------------------------------------------------------------------
+
+;; We take advantage of the library routines which don't clobber as many
+;; registers as a normal function call would.
+
+;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
+;; hard register 0.  If we used hard register 0, then the next instruction
+;; would be a move from hard register 0 to a pseudo-reg.  If the pseudo-reg
+;; gets allocated to a stack slot that needs its address reloaded, then
+;; there is nothing to prevent reload from using r0 to reload the address.
+;; This reload would clobber the value in r0 we are trying to store.
+;; If we let reload allocate r0, then this problem can never happen.
+
+(define_insn ""
+  [(set (match_operand:SI 1 "register_operand" "=z")
+	(udiv:SI (reg:SI 4) (reg:SI 5)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 17))
+   (clobber (reg:SI 4))
+   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "udivsi3"
+  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+   (set (match_dup 3) (symbol_ref:SI "__udivsi3"))
+   (parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (udiv:SI (reg:SI 4)
+			    (reg:SI 5)))
+	      (clobber (reg:SI 18))
+	      (clobber (reg:SI 17))
+	      (clobber (reg:SI 4))
+	      (use (match_dup 3))])]
+  ""
+  "operands[3] = gen_reg_rtx(SImode);")
+
+(define_insn ""
+  [(set (match_operand:SI 1 "register_operand" "=z")
+	(div:SI (reg:SI 4) (reg:SI 5)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 17))
+   (clobber (reg:SI 1))
+   (clobber (reg:SI 2))
+   (clobber (reg:SI 3))
+   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "divsi3"
+  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+   (set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
+   (parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (div:SI (reg:SI 4)
+			   (reg:SI 5)))
+	      (clobber (reg:SI 18))
+	      (clobber (reg:SI 17))
+	      (clobber (reg:SI 1))
+	      (clobber (reg:SI 2))
+	      (clobber (reg:SI 3))
+	      (use (match_dup 3))])]
+  ""
+  "operands[3] = gen_reg_rtx(SImode);")
+
+;; -------------------------------------------------------------------------
+;; Multiplication instructions
+;; -------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (reg:SI 21)
+	(mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))
+		 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand" "r"))))]
+  ""
+  "mulu	%2,%1"
+  [(set_attr "type" "smpy")])
+
+(define_insn ""
+  [(set (reg:SI 21)
+	(mult:SI (sign_extend:SI
+		  (match_operand:HI 1 "arith_reg_operand" "r"))
+		 (sign_extend:SI
+		  (match_operand:HI 2 "arith_reg_operand" "r"))))]
+  ""
+  "muls	%2,%1"
+  [(set_attr "type" "smpy")])
+
+(define_expand "mulhisi3"
+  [(set (reg:SI 21)
+	(mult:SI (sign_extend:SI
+		  (match_operand:HI 1 "arith_reg_operand" ""))
+		 (sign_extend:SI
+		  (match_operand:HI 2 "arith_reg_operand" ""))))
+   (set (match_operand:SI 0 "arith_reg_operand" "")
+	(reg:SI 21))]
+  ""
+  "")
+
+(define_expand "umulhisi3"
+  [(set (reg:SI 21)
+	(mult:SI (zero_extend:SI
+		  (match_operand:HI 1 "arith_reg_operand" ""))
+		 (zero_extend:SI
+		  (match_operand:HI 2 "arith_reg_operand" ""))))
+   (set (match_operand:SI 0 "arith_reg_operand" "")
+	(reg:SI 21))]
+  ""
+  "")
+
+;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
+;; a call to a routine which clobbers known registers.
+
+(define_insn ""
+  [(set (match_operand:SI 1 "register_operand" "=z")
+	(mult:SI (reg:SI 4) (reg:SI 5)))
+   (clobber (reg:SI 21))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 17))
+   (clobber (reg:SI 3))
+   (clobber (reg:SI 2))
+   (clobber (reg:SI 1))
+   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "mulsi3_call"
+  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+   (set (match_dup 3) (symbol_ref:SI "__mulsi3"))
+   (parallel[(set (match_operand:SI 0 "register_operand" "")
+		  (mult:SI (reg:SI 4)
+			   (reg:SI 5)))
+	     (clobber (reg:SI 21))
+	     (clobber (reg:SI 18))
+	     (clobber (reg:SI 17))
+	     (clobber (reg:SI 3))
+	     (clobber (reg:SI 2))
+	     (clobber (reg:SI 1))
+	     (use (match_dup 3))])]
+  ""
+  "operands[3] = gen_reg_rtx(SImode);")
+
+(define_insn "mul_l"
+  [(set (reg:SI 21)
+	(mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
+		 (match_operand:SI 1 "arith_reg_operand" "r")))]
+  "TARGET_SH2"
+  "mul.l	%1,%0"
+  [(set_attr "type" "dmpy")])
+
+(define_expand "mulsi3"
+  [(set (reg:SI 21)
+	(mult:SI  (match_operand:SI 1 "arith_reg_operand" "")
+		  (match_operand:SI 2 "arith_reg_operand" "")))
+   (set (match_operand:SI 0 "arith_reg_operand" "")
+	(reg:SI 21))]
+  ""
+  "
+{
+  if (!TARGET_SH2)
+    {
+      FAIL;
+      /* ??? Does this give worse or better code?  */
+      emit_insn (gen_mulsi3_call (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (reg:DI 20)
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+  "TARGET_SH2"
+  "dmuls.l	%2,%1"
+  [(set_attr "type" "dmpy")])
+
+(define_expand "mulsidi3"
+  [(set (reg:DI 20)
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
+   (set (match_operand:DI 0 "arith_reg_operand" "")
+	(reg:DI 20))]
+  "TARGET_SH2"
+  "")
+
+(define_insn ""
+  [(set (reg:DI 20)
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+  "TARGET_SH2"
+  "dmulu.l	%2,%1"
+  [(set_attr "type" "dmpy")])
+
+(define_expand "umulsidi3"
+  [(set (reg:DI 20)
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
+   (set (match_operand:DI 0 "arith_reg_operand" "")
+	(reg:DI 20))]
+  "TARGET_SH2"
+  "")
+
+(define_insn ""
+  [(set (reg:SI 20)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+			       (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))
+		      (const_int 32))))
+   (clobber (reg:SI 21))]
+  "TARGET_SH2"
+  "dmuls.l	%2,%1"
+  [(set_attr "type" "dmpy")])
+
+(define_expand "smulsi3_highpart"
+  [(parallel [(set (reg:SI 20)
+		   (truncate:SI
+		    (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+					  (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
+				 (const_int 32))))
+	      (clobber (reg:SI 21))])
+   (set (match_operand:SI 0 "arith_reg_operand" "")
+	(reg:SI 20))]
+  "TARGET_SH2"
+  "")
+
+(define_insn ""
+  [(set (reg:SI 20)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+			       (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r")))
+		      (const_int 32))))
+   (clobber (reg:SI 21))]
+  "TARGET_SH2"
+  "dmulu.l	%2,%1"
+  [(set_attr "type" "dmpy")])
+
+(define_expand "umulsi3_highpart"
+  [(parallel [(set (reg:SI 20)
+		   (truncate:SI
+		    (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+					  (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
+				 (const_int 32))))
+	      (clobber (reg:SI 21))])
+   (set (match_operand:SI 0 "arith_reg_operand" "")
+	(reg:SI 20))]
+  "TARGET_SH2"
+  "")
+
+;; -------------------------------------------------------------------------
+;; Logical operations
+;; -------------------------------------------------------------------------
+
+(define_insn ""
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
+	(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "r,L")))]
+  ""
+  "and	%2,%0"
+  [(set_attr "type" "arith")])
+
+;; If the constant is 255, then emit a extu.b instruction instead of an
+;; and, since that will give better code.
+
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(and:SI (match_operand:SI 1 "arith_reg_operand" "")
+		(match_operand:SI 2 "logical_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
+    {
+      emit_insn (gen_zero_extendqisi2 (operands[0],
+				       gen_lowpart (QImode, operands[1])));
+      DONE;
+    }
+}")
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
+	(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "r,L")))]
+  ""
+  "or	%2,%0")
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
+	(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
+		(match_operand:SI 2 "logical_operand" "L,r")))]
+  ""
+  "xor	%2,%0"
+  [(set_attr "type" "arith")])
+
+;; -------------------------------------------------------------------------
+;; Shifts and rotates
+;; -------------------------------------------------------------------------
+
+(define_insn "rotlsi3_1"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		   (const_int 1)))
+   (set (reg:SI 18)
+	(lshiftrt:SI (match_dup 1) (const_int 31)))]
+  ""
+  "rotl	%0")
+
+(define_insn "rotlsi3_31"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		   (const_int 31)))
+   (clobber (reg:SI 18))]
+  ""
+  "rotr	%0")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
+		   (const_int 16)))]
+  ""
+  "swap.w	%1,%0")
+
+(define_expand "rotlsi3"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
+		   (match_operand:SI 2 "immediate_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    FAIL;
+
+  if (INTVAL (operands[2]) == 1)
+    {
+      emit_insn (gen_rotlsi3_1 (operands[0], operands[1]));
+      DONE;
+    }
+  else if (INTVAL (operands[2]) == 31)
+    {
+      emit_insn (gen_rotlsi3_31 (operands[0], operands[1]));
+      DONE;
+    }
+  else if (INTVAL (operands[2]) != 16)
+    FAIL;
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
+	(rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
+		   (const_int 8)))]
+  ""
+  "swap.b	%1,%0")
+
+(define_expand "rotlhi3"
+  [(set (match_operand:HI 0 "arith_reg_operand" "")
+	(rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
+		   (match_operand:HI 2 "immediate_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
+    FAIL;
+}")
+
+;;
+;; shift left
+
+(define_insn "ashlsi3_d"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		   (match_operand:SI 2 "arith_reg_operand" "r")))]
+  "TARGET_SH3"
+  "shld	%2,%0")
+
+(define_insn "ashlsi3_k"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
+		   (match_operand:SI 2 "const_int_operand" "M,K")))]
+  "CONST_OK_FOR_K (INTVAL (operands[2]))"
+  "@
+	add	%0,%0
+	shll%O2	%0")
+
+(define_insn "ashlsi3_n"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		   (match_operand:SI 2 "const_int_operand" "n")))
+   (clobber (reg:SI 18))]
+  ""
+  "#"
+  [(set (attr "length")
+	(cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
+	       (const_string "2")
+	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
+	       (const_string "4")
+	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
+	       (const_string "6")]
+	      (const_string "8")))
+   (set_attr "type" "arith")])
+
+(define_split
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
+		   (match_operand:SI 2 "const_int_operand" "n")))
+   (clobber (reg:SI 18))]
+  ""
+  [(use (reg:SI 0))]
+  "
+{
+  gen_shifty_op (ASHIFT, operands);
+  DONE;
+}")
+
+(define_expand "ashlsi3"
+  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
+		   (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
+			      (match_operand:SI 2 "nonmemory_operand" "")))
+	      (clobber (reg:SI 18))])]
+  ""
+  "
+{
+  if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
+    {
+      emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
+    FAIL;
+}")
+
+;
+; arithmetic shift right
+;
+
+(define_insn "ashrsi3_k"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (match_operand:SI 2 "const_int_operand" "M")))
+   (clobber (reg:SI 18))]
+  "INTVAL (operands[2]) == 1"
+  "shar	%0"
+  [(set_attr "type" "arith")])
+
+;; ??? This should be a define expand.
+
+(define_insn "ashrsi2_16"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
+                     (const_int 16)))]
+  ""
+  "swap.w	%1,%0\;exts.w	%0,%0"
+  [(set_attr "length" "4")])
+
+;; ??? This should be a define expand.
+
+(define_insn "ashrsi2_31"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+                     (const_int 31)))
+   (clobber (reg:SI 18))]
+  ""
+  "@
+   shll	%0\;subc	%0,%0"
+  [(set_attr "length" "4")])
+
+(define_insn "ashrsi3_d"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+  "TARGET_SH3"
+  "shad	%2,%1")
+
+(define_insn "ashrsi3_n"
+  [(set (reg:SI 4)
+	(ashiftrt:SI (reg:SI 4)
+		     (match_operand:SI 0 "const_int_operand" "i")))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 17))
+   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
+  ""
+  "jsr	@%1%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "ashrsi3"
+  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
+		   (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
+				(match_operand:SI 2 "nonmemory_operand" "")))
+	      (clobber (reg:SI 18))])]
+  ""
+  "if (expand_ashiftrt (operands)) DONE; else FAIL;")
+
+;; logical shift right
+
+(define_insn "lshrsi3_d"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
+  "TARGET_SH3"
+  "shld	%2,%0")
+
+;;  Only the single bit shift clobbers the T bit.
+
+(define_insn "lshrsi3_m"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (match_operand:SI 2 "const_int_operand" "M")))
+   (clobber (reg:SI 18))]
+  "CONST_OK_FOR_M (INTVAL (operands[2]))"
+  "shlr	%0")
+
+(define_insn "lshrsi3_k"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (match_operand:SI 2 "const_int_operand" "K")))]
+  "CONST_OK_FOR_K (INTVAL (operands[2]))
+   && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
+  "shlr%O2	%0")
+
+(define_insn "lshrsi3_n"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
+		     (match_operand:SI 2 "const_int_operand" "n")))
+   (clobber (reg:SI 18))]
+  ""
+  "#"
+  [(set (attr "length")
+	(cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
+	       (const_string "2")
+	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
+	       (const_string "4")
+	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
+	       (const_string "6")]
+	      (const_string "8")))
+   (set_attr "type" "arith")])
+
+(define_split
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
+		     (match_operand:SI 2 "const_int_operand" "n")))
+   (clobber (reg:SI 18))]
+  ""
+  [(use (reg:SI 0))]
+  "
+{
+  gen_shifty_op (LSHIFTRT, operands);
+  DONE;
+}")
+
+(define_expand "lshrsi3"
+  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
+		   (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
+				(match_operand:SI 2 "nonmemory_operand" "")))
+	      (clobber (reg:SI 18))])]
+  ""
+  "
+{
+  if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
+    {
+      rtx count = copy_to_mode_reg (SImode, operands[2]);
+      emit_insn (gen_negsi2 (count, count));
+      emit_insn (gen_ashlsi3_d (operands[0], operands[1], count));
+      DONE;
+    }
+  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
+    FAIL;
+}")
+
+;; ??? This should be a define expand.
+
+(define_insn "ashldi3_k"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
+		   (const_int 1)))
+   (clobber (reg:SI 18))]
+  ""
+  "shll	%R0\;rotcl	%S0"
+  [(set_attr "length" "4")])
+
+(define_expand "ashldi3"
+  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
+		   (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
+			      (match_operand:DI 2 "immediate_operand" "")))
+	      (clobber (reg:SI 18))])]
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT
+	 || INTVAL (operands[2]) != 1) FAIL;} ")
+
+;; ??? This should be a define expand.
+
+(define_insn "lshrdi3_k"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
+		     (const_int 1)))
+   (clobber (reg:SI 18))]
+  ""
+  "shlr	%S0\;rotcr	%R0"
+  [(set_attr "length" "4")])
+
+(define_expand "lshrdi3"
+  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
+		   (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
+			       (match_operand:DI 2 "immediate_operand" "")))
+	     (clobber (reg:SI 18))])]
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT
+	 || INTVAL (operands[2]) != 1) FAIL;} ")
+
+;; ??? This should be a define expand.
+
+(define_insn "ashrdi3_k"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
+		     (const_int 1)))
+   (clobber (reg:SI 18))]
+  ""
+  "shar	%S0\;rotcr	%R0"
+  [(set_attr "length" "4")])
+
+(define_expand "ashrdi3"
+  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
+		   (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
+				(match_operand:DI 2 "immediate_operand" "")))
+	      (clobber (reg:SI 18))])]
+  ""
+  "{ if (GET_CODE (operands[2]) != CONST_INT
+	 || INTVAL (operands[2]) != 1) FAIL; } ")
+
+;; -------------------------------------------------------------------------
+;; Unary arithmetic
+;; -------------------------------------------------------------------------
+
+(define_insn "negc"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(neg:SI (plus:SI (reg:SI 18)
+			 (match_operand:SI 1 "arith_reg_operand" "r"))))
+   (set (reg:SI 18)
+	(ne:SI (ior:SI (reg:SI 18) (match_dup 1))
+	       (const_int 0)))]
+  ""
+  "negc	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_expand "negdi2"
+  [(set (match_operand:DI 0 "arith_reg_operand" "")
+	(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
+   (clobber (reg:SI 18))]
+  ""
+  "
+{
+  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
+  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+
+  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
+  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+
+  rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
+  rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
+
+  emit_insn (gen_clrt ());
+  emit_insn (gen_negc (low_dst, low_src));
+  emit_insn (gen_negc (high_dst, high_src));
+  DONE;
+}")
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
+  ""
+  "neg	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
+  ""
+  "not	%1,%0"
+  [(set_attr "type" "arith")])
+
+;; -------------------------------------------------------------------------
+;; Zero extension instructions
+;; -------------------------------------------------------------------------
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
+  ""
+  "extu.w	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
+  ""
+  "extu.b	%1,%0"
+  [(set_attr "type" "arith")])
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
+	(zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
+  ""
+  "extu.b	%1,%0"
+  [(set_attr "type" "arith")])
+
+;; -------------------------------------------------------------------------
+;; Sign extension instructions
+;; -------------------------------------------------------------------------
+
+;; ??? This should be a define expand.
+;; ??? Or perhaps it should be dropped?
+
+(define_insn "extendsidi2"
+  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
+	(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
+   (clobber (reg:SI 18))]
+  ""
+  "mov	%1,%S0\;mov	%1,%R0\;shll	%S0\;subc	%S0,%S0"
+  [(set_attr "length" "8")])
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+	(sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
+  ""
+  "@
+	exts.w	%1,%0
+   	mov.w	%1,%0"
+  [(set_attr "type" "arith,load")])
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
+	(sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
+  ""
+  "@
+	exts.b	%1,%0
+	mov.b	%1,%0"
+  [(set_attr "type" "arith,load")])
+
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
+	(sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
+  ""
+  "@
+	exts.b	%1,%0
+	mov.b	%1,%0"
+  [(set_attr "type" "arith,load")])
+
+;; -------------------------------------------------------------------------
+;; Move instructions
+;; -------------------------------------------------------------------------
+
+;; define push and pop so it is easy for sh.c
+
+(define_insn "push"
+  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+	(match_operand:SI 0 "register_operand" "r,l,x"))]
+  ""
+  "@
+	mov.l	%0,@-r15
+	sts.l	%0,@-r15
+	sts.l	%0,@-r15"
+  [(set_attr "type" "store,pstore,store")
+   (set_attr "hit_stack" "yes")])
+
+(define_insn "pop"
+  [(set (match_operand:SI 0 "register_operand" "=r,l,x")
+	(mem:SI (post_inc:SI (reg:SI 15))))]
+  ""
+  "@
+	mov.l	@r15+,%0
+	lds.l	@r15+,%0
+	lds.l	@r15+,%0"
+  [(set_attr "type" "load,pload,load")
+   (set_attr "hit_stack" "yes")])
+
+;; These two patterns can happen as the result of optimization, when
+;; comparisons get simplified to a move of zero or 1 into the T reg.
+;; They don't disappear completely, because the T reg is a fixed hard reg.
+
+(define_insn "clrt"
+  [(set (reg:SI 18) (const_int 0))]
+  ""
+  "clrt")
+
+(define_insn "sett"
+  [(set (reg:SI 18) (const_int 1))]
+  ""
+  "sett")
+
+;; t/z is first, so that it will be preferred over r/r when reloading a move
+;; of a pseudo-reg into the T reg
+(define_insn "movsi_i"
+  [(set (match_operand:SI 0 "general_movdst_operand" "=t,r,r,r,r,r,m,<,xl,xl,r")
+	(match_operand:SI 1 "general_movsrc_operand" "z,Q,rI,m,xl,t,r,xl,r,>,i"))]
+  "register_operand (operands[0], SImode)
+   || register_operand (operands[1], SImode)"
+  "@
+	tst	%1,%1\;rotcl	%1\;xor	#1,%1\;rotcr	%1
+	mov.l	%1,%0
+	mov	%1,%0
+	mov.l	%1,%0
+	sts	%1,%0
+	movt	%0
+	mov.l	%1,%0
+	sts.l	%1,%0
+	lds	%1,%0
+	lds.l	%1,%0
+	fake	%1,%0"
+  [(set_attr "type" "move,pcload,move,load,move,store,store,move,load,move,move")
+   (set_attr "length" "8,*,*,*,*,*,*,*,*,*,*")])
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_movdst_operand" "")
+	(match_operand:SI 1 "general_movsrc_operand" ""))]
+  ""
+  "{ if (prepare_move_operands (operands, SImode)) DONE; }")
+
+(define_insn "movqi_i"
+  [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
+	(match_operand:QI 1 "general_movsrc_operand"  "ri,m,r,t,l,r"))]
+  "arith_reg_operand (operands[0], QImode)
+   || arith_reg_operand (operands[1], QImode)"
+  "@
+	mov	%1,%0
+	mov.b	%1,%0
+	mov.b	%1,%0
+	movt	%0
+	sts	%1,%0
+	lds	%1,%0"
+ [(set_attr "type" "move,load,store,move,move,move")])
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand"  ""))]
+  ""
+  "{ if (prepare_move_operands (operands, QImode)) DONE; }")
+
+(define_insn "movhi_i"
+  [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
+	(match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
+  "arith_reg_operand (operands[0], HImode)
+   || arith_reg_operand (operands[1], HImode)"
+  "@
+	mov.w	%1,%0
+	mov	%1,%0
+	mov.w	%1,%0
+	movt	%0
+	mov.w	%1,%0
+	sts	%1,%0
+	lds	%1,%0
+	fake	%1,%0"
+  [(set_attr "type" "pcload,move,load,move,store,move,move,move")])
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_movdst_operand" "")
+	(match_operand:HI 1 "general_movsrc_operand"  ""))]
+  ""
+  "{ if (prepare_move_operands (operands, HImode)) DONE; }")
+
+;; ??? This should be a define expand.
+
+(define_insn ""
+  [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r")
+	(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,i,x"))]
+  "arith_reg_operand (operands[0], DImode)
+   || arith_reg_operand (operands[1], DImode)"
+  "* return output_movedouble (insn, operands, DImode);"
+  [(set_attr "length" "4")
+   (set_attr "type" "pcload,move,load,store,move,move")])
+
+;; If the output is a register and the input is memory or a register, we have
+;; to be careful and see which word needs to be loaded first.  
+
+(define_split
+  [(set (match_operand:DI 0 "general_movdst_operand" "")
+	(match_operand:DI 1 "general_movsrc_operand" ""))]
+  "reload_completed"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+  "
+{
+  int regno;
+
+  if ((GET_CODE (operands[0]) == MEM
+       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+      || (GET_CODE (operands[1]) == MEM
+	  && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
+    FAIL;
+
+  if (GET_CODE (operands[0]) == REG)
+    regno = REGNO (operands[0]);
+  else if (GET_CODE (operands[0]) == SUBREG)
+    regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
+  else if (GET_CODE (operands[0]) == MEM)
+    regno = -1;
+
+  if (regno == -1
+      || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
+    {
+      operands[2] = operand_subword (operands[0], 0, 0, DImode);
+      operands[3] = operand_subword (operands[1], 0, 0, DImode);
+      operands[4] = operand_subword (operands[0], 1, 0, DImode);
+      operands[5] = operand_subword (operands[1], 1, 0, DImode);
+    }
+  else
+    {
+      operands[2] = operand_subword (operands[0], 1, 0, DImode);
+      operands[3] = operand_subword (operands[1], 1, 0, DImode);
+      operands[4] = operand_subword (operands[0], 0, 0, DImode);
+      operands[5] = operand_subword (operands[1], 0, 0, DImode);
+    }
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+}")
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_movdst_operand" "")
+	(match_operand:DI 1 "general_movsrc_operand" ""))]
+  ""
+  "{ if ( prepare_move_operands (operands, DImode)) DONE; }")
+
+;; ??? This should be a define expand.
+
+(define_insn "movdf_k"
+  [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,m")
+	(match_operand:DF 1 "general_movsrc_operand" "r,m,r"))]
+  "arith_reg_operand (operands[0], DFmode)
+   || arith_reg_operand (operands[1], DFmode)"
+  "* return output_movedouble (insn, operands, DFmode);"
+  [(set_attr "length" "4")
+   (set_attr "type" "move,load,store")])
+
+;; If the output is a register and the input is memory or a register, we have
+;; to be careful and see which word needs to be loaded first.  
+
+(define_split
+  [(set (match_operand:DF 0 "general_movdst_operand" "")
+	(match_operand:DF 1 "general_movsrc_operand" ""))]
+  "reload_completed"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+  "
+{
+  int regno;
+
+  if ((GET_CODE (operands[0]) == MEM
+       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+      || (GET_CODE (operands[1]) == MEM
+	  && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
+    FAIL;
+
+  if (GET_CODE (operands[0]) == REG)
+    regno = REGNO (operands[0]);
+  else if (GET_CODE (operands[0]) == SUBREG)
+    regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
+  else if (GET_CODE (operands[0]) == MEM)
+    regno = -1;
+
+  if (regno == -1
+      || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
+    {
+      operands[2] = operand_subword (operands[0], 0, 0, DFmode);
+      operands[3] = operand_subword (operands[1], 0, 0, DFmode);
+      operands[4] = operand_subword (operands[0], 1, 0, DFmode);
+      operands[5] = operand_subword (operands[1], 1, 0, DFmode);
+    }
+  else
+    {
+      operands[2] = operand_subword (operands[0], 1, 0, DFmode);
+      operands[3] = operand_subword (operands[1], 1, 0, DFmode);
+      operands[4] = operand_subword (operands[0], 0, 0, DFmode);
+      operands[5] = operand_subword (operands[1], 0, 0, DFmode);
+    }
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+}")
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_movdst_operand" "")
+	(match_operand:DF 1 "general_movsrc_operand" ""))]
+  ""
+  "{ if (prepare_move_operands (operands, DFmode)) DONE; }")
+
+(define_insn "movsf_i"
+  [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m,l,r")
+	(match_operand:SF 1 "general_movsrc_operand"  "r,I,m,r,r,l"))]
+  "arith_reg_operand (operands[0], SFmode)
+   || arith_reg_operand (operands[1], SFmode)"
+  "@
+	mov	%1,%0
+	mov	%1,%0
+	mov.l	%1,%0
+	mov.l	%1,%0
+	lds	%1,%0
+	sts	%1,%0"
+  [(set_attr "type" "move,move,load,store,move,move")])
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_movdst_operand" "")
+	(match_operand:SF 1 "general_movsrc_operand" ""))]
+  ""
+  "{ if (prepare_move_operands (operands, SFmode)) DONE; }")
+
+;; ------------------------------------------------------------------------
+;; Define the real conditional branch instructions.
+;; ------------------------------------------------------------------------
+
+(define_insn "branch_true"
+  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
+			   (label_ref (match_operand 0 "" ""))
+			   (pc)))]
+  ""
+  "* return output_branch (1, insn, operands);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "branch_false"
+  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
+			   (label_ref (match_operand 0 "" ""))
+			   (pc)))]
+  ""
+  "* return output_branch (0, insn, operands);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "inverse_branch_true"
+  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 1))
+			   (pc)
+			   (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_branch (0, insn, operands);"
+  [(set_attr "type" "cbranch")])
+
+(define_insn "inverse_branch_false"
+  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 1))
+   			   (pc)
+			   (label_ref (match_operand 0 "" ""))))]
+  ""
+  "* return output_branch (1, insn, operands);"
+  [(set_attr "type" "cbranch")])
+
+;; Conditional branch insns
+
+(define_expand "beq"
+  [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "from_compare (operands, EQ);")
+
+; There is no bne compare, so we reverse the branch arms.
+
+(define_expand "bne"
+  [(set (reg:SI 18) (eq:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "from_compare (operands, NE);")
+
+(define_expand "bgt"
+  [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "from_compare (operands, GT);")
+
+(define_expand "blt"
+  [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "from_compare (operands, LT);")
+
+(define_expand "ble"
+  [(set (reg:SI 18) (gt:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "from_compare (operands, LE);")
+
+(define_expand "bge"
+  [(set (reg:SI 18) (ge:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "from_compare (operands, GE);")
+
+(define_expand "bgtu"
+  [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "from_compare (operands, GTU); ")
+
+(define_expand "bltu"
+  [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+		  (if_then_else (eq (reg:SI 18) (const_int 1))
+				(pc)
+				(label_ref (match_operand 0 "" ""))))]
+  ""
+  "from_compare (operands, LTU);")
+
+(define_expand "bgeu"
+  [(set (reg:SI 18) (geu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "from_compare (operands, GEU);")
+
+(define_expand "bleu"
+  [(set (reg:SI 18) (gtu:SI (match_dup 1) (match_dup 2)))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18) (const_int 1))
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "from_compare (operands, LEU);")
+
+;; ------------------------------------------------------------------------
+;; Jump and linkage insns
+;; ------------------------------------------------------------------------
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+{
+  /* The length is 16 if the delay slot is unfilled.  */
+  if (get_attr_length(insn) >= 14)
+    return output_far_jump(insn, operands[0]);
+  else
+    return   \"bra	%l0%#\";
+}"
+  [(set_attr "type" "jump")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_insn "calli"
+  [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
+	 (match_operand 1 "" ""))
+   (clobber (reg:SI 17))]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "call")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_insn "call_valuei"
+  [(set (match_operand 0 "" "=rf")
+	(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
+	      (match_operand 2 "" "")))
+   (clobber (reg:SI 17))]
+  ""
+  "jsr	@%1%#"
+  [(set_attr "type" "call")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "call"
+  [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
+			    (match_operand 1 "" ""))
+	      (clobber (reg:SI 17))])]
+  ""
+  "operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
+
+(define_expand "call_value"
+  [(parallel [(set (match_operand 0 "arith_reg_operand" "")
+		   (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
+				 (match_operand 2 "" "")))
+	      (clobber (reg:SI 17))])]
+  ""
+  "operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
+
+(define_insn "indirect_jump"
+  [(set (pc)
+	(match_operand:SI 0 "arith_reg_operand" "r"))]
+  ""
+  "jmp	@%0%#"
+  [(set_attr "needs_delay_slot" "yes")])
+
+;; ------------------------------------------------------------------------
+;; Misc insns
+;; ------------------------------------------------------------------------
+
+;; ??? This combiner pattern does not work, because combine does not combine
+;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
+;; defined.  Perhaps use a pseudo-reg for the T bit?
+
+(define_insn "dect"
+  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+		   (plus:SI (match_dup 0)
+			    (const_int -1)))
+	      (set (reg:SI 18)
+		   (eq:SI (plus:SI (match_dup 0) (const_int -1))
+			  (const_int 0)))])]
+  "TARGET_SH2"
+  "dt	%0")
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop")
+
+;; Load address of a label. This is only generated by the casesi expand.
+;; This must use unspec, because this only works immediately before a casesi.
+
+(define_insn "mova"
+  [(set (reg:SI 0)
+	(unspec [(label_ref (match_operand 0 "" ""))] 1))]
+  ""
+  "mova	%O0,r0"
+  [(set_attr "in_delay_slot" "no")])
+
+;; case instruction for switch statements.
+
+;; Operand 0 is index
+;; operand 1 is the minimum bound
+;; operand 2 is the maximum bound - minimum bound + 1
+;; operand 3 is CODE_LABEL for the table;
+;; operand 4 is the CODE_LABEL to go to if index out of range.
+
+;; ??? There should be a barrier after the jump at the end.
+
+(define_expand "casesi"
+  [(set (match_dup 5) (match_operand:SI 0 "arith_reg_operand" ""))
+   (set (match_dup 5) (minus:SI (match_dup 5)
+				(match_operand:SI 1 "arith_operand" "")))
+   (set (reg:SI 18)
+	(gtu:SI (match_dup 5)
+		(match_operand:SI 2 "arith_reg_operand" "")))
+   (set (pc)
+	(if_then_else (eq (reg:SI 18)
+			  (const_int 1))
+		      (label_ref (match_operand 4 "" ""))
+		      (pc)))
+   (set (match_dup 6) (match_dup 5))
+   (set (match_dup 6) (ashift:SI (match_dup 6) (match_dup 7)))
+   (set (reg:SI 0) (unspec [(label_ref (match_operand 3 "" ""))] 1))
+   (parallel [(set (reg:SI 0) (plus:SI (reg:SI 0)
+				       (mem:HI (plus:SI (reg:SI 0)
+							(match_dup 6)))))
+	      (set (match_dup 6) (mem:HI (plus:SI (reg:SI 0) (match_dup 6))))])
+   (set (pc) (reg:SI 0))]
+  ""
+  "
+{
+  operands[1] = copy_to_mode_reg (SImode, operands[1]);
+  operands[2] = copy_to_mode_reg (SImode, operands[2]);
+  operands[5] = gen_reg_rtx (SImode);
+  operands[6] = gen_reg_rtx (SImode);
+  operands[7] = GEN_INT (TARGET_BIGTABLE  ? 2 : 1);
+}")
+
+(define_insn "casesi_worker"
+  [(set (reg:SI 0)
+	(plus:SI (reg:SI 0)
+		 (mem:HI (plus:SI (reg:SI 0)
+				  (match_operand:SI 0 "arith_reg_operand" "+r")))))
+   (set (match_dup 0) (mem:HI (plus:SI (reg:SI 0)
+				       (match_dup 0))))]
+  ""
+  "*
+{
+  if (TARGET_BIGTABLE)
+    return \"mov.l	@(r0,%0),%0\;add	%0,r0\";
+  else
+    return \"mov.w	@(r0,%0),%0\;add	%0,r0\";
+}"
+  [(set_attr "length" "4")])
+
+(define_insn "return"
+  [(return)]
+  "reload_completed"
+  "%@	%#"
+  [(set_attr "type" "return")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_expand "prologue"
+  [(const_int 0)]
+  ""
+  "sh_expand_prologue (); DONE;")
+
+(define_expand "epilogue"
+  [(return)]
+  ""
+  "sh_expand_epilogue ();")
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  ""
+  [(set_attr "length" "0")])
+
+;; ------------------------------------------------------------------------
+;; Scc instructions
+;; ------------------------------------------------------------------------
+
+(define_insn "movt"
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(eq:SI (reg:SI 18) (const_int 1)))]
+  ""
+  "movt	%0")
+
+(define_expand "seq"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (EQ);")
+
+(define_expand "slt"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LT);")
+
+(define_expand "sle"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LE);")
+
+(define_expand "sgt"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GT);")
+
+(define_expand "sge"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GE);")
+
+(define_expand "sgtu"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GTU);")
+
+(define_expand "sltu"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LTU);")
+
+(define_expand "sleu"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (LEU);")
+
+(define_expand "sgeu"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "operands[1] = prepare_scc_operands (GEU);")
+
+(define_expand "sne"
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(match_dup 1))
+   (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))]
+  ""
+  "operands[1] = prepare_scc_operands (EQ);")
+
+;; -------------------------------------------------------------------------
+;; Instructions to cope with inline literal tables
+;; -------------------------------------------------------------------------
+
+; 2 byte integer in line
+
+(define_insn "consttable_2"
+ [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
+ ""
+ "*
+{
+  assemble_integer (operands[0], 2, 1);
+  return \"\";
+}"
+ [(set_attr "length" "2")
+ (set_attr "in_delay_slot" "no")])
+
+; 4 byte integer in line
+
+(define_insn "consttable_4"
+ [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
+ ""
+ "*
+{
+  assemble_integer (operands[0], 4, 1);
+  return \"\";
+}"
+ [(set_attr "length" "4")
+  (set_attr "in_delay_slot" "no")])
+
+; 8 byte integer in line
+
+(define_insn "consttable_8"
+ [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
+ ""
+ "*
+{
+  assemble_integer (operands[0], 8, 1);
+  return \"\";
+}"
+ [(set_attr "length" "8")
+  (set_attr "in_delay_slot" "no")])
+
+; align to a two byte boundary
+
+(define_insn "align_2"
+ [(unspec_volatile [(const_int 0)] 10)]
+ ""
+ ".align 1"
+ [(set_attr "length" "0")
+  (set_attr "in_delay_slot" "no")])
+
+; align to a four byte boundary
+
+(define_insn "align_4"
+ [(unspec_volatile [(const_int 0)] 5)]
+ ""
+ ".align 2"
+ [(set_attr "in_delay_slot" "no")])
+
+; emitted at the end of the literal table, used to emit the
+; 32bit branch labels if needed.
+
+(define_insn "consttable_end"
+  [(unspec_volatile [(const_int 0)] 11)]
+  ""
+  "* return output_jump_label_table ();"
+  [(set_attr "in_delay_slot" "no")])
+
+;; -------------------------------------------------------------------------
+;; Misc
+;; -------------------------------------------------------------------------
+
+;; String/block move insn.
+
+(define_expand "movstrsi"
+  [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
+		   (mem:BLK (match_operand:BLK 1 "" "")))
+	      (use (match_operand:SI 2 "nonmemory_operand" ""))
+	      (use (match_operand:SI 3 "immediate_operand" ""))
+	      (clobber (reg:SI 17))
+	      (clobber (reg:SI 4))
+	      (clobber (reg:SI 5))
+	      (clobber (reg:SI 0))])]
+  ""
+  "
+{
+  if(expand_block_move (operands))
+     DONE;
+  else FAIL;
+}")
+
+(define_insn "block_move_real"
+  [(parallel [(set (mem:BLK (reg:SI 4))
+		   (mem:BLK (reg:SI 5)))
+	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
+	      (clobber (reg:SI 17))
+	      (clobber (reg:SI 0))])]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+(define_insn "block_lump_real"
+  [(parallel [(set (mem:BLK (reg:SI 4))
+		   (mem:BLK (reg:SI 5)))
+	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
+	      (use (reg:SI 6))
+	      (clobber (reg:SI 17))
+	      (clobber (reg:SI 4))
+	      (clobber (reg:SI 5))
+	      (clobber (reg:SI 6))
+	      (clobber (reg:SI 0))])]
+  ""
+  "jsr	@%0%#"
+  [(set_attr "type" "sfunc")
+   (set_attr "needs_delay_slot" "yes")])
+
+;; -------------------------------------------------------------------------
+;; Peepholes
+;; -------------------------------------------------------------------------
+
+;; This matches cases where a stack pointer increment at the start of the
+;; epilogue combines with a stack slot read loading the return value.
+
+(define_peephole
+  [(set (match_operand:SI 0 "arith_reg_operand" "")
+	(mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
+   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
+  "REGNO (operands[1]) != REGNO (operands[0])"
+  "mov.l	@%1+,%0")
+
+;; See the comment on the dt combiner pattern above.
+
+(define_peephole
+  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
+	(plus:SI (match_dup 0)
+		 (const_int -1)))
+   (set (reg:SI 18)
+	(eq:SI (match_dup 0)
+	       (const_int 0)))]
+  "TARGET_SH2"
+  "dt	%0")
+
+;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
+;; to `mov #k,r0; mov.l @(r0,r15),rn'.  These sequences are generated by
+;; reload when the constant is too large for a reg+offset address.
+
+;; ??? We would get much better code if this was done in reload.  This would
+;; require modifying find_reloads_address to recognize that if the constant
+;; is out-of-range for an immediate add, then we get better code by reloading
+;; the constant into a register than by reloading the sum into a register,
+;; since the former is one instruction shorter if the address does not need
+;; to be offsettable.  Unfortunately this does not work, because there is
+;; only one register, r0, that can be used as an index register.  This register
+;; is also the function return value register.  So, if we try to force reload
+;; to use double-reg addresses, then we end up with some instructions that
+;; need to use r0 twice.  The only way to fix this is to change the calling
+;; convention so that r0 is not used to return values.
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (mem:SI (match_dup 0))
+	(match_operand:SI 2 "general_movsrc_operand" ""))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.l	%2,@(%0,%1)")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (match_operand:SI 2 "general_movdst_operand" "")
+	(mem:SI (match_dup 0)))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.l	@(%0,%1),%2")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (mem:HI (match_dup 0))
+	(match_operand:HI 2 "general_movsrc_operand" ""))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.w	%2,@(%0,%1)")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (match_operand:HI 2 "general_movdst_operand" "")
+	(mem:HI (match_dup 0)))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.w	@(%0,%1),%2")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (mem:QI (match_dup 0))
+	(match_operand:QI 2 "general_movsrc_operand" ""))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.b	%2,@(%0,%1)")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (match_operand:QI 2 "general_movdst_operand" "")
+	(mem:QI (match_dup 0)))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.b	@(%0,%1),%2")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (mem:SF (match_dup 0))
+	(match_operand:SF 2 "general_movsrc_operand" ""))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.l	%2,@(%0,%1)")
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
+   (set (match_operand:SF 2 "general_movdst_operand" "")
+
+	(mem:SF (match_dup 0)))]
+  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
+  "mov.l	@(%0,%1),%2")
diff --git a/gnu/usr.bin/gcc/config/sh/t-sh b/gnu/usr.bin/gcc/config/sh/t-sh
new file mode 100644
index 00000000000..e4761b13853
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/t-sh
@@ -0,0 +1,29 @@
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = sh/lib1funcs.asm
+LIB1ASMFUNCS = _ashiftrt _ashiftrt_n _ashiftlt _lshiftrt _movstr \
+  _mulsi3 _sdivsi3 _udivsi3
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so...
+
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
+	echo '#endif' 		>> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
+	echo '#endif' 		>> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+MULTILIB_OPTIONS = ml m2
+MULTILIB_DIRNAMES = ml m2
+MULTILIB_MATCHES = m2=m3
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff --git a/gnu/usr.bin/gcc/config/sh/xm-sh.h b/gnu/usr.bin/gcc/config/sh/xm-sh.h
new file mode 100644
index 00000000000..3d8ef8410b8
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/sh/xm-sh.h
@@ -0,0 +1,44 @@
+/* Configuration for GNU C-compiler for Hitachi SH.
+   Copyright (C) 1993 Free Software Foundation, Inc.
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+
+/* If compiled with GNU C, use the built-in alloca.  */
+#ifdef __GNUC__
+#define alloca __builtin_alloca
+#endif
+
+/* We have the vprintf function.  */
+#define HAVE_VPRINTF 1
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.  */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33