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authorJonathan Gray <jsg@cvs.openbsd.org>2012-10-18 00:54:13 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2012-10-18 00:54:13 +0000
commit3f87f497abcfedd91fbaf9854614cbba4abebe7a (patch)
treefa6c4439f226fee2e49d00fcb21096b2429a113a /gnu
parent3d005fea62b6604db1aca053d8c0a73bafb8c987 (diff)
Add support for stac/clac instructions to manipulate the flag
that controls the behaviour of Intel's Supervisor Mode Access Prevention (SMAP) feature. 'looks correct' miod@ ok deraadt@
Diffstat (limited to 'gnu')
-rw-r--r--gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c2
-rw-r--r--gnu/usr.bin/binutils-2.17/gas/config/tc-i386.h3
-rw-r--r--gnu/usr.bin/binutils-2.17/include/opcode/i386.h4
-rw-r--r--gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c10
-rw-r--r--gnu/usr.bin/binutils/gas/config/tc-i386.c2
-rw-r--r--gnu/usr.bin/binutils/gas/config/tc-i386.h3
-rw-r--r--gnu/usr.bin/binutils/include/opcode/i386.h4
-rw-r--r--gnu/usr.bin/binutils/opcodes/i386-dis.c12
8 files changed, 35 insertions, 5 deletions
diff --git a/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c b/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c
index 3c5551e038c..0967efaca43 100644
--- a/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c
+++ b/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c
@@ -1557,7 +1557,7 @@ md_assemble (line)
{
expressionS *exp;
- if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+ if ((i.tm.cpu_flags & (CpuPNI|CpuSMAP)) && i.operands > 0)
{
/* These Intel Prescott New Instructions have the fixed
operands with an opcode suffix which is coded in the same
diff --git a/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.h b/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.h
index 53f2918eb1b..2317f961322 100644
--- a/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.h
+++ b/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.h
@@ -188,6 +188,7 @@ typedef struct
#define CpuAES 0x400000 /* Intel AES extensions required */
#define CpuPCLMUL 0x800000 /* Intel Carry-less Multiplication extensions */
#define CpuRdRnd 0x1000000 /* Intel Random Number Generator extensions */
+#define CpuSMAP 0x2000000 /* Intel Supervisor Mode Access Prevention */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
@@ -197,7 +198,7 @@ typedef struct
#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI|CpuAES \
- |CpuPCLMUL|CpuRdRnd)
+ |CpuPCLMUL|CpuRdRnd|CpuSMAP)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
diff --git a/gnu/usr.bin/binutils-2.17/include/opcode/i386.h b/gnu/usr.bin/binutils-2.17/include/opcode/i386.h
index 64252154c40..a367b6bd5e2 100644
--- a/gnu/usr.bin/binutils-2.17/include/opcode/i386.h
+++ b/gnu/usr.bin/binutils-2.17/include/opcode/i386.h
@@ -1504,6 +1504,10 @@ static const template i386_optab[] =
/* Intel Random Number Generator extensions */
{"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } },
+/* Intel Supervisor Mode Access Prevention extensions */
+{"clac", 0, 0x0f01, 0xca, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } },
+{"stac", 0, 0x0f01, 0xcb, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } },
+
/* sentinel */
{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
};
diff --git a/gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c b/gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c
index f0db2b45b7f..03fa624070a 100644
--- a/gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c
+++ b/gnu/usr.bin/binutils-2.17/opcodes/i386-dis.c
@@ -5069,6 +5069,16 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
codep++;
}
+ else if (mod == 3 && reg == 1 && rm <= 3)
+ {
+ size_t olen = strlen (obuf);
+ char *p = obuf + olen - 4;
+ if (*codep == 0xca)
+ strcpy (p, "clac");
+ else if (*codep == 0xcb)
+ strcpy (p, "stac");
+ codep++;
+ }
else
OP_M (0, sizeflag);
}
diff --git a/gnu/usr.bin/binutils/gas/config/tc-i386.c b/gnu/usr.bin/binutils/gas/config/tc-i386.c
index acb0463b2e3..207253c94ff 100644
--- a/gnu/usr.bin/binutils/gas/config/tc-i386.c
+++ b/gnu/usr.bin/binutils/gas/config/tc-i386.c
@@ -1380,7 +1380,7 @@ md_assemble (line)
{
expressionS *exp;
- if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+ if ((i.tm.cpu_flags & (CpuPNI|CpuSMAP)) && i.operands > 0)
{
/* These Intel Prescott New Instructions have the fixed
operands with an opcode suffix which is coded in the same
diff --git a/gnu/usr.bin/binutils/gas/config/tc-i386.h b/gnu/usr.bin/binutils/gas/config/tc-i386.h
index 3f78ffde4a0..b1f3e760265 100644
--- a/gnu/usr.bin/binutils/gas/config/tc-i386.h
+++ b/gnu/usr.bin/binutils/gas/config/tc-i386.h
@@ -199,13 +199,14 @@ typedef struct
#define CpuAES 0x40000 /* Intel AES extensions required */
#define CpuPCLMUL 0x80000 /* Intel Carry-less Multiplication extensions */
#define CpuRdRnd 0x100000 /* Intel Random Number Generator extensions */
+#define CpuSMAP 0x200000 /* Intel Supervisor Mode Access Prevention */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
/* The default value for unknown CPUs - enable all features to avoid problems. */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock|CpuSSSE3|CpuAES|CpuPCLMUL|CpuRdRnd)
+#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock|CpuSSSE3|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
diff --git a/gnu/usr.bin/binutils/include/opcode/i386.h b/gnu/usr.bin/binutils/include/opcode/i386.h
index a9c1ec93194..9d811b325ab 100644
--- a/gnu/usr.bin/binutils/include/opcode/i386.h
+++ b/gnu/usr.bin/binutils/include/opcode/i386.h
@@ -1405,6 +1405,10 @@ static const template i386_optab[] = {
/* Intel Random Number Generator extensions */
{"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } },
+/* Intel Supervisor Mode Access Prevention extensions */
+{"clac", 0, 0x0f01, 0xca, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } },
+{"stac", 0, 0x0f01, 0xcb, CpuSMAP, NoSuf|ImmExt, { 0, 0, 0 } },
+
/* sentinel */
{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
};
diff --git a/gnu/usr.bin/binutils/opcodes/i386-dis.c b/gnu/usr.bin/binutils/opcodes/i386-dis.c
index cb52199b519..f33929fd8f8 100644
--- a/gnu/usr.bin/binutils/opcodes/i386-dis.c
+++ b/gnu/usr.bin/binutils/opcodes/i386-dis.c
@@ -4148,7 +4148,7 @@ SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
static void
PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
{
- if (mod == 3 && reg == 1)
+ if (mod == 3 && reg == 1 && rm <= 1)
{
char *p = obuf + strlen (obuf);
@@ -4166,6 +4166,16 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
codep++;
}
+ else if (mod == 3 && reg == 1 && rm <= 3)
+ {
+ size_t olen = strlen (obuf);
+ char *p = obuf + olen - 4;
+ if (*codep == 0xca)
+ strcpy (p, "clac");
+ else if (*codep == 0xcb)
+ strcpy (p, "stac");
+ codep++;
+ }
else
OP_E (0, sizeflag);
}