Move the actual operand contraints in define_split constructs from the lisp

expression attributes to the conditional C statement chunk, for this is the
only way to have them honored with gcc 3 (thanks for genrecog to warn about
this).

Note that most of the affected operands were ``register_operand'', hence the
"r" constraint is implied. There are a few `register + ccmode' constructs which
could have caused wrong code generation before this change, though.

1 files changed, 153 insertions, 101 deletions

diff --git a/gnu/usr.bin/gcc/gcc/config/m88k/m88k.md b/gnu/usr.bin/gcc/gcc/config/m88k/m88k.md
index 9f64c2cca27..a79cce0778c 100644
--- a/gnu/usr.bin/gcc/gcc/config/m88k/m88k.md
+++ b/gnu/usr.bin/gcc/gcc/config/m88k/m88k.md
@@ -198,11 +198,14 @@
 ;;      addu.cio r6,r4,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (geu:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "register_operand" "r"))))]
-  ""
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (geu:SI (match_operand:SI 2 "register_operand" "")
+			  (match_operand:SI 3 "register_operand" ""))))]
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG
+   && GET_CODE (operands[3]) == REG"
   [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
    (set (match_dup 0)
 	(plus:SI (match_dup 1)
@@ -215,11 +218,14 @@
 ;;      addu.cio r6,r4,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (leu:SI (match_operand:SI 3 "register_operand" "r")
-			  (match_operand:SI 2 "register_operand" "r"))))]
-  ""
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (leu:SI (match_operand:SI 3 "register_operand" "")
+			  (match_operand:SI 2 "register_operand" ""))))]
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG
+   && GET_CODE (operands[3]) == REG"
   [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
    (set (match_dup 0)
 	(plus:SI (match_dup 1)
@@ -232,11 +238,13 @@
 ;;      addu.cio r5,r3,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (eq:SI (match_operand:SI 2 "register_operand" "r")
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (eq:SI (match_operand:SI 2 "register_operand" "")
 			 (const_int 0))))]
-  ""
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG"
   [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1))
    (set (match_dup 0)
 	(plus:SI (match_dup 1)
@@ -249,11 +257,14 @@
 ;;      subu.cio r6,r4,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ltu:SI (match_operand:SI 2 "register_operand" "r")
-			 (match_operand:SI 3 "register_operand" "r"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (ltu:SI (match_operand:SI 2 "register_operand" "")
+			 (match_operand:SI 3 "register_operand" ""))
+		 (match_operand:SI 1 "register_operand" "")))]
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG
+   && GET_CODE (operands[3]) == REG"
   [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
    (set (match_dup 0)
 	(minus:SI (match_dup 1)
@@ -266,11 +277,14 @@
 ;;      subu.cio r6,r4,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (gtu:SI (match_operand:SI 3 "register_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (gtu:SI (match_operand:SI 3 "register_operand" "")
+			 (match_operand:SI 2 "register_operand" ""))
+		 (match_operand:SI 1 "register_operand" "")))]
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG
+   && GET_CODE (operands[3]) == REG"
   [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
    (set (match_dup 0)
 	(minus:SI (match_dup 1)
@@ -283,11 +297,13 @@
 ;;      subu.cio r5,r3,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ne:SI (match_operand:SI 2 "register_operand" "r")
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (ne:SI (match_operand:SI 2 "register_operand" "")
 			(const_int 0))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
+		 (match_operand:SI 1 "register_operand" "")))]
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG"
   [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1))
    (set (match_dup 0)
 	(minus:SI (match_dup 1)
@@ -300,13 +316,15 @@
 ;;	subu.cio r5,r3,r0
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
 		  (xor:SI (lshiftrt:SI
-			   (match_operand:SI 2 "register_operand" "r")
+			   (match_operand:SI 2 "register_operand" "")
 			   (const_int 31))
 			  (const_int 1))))]
-  ""
+  "GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG
+   && GET_CODE (operands[2]) == REG"
   [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 2)] 0))
    (set (match_dup 0)
 	(minus:SI (match_dup 1)
@@ -409,7 +427,7 @@
 ;; into an alternate form of bb0 and bb1.
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (neg:SI 
 		 (match_operator 1 "even_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -418,8 +436,9 @@
 		 (match_operator 3 "relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -447,7 +466,7 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (neg:SI 
 		 (match_operator 1 "odd_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -456,8 +475,9 @@
 		 (match_operator 3 "odd_relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -477,7 +497,7 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (neg:SI 
 		 (match_operator 1 "odd_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -486,8 +506,9 @@
 		 (match_operator 3 "even_relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(ior:CCEVEN (not:CC (match_dup 2))
 		(match_dup 4)))
@@ -509,16 +530,18 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (match_operator 1 "even_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])
-   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && (GET_CODE (operands[1]) == GET_CODE (operands[3])
+       || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3])))"
   [(set (match_dup 5)
 	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -530,15 +553,17 @@
       operands[4] = gen_rtx_NOT (CCmode, operands[4]);")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (match_operator 1 "odd_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "odd_relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == GET_CODE (operands[3])"
   [(set (match_dup 5)
 	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -547,15 +572,17 @@
   "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(ior:SI (match_operator 1 "odd_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "even_relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
   [(set (match_dup 5)
 	(ior:CCEVEN (not:CC (match_dup 4))
 		(match_dup 2)))
@@ -564,7 +591,7 @@
   "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (neg:SI 
 		 (match_operator 1 "even_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -573,8 +600,9 @@
 		 (match_operator 3 "relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -601,7 +629,7 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (neg:SI 
 		 (match_operator 1 "odd_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -610,8 +638,9 @@
 		 (match_operator 3 "odd_relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -630,7 +659,7 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (neg:SI 
 		 (match_operator 1 "odd_relop"
 				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
@@ -639,8 +668,9 @@
 		 (match_operator 3 "even_relop"
 				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 5)
 	(and:CCEVEN (not:CC (match_dup 2))
 		(match_dup 4)))
@@ -661,16 +691,18 @@
      }")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (match_operator 1 "even_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])
-   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && (GET_CODE (operands[1]) == GET_CODE (operands[3])
+       || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3])))"
   [(set (match_dup 5)
 	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -682,15 +714,17 @@
       operands[4] = gen_rtx_NOT (CCmode, operands[4]);")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (match_operator 1 "odd_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "odd_relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == GET_CODE (operands[3])"
   [(set (match_dup 5)
 	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
@@ -699,15 +733,17 @@
   "operands[5] = gen_rtx_SUBREG (CCEVENmode, operands[5], 0);")
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(and:SI (match_operator 1 "odd_relop"
 				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "even_relop"
 				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+   (clobber (match_operand:SI 5 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
   [(set (match_dup 5)
 	(and:CCEVEN (not:CC (match_dup 2))
 		(match_dup 4)))
@@ -765,12 +801,15 @@
 ;; rotate/and[.c] and rotate/ior[.c]
 
 (define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "")
+	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
+		(match_operand 3 "partial_ccmode_register_operand" "")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && partial_ccmode_register_operand (operands[1], VOIDmode)
+   && partial_ccmode_register_operand (operands[3], VOIDmode)"
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -787,12 +826,15 @@
   "#")
 
 (define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "")
+	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
+		(match_operand 3 "partial_ccmode_register_operand" "")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && partial_ccmode_register_operand (operands[1], VOIDmode)
+   && partial_ccmode_register_operand (operands[3], VOIDmode)"
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -809,12 +851,15 @@
   "#")
 
 (define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "")
+	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
+		(match_operand 3 "partial_ccmode_register_operand" "")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && partial_ccmode_register_operand (operands[1], VOIDmode)
+   && partial_ccmode_register_operand (operands[3], VOIDmode)"
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -831,12 +876,15 @@
   "#")
 
 (define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "")
+	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
+		(match_operand 3 "partial_ccmode_register_operand" "")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && partial_ccmode_register_operand (operands[1], VOIDmode)
+   && partial_ccmode_register_operand (operands[3], VOIDmode)"
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -1386,12 +1434,13 @@
   [(set_attr "type" "bit")])
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(match_operator:SI 1 "odd_relop"
 			   [(match_operand:CCEVEN 2 "register_operand" "r")
 			    (const_int 0)]))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
    (set (match_dup 0) (not:SI (match_dup 3)))]
   "")
@@ -1436,12 +1485,13 @@
   [(set_attr "type" "bit")])
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(neg:SI (match_operator:SI 1 "odd_relop"
 			   [(match_operand:CCEVEN 2 "register_operand" "r")
 			    (const_int 0)])))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  ""
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG"
   [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
                                                        (const_int 0)]))))
    (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
@@ -1983,8 +2033,8 @@
 }")
 
 (define_split
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(match_operand:DF 1 "register_operand" "r"))]
+  [(set (match_operand:DF 0 "register_operand" "")
+	(match_operand:DF 1 "register_operand" ""))]
   "reload_completed
    && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0]))
    && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))"
@@ -2320,9 +2370,11 @@
   "#")
 
 (define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
-  "reload_completed"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG
+   && GET_CODE (operands[1]) == REG"
   [(set (subreg:SI (match_dup 0) 4) (match_dup 1))
    (set (subreg:SI (match_dup 0) 0)
 	(ashiftrt:SI (match_dup 1) (const_int 31)))]