use the new CPU_ID_AA64ISAR0 sysctl to determine CPU features on arm64

ok tb@, deraadt@, kettenis@

1 files changed, 55 insertions, 5 deletions

diff --git a/lib/libcrypto/arch/aarch64/arm64cap.c b/lib/libcrypto/arch/aarch64/arm64cap.c
index b541ac31b9f..9d75daba0ba 100644
--- a/lib/libcrypto/arch/aarch64/arm64cap.c
+++ b/lib/libcrypto/arch/aarch64/arm64cap.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: arm64cap.c,v 1.1 2022/03/23 15:13:31 tb Exp $ */
+/* $OpenBSD: arm64cap.c,v 1.2 2022/03/25 17:42:07 robert Exp $ */
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -6,10 +6,63 @@
 #include <signal.h>
 #include <openssl/crypto.h>
 
+#if defined(__OpenBSD__)
+#include <sys/sysctl.h>
+#include <machine/cpu.h>	/* CPU_ID_AA64ISAR0 */
+#endif
+
 #include "arm64_arch.h"
 
+/* ID_AA64ISAR0_EL1 required for OPENSSL_cpuid_setup */
+#define	ID_AA64ISAR0_AES_SHIFT		4
+#define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
+#define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
+#define	 ID_AA64ISAR0_AES_BASE		(0x1 << ID_AA64ISAR0_AES_SHIFT)
+#define	 ID_AA64ISAR0_AES_PMULL		(0x2 << ID_AA64ISAR0_AES_SHIFT)
+#define	ID_AA64ISAR0_SHA1_SHIFT		8
+#define	ID_AA64ISAR0_SHA1_MASK		(0xf << ID_AA64ISAR0_SHA1_SHIFT)
+#define	ID_AA64ISAR0_SHA1(x)		((x) & ID_AA64ISAR0_SHA1_MASK)
+#define	 ID_AA64ISAR0_SHA1_BASE		(0x1 << ID_AA64ISAR0_SHA1_SHIFT)
+#define	ID_AA64ISAR0_SHA2_SHIFT		12
+#define	ID_AA64ISAR0_SHA2_MASK		(0xf << ID_AA64ISAR0_SHA2_SHIFT)
+#define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
+#define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
+
 unsigned int OPENSSL_armcap_P;
 
+#if defined(__GNUC__) && __GNUC__ >= 2
+void OPENSSL_cpuid_setup(void) __attribute__((constructor));
+#endif
+
+#if defined(CPU_ID_AA64ISAR0)
+void
+OPENSSL_cpuid_setup(void)
+{
+	int isar0_mib[] = { CTL_MACHDEP, CPU_ID_AA64ISAR0 };
+	size_t len = sizeof(uint64_t);
+	uint64_t cpu_id = 0;
+
+	if (OPENSSL_armcap_P != 0)
+		return;
+
+	if (sysctl(isar0_mib, 2, &cpu_id, &len, NULL, 0) < 0)
+		return;
+
+	OPENSSL_armcap_P |= ARMV7_NEON;
+
+	if (ID_AA64ISAR0_AES(cpu_id) >= ID_AA64ISAR0_AES_BASE)
+		OPENSSL_armcap_P |= ARMV8_AES;
+
+	if (ID_AA64ISAR0_AES(cpu_id) >= ID_AA64ISAR0_AES_PMULL)
+		OPENSSL_armcap_P |= ARMV8_PMULL;
+
+	if (ID_AA64ISAR0_SHA1(cpu_id) >= ID_AA64ISAR0_SHA1_BASE)
+		OPENSSL_armcap_P |= ARMV8_SHA1;
+
+	if (ID_AA64ISAR0_SHA2(cpu_id) >= ID_AA64ISAR0_SHA2_BASE)
+		OPENSSL_armcap_P |= ARMV8_SHA256;
+}
+#else
 #if __ARM_ARCH__ >= 7
 static sigset_t all_masked;
 
@@ -28,10 +81,6 @@ void _armv8_sha256_probe(void);
 void _armv8_pmull_probe(void);
 #endif
 
-#if defined(__GNUC__) && __GNUC__>=2
-void OPENSSL_cpuid_setup(void) __attribute__((constructor));
-#endif
-
 void
 OPENSSL_cpuid_setup(void)
 {
@@ -86,3 +135,4 @@ OPENSSL_cpuid_setup(void)
 	sigprocmask(SIG_SETMASK, &oset, NULL);
 #endif
 }
+#endif