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authorOwain Ainsworth <oga@cvs.openbsd.org>2010-04-08 11:45:55 +0000
committerOwain Ainsworth <oga@cvs.openbsd.org>2010-04-08 11:45:55 +0000
commit0b6361ab565dfaf98b3a52bb33bc52b3912cd495 (patch)
treedf735a2e0df56501cf648a463390dc91e12595b1 /regress/sbin/ipsecctl/ike49.ok
parenteaf575b0d9e584b55a93a77a41f2126f201ae444 (diff)
DRM memory management for inteldrm(4) using the Graphics Execution
Manager api. This is currently disabled by default under ifdef INTELDRM_GEM (option INTELDRM_GEM in a kernel config or a patch to i915_drv.h needed to enable), mostly because the intel X driver currently in tree does not always play well with GEM and needs to be switched to UXA accelmethod (which is the only option on later drivers). While based on the intel drm code in the linux kernel this has come cleanups and some obvious behaviour changes: 1) mmap through the GTT is entirely coherent with the gpu cache, removing mappings whenever the cache dirties so you can not race with userland to write to memory at the same time as the gpu. 2) pread/pwrite access is tiling-correct, so userland does not need to tile manually (mesa has already been fixed for this a while ago). The straw that broke the camels back here was the bit17 swizzling stuff on some mobile gpus meansing that while userland did the swizzle itself, the kernel had to do *extra* swizzling, this was frankly retarded so the option was dropped. 3) there is no option to map via the cpu from userland, again due to coherency issues. 4) additional integer overflow checking in some areas. 5) we only support the newer EXECBUFFER2 command submission ioctl. the old one is not supported at all (libdrm was fixed WRT over a week ago). now the TODOs: 1) the locking is funky and is only correct due to biglock. it does however work due to that. This will be fixed in tree, the design in formulating in my head as I type. 2) there are currently no memory limits on drm memory, this needs to be changed. 3) we really need PAT support for the machines where MTRRs are useless, else drm uses quite a lot of cpu (this is a bug that continues from the older code though, nothing new). 4) gpu resetting support on other than 965 is not written yet. 5) currently a lot of the code is in inteldrm, when memory management comes to other chipset common code will be factored out into the drm midlayer. Tested on: 855 (x40), GM965 and 915 by me. 945 by armani@ and jkmeuser@, gm45 by armani@ and marco@. More testing is needed before I enable this by default though. Others also provided testing by what they tested escapes me right now. In order to test this enable INTELDRM_GEM in a kernel and add the following line to the driver section in xorg.conf (I am working on a patch to autodetect the X stuff): Option "AccelMethod" "UXA"
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