Add a setperf mechanism for ich speedstep controlled by SMI on certain

parings of the Intel Pentium 3 and the ich southbridges. Written by
Stefan Sperling <stsp AT tsp DOT in-berlin DOT de> based on a driver in
NetBSD and sys/arch/i386/pci/ichpcib.c.
Tested my mpf@ among others,
ok tedu

2 files changed, 75 insertions, 2 deletions

diff --git a/share/man/man4/man4.i386/Makefile b/share/man/man4/man4.i386/Makefile
index a3dbae4884c..e2e576de085 100644
--- a/share/man/man4/man4.i386/Makefile
+++ b/share/man/man4/man4.i386/Makefile
@@ -1,4 +1,4 @@
-#	$OpenBSD: Makefile,v 1.59 2006/10/27 17:10:48 jmc Exp $
+#	$OpenBSD: Makefile,v 1.60 2007/04/26 01:43:14 gwk Exp $
 #	from: @(#)Makefile	5.1 (Berkeley) 2/12/91
 #	Id: Makefile,v 1.4 1995/12/14 05:41:38 deraadt Exp $
 
@@ -6,7 +6,7 @@ MAN=	apm.4 autoconf.4 bios.4 cpu.4 elansc.4 esm.4 \
 	geodesc.4 glxsb.4 gscpcib.4 gscpm.4 gus.4 ie.4 \
 	ichpcib.4 intro.4 ioapic.4 \
 	joy.4 le.4 lms.4 mcd.4 mem.4 mms.4 mtrr.4 npx.4 nvram.4 pas.4 \
-	pcibios.4 pctr.4 pss.4 sb.4 \
+	pcibios.4 pctr.4 piixpcib.4 pss.4 sb.4 \
 	sea.4 uha.4 wds.4 wdt.4 wss.4 wt.4
 
 MLINKS+= mem.4 kmem.4
diff --git a/share/man/man4/man4.i386/piixpcib.4 b/share/man/man4/man4.i386/piixpcib.4
new file mode 100644
index 00000000000..ca2501605c3
--- /dev/null
+++ b/share/man/man4/man4.i386/piixpcib.4
@@ -0,0 +1,73 @@
+.\"	$OpenBSD: piixpcib.4,v 1.1 2007/04/26 01:43:14 gwk Exp $
+.\"
+.\" Copyright (c) 2007 Stefan Sperling <stsp@stsp.in-berlin.de>
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd March 20, 2007
+.Dt PIIXPCIB 4 i386
+.Os
+.Sh NAME
+.Nm piixpcib
+.Nd Intel PIIX4 ISA bridges
+.Sh SYNOPSIS
+.Cd "piixpcib* at pci?"
+.Cd "isa* at piixpcib?"
+.Sh DESCRIPTION
+The
+.Nm
+driver supports Intel
+.Tn 82371AB
+and
+.Tn 82440MX
+PIIX4 ISA bridges.
+
+Besides the core
+.Xr pcib 4
+functionality, the
+.Nm
+driver provides support for the first generation of Intel's SpeedStep
+technology present in some Pentium III CPUs.
+It allows the user to manually control CPU frequency with the
+.Xr sysctl 8
+program.
+The
+.Xr apmd 8
+daemon can be used to automatically control CPU frequency.
+SpeedStep provides two CPU power states, low and high.
+The driver will switch the CPU into low power state if the
+hw.setperf sysctl is smaller or equal 50, and into high
+power state if hw.setperf is greater 50.
+.Sh SEE ALSO
+.Xr cpu 4 ,
+.Xr intro 4 ,
+.Xr isa 4 ,
+.Xr pci 4 ,
+.Xr pcib 4 ,
+.Xr ichpcib 4 ,
+.Xr sysctl 8 ,
+.Xr apmd 8
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 4.2 .
+.Sh BUGS
+The driver sometimes fails to update the hw.cpuspeed sysctl correctly
+after switching power state. The reason is that there seems to be
+no reliable way to determine CPU frequencies corresponding to low
+and high power states, so the driver has to rely on the p3_update_cpuspeed
+function to dynamically determine CPU speed after switching power state.
+This seems to fail occasionally, especially if interrupt load of the system
+is high. Note that this bug is purely cosmetic. Switching power state still
+works even if the CPU speed is displayed incorrectly.