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authorTheo de Raadt <deraadt@cvs.openbsd.org>1996-06-18 09:45:47 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>1996-06-18 09:45:47 +0000
commit41ae123ec2d77615cd0b0476ff62564bd7a4865f (patch)
treeba6a57d3a8d7d725a5e0ae64e8401ed3bea0efb9 /sys/arch/alpha/pci/ciareg.h
parent7a0b7f798c45842a34a4c6413f45e1b3824154a5 (diff)
sync to 0616, retaining local diffs
Diffstat (limited to 'sys/arch/alpha/pci/ciareg.h')
-rw-r--r--sys/arch/alpha/pci/ciareg.h34
1 files changed, 27 insertions, 7 deletions
diff --git a/sys/arch/alpha/pci/ciareg.h b/sys/arch/alpha/pci/ciareg.h
index 5fc6ae9435a..403afa6e3de 100644
--- a/sys/arch/alpha/pci/ciareg.h
+++ b/sys/arch/alpha/pci/ciareg.h
@@ -1,7 +1,7 @@
-/* $NetBSD: ciareg.h,v 1.1 1995/11/23 02:37:31 cgd Exp $ */
+/* $NetBSD: ciareg.h,v 1.1.4.3 1996/06/13 18:35:27 cgd Exp $ */
/*
- * Copyright (c) 1995 Carnegie-Mellon University.
+ * Copyright (c) 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
@@ -38,14 +38,34 @@
/*
* Base addresses
*/
-#define CIA_PCI_SPARSE0 0x8000000000L
-#define CIA_PCI_SPARSE1 0x8400000000L
-#define CIA_PCI_SPARSE2 0x8500000000L
-#define CIA_PCI_SIO0 0x8580000000L
-#define CIA_PCI_SIO1 0x85c0000000L
+#define CIA_PCI_SMEM1 0x8000000000L
+#define CIA_PCI_SMEM2 0x8400000000L
+#define CIA_PCI_SMEM3 0x8500000000L
+#define CIA_PCI_SIO1 0x8580000000L
+#define CIA_PCI_SIO2 0x85c0000000L
#define CIA_PCI_DENSE 0x8600000000L
#define CIA_PCI_CONF 0x8700000000L
#define CIA_PCI_IACK 0x8720000000L
#define CIA_CSRS 0x8740000000L
#define CIA_PCI_MC_CSRS 0x8750000000L
#define CIA_PCI_ATRANS 0x8760000000L
+
+/*
+ * General CSRs
+ */
+
+#define CIA_CSR_HAE_MEM (CIA_CSRS + 0x400)
+
+#define HAE_MEM_REG1_START(x) (((u_int32_t)(x) & 0xe0000000) << 0)
+#define HAE_MEM_REG1_MASK 0x1fffffff
+#define HAE_MEM_REG2_START(x) (((u_int32_t)(x) & 0x0000f800) << 16)
+#define HAE_MEM_REG2_MASK 0x07ffffff
+#define HAE_MEM_REG3_START(x) (((u_int32_t)(x) & 0x000000fc) << 16)
+#define HAE_MEM_REG3_MASK 0x03ffffff
+
+#define CIA_CSR_HAE_IO (CIA_CSRS + 0x440)
+
+#define HAE_IO_REG1_START(x) 0
+#define HAE_IO_REG1_MASK 0x01ffffff
+#define HAE_IO_REG2_START(x) (((u_int32_t)(x) & 0xfe000000) << 0)
+#define HAE_IO_REG2_MASK 0x01ffffff