add DEC_KN300 support from NetBSD;

This code makes it possible to run on some of the AlphaServers,
namely AlphaServer 4100 and 1200.

add mcbus(4) and mcpcia(4) to provide support for the system bus and
the MCPCIA-to-PCI bus adapter that can be found in these systems

allow the pci_swiz_bus code to handle variable extent names
to be able to handle more than one mcpcia(4)

"just commit it" deraadt@

19 files changed, 2830 insertions, 25 deletions

diff --git a/sys/arch/alpha/alpha/cpuconf.c b/sys/arch/alpha/alpha/cpuconf.c
index fa2e3e8287f..fe20e5dce92 100644
--- a/sys/arch/alpha/alpha/cpuconf.c
+++ b/sys/arch/alpha/alpha/cpuconf.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpuconf.c,v 1.10 2005/04/28 17:19:14 deraadt Exp $ */
+/* $OpenBSD: cpuconf.c,v 1.11 2007/03/16 21:22:27 robert Exp $ */
 /* $NetBSD: cpuconf.c,v 1.27 2000/06/26 02:42:04 enami Exp $ */
 
 /*-
@@ -172,7 +172,7 @@ static const struct cpuinit cpuinit[] = {
 	cpu_notsupp(ST_EB66, "DEC_EB66"),
 	cpu_init(ST_EB64P, dec_eb64plus_init, "DEC_EB64PLUS"),
 	cpu_notsupp(ST_ALPHABOOK1, "DEC_ALPHABOOK1"),
-	cpu_notsupp(ST_DEC_4100, "DEC_KN300"),
+	cpu_init(ST_DEC_4100, dec_kn300_init, "DEC_KN300"),
 	cpu_notsupp(ST_DEC_EV45_PBP, "EV45 Passive Backplane Board"),
 	cpu_notsupp(ST_DEC_2100A_A500, "DEC_2100A_A500"),
 	cpu_init(ST_EB164, dec_eb164_init, "DEC_EB164"),
diff --git a/sys/arch/alpha/alpha/dec_kn300.c b/sys/arch/alpha/alpha/dec_kn300.c
new file mode 100644
index 00000000000..e72270d3b30
--- /dev/null
+++ b/sys/arch/alpha/alpha/dec_kn300.c
@@ -0,0 +1,325 @@
+/* $OpenBSD: dec_kn300.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: dec_kn300.c,v 1.34 2007/03/04 15:18:10 yamt Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/termios.h>
+#include <sys/conf.h>
+#include <dev/cons.h>
+
+#include <machine/rpb.h>
+#include <machine/autoconf.h>
+#include <machine/frame.h>
+#include <machine/cpuconf.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/ic/i8042reg.h>
+#include <dev/ic/pckbcvar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <alpha/mcbus/mcbusreg.h>
+#include <alpha/mcbus/mcbusvar.h>
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+#include <alpha/pci/pci_kn300.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include "pckbd.h"
+
+#ifndef	CONSPEED
+#define	CONSPEED	TTYDEF_SPEED
+#endif
+static int comcnrate = CONSPEED;
+
+#ifdef DEBUG
+int bootdev_debug;
+#define DPRINTF(x)	if (bootdev_debug) printf x
+#else
+#define DPRINTF(x)
+#endif
+
+void dec_kn300_init (void);
+void dec_kn300_cons_init (void);
+static void dec_kn300_device_register (struct device *, void *);
+
+#ifdef KGDB
+#include <machine/db_machdep.h>
+
+static const char *kgdb_devlist[] = {
+	"com",
+	NULL,
+};
+#endif /* KGDB */
+
+#define	ALPHASERVER_4100	"AlphaServer 4100"
+
+const struct alpha_variation_table dec_kn300_variations[] = {
+	{ 0, ALPHASERVER_4100 },
+	{ 0, NULL },
+};
+
+void
+dec_kn300_init()
+{
+	u_int64_t variation;
+	int cachesize;
+
+	platform.family = ALPHASERVER_4100;
+
+	if ((platform.model = alpha_dsr_sysname()) == NULL) {
+		variation = hwrpb->rpb_variation & SV_ST_MASK;
+		if ((platform.model = alpha_variation_name(variation,
+		    dec_kn300_variations)) == NULL)
+			platform.model = alpha_unknown_sysname();
+	}
+
+	platform.iobus = "mcbus";
+	platform.cons_init = dec_kn300_cons_init;
+	platform.device_register = dec_kn300_device_register;
+
+	/*
+	 * Determine B-cache size by looking at the primary (console)
+	 * MCPCIA's WHOAMI register.
+	 */
+	mcpcia_init();
+
+	if (mcbus_primary.mcbus_valid) {
+		switch (mcbus_primary.mcbus_bcache) {
+		default:
+		case CPU_BCache_0MB:
+			/* No B-cache or invalid; default to 1MB. */
+			/* FALLTHROUGH */
+
+		case CPU_BCache_1MB:
+			cachesize = (1 * 1024 * 1024);
+			break;
+
+		case CPU_BCache_2MB:
+			cachesize = (2 * 1024 * 1024);
+			break;
+
+		case CPU_BCache_4MB:
+			cachesize = (4 * 1024 * 1024);
+			break;
+		}
+	} else {
+		/* Default to 1MB. */
+		cachesize = (1 * 1024 * 1024);
+	}
+}
+
+void
+dec_kn300_cons_init()
+{
+	struct ctb *ctb;
+	struct mcpcia_config *ccp;
+	extern struct mcpcia_config mcpcia_console_configuration;
+
+	ccp = &mcpcia_console_configuration;
+	/* It's already initialized. */
+
+	ctb = (struct ctb *)(((char *)hwrpb) + hwrpb->rpb_ctb_off);
+
+	switch (ctb->ctb_term_type) {
+	case CTB_PRINTERPORT: 
+		/* serial console ... */
+		/*
+		 * Delay to allow PROM putchars to complete.
+		 * FIFO depth * character time,
+		 * character time = (1000000 / (defaultrate / 10))
+		 */
+		DELAY(160000000 / comcnrate);
+		if (comcnattach(&ccp->cc_iot, 0x3f8, comcnrate,
+		    COM_FREQ,
+		    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
+			panic("can't init serial console");
+
+		}
+		break;
+
+	case CTB_GRAPHICS:
+#if NPCKBD > 0
+		/* display console ... */
+		/* XXX */
+		(void) pckbc_cnattach(&ccp->cc_iot, IO_KBD, KBCMDP,
+		    PCKBC_KBD_SLOT);
+
+		if (CTB_TURBOSLOT_TYPE(ctb->ctb_turboslot) ==
+		    CTB_TURBOSLOT_TYPE_ISA)
+			isa_display_console(&ccp->cc_iot, &ccp->cc_memt);
+		else
+			pci_display_console(&ccp->cc_iot, &ccp->cc_memt,
+			    &ccp->cc_pc, CTB_TURBOSLOT_BUS(ctb->ctb_turboslot),
+			    CTB_TURBOSLOT_SLOT(ctb->ctb_turboslot), 0);
+#else
+		panic("not configured to use display && keyboard console");
+#endif
+		break;
+
+	default:
+		printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
+		printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
+
+		panic("consinit: unknown console type %ld",
+		    ctb->ctb_term_type);
+	}
+#ifdef KGDB
+	/* Attach the KGDB device. */
+	alpha_kgdb_init(kgdb_devlist, &ccp->cc_iot);
+#endif /* KGDB */
+}
+
+static void
+dec_kn300_device_register(dev, aux)
+	struct device *dev;
+	void *aux;
+{
+	static int found, initted, diskboot, netboot;
+	static struct device *primarydev, *pcidev, *ctrlrdev;
+	struct bootdev_data *b = bootdev_data;
+	struct device *parent = dev->dv_parent; 
+	struct cfdata *cf = dev->dv_cfdata;
+	struct cfdriver *cd = cf->cf_driver;
+
+	if (found)
+		return;
+
+	if (!initted) {
+		diskboot = (strncasecmp(b->protocol, "SCSI", 4) == 0);
+		netboot = (strncasecmp(b->protocol, "BOOTP", 5) == 0) ||
+		    (strncasecmp(b->protocol, "MOP", 3) == 0);
+
+		DPRINTF(("proto:%s bus:%d slot:%d chan:%d", b->protocol,
+		    b->bus, b->slot, b->channel));
+		if (b->remote_address)
+			printf(" remote_addr:%s", b->remote_address);
+		DPRINTF((" un:%d bdt:%d", b->unit, b->boot_dev_type));
+		if (b->ctrl_dev_type)
+			DPRINTF((" cdt:%s\n", b->ctrl_dev_type));
+		else
+			DPRINTF(("\n"));
+		DPRINTF(("diskboot = %d, netboot = %d\n", diskboot, netboot));
+		initted = 1;
+	}
+
+	if (primarydev == NULL) {
+		if (strcmp(cd->cd_name, "mcpcia"))
+			return;
+		else {
+			struct mcbus_dev_attach_args *ma = aux;
+
+			if (b->bus != ma->ma_mid - 4)
+				return;
+			primarydev = dev;
+			DPRINTF(("\nprimarydev = %s\n", dev->dv_xname));
+			return;
+		}
+	}
+
+	if (pcidev == NULL) {
+		if (strcmp(cd->cd_name, "pci"))
+			return;
+		/*
+		 * Try to find primarydev anywhere in the ancestry.  This is
+		 * necessary if the PCI bus is hidden behind a bridge.
+		 */
+		else {
+			struct pcibus_attach_args *pba = aux;
+
+			if ((b->slot / 1000) != pba->pba_bus)
+				return;
+	
+			pcidev = dev;
+			DPRINTF(("\npcidev = %s\n", dev->dv_xname));
+			return;
+		}
+	}
+
+	if (ctrlrdev == NULL) {
+		if (parent != pcidev)
+			return;
+		else {
+			struct pci_attach_args *pa = aux;
+			int slot;
+
+			slot = pa->pa_bus * 1000 + pa->pa_function * 100 +
+			    pa->pa_device;
+			if (b->slot != slot)
+				return;
+	
+			if (netboot) {
+				booted_device = dev;
+				DPRINTF(("\nbooted_device = %s\n", dev->dv_xname));
+				found = 1;
+			} else {
+				ctrlrdev = dev;
+				DPRINTF(("\nctrlrdev = %s\n", dev->dv_xname));
+			}
+			return;
+		}
+	}
+
+	if (!diskboot)
+		return;
+
+	if (strcmp(cd->cd_name, "sd") ||
+	    strcmp(cd->cd_name, "st") ||
+	    strcmp(cd->cd_name, "cd")) {
+		struct scsi_attach_args *sa = aux;
+		struct scsi_link *periph = sa->sa_sc_link;
+		int unit;
+
+		if (parent->dv_parent != ctrlrdev)
+			return;
+
+		unit = periph->target * 100 + periph->lun;
+		if (b->unit != unit)
+			return;
+
+		/* we've found it! */
+		booted_device = dev;
+		DPRINTF(("\nbooted_device = %s\n", dev->dv_xname));
+		found = 1;
+	}
+}
diff --git a/sys/arch/alpha/conf/GENERIC b/sys/arch/alpha/conf/GENERIC
index 85d5675777a..1a9c638bc8b 100644
--- a/sys/arch/alpha/conf/GENERIC
+++ b/sys/arch/alpha/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.189 2007/02/28 21:54:43 grange Exp $
+#	$OpenBSD: GENERIC,v 1.190 2007/03/16 21:22:27 robert Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -18,6 +18,7 @@ option		DEC_3000_500	# Flamingo etc:	3000/[4-9]00*
 option		DEC_3000_300	# Pelican etc:	3000/300*
 option		DEC_2100_A50	# Avanti etc:	AlphaStation 400, 200, etc.
 option		DEC_KN20AA	# KN20AA:	AlphaStation 600
+option		DEC_KN300	# KN300:	AlphaServer 4100 and 1200
 option		DEC_AXPPCI_33	# NoName:	AXPpci33, etc.
 option		DEC_EB164	# EB164:	AlphaPC 164
 option		DEC_EB64PLUS	# EB64+:	AlphaPC 64, etc.
@@ -131,6 +132,10 @@ tsc*	at	mainbus0
 # TURBOchannel host bus adapter support
 tcasic*	at	mainbus0
 
+# MCBUS bus support
+mcbus*	at	mainbus0
+mcmem*	at	mcbus? mid ? 
+
 # TURBOchannel bus support
 tc*	at	tcasic?
 
@@ -155,6 +160,7 @@ cia*	at	mainbus?
 irongate* at	mainbus?
 lca*	at	mainbus?
 tsp*	at	tsc?
+mcpcia*	at	mcbus? mid ?
 
 # PCI bus support
 pci*	at	apecs?
@@ -163,6 +169,7 @@ pci*	at	irongate?
 pci*	at	lca?
 pci*	at	ppb?
 pci*	at	tsp?
+pci*	at	mcpcia?
 
 # PCI devices
 ppb*	at pci?				# PCI-PCI bridges
diff --git a/sys/arch/alpha/conf/files.alpha b/sys/arch/alpha/conf/files.alpha
index 1d0815989e5..e4cbf718643 100644
--- a/sys/arch/alpha/conf/files.alpha
+++ b/sys/arch/alpha/conf/files.alpha
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.alpha,v 1.77 2006/09/27 06:33:03 grange Exp $
+#	$OpenBSD: files.alpha,v 1.78 2007/03/16 21:22:27 robert Exp $
 #	$NetBSD: files.alpha,v 1.32 1996/11/25 04:03:21 cgd Exp $
 #
 # alpha-specific configuration info
@@ -12,7 +12,8 @@ maxusers 2 8 64
 define	alpha_shared_intr
 file	arch/alpha/dev/shared_intr.c	alpha_shared_intr | dec_eb164 |
 					dec_kn20aa | dec_6600 | dec_550 |
-					dec_1000 | dec_1000a | dec_eb64plus
+					dec_1000 | dec_1000a | dec_eb64plus |
+					dec_kn300
 
 define	alpha_sgmap
 file	arch/alpha/dev/sgmap_common.c		alpha_sgmap | dec_3000_500
@@ -67,9 +68,19 @@ include	"dev/dec/files.dec"
 #
 # TURBOchannel Devices
 #
-
 include	"dev/tc/files.tc"
 
+#
+# MCBUS bus Devices
+#
+device	mcbus { mid = -1 }
+attach	mcbus at mainbus
+file	arch/alpha/mcbus/mcbus.c		mcbus & dec_kn300
+
+device	mcmem: mcbus
+attach	mcmem at mcbus
+file	arch/alpha/mcbus/mcmem.c		mcmem
+
 # TC attachment is MD
 attach	tc at tcbus
 
@@ -210,6 +221,14 @@ file	arch/alpha/pci/tsp_pci.c		tsp
 file	arch/alpha/pci/tsp_bus_io.c		tsp
 file	arch/alpha/pci/tsp_bus_mem.c		tsp
 
+device	mcpcia: pcibus, alpha_sgmap, alpha_pci_sgmap_pte64
+attach	mcpcia at mcbus
+file	arch/alpha/pci/mcpcia.c		mcpcia
+file	arch/alpha/pci/mcpcia_bus_io.c	mcpcia
+file	arch/alpha/pci/mcpcia_bus_mem.c	mcpcia
+file	arch/alpha/pci/mcpcia_dma.c	mcpcia
+file	arch/alpha/pci/mcpcia_pci.c	mcpcia
+
 file	arch/alpha/pci/pci_2100_a50.c		dec_2100_a50
 file	arch/alpha/pci/pci_axppci_33.c		dec_axppci_33
 file	arch/alpha/pci/pci_eb164.c		dec_eb164
@@ -217,6 +236,7 @@ file	arch/alpha/pci/pci_eb164_intr.s		dec_eb164
 file	arch/alpha/pci/pci_eb64plus.c		dec_eb64plus
 file	arch/alpha/pci/pci_eb64plus_intr.s	dec_eb64plus
 file	arch/alpha/pci/pci_kn20aa.c		dec_kn20aa
+file	arch/alpha/pci/pci_kn300.c		dec_kn300
 file	arch/alpha/pci/pci_550.c		dec_550
 file	arch/alpha/pci/pci_1000a.c		dec_1000a
 file	arch/alpha/pci/pci_1000.c		dec_1000
@@ -304,6 +324,7 @@ file	arch/alpha/alpha/dec_axppci_33.c	dec_axppci_33	needs-flag
 file	arch/alpha/alpha/dec_eb164.c		dec_eb164	needs-flag
 file	arch/alpha/alpha/dec_eb64plus.c		dec_eb64plus	needs-flag
 file	arch/alpha/alpha/dec_kn20aa.c		dec_kn20aa	needs-flag
+file	arch/alpha/alpha/dec_kn300.c		dec_kn300	needs-flag
 file	arch/alpha/alpha/dec_550.c		dec_550		needs-flag
 file	arch/alpha/alpha/dec_1000a.c		dec_1000 | dec_1000a	needs-flag
 file	arch/alpha/alpha/dec_6600.c		dec_6600	needs-flag
diff --git a/sys/arch/alpha/mcbus/mcbus.c b/sys/arch/alpha/mcbus/mcbus.c
new file mode 100644
index 00000000000..30e050bd5ac
--- /dev/null
+++ b/sys/arch/alpha/mcbus/mcbus.c
@@ -0,0 +1,211 @@
+/* $OpenBSD: mcbus.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcbus.c,v 1.19 2007/03/04 05:59:11 christos Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Autoconfiguration routines for the MCBUS system
+ * bus found on AlphaServer 4100 systems.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+#include <machine/pte.h>
+
+#include <alpha/mcbus/mcbusreg.h>
+#include <alpha/mcbus/mcbusvar.h>
+
+#include <alpha/pci/mcpciareg.h>
+
+#define KV(_addr)	((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
+#define	MCPCIA_EXISTS(mid, gid)	\
+	(!badaddr((void *)KV(MCPCIA_BRIDGE_ADDR(gid, mid)), sizeof (u_int32_t)))
+
+struct mcbus_cpu_busdep mcbus_primary;
+
+int	mcbusmatch (struct device *, void *, void *);
+void	mcbusattach (struct device *, struct device *, void *);
+int	mcbusprint (void *, const char *);
+int	mcbussbm (struct device *, void *, void *);
+
+const	char *mcbus_node_type_str (u_int8_t);
+
+typedef struct {
+	struct device	mcbus_dev;
+	u_int8_t	mcbus_types[MCBUS_MID_MAX];
+} mcbus_softc_t;
+
+struct cfattach mcbus_ca = {
+	sizeof(mcbus_softc_t), mcbusmatch, mcbusattach
+};
+
+struct cfdriver mcbus_cd = {
+        NULL, "mcbus", DV_DULL,
+};
+
+/*
+ * Tru64 UNIX (formerly Digital UNIX (formerly DEC OSF/1)) probes for MCPCIAs
+ * in the following order:
+ *
+ *	5, 4, 7, 6
+ *
+ * This is so that the built-in CD-ROM on the internal 53c810 is always
+ * dka500.  We probe them in the same order, for consistency.
+ */
+const int mcbus_mcpcia_probe_order[] = { 5, 4, 7, 6 };
+
+extern void mcpcia_config_cleanup (void);
+
+int
+mcbusprint(aux, cp)
+	void *aux;
+	const char *cp;
+{
+	struct mcbus_dev_attach_args *tap = aux;
+	printf(" mid %d: %s", tap->ma_mid,
+	    mcbus_node_type_str(tap->ma_type));
+	return (UNCONF);
+}
+
+int
+mcbussbm(parent, cf, aux)
+	struct device *parent;
+	void *cf;
+	void *aux;
+{
+	struct mcbus_dev_attach_args *tap = aux;
+	struct cfdata *mcf = (struct cfdata *)cf;
+
+	if (mcf->cf_loc[MCBUSCF_MID] != MCBUSCF_MID_DEFAULT &&
+	    mcf->cf_loc[MCBUSCF_MID] != tap->ma_mid) 
+		return (0);
+
+
+	return ((*mcf->cf_attach->ca_match)(parent, mcf, aux));
+}
+
+int
+mcbusmatch(parent, cf, aux)
+	struct device *parent;
+	void *cf;
+	void *aux;
+{
+	struct mainbus_attach_args *ma = aux;
+
+	/* Make sure we're looking for a MCBUS. */
+	if (strcmp(ma->ma_name, mcbus_cd.cd_name) != 0)
+		return (0);
+
+	/*
+	 * Only available on 4100 processor type platforms.
+	 */
+	if (cputype != ST_DEC_4100)
+		return (0);
+
+	return (1);
+}
+
+void
+mcbusattach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	static const char *bcs[CPU_BCacheMask + 1] = {
+		"No", "1MB", "2MB", "4MB",
+	};
+	struct mcbus_dev_attach_args ta;
+	mcbus_softc_t *mbp = (mcbus_softc_t *)self;
+	int i, mid;
+
+	printf(": %s BCache\n", mcbus_primary.mcbus_valid ?
+	    bcs[mcbus_primary.mcbus_bcache] : "Unknown");
+
+	mbp->mcbus_types[0] = MCBUS_TYPE_RES;
+	for (mid = 1; mid <= MCBUS_MID_MAX; ++mid)
+		mbp->mcbus_types[mid] = MCBUS_TYPE_UNK;
+
+	/*
+	 * Find and "configure" memory.
+	 */
+	ta.ma_name = mcbus_cd.cd_name;
+	ta.ma_gid = MCBUS_GID_FROM_INSTANCE(0);
+	ta.ma_mid = 1;
+	ta.ma_type = MCBUS_TYPE_MEM;
+	mbp->mcbus_types[1] = MCBUS_TYPE_MEM;
+
+	(void) config_found_sm(self, &ta, mcbusprint, mcbussbm);
+
+	/*
+	 * Now find PCI busses.
+	 */
+	for (i = 0; i < MCPCIA_PER_MCBUS; i++) {
+		mid = mcbus_mcpcia_probe_order[i];
+		ta.ma_name = mcbus_cd.cd_name;
+		ta.ma_gid = MCBUS_GID_FROM_INSTANCE(0);
+		ta.ma_mid = mid;
+		ta.ma_type = MCBUS_TYPE_PCI;
+		if (MCPCIA_EXISTS(ta.ma_mid, ta.ma_gid))
+			(void) config_found_sm(self, &ta, mcbusprint,
+					mcbussbm);
+	}
+
+	mcpcia_config_cleanup();
+}
+
+const char *
+mcbus_node_type_str(type)
+	u_int8_t type;
+{
+	switch (type) {
+	case MCBUS_TYPE_RES:
+		panic ("RESERVED TYPE IN MCBUS_NODE_TYPE_STR");
+		break;
+	case MCBUS_TYPE_UNK:
+		panic ("UNKNOWN TYPE IN MCBUS_NODE_TYPE_STR");
+		break;
+	case MCBUS_TYPE_MEM:
+		return ("Memory");
+	case MCBUS_TYPE_CPU:
+		return ("CPU");
+	case MCBUS_TYPE_PCI:
+		return ("PCI Bridge");
+	default:
+		panic("REALLY UNKNWON (%x) TYPE IN MCBUS_NODE_TYPE_STR", type);
+		break;
+	}
+}
diff --git a/sys/arch/alpha/mcbus/mcbusreg.h b/sys/arch/alpha/mcbus/mcbusreg.h
new file mode 100644
index 00000000000..8f345beca94
--- /dev/null
+++ b/sys/arch/alpha/mcbus/mcbusreg.h
@@ -0,0 +1,93 @@
+/* $OpenBSD: mcbusreg.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcbusreg.h,v 1.3 1999/11/16 18:36:27 mjacob Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * 'Register' definitions for the MCBUS main
+ * system bus found on AlphaServer 4100 systems.
+ */
+
+/*
+ * Information gathered from:
+ *
+ * "Rawhide System Programmer's Manual, revision 1.4".
+ */
+
+/*
+ * There are 7 possible MC bus modules (architecture says 10, but
+ * the address map details say otherwise), 1 though 7.
+ * Their uses are defined as follows:
+ *
+ *	MID	Module
+ *	----    ------
+ *	1	Memory
+ *	2	CPU
+ *	3	CPU
+ *	4	CPU, PCI
+ *	5	CPU, PCI
+ *	6	CPU, PCI
+ *	7	CPU, PCI
+ *
+ */
+#define	MCBUS_MID_MAX		7
+
+/*
+ * For this architecture, bit 39 of a 40 bit address controls whether
+ * you access I/O or Memory space. Further, there *could* be multiple
+ * MC busses (but only one specified for now).
+ */
+
+#define	MCBUS_IOSPACE		0x0000008000000000L
+#define MCBUS_GID_MASK          0x0000007000000000L
+#define	MCBUS_GID_SHIFT		36
+#define	MCBUS_MID_MASK		0x0000000E00000000L
+#define	MCBUS_MID_SHIFT		33
+
+#define	MAX_MC_BUS		8
+
+/*
+ * This is something of a layering violation, but it makes probing cleaner.
+ */
+#define	MCPCIA_PER_MCBUS	4
+
+/*
+ * defaults for locators
+ */
+#define MCBUSCF_NLOCS 1
+#define MCBUSCF_MID 0
+#define MCBUSCF_MID_DEFAULT -1  
+
+/* the MCPCIA bridge CSR addresses, offset zero, is a good thing to probe for */
+#define	MCPCIA_BRIDGE_ADDR(gid, mid)	\
+	(MCBUS_IOSPACE | 0x1E0000000LL	|		\
+	(((unsigned long) gid) << MCBUS_GID_SHIFT) |	\
+	(((unsigned long) mid) << MCBUS_MID_SHIFT))
diff --git a/sys/arch/alpha/mcbus/mcbusvar.h b/sys/arch/alpha/mcbus/mcbusvar.h
new file mode 100644
index 00000000000..b77cfcc7190
--- /dev/null
+++ b/sys/arch/alpha/mcbus/mcbusvar.h
@@ -0,0 +1,80 @@
+/* $OpenBSD: mcbusvar.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcbusvar.h,v 1.6 2005/12/11 12:16:17 christos Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Soft definitions for the MCBUS main system
+ * bus found on AlphaServer 4100 systems.
+ */
+
+/*
+ * The structure used to attach devices to the MCbus.
+ */
+struct mcbus_dev_attach_args {
+	char *		ma_name;	/* so things aren't confused */
+	u_int8_t	ma_gid;		/* GID of MCBUS (MCBUS #) */
+	u_int8_t	ma_mid;		/* Module ID on MCBUS */
+	u_int8_t	ma_type;	/* Module "type" */
+	u_int8_t	ma_configured;	/* nonzero if configured */
+};
+#define	MCBUS_GID_FROM_INSTANCE(unit)	(7 - unit)
+
+/*
+ * Bus-dependent structure for CPUs. This is dynamically allocated
+ * for each CPU on the MCbus, and glued into the cpu_softc as sc_busdep,
+ * if there is such a beast available. Otherwise, a single global version
+ * is used so that the MCPCIA configuration code can determine toads
+ * like module id and bcache size of the master CPU.
+ */
+struct mcbus_cpu_busdep {
+	u_int8_t	mcbus_cpu_mid;	/* MCbus Module ID */
+	u_int8_t	mcbus_bcache;	/* BCache on this CPU */
+	u_int8_t	mcbus_valid;
+};
+
+#define	MCBUS_CPU_BCACHE_0MB	0
+#define	MCBUS_CPU_BCACHE_1MB	1
+#define	MCBUS_CPU_BCACHE_4MB	2
+
+/*
+ * "types"
+ */
+#define	MCBUS_TYPE_RES	0
+#define	MCBUS_TYPE_UNK	1
+#define	MCBUS_TYPE_MEM	2
+#define	MCBUS_TYPE_CPU	3
+#define	MCBUS_TYPE_PCI	4
+
+#ifdef _KERNEL
+extern struct mcbus_cpu_busdep mcbus_primary;
+extern const int mcbus_mcpcia_probe_order[];
+#endif
diff --git a/sys/arch/alpha/mcbus/mcmem.c b/sys/arch/alpha/mcbus/mcmem.c
new file mode 100644
index 00000000000..48f2aaea474
--- /dev/null
+++ b/sys/arch/alpha/mcbus/mcmem.c
@@ -0,0 +1,85 @@
+/* $OpenBSD: mcmem.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcmem.c,v 1.4 2002/10/02 04:06:38 thorpej Exp $ */
+
+/*
+ * Copyright (c) 2007 Robert Nagy <robert@openbsd.org>
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * 'dummy' (for now) node for the memory modules attached to
+ * the MCBUS main system bus found on AlphaServer 4100 systems.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+#include <machine/pte.h>
+
+#include <alpha/mcbus/mcbusreg.h>
+#include <alpha/mcbus/mcbusvar.h>
+
+int	mcmemmatch (struct device *, void *, void *);
+void	mcmemattach (struct device *, struct device *, void *);
+
+struct cfattach mcmem_ca = {
+        sizeof(struct device), mcmemmatch, mcmemattach
+};
+
+struct cfdriver mcmem_cd = {
+        NULL, "mcmem", DV_DULL,
+};
+
+int
+mcmemmatch(parent, cf, aux)
+	struct device *parent;
+	void *cf;
+	void *aux;
+{
+	struct mcbus_dev_attach_args *ta = aux;
+
+	if (ta->ma_type == MCBUS_TYPE_MEM)
+		return (1);
+
+	return (0);
+}
+
+void
+mcmemattach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	printf("\n");
+}
diff --git a/sys/arch/alpha/pci/mcpcia.c b/sys/arch/alpha/pci/mcpcia.c
new file mode 100644
index 00000000000..f22133bfe3e
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpcia.c
@@ -0,0 +1,354 @@
+/* $OpenBSD: mcpcia.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpcia.c,v 1.20 2007/03/04 05:59:11 christos Exp $ */
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * MCPCIA mcbus to PCI bus adapter
+ * found on AlphaServer 4100 systems.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <machine/rpb.h>
+#include <machine/sysarch.h>
+
+#include <alpha/mcbus/mcbusreg.h>
+#include <alpha/mcbus/mcbusvar.h>
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+#include <alpha/pci/pci_kn300.h>
+
+#define KV(_addr)	((caddr_t)ALPHA_PHYS_TO_K0SEG((_addr)))
+#define	MCPCIA_SYSBASE(mc)	\
+	((((unsigned long) (mc)->cc_gid) << MCBUS_GID_SHIFT) | \
+	 (((unsigned long) (mc)->cc_mid) << MCBUS_MID_SHIFT) | \
+	 (MCBUS_IOSPACE))
+
+#define	MCPCIA_PROBE(mid, gid)	\
+	badaddr((void *)KV(((((unsigned long) gid) << MCBUS_GID_SHIFT) | \
+	 (((unsigned long) mid) << MCBUS_MID_SHIFT) | \
+	 (MCBUS_IOSPACE) | MCPCIA_PCI_BRIDGE | _MCPCIA_PCI_REV)), \
+	sizeof(u_int32_t))
+
+int	mcpciamatch (struct device *, void *, void *);
+void	mcpciaattach (struct device *, struct device *, void *);
+void	mcpcia_config_cleanup (void);
+
+int	mcpciaprint (void *, const char *);
+
+struct cfattach mcpcia_ca = {
+	sizeof(struct mcpcia_softc), mcpciamatch, mcpciaattach
+};
+
+struct cfdriver mcpcia_cd = {
+        NULL, "mcpcia", DV_DULL,
+};
+
+/*
+ * We have one statically-allocated mcpcia_config structure; this is
+ * the one used for the console (which, coincidentally, is the only
+ * MCPCIA with an EISA adapter attached to it).
+ */
+struct mcpcia_config mcpcia_console_configuration;
+
+int
+mcpciaprint(aux, pnp)
+       void *aux;
+       const char *pnp;
+{
+       register struct pcibus_attach_args *pba = aux;
+       /* only PCIs can attach to MCPCIA for now */
+       if (pnp)
+               printf("%s at %s", pba->pba_busname, pnp);
+       printf(" bus %d", pba->pba_bus);
+       return (UNCONF);
+}
+
+int
+mcpciamatch(parent, cf, aux)
+	struct device *parent;
+	void *cf;
+	void *aux;
+{
+	struct mcbus_dev_attach_args *ma = aux;
+
+	if (ma->ma_type == MCBUS_TYPE_PCI)
+		return (1);
+
+	return (0);
+}
+
+void
+mcpciaattach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	static int first = 1;
+	struct mcbus_dev_attach_args *ma = aux;
+	struct mcpcia_softc *mcp = (struct mcpcia_softc *)self;
+	struct mcpcia_config *ccp;
+	struct pcibus_attach_args pba;
+	u_int32_t ctl;
+
+	/*
+	 * Make sure this MCPCIA exists...
+	 */
+	if (MCPCIA_PROBE(ma->ma_mid, ma->ma_gid)) {
+		mcp->mcpcia_cc = NULL;
+		printf(" (not present)\n");
+		return;
+	}
+	printf("\n");
+
+	/*
+	 * Determine if we're the console's MCPCIA.
+	 */
+	if (ma->ma_mid == mcpcia_console_configuration.cc_mid &&
+	    ma->ma_gid == mcpcia_console_configuration.cc_gid)
+		ccp = &mcpcia_console_configuration;
+	else {
+		ccp = malloc(sizeof(struct mcpcia_config), M_DEVBUF, M_WAITOK);
+		memset(ccp, 0, sizeof(struct mcpcia_config));
+
+		ccp->cc_mid = ma->ma_mid;
+		ccp->cc_gid = ma->ma_gid;
+	}
+	mcp->mcpcia_cc = ccp;
+	ccp->cc_sc = mcp;
+
+	/* This initializes cc_sysbase so we can do register access. */
+	mcpcia_init0(ccp, 1);
+
+	ctl = REGVAL(MCPCIA_PCI_REV(ccp));
+	printf("%s: Horse Revision %d, %s Handed Saddle Revision %d,"
+	    " CAP Revision %d\n", mcp->mcpcia_dev.dv_xname, HORSE_REV(ctl),
+	    (SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl),
+	    CAP_REV(ctl));
+
+	mcpcia_dma_init(ccp);
+
+	/*
+	 * Set up interrupts
+	 */
+	pci_kn300_pickintr(ccp, first);
+	first = 0;
+
+	/*
+	 * Attach PCI bus
+	 */
+	pba.pba_busname = "pci";
+	pba.pba_iot = &ccp->cc_iot;
+	pba.pba_memt = &ccp->cc_memt;
+	pba.pba_dmat =
+	    alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
+	pba.pba_pc = &ccp->cc_pc;
+	pba.pba_domain = pci_ndomains++;
+	pba.pba_bus = 0;
+	pba.pba_bridgetag = NULL;
+
+	(void) config_found(self, &pba, mcpciaprint);
+
+	/*
+	 * Clear any errors that may have occurred during the probe
+	 * sequence.
+	 */
+	REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
+	alpha_mb();
+}
+
+void
+mcpcia_init()
+{
+	struct mcpcia_config *ccp = &mcpcia_console_configuration;
+	int i;
+
+	/*
+	 * Look for all of the MCPCIAs on the system.  One of them
+	 * will have an EISA attached to it.  This MCPCIA is the
+	 * only one that can be used for the console.  Once we find
+	 * that one, initialize it.
+	 */
+	for (i = 0; i < MCPCIA_PER_MCBUS; i++) {
+		ccp->cc_mid = mcbus_mcpcia_probe_order[i];
+		/*
+		 * XXX If we ever support more than one MCBUS, we'll
+		 * XXX have to probe for them, and map them to unit
+		 * XXX numbers.
+		 */
+		ccp->cc_gid = MCBUS_GID_FROM_INSTANCE(0);
+		ccp->cc_sysbase = MCPCIA_SYSBASE(ccp);
+
+		if (badaddr((void *)ALPHA_PHYS_TO_K0SEG(MCPCIA_PCI_REV(ccp)),
+		    sizeof(u_int32_t)))
+			continue;
+
+		if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) {
+			mcpcia_init0(ccp, 0);
+			return;
+		}
+	}
+
+	panic("mcpcia_init: unable to find EISA bus");
+}
+
+void
+mcpcia_init0(ccp, mallocsafe)
+	struct mcpcia_config *ccp;
+	int mallocsafe;
+{
+	u_int32_t ctl;
+	
+	snprintf(ccp->pc_io_ex_name, sizeof ccp->pc_io_ex_name,
+	    "mcpcia%d_bus_io", ccp->cc_mid);
+	snprintf(ccp->pc_mem_dex_name, sizeof ccp->pc_mem_dex_name,
+	    "mcpciad%d_bus_mem", ccp->cc_mid);
+	snprintf(ccp->pc_mem_dex_name, sizeof ccp->pc_mem_sex_name,
+	    "mcpcias%d_bus_mem", ccp->cc_mid);
+
+	if (!ccp->cc_initted) {
+		/* don't do these twice since they set up extents */
+		mcpcia_bus_io_init(&ccp->cc_iot, ccp);
+		mcpcia_bus_mem_init(&ccp->cc_memt, ccp);
+	}
+	ccp->cc_mallocsafe = mallocsafe;
+
+	mcpcia_pci_init(&ccp->cc_pc, ccp);
+
+        /*
+         * Establish a precalculated base for convenience's sake.
+         */
+        ccp->cc_sysbase = MCPCIA_SYSBASE(ccp);
+
+        /*
+         * Disable interrupts and clear errors prior to probing
+         */
+        REGVAL(MCPCIA_INT_MASK0(ccp)) = 0;
+        REGVAL(MCPCIA_INT_MASK1(ccp)) = 0;
+        REGVAL(MCPCIA_CAP_ERR(ccp)) = 0xFFFFFFFF;
+        alpha_mb();
+
+        if (ccp == &mcpcia_console_configuration) {
+                /*
+                 * Use this opportunity to also find out the MID and CPU
+                 * type of the currently running CPU (that's us, billybob....)
+                 */
+                ctl = REGVAL(MCPCIA_WHOAMI(ccp));
+                mcbus_primary.mcbus_cpu_mid = MCBUS_CPU_MID(ctl);
+                if ((MCBUS_CPU_INFO(ctl) & CPU_Fill_Err) == 0 &&
+                    mcbus_primary.mcbus_valid == 0) {
+                        mcbus_primary.mcbus_bcache =
+                            MCBUS_CPU_INFO(ctl) & CPU_BCacheMask;
+                        mcbus_primary.mcbus_valid = 1;
+                }
+                alpha_mb();
+        }
+
+	alpha_pci_chipset = &ccp->cc_pc;
+	alpha_pci_chipset->pc_name = "mcpcia";
+	alpha_pci_chipset->pc_hae_mask = 0;
+	alpha_pci_chipset->pc_dense = MCPCIA_PCI_DENSE;
+	
+        ccp->cc_initted = 1;
+}
+
+void
+mcpcia_config_cleanup()
+{
+	volatile u_int32_t ctl;
+	struct mcpcia_softc *mcp;
+	struct mcpcia_config *ccp;
+	int i;
+	extern struct cfdriver mcpcia_cd;
+
+	/*
+	 * Turn on Hard, Soft error interrupts. Maybe i2c too.
+	 */
+	for (i = 0; i < mcpcia_cd.cd_ndevs; i++) {
+		if ((mcp = mcpcia_cd.cd_devs[i]) == NULL)
+			continue;
+		
+		ccp = mcp->mcpcia_cc;
+		if (ccp == NULL)
+			continue;
+
+		ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
+		ctl |= MCPCIA_GEN_IENABL;
+		REGVAL(MCPCIA_INT_MASK0(ccp)) = ctl;
+		alpha_mb();
+
+		/* force stall while write completes */
+		ctl = REGVAL(MCPCIA_INT_MASK0(ccp));
+	}
+}
diff --git a/sys/arch/alpha/pci/mcpcia_bus_io.c b/sys/arch/alpha/pci/mcpcia_bus_io.c
new file mode 100644
index 00000000000..aa39c1bbada
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpcia_bus_io.c
@@ -0,0 +1,76 @@
+/* $OpenBSD: mcpcia_bus_io.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpcia_bus_io.c,v 1.3 2000/06/29 08:58:47 mrg Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+
+#define	CHIP		mcpcia
+
+#define	CHIP_EX_MALLOC_SAFE(v)	(((struct mcpcia_config *)(v))->cc_mallocsafe)
+#define	CHIP_IO_EXTENT(v)	(((struct mcpcia_config *)(v))->cc_io_ex)
+#define	CHIP_IO_EX_STORE(v)	(((struct mcpcia_config *)(v))->cc_io_exstorage)
+#define	CHIP_IO_EX_STORE_SIZE(v)					\
+	(sizeof (((struct mcpcia_config *)(v))->cc_io_exstorage))
+
+/* IO Region 1 */
+#define	CHIP_IO_W1_BUS_START(v)	0x00000000UL
+#define	CHIP_IO_W1_BUS_END(v)	0x0000ffffUL
+#define	CHIP_IO_W1_SYS_START(v)						\
+	(((struct mcpcia_config *)(v))->cc_sysbase | MCPCIA_PCI_IOSPACE)
+#define	CHIP_IO_W1_SYS_END(v)						\
+	(CHIP_IO_W1_SYS_START(v) + ((CHIP_IO_W1_BUS_END(v) + 1) << 5) - 1)
+
+/* IO Region 2 */
+#define	CHIP_IO_W2_BUS_START(v)	0x00010000UL
+#define	CHIP_IO_W2_BUS_END(v)	0x01ffffffUL
+#define	CHIP_IO_W2_SYS_START(v)						\
+	(((struct mcpcia_config *)(v))->cc_sysbase + MCPCIA_PCI_IOSPACE + \
+	    (0x00010000 << 5))
+#define	CHIP_IO_W2_SYS_END(v)						\
+	((CHIP_IO_W1_SYS_START(v) + ((CHIP_IO_W2_BUS_END(v) + 1) << 5) - 1))
+
+#define CHIP_EXTENT_NAME(v)		((struct mcpcia_config *)(v))->pc_io_ex_name
+#define CHIP_EXTENT_STORAGE(v)		((struct mcpcia_config *)(v))->pc_io_ex_storage
+
+#include "alpha/pci/pci_swiz_bus_io_chipdep.c"
diff --git a/sys/arch/alpha/pci/mcpcia_bus_mem.c b/sys/arch/alpha/pci/mcpcia_bus_mem.c
new file mode 100644
index 00000000000..b684e4241a4
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpcia_bus_mem.c
@@ -0,0 +1,92 @@
+/* $OpenBSD: mcpcia_bus_mem.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpcia_bus_mem.c,v 1.3 2000/06/29 08:58:47 mrg Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/syslog.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+
+#define	CHIP		mcpcia
+
+#define	CHIP_EX_MALLOC_SAFE(v)	(((struct mcpcia_config *)(v))->cc_mallocsafe)
+#define	CHIP_D_MEM_EXTENT(v)	(((struct mcpcia_config *)(v))->cc_d_mem_ex)
+#define	CHIP_D_MEM_EX_STORE(v)						\
+	(((struct mcpcia_config *)(v))->cc_dmem_exstorage)
+#define	CHIP_D_MEM_EX_STORE_SIZE(v)					\
+	(sizeof (((struct mcpcia_config *)(v))->cc_dmem_exstorage))
+#define	CHIP_S_MEM_EXTENT(v)	(((struct mcpcia_config *)(v))->cc_s_mem_ex)
+#define	CHIP_S_MEM_EX_STORE(v)						\
+	(((struct mcpcia_config *)(v))->cc_smem_exstorage)
+#define	CHIP_S_MEM_EX_STORE_SIZE(v)					\
+	(sizeof (((struct mcpcia_config *)(v))->cc_smem_exstorage))
+
+/* Dense region 1 */
+#define	CHIP_D_MEM_W1_BUS_START(v)	0x00000000UL
+#define	CHIP_D_MEM_W1_BUS_END(v)	0x7fffffffUL
+#define	CHIP_D_MEM_W1_SYS_START(v)					\
+	(((struct mcpcia_config *)(v))->cc_sysbase | MCPCIA_PCI_DENSE)
+#define	CHIP_D_MEM_W1_SYS_END(v)					\
+	(CHIP_D_MEM_W1_SYS_START(v) + 0x7fffffffUL)
+
+/* Sparse region 1 */
+#define	CHIP_S_MEM_W1_BUS_START(v)	0x00000000UL
+#define	CHIP_S_MEM_W1_BUS_END(v)	0x00ffffffUL
+#define	CHIP_S_MEM_W1_SYS_START(v)					\
+	(((struct mcpcia_config *)(v))->cc_sysbase | MCPCIA_PCI_SPARSE)
+#define	CHIP_S_MEM_W1_SYS_END(v)					\
+	(CHIP_S_MEM_W1_SYS_START(v) + ((CHIP_S_MEM_W1_BUS_END(v) + 1) << 5) - 1)
+
+/* Sparse region 2 */
+#define	CHIP_S_MEM_W2_BUS_START(v)	0x01000000UL
+#define	CHIP_S_MEM_W2_BUS_END(v)	0x07FFFFFFUL
+#define	CHIP_S_MEM_W2_SYS_START(v)					\
+	((((struct mcpcia_config *)(v))->cc_sysbase|MCPCIA_PCI_SPARSE) + \
+	(0x01000000UL<<5))
+#define	CHIP_S_MEM_W2_SYS_END(v)					\
+	(CHIP_S_MEM_W1_SYS_START(v) + ((CHIP_S_MEM_W2_BUS_END(v) + 1) << 5) - 1)
+
+#define CHIP_EXTENT_DNAME(v)		((struct mcpcia_config *)(v))->pc_mem_dex_name
+#define CHIP_EXTENT_SNAME(v)		((struct mcpcia_config *)(v))->pc_mem_sex_name
+#define CHIP_EXTENT_DSTORAGE(v)		((struct mcpcia_config *)(v))->pc_mem_dex_storage
+#define CHIP_EXTENT_SSTORAGE(v)		((struct mcpcia_config *)(v))->pc_mem_sex_storage
+
+#include "alpha/pci/pci_swiz_bus_mem_chipdep.c"
diff --git a/sys/arch/alpha/pci/mcpcia_dma.c b/sys/arch/alpha/pci/mcpcia_dma.c
new file mode 100644
index 00000000000..50f0fbfe203
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpcia_dma.c
@@ -0,0 +1,395 @@
+/* $OpenBSD: mcpcia_dma.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpcia_dma.c,v 1.15 2001/07/19 18:55:40 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe and Matthew Jacob of the Numerical Aerospace Simulation
+ * Facility, NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define _ALPHA_BUS_DMA_PRIVATE
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/rpb.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+#include <alpha/pci/pci_kn300.h>
+
+bus_dma_tag_t mcpcia_dma_get_tag (bus_dma_tag_t, alpha_bus_t);
+
+int	mcpcia_bus_dmamap_load_sgmap (bus_dma_tag_t, bus_dmamap_t, void *,
+	    bus_size_t, struct proc *, int);
+
+int	mcpcia_bus_dmamap_load_mbuf_sgmap (bus_dma_tag_t, bus_dmamap_t,
+	    struct mbuf *, int);
+
+int	mcpcia_bus_dmamap_load_uio_sgmap (bus_dma_tag_t, bus_dmamap_t,
+	    struct uio *, int);
+
+int	mcpcia_bus_dmamap_load_raw_sgmap (bus_dma_tag_t, bus_dmamap_t,
+	    bus_dma_segment_t *, int, bus_size_t, int);
+
+void	mcpcia_bus_dmamap_unload_sgmap (bus_dma_tag_t, bus_dmamap_t);
+
+/*
+ * Direct-mapped window: 2G at 2G
+ */
+#define	MCPCIA_DIRECT_MAPPED_BASE	(2UL*1024UL*1024UL*1024UL)
+#define	MCPCIA_DIRECT_MAPPED_SIZE	(2UL*1024UL*1024UL*1024UL)
+
+/*
+ * SGMAP window for PCI: 1G at 1G
+ */
+#define	MCPCIA_PCI_SG_MAPPED_BASE	(1UL*1024UL*1024UL*1024UL)
+#define	MCPCIA_PCI_SG_MAPPED_SIZE	(1UL*1024UL*1024UL*1024UL)
+
+/*
+ * SGMAP window for ISA: 8M at 8M
+ */
+#define	MCPCIA_ISA_SG_MAPPED_BASE	(8*1024*1024)
+#define	MCPCIA_ISA_SG_MAPPED_SIZE	(8*1024*1024)
+
+/* MCPCIA has a 256-byte out-bound DMA prefetch threshold. */
+#define	MCPCIA_SG_MAPPED_PFTHRESH	256
+
+#define	MCPCIA_SGTLB_INVALIDATE(ccp)					\
+do {									\
+	alpha_mb();							\
+	REGVAL(MCPCIA_SG_TBIA(ccp)) = 0xdeadbeef;			\
+	alpha_mb();							\
+} while (0)
+
+void
+mcpcia_dma_init(ccp)
+	struct mcpcia_config *ccp;
+{
+	bus_dma_tag_t t;
+
+	/*
+	 * Initialize the DMA tag used for direct-mapped DMA.
+	 */
+	t = &ccp->cc_dmat_direct;
+	t->_cookie = ccp;
+	t->_wbase = MCPCIA_DIRECT_MAPPED_BASE;
+	t->_wsize = MCPCIA_DIRECT_MAPPED_SIZE;
+	t->_next_window = &ccp->cc_dmat_pci_sgmap;
+	t->_boundary = 0;
+	t->_sgmap = NULL;
+	t->_get_tag = mcpcia_dma_get_tag;
+	t->_dmamap_create = _bus_dmamap_create;
+	t->_dmamap_destroy = _bus_dmamap_destroy;
+	t->_dmamap_load = _bus_dmamap_load_direct;
+	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
+	t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
+	t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
+	t->_dmamap_unload = _bus_dmamap_unload;
+	t->_dmamap_sync = _bus_dmamap_sync;
+
+	t->_dmamem_alloc = _bus_dmamem_alloc;
+	t->_dmamem_free = _bus_dmamem_free;
+	t->_dmamem_map = _bus_dmamem_map;
+	t->_dmamem_unmap = _bus_dmamem_unmap;
+	t->_dmamem_mmap = _bus_dmamem_mmap;
+
+	/*
+	 * Initialize the DMA tag used for sgmap-mapped PCI DMA.
+	 */
+	t = &ccp->cc_dmat_pci_sgmap;
+	t->_cookie = ccp;
+	t->_wbase = MCPCIA_PCI_SG_MAPPED_BASE;
+	t->_wsize = MCPCIA_PCI_SG_MAPPED_SIZE;
+	t->_next_window = NULL;
+	t->_boundary = 0;
+	t->_sgmap = &ccp->cc_pci_sgmap;
+	t->_pfthresh = MCPCIA_SG_MAPPED_PFTHRESH;
+	t->_get_tag = mcpcia_dma_get_tag;
+	t->_dmamap_create = alpha_sgmap_dmamap_create;
+	t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
+	t->_dmamap_load = mcpcia_bus_dmamap_load_sgmap;
+	t->_dmamap_load_mbuf = mcpcia_bus_dmamap_load_mbuf_sgmap;
+	t->_dmamap_load_uio = mcpcia_bus_dmamap_load_uio_sgmap;
+	t->_dmamap_load_raw = mcpcia_bus_dmamap_load_raw_sgmap;
+	t->_dmamap_unload = mcpcia_bus_dmamap_unload_sgmap;
+	t->_dmamap_sync = _bus_dmamap_sync;
+
+	t->_dmamem_alloc = _bus_dmamem_alloc;
+	t->_dmamem_free = _bus_dmamem_free;
+	t->_dmamem_map = _bus_dmamem_map;
+	t->_dmamem_unmap = _bus_dmamem_unmap;
+	t->_dmamem_mmap = _bus_dmamem_mmap;
+
+	/*
+	 * Initialize the DMA tag used for sgmap-mapped ISA DMA.
+	 */
+	t = &ccp->cc_dmat_isa_sgmap;
+	t->_cookie = ccp;
+	t->_wbase = MCPCIA_ISA_SG_MAPPED_BASE;
+	t->_wsize = MCPCIA_ISA_SG_MAPPED_SIZE;
+	t->_next_window = NULL;
+	t->_boundary = 0;
+	t->_sgmap = &ccp->cc_isa_sgmap;
+	t->_pfthresh = MCPCIA_SG_MAPPED_PFTHRESH;
+	t->_get_tag = mcpcia_dma_get_tag;
+	t->_dmamap_create = alpha_sgmap_dmamap_create;
+	t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
+	t->_dmamap_load = mcpcia_bus_dmamap_load_sgmap;
+	t->_dmamap_load_mbuf = mcpcia_bus_dmamap_load_mbuf_sgmap;
+	t->_dmamap_load_uio = mcpcia_bus_dmamap_load_uio_sgmap;
+	t->_dmamap_load_raw = mcpcia_bus_dmamap_load_raw_sgmap;
+	t->_dmamap_unload = mcpcia_bus_dmamap_unload_sgmap;
+	t->_dmamap_sync = _bus_dmamap_sync;
+
+	t->_dmamem_alloc = _bus_dmamem_alloc;
+	t->_dmamem_free = _bus_dmamem_free;
+	t->_dmamem_map = _bus_dmamem_map;
+	t->_dmamem_unmap = _bus_dmamem_unmap;
+	t->_dmamem_mmap = _bus_dmamem_mmap;
+
+	/*
+	 * Initialize the SGMAPs.
+	 */
+	alpha_sgmap_init(&ccp->cc_dmat_pci_sgmap, &ccp->cc_pci_sgmap,
+	    "mcpcia pci sgmap",
+	    MCPCIA_PCI_SG_MAPPED_BASE, 0, MCPCIA_PCI_SG_MAPPED_SIZE,
+	    sizeof(u_int64_t), NULL, 0);
+
+	alpha_sgmap_init(&ccp->cc_dmat_isa_sgmap, &ccp->cc_isa_sgmap,
+	    "mcpcia isa sgmap",
+	    MCPCIA_ISA_SG_MAPPED_BASE, 0, MCPCIA_ISA_SG_MAPPED_SIZE,
+	    sizeof(u_int64_t), NULL, 0);
+
+	/*
+	 * Disable windows first.
+	 */
+	REGVAL(MCPCIA_W0_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_W1_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_W2_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_W3_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_T0_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_T2_BASE(ccp)) = 0;
+	REGVAL(MCPCIA_T3_BASE(ccp)) = 0;
+	alpha_mb();
+
+	/*
+	 * Set up window 0 as an 8MB SGMAP-mapped window starting at 8MB.
+	 */
+	REGVAL(MCPCIA_W0_MASK(ccp)) = MCPCIA_WMASK_8M;
+	REGVAL(MCPCIA_T0_BASE(ccp)) =
+		ccp->cc_isa_sgmap.aps_ptpa >> MCPCIA_TBASEX_SHIFT;
+	alpha_mb();
+	REGVAL(MCPCIA_W0_BASE(ccp)) =
+		MCPCIA_WBASE_EN | MCPCIA_WBASE_SG | MCPCIA_ISA_SG_MAPPED_BASE;
+	alpha_mb();
+
+	MCPCIA_SGTLB_INVALIDATE(ccp);
+
+	/*
+	 * Set up window 1 as a 2 GB Direct-mapped window starting at 2GB.
+	 */
+	REGVAL(MCPCIA_W1_MASK(ccp)) = MCPCIA_WMASK_2G;
+	REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
+	alpha_mb();
+	REGVAL(MCPCIA_W1_BASE(ccp)) =
+		MCPCIA_DIRECT_MAPPED_BASE | MCPCIA_WBASE_EN;
+	alpha_mb();
+
+	/*
+	 * Set up window 2 as a 1G SGMAP-mapped window starting at 1G.
+	 */
+	REGVAL(MCPCIA_W2_MASK(ccp)) = MCPCIA_WMASK_1G;
+	REGVAL(MCPCIA_T2_BASE(ccp)) =
+		ccp->cc_pci_sgmap.aps_ptpa >> MCPCIA_TBASEX_SHIFT;
+	alpha_mb();
+	REGVAL(MCPCIA_W2_BASE(ccp)) =
+		MCPCIA_WBASE_EN | MCPCIA_WBASE_SG | MCPCIA_PCI_SG_MAPPED_BASE;
+	alpha_mb();
+
+	/* XXX XXX BEGIN XXX XXX */
+	{							/* XXX */
+		extern paddr_t alpha_XXX_dmamap_or;		/* XXX */
+		alpha_XXX_dmamap_or = MCPCIA_DIRECT_MAPPED_BASE;/* XXX */
+	}							/* XXX */
+	/* XXX XXX END XXX XXX */
+}
+
+/*
+ * Return the bus dma tag to be used for the specified bus type.
+ * INTERNAL USE ONLY!
+ */
+bus_dma_tag_t
+mcpcia_dma_get_tag(t, bustype)
+	bus_dma_tag_t t;
+	alpha_bus_t bustype;
+{
+	struct mcpcia_config *ccp = t->_cookie;
+
+	switch (bustype) {
+	case ALPHA_BUS_PCI:
+	case ALPHA_BUS_EISA:
+		/*
+		 * Start off using the direct-mapped window.  We will
+		 * automatically fall backed onto the chained PCI SGMAP
+		 * window if necessary.
+		 */
+		return (&ccp->cc_dmat_direct);
+
+	case ALPHA_BUS_ISA:
+		/*
+		 * ISA doesn't have enough address bits to use
+		 * the direct-mapped DMA window, so we must use
+		 * SGMAPs.
+		 */
+		return (&ccp->cc_dmat_isa_sgmap);
+
+	default:
+		panic("mcpcia_dma_get_tag: shouldn't be here, really...");
+	}
+}
+
+/*
+ * Load a MCPCIA SGMAP-mapped DMA map with a linear buffer.
+ */
+int
+mcpcia_bus_dmamap_load_sgmap(t, map, buf, buflen, p, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	void *buf;
+	bus_size_t buflen;
+	struct proc *p;
+	int flags;
+{
+	int error;
+	struct mcpcia_config *ccp = t->_cookie;
+
+	error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags,
+	    t->_sgmap);
+	if (error == 0)
+		MCPCIA_SGTLB_INVALIDATE(ccp);
+	return (error);
+}
+
+/*
+ * Load a MCPCIA SGMAP-mapped DMA map with an mbuf chain.
+ */
+int
+mcpcia_bus_dmamap_load_mbuf_sgmap(t, map, m, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	struct mbuf *m;
+	int flags;
+{
+	int error;
+	struct mcpcia_config *ccp = t->_cookie;
+
+	error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap);
+	if (error == 0)
+		MCPCIA_SGTLB_INVALIDATE(ccp);
+	return (error);
+}
+
+/*
+ * Load a MCPCIA SGMAP-mapped DMA map with a uio.
+ */
+int
+mcpcia_bus_dmamap_load_uio_sgmap(t, map, uio, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	struct uio *uio;
+	int flags;
+{
+	int error;
+	struct mcpcia_config *ccp = t->_cookie;
+
+	error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap);
+	if (error == 0)
+		MCPCIA_SGTLB_INVALIDATE(ccp);
+	return (error);
+}
+
+/*
+ * Load a MCPCIA SGMAP-mapped DMA map with raw memory.
+ */
+int
+mcpcia_bus_dmamap_load_raw_sgmap(t, map, segs, nsegs, size, flags)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+	bus_dma_segment_t *segs;
+	int nsegs;
+	bus_size_t size;
+	int flags;
+{
+	int error;
+	struct mcpcia_config *ccp = t->_cookie;
+
+	error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags,
+	    t->_sgmap);
+	if (error == 0)
+		MCPCIA_SGTLB_INVALIDATE(ccp);
+	return (error);
+}
+
+/*
+ * Unload a MCPCIA DMA map.
+ */
+void
+mcpcia_bus_dmamap_unload_sgmap(t, map)
+	bus_dma_tag_t t;
+	bus_dmamap_t map;
+{
+	struct mcpcia_config *ccp = t->_cookie;
+
+	/*
+	 * Invalidate any SGMAP page table entries used by this mapping.
+	 */
+	pci_sgmap_pte64_unload(t, map, t->_sgmap);
+	MCPCIA_SGTLB_INVALIDATE(ccp);
+
+	/*
+	 * Do the generic bits of the unload.
+	 */
+	_bus_dmamap_unload(t, map);
+}
diff --git a/sys/arch/alpha/pci/mcpcia_pci.c b/sys/arch/alpha/pci/mcpcia_pci.c
new file mode 100644
index 00000000000..ccc0b7b978a
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpcia_pci.c
@@ -0,0 +1,174 @@
+/* $OpenBSD: mcpcia_pci.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpcia_pci.c,v 1.5 2007/03/04 05:59:11 christos Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+
+#define	KV(_addr)	((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
+
+static void mcpcia_attach_hook (struct device *, struct device *,
+	struct pcibus_attach_args *);
+static int
+mcpcia_bus_maxdevs (void *, int);
+static pcitag_t
+mcpcia_make_tag (void *, int, int, int);
+static void
+mcpcia_decompose_tag (void *, pcitag_t, int *, int *, int *);
+static pcireg_t
+mcpcia_conf_read (void *, pcitag_t, int);
+static void
+mcpcia_conf_write (void *, pcitag_t, int, pcireg_t);
+
+void
+mcpcia_pci_init(pc, v)
+	pci_chipset_tag_t pc;
+	void *v;
+{
+	pc->pc_conf_v = v;
+	pc->pc_attach_hook = mcpcia_attach_hook;
+	pc->pc_bus_maxdevs = mcpcia_bus_maxdevs;
+	pc->pc_make_tag = mcpcia_make_tag;
+	pc->pc_decompose_tag = mcpcia_decompose_tag;
+	pc->pc_conf_read = mcpcia_conf_read;
+	pc->pc_conf_write = mcpcia_conf_write;
+}
+
+static void
+mcpcia_attach_hook(parent, self, pba)
+	struct device *parent, *self;
+	struct pcibus_attach_args *pba;
+{
+}
+
+static int
+mcpcia_bus_maxdevs(cpv, busno)
+	void *cpv;
+	int busno;
+{
+	return (MCPCIA_MAXDEV);
+}
+
+static pcitag_t
+mcpcia_make_tag(cpv, b, d, f)
+	void *cpv;
+	int b, d, f;
+{
+	pcitag_t tag;
+	tag = (b << 21) | (d << 16) | (f << 13);
+	return (tag);
+}
+
+static void
+mcpcia_decompose_tag(cpv, tag, bp, dp, fp)
+	void *cpv;
+	pcitag_t tag;
+	int *bp, *dp, *fp;
+{
+	if (bp != NULL)
+		*bp = (tag >> 21) & 0xff;
+	if (dp != NULL)
+		*dp = (tag >> 16) & 0x1f;
+	if (fp != NULL)
+		*fp = (tag >> 13) & 0x7;
+}
+
+static pcireg_t
+mcpcia_conf_read(cpv, tag, offset)
+	void *cpv;
+	pcitag_t tag;
+	int offset;
+{
+	struct mcpcia_config *ccp = cpv;
+	pcireg_t *dp, data = (pcireg_t) -1;
+	unsigned long paddr;
+
+	/*
+	 * There's nothing in slot 0 on a primary bus- don't even try.
+	 */
+	if ((tag >> 21) == 0 && ((u_int32_t) tag & 0x1f0000) == 0)
+		return (data);
+
+	if (ccp == NULL) {
+		panic("NULL ccp in mcpcia_conf_read");
+	}
+	paddr =	(unsigned long) tag;
+	paddr |= (3LL << 3);	/* 32 Bit PCI byte enables */
+	paddr |= ((unsigned long) ((offset >> 2) << 7));
+	paddr |= MCPCIA_PCI_CONF;
+	paddr |= ccp->cc_sysbase;
+	dp = (pcireg_t *)KV(paddr);
+	if (badaddr(dp, sizeof (*dp)) == 0) {
+		data = *dp;
+	}
+	return (data);
+}
+
+static void
+mcpcia_conf_write(cpv, tag, offset, data)
+	void *cpv;
+	pcitag_t tag;
+	int offset;
+	pcireg_t data;
+{
+	struct mcpcia_config *ccp = cpv;
+	pcireg_t *dp;
+	unsigned long paddr;
+
+	/*
+	 * There's nothing in slot 0 on a primary bus- don't even try.
+	 */
+	if ((tag >> 21) == 0 && ((u_int32_t) tag & 0x1f0000) == 0)
+		return;
+
+	if (ccp == NULL) {
+		panic("NULL ccp in mcpcia_conf_write");
+	}
+	paddr =	(unsigned long) tag;
+	paddr |= (3LL << 3);	/* 32 Bit PCI byte enables */
+	paddr |= ((unsigned long) ((offset >> 2) << 7));
+	paddr |= MCPCIA_PCI_CONF;
+	paddr |= ccp->cc_sysbase;
+
+	dp = (pcireg_t *)KV(paddr);
+	*dp = data;
+}
diff --git a/sys/arch/alpha/pci/mcpciareg.h b/sys/arch/alpha/pci/mcpciareg.h
new file mode 100644
index 00000000000..db55206056e
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpciareg.h
@@ -0,0 +1,443 @@
+/* $OpenBSD: mcpciareg.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpciareg.h,v 1.7 2006/05/17 21:32:59 drochner Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Taken from:
+ *
+ *	``RAWHIDE Systems Programmer's Manual, Revision 1.4''
+ */
+
+#define	REGVAL(r)	(*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
+
+/*
+ * There are 4 possible PCI busses per MCBUS.
+ *
+ * (from mcpcia.h, Digital Unix 4.0E):
+ *
+ * I/O Space Per PCI Node (8GBytes per)
+ * ------------------------------------
+ * (8+x)8 0000 0000 - (8+x)9 FFFF FFFF  - I/O Space for PCI0
+ * (8+x)A 0000 0000 - (8+x)B FFFF FFFF  - I/O Space for PCI1
+ * (8+x)C 0000 0000 - (8+x)D FFFF FFFF  - I/O Space for PCI2
+ * (8+x)E 0000 0000 - (8+x)F FFFF FFFF  - I/O Space for PCI3
+ *
+ * CPU to PCI Address Mapping:
+ * ---------------------------
+ *
+ * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
+ * | 1 |  GID  |  MID  |  |  |  |  |  |  | Byte Aligned  | Byte Len | Zero|
+ * |   |       |       |  |  |  |  |  |  | I/O Address   |   Field  |     |
+ * +---+-------+-------+--+--+--+--+--+--+---------------+----------+-----+
+ *  39  38   36 35   33 32 31 30 29 28 27 26            5 4        3  2  0
+ *
+ * <39> - I/O Select (Always 1 for direct I/O access)
+ *
+ * <38-36> - Global Bus slot # (MCBUS #)
+ *      GID slot #0->7 (MCBUS #0->7)
+ *
+ * <35-33> - MCBUS Slot #
+ *      MCBUS slot 0->7
+ *
+ * <32-27> - PCI Address Space
+ *      0.xxxxx = Sparse Memory Space   (  4GB on MCBUS; 128MB on PCI)
+ *      1.0xxxx = Dense Memory Space    (  2GB on MCBUS;   2GB on PCI)
+ *      1.10xxx = Sparse IO Space       (  1GB on MCBUS;  32MB on PCI)
+ *      1.110xx = Sparse Config Space   (512MB on MCBUS;  16MB on PCI)
+ *      1.1110x = PCI Bridge CSR Space  (256MB on MCBUS) -- Sparse-mapped!
+ *      1.11110 = Interrupt Acknowledge (128MB on MCBUS)
+ *      1.11111 = Unused                (128MB on MCBUS)
+ *
+ * ------------------------------------------------------------
+ * CPU to PCI Address Mapping for MCBUS-PCIy Bridge on MCBUS x:
+ * ------------------------------------------------------------    
+ * 
+ * CPU Address Range            PCI Address Range       PCI Address Space
+ * ------------------------     ---------------------   ------------------------
+ * (8+x)(8+y*2).0000.0000       0000.0000 - 00FF.FFFF   PCIy Sparse Memory Space
+ * - (8+x)(8+y*2).1FFF.FFFF                              (fixed, lower 16MB)
+ * 
+ * (8+x)(8+y*2).2000.0000       0100.0000 - 07FF.FFFF   PCIy Sparse Memory Space
+ * - (8+x)(8+y*2).FFFF.FFFF                              (variable, offset = 0)
+ * 
+ * (8+x)(9+y*2).0000.0000       0000.0000 - 7FFF.FFFF   PCIy Dense Memory Space
+ * - (8+x)(9+y*2).7FFF.FFFF  or 8000.0000 - FFFF.FFFF      if HAE_DENSE_MEM = 1
+ * 
+ * (8+x)(9+y*2).8000.0000       0000.0000 - 0000.FFFF   PCIy Sparse IO Space
+ * - (8+x)(9+y*2).801F.FFFF                              (fixed, lower 64K)
+ * 
+ * (8+x)(9+y*2).8020.0000       0001.0000 - 01FF.FFFF   PCIy Sparse IO Space
+ * - (8+x)(9+y*2).BFFF.FFFF                              (variable, offset = 0)
+ * 
+ * (8+x)(9+y*2).C000.0000       0000.0000 - 0FFF.FFFF   PCIy Config Space (16MB)
+ * - (8+x)(9+y*2).DFFF.FFFF
+ * 
+ * (8+x)(9+y*2).E000.0000               N/A             PCIy-Bridge CSR Space
+ *							(8MB)
+ * - (8+x)(9+y*2).EFFF.FFFF 
+ *
+ * (8+x)(9+y*2).F000.0000               N/A             Unused
+ * - (8+x)(9+y*2).F000.3EFF
+ *
+ * (8+x)(9+y*2).F000.3F00,              N/A             PCIy Interrupt ACK0
+ * (8+x)(9+y*2).F000.3F40                               PCIy INteruppt ACK1
+ *
+ * (8+x)(9+y*2).F000.3F80               N/A             Unused
+ * - (8+x)(9+y*2).FFFF.FFFF
+ *
+ */
+
+/*                                                       
+ * MC-PCI Bus Bridge CSRs
+ *                           
+ * Address Map Overview:
+ *
+ * Offset                Selected Space
+ * ----------------      -------------------------------------------------
+ * 0x00000000            General config, control, diag, error logging regs.
+ * 0x00001000            PCI Error Status
+ * 0x00001300            PCI Scatter/Gather Regs.
+ * 0x00001800            Scatter/Gather TLB Regs.        
+ * 0x00004000            MDPA Error Status & Diagnostic Control
+ * 0x00008000            MDPB Error Status & Diagnostic Control
+ * 0x000E0000 -          Flash Rom Space --
+ * 0x000FFFFF            offset address into PCI Dense Mem Space
+ * 0x10003F00            Interrupt Acknowledge
+ * 
+ */
+
+
+/*
+ * Address Space Cookies
+ */
+
+#define	MCPCIA_PCI_SPARSE	0x000000000UL
+#define	MCPCIA_PCI_DENSE	0x100000000UL
+#define	MCPCIA_PCI_IOSPACE	0x180000000UL
+#define	MCPCIA_PCI_CONF		0x1C0000000UL
+#define	MCPCIA_PCI_BRIDGE	0x1E0000000UL
+#define	MCPCIA_PCI_IACK		0x1F0000000UL
+
+/*
+ * MCPCIA Bus Bridge Registers
+ *
+ * These are offsets that don't include GBUS, MID, or address space offsets.
+ */
+
+#define	_MCPCIA_PCI_REV		0x000000000	/* PCI Revision Register (R) */
+#define	_MCPCIA_WHOAMI		0x000000040	/* PCI Who Am I (R) */
+#define	_MCPCIA_PCI_LAT		0x000000080	/* PCI Latency Timer (RW) */
+#define	_MCPCIA_CAP_CTRL	0x000000100	/* PCI Bridge Control (RW) */
+#define	_MCPCIA_HAE_MEM		0x000000400	/* PCI HAE Sparse Memory (RW) */
+#define	_MCPCIA_HAE_IO		0x000000440	/* PCI HAE Sparse I/O (RW) */
+#define	_MCPCIA_IACK_SC		0x000000480	/* PCI Special Cycle Ack */
+#define	_MCPCIA_HAE_DENSE	0x0000004C0	/* PCI HAE Dense Memory (RW) */
+
+#define	_MCPCIA_INT_CTL		0x000000500	/* PCI Interrupt Control */
+#define	_MCPCIA_INT_REQ		0x000000540	/* PCI Interrupt Request */
+#define	_MCPCIA_INT_TARG	0x000000580	/* PCI Int Tgt Devices */
+#define	_MCPCIA_INT_ADR		0x0000005C0	/* PCI Int Tgt Address */
+#define	_MCPCIA_INT_ADR_EXT	0x000000600	/* PCI Int Tgt Addr Ext */
+#define	_MCPCIA_INT_MASK0	0x000000640	/* PCI Int Mask 0 */
+#define	_MCPCIA_INT_MASK1	0x000000680	/* PCI Int Mask 1 */
+
+#define	_MCPCIA_INT_ACK0	0x100003F00	/* PCI Int Ack 0 */
+#define	_MCPCIA_INT_ACK1	0x100003F40	/* PCI Int Ack 1 */
+
+#define	_MCPCIA_PERF_MON	0x000000300	/* PCI Perf Monitor */
+#define	_MCPCIA_PERF_CONT	0x000000340	/* PCI Perf Monitor Control */
+
+#define	_MCPCIA_CAP_DIAG	0x000000700	/* MC-PCI Diagnostic Control */
+#define	_MCPCIA_SCRATCH0	0x000000740	/* Diag General */
+#define	_MCPCIA_SCRATCH1	0x000000780	/* Diag General */
+#define	_MCPCIA_TOM		0x0000007C0	/* Top Of Memory */
+#define	_MCPCIA_MC_ERR0		0x000000800	/* MC Err Info 0 */
+#define	_MCPCIA_MC_ERR1		0x000000840	/* MC Err Info 1 */
+#define	_MCPCIA_CAP_ERR		0x000000880	/* CAP Error Register */
+
+#define	_MCPCIA_PCI_ERR1	0x000001040	/* PCI Error Status */
+
+#define	_MCPCIA_MDPA_STAT	0x000004000	/* MDPA Status */
+#define	_MCPCIA_MDPA_SYN	0x000004040	/* MDPA Syndrome */
+#define	_MCPCIA_MDPA_DIAG	0x000004080	/* Diag Check MDPA */
+
+#define	_MCPCIA_MDPB_STAT	0x000008000	/* MDPB Status */
+#define	_MCPCIA_MDPB_SYN	0x000008040	/* MDPB Syndrome */
+#define	_MCPCIA_MDPB_DIAG	0x000008080	/* Diag Check MDPB */
+
+#define	_MCPCIA_SG_TBIA		0x000001300	/* Scatter/Gather TBIA */
+#define	_MCPCIA_HBASE		0x000001340	/* PC "Hole" Compatibility */
+#define	_MCPCIA_W0_BASE		0x000001400	/* Window Base 0 */
+#define	_MCPCIA_W0_MASK		0x000001440	/* Window Mask 0 */
+#define	_MCPCIA_T0_BASE		0x000001480	/* Translated Base 0 */
+#define	_MCPCIA_W1_BASE		0x000001500	/* Window Base 1 */
+#define	_MCPCIA_W1_MASK		0x000001540	/* Window Mask 1 */
+#define	_MCPCIA_T1_BASE		0x000001580	/* Translated Base 1 */
+#define	_MCPCIA_W2_BASE		0x000001600	/* Window Base 2 */
+#define	_MCPCIA_W2_MASK		0x000001640	/* Window Mask 2 */
+#define	_MCPCIA_T2_BASE		0x000001680	/* Translated Base 2 */
+#define	_MCPCIA_W3_BASE		0x000001700	/* Window Base 3 */
+#define	_MCPCIA_W3_MASK		0x000001740	/* Window Mask 3 */
+#define	_MCPCIA_T3_BASE		0x000001780	/* Translated Base 3 */
+#define	_MCPCIA_W_DAC		0x0000017C0	/* Window DAC Base */
+
+
+/*
+ * Handier defines- uses precalculated offset in softc.
+ */
+#define	_SYBRIDGE(ccp)	((ccp)->cc_sysbase | MCPCIA_PCI_BRIDGE)
+
+#define	MCPCIA_PCI_REV(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_PCI_REV)
+#define	MCPCIA_WHOAMI(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_WHOAMI)
+#define	MCPCIA_PCI_LAT(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_PCI_LAT)
+#define	MCPCIA_CAP_CTRL(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_CAP_CTRL)
+#define	MCPCIA_HAE_MEM(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_HAE_MEM)
+#define	MCPCIA_HAE_IO(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_HAE_IO)
+#define	MCPCIA_IACK_SC(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_IACK_SC)
+#define	MCPCIA_HAE_DENSE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_HAE_DENSE)
+#define	MCPCIA_INT_CTL(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_CTL)
+#define	MCPCIA_INT_REQ(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_REQ)
+#define	MCPCIA_INT_TARG(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_TARG)
+#define	MCPCIA_INT_ADR(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_ADR)
+#define	MCPCIA_INT_ADR_EXT(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_ADR_EXT)
+#define	MCPCIA_INT_MASK0(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_MASK0)
+#define	MCPCIA_INT_MASK1(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_MASK1)
+#define	MCPCIA_INT_ACK0(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_ACK0)
+#define	MCPCIA_INT_ACK1(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_INT_ACK1)
+#define	MCPCIA_PERF_MON(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_PERF_MON)
+#define	MCPCIA_PERF_CONT(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_PERF_CONT)
+#define	MCPCIA_CAP_DIAG(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_CAP_DIAG)
+#define	MCPCIA_SCRATCH0(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_SCRATCH0)
+#define	MCPCIA_SCRATCH1(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_SCRATCH1)
+#define	MCPCIA_TOM(ccp)		(_SYBRIDGE(ccp) | _MCPCIA_TOM)
+#define	MCPCIA_MC_ERR0(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MC_ERR0)
+#define	MCPCIA_MC_ERR1(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MC_ERR1)
+#define	MCPCIA_CAP_ERR(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_CAP_ERR)
+#define	MCPCIA_PCI_ERR1(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_PCI_ERR1)
+#define	MCPCIA_MDPA_STAT(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPA_STAT)
+#define	MCPCIA_MDPA_SYN(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPA_SYN)
+#define	MCPCIA_MDPA_DIAG(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPA_DIAG)
+#define	MCPCIA_MDPB_STAT(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPB_STAT)
+#define	MCPCIA_MDPB_SYN(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPB_SYN)
+#define	MCPCIA_MDPB_DIAG(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_MDPB_DIAG)
+#define	MCPCIA_SG_TBIA(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_SG_TBIA)
+#define	MCPCIA_HBASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_HBASE)
+#define	MCPCIA_W0_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W0_BASE)
+#define	MCPCIA_W0_MASK(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W0_MASK)
+#define	MCPCIA_T0_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_T0_BASE)
+#define	MCPCIA_W1_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W1_BASE)
+#define	MCPCIA_W1_MASK(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W1_MASK)
+#define	MCPCIA_T1_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_T1_BASE)
+#define	MCPCIA_W2_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W2_BASE)
+#define	MCPCIA_W2_MASK(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W2_MASK)
+#define	MCPCIA_T2_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_T2_BASE)
+#define	MCPCIA_W3_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W3_BASE)
+#define	MCPCIA_W3_MASK(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W3_MASK)
+#define	MCPCIA_T3_BASE(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_T3_BASE)
+#define	MCPCIA_W_DAC(ccp)	(_SYBRIDGE(ccp) | _MCPCIA_W_DAC)
+
+/*
+ * This is here for what error handling will get as a collected subpacket.
+ */
+
+struct mcpcia_iodsnap {
+	u_int64_t	base_addr;
+	u_int32_t	whami; 
+	u_int32_t	rsvd0;
+	u_int32_t	pci_rev;
+	u_int32_t	cap_ctrl;
+	u_int32_t	hae_mem;
+	u_int32_t	hae_io;
+	u_int32_t	int_ctl;
+	u_int32_t	int_reg;
+	u_int32_t	int_mask0; 
+	u_int32_t	int_mask1;
+	u_int32_t	mc_err0;
+	u_int32_t	mc_err1;
+	u_int32_t	cap_err;
+	u_int32_t	sys_env;
+	u_int32_t	pci_err1;
+	u_int32_t	mdpa_stat;
+	u_int32_t	mdpa_syn; 
+	u_int32_t	mdpb_stat;
+	u_int32_t	mdpb_syn;
+	u_int32_t	rsvd2;
+	u_int32_t	rsvd3;
+	u_int32_t	rsvd4;
+};
+
+/*
+ * PCI_REV Register definitions
+ */
+#define	CAP_REV(reg)		((reg) & 0xf)
+#define	HORSE_REV(reg)		(((reg) >> 4) & 0xf)
+#define	SADDLE_REV(reg)		(((reg) >> 8) & 0xf)
+#define	SADDLE_TYPE(reg)	(((reg) >> 12) & 0x3)
+#define	EISA_PRESENT(reg)	((reg) & (1 << 15))
+#define	IS_MCPCIA_MAGIC(reg)	(((reg) & 0xffff0000) == 0x6000000)
+
+
+/*
+ * WHOAMI Register definitions
+ *
+ * The Device ID is an echo of the MID of the CPU reading this register-
+ * cheezy way to figure out who you are (ask someone else!).
+ */
+#define	MCBUS_CPU_MID(x)		((x) & 0x7)
+#define	MCBUS_CPU_INFO(x)		(((x) >> 6) & 0xff)
+#define		CPU_Fill_Err	0x80
+#define		CPU_DTAG_Perr	0x40
+#define		CPU_RevMask	0x38
+#define		CPU_RevShift	3
+#define		CPU_BCacheMask	0x3
+#define			CPU_BCache_0MB	0
+#define			CPU_BCache_1MB	1
+#define			CPU_BCache_2MB	2
+#define			CPU_BCache_4MB	3
+
+/*
+ * PCI Latency Register Definitions
+ */
+#define	PCI_LAT_SHIFT	8	/* it's in the 2nd byte. */
+
+/*
+ * CAP Control Register Definitions
+ */
+#define	CAP_LED_ON	0x00000001	/* Selftest LED passed */
+#define	CAP_EV56_BW_EN	0x00000002	/* BW Enables (EV56, EV6 only) */
+#define	CAP_DLY_RD_EN	0x00000010	/* PCI Delayed Reads Enabled */
+#define	CAP_MEM_EN	0x00000020	/* Respond to PCI transactions */
+#define	CAP_REQ64_EN	0x00000040	/* Request 64 bit data transactions */
+#define	CAP_ACK64_EN	0x00000080	/* Respond to 64 bit data "" */
+#define	CAP_ADR_PAR_EN	0x00000100	/* Check PCI address Parity */
+#define	CAP_MC_CA_PAR	0x00000200	/* Check MC bus CMD/Address Parity */
+#define	CAP_MC_NXM_EN	0x00000400	/* Check for MC NXM */
+#define	CAP_BUS_MON	0x00000800	/* Check for PCI errs (as bystander) */
+/* bits 19:16 control number of pending write transactions */
+#define		SHORT	0
+#define		MED	1
+#define		LONG	2
+#define	CAP_MEMRD_PREFETCH_SHIFT	20
+#define	CAP_MEMRDLN_PREFETCH_SHIFT	22
+#define	CAP_MEMRDMULT_PREFETCH_SHIFT	24
+#define	CAP_PARTIAL_WRITE	(1 << 26)
+
+#define	CAP_ARB_BPRI	0x00000000	/* Bridge Priority Arb */
+#define	CAP_ARB_RROBIN	0x40000000	/* "" Round Robin */
+#define	CAP_ARB_RROBIN1	0x80000000	/* "" Round Robin #1 */
+
+/*
+ * Diagnostic Register Bits
+ */
+/* CAP_DIAG register */
+#define	CAP_DIAG_PCIRESET	0x1	/*
+					 * WriteOnly. Assert 1 for 100usec min.,
+					 * then write zero. NOTE: deadlocks
+					 * exist in h/w if anything but this
+					 * register is accessed while reset
+					 * is asserted.
+					 */
+#define	CAP_DIAG_MC_ADRPE	(1<<30)	/* Invert MC Bus Address/Parity */
+#define	CAP_DIAG_PCI_ADRPE	(1<<31)	/* Force bad PCI parity (low 32) */
+
+/* MDPA_DIAG or MDPB_DIAG registers */
+#define	MDPX_ECC_ENA		(1<<28)	/* Enable ECC on MC Bus (default 1) */
+#define	MDPX_PAR_ENA		(1<<29)	/* Enable Parity on PCI (default 0) */
+#define	MDPX_DIAG_FPE_PCI	(1<<30)	/* Force PCI parity error */
+#define	MDPX_DIAG_USE_CHK	(1<<31)	/*
+					 * When set, DMA write cycles use the
+					 * value in the low 8 bits of this
+					 * register (MDPA or MDPB) as ECC
+					 * sent onto main memory.
+					 */
+
+/*
+ * Interrupt Specific bits...
+ *
+ * Mostly we don't have to mess with any of the interrupt specific registers
+ * as the SRM has set most of this pretty complex stuff up for us.
+ *
+ * However, to enable specific interrupts, we need to set some bits
+ * in imask0 if we want to have them vectored to PALcode for appropriate
+ * dispatch.
+ */
+
+/*
+ * bits 0-15 correspond to 4 slots (time 4 buspins) for each PCI bus.
+ * bit 16 is the NCR810 onboard SCSI interrupt.
+ * bits 19-20 are reserved.
+ */
+
+#define	MCPCIA_I2C_CTRL_INTR		(1<<17)
+#define	MCPCIA_I2C_CTRL_BUS_ERR		(1<<18)
+
+#define	MCPCIA_8259_NMI_INTR		(1<<21)
+#define	MCPCIA_SOFT_ERR_INTR		(1<<22)
+#define	MCPCIA_HARD_ERR_INTR		(1<<23)
+
+#ifdef	YET
+#define	MCPCIA_GEN_IENABL	\
+	(MCPCIA_I2C_CTRL_BUS_ERR|MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
+#else
+#define	MCPCIA_GEN_IENABL	\
+	(MCPCIA_SOFT_ERR_INTR|MCPCIA_HARD_ERR_INTR)
+#endif
+
+/*
+ * DMA Address Specific bits...
+ */
+
+#define	MCPCIA_WBASE_EN			0x1
+#define	MCPCIA_WBASE_SG			0x2
+#define	MCPCIA_WBASE_DAC		0x8
+#define	MCPCIA_WBASE_BSHIFT		20
+
+#define	MCPCIA_WMASK_1M			0x00000000
+#define	MCPCIA_WMASK_2M			0x00100000
+#define	MCPCIA_WMASK_4M			0x00300000
+#define	MCPCIA_WMASK_8M			0x00700000
+#define	MCPCIA_WMASK_16M		0x00f00000
+#define	MCPCIA_WMASK_32M		0x01f00000
+#define	MCPCIA_WMASK_64M		0x03f00000
+#define	MCPCIA_WMASK_128M		0x07f00000
+#define	MCPCIA_WMASK_256M		0x0ff00000
+#define	MCPCIA_WMASK_512M		0x1ff00000
+#define	MCPCIA_WMASK_1G			0x3ff00000
+#define	MCPCIA_WMASK_2G			0x7ff00000
+#define	MCPCIA_WMASK_4G			0xfff00000
+
+/*
+ * The WBASEX register contains bits 39:10 of a physical address
+ * shifted to bits 31:2 of this 32 bit register. Namely, shifted
+ * right by 8 bits.
+ */
+#define	MCPCIA_TBASEX_SHIFT		8
diff --git a/sys/arch/alpha/pci/mcpciavar.h b/sys/arch/alpha/pci/mcpciavar.h
new file mode 100644
index 00000000000..4d84fa7a382
--- /dev/null
+++ b/sys/arch/alpha/pci/mcpciavar.h
@@ -0,0 +1,115 @@
+/* $OpenBSD: mcpciavar.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: mcpciavar.h,v 1.4 1999/04/16 02:18:07 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <dev/pci/pcivar.h>
+#include <sys/extent.h>
+
+#include <alpha/pci/pci_sgmap_pte64.h>
+
+#define	_FSTORE	(EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long))
+
+/*
+ * MPCIA configuration.
+ */
+struct mcpcia_config {
+	int				cc_gid;	/* GID of this MCbus */
+	int				cc_mid;	/* MCbus Module ID */
+	int				cc_initted;
+	int				cc_mallocsafe;
+	struct alpha_bus_space		cc_iot;
+	struct alpha_bus_space		cc_memt;
+	struct extent *			cc_io_ex;
+	struct extent *			cc_d_mem_ex;
+	struct extent *			cc_s_mem_ex;
+	struct alpha_pci_chipset	cc_pc;
+	struct mcpcia_softc *		cc_sc;	/* back pointer */
+	long				cc_io_exstorage[_FSTORE];
+	long				cc_dmem_exstorage[_FSTORE];
+	long				cc_smem_exstorage[_FSTORE];
+	unsigned long			cc_sysbase;	/* shorthand */
+	struct alpha_bus_dma_tag	cc_dmat_direct;
+	struct alpha_bus_dma_tag	cc_dmat_pci_sgmap;
+	struct alpha_bus_dma_tag	cc_dmat_isa_sgmap;
+	struct alpha_sgmap		cc_pci_sgmap;
+	struct alpha_sgmap		cc_isa_sgmap;
+	char				pc_io_ex_name[16];
+	char				pc_mem_dex_name[16];
+	char				pc_mem_sex_name[16];
+	long				pc_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+	long				pc_mem_dex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+	long				pc_mem_sex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+};
+
+struct mcpcia_softc {
+	struct device		mcpcia_dev;
+	struct mcpcia_config	*mcpcia_cc;	/* config info */
+};
+
+void	mcpcia_init (void);
+void	mcpcia_init0 (struct mcpcia_config *, int);
+void	mcpcia_pci_init (pci_chipset_tag_t, void *);
+void	mcpcia_dma_init (struct mcpcia_config *);
+
+void	mcpcia_bus_io_init (bus_space_tag_t, void *);
+void	mcpcia_bus_mem_init (bus_space_tag_t, void *);
+
+/*
+ * IO Interrupt handler.
+ */
+void 	mcpcia_iointr (void *, unsigned long);
+
+/*
+ * There are four PCI slots per MCPCIA PCI bus here, but some are 'hidden'-
+ * none seems to be higher than 6 though.
+ */
+#define	MCPCIA_MAXDEV	6
+#define	MCPCIA_MAXSLOT	8
+
+/*
+ * Interrupt Stuff for MCPCIA systems.
+ *
+ * EISA interrupts (at vector 0x800) have to be shared interrupts-
+ * and that can be easily managed. All the PCI interrupts are deterministic
+ * in that they start at vector 0x900, 0x40 per PCI slot, 0x200 per
+ * MCPCIA, 4 MCPCIAs per GCBUS....
+ */
+#define MCPCIA_EISA_KEYB_IRQ	1
+#define MCPCIA_EISA_MOUSE_IRQ	12
+#define MCPCIA_VEC_EISA		0x800
+#define MCPCIA_VEC_PCI		0x900
+
+/*
+ * Special Vectors
+ */
+#define	MCPCIA_I2C_CVEC		0xA90
+#define	MCPCIA_I2C_BVEC		0xAA0
diff --git a/sys/arch/alpha/pci/pci_kn300.c b/sys/arch/alpha/pci/pci_kn300.c
new file mode 100644
index 00000000000..60e8a88a925
--- /dev/null
+++ b/sys/arch/alpha/pci/pci_kn300.c
@@ -0,0 +1,294 @@
+/* $OpenBSD: pci_kn300.c,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+/* $NetBSD: pci_kn300.c,v 1.28 2005/12/11 12:16:17 christos Exp $ */
+
+/*
+ * Copyright (c) 1998 by Matthew Jacob
+ * NASA AMES Research Center.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice immediately at the beginning of the file, without modification,
+ *    this list of conditions, and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/time.h>
+#include <sys/systm.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+#include <sys/syslog.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/autoconf.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <alpha/mcbus/mcbusvar.h>
+#include <alpha/mcbus/mcbusreg.h>
+#include <alpha/pci/mcpciareg.h>
+#include <alpha/pci/mcpciavar.h>
+#include <alpha/pci/pci_kn300.h>
+
+#include "sio.h"
+#if NSIO > 0 || NPCEB > 0
+#include <alpha/pci/siovar.h>
+#endif
+
+int	dec_kn300_intr_map (void *, pcitag_t, int, int, pci_intr_handle_t *);
+
+const char *dec_kn300_intr_string (void *, pci_intr_handle_t);
+void	*dec_kn300_intr_establish (void *, pci_intr_handle_t,
+	    int, int (*func)(void *), void *, char *);
+void	dec_kn300_intr_disestablish (void *, void *);
+
+#define	KN300_PCEB_IRQ	16
+#define	NPIN		4
+
+#define	NIRQ	(MAX_MC_BUS * MCPCIA_PER_MCBUS * MCPCIA_MAXSLOT * NPIN)
+static int savirqs[NIRQ];
+
+static struct alpha_shared_intr *kn300_pci_intr;
+
+static struct mcpcia_config *mcpcia_eisaccp = NULL;
+
+void	kn300_iointr (void *, unsigned long);
+void	kn300_enable_intr (struct mcpcia_config *, int);
+void	kn300_disable_intr (struct mcpcia_config *, int);
+
+void
+pci_kn300_pickintr(ccp, first)
+	struct mcpcia_config *ccp;
+	int first;
+{
+	pci_chipset_tag_t pc = &ccp->cc_pc;
+
+	if (first) {
+		int g;
+
+		kn300_pci_intr = alpha_shared_intr_alloc(NIRQ);
+		for (g = 0; g < NIRQ; g++) {
+			alpha_shared_intr_set_maxstrays(kn300_pci_intr, g, 25);
+			savirqs[g] = (char) -1;
+		}
+	}
+
+	pc->pc_intr_v = ccp;
+	pc->pc_intr_map = dec_kn300_intr_map;
+	pc->pc_intr_string = dec_kn300_intr_string;
+	pc->pc_intr_establish = dec_kn300_intr_establish;
+	pc->pc_intr_disestablish = dec_kn300_intr_disestablish;
+
+	/* Not supported on KN300. */
+	pc->pc_pciide_compat_intr_establish = NULL;
+
+	if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(ccp)))) {
+		mcpcia_eisaccp = ccp;
+#if NSIO > 0 || NPCEB > 0
+		sio_intr_setup(pc, &ccp->cc_iot);
+		kn300_enable_intr(ccp, KN300_PCEB_IRQ);
+#endif
+	}
+}
+
+int     
+dec_kn300_intr_map(ccv, bustag, buspin, line, ihp)
+	void *ccv;
+	pcitag_t bustag;
+	int buspin, line;
+	pci_intr_handle_t *ihp;
+{
+	struct mcpcia_config *ccp = ccv; 
+	pci_chipset_tag_t pc = &ccp->cc_pc;
+	int device;
+	int mcpcia_irq;
+
+	if (buspin == 0) {
+		/* No IRQ used. */
+		return 1;
+	}
+	if (buspin > 4 || buspin < 0) {
+		printf("dec_kn300_intr_map: bad interrupt pin %d\n", buspin);
+		return 1;
+	}
+
+	pci_decompose_tag(pc, bustag, NULL, &device, NULL);
+
+	/*
+	 * On MID 5 device 1 is the internal NCR 53c810.
+	 */
+	if (ccp->cc_mid == 5 && device == 1) {
+		mcpcia_irq = 16;
+	} else if (device >= 2 && device <= 5) {
+		mcpcia_irq = (device - 2) * 4 + buspin - 1;
+	} else {
+		printf("dec_kn300_intr_map: weird device number %d\n", device);
+		return(1);
+	}
+
+	/*
+	 * handle layout:
+	 *
+	 *	Determine kn300 IRQ (encoded in SCB vector):
+	 *	bits 0..1	buspin-1
+	 *	bits 2..4	PCI Slot (0..7- yes, some don't exist)
+	 *	bits 5..7	MID-4
+	 *	bits 8..10	7-GID
+	 *
+	 *	Software only:
+	 *	bits 11-15	MCPCIA IRQ
+	 */
+	*ihp = (pci_intr_handle_t)
+		(buspin - 1			    )	|
+		((device & 0x7)			<< 2)	|
+		((ccp->cc_mid - 4)		<< 5)	|
+		((7 - ccp->cc_gid)		<< 8)	|
+		(mcpcia_irq			<< 11);
+	return (0);
+}
+
+const char *
+dec_kn300_intr_string(ccv, ih)
+	void *ccv;
+	pci_intr_handle_t ih;
+{
+	static char irqstr[64];
+	int irq;
+
+	irq = ih & 0x3ff;
+	if (irq > NIRQ)
+		panic("dec_kn300_intr_string: bogus kn300 IRQ 0x%x", irq);
+
+	snprintf(irqstr, sizeof irqstr, "kn300 irq %ld", irq);
+
+	return (irqstr);
+}
+
+void *
+dec_kn300_intr_establish(ccv, ih, level, func, arg, name)
+        void *ccv, *arg;
+        pci_intr_handle_t ih;
+        int level;
+        int (*func) (void *);
+	char *name;
+{           
+	struct mcpcia_config *ccp = ccv;
+	void *cookie;
+	int irq;
+
+	irq = ih & 0x3ff;
+	if (irq > NIRQ)
+		panic("dec_kn300_intr_establish: bogus kn300 IRQ 0x%x", irq);
+
+	cookie = alpha_shared_intr_establish(kn300_pci_intr, irq, IST_LEVEL,
+	    level, func, arg, "kn300 irq");
+
+	if (cookie != NULL &&
+	    alpha_shared_intr_firstactive(kn300_pci_intr, irq)) {
+		scb_set(MCPCIA_VEC_PCI + SCB_IDXTOVEC(irq),
+		    kn300_iointr, NULL);
+		alpha_shared_intr_set_private(kn300_pci_intr, irq, ccp);
+		savirqs[irq] = (ih >> 11) & 0x1f;
+		kn300_enable_intr(ccp, savirqs[irq]);
+		alpha_mb();
+	}
+	return (cookie);
+}
+
+void    
+dec_kn300_intr_disestablish(ccv, cookie)
+	void *ccv, *cookie;
+{
+	panic("dec_kn300_intr_disestablish not implemented");
+}
+
+void
+kn300_iointr(arg, vec)
+	void *arg;
+	unsigned long vec;
+{
+	struct mcpcia_softc *mcp;
+	u_long irq;
+
+	irq = SCB_VECTOIDX(vec - MCPCIA_VEC_PCI);
+
+	if (alpha_shared_intr_dispatch(kn300_pci_intr, irq)) {
+		/*
+		 * Any claim of an interrupt at this level is a hint to
+		 * reset the stray interrupt count- elsewise a slow leak
+		 * over time will cause this level to be shutdown.
+		 */
+		alpha_shared_intr_reset_strays(kn300_pci_intr, irq);
+		return;
+	}
+
+	/*
+	 * If we haven't finished configuring yet, or there is no mcp
+	 * registered for this level yet, just return.
+	 */
+	mcp = alpha_shared_intr_get_private(kn300_pci_intr, irq);
+	if (mcp == NULL || mcp->mcpcia_cc == NULL)
+		return;
+
+	/*
+	 * We're getting an interrupt for a device we haven't enabled.
+	 * We had better not try and use -1 to find the right bit to disable.
+	 */
+	if (savirqs[irq] == -1) {
+		printf("kn300_iointr: stray interrupt vector 0x%lx\n", vec);
+		return;
+	}
+
+	/*
+	 * Stray interrupt; disable the IRQ on the appropriate MCPCIA
+	 * if we've reached the limit.
+	 */
+	alpha_shared_intr_stray(kn300_pci_intr, irq, "kn300 irq");
+	if (ALPHA_SHARED_INTR_DISABLE(kn300_pci_intr, irq) == 0)
+		return;
+	kn300_disable_intr(mcp->mcpcia_cc, savirqs[irq]);
+}
+
+void
+kn300_enable_intr(ccp, irq)
+	struct mcpcia_config *ccp;
+	int irq;
+{
+	alpha_mb();
+	REGVAL(MCPCIA_INT_MASK0(ccp)) |= (1 << irq);
+	alpha_mb();
+}
+
+void
+kn300_disable_intr(ccp, irq)
+	struct mcpcia_config *ccp;
+	int irq;
+{
+	alpha_mb();
+	REGVAL(MCPCIA_INT_MASK0(ccp)) &= ~(1 << irq);
+	alpha_mb();
+}
diff --git a/sys/arch/alpha/pci/pci_kn300.h b/sys/arch/alpha/pci/pci_kn300.h
new file mode 100644
index 00000000000..8ac80749828
--- /dev/null
+++ b/sys/arch/alpha/pci/pci_kn300.h
@@ -0,0 +1,19 @@
+/* $OpenBSD: pci_kn300.h,v 1.1 2007/03/16 21:22:27 robert Exp $ */
+
+/*
+ * Copyright (c) 2007 Robert Nagy <robert@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+void	pci_kn300_pickintr(struct mcpcia_config *, int);
diff --git a/sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c b/sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
index d5de92e3233..c4dfa8f5000 100644
--- a/sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
+++ b/sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pci_swiz_bus_io_chipdep.c,v 1.3 2002/03/14 01:26:27 millert Exp $	*/
+/*	$OpenBSD: pci_swiz_bus_io_chipdep.c,v 1.4 2007/03/16 21:22:27 robert Exp $	*/
 /*	$NetBSD: pcs_bus_io_common.c,v 1.14 1996/12/02 22:19:35 cgd Exp $	*/
 
 /*
@@ -42,6 +42,16 @@
 #define	__C(A,B)	__CONCAT(A,B)
 #define	__S(S)		__STRING(S)
 
+#ifndef	CHIP_EXTENT_NAME
+#define	CHIP_EXTENT_NAME(v)	__S(__C(CHIP,_bus_io))
+#endif
+
+#ifndef	CHIP_EXTENT_STORAGE
+#define CHIP_EXTENT_STORAGE(v)	__C(CHIP,_io_ex_storage)
+static long
+    __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+#endif
+
 /* mapping/unmapping */
 int		__C(CHIP,_io_map)(void *, bus_addr_t, bus_size_t, int,
 		    bus_space_handle_t *);
@@ -170,9 +180,6 @@ void		__C(CHIP,_io_write_raw_multi_8)(void *,
 		    bus_space_handle_t, bus_size_t, const u_int8_t *,
 		    bus_size_t);
 
-static long
-    __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
-
 void
 __C(CHIP,_bus_io_init)(t, v)
 	bus_space_tag_t t;
@@ -265,9 +272,9 @@ __C(CHIP,_bus_io_init)(t, v)
 
 
 	/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
-	ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL,
-	    M_DEVBUF, (caddr_t)__C(CHIP,_io_ex_storage),
-	    sizeof(__C(CHIP,_io_ex_storage)), EX_NOWAIT);
+	ex = extent_create(CHIP_EXTENT_NAME(v), 0x0UL, 0xffffffffUL,
+	    M_DEVBUF, (caddr_t)CHIP_EXTENT_STORAGE(v),
+	    sizeof(CHIP_EXTENT_STORAGE(v)), EX_NOWAIT);
 	extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT);
 
 #ifdef CHIP_IO_W1_BUS_START
diff --git a/sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c b/sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
index 2f7cd2376a3..4251ecf8115 100644
--- a/sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
+++ b/sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pci_swiz_bus_mem_chipdep.c,v 1.3 2002/03/14 01:26:27 millert Exp $	*/
+/*	$OpenBSD: pci_swiz_bus_mem_chipdep.c,v 1.4 2007/03/16 21:22:27 robert Exp $	*/
 /*	$NetBSD: pcs_bus_mem_common.c,v 1.15 1996/12/02 22:19:36 cgd Exp $	*/
 
 /*
@@ -43,6 +43,25 @@
 #define	__C(A,B)	__CONCAT(A,B)
 #define	__S(S)		__STRING(S)
 
+#ifndef	CHIP_EXTENT_DNAME
+#define	CHIP_EXTENT_DNAME(v)	__S(__C(CHIP,_bus_dmem))
+#endif
+#ifndef CHIP_EXTENT_SNAME
+#define CHIP_EXTENT_SNAME(v)	__S(__C(CHIP,_bus_smem))
+#endif
+
+#ifndef	CHIP_EXTENT_DSTORAGE
+#define CHIP_EXTENT_DSTORAGE(v)	__C(CHIP,_dmem_ex_storage)
+static long
+    __C(CHIP,_dmem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+#endif
+#ifndef CHIP_EXTENT_SSTORAGE
+#define CHIP_EXTENT_SSTORAGE(v)	__C(CHIP,_smem_ex_storage)
+static long
+    __C(CHIP,_smem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
+
+#endif
+
 /* mapping/unmapping */
 int		__C(CHIP,_mem_map)(void *, bus_addr_t, bus_size_t, int,
 		    bus_space_handle_t *);
@@ -171,11 +190,6 @@ void		__C(CHIP,_mem_write_raw_multi_8)(void *,
 		    bus_space_handle_t, bus_size_t, const u_int8_t *,
 		    bus_size_t);
 
-static long
-    __C(CHIP,_dmem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
-static long
-    __C(CHIP,_smem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
-
 void
 __C(CHIP,_bus_mem_init)(t, v)
 	bus_space_tag_t t;
@@ -267,10 +281,10 @@ __C(CHIP,_bus_mem_init)(t, v)
 	t->abs_wrm_8 =		__C(CHIP,_mem_write_raw_multi_8);
 
 	/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
-	dex = extent_create(__S(__C(CHIP,_bus_dmem)), 0x0UL,
+	dex = extent_create(CHIP_EXTENT_DNAME(v), 0x0UL,
 	    0xffffffffffffffffUL, M_DEVBUF,
-	    (caddr_t)__C(CHIP,_dmem_ex_storage),
-	    sizeof(__C(CHIP,_dmem_ex_storage)), EX_NOWAIT);
+	    (caddr_t)CHIP_EXTENT_DSTORAGE(v),
+	    sizeof(CHIP_EXTENT_DSTORAGE(v)), EX_NOWAIT);
 	extent_alloc_region(dex, 0, 0xffffffffffffffffUL, EX_NOWAIT);
 
 #ifdef CHIP_D_MEM_W1_BUS_START
@@ -289,10 +303,10 @@ __C(CHIP,_bus_mem_init)(t, v)
         CHIP_D_MEM_EXTENT(v) = dex;
 
 	/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
-	sex = extent_create(__S(__C(CHIP,_bus_smem)), 0x0UL,
+	sex = extent_create(CHIP_EXTENT_SNAME(v), 0x0UL,
 	    0xffffffffffffffffUL, M_DEVBUF,
-	    (caddr_t)__C(CHIP,_smem_ex_storage),
-	    sizeof(__C(CHIP,_smem_ex_storage)), EX_NOWAIT);
+	    (caddr_t)CHIP_EXTENT_SSTORAGE(v),
+	    sizeof(CHIP_EXTENT_SSTORAGE(v)), EX_NOWAIT);
 	extent_alloc_region(sex, 0, 0xffffffffffffffffUL, EX_NOWAIT);
 
 #ifdef CHIP_S_MEM_W1_BUS_START