diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-09 20:22:09 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-09 20:22:09 +0000 |
| commit | 59064bf58bfefca203d3fcd99c21fb80f3c6e310 (patch) | |
| tree | c157eb6d1ed058861e9b8ee8e45d9a90f3ae31c3 /sys/arch/amd64/include/specialreg.h | |
| parent | 20dbc48a615f5247f4a1686e516003284634dcfb (diff) | |
reorder some MSRs in the MSR list that were out of order. No functional
change; I'll be adding a few new ones and noticed these were misplaced.
Diffstat (limited to 'sys/arch/amd64/include/specialreg.h')
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 63b4909fc2f..3556c9d383d 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.58 2017/06/20 06:25:01 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.59 2017/08/09 20:22:08 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -327,19 +327,6 @@ #define MSR_PERFCTR0 0x0c1 #define MSR_PERFCTR1 0x0c2 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ -/* - * for Core i Series and newer Xeons, see - * http://www.intel.com/content/dam/www/public/us/en/ - * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf - */ -#define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ -#define MSR_TEMPERATURE_TARGET_TJMAX(msr) (((msr) >> 16) & 0xff) -/* - * not documented anywhere, see intelcore_update_sensor() - * only available Core Duo and Core Solo Processors - */ -#define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee -#define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 #define MSR_MTRRcap 0x0fe #define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */ #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ @@ -367,6 +354,19 @@ #define MSR_THERM_STATUS_VALID_BIT 0x80000000 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) #define MSR_THERM2_CTL 0x19d /* Pentium M */ +/* + * for Core i Series and newer Xeons, see + * http://www.intel.com/content/dam/www/public/us/en/ + * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf + */ +#define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ +#define MSR_TEMPERATURE_TARGET_TJMAX(msr) (((msr) >> 16) & 0xff) +/* + * not documented anywhere, see intelcore_update_sensor() + * only available Core Duo and Core Solo Processors + */ +#define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee +#define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 #define MSR_DEBUGCTLMSR 0x1d9 #define MSR_LASTBRANCHFROMIP 0x1db #define MSR_LASTBRANCHTOIP 0x1dc |