an amd64 arch support.

hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

65 files changed, 9529 insertions, 0 deletions

diff --git a/sys/arch/amd64/include/ansi.h b/sys/arch/amd64/include/ansi.h
new file mode 100644
index 00000000000..eba619188a4
--- /dev/null
+++ b/sys/arch/amd64/include/ansi.h
@@ -0,0 +1,87 @@
+/*	$NetBSD: ansi.h,v 1.1 2003/04/26 18:39:36 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)ansi.h	8.2 (Berkeley) 1/4/94
+ */
+
+#ifndef	_ANSI_H_
+#define	_ANSI_H_
+
+/*
+ * Types which are fundamental to the implementation and may appear in
+ * more than one standard header are defined here.  Standard headers
+ * then use:
+ *	#ifdef	_BSD_SIZE_T_
+ *	typedef	_BSD_SIZE_T_ size_t;
+ *	#undef	_BSD_SIZE_T_
+ *	#endif
+ */
+#define	_BSD_CLOCK_T_		unsigned int	/* clock() */
+#define	_BSD_PTRDIFF_T_		long		/* ptr1 - ptr2 */
+#define	_BSD_SIZE_T_		unsigned long	/* sizeof() */
+#define	_BSD_SSIZE_T_		long		/* byte count or error */
+#define	_BSD_TIME_T_		int		/* time() */
+#ifdef __GNUC__
+#define	_BSD_VA_LIST_		__builtin_va_list /* GCC built-in type */
+#else
+#define _BSD_VA_LIST_		char *		/* XXXfvdl should be ok? */
+#endif
+#define	_BSD_CLOCKID_T_		int		/* clockid_t */
+#define	_BSD_TIMER_T_		int		/* timer_t */
+
+/*
+ * Runes (wchar_t) is declared to be an ``int'' instead of the more natural
+ * ``unsigned long'' or ``long''.  Two things are happening here.  It is not
+ * unsigned so that EOF (-1) can be naturally assigned to it and used.  Also,
+ * it looks like 10646 will be a 31 bit standard.  This means that if your
+ * ints cannot hold 32 bits, you will be in trouble.  The reason an int was
+ * chosen over a long is that the is*() and to*() routines take ints (says
+ * ANSI C), but they use _RUNE_T_ instead of int.  By changing it here, you
+ * lose a bit of ANSI conformance, but your programs will still work.
+ *    
+ * Note that _WCHAR_T_ and _RUNE_T_ must be of the same type.  When wchar_t
+ * and rune_t are typedef'd, _WCHAR_T_ will be undef'd, but _RUNE_T remains
+ * defined for ctype.h.
+ */
+#define	_BSD_WCHAR_T_		int		/* wchar_t */
+#define	_BSD_WINT_T_		int		/* wint_t */
+#define	_BSD_RUNE_T_		int		/* rune_t */
+
+/*
+ * We describe off_t here so its declaration can be visible to
+ * stdio without pulling in all of <sys/type.h>, thus appeasing ANSI.
+ */
+#define _BSD_OFF_T_		long long	/* file offset */
+
+#endif	/* _ANSI_H_ */
diff --git a/sys/arch/amd64/include/apicvar.h b/sys/arch/amd64/include/apicvar.h
new file mode 100644
index 00000000000..e40b9552c18
--- /dev/null
+++ b/sys/arch/amd64/include/apicvar.h
@@ -0,0 +1,58 @@
+/*	$OpenBSD: apicvar.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* 	$NetBSD: apicvar.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_APICVAR_H_
+#define _X86_APICVAR_H_
+
+struct apic_attach_args {
+	const char *aaa_name;
+	int apic_id;
+	int apic_version;
+	int flags;
+#define IOAPIC_PICMODE		0x01
+#define IOAPIC_VWIRE		0x02
+	paddr_t apic_address;
+	int apic_vecbase;
+};
+
+void apic_format_redir(char *, char *, int, u_int32_t, u_int32_t);
+
+#endif /* !_X86_APICVAR_H_ */
diff --git a/sys/arch/amd64/include/apmvar.h b/sys/arch/amd64/include/apmvar.h
new file mode 100644
index 00000000000..7be38bb9db4
--- /dev/null
+++ b/sys/arch/amd64/include/apmvar.h
@@ -0,0 +1,300 @@
+/* XXX - DSR */
+/*	$OpenBSD: apmvar.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*
+ *  Copyright (c) 1995 John T. Kohl
+ *  All rights reserved.
+ * 
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef _I386_APMVAR_H_
+#define _I386_APMVAR_H_
+
+#include <sys/ioccom.h>
+
+/* Advanced Power Management (v1.0 and v1.1 specification)
+ * functions/defines/etc.
+ */
+
+#define	APM_VERSION	0x0102
+
+/*
+ * APM info word from boot loader
+ */
+#define APM_16BIT_SUPPORTED	0x00010000
+#define APM_32BIT_SUPPORTED	0x00020000
+#define APM_IDLE_SLOWS		0x00040000
+#define APM_BIOS_PM_DISABLED	0x00080000
+#define APM_BIOS_PM_DISENGAGED	0x00100000
+#define	APM_MAJOR(f)		(((f) >> 8) & 0xff)
+#define	APM_MINOR(f)		((f) & 0xff)
+#define	APM_VERMASK		0x0000ffff
+#define	APM_NOCLI		0x00010000
+#define	APM_BEBATT		0x00020000
+
+/* APM error codes */
+#define	APM_ERR_CODE(regs)	(((regs)->ax & 0xff00) >> 8)
+#define	APM_ERR_PM_DISABLED	0x01
+#define	APM_ERR_REALALREADY	0x02
+#define	APM_ERR_NOTCONN		0x03
+#define	APM_ERR_16ALREADY	0x05
+#define	APM_ERR_16NOTSUPP	0x06
+#define	APM_ERR_32ALREADY	0x07
+#define	APM_ERR_32NOTSUPP	0x08
+#define	APM_ERR_UNRECOG_DEV	0x09
+#define	APM_ERR_ERANGE		0x0A
+#define	APM_ERR_NOTENGAGED	0x0B
+#define	APM_ERR_EOPNOSUPP	0x0C
+#define	APM_ERR_RTIMER_DISABLED	0x0D
+#define APM_ERR_UNABLE		0x60
+#define APM_ERR_NOEVENTS	0x80
+#define	APM_ERR_NOT_PRESENT	0x86
+
+#define APM_DEV_APM_BIOS	0x0000
+#define APM_DEV_ALLDEVS		0x0001
+/* device classes are high byte; device IDs go in low byte */
+#define		APM_DEV_DISPLAY(x)	(0x0100|((x)&0xff))
+#define		APM_DEV_DISK(x)		(0x0200|((x)&0xff))
+#define		APM_DEV_PARALLEL(x)	(0x0300|((x)&0xff))
+#define		APM_DEV_SERIAL(x)	(0x0400|((x)&0xff))
+#define		APM_DEV_NETWORK(x)	(0x0500|((x)&0xff))
+#define		APM_DEV_PCMCIA(x)	(0x0600|((x)&0xff))
+#define		APM_DEV_BATTERIES(x)	(0x8000|((x)&0xff))
+#define		APM_DEV_ALLUNITS	0xff
+/* 0x8100-0xDFFF - reserved	*/
+/* 0xE000-0xEFFF - OEM-defined	*/
+/* 0xF000-0xFFFF - reserved	*/
+
+#define	APM_INSTCHECK		0x5300	/* int15 only */
+#define		APM_16BIT_SUPPORT	0x01
+#define		APM_32BIT_SUPPORT	0x02
+#define		APM_CPUIDLE_SLOW	0x04
+#define		APM_DISABLED		0x08
+#define		APM_DISENGAGED		0x10
+
+#define	APM_REAL_CONNECT	0x5301	/* int15 only */
+#define	APM_PROT16_CONNECT	0x5302	/* int15 only */
+#define	APM_PROT32_CONNECT	0x5303	/* int15 only */
+#define APM_DISCONNECT		0x5304	/* %bx = APM_DEV_APM_BIOS */
+
+#define APM_CPU_IDLE		0x5305
+#define APM_CPU_BUSY		0x5306
+
+#define APM_SET_PWR_STATE	0x5307
+#define		APM_SYS_READY		0x0000	/* %cx */
+#define		APM_SYS_STANDBY		0x0001
+#define		APM_SYS_SUSPEND		0x0002
+#define		APM_SYS_OFF		0x0003
+#define		APM_LASTREQ_INPROG	0x0004
+#define		APM_LASTREQ_REJECTED	0x0005
+/* 0x0006 - 0x001f	Reserved system states    */
+/* 0x0020 - 0x003f	OEM-defined system states */
+/* 0x0040 - 0x007f	OEM-defined device states */
+/* 0x0080 - 0xffff	Reserved device states    */
+
+/* system standby is device ID (%bx) 0x0001, APM_SYS_STANDBY */
+/* system suspend is device ID (%bx) 0x0001, APM_SYS_SUSPEND */
+
+#define APM_PWR_MGT_ENABLE	0x5308
+#define		APM_MGT_ALL	0xffff	/* %bx */
+#define		APM_MGT_DISABLE	0x0	/* %cx */
+#define		APM_MGT_ENABLE	0x1
+
+#define APM_SYSTEM_DEFAULTS	0x5309
+#define		APM_DEFAULTS_ALL	0xffff	/* %bx */
+
+#define APM_POWER_STATUS	0x530a
+#define		APM_AC_OFF		0x00
+#define		APM_AC_ON		0x01
+#define		APM_AC_BACKUP		0x02
+#define		APM_AC_UNKNOWN		0xff
+#define		APM_BATT_HIGH		0x00
+#define		APM_BATT_LOW		0x01
+#define		APM_BATT_CRITICAL	0x02
+#define		APM_BATT_CHARGING	0x03
+#define		APM_BATT_UNKNOWN	0xff
+#define		APM_BATT_FLAG_HIGH	0x01
+#define		APM_BATT_FLAG_LOW	0x02
+#define		APM_BATT_FLAG_CRITICAL	0x04
+#define		APM_BATT_FLAG_CHARGING	0x08
+#define		APM_BATT_FLAG_NOBATTERY	0x10
+#define		APM_BATT_FLAG_NOSYSBATT	0x80
+#define		APM_BATT_LIFE_UNKNOWN	0xff
+#define		BATT_STATE(regp) ((regp)->bx & 0xff)
+#define		BATT_FLAGS(regp) (((regp)->cx & 0xff00) >> 8)
+#define		AC_STATE(regp) (((regp)->bx & 0xff00) >> 8)
+#define		BATT_LIFE(regp) ((regp)->cx & 0xff) /* in % */
+/* Return time in minutes. According to the APM 1.2 spec:
+	DX = Remaining battery life -- time units
+		Bit 15 = 0	Time units are seconds
+		       = 1 	Time units are minutes
+		Bits 14-0 =	Number of seconds or minutes */
+#define		BATT_REMAINING(regp) (((regp)->dx & 0x8000) ? \
+				      ((regp)->dx & 0x7fff) : \
+				      ((regp)->dx & 0x7fff)/60)
+#define		BATT_REM_VALID(regp) (((regp)->dx & 0xffff) != 0xffff)
+#define		BATT_COUNT(regp)	((regp)->si)
+
+#define	APM_GET_PM_EVENT	0x530b
+#define		APM_NOEVENT		0x0000
+#define		APM_STANDBY_REQ		0x0001 /* %bx on return */
+#define		APM_SUSPEND_REQ		0x0002
+#define		APM_NORMAL_RESUME	0x0003
+#define		APM_CRIT_RESUME		0x0004 /* suspend/resume happened
+						  without us */
+#define		APM_BATTERY_LOW		0x0005
+#define		APM_POWER_CHANGE	0x0006
+#define		APM_UPDATE_TIME		0x0007
+#define		APM_CRIT_SUSPEND_REQ	0x0008
+#define		APM_USER_STANDBY_REQ	0x0009
+#define		APM_USER_SUSPEND_REQ	0x000A
+#define		APM_SYS_STANDBY_RESUME	0x000B
+#define		APM_CAPABILITY_CHANGE	0x000C	/* apm v1.2 */
+/* 0x000d - 0x00ff	Reserved system events */
+/* 0x0100 - 0x01ff	Reserved device events */
+/* 0x0200 - 0x02ff	OEM-defined APM events */
+/* 0x0300 - 0xffff	Reserved */
+#define		APM_EVENT_MASK		0xffff
+
+#define	APM_EVENT_COMPOSE(t,i)	((((i) & 0x7fff) << 16)|((t) & APM_EVENT_MASK))
+#define	APM_EVENT_TYPE(e)	((e) & APM_EVENT_MASK)
+#define	APM_EVENT_INDEX(e)	((e) >> 16)
+
+#define	APM_GET_POWER_STATE	0x530c
+#define	APM_DEVICE_MGMT_ENABLE	0x530d
+
+#define	APM_DRIVER_VERSION	0x530e
+/* %bx should be DEV value (APM_DEV_APM_BIOS)
+   %ch = driver major vno
+   %cl = driver minor vno
+   return: %ah = conn major; %al = conn minor
+   */
+#define		APM_CONN_MINOR(regp) ((regp)->ax & 0xff)
+#define		APM_CONN_MAJOR(regp) (((regp)->ax & 0xff00) >> 8)
+
+#define APM_PWR_MGT_ENGAGE	0x530F
+#define		APM_MGT_DISENGAGE	0x0	/* %cx */
+#define		APM_MGT_ENGAGE		0x1
+
+/* %bx - APM_DEV_APM_BIOS
+ * %bl - number of batteries
+ * %cx - capabilities
+ */
+#define	APM_GET_CAPABILITIES	0x5310
+#define		APM_NBATTERIES(regp)	((regp)->bx)
+#define		APM_GLOBAL_STANDBY	0x0001
+#define		APM_GLOBAL_SUSPEND	0x0002
+#define		APM_RTIMER_STANDBY	0x0004	/* resume time wakes up */
+#define		APM_RTIMER_SUSPEND	0x0008
+#define		APM_IRRING_STANDBY	0x0010	/* internal ring wakes up */
+#define		APM_IRRING_SUSPEND	0x0020
+#define		APM_PCCARD_STANDBY	0x0040	/* pccard wakes up */
+#define		APM_PCCARD_SUSPEND	0x0080
+
+/* %bx - APM_DEV_APM_BIOS
+ * %cl - function
+ *	for %cl=2 (set resume timer)
+ * %ch - seconds in BCD
+ * %dh - hours in BCD
+ * %dl - minutes in BCD
+ * %si - month in BCD (high), day in BCD (low)
+ * %di - year in BCD
+ */
+#define	APM_RESUME_TIMER	0x5311
+#define		APM_RT_DISABLE	0x0
+#define		APM_RT_GET	0x1
+#define		APM_RT_SET	0x2
+
+/* %bx - APM_DEV_APM_BIOS
+ * %cx - function
+ */
+#define	APM_RESUME_ON_RING	0x5312
+#define		APM_ROR_DISABLE	0x0
+#define		APM_ROR_ENABLE	0x1
+#define		APM_ROR_STATUS	0x2
+
+/* %bx - APM_EDV_APM_BIOS
+ * %cx - function
+ */
+#define	APM_INACTIVITY_TIMER	0x5313
+#define		APM_IT_DISABLE	0x0
+#define		APM_IT_ENABLE	0x1
+#define		APM_IT_STATUS	0x2
+
+/* %bh - function */
+#define APM_OEM			0x5380
+#define		APM_OEM_INSTCHECK	0x7f	/* %bx - OEM ID */
+
+/*
+ * LP (Laptop Package)
+ *
+ * Copyright (C) 1994 by HOSOKAWA Tatsumi <hosokawa@mt.cs.keio.ac.jp>
+ *
+ * This software may be used, modified, copied, and distributed, in
+ * both source and binary form provided that the above copyright and
+ * these terms are retained. Under no circumstances is the author 
+ * responsible for the proper functioning of this software, nor does 
+ * the author assume any responsibility for damages incurred with its 
+ * use.
+ *
+ * Sep., 1994	Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD)
+ */
+
+#define APM_BATTERY_ABSENT 4
+
+struct apm_power_info {
+	u_char battery_state;
+	u_char ac_state;
+	u_char battery_life;
+	u_char spare1;
+	u_int minutes_left;		/* estimate */
+	u_int spare2[6];
+};
+
+struct apm_ctl {
+	u_int dev;
+	u_int mode;
+};
+
+#define	APM_IOC_REJECT	_IOW('A', 0, struct apm_event_info) /* reject request # */
+#define	APM_IOC_STANDBY	_IO('A', 1)	/* put system into standby */
+#define	APM_IOC_SUSPEND	_IO('A', 2)	/* put system into suspend */
+#define	APM_IOC_GETPOWER _IOR('A', 3, struct apm_power_info) /* fetch battery state */
+#define	APM_IOC_DEV_CTL	_IOW('A', 5, struct apm_ctl) /* put device into mode */
+#define APM_IOC_PRN_CTL _IOW('A', 6, int ) /* driver power status msg */
+#define		APM_PRINT_ON	0	/* driver power status displayed */
+#define		APM_PRINT_OFF	1	/* driver power status not displayed */
+#define		APM_PRINT_PCT	2	/* driver power status only displayed
+					   if the percentage changes */
+
+#ifdef _KERNEL
+extern void apm_cpu_busy(void);
+extern void apm_cpu_idle(void);
+extern void apminit(void);
+int apm_set_powstate(u_int devid, u_int powstate);
+int apm_kqfilter(dev_t dev, struct knote *kn);
+#endif /* _KERNEL */
+
+#endif /* _I386_APMVAR_H_ */
diff --git a/sys/arch/amd64/include/asm.h b/sys/arch/amd64/include/asm.h
new file mode 100644
index 00000000000..4dc7f0facac
--- /dev/null
+++ b/sys/arch/amd64/include/asm.h
@@ -0,0 +1,122 @@
+/*	$OpenBSD: asm.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: asm.h,v 1.2 2003/05/02 18:05:47 yamt Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)asm.h	5.5 (Berkeley) 5/7/91
+ */
+
+#ifndef _AMD64_ASM_H_
+#define _AMD64_ASM_H_
+
+#ifdef PIC
+#define PIC_PLT(x)	x@PLT
+#define PIC_GOT(x)	x@GOTPCREL(%rip)
+#else
+#define PIC_PLT(x)	x
+#define PIC_GOT(x)	x
+#endif
+
+# define _C_LABEL(x)	x
+#define	_ASM_LABEL(x)	x
+
+#define CVAROFF(x,y)		(_C_LABEL(x)+y)(%rip)
+
+#ifdef __STDC__
+# define __CONCAT(x,y)	x ## y
+# define __STRING(x)	#x
+#else
+# define __CONCAT(x,y)	x/**/y
+# define __STRING(x)	"x"
+#endif
+
+/* let kernels and others override entrypoint alignment */
+#ifndef _ALIGN_TEXT
+#define _ALIGN_TEXT .align 16, 0x90
+#endif
+
+#define _ENTRY(x) \
+	.text; _ALIGN_TEXT; .globl x; .type x,@function; x:
+
+#ifdef _KERNEL
+/* XXX Can't use __CONCAT() here, as it would be evaluated incorrectly. */
+#ifdef __STDC__
+#define	IDTVEC(name) \
+	.text; ALIGN_TEXT; .globl X ## name; .type X ## name,@function; X ## name:
+#else 
+#define	IDTVEC(name) \
+	.text; ALIGN_TEXT; .globl X/**/name; .type X/**/name,@function; X/**/name:
+#endif /* __STDC__ */ 
+#endif /* _KERNEL */
+
+#ifdef __STDC__
+#define CPUVAR(off)	%gs:CPU_INFO_ ## off
+#else
+#define CPUVAR(off)     %gs:CPU_INFO_/**/off
+#endif
+
+
+#ifdef GPROF
+# define _PROF_PROLOGUE	\
+	pushq %rbp; leaq (%rsp),%rbp; call PIC_PLT(__mcount); popq %rbp
+#else
+# define _PROF_PROLOGUE
+#endif
+
+#define	ENTRY(y)	_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
+#define	NENTRY(y)	_ENTRY(_C_LABEL(y))
+#define	ASENTRY(y)	_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
+
+#define	ASMSTR		.asciz
+
+#define RCSID(x)	.text; .asciz x
+
+#define	WEAK_ALIAS(alias,sym)						\
+	.weak alias;							\
+	alias = sym
+
+/* XXXfvdl do not use stabs here */
+#ifdef __STDC__
+#define	WARN_REFERENCES(sym,msg)					\
+	.stabs msg ## ,30,0,0,0 ;					\
+	.stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0
+#else
+#define	WARN_REFERENCES(sym,msg)					\
+	.stabs msg,30,0,0,0 ;						\
+	.stabs __STRING(sym),1,0,0,0
+#endif /* __STDC__ */
+
+#endif /* !_AMD64_ASM_H_ */
diff --git a/sys/arch/amd64/include/atomic.h b/sys/arch/amd64/include/atomic.h
new file mode 100644
index 00000000000..027415b18c2
--- /dev/null
+++ b/sys/arch/amd64/include/atomic.h
@@ -0,0 +1,96 @@
+/*	$OpenBSD: atomic.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: atomic.h,v 1.1 2003/04/26 18:39:37 fvdl Exp $	*/
+
+/*
+ * Copyright 2002 (c) Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ATOMIC_H
+#define _ATOMIC_H
+
+#ifndef _LOCORE
+
+static __inline u_int64_t
+x86_atomic_testset_u64(volatile u_int64_t *ptr, u_int64_t val) {
+    __asm__ volatile ("xchgq %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
+    return val;
+}
+
+static __inline u_int32_t
+x86_atomic_testset_u32(volatile u_int32_t *ptr, u_int32_t val) {
+    __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
+    return val;
+}
+
+
+
+static __inline int32_t
+x86_atomic_testset_i32(volatile int32_t *ptr, int32_t val) {
+    __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
+    return val;
+}
+
+
+
+static __inline void
+x86_atomic_setbits_u32(volatile u_int32_t *ptr, u_int32_t bits) {
+    __asm __volatile("lock ; orl %1,%0" :  "=m" (*ptr) : "ir" (bits));
+}
+
+static __inline void
+x86_atomic_clearbits_u32(volatile u_int32_t *ptr, u_int32_t bits) {
+    __asm __volatile("lock ; andl %1,%0" :  "=m" (*ptr) : "ir" (~bits));
+}
+
+
+
+static __inline void
+x86_atomic_setbits_u64(volatile u_int64_t *ptr, u_int64_t bits) {
+    __asm __volatile("lock ; orq %1,%0" :  "=m" (*ptr) : "ir" (~bits));
+}
+
+static __inline void
+x86_atomic_clearbits_u64(volatile u_int64_t *ptr, u_int64_t bits) {
+    __asm __volatile("lock ; andq %1,%0" :  "=m" (*ptr) : "ir" (~bits));
+}
+
+#define x86_atomic_testset_ul	x86_atomic_testset_u32
+#define x86_atomic_testset_i	x86_atomic_testset_i32
+#define x86_atomic_setbits_l	x86_atomic_setbits_u32
+#define x86_atomic_setbits_ul	x86_atomic_setbits_u32
+#define x86_atomic_clearbits_l	x86_atomic_clearbits_u32
+#define x86_atomic_clearbits_ul	x86_atomic_clearbits_u32
+
+#endif
+#endif
diff --git a/sys/arch/amd64/include/biosvar.h b/sys/arch/amd64/include/biosvar.h
new file mode 100644
index 00000000000..55922d4e002
--- /dev/null
+++ b/sys/arch/amd64/include/biosvar.h
@@ -0,0 +1,259 @@
+/* XXX - DSR */
+/*	$OpenBSD: biosvar.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*
+ * Copyright (c) 1997-1999 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Michael Shalayeff.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_BIOSVAR_H_
+#define _I386_BIOSVAR_H_
+#pragma pack(1)
+
+	/* some boxes put apm data seg in the 2nd page */
+#define	BOOTARG_OFF	(NBPG*2)
+#define	BOOTARG_LEN	(NBPG*1)
+#define	BOOTBIOS_ADDR	(0x7c00)
+
+	/* BIOS configure flags */
+#define	BIOSF_BIOS32	0x0001
+#define	BIOSF_PCIBIOS	0x0002
+#define	BIOSF_PROMSCAN	0x0004
+
+/* BIOS media ID */
+#define BIOSM_F320K	0xff	/* floppy ds/sd  8 spt */
+#define	BIOSM_F160K	0xfe	/* floppy ss/sd  8 spt */
+#define	BIOSM_F360K	0xfd	/* floppy ds/sd  9 spt */
+#define	BIOSM_F180K	0xfc	/* floppy ss/sd  9 spt */
+#define	BIOSM_ROMD	0xfa	/* ROM disk */
+#define	BIOSM_F120M	0xf9	/* floppy ds/hd 15 spt 5.25" */
+#define	BIOSM_F720K	0xf9	/* floppy ds/dd  9 spt 3.50" */
+#define	BIOSM_HD	0xf8	/* hard drive */
+#define	BIOSM_F144K	0xf0	/* floppy ds/hd 18 spt 3.50" */
+#define	BIOSM_OTHER	0xf0	/* any other */
+
+/*
+ * BIOS memory maps
+ */
+#define	BIOS_MAP_END	0x00	/* End of array XXX - special */
+#define	BIOS_MAP_FREE	0x01	/* Usable memory */
+#define	BIOS_MAP_RES	0x02	/* Reserved memory */
+#define	BIOS_MAP_ACPI	0x03	/* ACPI Reclaim memory */
+#define	BIOS_MAP_NVS	0x04	/* ACPI NVS memory */
+
+/*
+ * Optional ROM header
+ */
+typedef
+struct bios_romheader {
+	u_int16_t	signature;	/* 0xaa55 */
+	u_int8_t	len;		/* length in pages (512 bytes) */
+	u_int32_t	entry;		/* initialization entry point */
+	u_int8_t	reserved[19];
+	u_int16_t	pnpheader;	/* offset to PnP expansion header */
+} *bios_romheader_t;
+
+/*
+ * BIOS32
+ */
+typedef
+struct bios32_header {
+	u_int32_t	signature;	/* 00: signature "_32_" */
+	u_int32_t	entry;		/* 04: entry point */
+	u_int8_t	rev;		/* 08: revision */
+	u_int8_t	length;		/* 09: header length */
+	u_int8_t	cksum;		/* 0a: modulo 256 checksum */
+	u_int8_t	reserved[5];
+} *bios32_header_t;
+
+typedef
+struct bios32_entry_info {
+	paddr_t	bei_base;
+	psize_t	bei_size;
+	paddr_t	bei_entry;
+} *bios32_entry_info_t;
+
+typedef
+struct bios32_entry {
+	u_int32_t offset;
+	u_int16_t segment;
+} *bios32_entry_t;
+
+#define	BIOS32_START	0xe0000
+#define	BIOS32_SIZE	0x20000
+#define	BIOS32_END	(BIOS32_START + BIOS32_SIZE - 0x10)
+
+#define	BIOS32_MAKESIG(a, b, c, d) \
+	((a) | ((b) << 8) | ((c) << 16) | ((d) << 24))
+#define	BIOS32_SIGNATURE	BIOS32_MAKESIG('_', '3', '2', '_')
+#define	PCIBIOS_SIGNATURE	BIOS32_MAKESIG('$', 'P', 'C', 'I')
+
+/*
+ * CTL_BIOS definitions.
+ */
+#define	BIOS_DEV		1	/* int: BIOS boot device */
+#define	BIOS_DISKINFO		2	/* struct: BIOS boot device info */
+#define BIOS_CKSUMLEN		3	/* int: disk cksum block count */
+#define	BIOS_MAXID		4	/* number of valid machdep ids */
+
+#define	CTL_BIOS_NAMES { \
+	{ 0, 0 }, \
+	{ "biosdev", CTLTYPE_INT }, \
+	{ "diskinfo", CTLTYPE_STRUCT }, \
+	{ "cksumlen", CTLTYPE_INT }, \
+}
+
+#define	BOOTARG_MEMMAP 0
+typedef struct _bios_memmap {
+	u_int64_t addr;		/* Beginning of block */
+	u_int64_t size;		/* Size of block */
+	u_int32_t type;		/* Type of block */
+} bios_memmap_t;
+
+/* Info about disk from the bios, plus the mapping from
+ * BIOS numbers to BSD major (driver?) number.
+ *
+ * Also, do not bother with BIOSN*() macros, just parcel
+ * the info out, and use it like this.  This makes for less
+ * of a dependance on BIOSN*() macros having to be the same
+ * across /boot, /bsd, and userland.
+ */
+#define	BOOTARG_DISKINFO 1
+typedef struct _bios_diskinfo {
+	/* BIOS section */
+	int bios_number;	/* BIOS number of drive (or -1) */
+	u_int bios_cylinders;	/* BIOS cylinders */
+	u_int bios_heads;	/* BIOS heads */
+	u_int bios_sectors;	/* BIOS sectors */
+	int bios_edd;		/* EDD support */
+
+	/* BSD section */
+	dev_t bsd_dev;		/* BSD device */
+
+	/* Checksum section */
+	u_int32_t checksum;	/* Checksum for drive */
+
+	/* Misc. flags */
+	u_int32_t flags;
+#define BDI_INVALID	0x00000001	/* I/O error during checksumming */
+#define BDI_GOODLABEL	0x00000002	/* Had SCSI or ST506/ESDI disklabel */
+#define BDI_BADLABEL	0x00000004	/* Had another disklabel */
+#define BDI_PICKED	0x80000000	/* kernel-only: cksum matched */
+
+} bios_diskinfo_t;
+
+#define	BOOTARG_APMINFO 2
+typedef struct _bios_apminfo {
+	/* APM_CONNECT returned values */
+	u_int	apm_detail;
+	u_int	apm_code32_base;
+	u_int	apm_code16_base;
+	u_int	apm_code_len;
+	u_int	apm_data_base;
+	u_int	apm_data_len;
+	u_int	apm_entry;
+	u_int	apm_code16_len;
+} bios_apminfo_t;
+
+#define	BOOTARG_CKSUMLEN 3		/* u_int32_t */
+
+#define	BOOTARG_PCIINFO 4
+typedef struct _bios_pciinfo {
+	/* PCI BIOS v2.0+ - Installation check values */
+	u_int32_t	pci_chars;	/* Characteristics (%eax) */
+	u_int32_t	pci_rev;	/* BCD Revision (%ebx) */
+	u_int32_t	pci_entry32;	/* PM entry point for PCI BIOS */
+	u_int32_t	pci_lastbus;	/* Number of last PCI bus */
+} bios_pciinfo_t;
+
+#define	BOOTARG_CONSDEV	5
+typedef struct _bios_consdev {
+	dev_t	consdev;
+	int	conspeed;
+} bios_consdev_t;
+
+#if defined(_KERNEL) || defined (_STANDALONE)
+
+#ifdef _LOCORE
+#define	DOINT(n)	int	$0x20+(n)
+#else
+#define	DOINT(n)	"int $0x20+(" #n ")"
+
+extern struct BIOS_regs {
+	u_int32_t	biosr_ax;
+	u_int32_t	biosr_cx;
+	u_int32_t	biosr_dx;
+	u_int32_t	biosr_bx;
+	u_int32_t	biosr_bp;
+	u_int32_t	biosr_si;
+	u_int32_t	biosr_di;
+	u_int32_t	biosr_ds;
+	u_int32_t	biosr_es;
+}	BIOS_regs;
+
+#ifdef _KERNEL
+#include <machine/bus.h>
+
+struct bios_attach_args {
+	char *bios_dev;
+	u_int bios_func;
+	bus_space_tag_t bios_iot;
+	bus_space_tag_t bios_memt;
+	union {
+		void *_p;
+		bios_apminfo_t *_bios_apmp;
+	} _;
+};
+
+#define	bios_apmp	_._bios_apmp
+
+struct consdev;
+struct proc;
+
+int bios_sysctl(int *, u_int, void *, size_t *, void *, size_t, struct proc *);
+
+void bioscnprobe(struct consdev *);
+void bioscninit(struct consdev *);
+void bioscnputc(dev_t, int);
+int bioscngetc(dev_t);
+void bioscnpollc(dev_t, int);
+void bios_getopt(void);
+
+/* bios32.c */
+int  bios32_service(u_int32_t, bios32_entry_t, bios32_entry_info_t);
+
+extern u_int bootapiver;
+extern bios_memmap_t *bios_memmap;
+
+#endif /* _KERNEL */
+#endif /* _LOCORE */
+#endif /* _KERNEL || _STANDALONE */
+
+#pragma pack()
+#endif /* _I386_BIOSVAR_H_ */
diff --git a/sys/arch/amd64/include/bootinfo.h b/sys/arch/amd64/include/bootinfo.h
new file mode 100644
index 00000000000..8751e66a3be
--- /dev/null
+++ b/sys/arch/amd64/include/bootinfo.h
@@ -0,0 +1,159 @@
+/*	$OpenBSD: bootinfo.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: bootinfo.h,v 1.2 2003/04/16 19:16:42 dsl Exp $	*/
+
+/*
+ * Copyright (c) 1997
+ *	Matthias Drochner.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project
+ *	by Matthias Drochner.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _LOCORE
+
+struct btinfo_common {
+	int len;
+	int type;
+};
+
+#define BTINFO_BOOTPATH 0
+#define BTINFO_BOOTDISK 3
+#define BTINFO_NETIF 4
+#define BTINFO_CONSOLE 6
+#define BTINFO_BIOSGEOM 7
+#define BTINFO_SYMTAB 8
+#define BTINFO_MEMMAP 9
+
+struct btinfo_bootpath {
+	struct btinfo_common common;
+	char bootpath[80];
+};
+
+struct btinfo_bootdisk {
+	struct btinfo_common common;
+	int labelsector; /* label valid if != -1 */
+	struct {
+		u_int16_t type, checksum;
+		char packname[16];
+	} label;
+	int biosdev;
+	int partition;
+};
+
+struct btinfo_netif {
+	struct btinfo_common common;
+	char ifname[16];
+	int bus;
+#define BI_BUS_ISA 0
+#define BI_BUS_PCI 1
+	union {
+		unsigned int iobase; /* ISA */
+		unsigned int tag; /* PCI, BIOS format */
+	} addr;
+};
+
+struct btinfo_console {
+	struct btinfo_common common;
+	char devname[16];
+	int addr;
+	int speed;
+};
+
+struct btinfo_symtab {
+	struct btinfo_common common;
+	int nsym;
+	int ssym;
+	int esym;
+};
+
+struct bi_memmap_entry {
+	u_int64_t addr;		/* beginning of block */	/* 8 */
+	u_int64_t size;		/* size of block */		/* 8 */
+	u_int32_t type;		/* type of block */		/* 4 */
+} __attribute__((packed));				/*	== 20 */
+
+#define	BIM_Memory	1	/* available RAM usable by OS */
+#define	BIM_Reserved	2	/* in use or reserved by the system */
+#define	BIM_ACPI	3	/* ACPI Reclaim memory */
+#define	BIM_NVS		4	/* ACPI NVS memory */
+
+struct btinfo_memmap {
+	struct btinfo_common common;
+	int num;
+	struct bi_memmap_entry entry[1]; /* var len */
+};
+
+#include <machine/disklabel.h>
+
+/*
+ * Structure describing disk info as seen by the BIOS.
+ */
+struct bi_biosgeom_entry {
+	int		sec, head, cyl;		/* geometry */
+	u_int64_t	totsec;			/* LBA sectors from ext int13 */
+	int		flags, dev;		/* flags, BIOS device # */
+#define BI_GEOM_INVALID		0x000001
+#define BI_GEOM_EXTINT13	0x000002
+#ifdef BIOSDISK_EXT13INFO_V3
+#define BI_GEOM_BADCKSUM	0x000004	/* v3.x checksum invalid */
+#define BI_GEOM_BUS_MASK	0x00ff00	/* connecting bus type */
+#define BI_GEOM_BUS_ISA		0x000100
+#define BI_GEOM_BUS_PCI		0x000200
+#define BI_GEOM_BUS_OTHER	0x00ff00
+#define BI_GEOM_IFACE_MASK	0xff0000	/* interface type */
+#define BI_GEOM_IFACE_ATA	0x010000
+#define BI_GEOM_IFACE_ATAPI	0x020000
+#define BI_GEOM_IFACE_SCSI	0x030000
+#define BI_GEOM_IFACE_USB	0x040000
+#define BI_GEOM_IFACE_1394	0x050000	/* Firewire */
+#define BI_GEOM_IFACE_FIBRE	0x060000	/* Fibre channel */
+#define BI_GEOM_IFACE_OTHER	0xff0000	
+	unsigned int	cksum;			/* MBR checksum */
+	u_int		interface_path;		/* ISA iobase PCI bus/dev/fun */
+	u_int64_t	device_path;
+	int		res0;			/* future expansion; 0 now */
+#else
+	unsigned int	cksum;			/* MBR checksum */
+	int		res0, res1, res2, res3;	/* future expansion; 0 now */
+#endif
+	struct dos_partition dosparts[NDOSPART]; /* MBR itself */
+} __attribute__((packed));
+
+struct btinfo_biosgeom {
+	struct btinfo_common common;
+	int num;
+	struct bi_biosgeom_entry disk[1]; /* var len */
+};
+
+#ifdef _KERNEL
+void *lookup_bootinfo __P((int));
+#endif
+#endif /* _LOCORE */
+
+#ifdef _KERNEL
+#define BOOTINFO_MAXSIZE 4096
+#endif
diff --git a/sys/arch/amd64/include/bus.h b/sys/arch/amd64/include/bus.h
new file mode 100644
index 00000000000..4a1c326b8fc
--- /dev/null
+++ b/sys/arch/amd64/include/bus.h
@@ -0,0 +1,1158 @@
+/*	$OpenBSD: bus.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: bus.h,v 1.6 1996/11/10 03:19:25 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
+ * Copyright (c) 1996 Jason R. Thorpe.  All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Christopher G. Demetriou
+ *	for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_BUS_H_
+#define _X86_BUS_H_
+
+#include <machine/pio.h>
+
+/*
+ * Values for the x86 bus space tag, not to be used directly by MI code.
+ */
+#define	X86_BUS_SPACE_IO	0	/* space is i/o space */
+#define X86_BUS_SPACE_MEM	1	/* space is mem space */
+
+/*
+ * Bus address and size types
+ */
+typedef u_long bus_addr_t;
+typedef u_long bus_size_t;
+
+/*
+ * Access methods for bus resources and address space.
+ */
+typedef	int bus_space_tag_t;
+typedef	u_long bus_space_handle_t;
+
+#define	bus_space_map(t, a, s, f, hp)	x86_memio_map((t),(a),(s),(f),(hp))
+#define	bus_space_unmap(t, h, s)	x86_memio_unmap((t),(h),(s))
+#define bus_space_subregion(t, h, o, s, nhp)	\
+    x86_memio_subregion((t), (h), (o), (s), (nhp))
+
+int	x86_memio_map(bus_space_tag_t t, bus_addr_t addr,
+    bus_size_t size, int flags, bus_space_handle_t *bshp);
+/* like map, but without extent map checking/allocation */ 
+int	_x86_memio_map(bus_space_tag_t t, bus_addr_t addr,
+    bus_size_t size, int flags, bus_space_handle_t *bshp);
+
+/* 
+ *      int bus_space_unmap(bus_space_tag_t t,
+ *          bus_space_handle_t bsh, bus_size_t size);
+ * 
+ * Unmap a region of bus space.
+ */
+ 
+void	x86_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
+	    bus_size_t size);
+void	_x86_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
+	    bus_size_t size, bus_addr_t *);
+
+/* like bus_space_map(), but without extent map checking/allocation */
+int	_bus_space_map(bus_space_tag_t t, bus_addr_t addr,
+	    bus_size_t size, int cacheable, bus_space_handle_t *bshp);
+
+int	bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
+	    bus_addr_t rend, bus_size_t size, bus_size_t align,
+	    bus_size_t boundary, int cacheable, bus_addr_t *addrp,
+	    bus_space_handle_t *bshp);
+void	bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
+	    bus_size_t size);
+
+/*
+ *      int bus_space_subregion(bus_space_tag_t t,
+ *          bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
+ *          bus_space_handle_t *nbshp);
+ * 
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+ 
+int	x86_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
+	    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
+
+/*
+ *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset);
+ *
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+#define	bus_space_read_1(t, h, o)					\
+	((t) == X86_BUS_SPACE_IO ? (inb((h) + (o))) :			\
+	    (*(volatile u_int8_t *)((h) + (o))))
+
+#define	bus_space_read_2(t, h, o)					\
+	((t) == X86_BUS_SPACE_IO ? (inw((h) + (o))) :			\
+	    (*(volatile u_int16_t *)((h) + (o))))
+
+#define	bus_space_read_4(t, h, o)					\
+	((t) == X86_BUS_SPACE_IO ? (inl((h) + (o))) :			\
+	    (*(volatile u_int32_t *)((h) + (o))))
+
+#if 0	/* Cause a link error for bus_space_read_8 */
+#define	bus_space_read_8(t, h, o)	!!! bus_space_read_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_read_multi_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t *addr, size_t count);
+ *
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+#define	bus_space_read_multi_1(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		insb((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	movb (%2),%%al				;	\
+			stosb					;	\
+			loop 1b"				: 	\
+		    "=D" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o))       :	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_read_multi_2(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		insw((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	movw (%2),%%ax				;	\
+			stosw					;	\
+			loop 1b"				:	\
+		    "=D" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o))       :	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_read_multi_4(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		insl((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	movl (%2),%%eax				;	\
+			stosl					;	\
+			loop 1b"				:	\
+		    "=D" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o))       :       \
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#if 0	/* Cause a link error for bus_space_read_multi_8 */
+#define	bus_space_read_multi_8	!!! bus_space_read_multi_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_read_raw_multi_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_int8_t *addr, size_t count);
+ *
+ * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.  The buffer
+ * must have proper alignment for the N byte wide entities.  Furthermore
+ * possible byte-swapping should be done by these functions.
+ */
+
+#define	bus_space_read_raw_multi_2(t, h, o, a, c) \
+    bus_space_read_multi_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
+#define	bus_space_read_raw_multi_4(t, h, o, a, c) \
+    bus_space_read_multi_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
+
+#if 0	/* Cause a link error for bus_space_read_raw_multi_8 */
+#define	bus_space_read_raw_multi_8 \
+    !!! bus_space_read_raw_multi_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_read_region_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t *addr, size_t count);
+ *
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+
+#define	bus_space_read_region_1(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	inb %w1,%%al				;	\
+			stosb					;	\
+			incl %1					;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=D" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsb"					:	\
+		    "=S" (dummy1), "=D" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_read_region_2(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	inw %w1,%%ax				;	\
+			stosw					;	\
+			addl $2,%1				;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=D" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsw"					:	\
+		    "=S" (dummy1), "=D" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_read_region_4(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	inl %w1,%%eax				;	\
+			stosl					;	\
+			addl $4,%1				;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=D" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsl"					:	\
+		    "=S" (dummy1), "=D" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define bus_space_read_region_stream_1 bus_space_read_region_1
+#if 0	/* Cause a link error for bus_space_read_region_8 */
+#define	bus_space_read_region_8	!!! bus_space_read_region_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_read_raw_region_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_int8_t *addr, size_t count);
+ *
+ * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.  The buffer must have proper alignment for the N byte
+ * wide entities.  Furthermore possible byte-swapping should be done by
+ * these functions.
+ */
+
+#define	bus_space_read_raw_region_2(t, h, o, a, c) \
+    bus_space_read_region_2((t), (h), (o), (u_int16_t *)(a), (c) >> 1)
+#define	bus_space_read_raw_region_4(t, h, o, a, c) \
+    bus_space_read_region_4((t), (h), (o), (u_int32_t *)(a), (c) >> 2)
+
+#if 0	/* Cause a link error for bus_space_read_raw_region_8 */
+#define	bus_space_read_raw_region_8 \
+    !!! bus_space_read_raw_region_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_write_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t value);
+ *
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+#define	bus_space_write_1(t, h, o, v)	do {				\
+	if ((t) == X86_BUS_SPACE_IO)					\
+		outb((h) + (o), (v));					\
+	else								\
+		((void)(*(volatile u_int8_t *)((h) + (o)) = (v)));	\
+} while (0)
+
+#define	bus_space_write_2(t, h, o, v)	do {				\
+	if ((t) == X86_BUS_SPACE_IO)					\
+		outw((h) + (o), (v));					\
+	else								\
+		((void)(*(volatile u_int16_t *)((h) + (o)) = (v)));	\
+} while (0)
+
+#define	bus_space_write_4(t, h, o, v)	do {				\
+	if ((t) == X86_BUS_SPACE_IO)					\
+		outl((h) + (o), (v));					\
+	else								\
+		((void)(*(volatile u_int32_t *)((h) + (o)) = (v)));	\
+} while (0)
+
+#if 0	/* Cause a link error for bus_space_write_8 */
+#define	bus_space_write_8	!!! bus_space_write_8 not implemented !!!
+#endif
+
+/*
+ *	void bus_space_write_multi_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    const u_intN_t *addr, size_t count);
+ *
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+#define	bus_space_write_multi_1(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		outsb((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsb					;	\
+			movb %%al,(%2)				;	\
+			loop 1b"				: 	\
+		    "=S" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o)));		\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define bus_space_write_multi_2(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		outsw((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsw					;	\
+			movw %%ax,(%2)				;	\
+			loop 1b"				: 	\
+		    "=S" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o)));		\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define bus_space_write_multi_4(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		outsl((h) + (o), (ptr), (cnt));				\
+	} else {							\
+		void *dummy1;						\
+		int dummy2;						\
+		void *dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsl					;	\
+			movl %%eax,(%2)				;	\
+			loop 1b"				: 	\
+		    "=S" (dummy1), "=c" (dummy2), "=r" (dummy3), "=&a" (__x) : \
+		    "0" ((ptr)), "1" ((cnt)), "2" ((h) + (o)));		\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#if 0	/* Cause a link error for bus_space_write_multi_8 */
+#define	bus_space_write_multi_8(t, h, o, a, c)				\
+			!!! bus_space_write_multi_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_write_raw_multi_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    const u_int8_t *addr, size_t count);
+ *
+ * Write `count' bytes in 2, 4 or 8 byte wide quantities from the buffer
+ * provided to bus space described by tag/handle/offset.  The buffer
+ * must have proper alignment for the N byte wide entities.  Furthermore
+ * possible byte-swapping should be done by these functions.
+ */
+
+#define	bus_space_write_raw_multi_2(t, h, o, a, c) \
+    bus_space_write_multi_2((t), (h), (o), (const u_int16_t *)(a), (c) >> 1)
+#define	bus_space_write_raw_multi_4(t, h, o, a, c) \
+    bus_space_write_multi_4((t), (h), (o), (const u_int32_t *)(a), (c) >> 2)
+
+#if 0	/* Cause a link error for bus_space_write_raw_multi_8 */
+#define	bus_space_write_raw_multi_8 \
+    !!! bus_space_write_raw_multi_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_write_region_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    const u_intN_t *addr, size_t count);
+ *
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
+ * to bus space described by tag/handle starting at `offset'.
+ */
+
+#define	bus_space_write_region_1(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsb					;	\
+			outb %%al,%w1				;	\
+			incl %1					;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=S" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsb"					:	\
+		    "=D" (dummy1), "=S" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_write_region_2(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsw					;	\
+			outw %%ax,%w1				;	\
+			addl $2,%1				;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=S" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsw"					:	\
+		    "=D" (dummy1), "=S" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#define	bus_space_write_region_4(t, h, o, ptr, cnt)			\
+do {									\
+	if ((t) == X86_BUS_SPACE_IO) {					\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		int __x;						\
+		__asm __volatile("					\
+			cld					;	\
+		1:	lodsl					;	\
+			outl %%eax,%w1				;	\
+			addl $4,%1				;	\
+			loop 1b"				: 	\
+		    "=&a" (__x), "=d" (dummy1), "=S" (dummy2),		\
+		    "=c" (dummy3)				:	\
+		    "1" ((h) + (o)), "2" ((ptr)), "3" ((cnt))	:	\
+		    "memory");						\
+	} else {							\
+		int dummy1;						\
+		void *dummy2;						\
+		int dummy3;						\
+		__asm __volatile("					\
+			cld					;	\
+			repne					;	\
+			movsl"					:	\
+		    "=D" (dummy1), "=S" (dummy2), "=c" (dummy3)	:	\
+		    "0" ((h) + (o)), "1" ((ptr)), "2" ((cnt))	:	\
+		    "memory");						\
+	}								\
+} while (/* CONSTCOND */ 0)
+
+#if 0	/* Cause a link error for bus_space_write_region_8 */
+#define	bus_space_write_region_8					\
+			!!! bus_space_write_region_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_write_raw_region_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    const u_int8_t *addr, size_t count);
+ *
+ * Write `count' bytes in 2, 4 or 8 byte wide quantities to bus space
+ * described by tag/handle and starting at `offset' from the
+ * buffer provided.  The buffer must have proper alignment for the N byte
+ * wide entities.  Furthermore possible byte-swapping should be done by
+ * these functions.
+ */
+
+#define	bus_space_write_raw_region_2(t, h, o, a, c) \
+    bus_space_write_region_2((t), (h), (o), (const u_int16_t *)(a), (c) >> 1)
+#define	bus_space_write_raw_region_4(t, h, o, a, c) \
+    bus_space_write_region_4((t), (h), (o), (const u_int32_t *)(a), (c) >> 2)
+
+#if 0	/* Cause a link error for bus_space_write_raw_region_8 */
+#define	bus_space_write_raw_region_8 \
+    !!! bus_space_write_raw_region_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_set_multi_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t val, size_t count);
+ *
+ * Write the 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle/offset `count' times.
+ */
+
+static __inline void x86_memio_set_multi_1(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int8_t, size_t);
+static __inline void x86_memio_set_multi_2(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int16_t, size_t);
+static __inline void x86_memio_set_multi_4(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int32_t, size_t);
+
+#define	bus_space_set_multi_1(t, h, o, v, c)				\
+	x86_memio_set_multi_1((t), (h), (o), (v), (c))
+
+#define	bus_space_set_multi_2(t, h, o, v, c)				\
+	x86_memio_set_multi_2((t), (h), (o), (v), (c))
+
+#define	bus_space_set_multi_4(t, h, o, v, c)				\
+	x86_memio_set_multi_4((t), (h), (o), (v), (c))
+
+static __inline void
+x86_memio_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int8_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		while (c--)
+			outb(addr, v);
+	else
+		while (c--)
+			*(volatile u_int8_t *)(addr) = v;
+}
+
+static __inline void
+x86_memio_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int16_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		while (c--)
+			outw(addr, v);
+	else
+		while (c--)
+			*(volatile u_int16_t *)(addr) = v;
+}
+
+static __inline void
+x86_memio_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int32_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		while (c--)
+			outl(addr, v);
+	else
+		while (c--)
+			*(volatile u_int32_t *)(addr) = v;
+}
+
+#if 0	/* Cause a link error for bus_space_set_multi_8 */
+#define	bus_space_set_multi_8					\
+			!!! bus_space_set_multi_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_set_region_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t val, size_t count);
+ *
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static __inline void x86_memio_set_region_1(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int8_t, size_t);
+static __inline void x86_memio_set_region_2(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int16_t, size_t);
+static __inline void x86_memio_set_region_4(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, u_int32_t, size_t);
+
+#define	bus_space_set_region_1(t, h, o, v, c)				\
+	x86_memio_set_region_1((t), (h), (o), (v), (c))
+
+#define	bus_space_set_region_2(t, h, o, v, c)				\
+	x86_memio_set_region_2((t), (h), (o), (v), (c))
+
+#define	bus_space_set_region_4(t, h, o, v, c)				\
+	x86_memio_set_region_4((t), (h), (o), (v), (c))
+
+static __inline void
+x86_memio_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int8_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		for (; c != 0; c--, addr++)
+			outb(addr, v);
+	else
+		for (; c != 0; c--, addr++)
+			*(volatile u_int8_t *)(addr) = v;
+}
+
+static __inline void
+x86_memio_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int16_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		for (; c != 0; c--, addr += 2)
+			outw(addr, v);
+	else
+		for (; c != 0; c--, addr += 2)
+			*(volatile u_int16_t *)(addr) = v;
+}
+
+static __inline void
+x86_memio_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
+    u_int32_t v, size_t c)
+{
+	bus_addr_t addr = h + o;
+
+	if (t == X86_BUS_SPACE_IO)
+		for (; c != 0; c--, addr += 4)
+			outl(addr, v);
+	else
+		for (; c != 0; c--, addr += 4)
+			*(volatile u_int32_t *)(addr) = v;
+}
+
+#if 0	/* Cause a link error for bus_space_set_region_8 */
+#define	bus_space_set_region_8					\
+			!!! bus_space_set_region_8 unimplemented !!!
+#endif
+
+/*
+ *	void bus_space_copy_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh1, bus_size_t off1,
+ *	    bus_space_handle_t bsh2, bus_size_t off2,
+ *	    size_t count);
+ *
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+
+#define bus_space_copy_1 bus_space_copy_region_1
+#define bus_space_copy_2 bus_space_copy_region_2
+#define bus_space_copy_4 bus_space_copy_region_4
+#define bus_space_copy_8 bus_space_copy_region_8
+
+static __inline void x86_memio_copy_region_1(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, bus_space_handle_t,
+	bus_size_t, size_t);
+static __inline void x86_memio_copy_region_2(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, bus_space_handle_t,
+	bus_size_t, size_t);
+static __inline void x86_memio_copy_region_4(bus_space_tag_t,
+	bus_space_handle_t, bus_size_t, bus_space_handle_t,
+	bus_size_t, size_t);
+
+#define	bus_space_copy_region_1(t, h1, o1, h2, o2, c)			\
+	x86_memio_copy_region_1((t), (h1), (o1), (h2), (o2), (c))
+
+#define	bus_space_copy_region_2(t, h1, o1, h2, o2, c)			\
+	x86_memio_copy_region_2((t), (h1), (o1), (h2), (o2), (c))
+
+#define	bus_space_copy_region_4(t, h1, o1, h2, o2, c)			\
+	x86_memio_copy_region_4((t), (h1), (o1), (h2), (o2), (c))
+
+static __inline void
+x86_memio_copy_region_1(bus_space_tag_t t,
+    bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, size_t c)
+{
+	bus_addr_t addr1 = h1 + o1;
+	bus_addr_t addr2 = h2 + o2;
+
+	if (t == X86_BUS_SPACE_IO) {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1++, addr2++)
+				outb(addr2, inb(addr1));
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += (c - 1), addr2 += (c - 1);
+			    c != 0; c--, addr1--, addr2--)
+				outb(addr2, inb(addr1));
+		}
+	} else {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1++, addr2++)
+				*(volatile u_int8_t *)(addr2) =
+				    *(volatile u_int8_t *)(addr1);
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += (c - 1), addr2 += (c - 1);
+			    c != 0; c--, addr1--, addr2--)
+				*(volatile u_int8_t *)(addr2) =
+				    *(volatile u_int8_t *)(addr1);
+		}
+	}
+}
+
+static __inline void
+x86_memio_copy_region_2(bus_space_tag_t t,
+    bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, size_t c)
+{
+	bus_addr_t addr1 = h1 + o1;
+	bus_addr_t addr2 = h2 + o2;
+
+	if (t == X86_BUS_SPACE_IO) {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1 += 2, addr2 += 2)
+				outw(addr2, inw(addr1));
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
+			    c != 0; c--, addr1 -= 2, addr2 -= 2)
+				outw(addr2, inw(addr1));
+		}
+	} else {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1 += 2, addr2 += 2)
+				*(volatile u_int16_t *)(addr2) =
+				    *(volatile u_int16_t *)(addr1);
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
+			    c != 0; c--, addr1 -= 2, addr2 -= 2)
+				*(volatile u_int16_t *)(addr2) =
+				    *(volatile u_int16_t *)(addr1);
+		}
+	}
+}
+
+static __inline void
+x86_memio_copy_region_4(bus_space_tag_t t,
+    bus_space_handle_t h1, bus_size_t o1,
+    bus_space_handle_t h2, bus_size_t o2, size_t c)
+{
+	bus_addr_t addr1 = h1 + o1;
+	bus_addr_t addr2 = h2 + o2;
+
+	if (t == X86_BUS_SPACE_IO) {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1 += 4, addr2 += 4)
+				outl(addr2, inl(addr1));
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
+			    c != 0; c--, addr1 -= 4, addr2 -= 4)
+				outl(addr2, inl(addr1));
+		}
+	} else {
+		if (addr1 >= addr2) {
+			/* src after dest: copy forward */
+			for (; c != 0; c--, addr1 += 4, addr2 += 4)
+				*(volatile u_int32_t *)(addr2) =
+				    *(volatile u_int32_t *)(addr1);
+		} else {
+			/* dest after src: copy backwards */
+			for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
+			    c != 0; c--, addr1 -= 4, addr2 -= 4)
+				*(volatile u_int32_t *)(addr2) =
+				    *(volatile u_int32_t *)(addr1);
+		}
+	}
+}
+
+#if 0	/* Cause a link error for bus_space_copy_8 */
+#define	bus_space_copy_8					\
+			!!! bus_space_copy_8 unimplemented !!!
+#endif
+
+/*
+ * Bus read/write barrier methods.
+ *
+ *	void bus_space_barrier(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    bus_size_t len, int flags);
+ *
+ * Note: the x86 does not currently require barriers, but we must
+ * provide the flags to MI code.
+ */
+#define	bus_space_barrier(t, h, o, l, f)	\
+	((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
+#define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
+#define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */
+/* Compatibility defines */
+#define	BUS_BARRIER_READ	BUS_SPACE_BARRIER_READ
+#define	BUS_BARRIER_WRITE	BUS_SPACE_BARRIER_WRITE
+
+/*
+ * Flags used in various bus DMA methods.
+ */
+#define	BUS_DMA_WAITOK		0x000	/* safe to sleep (pseudo-flag) */
+#define	BUS_DMA_NOWAIT		0x001	/* not safe to sleep */
+#define	BUS_DMA_ALLOCNOW	0x002	/* perform resource allocation now */
+#define	BUS_DMA_COHERENT	0x004	/* hint: map memory DMA coherent */
+#define	BUS_DMA_BUS1		0x010	/* placeholders for bus functions... */
+#define	BUS_DMA_BUS2		0x020
+#define	BUS_DMA_BUS3		0x040
+#define	BUS_DMA_BUS4		0x080
+#define	BUS_DMA_STREAMING	0x100	/* hint: sequential, unidirectional */
+#define	BUS_DMA_READ		0x200	/* mapping is device -> memory only */
+#define	BUS_DMA_WRITE		0x400	/* mapping is memory -> device only */
+
+/* Forwards needed by prototypes below. */
+struct mbuf;
+struct proc;
+struct uio;
+
+/*
+ * Operations performed by bus_dmamap_sync().
+ */
+#define BUS_DMASYNC_PREREAD	0x01
+#define BUS_DMASYNC_POSTREAD	0x02
+#define BUS_DMASYNC_PREWRITE	0x04
+#define BUS_DMASYNC_POSTWRITE	0x08
+
+typedef struct x86_bus_dma_tag		*bus_dma_tag_t;
+typedef struct x86_bus_dmamap		*bus_dmamap_t;
+
+/*
+ *	bus_dma_segment_t
+ *
+ *	Describes a single contiguous DMA transaction.  Values
+ *	are suitable for programming into DMA registers.
+ */
+struct x86_bus_dma_segment {
+	bus_addr_t	ds_addr;	/* DMA address */
+	bus_size_t	ds_len;		/* length of transfer */
+};
+typedef struct x86_bus_dma_segment	bus_dma_segment_t;
+
+/*
+ *	bus_dma_tag_t
+ *
+ *	A machine-dependent opaque type describing the implementation of
+ *	DMA for a given bus.
+ */
+
+struct x86_bus_dma_tag {
+	void	*_cookie;		/* cookie used in the guts */
+
+	/*
+	 * DMA mapping methods.
+	 */
+	int	(*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
+		    bus_size_t, bus_size_t, int, bus_dmamap_t *);
+	void	(*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
+	int	(*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
+		    bus_size_t, struct proc *, int);
+	int	(*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
+		    struct mbuf *, int);
+	int	(*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
+		    struct uio *, int);
+	int	(*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
+		    bus_dma_segment_t *, int, bus_size_t, int);
+	void	(*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
+	void	(*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
+		    bus_addr_t, bus_size_t, int);
+
+	/*
+	 * DMA memory utility functions.
+	 */
+	int	(*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
+		    bus_size_t, bus_dma_segment_t *, int, int *, int);
+	void	(*_dmamem_free)(bus_dma_tag_t,
+		    bus_dma_segment_t *, int);
+	int	(*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
+		    int, size_t, caddr_t *, int);
+	void	(*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
+	paddr_t	(*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
+		    int, off_t, int, int);
+};
+
+#define	bus_dmamap_create(t, s, n, m, b, f, p)			\
+	(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
+#define	bus_dmamap_destroy(t, p)				\
+	(*(t)->_dmamap_destroy)((t), (p))
+#define	bus_dmamap_load(t, m, b, s, p, f)			\
+	(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
+#define	bus_dmamap_load_mbuf(t, m, b, f)			\
+	(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
+#define	bus_dmamap_load_uio(t, m, u, f)				\
+	(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
+#define	bus_dmamap_load_raw(t, m, sg, n, s, f)			\
+	(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
+#define	bus_dmamap_unload(t, p)					\
+	(*(t)->_dmamap_unload)((t), (p))
+#define	bus_dmamap_sync(t, p, o, l, ops)			\
+	(void)((t)->_dmamap_sync ?				\
+	    (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0)
+
+#define	bus_dmamem_alloc(t, s, a, b, sg, n, r, f)		\
+	(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
+#define	bus_dmamem_free(t, sg, n)				\
+	(*(t)->_dmamem_free)((t), (sg), (n))
+#define	bus_dmamem_map(t, sg, n, s, k, f)			\
+	(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
+#define	bus_dmamem_unmap(t, k, s)				\
+	(*(t)->_dmamem_unmap)((t), (k), (s))
+#define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
+	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
+
+/*
+ *	bus_dmamap_t
+ *
+ *	Describes a DMA mapping.
+ */
+struct x86_bus_dmamap {
+	/*
+	 * PRIVATE MEMBERS: not for use my machine-independent code.
+	 */
+	bus_size_t	_dm_size;	/* largest DMA transfer mappable */
+	int		_dm_segcnt;	/* number of segs this map can map */
+	bus_size_t	_dm_maxsegsz;	/* largest possible segment */
+	bus_size_t	_dm_boundary;	/* don't cross this */
+	int		_dm_flags;	/* misc. flags */
+
+	void		*_dm_cookie;	/* cookie for bus-specific functions */
+
+	/*
+	 * PUBLIC MEMBERS: these are used by machine-independent code.
+	 */
+	bus_size_t	dm_mapsize;	/* size of the mapping */
+	int		dm_nsegs;	/* # valid segments in mapping */
+	bus_dma_segment_t dm_segs[1];	/* segments; variable length */
+};
+
+#ifdef _X86_BUS_DMA_PRIVATE
+int	_bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
+	    bus_size_t, int, bus_dmamap_t *);
+void	_bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
+int	_bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
+	    bus_size_t, struct proc *, int);
+int	_bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
+	    struct mbuf *, int);
+int	_bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
+	    struct uio *, int);
+int	_bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
+	    bus_dma_segment_t *, int, bus_size_t, int);
+void	_bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
+void	_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
+	    bus_size_t, int);
+
+int	_bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
+	    bus_size_t alignment, bus_size_t boundary,
+	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
+void	_bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
+	    int nsegs);
+int	_bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
+	    int nsegs, size_t size, caddr_t *kvap, int flags);
+void	_bus_dmamem_unmap(bus_dma_tag_t tag, caddr_t kva,
+	    size_t size);
+paddr_t	_bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
+	    int nsegs, off_t off, int prot, int flags);
+
+int	_bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
+	    bus_size_t alignment, bus_size_t boundary,
+	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
+	    paddr_t low, paddr_t high);
+
+/* 
+ *      int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
+ *          bus_addr_t rend, bus_size_t size, bus_size_t align,
+ *          bus_size_t boundary, int flags, bus_addr_t *addrp,
+ *          bus_space_handle_t *bshp);
+ *
+ * Allocate a region of bus space.      
+ */
+ 
+int	x86_memio_alloc(bus_space_tag_t t, bus_addr_t rstart,
+	    bus_addr_t rend, bus_size_t size, bus_size_t align,
+	    bus_size_t boundary, int flags, bus_addr_t *addrp,
+	    bus_space_handle_t *bshp);
+
+/*          
+ *      int bus_space_free(bus_space_tag_t t,
+ *          bus_space_handle_t bsh, bus_size_t size);
+ * 
+ * Free a region of bus space.
+ */
+ 
+void	x86_memio_free(bus_space_tag_t t, bus_space_handle_t bsh,  
+	    bus_size_t size);
+
+/*      
+ *      paddr_t bus_space_mmap(bus_space_tag_t t, bus_addr_t base,
+ *          off_t offset, int prot, int flags);
+ * 
+ * Mmap an area of bus space.
+ */
+ 
+paddr_t x86_memio_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
+            
+
+#endif /* _X86_BUS_DMA_PRIVATE */
+
+#endif /* _X86_BUS_H_ */
diff --git a/sys/arch/amd64/include/cacheinfo.h b/sys/arch/amd64/include/cacheinfo.h
new file mode 100644
index 00000000000..ea0d7837029
--- /dev/null
+++ b/sys/arch/amd64/include/cacheinfo.h
@@ -0,0 +1,111 @@
+/*	$OpenBSD: cacheinfo.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: cacheinfo.h,v 1.1 2003/04/25 21:54:30 fvdl Exp $	*/
+
+#ifndef _X86_CACHEINFO_H
+#define _X86_CACHEINFO_H
+
+struct x86_cache_info {
+	uint8_t		cai_index;
+	uint8_t		cai_desc;
+	uint8_t		cai_associativity;
+	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
+	u_int		cai_linesize;	/* or page size for TLB */
+	const char	*cai_string;
+};
+
+#define	CAI_ITLB	0		/* Instruction TLB (4K pages) */
+#define	CAI_ITLB2	1		/* Instruction TLB (2/4M pages) */
+#define	CAI_DTLB	2		/* Data TLB (4K pages) */
+#define	CAI_DTLB2	3		/* Data TLB (2/4M pages) */
+#define	CAI_ICACHE	4		/* Instruction cache */
+#define	CAI_DCACHE	5		/* Data cache */
+#define	CAI_L2CACHE	6		/* Level 2 cache */
+
+#define	CAI_COUNT	7
+
+struct cpu_info;
+
+const struct x86_cache_info *cache_info_lookup(const struct x86_cache_info *,
+					       u_int8_t);
+void amd_cpu_cacheinfo(struct cpu_info *);
+void x86_print_cacheinfo(struct cpu_info *);
+
+/*
+ * AMD Cache Info:
+ *
+ *	Athlon, Duron:
+ *
+ *		Function 8000.0005 L1 TLB/Cache Information
+ *		EAX -- L1 TLB 2/4MB pages
+ *		EBX -- L1 TLB 4K pages
+ *		ECX -- L1 D-cache
+ *		EDX -- L1 I-cache
+ *
+ *		Function 8000.0006 L2 TLB/Cache Information
+ *		EAX -- L2 TLB 2/4MB pages
+ *		EBX -- L2 TLB 4K pages
+ *		ECX -- L2 Unified cache
+ *		EDX -- reserved
+ *
+ *	K5, K6:
+ *
+ *		Function 8000.0005 L1 TLB/Cache Information
+ *		EAX -- reserved
+ *		EBX -- TLB 4K pages
+ *		ECX -- L1 D-cache
+ *		EDX -- L1 I-cache
+ *
+ *	K6-III:
+ *
+ *		Function 8000.0006 L2 Cache Information
+ *		EAX -- reserved
+ *		EBX -- reserved
+ *		ECX -- L2 Unified cache
+ *		EDX -- reserved
+ */
+
+/* L1 TLB 2/4MB pages */
+#define	AMD_L1_EAX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
+#define	AMD_L1_EAX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
+#define	AMD_L1_EAX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
+#define	AMD_L1_EAX_ITLB_ENTRIES(x)	( (x)        & 0xff)
+
+/* L1 TLB 4K pages */
+#define	AMD_L1_EBX_DTLB_ASSOC(x)	(((x) >> 24) & 0xff)
+#define	AMD_L1_EBX_DTLB_ENTRIES(x)	(((x) >> 16) & 0xff)
+#define	AMD_L1_EBX_ITLB_ASSOC(x)	(((x) >> 8)  & 0xff)
+#define	AMD_L1_EBX_ITLB_ENTRIES(x)	( (x)        & 0xff)
+
+/* L1 Data Cache */
+#define	AMD_L1_ECX_DC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
+#define	AMD_L1_ECX_DC_ASSOC(x)		 (((x) >> 16) & 0xff)
+#define	AMD_L1_ECX_DC_LPT(x)		 (((x) >> 8)  & 0xff)
+#define	AMD_L1_ECX_DC_LS(x)		 ( (x)        & 0xff)
+
+/* L1 Instruction Cache */
+#define	AMD_L1_EDX_IC_SIZE(x)		((((x) >> 24) & 0xff) * 1024)
+#define	AMD_L1_EDX_IC_ASSOC(x)		 (((x) >> 16) & 0xff)
+#define	AMD_L1_EDX_IC_LPT(x)		 (((x) >> 8)  & 0xff)
+#define	AMD_L1_EDX_IC_LS(x)		 ( (x)        & 0xff)
+
+/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
+
+/* L2 TLB 2/4MB pages */
+#define	AMD_L2_EAX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
+#define	AMD_L2_EAX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
+#define	AMD_L2_EAX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
+#define	AMD_L2_EAX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
+
+/* L2 TLB 4K pages */
+#define	AMD_L2_EBX_DTLB_ASSOC(x)	(((x) >> 28)  & 0xf)
+#define	AMD_L2_EBX_DTLB_ENTRIES(x)	(((x) >> 16)  & 0xfff)
+#define	AMD_L2_EBX_IUTLB_ASSOC(x)	(((x) >> 12)  & 0xf)
+#define	AMD_L2_EBX_IUTLB_ENTRIES(x)	( (x)         & 0xfff)
+
+/* L2 Cache */
+#define	AMD_L2_ECX_C_SIZE(x)		((((x) >> 16) & 0xffff) * 1024)
+#define	AMD_L2_ECX_C_ASSOC(x)		 (((x) >> 12) & 0xf)
+#define	AMD_L2_ECX_C_LPT(x)		 (((x) >> 8)  & 0xf)
+#define	AMD_L2_ECX_C_LS(x)		 ( (x)        & 0xff)
+
+#endif /* _X86_CACHEINFO_H */
diff --git a/sys/arch/amd64/include/cdefs.h b/sys/arch/amd64/include/cdefs.h
new file mode 100644
index 00000000000..26606d3e377
--- /dev/null
+++ b/sys/arch/amd64/include/cdefs.h
@@ -0,0 +1,23 @@
+/*	$OpenBSD: cdefs.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: cdefs.h,v 1.2 1995/03/23 20:10:26 jtc Exp $	*/
+
+/*
+ * Written by J.T. Conklin <jtc@wimsey.com> 01/17/95.
+ * Public domain.
+ */
+
+#ifndef	_MACHINE_CDEFS_H_
+#define	_MACHINE_CDEFS_H_
+
+#if defined(__GNUC__) && defined(__STDC__)
+#define __weak_alias(alias,sym)						\
+	__asm__(".weak " __STRING(alias) " ; " __STRING(alias) " = " __STRING(sym))
+#define __warn_references(sym,msg)					\
+	__asm__(".section .gnu.warning." __STRING(sym) " ; .ascii \"" msg "\" ; .text")
+#else
+#define __indr_reference(sym,alias)
+#define __warn_references(sym,msg)
+#define __weak_alias(alias,sym)
+#endif
+
+#endif /* !_MACHINE_CDEFS_H_ */
diff --git a/sys/arch/amd64/include/conf.h b/sys/arch/amd64/include/conf.h
new file mode 100644
index 00000000000..0eeee30a029
--- /dev/null
+++ b/sys/arch/amd64/include/conf.h
@@ -0,0 +1,45 @@
+/*	$OpenBSD: conf.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: conf.h,v 1.2 1996/05/05 19:28:34 christos Exp $	*/
+
+/*
+ * Copyright (c) 1996 Christos Zoulas.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Christos Zoulas.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/conf.h>
+
+#define	mmread	mmrw
+#define	mmwrite	mmrw
+cdev_decl(mm);
+
+bdev_decl(fd);
+cdev_decl(fd);
+
+cdev_decl(spkr);
+
+#define biosselect seltrue
+cdev_decl(bios);
diff --git a/sys/arch/amd64/include/cpu.h b/sys/arch/amd64/include/cpu.h
new file mode 100644
index 00000000000..44e4a446ccb
--- /dev/null
+++ b/sys/arch/amd64/include/cpu.h
@@ -0,0 +1,376 @@
+/*	$OpenBSD: cpu.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)cpu.h	5.4 (Berkeley) 5/9/91
+ */
+
+#ifndef _AMD64_CPU_H_
+#define _AMD64_CPU_H_
+
+/*
+ * Definitions unique to x86-64 cpu support.
+ */
+#include <machine/frame.h>
+#include <machine/segments.h>
+#include <machine/tss.h>
+#include <machine/intrdefs.h>
+#include <machine/cacheinfo.h>
+
+#include <sys/device.h>
+#include <sys/lock.h>
+
+struct cpu_info {
+	struct device *ci_dev;
+	struct cpu_info *ci_self;
+#if 0
+	struct schedstate_percpu ci_schedstate; /* scheduler state */
+#endif
+	struct cpu_info *ci_next;
+
+	struct proc *ci_curproc;
+	struct simplelock ci_slock;
+	u_int ci_cpuid;
+	u_int ci_apicid;
+	u_long ci_spin_locks;
+	u_long ci_simple_locks;
+
+	u_int64_t ci_scratch;
+
+	struct proc *ci_fpcurproc;
+	int ci_fpsaving;
+
+	volatile u_int32_t ci_tlb_ipi_mask;
+
+	struct pcb *ci_curpcb;
+	struct pcb *ci_idle_pcb;
+	int ci_idle_tss_sel;
+
+	struct intrsource *ci_isources[MAX_INTR_SOURCES];
+	u_int32_t	ci_ipending;
+	int		ci_ilevel;
+	int		ci_idepth;
+	u_int32_t	ci_imask[NIPL];
+	u_int32_t	ci_iunmask[NIPL];
+
+	paddr_t 	ci_idle_pcb_paddr;
+	u_int		ci_flags;
+	u_int32_t	ci_ipis;
+
+	u_int32_t	ci_feature_flags;
+	u_int32_t	ci_signature;
+	u_int64_t	ci_tsc_freq;
+
+	struct cpu_functions *ci_func;
+	void (*cpu_setup)(struct cpu_info *);
+	void (*ci_info)(struct cpu_info *);
+
+	int		ci_want_resched;
+	int		ci_astpending;
+	struct trapframe *ci_ddb_regs;
+
+	struct x86_cache_info ci_cinfo[CAI_COUNT];
+
+	struct timeval 	ci_cc_time;
+	int64_t		ci_cc_cc;
+	int64_t		ci_cc_ms_delta;
+	int64_t		ci_cc_denom;
+
+	char		*ci_gdt;
+
+	struct x86_64_tss	ci_doubleflt_tss;
+	struct x86_64_tss	ci_ddbipi_tss;
+
+	char *ci_doubleflt_stack;
+	char *ci_ddbipi_stack;
+
+	struct evcnt ci_ipi_events[X86_NIPI];
+};
+
+#define CPUF_BSP	0x0001		/* CPU is the original BSP */
+#define CPUF_AP		0x0002		/* CPU is an AP */ 
+#define CPUF_SP		0x0004		/* CPU is only processor */  
+#define CPUF_PRIMARY	0x0008		/* CPU is active primary processor */
+
+#define CPUF_PRESENT	0x1000		/* CPU is present */
+#define CPUF_RUNNING	0x2000		/* CPU is running */
+#define CPUF_PAUSE	0x4000		/* CPU is paused in DDB */
+#define CPUF_GO		0x8000		/* CPU should start running */
+
+#define PROC_PC(p)	((p)->p_md.md_regs->tf_rip)
+
+extern struct cpu_info cpu_info_primary;
+extern struct cpu_info *cpu_info_list;
+
+#define CPU_INFO_ITERATOR		int
+#define CPU_INFO_FOREACH(cii, ci)	cii = 0, ci = cpu_info_list; \
+					ci != NULL; ci = ci->ci_next
+
+#if defined(MULTIPROCESSOR)
+
+#define X86_MAXPROCS		32	/* bitmask; can be bumped to 64 */
+
+#define CPU_STARTUP(_ci)	((_ci)->ci_func->start(_ci))
+#define CPU_STOP(_ci)		((_ci)->ci_func->stop(_ci))
+#define CPU_START_CLEANUP(_ci)	((_ci)->ci_func->cleanup(_ci))
+
+#define curcpu()	({struct cpu_info *__ci;                  \
+			asm volatile("movq %%gs:8,%0" : "=r" (__ci)); \
+			__ci;})
+#define cpu_number()	(curcpu()->ci_cpuid)
+
+#define CPU_IS_PRIMARY(ci)	((ci)->ci_flags & CPUF_PRIMARY)
+
+extern struct cpu_info *cpu_info[X86_MAXPROCS];
+
+void cpu_boot_secondary_processors(void);
+void cpu_init_idle_pcbs(void);    
+
+
+/*      
+ * Preempt the current process if in interrupt from user mode,
+ * or after the current trap/syscall if in system mode.
+ */
+extern void need_resched(struct cpu_info *);
+
+#else /* !MULTIPROCESSOR */
+
+#define X86_MAXPROCS		1
+
+#ifdef _KERNEL
+extern struct cpu_info cpu_info_primary;
+
+#define curcpu()		(&cpu_info_primary)
+
+#endif
+
+/*
+ * definitions of cpu-dependent requirements
+ * referenced in generic code
+ */
+#define	cpu_number()		0
+#define CPU_IS_PRIMARY(ci)	1
+
+/*
+ * Preempt the current process if in interrupt from user mode,
+ * or after the current trap/syscall if in system mode.
+ */
+
+#ifdef MULTIPROCESSOR
+#define need_resched(ci)						\
+do {									\
+	struct cpu_info *__ci = (ci);					\
+	__ci->ci_want_resched = 1;					\
+	if (__ci->ci_curproc != NULL)					\
+		aston(__ci->ci_curproc);				\
+} while (/*CONSTCOND*/0)
+#else
+#define need_resched()							\
+do {									\
+	struct cpu_info *__ci = curcpu();				\
+	__ci->ci_want_resched = 1;					\
+	if (__ci->ci_curproc != NULL)					\
+		aston(__ci->ci_curproc);				\
+} while (/*CONSTCOND*/0)
+#endif
+
+#endif
+
+#define aston(p)	((p)->p_md.md_astpending = 1)
+
+extern u_int32_t cpus_attached;
+
+#define curpcb		curcpu()->ci_curpcb
+#define curproc		curcpu()->ci_curproc
+
+/*
+ * Arguments to hardclock, softclock and statclock
+ * encapsulate the previous machine state in an opaque
+ * clockframe; for now, use generic intrframe.
+ */
+#define clockframe intrframe
+
+#define	CLKF_USERMODE(frame)	USERMODE((frame)->if_cs, (frame)->if_rflags)
+#define CLKF_BASEPRI(frame)	(0)
+#define CLKF_PC(frame)		((frame)->if_rip)
+#define CLKF_INTR(frame)	(curcpu()->ci_idepth > 1)
+
+/*
+ * Give a profiling tick to the current process when the user profiling
+ * buffer pages are invalid.  On the i386, request an ast to send us
+ * through trap(), marking the proc as needing a profiling tick.
+ */
+#define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, aston(p))
+
+/*
+ * Notify the current process (p) that it has a signal pending,
+ * process as soon as possible.
+ */
+#define	signotify(p)		aston(p)
+
+/*
+ * We need a machine-independent name for this.
+ */
+extern void (*delay_func)(int);
+struct timeval;
+extern void (*microtime_func)(struct timeval *);
+
+#define DELAY(x)		(*delay_func)(x)
+#define delay(x)		(*delay_func)(x)
+#define microtime(tv)		(*microtime_func)(tv)
+
+
+/*
+ * pull in #defines for kinds of processors
+ */
+
+#ifdef _KERNEL
+extern int biosbasemem;
+extern int biosextmem;
+extern int cpu;
+extern int cpu_feature;
+extern int cpu_id;
+extern char cpu_vendor[];
+extern int cpuid_level;
+
+/* kern_microtime.c */
+
+extern struct timeval cc_microset_time;
+void	cc_microtime(struct timeval *);
+void	cc_microset(struct cpu_info *);
+
+/* identcpu.c */
+
+void	identifycpu(struct cpu_info *);
+void cpu_probe_features(struct cpu_info *);
+
+/* machdep.c */
+void	delay(int);
+void	dumpconf(void);
+int	cpu_maxproc(void);
+void	cpu_reset(void);
+void	x86_64_proc0_tss_ldt_init(void);
+void	x86_64_bufinit(void);
+void	x86_64_init_pcb_tss_ldt(struct cpu_info *);
+void	cpu_proc_fork(struct proc *, struct proc *);
+
+struct region_descriptor;
+void	lgdt(struct region_descriptor *);
+void	fillw(short, void *, size_t);
+
+struct pcb;
+void	savectx(struct pcb *);
+void	switch_exit(struct proc *, void (*)(struct proc *));
+void	proc_trampoline(void);
+void	child_trampoline(void);
+
+/* clock.c */
+void	initrtclock(void);
+void	startrtclock(void);
+void	i8254_delay(int);
+void	i8254_microtime(struct timeval *);
+void	i8254_initclocks(void);
+
+void cpu_init_msrs(struct cpu_info *);
+
+
+/* trap.c */
+void	child_return(void *);
+
+/* consinit.c */
+void kgdb_port_init(void);
+
+/* bus_machdep.c */
+void x86_bus_space_init(void);
+void x86_bus_space_mallocok(void);
+
+#endif /* _KERNEL */
+
+#include <machine/psl.h>
+
+/* 
+ * CTL_MACHDEP definitions.
+ */
+#define	CPU_CONSDEV		1	/* dev_t: console terminal device */
+#define	CPU_BIOSBASEMEM		2	/* int: bios-reported base mem (K) */
+#define	CPU_BIOSEXTMEM		3	/* int: bios-reported ext. mem (K) */
+#define	CPU_NKPDE		4	/* int: number of kernel PDEs */
+#define	CPU_BOOTED_KERNEL	5	/* string: booted kernel name */
+#define CPU_DISKINFO		6	/* disk geometry information */
+#define CPU_FPU_PRESENT		7	/* FPU is present */
+#define	CPU_MAXID		8	/* number of valid machdep ids */
+
+#define	CTL_MACHDEP_NAMES { \
+	{ 0, 0 }, \
+	{ "console_device", CTLTYPE_STRUCT }, \
+	{ "biosbasemem", CTLTYPE_INT }, \
+	{ "biosextmem", CTLTYPE_INT }, \
+	{ "nkpde", CTLTYPE_INT }, \
+	{ "booted_kernel", CTLTYPE_STRING }, \
+	{ "diskinfo", CTLTYPE_STRUCT }, \
+	{ "fpu_present", CTLTYPE_INT }, \
+}
+
+
+/*
+ * Structure for CPU_DISKINFO sysctl call.
+ * XXX this should be somewhere else.
+ */
+#define MAX_BIOSDISKS	16
+
+struct disklist {
+	int dl_nbiosdisks;			   /* number of bios disks */
+	struct biosdisk_info {
+		int bi_dev;			   /* BIOS device # (0x80 ..) */
+		int bi_cyl;			   /* cylinders on disk */
+		int bi_head;			   /* heads per track */
+		int bi_sec;			   /* sectors per track */
+		u_int64_t bi_lbasecs;		   /* total sec. (iff ext13) */
+#define BIFLAG_INVALID		0x01
+#define BIFLAG_EXTINT13		0x02
+		int bi_flags;
+	} dl_biosdisks[MAX_BIOSDISKS];
+
+	int dl_nnativedisks;			   /* number of native disks */
+	struct nativedisk_info {
+		char ni_devname[16];		   /* native device name */
+		int ni_nmatches; 		   /* # of matches w/ BIOS */
+		int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */
+	} dl_nativedisks[1];			   /* actually longer */
+};
+
+#endif /* !_AMD64_CPU_H_ */
diff --git a/sys/arch/amd64/include/cpufunc.h b/sys/arch/amd64/include/cpufunc.h
new file mode 100644
index 00000000000..085a658a23e
--- /dev/null
+++ b/sys/arch/amd64/include/cpufunc.h
@@ -0,0 +1,280 @@
+/*	$OpenBSD: cpufunc.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.3 2003/05/08 10:27:43 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AMD64_CPUFUNC_H_
+#define	_AMD64_CPUFUNC_H_
+
+/*
+ * Functions to provide access to i386-specific instructions.
+ */
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+
+#include <machine/specialreg.h>
+
+static __inline void
+x86_pause(void)
+{
+	/* nothing */
+}
+
+#ifdef _KERNEL
+
+extern int cpu_feature;
+
+static __inline void 
+invlpg(u_int64_t addr)
+{ 
+        __asm __volatile("invlpg (%0)" : : "r" (addr) : "memory");
+}  
+
+static __inline void
+lidt(void *p)
+{
+	__asm __volatile("lidt (%0)" : : "r" (p));
+}
+
+static __inline void
+lldt(u_short sel)
+{
+	__asm __volatile("lldt %0" : : "r" (sel));
+}
+
+static __inline void
+ltr(u_short sel)
+{
+	__asm __volatile("ltr %0" : : "r" (sel));
+}
+
+static __inline void
+lcr8(u_int val)
+{
+	u_int64_t val64 = val;
+	__asm __volatile("movq %0,%%cr8" : : "r" (val64));
+}
+
+/*
+ * Upper 32 bits are reserved anyway, so just keep this 32bits.
+ */
+static __inline void
+lcr0(u_int val)
+{
+	u_int64_t val64 = val;
+	__asm __volatile("movq %0,%%cr0" : : "r" (val64));
+}
+
+static __inline u_int
+rcr0(void)
+{
+	u_int64_t val64;
+	u_int val;
+	__asm __volatile("movq %%cr0,%0" : "=r" (val64));
+	val = val64;
+	return val;
+}
+
+static __inline u_int64_t
+rcr2(void)
+{
+	u_int64_t val;
+	__asm __volatile("movq %%cr2,%0" : "=r" (val));
+	return val;
+}
+
+static __inline void
+lcr3(u_int64_t val)
+{
+	__asm __volatile("movq %0,%%cr3" : : "r" (val));
+}
+
+static __inline u_int64_t
+rcr3(void)
+{
+	u_int64_t val;
+	__asm __volatile("movq %%cr3,%0" : "=r" (val));
+	return val;
+}
+
+/*
+ * Same as for cr0. Don't touch upper 32 bits.
+ */
+static __inline void
+lcr4(u_int val)
+{
+	u_int64_t val64 = val;
+
+	__asm __volatile("movq %0,%%cr4" : : "r" (val64));
+}
+
+static __inline u_int
+rcr4(void)
+{
+	u_int val;
+	u_int64_t val64;
+	__asm __volatile("movq %%cr4,%0" : "=r" (val64));
+	val = val64;
+	return val;
+}
+
+static __inline void
+tlbflush(void)
+{
+	u_int64_t val;
+	__asm __volatile("movq %%cr3,%0" : "=r" (val));
+	__asm __volatile("movq %0,%%cr3" : : "r" (val));
+}
+
+static __inline void
+tlbflushg(void)
+{
+	/*
+	 * Big hammer: flush all TLB entries, including ones from PTE's
+	 * with the G bit set.  This should only be necessary if TLB
+	 * shootdown falls far behind.
+	 *
+	 * Intel Architecture Software Developer's Manual, Volume 3,
+	 *	System Programming, section 9.10, "Invalidating the
+	 * Translation Lookaside Buffers (TLBS)":
+	 * "The following operations invalidate all TLB entries, irrespective
+	 * of the setting of the G flag:
+	 * ...
+	 * "(P6 family processors only): Writing to control register CR4 to
+	 * modify the PSE, PGE, or PAE flag."
+	 *
+	 * (the alternatives not quoted above are not an option here.)
+	 *
+	 * If PGE is not in use, we reload CR3 for the benefit of
+	 * pre-P6-family processors.
+	 */
+
+	if (cpu_feature & CPUID_PGE) {
+		u_int cr4 = rcr4();
+		lcr4(cr4 & ~CR4_PGE);
+		lcr4(cr4);
+	} else
+		tlbflush();
+}
+
+#ifdef notyet
+void	setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl);
+#endif
+
+
+/* XXXX ought to be in psl.h with spl() functions */
+
+static __inline void
+disable_intr(void)
+{
+	__asm __volatile("cli");
+}
+
+static __inline void
+enable_intr(void)
+{
+	__asm __volatile("sti");
+}
+
+static __inline u_long
+read_rflags(void)
+{
+	u_long	ef;
+
+	__asm __volatile("pushfq; popq %0" : "=r" (ef));
+	return (ef);
+}
+
+static __inline void
+write_rflags(u_long ef)
+{
+	__asm __volatile("pushq %0; popfq" : : "r" (ef));
+}
+
+static __inline u_int64_t
+rdmsr(u_int msr)
+{
+	uint32_t hi, lo;
+	__asm __volatile("rdmsr" : "=d" (hi), "=a" (lo) : "c" (msr));
+	return (((uint64_t)hi << 32) | (uint64_t) lo);
+}
+
+static __inline void
+wrmsr(u_int msr, u_int64_t newval)
+{
+	__asm __volatile("wrmsr" :
+	    : "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr));
+}
+
+static __inline void
+wbinvd(void)
+{
+	__asm __volatile("wbinvd");
+}
+
+static __inline u_int64_t
+rdtsc(void)
+{
+	uint32_t hi, lo;
+
+	__asm __volatile("rdtsc" : "=d" (hi), "=a" (lo));
+	return (((uint64_t)hi << 32) | (uint64_t) lo);
+}
+
+static __inline u_int64_t
+rdpmc(u_int pmc)
+{
+	uint32_t hi, lo;
+
+	__asm __volatile("rdpmc" : "=d" (hi), "=a" (lo) : "c" (pmc));
+	return (((uint64_t)hi << 32) | (uint64_t) lo);
+}
+
+/* Break into DDB/KGDB. */
+static __inline void
+breakpoint(void)
+{
+	__asm __volatile("int $3");
+}
+
+#define read_psl()	read_rflags()
+#define write_psl(x)	write_rflags(x)
+
+#endif /* _KERNEL */
+
+#endif /* !_AMD64_CPUFUNC_H_ */
diff --git a/sys/arch/amd64/include/cpuvar.h b/sys/arch/amd64/include/cpuvar.h
new file mode 100644
index 00000000000..b821592e1b8
--- /dev/null
+++ b/sys/arch/amd64/include/cpuvar.h
@@ -0,0 +1,109 @@
+/*	$OpenBSD: cpuvar.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* 	$NetBSD: cpuvar.h,v 1.1 2003/03/01 18:29:28 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999 Stefan Grefen
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+struct cpu_functions {
+	int (*start)(struct cpu_info *);
+	int (*stop)(struct cpu_info *);
+	void (*cleanup)(struct cpu_info *);
+};
+
+extern struct cpu_functions mp_cpu_funcs;
+
+#define CPU_ROLE_SP	0
+#define CPU_ROLE_BP	1
+#define CPU_ROLE_AP	2
+
+struct cpu_attach_args {
+	const char *caa_name;
+	int cpu_number;
+	int cpu_role;
+	struct cpu_functions *cpu_func;
+};
+
+#define MP_PICMODE	0x00000001      /* System booted in picmode */
+
+#ifdef _KERNEL
+
+#ifdef MULTIPROCESSOR
+extern u_int32_t cpus_running;
+#endif
+
+int x86_ipi(int,int,int);
+void x86_self_ipi(int);
+int x86_ipi_init(int);
+
+void identifycpu(struct cpu_info *);
+void cpu_init(struct cpu_info *);
+void cpu_init_first(void);
+
+#endif
diff --git a/sys/arch/amd64/include/db_machdep.h b/sys/arch/amd64/include/db_machdep.h
new file mode 100644
index 00000000000..c2569ee9379
--- /dev/null
+++ b/sys/arch/amd64/include/db_machdep.h
@@ -0,0 +1,141 @@
+/*	$OpenBSD: db_machdep.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: db_machdep.h,v 1.2 2003/04/29 17:06:04 scw Exp $	*/
+
+/* 
+ * Mach Operating System
+ * Copyright (c) 1991,1990 Carnegie Mellon University
+ * All Rights Reserved.
+ * 
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ * 
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ * 
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */
+
+#ifndef	_I386_DB_MACHDEP_H_
+#define	_I386_DB_MACHDEP_H_
+
+/*
+ * Machine-dependent defines for new kernel debugger.
+ */
+
+#include <sys/param.h>
+#include <uvm/uvm_extern.h>
+#include <machine/trap.h>
+
+typedef	vaddr_t		db_addr_t;	/* address - unsigned */
+typedef	long		db_expr_t;	/* expression - signed */
+
+typedef struct trapframe db_regs_t;
+#ifndef MULTIPROCESSOR
+extern db_regs_t ddb_regs;	/* register state */
+#define	DDB_REGS	(&ddb_regs)
+#else
+extern db_regs_t *ddb_regp;
+#define DDB_REGS	(ddb_regp)
+#define ddb_regs	(*ddb_regp)
+#endif
+
+#if defined(lint)
+#define	PC_REGS(regs)	((regs)->tf_rip)
+#else
+#define	PC_REGS(regs)	((db_addr_t)(regs)->tf_rip)
+#endif
+
+#define	BKPT_ADDR(addr)	(addr)		/* breakpoint address */
+#define	BKPT_INST	0xcc		/* breakpoint instruction */
+#define	BKPT_SIZE	(1)		/* size of breakpoint inst */
+#define	BKPT_SET(inst)	(BKPT_INST)
+
+#define	FIXUP_PC_AFTER_BREAK(regs)	((regs)->tf_rip -= BKPT_SIZE)
+
+#define	db_clear_single_step(regs)	((regs)->tf_rflags &= ~PSL_T)
+#define	db_set_single_step(regs)	((regs)->tf_rflags |=  PSL_T)
+
+#define	IS_BREAKPOINT_TRAP(type, code)	((type) == T_BPTFLT)
+#define IS_WATCHPOINT_TRAP(type, code)	((type) == T_TRCTRAP && (code) & 15)
+
+#define	I_CALL		0xe8
+#define	I_CALLI		0xff
+#define	I_RET		0xc3
+#define	I_IRET		0xcf
+
+#define	inst_trap_return(ins)	(((ins)&0xff) == I_IRET)
+#define	inst_return(ins)	(((ins)&0xff) == I_RET)
+#define	inst_call(ins)		(((ins)&0xff) == I_CALL || \
+				 (((ins)&0xff) == I_CALLI && \
+				  ((ins)&0x3800) == 0x1000))
+#define inst_load(ins)		0
+#define inst_store(ins)		0
+
+/* access capability and access macros */
+
+#define DB_ACCESS_LEVEL		2	/* access any space */
+#define DB_CHECK_ACCESS(addr,size,task)				\
+	db_check_access(addr,size,task)
+#define DB_PHYS_EQ(task1,addr1,task2,addr2)			\
+	db_phys_eq(task1,addr1,task2,addr2)
+#define DB_VALID_KERN_ADDR(addr)				\
+	((addr) >= VM_MIN_KERNEL_ADDRESS && 			\
+	 (addr) < VM_MAX_KERNEL_ADDRESS)
+#define DB_VALID_ADDRESS(addr,user)				\
+	((!(user) && DB_VALID_KERN_ADDR(addr)) ||		\
+	 ((user) && (addr) < VM_MAX_ADDRESS))
+
+#if 0
+boolean_t 	db_check_access(vaddr_t, int, task_t);
+boolean_t	db_phys_eq(task_t, vaddr_t, task_t, vaddr_t);
+#endif
+
+/* macros for printing OS server dependent task name */
+
+#define DB_TASK_NAME(task)	db_task_name(task)
+#define DB_TASK_NAME_TITLE	"COMMAND                "
+#define DB_TASK_NAME_LEN	23
+#define DB_NULL_TASK_NAME	"?                      "
+
+/*
+ * Constants for KGDB.
+ */
+typedef	long		kgdb_reg_t;
+#define	KGDB_NUMREGS	16
+#define	KGDB_BUFLEN	512
+
+#if 0
+void		db_task_name(/* task_t */);
+#endif
+
+/* macro for checking if a thread has used floating-point */
+
+#define db_thread_fp_used(thread)	((thread)->pcb->ims.ifps != 0)
+
+int kdb_trap(int, int, db_regs_t *);
+
+/*
+ * We define some of our own commands
+ */
+#define DB_MACHINE_COMMANDS
+
+#define	DB_ELF_SYMBOLS
+#define	DB_ELFSIZE	64
+
+extern void db_machine_init(void);
+
+extern void cpu_debug_dump(void);
+
+#endif	/* _I386_DB_MACHDEP_H_ */
diff --git a/sys/arch/amd64/include/disklabel.h b/sys/arch/amd64/include/disklabel.h
new file mode 100644
index 00000000000..8b2ef5f335c
--- /dev/null
+++ b/sys/arch/amd64/include/disklabel.h
@@ -0,0 +1,118 @@
+/*	$OpenBSD: disklabel.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: disklabel.h,v 1.3 1996/03/09 20:52:54 ghudson Exp $	*/
+
+/*
+ * Copyright (c) 1994 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christopher G. Demetriou.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_DISKLABEL_H_
+#define _MACHINE_DISKLABEL_H_
+
+#define	LABELSECTOR	1		/* sector containing label */
+#define	LABELOFFSET	0		/* offset of label in sector */
+#define	MAXPARTITIONS	16		/* number of partitions */
+#define	RAW_PART	2		/* raw partition: ie. rsd0c */
+
+/* DOS partition table -- located in boot block */
+#define	DOSBBSECTOR	0		/* DOS boot block relative sector # */
+#define	DOSPARTOFF	446
+#define	DOSDISKOFF	444
+#define	NDOSPART	4
+#define	DOSACTIVE	0x80		/* active partition */
+
+struct dos_partition {
+	u_int8_t	dp_flag;	/* bootstrap flags */
+	u_int8_t	dp_shd;		/* starting head */
+	u_int8_t	dp_ssect;	/* starting sector */
+	u_int8_t	dp_scyl;	/* starting cylinder */
+	u_int8_t	dp_typ;		/* partition type (see below) */
+	u_int8_t	dp_ehd;		/* end head */
+	u_int8_t	dp_esect;	/* end sector */
+	u_int8_t	dp_ecyl;	/* end cylinder */
+	u_int32_t	dp_start;	/* absolute starting sector number */
+	u_int32_t	dp_size;	/* partition size in sectors */
+};
+
+/* Known DOS partition types. */
+#define	DOSPTYP_UNUSED	0x00		/* Unused partition */
+#define DOSPTYP_FAT12	0x01		/* 12-bit FAT */
+#define DOSPTYP_FAT16S	0x04		/* 16-bit FAT, less than 32M */
+#define DOSPTYP_EXTEND	0x05		/* Extended; contains sub-partitions */
+#define DOSPTYP_FAT16B	0x06		/* 16-bit FAT, more than 32M */
+#define DOSPTYP_FAT32	0x0b		/* 32-bit FAT */
+#define DOSPTYP_FAT32L	0x0c		/* 32-bit FAT, LBA-mapped */
+#define DOSPTYP_FAT16L	0x0e		/* 16-bit FAT, LBA-mapped */
+#define DOSPTYP_EXTENDL 0x0f		/* Extended, LBA-mapped; contains sub-partitions */
+#define DOSPTYP_ONTRACK	0x54
+#define	DOSPTYP_LINUX	0x83		/* That other thing */
+#define DOSPTYP_FREEBSD	0xa5		/* FreeBSD partition type */
+#define DOSPTYP_OPENBSD	0xa6		/* OpenBSD partition type */
+#define DOSPTYP_NETBSD	0xa9		/* NetBSD partition type */
+
+struct dos_mbr {
+	u_int8_t		dmbr_boot[DOSPARTOFF];
+	struct dos_partition	dmbr_parts[NDOSPART];
+	u_int16_t		dmbr_sign;
+} __attribute__((__packed__));
+
+#define DOSMBR_SIGNATURE	(0xaa55)
+#define DOSMBR_SIGNATURE_OFF	(0x1fe)
+
+#include <sys/dkbad.h>
+struct cpu_disklabel {
+	struct dos_partition dosparts[NDOSPART];
+	struct dkbad bad;
+};
+
+#define DKBAD(x) ((x)->bad)
+
+/* Isolate the relevant bits to get sector and cylinder. */
+#define	DPSECT(s)	((s) & 0x3f)
+#define	DPCYL(c, s)	((c) + (((s) & 0xc0) << 2))
+
+static __inline u_int32_t get_le(void *);
+
+static __inline u_int32_t
+#ifdef __cplusplus
+get_le(void *p)
+#else
+get_le(p)
+	void *p;
+#endif
+{
+	u_int8_t *_p = (u_int8_t *)p;
+	u_int32_t x;
+	x = _p[0];
+	x |= _p[1] << 8;
+	x |= _p[2] << 16;
+	x |= _p[3] << 24;
+	return x;
+}
+
+#endif /* _MACHINE_DISKLABEL_H_ */
diff --git a/sys/arch/amd64/include/endian.h b/sys/arch/amd64/include/endian.h
new file mode 100644
index 00000000000..a8ee99504de
--- /dev/null
+++ b/sys/arch/amd64/include/endian.h
@@ -0,0 +1,67 @@
+/*	$OpenBSD: endian.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*-
+ * Copyright (c) 1997 Niklas Hallqvist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Niklas Hallqvist.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_ENDIAN_H_
+#define _I386_ENDIAN_H_
+
+#ifdef __GNUC__
+
+#define	__swap32md(x) ({						\
+	u_int32_t __swap32md_x = (x);					\
+									\
+	__asm ("bswap %1" : "+r" (__swap32md_x));			\
+	__swap32md_x;							\
+})
+
+/* XXX - I'm sure there is a better way on this cpu. */
+#define	__swap64md(x) ({						\
+	u_int64_t __swap64md_x = (x);					\
+									\
+	(u_int64_t)__swap32md(__swap64md_x >> 32) |			\
+	    (u_int64_t)__swap32md(__swap64md_x & 0xffffffff) << 32;	\
+})
+
+#define	__swap16md(x) ({						\
+	u_int16_t __swap16md_x = (x);					\
+									\
+	__asm ("rorw $8, %w1" : "+r" (__swap16md_x));			\
+	__swap16md_x;							\
+})
+
+/* Tell sys/endian.h we have MD variants of the swap macros.  */
+#define MD_SWAP
+
+#endif	/* __GNUC__ */
+
+#define BYTE_ORDER LITTLE_ENDIAN
+#include <sys/endian.h>
+
+#endif /* _I386_ENDIAN_H_ */
diff --git a/sys/arch/amd64/include/exec.h b/sys/arch/amd64/include/exec.h
new file mode 100644
index 00000000000..45290aafa7d
--- /dev/null
+++ b/sys/arch/amd64/include/exec.h
@@ -0,0 +1,22 @@
+/*	$OpenBSD: exec.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*
+ * Written by Artur Grabowski <art@openbsd.org> Public Domain
+ */
+
+#ifndef _AMD64_EXEC_H_
+#define _AMD64_EXEC_H_
+
+#define __LDPGSZ 4096
+
+#define NATIVE_EXEC_ELF
+
+#define ARCH_ELFSIZE 64
+
+#define ELF_TARG_CLASS		ELFCLASS64
+#define ELF_TARG_DATA		ELFDATA2LSB
+#define ELF_TARG_MACH		EM_X86_64
+
+#define _NLIST_DO_ELF
+#define _KERN_DO_ELF64
+
+#endif
diff --git a/sys/arch/amd64/include/float.h b/sys/arch/amd64/include/float.h
new file mode 100644
index 00000000000..7c315a0e10d
--- /dev/null
+++ b/sys/arch/amd64/include/float.h
@@ -0,0 +1,77 @@
+/*	$OpenBSD: float.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: float.h,v 1.8 1995/06/20 20:45:37 jtc Exp $	*/
+
+/*
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)float.h	7.1 (Berkeley) 5/8/90
+ */
+
+#ifndef _I386_FLOAT_H_
+#define _I386_FLOAT_H_
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+int __flt_rounds(void);
+__END_DECLS
+
+#define FLT_RADIX	2		/* b */
+#define FLT_ROUNDS	__flt_rounds()
+
+#define FLT_MANT_DIG	24		/* p */
+#define FLT_EPSILON	1.19209290E-07F	/* b**(1-p) */
+#define FLT_DIG		6		/* floor((p-1)*log10(b))+(b == 10) */
+#define FLT_MIN_EXP	(-125)		/* emin */
+#define FLT_MIN		1.17549435E-38F	/* b**(emin-1) */
+#define FLT_MIN_10_EXP	(-37)		/* ceil(log10(b**(emin-1))) */
+#define FLT_MAX_EXP	128		/* emax */
+#define FLT_MAX		3.40282347E+38F	/* (1-b**(-p))*b**emax */
+#define FLT_MAX_10_EXP	38		/* floor(log10((1-b**(-p))*b**emax)) */
+
+#define DBL_MANT_DIG	53
+#define DBL_EPSILON	2.2204460492503131E-16
+#define DBL_DIG		15
+#define DBL_MIN_EXP	(-1021)
+#define DBL_MIN		2.2250738585072014E-308
+#define DBL_MIN_10_EXP	(-307)
+#define DBL_MAX_EXP	1024
+#define DBL_MAX		1.7976931348623157E+308
+#define DBL_MAX_10_EXP	308
+
+#define LDBL_MANT_DIG	DBL_MANT_DIG
+#define LDBL_EPSILON	DBL_EPSILON
+#define LDBL_DIG	DBL_DIG
+#define LDBL_MIN_EXP	DBL_MIN_EXP
+#define LDBL_MIN	DBL_MIN
+#define LDBL_MIN_10_EXP	DBL_MIN_10_EXP
+#define LDBL_MAX_EXP	DBL_MAX_EXP
+#define LDBL_MAX	DBL_MAX
+#define LDBL_MAX_10_EXP	DBL_MAX_10_EXP
+
+#endif	/* _I386_FLOAT_H_ */
diff --git a/sys/arch/amd64/include/fpu.h b/sys/arch/amd64/include/fpu.h
new file mode 100644
index 00000000000..a7952df5d54
--- /dev/null
+++ b/sys/arch/amd64/include/fpu.h
@@ -0,0 +1,84 @@
+/*	$OpenBSD: fpu.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: fpu.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $	*/
+
+#ifndef	_AMD64_FPU_H_
+#define	_AMD64_FPU_H_
+
+#include <sys/types.h>
+
+/*
+ * NetBSD/amd64 only uses the extended save/restore format used
+ * by fxsave/fsrestore, to always deal with the SSE registers,
+ * which are part of the ABI to pass floating point values.
+ * Must be stored in memory on a 16-byte boundary.
+ */
+
+struct fxsave64 {
+	u_int16_t  fx_fcw;
+	u_int16_t  fx_fsw;
+	u_int8_t   fx_ftw;
+	u_int8_t   fx_unused1;
+	u_int16_t  fx_fop;
+	u_int64_t  fx_rip;
+	u_int64_t  fx_rdp;
+	u_int32_t  fx_mxcsr;
+	u_int32_t  fx_mxcsr_mask;
+	u_int64_t  fx_st[8][2];   /* 8 normal FP regs */
+	u_int64_t  fx_xmm[16][2]; /* 16 SSE2 registers */
+	u_int8_t   fx_unused3[96];
+} __attribute__((packed));
+
+struct savefpu {
+	struct fxsave64 fp_fxsave;	/* see above */
+	u_int16_t fp_ex_sw;		/* saved status from last exception */
+	u_int16_t fp_ex_tw;		/* saved tag from last exception */
+};
+
+/*
+ * The i387 defaults to Intel extended precision mode and round to nearest,
+ * with all exceptions masked.
+ */
+#define	__INITIAL_NPXCW__	0x037f
+#define __INITIAL_MXCSR__ 	0x1f80
+#define __INITIAL_MXCSR_MASK__	0xffbf
+
+/* NetBSD uses IEEE double precision. */
+#define	__NetBSD_NPXCW__	0x127f
+/* Linux just uses the default control word. */
+#define	__Linux_NPXCW__		0x037f
+
+/*
+ * The standard control word from finit is 0x37F, giving:
+ *	round to nearest
+ *	64-bit precision
+ *	all exceptions masked.
+ *
+ * Now we want:
+ *	affine mode (if we decide to support 287's)
+ *	round to nearest
+ *	53-bit precision
+ *	all exceptions masked.
+ *
+ * 64-bit precision often gives bad results with high level languages
+ * because it makes the results of calculations depend on whether
+ * intermediate values are stored in memory or in FPU registers.
+ */
+
+#ifdef _KERNEL
+/*
+ * XXX
+ */
+struct trapframe;
+struct cpu_info;
+
+void fpuinit(struct cpu_info *);
+void fpudrop(void);
+void fpusave(struct proc *);
+void fpudiscard(struct proc *);
+void fputrap(struct trapframe *);
+void fpusave_proc(struct proc *, int);
+void fpusave_cpu(struct cpu_info *, int);
+
+#endif
+
+#endif /* _AMD64_FPU_H_ */
diff --git a/sys/arch/amd64/include/frame.h b/sys/arch/amd64/include/frame.h
new file mode 100644
index 00000000000..d0fb538ceeb
--- /dev/null
+++ b/sys/arch/amd64/include/frame.h
@@ -0,0 +1,175 @@
+/*	$OpenBSD: frame.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: frame.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)frame.h	5.2 (Berkeley) 1/18/91
+ */
+
+/*
+ * Adapted for NetBSD/amd64 by fvdl@wasabisystems.com
+ */
+
+#ifndef _AMD64_FRAME_H_
+#define _AMD64_FRAME_H_
+
+#include <sys/signal.h>
+#include <machine/fpu.h>
+
+/*
+ * System stack frames.
+ */
+
+/*
+ * Exception/Trap Stack Frame
+ */
+struct trapframe {
+	int64_t	tf_rdi;
+	int64_t	tf_rsi;
+	int64_t	tf_rdx;
+	int64_t	tf_rcx;
+	int64_t tf_r8;
+	int64_t tf_r9;
+	int64_t tf_r10;
+	int64_t tf_r11;
+	int64_t tf_r12;
+	int64_t tf_r13;
+	int64_t tf_r14;
+	int64_t tf_r15;
+	int64_t	tf_rbp;
+	int64_t	tf_rbx;
+	int64_t	tf_rax;
+	int64_t	tf_gs;
+	int64_t	tf_fs;
+	int64_t	tf_es;
+	int64_t	tf_ds;
+	int64_t	tf_trapno;
+	/* below portion defined in hardware */
+	int64_t	tf_err;
+	int64_t	tf_rip;
+	int64_t	tf_cs;
+	int64_t	tf_rflags;
+	/* These are pushed unconditionally on the x86-64 */
+	int64_t	tf_rsp;
+	int64_t	tf_ss;
+};
+
+/*
+ * Interrupt stack frame
+ */
+struct intrframe {
+	int64_t	if_ppl;
+	int64_t	if_rdi;
+	int64_t	if_rsi;
+	int64_t	if_rdx;
+	int64_t	if_rcx;
+	int64_t if_r8;
+	int64_t if_r9;
+	int64_t if_r10;
+	int64_t if_r11;
+	int64_t if_r12;
+	int64_t if_r13;
+	int64_t if_r14;
+	int64_t if_r15;
+	int64_t	if_rbp;
+	int64_t	if_rbx;
+	int64_t	if_rax;
+	int64_t	tf_gs;
+	int64_t	tf_fs;
+	int64_t	tf_es;
+	int64_t	tf_ds;
+	u_int64_t __if_trapno; /* for compat with trap frame - trapno */
+	u_int64_t __if_err;	/* for compat with trap frame - err */
+	/* below portion defined in hardware */
+	int64_t	if_rip;
+	int64_t	if_cs;
+	int64_t	if_rflags;
+	/* These are pushed unconditionally on the x86-64 */
+	int64_t	if_rsp;
+	int64_t	if_ss;
+};
+
+/*
+ * Stack frame inside cpu_switch()
+ */
+struct switchframe {
+	int64_t	sf_ppl;
+	int64_t	sf_r15;
+	int64_t	sf_r14;
+	int64_t	sf_r13;
+	int64_t	sf_r12;
+	int64_t sf_rbp;
+	int64_t	sf_rbx;
+	int64_t	sf_rip;
+};
+
+#endif  /* _AMD64_FRAME_H_ */
diff --git a/sys/arch/amd64/include/frameasm.h b/sys/arch/amd64/include/frameasm.h
new file mode 100644
index 00000000000..c23b0e65a4d
--- /dev/null
+++ b/sys/arch/amd64/include/frameasm.h
@@ -0,0 +1,94 @@
+/*	$OpenBSD: frameasm.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: frameasm.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $	*/
+
+#ifndef _AMD64_MACHINE_FRAMEASM_H
+#define _AMD64_MACHINE_FRAMEASM_H
+
+/*
+ * Macros to define pushing/popping frames for interrupts, traps
+ * and system calls. Currently all the same; will diverge later.
+ */
+
+/*
+ * These are used on interrupt or trap entry or exit.
+ */
+#define INTR_SAVE_GPRS \
+	subq	$120,%rsp	; \
+	movq	%r15,TF_R15(%rsp)	; \
+	movq	%r14,TF_R14(%rsp)	; \
+	movq	%r13,TF_R13(%rsp)	; \
+	movq	%r12,TF_R12(%rsp)	; \
+	movq	%r11,TF_R11(%rsp)	; \
+	movq	%r10,TF_R10(%rsp)	; \
+	movq	%r9,TF_R9(%rsp)		; \
+	movq	%r8,TF_R8(%rsp)		; \
+	movq	%rdi,TF_RDI(%rsp)	; \
+	movq	%rsi,TF_RSI(%rsp)	; \
+	movq	%rbp,TF_RBP(%rsp)	; \
+	movq	%rbx,TF_RBX(%rsp)	; \
+	movq	%rdx,TF_RDX(%rsp)	; \
+	movq	%rcx,TF_RCX(%rsp)	; \
+	movq	%rax,TF_RAX(%rsp)
+
+#define	INTR_RESTORE_GPRS \
+	movq	TF_R15(%rsp),%r15	; \
+	movq	TF_R14(%rsp),%r14	; \
+	movq	TF_R13(%rsp),%r13	; \
+	movq	TF_R12(%rsp),%r12	; \
+	movq	TF_R11(%rsp),%r11	; \
+	movq	TF_R10(%rsp),%r10	; \
+	movq	TF_R9(%rsp),%r9		; \
+	movq	TF_R8(%rsp),%r8		; \
+	movq	TF_RDI(%rsp),%rdi	; \
+	movq	TF_RSI(%rsp),%rsi	; \
+	movq	TF_RBP(%rsp),%rbp	; \
+	movq	TF_RBX(%rsp),%rbx	; \
+	movq	TF_RDX(%rsp),%rdx	; \
+	movq	TF_RCX(%rsp),%rcx	; \
+	movq	TF_RAX(%rsp),%rax	; \
+	addq	$120,%rsp
+
+#define	INTRENTRY \
+	subq	$32,%rsp		; \
+	testq	$SEL_UPL,56(%rsp)	; \
+	je	98f			; \
+	swapgs				; \
+	movw	%gs,0(%rsp)		; \
+	movw	%fs,8(%rsp)		; \
+	movw	%es,16(%rsp)		; \
+	movw	%ds,24(%rsp)		; \
+98: 	INTR_SAVE_GPRS
+
+#define INTRFASTEXIT \
+	INTR_RESTORE_GPRS 		; \
+	testq	$SEL_UPL,56(%rsp)	; \
+	je	99f			; \
+	cli				; \
+	swapgs				; \
+	movw	0(%rsp),%gs		; \
+	movw	8(%rsp),%fs		; \
+	movw	16(%rsp),%es		; \
+	movw	24(%rsp),%ds		; \
+99:	addq	$48,%rsp		; \
+	iretq
+
+#define INTR_RECURSE_HWFRAME \
+	movq	%rsp,%r10		; \
+	movl	%ss,%r11d		; \
+	pushq	%r11			; \
+	pushq	%r10			; \
+	pushfq				; \
+	movl	%cs,%r11d		; \
+	pushq	%r11			; \
+	pushq	%r13			;
+
+
+#define CHECK_ASTPENDING(reg)	movq	CPUVAR(CURPROC),reg		; \
+				cmpq	$0, reg				; \
+				je	99f				; \
+				cmpl	$0, P_MD_ASTPENDING(reg)	; \
+				99:
+
+#define CLEAR_ASTPENDING(reg)	movl	$0, P_MD_ASTPENDING(reg)
+
+#endif /* _AMD64_MACHINE_FRAMEASM_H */
diff --git a/sys/arch/amd64/include/gdt.h b/sys/arch/amd64/include/gdt.h
new file mode 100644
index 00000000000..a26608a78e8
--- /dev/null
+++ b/sys/arch/amd64/include/gdt.h
@@ -0,0 +1,62 @@
+/*	$OpenBSD: gdt.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: gdt.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by John T. Kohl and Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOCORE
+struct proc;
+struct pmap;
+
+void gdt_init(void);
+void gdt_init_cpu(struct cpu_info *);
+void gdt_reload_cpu(struct cpu_info *);
+void gdt_alloc_cpu(struct cpu_info *);
+
+int tss_alloc(struct pcb *);
+void tss_free(int);
+
+void ldt_alloc(struct pmap *, char *, size_t);
+void ldt_free(struct pmap *);
+
+void set_mem_gdt(struct mem_segment_descriptor *, void *, size_t,
+		 int, int, int, int, int);
+void set_sys_gdt(struct sys_segment_descriptor *, void *, size_t, int, int,
+		 int);
+#endif
+
+#define MINGDTSIZ       2048
+#define MAXGDTSIZ       65536
diff --git a/sys/arch/amd64/include/i82093reg.h b/sys/arch/amd64/include/i82093reg.h
new file mode 100644
index 00000000000..91dc73bb1df
--- /dev/null
+++ b/sys/arch/amd64/include/i82093reg.h
@@ -0,0 +1,121 @@
+/*	$OpenBSD: i82093reg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* 	$NetBSD: i82093reg.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Typically, the first apic lives here.
+ */
+#define IOAPIC_BASE_DEFAULT	0xfec00000
+
+/*
+ * Memory-space registers.
+ */
+
+/*
+ * The externally visible registers are all 32 bits wide;
+ * store the register number of interest in IOAPIC_REG, and store/fetch
+ * the real value in IOAPIC_DATA.
+ */
+   
+
+
+#define	IOAPIC_REG		0x0000
+#define IOAPIC_DATA		0x0010
+
+/*
+ * Internal I/O APIC registers.
+ */
+
+#define IOAPIC_ID		0x00
+
+#define 	IOAPIC_ID_SHIFT		24
+#define		IOAPIC_ID_MASK		0x0f000000
+
+/* Version, and maximum interrupt pin number. */
+  
+#define IOAPIC_VER		0x01
+
+#define		IOAPIC_VER_SHIFT		0
+#define		IOAPIC_VER_MASK			0x000000ff
+
+#define		IOAPIC_MAX_SHIFT	       	16
+#define		IOAPIC_MAX_MASK	       	0x00ff0000
+
+/*
+ * Arbitration ID.  Same format as IOAPIC_ID register.
+ */
+#define IOAPIC_ARB		0x02
+
+/*
+ * Redirection table registers.
+ */
+
+#define IOAPIC_REDHI(pin)	(0x11 + ((pin)<<1))
+#define IOAPIC_REDLO(pin)	(0x10 + ((pin)<<1))
+
+#define IOAPIC_REDHI_DEST_SHIFT		24	   /* destination. */
+#define IOAPIC_REDHI_DEST_MASK		0xff000000
+
+#define IOAPIC_REDLO_MASK		0x00010000 /* 0=enabled; 1=masked */
+
+#define IOAPIC_REDLO_LEVEL		0x00008000 /* 0=edge, 1=level */
+#define IOAPIC_REDLO_RIRR		0x00004000 /* remote IRR; read only */
+#define IOAPIC_REDLO_ACTLO		0x00002000 /* 0=act. hi; 1=act. lo */
+#define IOAPIC_REDLO_DELSTS		0x00001000 /* 0=idle; 1=send pending */
+#define IOAPIC_REDLO_DSTMOD		0x00000800 /* 0=physical; 1=logical */
+
+#define IOAPIC_REDLO_DEL_MASK		0x00000700 /* del. mode mask */
+#define IOAPIC_REDLO_DEL_SHIFT		8
+
+#define IOAPIC_REDLO_DEL_FIXED		0
+#define IOAPIC_REDLO_DEL_LOPRI		1
+#define IOAPIC_REDLO_DEL_SMI		2
+#define IOAPIC_REDLO_DEL_NMI		4
+#define IOAPIC_REDLO_DEL_INIT		5
+#define IOAPIC_REDLO_DEL_EXTINT		7
+
+#define IOAPIC_REDLO_VECTOR_MASK	0x000000ff /* delivery vector */
+
+#define IMCR_ADDR		0x22
+#define IMCR_DATA		0x23
+
+#define IMCR_REGISTER		0x70
+#define		IMCR_PIC	0x00
+#define 	IMCR_APIC	0x01
diff --git a/sys/arch/amd64/include/i82093var.h b/sys/arch/amd64/include/i82093var.h
new file mode 100644
index 00000000000..78f1358bb63
--- /dev/null
+++ b/sys/arch/amd64/include/i82093var.h
@@ -0,0 +1,104 @@
+/*	$OpenBSD: i82093var.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* $NetBSD: i82093var.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_I82093VAR_H_
+#define _X86_I82093VAR_H_
+
+#include <machine/apicvar.h>
+
+struct ioapic_pin 
+{
+	struct ioapic_pin	*ip_next;	/* next pin on this vector */
+	struct mp_intr_map 	*ip_map;
+	int			ip_vector;	/* IDT vector */
+	int			ip_type;
+	struct cpu_info		*ip_cpu;	/* target CPU */
+};
+
+struct ioapic_softc {
+	struct pic		sc_pic;
+	struct ioapic_softc	*sc_next;
+	int			sc_apicid;
+	int			sc_apic_vers;
+	int			sc_apic_vecbase; /* global int base if ACPI */
+	int			sc_apic_sz;	/* apic size*/
+	int			sc_flags;
+	paddr_t			sc_pa;		/* PA of ioapic */
+	volatile u_int32_t	*sc_reg;	/* KVA of ioapic addr */
+	volatile u_int32_t	*sc_data;	/* KVA of ioapic data */
+	struct ioapic_pin	*sc_pins;	/* sc_apic_sz entries */
+};      
+
+/*
+ * MP: intr_handle_t is bitfielded.
+ * ih&0xff -> legacy irq number.
+ * ih&0x10000000 -> if 0, old-style isa irq; if 1, routed via ioapic.
+ * (ih&0xff0000)>>16 -> ioapic id.
+ * (ih&0x00ff00)>>8 -> ioapic pin.
+ */
+
+#define APIC_INT_VIA_APIC	0x10000000
+#define APIC_INT_APIC_MASK	0x00ff0000
+#define APIC_INT_APIC_SHIFT	16
+#define APIC_INT_PIN_MASK	0x0000ff00
+#define APIC_INT_PIN_SHIFT	8
+
+#define APIC_IRQ_APIC(x) ((x & APIC_INT_APIC_MASK) >> APIC_INT_APIC_SHIFT)
+#define APIC_IRQ_PIN(x) ((x & APIC_INT_PIN_MASK) >> APIC_INT_PIN_SHIFT)
+#define APIC_IRQ_ISLEGACY(x) (!((x) & APIC_INT_VIA_APIC))
+#define APIC_IRQ_LEGACY_IRQ(x) ((x) & 0xff)
+
+void *apic_intr_establish(int, int, int, int (*)(void *), void *); 
+void apic_intr_disestablish(void *);
+
+void ioapic_print_redir(struct ioapic_softc *, char *, int);
+void ioapic_format_redir(char *, char *, int, u_int32_t, u_int32_t);
+struct ioapic_softc *ioapic_find(int);
+struct ioapic_softc *ioapic_find_bybase(int);
+
+void ioapic_enable(void);
+void lapic_vectorset(void); /* XXX */
+
+extern int ioapic_bsp_id;
+extern int nioapics;
+extern struct ioapic_softc *ioapics;
+
+#endif /* !_X86_I82093VAR_H_ */
diff --git a/sys/arch/amd64/include/i82489reg.h b/sys/arch/amd64/include/i82489reg.h
new file mode 100644
index 00000000000..fb1bb6217b4
--- /dev/null
+++ b/sys/arch/amd64/include/i82489reg.h
@@ -0,0 +1,150 @@
+/*	$OpenBSD: i82489reg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: i82489reg.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Registers and constants for the 82489DX and Pentium (and up) integrated
+ * "local" APIC.
+ */
+
+#define	LAPIC_ID		0x020		/* ID. RW */
+#	define LAPIC_ID_MASK		0x0f000000
+#	define LAPIC_ID_SHIFT		24
+
+#define LAPIC_VERS		0x030		/* Version. R */
+#	define LAPIC_VERSION_MASK	0x000000ff
+#	define LAPIC_VERSION_LVT_MASK	0x00ff0000
+#	define LAPIC_VERSION_LVT_SHIFT	16
+
+#define LAPIC_TPRI		0x080		/* Task Prio. RW */
+#	define LAPIC_TPRI_MASK		0x000000ff
+#	define LAPIC_TPRI_INT_MASK	0x000000f0
+#	define LAPIC_TPRI_SUB_MASK	0x0000000f
+
+#define LAPIC_APRI		0x090		/* Arbitration prio R */
+#	define LAPIC_APRI_MASK		0x000000ff
+
+#define LAPIC_PPRI		0x0a0		/* Processor prio. R */
+#define LAPIC_EOI		0x0b0		/* End Int. W */
+#define LAPIC_RRR		0x0c0		/* Remote read R */
+#define LAPIC_LDR		0x0d0		/* Logical dest. RW */
+#define LAPIC_DFR		0x0e0		/* Dest. format RW */
+
+#define LAPIC_SVR		0x0f0		/* Spurious intvec RW */
+#	define LAPIC_SVR_VECTOR_MASK	0x000000ff
+#	define LAPIC_SVR_VEC_FIX	0x0000000f
+#	define LAPIC_SVR_VEC_PROG	0x000000f0
+#	define LAPIC_SVR_ENABLE		0x00000100
+#	define LAPIC_SVR_SWEN		0x00000100
+#	define LAPIC_SVR_FOCUS		0x00000200
+#	define LAPIC_SVR_FDIS		0x00000200
+
+#define LAPIC_ISR	0x100			/* Int. status. R */
+#define LAPIC_TMR	0x180
+#define LAPIC_IRR	0x200
+#define LAPIC_ESR	0x280			/* Err status. R */
+
+#define LAPIC_ICRLO	0x300			/* Int. cmd. RW */
+#	define LAPIC_DLMODE_MASK	0x00000700
+#	define LAPIC_DLMODE_FIXED	0x00000000
+#	define LAPIC_DLMODE_LOW		0x00000100
+#	define LAPIC_DLMODE_SMI		0x00000200
+#	define LAPIC_DLMODE_RR		0x00000300
+#	define LAPIC_DLMODE_NMI		0x00000400
+#	define LAPIC_DLMODE_INIT	0x00000500
+#	define LAPIC_DLMODE_STARTUP	0x00000600
+
+#	define LAPIC_DSTMODE_LOG	0x00000800
+
+#	define LAPIC_DLSTAT_BUSY	0x00001000
+
+#	define LAPIC_LVL_ASSERT		0x00004000
+#	define LAPIC_LVL_DEASSERT	0x00000000
+
+#	define LAPIC_LVL_TRIG		0x00008000
+
+#	define LAPIC_RRSTAT_MASK	0x00030000
+#	define LAPIC_RRSTAT_INPROG	0x00010000
+#	define LAPIC_RRSTAT_VALID	0x00020000
+
+#	define LAPIC_DEST_MASK		0x000c0000
+#	define LAPIC_DEST_SELF		0x00040000
+#	define LAPIC_DEST_ALLINCL	0x00080000
+#	define LAPIC_DEST_ALLEXCL	0x000c0000
+
+#	define LAPIC_RESV2_MASK		0xfff00000
+
+
+#define LAPIC_ICRHI	0x310			/* Int. cmd. RW */
+#	define LAPIC_ID_MASK		0x0f000000
+#	define LAPIC_ID_SHIFT		24
+
+#define LAPIC_LVTT	0x320			/* Loc.vec.(timer) RW */
+#	define LAPIC_LVTT_VEC_MASK	0x000000ff
+#	define LAPIC_LVTT_DS		0x00001000
+#	define LAPIC_LVTT_M		0x00010000
+#	define LAPIC_LVTT_TM		0x00020000
+
+#define LAPIC_PCINT	0x340
+#define LAPIC_LVINT0	0x350			/* Loc.vec (LINT0) RW */
+#	define LAPIC_LVT_PERIODIC	0x00020000
+#	define LAPIC_LVT_MASKED		0x00010000
+#	define LAPIC_LVT_LEVTRIG	0x00008000
+#	define LAPIC_LVT_REMOTE_IRR	0x00004000
+#	define LAPIC_INP_POL		0x00002000
+#	define LAPIC_PEND_SEND		0x00001000
+
+#define LAPIC_LVINT1	0x360			/* Loc.vec (LINT1) RW */
+#define LAPIC_LVERR	0x370			/* Loc.vec (ERROR) RW */
+#define LAPIC_ICR_TIMER	0x380			/* Initial count RW */
+#define LAPIC_CCR_TIMER	0x390			/* Current count RO */
+
+#define LAPIC_DCR_TIMER	0x3e0			/* Divisor config register */
+#	define LAPIC_DCRT_DIV1		0x0b
+#	define LAPIC_DCRT_DIV2		0x00
+#	define LAPIC_DCRT_DIV4		0x01
+#	define LAPIC_DCRT_DIV8		0x02
+#	define LAPIC_DCRT_DIV16		0x03
+#	define LAPIC_DCRT_DIV32		0x08
+#	define LAPIC_DCRT_DIV64		0x09
+#	define LAPIC_DCRT_DIV128	0x0a
+
+#define LAPIC_BASE		0xfee00000
+
+#define LAPIC_IRQ_MASK(i)	(1 << ((i) + 1))
diff --git a/sys/arch/amd64/include/i8259.h b/sys/arch/amd64/include/i8259.h
new file mode 100644
index 00000000000..e89f77f4164
--- /dev/null
+++ b/sys/arch/amd64/include/i8259.h
@@ -0,0 +1,152 @@
+/*	$OpenBSD: i8259.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: i8259.h,v 1.3 2003/05/04 22:01:56 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)icu.h	5.6 (Berkeley) 5/9/91
+ */
+
+#ifndef	_X86_I8259_H_
+#define	_X86_I8259_H_
+
+#include <dev/isa/isareg.h>
+
+#ifndef	_LOCORE
+
+/*
+ * Interrupt "level" mechanism variables, masks, and macros
+ */
+extern	unsigned i8259_imen;		/* interrupt mask enable */
+extern unsigned i8259_setmask(unsigned);
+
+#define SET_ICUS()	(outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
+
+extern void i8259_default_setup(void);
+extern void i8259_reinit(void);
+
+#endif /* !_LOCORE */
+
+/*
+ * Interrupt enable bits -- in order of priority
+ */
+#define	IRQ_SLAVE	2
+
+/*
+ * Interrupt Control offset into Interrupt descriptor table (IDT)
+ */
+#define	ICU_OFFSET	32		/* 0-31 are processor exceptions */
+#define	ICU_LEN		16		/* 32-47 are ISA interrupts */
+
+
+#define ICU_HARDWARE_MASK
+
+/*
+ * These macros are fairly self explanatory.  If ICU_SPECIAL_MASK_MODE is
+ * defined, we try to take advantage of the ICU's `special mask mode' by only
+ * EOIing the interrupts on return.  This avoids the requirement of masking and
+ * unmasking.  We can't do this without special mask mode, because the ICU
+ * would also hold interrupts that it thinks are of lower priority.
+ *
+ * Many machines do not support special mask mode, so by default we don't try
+ * to use it.
+ */
+
+#define	IRQ_BIT(num)	(1 << ((num) % 8))
+#define	IRQ_BYTE(num)	((num) >> 3)
+
+#define i8259_late_ack(num)
+
+#ifdef ICU_SPECIAL_MASK_MODE
+
+#define	i8259_asm_ack1(num)
+#define	i8259_asm_ack2(num) \
+	movb	$(0x60|IRQ_SLAVE),%al	/* specific EOI for IRQ2 */	;\
+	outb	%al,$IO_ICU1
+#define	i8259_asm_mask(num)
+#define	i8259_asm_unmask(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$ICUADDR
+
+#else /* ICU_SPECIAL_MASK_MODE */
+
+#ifndef	AUTO_EOI_1
+#define	i8259_asm_ack1(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$IO_ICU1
+#else
+#define	i8259_asm_ack1(num)
+#endif
+
+#ifndef AUTO_EOI_2
+#define	i8259_asm_ack2(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$IO_ICU2		/* do the second ICU first */	;\
+	movb	$(0x60|IRQ_SLAVE),%al	/* specific EOI for IRQ2 */	;\
+	outb	%al,$IO_ICU1
+#else
+#define	i8259_asm_ack2(num)
+#endif
+
+#ifdef PIC_MASKDELAY
+#define MASKDELAY	pushl %eax ; inb $0x84,%al ; popl %eax
+#else
+#define MASKDELAY
+#endif
+
+#ifdef ICU_HARDWARE_MASK
+
+#define	i8259_asm_mask(num) \
+	movb	CVAROFF(i8259_imen, IRQ_BYTE(num)),%al			;\
+	orb	$IRQ_BIT(num),%al					;\
+	movb	%al,CVAROFF(i8259_imen, IRQ_BYTE(num))			;\
+	MASKDELAY							;\
+	outb	%al,$(ICUADDR+1)
+#define	i8259_asm_unmask(num) \
+	movb	CVAROFF(i8259_imen, IRQ_BYTE(num)),%al			;\
+	andb	$~IRQ_BIT(num),%al					;\
+	movb	%al,CVAROFF(i8259_imen, IRQ_BYTE(num))			;\
+	MASKDELAY							;\
+	outb	%al,$(ICUADDR+1)
+
+#else /* ICU_HARDWARE_MASK */
+
+#define	i8259_asm_mask(num)
+#define	i8259_asm_unmask(num)
+
+#endif /* ICU_HARDWARE_MASK */
+#endif /* ICU_SPECIAL_MASK_MODE */
+
+#endif /* !_X86_I8259_H_ */
diff --git a/sys/arch/amd64/include/ieee.h b/sys/arch/amd64/include/ieee.h
new file mode 100644
index 00000000000..5a34355d223
--- /dev/null
+++ b/sys/arch/amd64/include/ieee.h
@@ -0,0 +1,133 @@
+/*	$OpenBSD: ieee.h,v 1.1 2004/01/28 01:39:39 mickey Exp $ */
+/*	$NetBSD: ieee.h,v 1.1 1996/09/30 16:34:25 ws Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)ieee.h	8.1 (Berkeley) 6/11/93
+ */
+
+/*
+ * ieee.h defines the machine-dependent layout of the machine's IEEE
+ * floating point.  It does *not* define (yet?) any of the rounding
+ * mode bits, exceptions, and so forth.
+ */
+
+/*
+ * Define the number of bits in each fraction and exponent.
+ *
+ *		     k	         k+1
+ * Note that  1.0 x 2  == 0.1 x 2      and that denorms are represented
+ *
+ *					  (-exp_bias+1)
+ * as fractions that look like 0.fffff x 2             .  This means that
+ *
+ *			 -126
+ * the number 0.10000 x 2    , for instance, is the same as the normalized
+ *
+ *		-127			   -128
+ * float 1.0 x 2    .  Thus, to represent 2    , we need one leading zero
+ *
+ *				  -129
+ * in the fraction; to represent 2    , we need two, and so on.  This
+ *
+ *						     (-exp_bias-fracbits+1)
+ * implies that the smallest denormalized number is 2
+ *
+ * for whichever format we are talking about: for single precision, for
+ *
+ *						-126		-149
+ * instance, we get .00000000000000000000001 x 2    , or 1.0 x 2    , and
+ *
+ * -149 == -127 - 23 + 1.
+ */
+#define	SNG_EXPBITS	8
+#define	SNG_FRACBITS	23
+
+#define	DBL_EXPBITS	11
+#define	DBL_FRACBITS	52
+
+#define	EXT_EXPBITS	15
+#define	EXT_FRACBITS	112
+
+struct ieee_single {
+	u_int	sng_frac:23;
+	u_int	sng_exp:8;
+	u_int	sng_sign:1;
+};
+
+struct ieee_double {
+	u_int	dbl_fracl;
+	u_int	dbl_frach:20;
+	u_int	dbl_exp:11;
+	u_int	dbl_sign:1;
+};
+
+struct ieee_ext {
+	u_int	ext_fracl;
+	u_int	ext_fraclm;
+	u_int	ext_frachm;
+	u_int	ext_frach:16;
+	u_int	ext_exp:15;
+	u_int	ext_sign:1;
+};
+
+/*
+ * Floats whose exponent is in [1..INFNAN) (of whatever type) are
+ * `normal'.  Floats whose exponent is INFNAN are either Inf or NaN.
+ * Floats whose exponent is zero are either zero (iff all fraction
+ * bits are zero) or subnormal values.
+ *
+ * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
+ * high fraction; if the bit is set, it is a `quiet NaN'.
+ */
+#define	SNG_EXP_INFNAN	255
+#define	DBL_EXP_INFNAN	2047
+#define	EXT_EXP_INFNAN	32767
+
+#if 0
+#define	SNG_QUIETNAN	(1 << 22)
+#define	DBL_QUIETNAN	(1 << 19)
+#define	EXT_QUIETNAN	(1 << 15)
+#endif
+
+/*
+ * Exponent biases.
+ */
+#define	SNG_EXP_BIAS	127
+#define	DBL_EXP_BIAS	1023
+#define	EXT_EXP_BIAS	16383
diff --git a/sys/arch/amd64/include/ieeefp.h b/sys/arch/amd64/include/ieeefp.h
new file mode 100644
index 00000000000..774ee8d6adc
--- /dev/null
+++ b/sys/arch/amd64/include/ieeefp.h
@@ -0,0 +1,26 @@
+/*	$OpenBSD: ieeefp.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/* 
+ * Written by J.T. Conklin, Apr 6, 1995
+ * Public domain.
+ */
+
+#ifndef _I386_IEEEFP_H_
+#define _I386_IEEEFP_H_
+
+typedef int fp_except;
+#define FP_X_INV	0x01	/* invalid operation exception */
+#define FP_X_DNML	0x02	/* denormalization exception */
+#define FP_X_DZ		0x04	/* divide-by-zero exception */
+#define FP_X_OFL	0x08	/* overflow exception */
+#define FP_X_UFL	0x10	/* underflow exception */
+#define FP_X_IMP	0x20	/* imprecise (loss of precision) */
+
+typedef enum {
+    FP_RN=0,			/* round to nearest representable number */
+    FP_RM=1,			/* round toward negative infinity */
+    FP_RP=2,			/* round toward positive infinity */
+    FP_RZ=3			/* round to zero (truncate) */
+} fp_rnd;
+
+#endif /* _I386_IEEEFP_H_ */
diff --git a/sys/arch/amd64/include/internal_types.h b/sys/arch/amd64/include/internal_types.h
new file mode 100644
index 00000000000..8237a6b4cef
--- /dev/null
+++ b/sys/arch/amd64/include/internal_types.h
@@ -0,0 +1,10 @@
+/*	$OpenBSD: internal_types.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* Public domain */
+#ifndef _MACHINE_INTERNAL_TYPES_H_
+#define _MACHINE_INTERNAL_TYPES_H_
+
+#ifdef __x86_64__
+#define __machine_is_64_bits
+#endif
+
+#endif
diff --git a/sys/arch/amd64/include/intr.h b/sys/arch/amd64/include/intr.h
new file mode 100644
index 00000000000..1b3390d7b17
--- /dev/null
+++ b/sys/arch/amd64/include/intr.h
@@ -0,0 +1,356 @@
+/*	$OpenBSD: intr.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: intr.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum, and by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_INTR_H_
+#define _X86_INTR_H_
+
+#include <machine/intrdefs.h>
+
+#ifndef _LOCORE
+#include <machine/cpu.h>
+#include <machine/pic.h>
+
+/*
+ * Struct describing an interrupt source for a CPU. struct cpu_info
+ * has an array of MAX_INTR_SOURCES of these. The index in the array
+ * is equal to the stub number of the stubcode as present in vector.s
+ *
+ * The primary CPU's array of interrupt sources has its first 16
+ * entries reserved for legacy ISA irq handlers. This means that
+ * they have a 1:1 mapping for arrayindex:irq_num. This is not
+ * true for interrupts that come in through IO APICs, to find
+ * their source, go through ci->ci_isources[index].is_pic
+ *
+ * It's possible to always maintain a 1:1 mapping, but that means
+ * limiting the total number of interrupt sources to MAX_INTR_SOURCES
+ * (32), instead of 32 per CPU. It also would mean that having multiple
+ * IO APICs which deliver interrupts from an equal pin number would
+ * overlap if they were to be sent to the same CPU.
+ */
+
+struct intrstub {
+	void *ist_entry;
+	void *ist_recurse; 
+	void *ist_resume;
+};
+
+struct intrsource {
+	int is_maxlevel;		/* max. IPL for this source */
+	int is_pin;			/* IRQ for legacy; pin for IO APIC */
+	struct intrhand *is_handlers;	/* handler chain */
+	struct pic *is_pic;		/* originating PIC */
+	void *is_recurse;		/* entry for spllower */
+	void *is_resume;		/* entry for doreti */
+	struct evcnt is_evcnt;		/* interrupt counter */
+	char is_evname[32];		/* event counter name */
+	int is_flags;			/* see below */
+	int is_type;			/* level, edge */
+	int is_idtvec;
+	int is_minlevel;
+};
+
+#define IS_LEGACY	0x0001		/* legacy ISA irq source */
+#define IS_IPI		0x0002
+#define IS_LOG		0x0004
+
+
+/*
+ * Interrupt handler chains.  *_intr_establish() insert a handler into
+ * the list.  The handler is called with its (single) argument.
+ */
+
+struct intrhand {
+	int	(*ih_fun)(void *);
+	void	*ih_arg;
+	int	ih_level;
+	struct	intrhand *ih_next;
+	int	ih_pin;
+	int	ih_slot;
+	struct cpu_info *ih_cpu;
+	int	ih_irq;
+	char	*ih_what;
+};
+
+#define IMASK(ci,level) (ci)->ci_imask[(level)]
+#define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
+
+extern void Xspllower(int);
+
+static __inline int splraise(int);
+static __inline void spllower(int);
+static __inline void softintr(int);
+
+/*
+ * Convert spl level to local APIC level
+ */
+#define APIC_LEVEL(l)   ((l) << 4)
+
+/*
+ * compiler barrier: prevent reordering of instructions.
+ * XXX something similar will move to <sys/cdefs.h>
+ * or thereabouts.
+ * This prevents the compiler from reordering code around
+ * this "instruction", acting as a sequence point for code generation.
+ */
+
+#define	__splbarrier() __asm __volatile("":::"memory")
+
+/*
+ * Add a mask to cpl, and return the old value of cpl.
+ */
+static __inline int
+splraise(int nlevel)
+{
+	int olevel;
+	struct cpu_info *ci = curcpu();
+
+	olevel = ci->ci_ilevel;
+	if (nlevel > olevel)
+		ci->ci_ilevel = nlevel;
+	__splbarrier();
+	return (olevel);
+}
+
+/*
+ * Restore a value to cpl (unmasking interrupts).  If any unmasked
+ * interrupts are pending, call Xspllower() to process them.
+ */
+static __inline void
+spllower(int nlevel)
+{
+	struct cpu_info *ci = curcpu();
+
+	__splbarrier();
+	/*
+	 * Since this should only lower the interrupt level,
+	 * the XOR below should only show interrupts that
+	 * are being unmasked.
+	 */
+	if (ci->ci_ipending & IUNMASK(ci,nlevel))
+		Xspllower(nlevel);
+	else
+		ci->ci_ilevel = nlevel;
+}
+
+/*
+ * Hardware interrupt masks
+ */
+#define	splbio()	splraise(IPL_BIO)
+#define	splnet()	splraise(IPL_NET)
+#define	spltty()	splraise(IPL_TTY)
+#define	splaudio()	splraise(IPL_AUDIO)
+#define	splclock()	splraise(IPL_CLOCK)
+#define	splstatclock()	splclock()
+#define	splserial()	splraise(IPL_SERIAL)
+#define splipi()	splraise(IPL_IPI)
+
+#define spllpt()	spltty()
+
+#define	spllpt()	spltty()
+
+/*
+ * Software interrupt masks
+ *
+ * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from
+ * clock to softclock before it calls softclock().
+ */
+#define	spllowersoftclock() spllower(IPL_SOFTCLOCK)
+
+#define	splsoftclock()	splraise(IPL_SOFTCLOCK)
+#define	splsoftnet()	splraise(IPL_SOFTNET)
+#define	splsoftserial()	splraise(IPL_SOFTSERIAL)
+
+/*
+ * Miscellaneous
+ */
+#define splimp()	splraise(IPL_IMP)
+#define	splvm()		splraise(IPL_IMP)
+#define	splhigh()	splraise(IPL_HIGH)
+#define	spl0()		spllower(IPL_NONE)
+#define	splsched()	splraise(IPL_SCHED)
+#define spllock() 	splhigh()
+#define	splx(x)		spllower(x)
+
+/* SPL asserts */
+#ifdef DIAGNOSTIC
+/*
+ * Although this function is implemented in MI code, it must be in this MD
+ * header because we don't want this header to include MI includes.
+ */
+void splassert_fail(int, int, const char *);
+extern int splassert_ctl;
+void splassert_check(int, const char *);
+#define splassert(__wantipl) do {			\
+	if (__predict_false(splassert_ctl > 0)) {	\
+		splassert_check(__wantipl, __func__);	\
+	}						\
+} while (0)
+#else
+#define splassert(wantipl) do { /* nada */ } while (0)
+#endif
+
+/*
+ * Software interrupt registration
+ *
+ * We hand-code this to ensure that it's atomic.
+ *
+ * XXX always scheduled on the current CPU.
+ */
+static __inline void
+softintr(int sir)
+{
+	struct cpu_info *ci = curcpu();
+
+	__asm __volatile("lock ; orl %1, %0" :
+	    "=m"(ci->ci_ipending) : "ir" (1 << sir));
+}
+
+/*
+ * XXX
+ */
+#define	setsoftnet()	softintr(SIR_NET)
+
+#define IPLSHIFT 4			/* The upper nibble of vectors is the IPL.      */
+#define IPL(level) ((level) >> IPLSHIFT)	/* Extract the IPL.    */
+
+/*
+ * Stub declarations.
+ */
+
+extern void Xsoftclock(void);
+extern void Xsoftnet(void);
+extern void Xsoftserial(void);
+
+extern struct intrstub i8259_stubs[];
+extern struct intrstub ioapic_edge_stubs[];
+extern struct intrstub ioapic_level_stubs[];
+
+struct cpu_info;
+
+extern char idt_allocmap[];
+
+void intr_default_setup(void);
+int x86_nmi(void);
+void intr_calculatemasks(struct cpu_info *);
+int intr_allocate_slot_cpu(struct cpu_info *, struct pic *, int, int *);
+int intr_allocate_slot(struct pic *, int, int, int, struct cpu_info **, int *,
+		       int *);
+void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *);
+void intr_disestablish(struct intrhand *);
+void cpu_intr_init(struct cpu_info *);
+int intr_find_mpmapping(int bus, int pin, int *handle);
+void intr_printconfig(void);
+
+#ifdef MULTIPROCESSOR
+int x86_send_ipi(struct cpu_info *, int);
+void x86_broadcast_ipi(int);
+void x86_multicast_ipi(int, int);
+void x86_ipi_handler(void);
+void x86_intlock(struct intrframe);
+void x86_intunlock(struct intrframe);
+void x86_softintlock(void);
+void x86_softintunlock(void);
+
+extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
+#endif
+
+#endif /* !_LOCORE */
+
+/*
+ * Generic software interrupt support.
+ */
+
+#define	X86_SOFTINTR_SOFTCLOCK		0
+#define	X86_SOFTINTR_SOFTNET		1
+#define	X86_SOFTINTR_SOFTSERIAL	2
+#define	X86_NSOFTINTR			3
+
+#ifndef _LOCORE
+#include <sys/queue.h>
+
+struct x86_soft_intrhand {
+	TAILQ_ENTRY(x86_soft_intrhand)
+		sih_q;
+	struct x86_soft_intr *sih_intrhead;
+	void	(*sih_fn)(void *);
+	void	*sih_arg;
+	int	sih_pending;
+};
+
+struct x86_soft_intr {
+	TAILQ_HEAD(, x86_soft_intrhand)
+		softintr_q;
+	int softintr_ssir;
+	struct simplelock softintr_slock;
+};
+
+#define	x86_softintr_lock(si, s)					\
+do {									\
+	(s) = splhigh();						\
+	simple_lock(&si->softintr_slock);				\
+} while (/*CONSTCOND*/ 0)
+
+#define	x86_softintr_unlock(si, s)					\
+do {									\
+	simple_unlock(&si->softintr_slock);				\
+	splx((s));							\
+} while (/*CONSTCOND*/ 0)
+
+void	*softintr_establish(int, void (*)(void *), void *);
+void	softintr_disestablish(void *);
+void	softintr_init(void);
+void	softintr_dispatch(int);
+
+#define	softintr_schedule(arg)						\
+do {									\
+	struct x86_soft_intrhand *__sih = (arg);			\
+	struct x86_soft_intr *__si = __sih->sih_intrhead;		\
+	int __s;							\
+									\
+	x86_softintr_lock(__si, __s);					\
+	if (__sih->sih_pending == 0) {					\
+		TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q);	\
+		__sih->sih_pending = 1;					\
+		softintr(__si->softintr_ssir);				\
+	}								\
+	x86_softintr_unlock(__si, __s);					\
+} while (/*CONSTCOND*/ 0)
+#endif /* _LOCORE */
+
+#endif /* !_X86_INTR_H_ */
diff --git a/sys/arch/amd64/include/intrdefs.h b/sys/arch/amd64/include/intrdefs.h
new file mode 100644
index 00000000000..d1b46308c38
--- /dev/null
+++ b/sys/arch/amd64/include/intrdefs.h
@@ -0,0 +1,93 @@
+/*	$OpenBSD: intrdefs.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $	*/
+
+#ifndef _i386_INTRDEFS_H
+#define _i386_INTRDEFS_H
+
+/*
+ * Interrupt priority levels.
+ * 
+ * There are tty, network and disk drivers that use free() at interrupt
+ * time, so imp > (tty | net | bio).
+ *
+ * Since run queues may be manipulated by both the statclock and tty,
+ * network, and disk drivers, clock > imp.
+ *
+ * IPL_HIGH must block everything that can manipulate a run queue.
+ *
+ * We need serial drivers to run at the absolute highest priority to
+ * avoid overruns, so serial > high.
+ *
+ * The level numbers are picked to fit into APIC vector priorities.
+ *
+ */
+#define	IPL_NONE	0x0	/* nothing */
+#define	IPL_SOFTCLOCK	0x4	/* timeouts */
+#define	IPL_SOFTNET	0x5	/* protocol stacks */
+#define	IPL_BIO		0x6	/* block I/O */
+#define	IPL_NET		0x7	/* network */
+#define	IPL_SOFTSERIAL	0x8	/* serial */
+#define	IPL_TTY		0x9	/* terminal */
+#define	IPL_VM		0xa	/* memory allocation */
+#define IPL_IMP		IPL_VM
+#define	IPL_AUDIO	0xb	/* audio */
+#define	IPL_CLOCK	0xc	/* clock */
+#define IPL_SCHED	IPL_CLOCK
+#define IPL_STATCLOCK	IPL_CLOCK
+#define	IPL_HIGH	0xd	/* everything */
+#define	IPL_SERIAL	0xd	/* serial */
+#define IPL_IPI		0xe	/* inter-processor interrupts */
+#define	NIPL		16
+
+/* Interrupt sharing types. */
+#define	IST_NONE	0	/* none */
+#define	IST_PULSE	1	/* pulsed */
+#define	IST_EDGE	2	/* edge-triggered */
+#define	IST_LEVEL	3	/* level-triggered */
+
+/*
+ * Local APIC masks. Must not conflict with SIR_* above, and must
+ * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first.
+ */
+#define LIR_IPI		31
+#define LIR_TIMER	30
+
+/* Soft interrupt masks. */
+#define	SIR_CLOCK	29
+#define	SIR_NET		28
+#define	SIR_SERIAL	27
+
+
+/*
+ * Maximum # of interrupt sources per CPU. 32 to fit in one word.
+ * ioapics can theoretically produce more, but it's not likely to
+ * happen. For multiple ioapics, things can be routed to different
+ * CPUs.
+ */
+#define MAX_INTR_SOURCES	32
+#define NUM_LEGACY_IRQS		16
+
+/*
+ * Low and high boundaries between which interrupt gates will
+ * be allocated in the IDT.
+ */
+#define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
+#define IDT_INTR_HIGH	0xef
+
+#define X86_IPI_HALT			0x00000001
+#define X86_IPI_MICROSET		0x00000002
+#define X86_IPI_FLUSH_FPU		0x00000004
+#define X86_IPI_SYNCH_FPU		0x00000008
+#define X86_IPI_TLB			0x00000010
+#define X86_IPI_MTRR			0x00000020
+#define X86_IPI_GDT			0x00000040
+
+#define X86_NIPI		7
+
+#define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
+			 "FPU synch IPI", "TLB shootdown IPI", \
+			 "MTRR update IPI", "GDT update IPI" }
+
+#define IREENT_MAGIC	0x18041969
+
+#endif /* _X86_INTRDEFS_H */
diff --git a/sys/arch/amd64/include/isa_machdep.h b/sys/arch/amd64/include/isa_machdep.h
new file mode 100644
index 00000000000..306eed9ef8e
--- /dev/null
+++ b/sys/arch/amd64/include/isa_machdep.h
@@ -0,0 +1,237 @@
+/*	$OpenBSD: isa_machdep.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: isa_machdep.h,v 1.2 2003/05/09 23:51:28 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)isa.h	5.7 (Berkeley) 5/9/91
+ */
+
+/*
+ * Various pieces of the i386 port want to include this file without
+ * or in spite of using isavar.h, and should be fixed.
+ */
+
+#ifndef _I386_ISA_MACHDEP_H_			/* XXX */
+#define _I386_ISA_MACHDEP_H_			/* XXX */
+
+#include <machine/bus.h>
+#include <dev/isa/isadmavar.h>
+
+/*
+ * XXX THIS FILE IS A MESS.  copyright: berkeley's probably.
+ * contents from isavar.h and isareg.h, mostly the latter.
+ * perhaps charles's?
+ *
+ * copyright from berkeley's isa.h which is now dev/isa/isareg.h.
+ */
+
+/*
+ * Types provided to machine-independent ISA code.
+ */
+
+typedef void *isa_chipset_tag_t;
+
+struct device;			/* XXX */
+struct isabus_attach_args;	/* XXX */
+
+/*
+ * Functions provided to machine-independent ISA code.
+ */
+void	isa_attach_hook(struct device *, struct device *,
+	    struct isabus_attach_args *);
+int	isa_intr_alloc(isa_chipset_tag_t, int, int, int *);
+const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq);
+void	*isa_intr_establish(isa_chipset_tag_t ic, int irq, int type,
+	    int level, int (*ih_fun)(void *), void *ih_arg, char *);
+void	isa_intr_disestablish(isa_chipset_tag_t ic, void *handler);
+int	isa_mem_alloc(bus_space_tag_t, bus_size_t, bus_size_t,
+	    bus_addr_t, int, bus_addr_t *, bus_space_handle_t *);
+void	isa_mem_free(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+
+#define	isa_dmainit(ic, bst, dmat, d)					\
+	_isa_dmainit(&(ic)->ic_dmastate, (bst), (dmat), (d))
+#define	isa_dmacascade(ic, c)						\
+	_isa_dmacascade(&(ic)->ic_dmastate, (c))
+#define	isa_dmamaxsize(ic, c)						\
+	_isa_dmamaxsize(&(ic)->ic_dmastate, (c))
+#define	isa_dmamap_create(ic, c, s, f)					\
+	_isa_dmamap_create(&(ic)->ic_dmastate, (c), (s), (f))
+#define	isa_dmamap_destroy(ic, c)					\
+	_isa_dmamap_destroy(&(ic)->ic_dmastate, (c))
+#define	isa_dmastart(ic, c, a, n, p, f, bf)				\
+	_isa_dmastart(&(ic)->ic_dmastate, (c), (a), (n), (p), (f), (bf))
+#define	isa_dmaabort(ic, c)						\
+	_isa_dmaabort(&(ic)->ic_dmastate, (c))
+#define	isa_dmacount(ic, c)						\
+	_isa_dmacount(&(ic)->ic_dmastate, (c))
+#define	isa_dmafinished(ic, c)						\
+	_isa_dmafinished(&(ic)->ic_dmastate, (c))
+#define	isa_dmadone(ic, c)						\
+	_isa_dmadone(&(ic)->ic_dmastate, (c))
+#define	isa_dmafreeze(ic)						\
+	_isa_dmafreeze(&(ic)->ic_dmastate)
+#define	isa_dmathaw(ic)							\
+	_isa_dmathaw(&(ic)->ic_dmastate)
+#define	isa_dmamem_alloc(ic, c, s, ap, f)				\
+	_isa_dmamem_alloc(&(ic)->ic_dmastate, (c), (s), (ap), (f))
+#define	isa_dmamem_free(ic, c, a, s)					\
+	_isa_dmamem_free(&(ic)->ic_dmastate, (c), (a), (s))
+#define	isa_dmamem_map(ic, c, a, s, kp, f)				\
+	_isa_dmamem_map(&(ic)->ic_dmastate, (c), (a), (s), (kp), (f))
+#define	isa_dmamem_unmap(ic, c, k, s)					\
+	_isa_dmamem_unmap(&(ic)->ic_dmastate, (c), (k), (s))
+#define	isa_dmamem_mmap(ic, c, a, s, o, p, f)				\
+	_isa_dmamem_mmap(&(ic)->ic_dmastate, (c), (a), (s), (o), (p), (f))
+#define isa_drq_alloc(ic, c)						\
+	_isa_drq_alloc(&(ic)->ic_dmastate, c)
+#define isa_drq_free(ic, c)						\
+	_isa_drq_free(&(ic)->ic_dmastate, c)
+#define	isa_drq_isfree(ic, c)						\
+	_isa_drq_isfree(&(ic)->ic_dmastate, (c))
+#define	isa_malloc(ic, c, s, p, f)					\
+	_isa_malloc(&(ic)->ic_dmastate, (c), (s), (p), (f))
+#define	isa_free(a, p)							\
+	_isa_free((a), (p))
+#define	isa_mappage(m, o, p)						\
+	_isa_mappage((m), (o), (p))
+
+int isa_intr_check(isa_chipset_tag_t, int, int);
+
+/*
+ * for ACPI code
+ */
+
+void	isa_reinit_irq(void);
+
+/*
+ * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED
+ * BY PORTABLE CODE.
+ */
+
+extern struct x86_bus_dma_tag isa_bus_dma_tag;
+
+/*
+ * XXX Various seemingly PC-specific constants, some of which may be
+ * unnecessary anyway.
+ */
+
+/*
+ * RAM Physical Address Space (ignoring the above mentioned "hole")
+ */
+#define	RAM_BEGIN	0x0000000	/* Start of RAM Memory */
+#define	RAM_END		0x1000000	/* End of RAM Memory */
+#define	RAM_SIZE	(RAM_END - RAM_BEGIN)
+
+/*
+ * Oddball Physical Memory Addresses
+ */
+#define	COMPAQ_RAMRELOC	0x80c00000	/* Compaq RAM relocation/diag */
+#define	COMPAQ_RAMSETUP	0x80c00002	/* Compaq RAM setup */
+#define	WEITEK_FPU	0xC0000000	/* WTL 2167 */
+#define	CYRIX_EMC	0xC0000000	/* Cyrix EMC */
+
+/*
+ * stuff that used to be in pccons.c
+ */
+#define	MONO_BASE	0x3B4
+#define	MONO_BUF	0xB0000
+#define	CGA_BASE	0x3D4
+#define	CGA_BUF		0xB8000
+
+/*
+ * Variables and macros to deal with the ISA I/O hole.
+ * XXX These should be converted to machine- and bus-mapping-independent
+ * function definitions, invoked through the softc.
+ */
+
+extern u_long atdevbase;           /* kernel virtual address of "hole" */
+
+/*
+ * Given a kernel virtual address for some location
+ * in the "hole" I/O space, return a physical address.
+ */
+#define ISA_PHYSADDR(v) ((void *) ((u_long)(v) - atdevbase + IOM_BEGIN))
+
+/*
+ * Given a physical address in the "hole",
+ * return a kernel virtual address.
+ */
+#define ISA_HOLE_VADDR(p)  ((void *) ((u_long)(p) - IOM_BEGIN + atdevbase))
+
+
+/*
+ * Miscellanous functions.
+ */
+void sysbeep(int, int);		/* beep with the system speaker */
+
+#endif /* _I386_ISA_MACHDEP_H_ XXX */
diff --git a/sys/arch/amd64/include/kcore.h b/sys/arch/amd64/include/kcore.h
new file mode 100644
index 00000000000..ddb4d1d7a85
--- /dev/null
+++ b/sys/arch/amd64/include/kcore.h
@@ -0,0 +1,49 @@
+/*	$NetBSD: kcore.h,v 1.1 2003/04/26 18:39:43 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 1996 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+/*
+ * Modified for NetBSD/i386 by Jason R. Thorpe, Numerical Aerospace
+ * Simulation Facility, NASA Ames Research Center.
+ *
+ * And once again modified for x86-64 by Frank van der Linden of
+ * Wasabi Systems, Inc.
+ */
+
+#ifndef _AMD64KCORE_H_
+#define _AMD64_KCORE_H_
+
+typedef struct cpu_kcore_hdr {
+	u_int64_t	ptdpaddr;		/* PA of PML4 */
+	u_int64_t	nmemsegs;		/* Number of RAM segments */
+#if 0
+	phys_ram_seg_t  memsegs[];		/* RAM segments */
+#endif
+} cpu_kcore_hdr_t;
+
+#endif /* _AMD64_KCORE_H_ */
diff --git a/sys/arch/amd64/include/limits.h b/sys/arch/amd64/include/limits.h
new file mode 100644
index 00000000000..8cde663caa5
--- /dev/null
+++ b/sys/arch/amd64/include/limits.h
@@ -0,0 +1,57 @@
+/*	$OpenBSD: limits.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*
+ * Copyright (c) 1988 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)limits.h	7.2 (Berkeley) 6/28/90
+ */
+
+#ifndef	_MACHINE_LIMITS_H_
+#define	_MACHINE_LIMITS_H_
+
+#define	MB_LEN_MAX	1		/* no multibyte characters */
+
+#if !defined(_ANSI_SOURCE)
+#define SIZE_MAX	ULONG_MAX	/* max value for a size_t */
+#define SSIZE_MAX	LONG_MAX	/* max value for a ssize_t */
+
+#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE)
+#define	SIZE_T_MAX	ULONG_MAX	/* max value for a size_t */
+
+#define	UQUAD_MAX	0xffffffffffffffffULL		/* max unsigned quad */
+#define	QUAD_MAX	0x7fffffffffffffffLL		/* max signed quad */
+#define	QUAD_MIN	(-0x7fffffffffffffffLL-1)	/* min signed quad */
+
+#endif /* !_POSIX_C_SOURCE && !_XOPEN_SOURCE */
+#endif /* !_ANSI_SOURCE */
+
+#endif /* _MACHINE_LIMITS_H_ */
diff --git a/sys/arch/amd64/include/loadfile_machdep.h b/sys/arch/amd64/include/loadfile_machdep.h
new file mode 100644
index 00000000000..7de50b522ee
--- /dev/null
+++ b/sys/arch/amd64/include/loadfile_machdep.h
@@ -0,0 +1,60 @@
+/* XXX - DSR */
+/*	$OpenBSD: loadfile_machdep.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: loadfile_machdep.h,v 1.1 1999/04/29 03:17:12 tsubai Exp $	*/
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Christos Zoulas.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define BOOT_ELF
+#define ELFSIZE 64
+
+#define LOAD_KERNEL	(LOAD_ALL & ~LOAD_TEXTA)
+#define COUNT_KERNEL	(COUNT_ALL & ~COUNT_TEXTA)
+
+#define LOADADDR(a)		((((u_long)(a)) + offset)&0xfffffff)
+#define ALIGNENTRY(a)		((u_long)(a))
+#define READ(f, b, c)		read((f), (void *)LOADADDR(b), (c))
+#define BCOPY(s, d, c)		memcpy((void *)LOADADDR(d), (void *)(s), (c))
+#define BZERO(d, c)		memset((void *)LOADADDR(d), 0, (c))
+#define	WARN(a)			(void)(printf a, \
+				    printf((errno ? ": %s\n" : "\n"), \
+				    strerror(errno)))
+#define PROGRESS(a)		(void) printf a
+#define ALLOC(a)		alloc(a)
+#define FREE(a, b)		free(a, b)
+#define OKMAGIC(a)		((a) == OMAGIC)
+
+void run_loadfile(u_long *, int);
diff --git a/sys/arch/amd64/include/mcontext.h b/sys/arch/amd64/include/mcontext.h
new file mode 100644
index 00000000000..ec1ed5f816c
--- /dev/null
+++ b/sys/arch/amd64/include/mcontext.h
@@ -0,0 +1,108 @@
+/*	$OpenBSD: mcontext.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: mcontext.h,v 1.1 2003/04/26 18:39:44 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AMD64_MCONTEXT_H_
+#define _AMD64_MCONTEXT_H_
+
+/*
+ * Layout of mcontext_t according to the System V Application Binary Interface,
+ * Intel386(tm) Architecture Processor Supplement, Fourth Edition.
+ */  
+
+/*
+ * General register state
+ */
+#define _NGREG		26
+typedef	long		__greg_t;
+typedef	__greg_t	__gregset_t[_NGREG];
+
+/*
+ * This is laid out to match trapframe and intrframe (see <machine/frame.h>).
+ * Hence, memcpy between gregs and a trapframe is possible.
+ */
+#define _REG_RDI	0
+#define _REG_RSI	1
+#define _REG_RDX	2
+#define _REG_RCX	3
+#define _REG_R8		4
+#define _REG_R9		5
+#define _REG_R10	6
+#define _REG_R11	7
+#define _REG_R12	8
+#define _REG_R13	9
+#define _REG_R14	10
+#define _REG_R15	11
+#define _REG_RBP	12
+#define _REG_RBX	13
+#define _REG_RAX	14
+#define _REG_GS		15
+#define _REG_FS		16
+#define _REG_ES		17
+#define _REG_DS		18
+#define _REG_TRAPNO	19
+#define _REG_ERR	20
+#define _REG_RIP	21
+#define _REG_CS		22
+#define _REG_RFL	23
+#define _REG_URSP	24
+#define _REG_SS		25
+
+/*
+ * Floating point register state
+ */
+typedef char __fpregset_t[512];
+
+/*
+ * The padding below is to make __fpregs have a 16-byte aligned offset
+ * within ucontext_t.
+ */
+
+typedef struct {
+	__gregset_t	__gregs;
+	long 		__pad;
+	__fpregset_t	__fpregs;
+} mcontext_t;
+
+#define _UC_UCONTEXT_ALIGN	(~0xf)
+
+#ifdef _KERNEL
+#define _UC_MACHINE_SP(uc)	((uc)->uc_mcontext.__gregs[_REG_URSP])
+#endif
+
+#endif	/* !_AMD64_MCONTEXT_H_ */
diff --git a/sys/arch/amd64/include/mpbiosreg.h b/sys/arch/amd64/include/mpbiosreg.h
new file mode 100644
index 00000000000..8041f5bb930
--- /dev/null
+++ b/sys/arch/amd64/include/mpbiosreg.h
@@ -0,0 +1,138 @@
+/*	$OpenBSD: mpbiosreg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* 	$NetBSD: mpbiosreg.h,v 1.3 2003/03/04 23:27:32 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_MPBIOSREG_H_
+#define _X86_MPBIOSREG_H_
+
+#define BIOS_BASE		(0xf0000)
+#define BIOS_SIZE		(0x10000)
+#define BIOS_COUNT		(BIOS_SIZE)
+
+/*
+ * Multiprocessor config table entry types.
+ */
+
+#define MPS_MCT_CPU	0
+#define MPS_MCT_BUS	1
+#define MPS_MCT_IOAPIC	2
+#define MPS_MCT_IOINT	3
+#define MPS_MCT_LINT	4
+
+#define MPS_MCT_NTYPES	5
+
+/* MP Floating Pointer Structure */
+struct mpbios_fps {
+	u_int32_t	signature;
+/* string defined by the Intel MP Spec as identifying the MP table */
+#define MP_FP_SIG		0x5f504d5f	/* _MP_ */
+	
+	u_int32_t 	pap;
+	u_int8_t  	length;
+	u_int8_t  	spec_rev;
+	u_int8_t  	checksum;
+	u_int8_t  	mpfb1;	/* system configuration */
+	u_int8_t  	mpfb2;	/* flags */
+#define MPFPS_FLAG_IMCR		0x80	/* IMCR present */
+	u_int8_t  	mpfb3;	/* unused */
+	u_int8_t  	mpfb4;	/* unused */
+	u_int8_t  	mpfb5;	/* unused */
+};
+
+/* MP Configuration Table Header */
+struct mpbios_cth {
+	u_int32_t	signature;
+#define MP_CT_SIG		0x504d4350 	/* PCMP */
+	
+	u_int16_t 	base_len;
+	u_int8_t  	spec_rev;
+	u_int8_t  	checksum;
+	u_int8_t  	oem_id[8];
+	u_int8_t  	product_id[12];
+	u_int32_t	oem_table_pointer;
+	u_int16_t 	oem_table_size;
+	u_int16_t 	entry_count;
+	u_int32_t	apic_address;
+	u_int16_t	ext_len;
+	u_int8_t  	ext_cksum;
+	u_int8_t  	reserved;
+};
+
+struct mpbios_proc {
+	u_int8_t  type;
+	u_int8_t  apic_id;
+	u_int8_t  apic_version;
+	u_int8_t  cpu_flags;
+#define PROCENTRY_FLAG_EN	0x01
+#define PROCENTRY_FLAG_BP	0x02
+	u_int32_t  cpu_signature;
+	u_int32_t  feature_flags;
+	u_int32_t  reserved1;
+	u_int32_t  reserved2;
+};
+
+struct mpbios_bus {
+	u_int8_t  type;
+	u_int8_t  bus_id;
+	char    bus_type[6];
+};
+
+struct mpbios_ioapic {
+	u_int8_t  type;
+	u_int8_t  apic_id;
+	u_int8_t  apic_version;
+	u_int8_t  apic_flags;
+#define IOAPICENTRY_FLAG_EN	0x01
+	u_int32_t   apic_address;
+};
+
+struct mpbios_int {
+	u_int8_t  type;
+	u_int8_t  int_type;
+	u_int16_t int_flags;
+	u_int8_t  src_bus_id;
+	u_int8_t  src_bus_irq;
+	u_int8_t  dst_apic_id;
+#define MPS_ALL_APICS	0xff
+	u_int8_t  dst_apic_int;
+};
+
+
+#endif /* !_X86_MPBIOSREG_H_ */
diff --git a/sys/arch/amd64/include/mpbiosvar.h b/sys/arch/amd64/include/mpbiosvar.h
new file mode 100644
index 00000000000..b10bbe44fc7
--- /dev/null
+++ b/sys/arch/amd64/include/mpbiosvar.h
@@ -0,0 +1,62 @@
+/*	$OpenBSD: mpbiosvar.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* $NetBSD: mpbiosvar.h,v 1.2 2003/04/02 07:53:57 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _X86_MPBIOSVAR_H_
+#define _X86_MPBIOSVAR_H_
+
+#define MP_TRAMPOLINE  (2 * PAGE_SIZE)
+
+#if !defined(_LOCORE)
+
+#include <machine/mpbiosreg.h>
+#include <machine/mpconfig.h>
+
+#if defined(_KERNEL)
+void mpbios_scan(struct device *);
+int mpbios_probe(struct device *);
+
+extern int mpbios_scanned;
+#endif
+
+#endif
+
+#endif /* !_X86_MPBIOSVAR_H_ */
diff --git a/sys/arch/amd64/include/mpconfig.h b/sys/arch/amd64/include/mpconfig.h
new file mode 100644
index 00000000000..7c12822824c
--- /dev/null
+++ b/sys/arch/amd64/include/mpconfig.h
@@ -0,0 +1,65 @@
+/*	$NetBSD: mpconfig.h,v 1.1 2003/02/26 21:26:11 fvdl Exp $	*/
+
+/*
+ * Definitions originally from the mpbios code, but now used for ACPI
+ * MP config as well.
+ */
+
+#ifndef _X86_MPCONFIG_H
+#define _X86_MPCONFIG_H
+
+/* 
+ * Interrupt typess
+ */
+#define MPS_INTTYPE_INT         0
+#define MPS_INTTYPE_NMI         1
+#define MPS_INTTYPE_SMI         2
+#define MPS_INTTYPE_ExtINT      3
+ 
+#define MPS_INTPO_DEF           0
+#define MPS_INTPO_ACTHI         1
+#define MPS_INTPO_ACTLO         3
+ 
+#define MPS_INTTR_DEF           0 
+#define MPS_INTTR_EDGE          1
+#define MPS_INTTR_LEVEL         3
+
+#ifndef _LOCORE
+
+struct mpbios_int;
+
+struct mp_bus
+{
+	char *mb_name;		/* XXX bus name */
+	int mb_idx;		/* XXX bus index */
+	void (*mb_intr_print)(int);
+	void (*mb_intr_cfg)(const struct mpbios_int *, u_int32_t *);
+	struct mp_intr_map *mb_intrs;
+	u_int32_t mb_data;	/* random bus-specific datum. */
+};
+
+struct mp_intr_map
+{
+	struct mp_intr_map *next;
+	struct mp_bus *bus;
+	int bus_pin;
+	struct ioapic_softc *ioapic;
+	int ioapic_pin;
+	int ioapic_ih;		/* int handle, for apic_intr_est */
+	int type;		/* from mp spec intr record */
+ 	int flags;		/* from mp spec intr record */
+	u_int32_t redir;
+	int cpu_id;
+};
+
+#if defined(_KERNEL)
+extern int mp_verbose;
+extern struct mp_bus *mp_busses;
+extern struct mp_intr_map *mp_intrs;
+extern int mp_nintr;
+extern int mp_isa_bus, mp_eisa_bus;
+extern int mp_nbus;
+#endif
+#endif
+
+#endif /* _X86_MPCONFIG_H */
diff --git a/sys/arch/amd64/include/mtrr.h b/sys/arch/amd64/include/mtrr.h
new file mode 100644
index 00000000000..ab17926ecf5
--- /dev/null
+++ b/sys/arch/amd64/include/mtrr.h
@@ -0,0 +1,160 @@
+/*	$OpenBSD: mtrr.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/* $NetBSD: mtrr.h,v 1.1 2003/02/26 21:26:11 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_MTRR_H_
+#define _X86_MTRR_H_
+
+#define MTRR_I686_FIXED_IDX64K	0
+#define MTRR_I686_FIXED_IDX16K	1
+#define MTRR_I686_FIXED_IDX4K	3
+
+#define MTRR_I686_NVAR		8
+
+#define MTRR_I686_64K_START		0x00000
+#define MTRR_I686_16K_START		0x80000
+#define MTRR_I686_4K_START		0xc0000
+
+#define MTRR_I686_NFIXED_64K		1
+#define MTRR_I686_NFIXED_16K		2
+#define MTRR_I686_NFIXED_4K		8
+#define MTRR_I686_NFIXED		11
+#define MTRR_I686_NFIXED_SOFT_64K	(MTRR_I686_NFIXED_64K * 8)
+#define MTRR_I686_NFIXED_SOFT_16K	(MTRR_I686_NFIXED_16K * 8)
+#define MTRR_I686_NFIXED_SOFT_4K	(MTRR_I686_NFIXED_4K * 8)
+#define MTRR_I686_NFIXED_SOFT		(MTRR_I686_NFIXED * 8)
+
+#define MTRR_I686_ENABLE_MASK	0x0800
+#define MTRR_I686_FIXED_ENABLE_MASK	0x0400
+
+#define MTRR_I686_CAP_VCNT_MASK	0x00ff
+#define MTRR_I686_CAP_FIX_MASK	0x0100
+#define MTRR_I686_CAP_WC_MASK	0x0400
+
+#define MTRR_TYPE_UC		0
+#define MTRR_TYPE_WC		1
+#define MTRR_TYPE_UNDEF1	2
+#define MTRR_TYPE_UNDEF2	3
+#define MTRR_TYPE_WT		4
+#define MTRR_TYPE_WP		5
+#define MTRR_TYPE_WB		6
+
+struct mtrr_state {
+	uint32_t msraddr;
+	uint64_t msrval;
+};
+	
+#define MTRR_PRIVATE	0x0001		/* 'own' range, reset at exit */
+#define MTRR_FIXED	0x0002		/* use fixed range mtrr */
+#define MTRR_VALID	0x0004		/* entry is valid */
+
+#define MTRR_CANTSET	MTRR_FIXED
+
+#define MTRR_I686_MASK_VALID	(1 << 11)
+
+/*
+ * AMD K6 MTRRs.
+ *
+ * There are two of these MTRR-like registers in the UWCRR.
+ */
+
+#define	MTRR_K6_ADDR_SHIFT 17
+#define	MTRR_K6_ADDR	(0x7fffU << MTRR_K6_ADDR_SHIFT)
+#define	MTRR_K6_MASK_SHIFT 2
+#define	MTRR_K6_MASK	(0x7fffU << MTRR_K6_MASK_SHIFT)
+#define	MTRR_K6_WC	(1U << 1)	/* write-combine */
+#define	MTRR_K6_UC	(1U << 0)	/* uncached */
+
+#define	MTRR_K6_NVAR	2
+
+#ifdef _KERNEL
+
+#define mtrr_base_value(mtrrp) \
+    (((uint64_t)(mtrrp)->base) | ((uint64_t)(mtrrp)->type))
+#define mtrr_mask_value(mtrrp) \
+    ((~((mtrrp)->len - 1) & 0x0000000ffffff000))
+	
+
+#define mtrr_len(val) \
+    ((~((val) & 0x0000000ffffff000)+1) & 0x0000000ffffff000)
+#define mtrr_base(val)		((val) & 0x0000000ffffff000)
+#define mtrr_type(val)		((uint8_t)((val) & 0x00000000000000ff))
+#define mtrr_valid(val)		(((val) & MTRR_I686_MASK_VALID) != 0)
+
+struct proc;
+struct mtrr;
+
+void i686_mtrr_init_first(void);
+void k6_mtrr_init_first(void);
+
+struct mtrr_funcs {
+	void (*init_cpu)(struct cpu_info *ci);
+	void (*reload_cpu)(struct cpu_info *ci);
+	void (*clean)(struct proc *p);
+	int (*set)(struct mtrr *, int *n, struct proc *p, int flags);
+	int (*get)(struct mtrr *, int *n, struct proc *p, int flags);
+	void (*commit)(void);
+	void (*dump)(const char *tag);
+};
+
+extern struct mtrr_funcs i686_mtrr_funcs;
+extern struct mtrr_funcs k6_mtrr_funcs;
+extern struct mtrr_funcs *mtrr_funcs;
+
+#define mtrr_init_cpu(ci)	mtrr_funcs->init_cpu(ci)
+#define mtrr_reload_cpu(ci)	mtrr_funcs->reload_cpu(ci)
+#define mtrr_clean(p)		mtrr_funcs->clean(p)
+#define mtrr_set(mp,n,p,f)	mtrr_funcs->set(mp,n,p,f)
+#define mtrr_get(mp,n,p,f)	mtrr_funcs->get(mp,n,p,f)
+#define mtrr_dump(s)		mtrr_funcs->dump(s)
+#define mtrr_commit()		mtrr_funcs->commit()
+
+#define MTRR_GETSET_USER	0x0001
+#define MTRR_GETSET_KERNEL	0x0002
+
+#endif /* _KERNEL */
+
+struct mtrr {
+	uint64_t base;		/* physical base address */
+	uint64_t len;
+	uint8_t type;
+	int flags;
+	pid_t owner;		/* valid if MTRR_PRIVATE set in flags */
+};
+
+#endif /* _X86_MTRR_H_ */
diff --git a/sys/arch/amd64/include/param.h b/sys/arch/amd64/include/param.h
new file mode 100644
index 00000000000..7e3f512977f
--- /dev/null
+++ b/sys/arch/amd64/include/param.h
@@ -0,0 +1,173 @@
+/*	$OpenBSD: param.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)param.h     5.8 (Berkeley) 6/28/91
+ */
+
+#ifdef _KERNEL
+#ifdef _LOCORE
+#include <machine/psl.h>
+#else
+#include <machine/cpu.h>
+#endif
+#endif
+
+#define	_MACHINE	amd64
+#define	MACHINE		"amd64"
+#define	_MACHINE_ARCH	x86_64
+#define	MACHINE_ARCH	"x86_64"
+#define MID_MACHINE	MID_X86_64
+
+/*
+ * Round p (pointer or byte index) up to a correctly-aligned value
+ * for all data types (int, long, ...).   The result is u_long and
+ * must be cast to any desired pointer type.
+ *
+ * ALIGNED_POINTER is a boolean macro that checks whether an address
+ * is valid to fetch data elements of type t from on this architecture.
+ * This does not reflect the optimal alignment, just the possibility
+ * (within reasonable limits). 
+ *
+ */
+#define ALIGNBYTES		(sizeof(long) - 1)
+#define ALIGN(p)		(((u_long)(p) + ALIGNBYTES) &~ALIGNBYTES)
+#define ALIGNED_POINTER(p,t)	1
+
+#define	PGSHIFT		12		/* LOG2(NBPG) */
+#define	NBPG		(1 << PGSHIFT)	/* bytes/page */
+#define	PGOFSET		(NBPG-1)	/* byte offset into page */
+
+#define PAGE_SHIFT	12
+#define PAGE_SIZE	(1 << PAGE_SHIFT)
+#define PAGE_MASK	(PAGE_SIZE - 1)
+
+#define	NPTEPG		(NBPG/(sizeof (pt_entry_t)))
+
+#define	KERNBASE	0xffffffff80000000 /* start of kernel virtual space */
+#define KERNTEXTOFF	(KERNBASE+0x100000)	/* start of kernel text */
+#define	BTOPKERNBASE	((u_long)KERNBASE >> PGSHIFT)
+
+#define KERNTEXTOFF_HI	0xffffffff
+#define KERNTEXTOFF_LO	0x80100000
+
+#define KERNBASE_HI	0xffffffff
+#define KERNBASE_LO	0x80000000
+
+#define	DEV_BSHIFT	9		/* log2(DEV_BSIZE) */
+#define	DEV_BSIZE	(1 << DEV_BSHIFT)
+#define	BLKDEV_IOSIZE	2048
+#ifndef	MAXPHYS
+#define	MAXPHYS		(64 * 1024)	/* max raw I/O transfer size */
+#endif
+
+#define	SSIZE		1		/* initial stack size/NBPG */
+#define	SINCR		1		/* increment of stack/NBPG */
+#define	UPAGES		5		/* pages of u-area */
+#define	USPACE		(UPAGES * NBPG)	/* total size of u-area */
+
+#ifndef MSGBUFSIZE
+#define MSGBUFSIZE	4*NBPG		/* default message buffer size */
+#endif
+
+/*
+ * Constants related to network buffer management.
+ * MCLBYTES must be no larger than NBPG (the software page size), and,
+ * on machines that exchange pages of input or output buffers with mbuf
+ * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
+ * of the hardware page size.
+ */
+#define	MSIZE		256		/* size of an mbuf */
+#define	MCLSHIFT	11		/* convert bytes to m_buf clusters */
+#define	MCLBYTES	(1 << MCLSHIFT)	/* size of a m_buf cluster */
+#define MCLOFSET	(MCLBYTES - 1)	/* offset within a m_buf cluster */
+
+#ifndef NMBCLUSTERS
+#define	NMBCLUSTERS	2048		/* map size, max cluster allocation */
+#endif
+
+/*
+ * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized
+ * logical pages.
+ */
+#define	NKMEMPAGES_MIN_DEFAULT	((8 * 1024 * 1024) >> PAGE_SHIFT)
+#define	NKMEMPAGES_MAX_DEFAULT	((128 * 1024 * 1024) >> PAGE_SHIFT)
+
+/* pages ("clicks") to disk blocks */
+#define	ctod(x)		((x) << (PGSHIFT - DEV_BSHIFT))
+#define	dtoc(x)		((x) >> (PGSHIFT - DEV_BSHIFT))
+
+/* bytes to pages */
+#define	ctob(x)		((x) << PGSHIFT)
+#define	btoc(x)		(((x) + PGOFSET) >> PGSHIFT)
+
+/* bytes to disk blocks */
+#define	dbtob(x)	((x) << DEV_BSHIFT)
+#define	btodb(x)	((x) >> DEV_BSHIFT)
+
+/*
+ * Map a ``block device block'' to a file system block.
+ * This should be device dependent, and should use the bsize
+ * field from the disk label.
+ * For now though just use DEV_BSIZE.
+ */
+#define	bdbtofsb(bn)	((bn) / (BLKDEV_IOSIZE / DEV_BSIZE))
+
+/*
+ * XXXfvdl the PD* stuff is different from i386.
+ */
+/*
+ * Mach derived conversion macros
+ */
+#define	x86_round_pdr(x) \
+	((((unsigned long)(x)) + (NBPD_L2 - 1)) & ~(NBPD_L2 - 1))
+#define	x86_trunc_pdr(x)	((unsigned long)(x) & ~(NBPD_L2 - 1))
+#define	x86_btod(x)		((unsigned long)(x) >> L2_SHIFT)
+#define	x86_dtob(x)		((unsigned long)(x) << L2_SHIFT)
+#define	x86_round_page(x)	((((unsigned long)(x)) + PGOFSET) & ~PGOFSET)
+#define	x86_trunc_page(x)	((unsigned long)(x) & ~PGOFSET)
+#define	x86_btop(x)		((unsigned long)(x) >> PGSHIFT)
+#define	x86_ptob(x)		((unsigned long)(x) << PGSHIFT)
+
+#define btop(x)				x86_btop(x)
+#define ptob(x)				x86_ptob(x)
+#define round_pdr(x)			x86_round_pdr(x)
+
+/* XXX - oh, the horror.. Just for now. */
+#define KERNEL_PROC_LOCK(p)
+#define KERNEL_PROC_UNLOCK(p)
+#define KERNEL_LOCK(i)
+#define KERNEL_UNLOCK()
diff --git a/sys/arch/amd64/include/pcb.h b/sys/arch/amd64/include/pcb.h
new file mode 100644
index 00000000000..af95ea5aa9b
--- /dev/null
+++ b/sys/arch/amd64/include/pcb.h
@@ -0,0 +1,130 @@
+/*	$NetBSD: pcb.h,v 1.1 2003/04/26 18:39:45 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)pcb.h	5.10 (Berkeley) 5/12/91
+ */
+
+/*
+ * XXXfvdl these copyrights don't really match anymore
+ */
+
+#ifndef _AMD64_PCB_H_
+#define _AMD64_PCB_H_
+
+#include <sys/signal.h>
+
+#include <machine/segments.h>
+#include <machine/tss.h>
+#include <machine/fpu.h>
+#include <machine/sysarch.h>
+
+#define	NIOPORTS	1024		/* # of ports we allow to be mapped */
+
+/*
+ * Please note that the pcb_savefpu field in struct below must be
+ * on a 16-byte boundary.
+ */
+struct pcb {
+	/*
+	 * XXXfvdl
+	 * It's overkill to have a TSS here, as it's only needed
+	 * for compatibility processes who use an I/O permission map.
+	 * The pcb fields below are not in the TSS anymore (and there's
+	 * not enough room in the TSS to store them all)
+	 * Should just make this a pointer and allocate.
+	 */
+	struct	x86_64_tss pcb_tss;
+	u_int64_t pcb_cr3;
+	u_int64_t pcb_rsp;
+	u_int64_t pcb_rbp;
+	u_int64_t pcb_usersp;
+	u_int64_t pcb_ldt_sel;
+	struct	savefpu pcb_savefpu;	/* floating point state */
+	int	pcb_cr0;		/* saved image of CR0 */
+	int	pcb_flags;
+#define	PCB_USER_LDT	0x01		/* has user-set LDT */
+	caddr_t	pcb_onfault;		/* copyin/out fault recovery */
+	struct cpu_info *pcb_fpcpu;	/* cpu holding our fp state. */
+	unsigned pcb_iomap[NIOPORTS/32];	/* I/O bitmap */
+	struct pmap *pcb_pmap;		/* back pointer to our pmap */
+};
+
+/*    
+ * The pcb is augmented with machine-dependent additional data for 
+ * core dumps. For the i386, there is nothing to add.
+ */     
+struct md_coredump {
+	long	md_pad[8];
+};    
+
+#endif /* _AMD64_PCB_H_ */
diff --git a/sys/arch/amd64/include/pci_machdep.h b/sys/arch/amd64/include/pci_machdep.h
new file mode 100644
index 00000000000..e7852418297
--- /dev/null
+++ b/sys/arch/amd64/include/pci_machdep.h
@@ -0,0 +1,110 @@
+/*	$OpenBSD: pci_machdep.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: pci_machdep.h,v 1.1 2003/02/26 21:26:11 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
+ * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Charles M. Hannum.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-specific definitions for PCI autoconfiguration.
+ */
+
+/*
+ * i386-specific PCI structure and type definitions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ *
+ * Configuration tag; created from a {bus,device,function} triplet by
+ * pci_make_tag(), and passed to pci_conf_read() and pci_conf_write().
+ * We could instead always pass the {bus,device,function} triplet to
+ * the read and write routines, but this would cause extra overhead.
+ *
+ * Mode 2 is historical and deprecated by the Revision 2.0 specification.
+ */
+union x86_pci_tag_u {
+	u_int32_t mode1;
+	struct {
+		u_int16_t port;
+		u_int8_t enable;
+		u_int8_t forward;
+	} mode2;
+};
+
+extern struct x86_bus_dma_tag pci_bus_dma_tag;
+
+/*
+ * Types provided to machine-independent PCI code
+ */
+typedef void *pci_chipset_tag_t;
+typedef union x86_pci_tag_u pcitag_t;
+typedef int pci_intr_handle_t;
+
+/*
+ * i386-specific PCI variables and functions.
+ * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
+ */
+extern int pci_mode;
+int		pci_mode_detect(void);
+int		pci_bus_flags(void);
+struct		pci_attach_args;
+
+/*
+ * Functions provided to machine-independent PCI code.
+ */
+void		pci_attach_hook(struct device *, struct device *,
+		    struct pcibus_attach_args *);
+int		pci_bus_maxdevs(pci_chipset_tag_t, int);
+pcitag_t	pci_make_tag(pci_chipset_tag_t, int, int, int);
+void		pci_decompose_tag(pci_chipset_tag_t, pcitag_t,
+		    int *, int *, int *);
+pcireg_t	pci_conf_read(pci_chipset_tag_t, pcitag_t, int);
+void		pci_conf_write(pci_chipset_tag_t, pcitag_t, int,
+		    pcireg_t);
+int		pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
+const char	*pci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
+const struct evcnt *pci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
+void		*pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
+		    int, int (*)(void *), void *, char *);
+void		pci_intr_disestablish(pci_chipset_tag_t, void *);
+void		pci_decompose_tag(pci_chipset_tag_t, pcitag_t,
+		    int *, int *, int *);
+
+#define	pci_enumerate_bus(sc, m, p)					\
+	pci_enumerate_bus_generic((sc), (m), (p))
+
+/*
+ * ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED
+ * BY PORTABLE CODE.
+ */
+
+/*
+ * Section 6.2.4, `Miscellaneous Functions' of the PCI Specification,
+ * says that 255 means `unknown' or `no connection' to the interrupt
+ * controller on a PC.
+ */
+#define	X86_PCI_INTERRUPT_LINE_NO_CONNECTION	0xff
diff --git a/sys/arch/amd64/include/pic.h b/sys/arch/amd64/include/pic.h
new file mode 100644
index 00000000000..c9d9a5082a6
--- /dev/null
+++ b/sys/arch/amd64/include/pic.h
@@ -0,0 +1,40 @@
+/*	$OpenBSD: pic.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: pic.h,v 1.1 2003/02/26 21:26:11 fvdl Exp $	*/
+
+#ifndef _X86_PIC_H
+#define _X86_PIC_H
+
+#include <sys/device.h>
+#include <sys/lock.h>
+
+struct cpu_info;
+
+/* 
+ * Structure common to all PIC softcs
+ */
+struct pic {
+	struct device pic_dev;
+        int pic_type;
+	simple_lock_t pic_lock;
+        void (*pic_hwmask)(struct pic *, int);
+        void (*pic_hwunmask)(struct pic *, int);
+	void (*pic_addroute)(struct pic *, struct cpu_info *, int, int, int);
+	void (*pic_delroute)(struct pic *, struct cpu_info *, int, int, int);
+	struct intrstub *pic_level_stubs;
+	struct intrstub *pic_edge_stubs;
+};
+
+#define pic_name pic_dev.dv_xname
+
+/*
+ * PIC types.
+ */
+#define PIC_I8259	0
+#define PIC_IOAPIC	1
+#define PIC_LAPIC	2
+#define PIC_SOFT	3
+
+extern struct pic i8259_pic;
+extern struct pic local_pic;
+extern struct pic softintr_pic;
+#endif
diff --git a/sys/arch/amd64/include/pio.h b/sys/arch/amd64/include/pio.h
new file mode 100644
index 00000000000..9d54de16fc5
--- /dev/null
+++ b/sys/arch/amd64/include/pio.h
@@ -0,0 +1,232 @@
+/*	$OpenBSD: pio.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: pio.h,v 1.2 2003/02/27 11:22:46 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_PIO_H_
+#define _X86_PIO_H_
+
+/*
+ * Functions to provide access to x86 programmed I/O instructions.
+ *
+ * The in[bwl]() and out[bwl]() functions are split into two varieties: one to
+ * use a small, constant, 8-bit port number, and another to use a large or
+ * variable port number.  The former can be compiled as a smaller instruction.
+ */
+
+
+#ifdef __OPTIMIZE__
+
+#define	__use_immediate_port(port) \
+	(__builtin_constant_p((port)) && (port) < 0x100)
+
+#else
+
+#define	__use_immediate_port(port)	0
+
+#endif
+
+
+#define	inb(port) \
+    (/* CONSTCOND */ __use_immediate_port(port) ? __inbc(port) : __inb(port))
+
+static __inline u_int8_t
+__inbc(unsigned port)
+{
+	u_int8_t data;
+	__asm __volatile("inb %w1,%0" : "=a" (data) : "id" (port));
+	return data;
+}
+
+static __inline u_int8_t
+__inb(unsigned port)
+{
+	u_int8_t data;
+	__asm __volatile("inb %w1,%0" : "=a" (data) : "d" (port));
+	return data;
+}
+
+static __inline void
+insb(unsigned port, void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\tinsb"			:
+			 "=D" (dummy1), "=c" (dummy2) 		:
+			 "d" (port), "0" (addr), "1" (cnt)	:
+			 "memory");
+}
+
+#define	inw(port) \
+    (/* CONSTCOND */ __use_immediate_port(port) ? __inwc(port) : __inw(port))
+
+static __inline u_int16_t
+__inwc(unsigned port)
+{
+	u_int16_t data;
+	__asm __volatile("inw %w1,%0" : "=a" (data) : "id" (port));
+	return data;
+}
+
+static __inline u_int16_t
+__inw(unsigned port)
+{
+	u_int16_t data;
+	__asm __volatile("inw %w1,%0" : "=a" (data) : "d" (port));
+	return data;
+}
+
+static __inline void
+insw(unsigned port, void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\tinsw"			:
+			 "=D" (dummy1), "=c" (dummy2)		:
+			 "d" (port), "0" (addr), "1" (cnt)	:
+			 "memory");
+}
+
+#define	inl(port) \
+    (/* CONSTCOND */ __use_immediate_port(port) ? __inlc(port) : __inl(port))
+
+static __inline u_int32_t
+__inlc(unsigned port)
+{
+	u_int32_t data;
+	__asm __volatile("inl %w1,%0" : "=a" (data) : "id" (port));
+	return data;
+}
+
+static __inline u_int32_t
+__inl(unsigned port)
+{
+	u_int32_t data;
+	__asm __volatile("inl %w1,%0" : "=a" (data) : "d" (port));
+	return data;
+}
+
+static __inline void
+insl(unsigned port, void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\tinsl"			:
+			 "=D" (dummy1), "=c" (dummy2)		:
+			 "d" (port), "0" (addr), "1" (cnt)	:
+			 "memory");
+}
+
+#define	outb(port, data) \
+    (/* CONSTCOND */__use_immediate_port(port) ? __outbc(port, data) : \
+						__outb(port, data))
+
+static __inline void
+__outbc(unsigned port, u_int8_t data)
+{
+	__asm __volatile("outb %0,%w1" : : "a" (data), "id" (port));
+}
+
+static __inline void
+__outb(unsigned port, u_int8_t data)
+{
+	__asm __volatile("outb %0,%w1" : : "a" (data), "d" (port));
+}
+
+static __inline void
+outsb(unsigned port, const void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\toutsb"		:
+			 "=S" (dummy1), "=c" (dummy2)		:
+			 "d" (port), "0" (addr), "1" (cnt));
+}
+
+#define	outw(port, data) \
+    (/* CONSTCOND */ __use_immediate_port(port) ? __outwc(port, data) : \
+						__outw(port, data))
+
+static __inline void
+__outwc(unsigned port, u_int16_t data)
+{
+	__asm __volatile("outw %0,%w1" : : "a" (data), "id" (port));
+}
+
+static __inline void
+__outw(unsigned port, u_int16_t data)
+{
+	__asm __volatile("outw %0,%w1" : : "a" (data), "d" (port));
+}
+
+static __inline void
+outsw(unsigned port, const void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\toutsw"		:
+			 "=S" (dummy1), "=c" (dummy2)		:
+			 "d" (port), "0" (addr), "1" (cnt));
+}
+
+#define	outl(port, data) \
+    (/* CONSTCOND */ __use_immediate_port(port) ? __outlc(port, data) : \
+						__outl(port, data))
+
+static __inline void
+__outlc(unsigned port, u_int32_t data)
+{
+	__asm __volatile("outl %0,%w1" : : "a" (data), "id" (port));
+}
+
+static __inline void
+__outl(unsigned port, u_int32_t data)
+{
+	__asm __volatile("outl %0,%w1" : : "a" (data), "d" (port));
+}
+
+static __inline void
+outsl(unsigned port, const void *addr, int cnt)
+{
+	void *dummy1;
+	int dummy2;
+	__asm __volatile("cld\n\trepne\n\toutsl"		:
+			 "=S" (dummy1), "=c" (dummy2)		:
+			 "d" (port), "0" (addr), "1" (cnt));
+}
+
+#endif /* _X86_PIO_H_ */
diff --git a/sys/arch/amd64/include/pmap.h b/sys/arch/amd64/include/pmap.h
new file mode 100644
index 00000000000..a9366187930
--- /dev/null
+++ b/sys/arch/amd64/include/pmap.h
@@ -0,0 +1,592 @@
+/*	$OpenBSD: pmap.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: pmap.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $	*/
+
+/*
+ *
+ * Copyright (c) 1997 Charles D. Cranor and Washington University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgment:
+ *      This product includes software developed by Charles D. Cranor and
+ *      Washington University.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * pmap.h: see pmap.c for the history of this pmap module.
+ */
+
+#ifndef	_AMD64_PMAP_H_
+#define	_AMD64_PMAP_H_
+
+#ifndef _LOCORE
+#include <machine/cpufunc.h>
+#include <machine/pte.h>
+#include <machine/segments.h>
+#include <uvm/uvm_object.h>
+#endif
+
+/*
+ * The x86_64 pmap module closely resembles the i386 one. It uses
+ * the same recursive entry scheme, and the same alternate area
+ * trick for accessing non-current pmaps. See the i386 pmap.h
+ * for a description. The obvious difference is that 3 extra
+ * levels of page table need to be dealt with. The level 1 page
+ * table pages are at:
+ *
+ * l1: 0x00007f8000000000 - 0x00007fffffffffff     (39 bits, needs PML4 entry)
+ *
+ * The alternate space is at:
+ *
+ * l1: 0xffffff8000000000 - 0xffffffffffffffff     (39 bits, needs PML4 entry)
+ *
+ * The rest is kept as physical pages in 3 UVM objects, and is
+ * temporarily mapped for virtual access when needed.
+ *
+ * Note that address space is signed, so the layout for 48 bits is:
+ *
+ *  +---------------------------------+ 0xffffffffffffffff
+ *  |                                 |
+ *  |    alt.L1 table (PTE pages)     |
+ *  |                                 |
+ *  +---------------------------------+ 0xffffff8000000000
+ *  ~                                 ~
+ *  |                                 |
+ *  |         Kernel Space            |
+ *  |                                 |
+ *  |                                 |
+ *  +---------------------------------+ 0xffff800000000000 = 0x0000008000000000
+ *  |                                 |
+ *  |    alt.L1 table (PTE pages)     |
+ *  |                                 |
+ *  +---------------------------------+ 0x00007f8000000000
+ *  ~                                 ~
+ *  |                                 |
+ *  |         User Space              |
+ *  |                                 |
+ *  |                                 |
+ *  +---------------------------------+ 0x0000000000000000
+ *
+ * In other words, there is a 'VA hole' at 0x0000008000000000 -
+ * 0xffff800000000000 which will trap, just as on, for example,
+ * sparcv9.
+ *
+ * The unused space can be used if needed, but it adds a little more
+ * complexity to the calculations.
+ */
+
+/*
+ * The first generation of Hammer processors can use 48 bits of
+ * virtual memory, and 40 bits of physical memory. This will be
+ * more for later generations. These defines can be changed to
+ * variable names containing the # of bits, extracted from an
+ * extended cpuid instruction (variables are harder to use during
+ * bootstrap, though)
+ */
+#define VIRT_BITS	48
+#define PHYS_BITS	40
+
+/*
+ * Mask to get rid of the sign-extended part of addresses.
+ */
+#define VA_SIGN_MASK		0xffff000000000000
+#define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
+/*
+ * XXXfvdl this one's not right.
+ */
+#define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
+
+#define L4_SLOT_PTE		255
+#define L4_SLOT_KERN		256
+#define L4_SLOT_KERNBASE	511
+#define L4_SLOT_APTE		510
+
+#define PDIR_SLOT_KERN	L4_SLOT_KERN
+#define PDIR_SLOT_PTE	L4_SLOT_PTE
+#define PDIR_SLOT_APTE	L4_SLOT_APTE
+
+/*
+ * the following defines give the virtual addresses of various MMU
+ * data structures:
+ * PTE_BASE and APTE_BASE: the base VA of the linear PTE mappings
+ * PTD_BASE and APTD_BASE: the base VA of the recursive mapping of the PTD
+ * PDP_PDE and APDP_PDE: the VA of the PDE that points back to the PDP/APDP
+ *
+ */
+
+#define PTE_BASE  ((pt_entry_t *) (L4_SLOT_PTE * NBPD_L4))
+#define APTE_BASE ((pt_entry_t *) (VA_SIGN_NEG((L4_SLOT_APTE * NBPD_L4))))
+
+#define L1_BASE		PTE_BASE
+#define AL1_BASE	APTE_BASE
+
+#define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
+#define L3_BASE ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
+#define L4_BASE ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
+
+#define AL2_BASE ((pd_entry_t *)((char *)AL1_BASE + L4_SLOT_PTE * NBPD_L3))
+#define AL3_BASE ((pd_entry_t *)((char *)AL2_BASE + L4_SLOT_PTE * NBPD_L2))
+#define AL4_BASE ((pd_entry_t *)((char *)AL3_BASE + L4_SLOT_PTE * NBPD_L1))
+
+#define PDP_PDE		(L4_BASE + PDIR_SLOT_PTE)
+#define APDP_PDE	(L4_BASE + PDIR_SLOT_APTE)
+
+#define PDP_BASE	L4_BASE
+#define APDP_BASE	AL4_BASE
+
+#define NKL4_MAX_ENTRIES	(unsigned long)1
+#define NKL3_MAX_ENTRIES	(unsigned long)(NKL4_MAX_ENTRIES * 512)
+#define NKL2_MAX_ENTRIES	(unsigned long)(NKL3_MAX_ENTRIES * 512)
+#define NKL1_MAX_ENTRIES	(unsigned long)(NKL2_MAX_ENTRIES * 512)
+
+#define NKL4_KIMG_ENTRIES	1
+#define NKL3_KIMG_ENTRIES	1
+#define NKL2_KIMG_ENTRIES	8
+
+/*
+ * Since kva space is below the kernel in its entirety, we start off
+ * with zero entries on each level.
+ */
+#define NKL4_START_ENTRIES	0
+#define NKL3_START_ENTRIES	0
+#define NKL2_START_ENTRIES	0
+#define NKL1_START_ENTRIES	0	/* XXX */
+
+#define NTOPLEVEL_PDES		(PAGE_SIZE / (sizeof (pd_entry_t)))
+
+#define KERNSPACE		(NKL4_ENTRIES * NBPD_L4)
+
+#define NPDPG			(PAGE_SIZE / sizeof (pd_entry_t))
+
+#define ptei(VA)	(((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
+
+/*
+ * pl*_pi: index in the ptp page for a pde mapping a VA.
+ * (pl*_i below is the index in the virtual array of all pdes per level)
+ */
+#define pl1_pi(VA)	(((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
+#define pl2_pi(VA)	(((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT)
+#define pl3_pi(VA)	(((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT)
+#define pl4_pi(VA)	(((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT)
+
+/*
+ * pl*_i: generate index into pde/pte arrays in virtual space
+ */
+#define pl1_i(VA)	(((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
+#define pl2_i(VA)	(((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
+#define pl3_i(VA)	(((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
+#define pl4_i(VA)	(((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
+#define pl_i(va, lvl) \
+        (((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1])
+
+#define PTP_MASK_INITIALIZER	{ L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME }
+#define PTP_SHIFT_INITIALIZER	{ L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT }
+#define NKPTP_INITIALIZER	{ NKL1_START_ENTRIES, NKL2_START_ENTRIES, \
+				  NKL3_START_ENTRIES, NKL4_START_ENTRIES }
+#define NKPTPMAX_INITIALIZER	{ NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \
+				  NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES }
+#define NBPD_INITIALIZER	{ NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 }
+#define PDES_INITIALIZER	{ L2_BASE, L3_BASE, L4_BASE }
+#define APDES_INITIALIZER	{ AL2_BASE, AL3_BASE, AL4_BASE }
+
+/*
+ * PTP macros:
+ *   a PTP's index is the PD index of the PDE that points to it
+ *   a PTP's offset is the byte-offset in the PTE space that this PTP is at
+ *   a PTP's VA is the first VA mapped by that PTP
+ *
+ * note that PAGE_SIZE == number of bytes in a PTP (4096 bytes == 1024 entries)
+ *           NBPD == number of bytes a PTP can map (4MB)
+ */
+
+#define ptp_va2o(va, lvl)	(pl_i(va, (lvl)+1) * PAGE_SIZE)
+
+#define PTP_LEVELS	4
+
+/*
+ * PG_AVAIL usage: we make use of the ignored bits of the PTE
+ */
+
+#define PG_W		PG_AVAIL1	/* "wired" mapping */
+#define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
+/* PG_AVAIL3 not used */
+
+/*
+ * Number of PTE's per cache line.  8 byte pte, 64-byte cache line
+ * Used to avoid false sharing of cache lines.
+ */
+#define NPTECL		8
+
+
+#if defined(_KERNEL) && !defined(_LOCORE)
+/*
+ * pmap data structures: see pmap.c for details of locking.
+ */
+
+struct pmap;
+typedef struct pmap *pmap_t;
+
+/*
+ * we maintain a list of all non-kernel pmaps
+ */
+
+LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */
+
+/*
+ * the pmap structure
+ *
+ * note that the pm_obj contains the simple_lock, the reference count,
+ * page list, and number of PTPs within the pmap.
+ *
+ * pm_lock is the same as the spinlock for vm object 0. Changes to
+ * the other objects may only be made if that lock has been taken
+ * (the other object locks are only used when uvm_pagealloc is called)
+ */
+
+struct pmap {
+	struct uvm_object pm_obj[PTP_LEVELS-1]; /* objects for lvl >= 1) */
+#define	pm_lock	pm_obj[0].vmobjlock
+#define pm_obj_l1 pm_obj[0]
+#define pm_obj_l2 pm_obj[1]
+#define pm_obj_l3 pm_obj[2]
+	LIST_ENTRY(pmap) pm_list;	/* list (lck by pm_list lock) */
+	pd_entry_t *pm_pdir;		/* VA of PD (lck by object lock) */
+	paddr_t pm_pdirpa;		/* PA of PD (read-only after create) */
+	struct vm_page *pm_ptphint[PTP_LEVELS-1];
+					/* pointer to a PTP in our pmap */
+	struct pmap_statistics pm_stats;  /* pmap stats (lck by object lock) */
+
+	int pm_flags;			/* see below */
+
+	union descriptor *pm_ldt;	/* user-set LDT */
+	int pm_ldt_len;			/* number of LDT entries */
+	int pm_ldt_sel;			/* LDT selector */
+	u_int32_t pm_cpus;		/* mask of CPUs using pmap */
+};
+
+/* pm_flags */
+#define	PMF_USER_LDT	0x01	/* pmap has user-set LDT */
+
+/*
+ * for each managed physical page we maintain a list of <PMAP,VA>'s
+ * which it is mapped at.  the list is headed by a pv_head structure.
+ * there is one pv_head per managed phys page (allocated at boot time).
+ * the pv_head structure points to a list of pv_entry structures (each
+ * describes one mapping).
+ */
+
+struct pv_entry;
+
+struct pv_head {
+	struct simplelock pvh_lock;	/* locks every pv on this list */
+	struct pv_entry *pvh_list;	/* head of list (locked by pvh_lock) */
+};
+
+struct pv_entry {			/* locked by its list's pvh_lock */
+	struct pv_entry *pv_next;	/* next entry */
+	struct pmap *pv_pmap;		/* the pmap */
+	vaddr_t pv_va;			/* the virtual address */
+	struct vm_page *pv_ptp;		/* the vm_page of the PTP */
+};
+
+/*
+ * pv_entrys are dynamically allocated in chunks from a single page.
+ * we keep track of how many pv_entrys are in use for each page and
+ * we can free pv_entry pages if needed.  there is one lock for the
+ * entire allocation system.
+ */
+
+struct pv_page_info {
+	TAILQ_ENTRY(pv_page) pvpi_list;
+	struct pv_entry *pvpi_pvfree;
+	int pvpi_nfree;
+};
+
+/*
+ * number of pv_entry's in a pv_page
+ * (note: won't work on systems where NPBG isn't a constant)
+ */
+
+#define PVE_PER_PVPAGE ((PAGE_SIZE - sizeof(struct pv_page_info)) / \
+			sizeof(struct pv_entry))
+
+/*
+ * a pv_page: where pv_entrys are allocated from
+ */
+
+struct pv_page {
+	struct pv_page_info pvinfo;
+	struct pv_entry pvents[PVE_PER_PVPAGE];
+};
+
+/*
+ * pmap_remove_record: a record of VAs that have been unmapped, used to
+ * flush TLB.  if we have more than PMAP_RR_MAX then we stop recording.
+ */
+
+#define PMAP_RR_MAX	16	/* max of 16 pages (64K) */
+
+struct pmap_remove_record {
+	int prr_npages;
+	vaddr_t prr_vas[PMAP_RR_MAX];
+};
+
+/*
+ * global kernel variables
+ */
+
+/* PTDpaddr: is the physical address of the kernel's PDP */
+extern u_long PTDpaddr;
+
+extern struct pmap kernel_pmap_store;	/* kernel pmap */
+extern int pmap_pg_g;			/* do we support PG_G? */
+
+extern paddr_t ptp_masks[];
+extern int ptp_shifts[];
+extern long nkptp[], nbpd[], nkptpmax[];
+extern pd_entry_t *pdes[];
+
+/*
+ * macros
+ */
+
+#define	pmap_kernel()			(&kernel_pmap_store)
+#define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
+#define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
+#define	pmap_update(pmap)		/* nothing (yet) */
+
+#define pmap_clear_modify(pg)		pmap_clear_attrs(pg, PG_M)
+#define pmap_clear_reference(pg)	pmap_clear_attrs(pg, PG_U)
+#define pmap_copy(DP,SP,D,L,S)		
+#define pmap_is_modified(pg)		pmap_test_attrs(pg, PG_M)
+#define pmap_is_referenced(pg)		pmap_test_attrs(pg, PG_U)
+#define pmap_move(DP,SP,D,L,S)		
+#define pmap_phys_address(ppn)		ptob(ppn)
+#define pmap_valid_entry(E) 		((E) & PG_V) /* is PDE or PTE valid? */
+
+
+/*
+ * prototypes
+ */
+
+void		pmap_bootstrap(vaddr_t);
+boolean_t	pmap_clear_attrs(struct vm_page *, unsigned);
+static void	pmap_page_protect(struct vm_page *, vm_prot_t);
+void		pmap_page_remove (struct vm_page *);
+static void	pmap_protect(struct pmap *, vaddr_t,
+				vaddr_t, vm_prot_t);
+void		pmap_remove(struct pmap *, vaddr_t, vaddr_t);
+boolean_t	pmap_test_attrs(struct vm_page *, unsigned);
+static void	pmap_update_pg(vaddr_t);
+static void	pmap_update_2pg(vaddr_t,vaddr_t);
+void		pmap_write_protect(struct pmap *, vaddr_t,
+				vaddr_t, vm_prot_t);
+
+vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
+
+void	pmap_tlb_shootdown(pmap_t, vaddr_t, pt_entry_t, int32_t *);
+void	pmap_tlb_shootnow(int32_t);
+void	pmap_do_tlb_shootdown(struct cpu_info *);
+void	pmap_prealloc_lowmem_ptps(void);
+
+#define PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
+
+/*
+ * Do idle page zero'ing uncached to avoid polluting the cache.
+ */
+boolean_t	pmap_pageidlezero(struct vm_page *);
+#define	PMAP_PAGEIDLEZERO(pg)	pmap_pageidlezero((pg))
+
+/*
+ * inline functions
+ */
+
+static __inline void
+pmap_remove_all(struct pmap *pmap)
+{
+	/* Nothing. */
+}
+
+/*
+ * pmap_update_pg: flush one page from the TLB (or flush the whole thing
+ *	if hardware doesn't support one-page flushing)
+ */
+
+__inline static void
+pmap_update_pg(va)
+	vaddr_t va;
+{
+	invlpg(va);
+}
+
+/*
+ * pmap_update_2pg: flush two pages from the TLB
+ */
+
+__inline static void
+pmap_update_2pg(va, vb)
+	vaddr_t va, vb;
+{
+	invlpg(va);
+	invlpg(vb);
+}
+
+/*
+ * pmap_page_protect: change the protection of all recorded mappings
+ *	of a managed page
+ *
+ * => this function is a frontend for pmap_page_remove/pmap_clear_attrs
+ * => we only have to worry about making the page more protected.
+ *	unprotecting a page is done on-demand at fault time.
+ */
+
+__inline static void
+pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
+{
+	if ((prot & VM_PROT_WRITE) == 0) {
+		if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
+			(void) pmap_clear_attrs(pg, PG_RW);
+		} else {
+			pmap_page_remove(pg);
+		}
+	}
+}
+
+/*
+ * pmap_protect: change the protection of pages in a pmap
+ *
+ * => this function is a frontend for pmap_remove/pmap_write_protect
+ * => we only have to worry about making the page more protected.
+ *	unprotecting a page is done on-demand at fault time.
+ */
+
+__inline static void
+pmap_protect(pmap, sva, eva, prot)
+	struct pmap *pmap;
+	vaddr_t sva, eva;
+	vm_prot_t prot;
+{
+	if ((prot & VM_PROT_WRITE) == 0) {
+		if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
+			pmap_write_protect(pmap, sva, eva, prot);
+		} else {
+			pmap_remove(pmap, sva, eva);
+		}
+	}
+}
+
+/*
+ * various address inlines
+ *
+ *  vtopte: return a pointer to the PTE mapping a VA, works only for
+ *  user and PT addresses
+ *
+ *  kvtopte: return a pointer to the PTE mapping a kernel VA
+ */
+
+#include <lib/libkern/libkern.h>
+
+static __inline pt_entry_t *
+vtopte(vaddr_t va)
+{
+
+	KASSERT(va < (L4_SLOT_KERN * NBPD_L4));
+
+	return (PTE_BASE + pl1_i(va));
+}
+
+static __inline pt_entry_t *
+kvtopte(vaddr_t va)
+{
+
+	KASSERT(va >= (L4_SLOT_KERN * NBPD_L4));
+
+#ifdef LARGEPAGES
+	{
+		pd_entry_t *pde;
+
+		pde = L1_BASE + pl2_i(va);
+		if (*pde & PG_PS)
+			return ((pt_entry_t *)pde);
+	}
+#endif
+
+	return (PTE_BASE + pl1_i(va));
+}
+
+#define pmap_pte_set(p, n)		x86_atomic_testset_u64(p, n)
+#define pmap_pte_clearbits(p, b)	x86_atomic_clearbits_u64(p, b)
+#define pmap_cpu_has_pg_n()		(1)
+#define pmap_cpu_has_invlpg		(1)
+
+paddr_t vtophys(vaddr_t);
+vaddr_t	pmap_map(vaddr_t, paddr_t, paddr_t, vm_prot_t);
+
+#if 0   /* XXXfvdl was USER_LDT, need to check if that can be supported */
+void	pmap_ldt_cleanup(struct proc *);
+#define	PMAP_FORK
+#endif /* USER_LDT */
+
+/* 
+ * Hooks for the pool allocator.
+ */
+/* #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va)) */
+
+#endif /* _KERNEL && !_LOCORE */
+#endif	/* _AMD64_PMAP_H_ */
diff --git a/sys/arch/amd64/include/proc.h b/sys/arch/amd64/include/proc.h
new file mode 100644
index 00000000000..89e8360b954
--- /dev/null
+++ b/sys/arch/amd64/include/proc.h
@@ -0,0 +1,63 @@
+/*	$OpenBSD: proc.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: proc.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 1991 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)proc.h	7.1 (Berkeley) 5/15/91
+ */
+
+#ifndef _AMD64_PROC_H
+#define _AMD64_PROC_H
+
+#include <machine/frame.h>
+
+/*
+ * Machine-dependent part of the proc structure for amd64.
+ */
+struct mdproc {
+	struct	trapframe *md_regs;	/* registers on current frame */
+	int	md_tss_sel;		/* TSS selector */
+	int	md_flags;
+					/* Syscall handling function */
+	void	(*md_syscall)(struct trapframe);
+	__volatile int md_astpending;
+};
+
+/* md_flags */
+#define	MDP_USEDFPU	0x0001	/* has used the FPU */
+#define MDP_COMPAT	0x0002	/* x86 compatibility process */
+#define MDP_SYSCALL	0x0004	/* entered kernel via syscall ins */
+#define MDP_USEDMTRR	0x0008	/* has set volatile MTRRs */
+#define MDP_IRET	0x0010	/* return via iret, not sysret */
+
+#endif /* _AMD64_PROC_H */
diff --git a/sys/arch/amd64/include/profile.h b/sys/arch/amd64/include/profile.h
new file mode 100644
index 00000000000..5d928249a31
--- /dev/null
+++ b/sys/arch/amd64/include/profile.h
@@ -0,0 +1,65 @@
+/*	$OpenBSD: profile.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: profile.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)profile.h	8.1 (Berkeley) 6/11/93
+ */
+
+#define	_MCOUNT_DECL static __inline void _mcount
+
+#define MCOUNT_ENTRY	"mcount"
+
+/*
+ * XXXfvdl this is screwed by -fomit-frame-pointer being included in
+ * -O.
+ */
+#define	MCOUNT \
+extern void mcount __P((void)) __asm__(MCOUNT_ENTRY);			\
+void									\
+mcount()								\
+{									\
+	_mcount((u_long)__builtin_return_address(1),			\
+		(u_long)__builtin_return_address(0)); 			\
+}
+
+
+#ifdef _KERNEL
+/*
+ * Note that we assume splhigh() and splx() cannot call mcount()
+ * recursively.
+ */
+#define	MCOUNT_ENTER	s = splhigh()
+#define	MCOUNT_EXIT	splx(s)
+#endif /* _KERNEL */
+
diff --git a/sys/arch/amd64/include/psl.h b/sys/arch/amd64/include/psl.h
new file mode 100644
index 00000000000..689c507c487
--- /dev/null
+++ b/sys/arch/amd64/include/psl.h
@@ -0,0 +1,87 @@
+/*	$OpenBSD: psl.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: psl.h,v 1.1 2003/02/26 21:26:11 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)psl.h	5.2 (Berkeley) 1/18/91
+ */
+
+#ifndef _X86_PSL_H_
+#define _X86_PSL_H_
+
+/*
+ * 386 processor status longword.
+ */
+#define	PSL_C		0x00000001	/* carry flag */
+#define	PSL_PF		0x00000004	/* parity flag */
+#define	PSL_AF		0x00000010	/* auxiliary carry flag */
+#define	PSL_Z		0x00000040	/* zero flag */
+#define	PSL_N		0x00000080	/* sign flag */
+#define	PSL_T		0x00000100	/* trap flag */
+#define	PSL_I		0x00000200	/* interrupt enable flag */
+#define	PSL_D		0x00000400	/* direction flag */
+#define	PSL_V		0x00000800	/* overflow flag */
+#define	PSL_IOPL	0x00003000	/* i/o privilege level */
+#define	PSL_NT		0x00004000	/* nested task */
+#define	PSL_RF		0x00010000	/* resume flag */
+#define	PSL_VM		0x00020000	/* virtual 8086 mode */
+#define	PSL_AC		0x00040000	/* alignment check flag */
+#define	PSL_VIF		0x00080000	/* virtual interrupt enable flag */
+#define	PSL_VIP		0x00100000	/* virtual interrupt pending flag */
+#define	PSL_ID		0x00200000	/* identification flag */
+
+#define	PSL_MBO		0x00000002	/* must be one bits */
+#define	PSL_MBZ		0xffc08028	/* must be zero bits */
+
+#define	PSL_USERSET	(PSL_MBO | PSL_I)
+#if defined(_KERNEL_OPT)
+#include "opt_vm86.h"
+#endif
+#ifdef VM86
+#define	PSL_USERSTATIC	(PSL_MBO | PSL_MBZ | PSL_I | PSL_IOPL | PSL_NT | PSL_VIF | PSL_VIP)
+#else
+#define	PSL_USERSTATIC	(PSL_MBO | PSL_MBZ | PSL_I | PSL_IOPL | PSL_NT | PSL_VM | PSL_VIF | PSL_VIP)
+#endif
+#define PSL_USER (PSL_C | PSL_MBO | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
+
+/*
+ * ???
+ */
+#ifdef _KERNEL
+#include <machine/intr.h>
+#endif
+
+#endif /* !_X86_PSL_H_ */
diff --git a/sys/arch/amd64/include/pte.h b/sys/arch/amd64/include/pte.h
new file mode 100644
index 00000000000..eaa883d3f6f
--- /dev/null
+++ b/sys/arch/amd64/include/pte.h
@@ -0,0 +1,137 @@
+/*	$OpenBSD: pte.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: pte.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AMD64_PTE_H_
+#define _AMD64_PTE_H_
+
+/*
+ * amd64 MMU hardware structure:
+ *
+ * the (first generation) amd64 MMU is a 4-level MMU which maps 2^48 bytes
+ * of  virtual memory. The  pagesize we use is is 4K (4096 [0x1000] bytes), 
+ * although 2M and 4M can be used as well. The indexes in the levels
+ * are 9 bits wide (512 64bit entries per level), dividing the bits
+ * 9-9-9-9-12.
+ *
+ * The top level table, called PML4, contains 512 64bit entries pointing
+ * to 3rd level table. The 3rd level table is called the 'page directory
+ * pointers directory' and has 512 entries pointing to page directories.
+ * The 2nd level is the page directory, containing 512 pointers to
+ * page table pages. Lastly, level 1 consists of pages containing 512
+ * PTEs.
+ *
+ * Simply put, levels 4-1 all consist of pages containing 512
+ * entries pointing to the next level. Level 0 is the actual PTEs
+ * themselves.
+ *
+ * For a description on the other bits, which are i386 compatible,
+ * see the i386 pte.h
+ */
+
+#if !defined(_LOCORE)
+
+/*
+ * here we define the data types for PDEs and PTEs
+ */
+
+typedef u_int64_t pd_entry_t;		/* PDE */
+typedef u_int64_t pt_entry_t;		/* PTE */
+
+#endif
+
+/*
+ * now we define various for playing with virtual addresses
+ */
+
+#define L1_SHIFT	12
+#define	L2_SHIFT	21
+#define	L3_SHIFT	30
+#define	L4_SHIFT	39
+#define	NBPD_L1		(1ULL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
+#define	NBPD_L2		(1ULL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
+#define	NBPD_L3		(1ULL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
+#define	NBPD_L4		(1ULL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
+
+#define L4_MASK		0x0000ff8000000000
+#define L3_MASK		0x0000007fc0000000
+#define L2_MASK		0x000000003fe00000
+#define L1_MASK		0x00000000001ff000
+
+#define L4_FRAME	L4_MASK
+#define L3_FRAME	(L4_FRAME|L3_MASK)
+#define L2_FRAME	(L3_FRAME|L2_MASK)
+#define L1_FRAME	(L2_FRAME|L1_MASK)
+
+/*
+ * PDE/PTE bits. These are no different from their i386 counterparts.
+ */
+
+#define	PG_V		0x0000000000000001	/* valid */
+#define	PG_RO		0x0000000000000000	/* read-only */
+#define	PG_RW		0x0000000000000002	/* read-write */
+#define	PG_u		0x0000000000000004	/* user accessible */
+#define	PG_PROT		0x0000000000000006
+#define	PG_N		0x0000000000000018	/* non-cacheable */
+#define	PG_U		0x0000000000000020	/* used */
+#define	PG_M		0x0000000000000040	/* modified */
+#define PG_PS		0x0000000000000080	/* 2MB page size */
+#define PG_G		0x0000000000000100	/* not flushed */
+#define PG_AVAIL1	0x0000000000000200
+#define PG_AVAIL2	0x0000000000000400
+#define PG_AVAIL3	0x0000000000000800
+#define PG_NX		0x8000000000000000	/* non-executable */
+#define	PG_FRAME	0xfffffffffffff000
+
+#define	PG_LGFRAME	0xffffffffffc00000	/* large (2M) page frame mask */
+
+/*
+ * short forms of protection codes
+ */
+
+#define	PG_KR		0x0000000000000000	/* kernel read-only */
+#define	PG_KW		0x0000000000000002	/* kernel read-write */
+
+/*
+ * page protection exception bits
+ */
+
+#define PGEX_P		0x01	/* protection violation (vs. no mapping) */
+#define PGEX_W		0x02	/* exception during a write cycle */
+#define PGEX_U		0x04	/* exception while in user mode (upl) */
+
+#endif /* _AMD64_PTE_H_ */
diff --git a/sys/arch/amd64/include/ptrace.h b/sys/arch/amd64/include/ptrace.h
new file mode 100644
index 00000000000..27c0bf29c1d
--- /dev/null
+++ b/sys/arch/amd64/include/ptrace.h
@@ -0,0 +1,41 @@
+/*	$OpenBSD: ptrace.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 1993 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Christopher G. Demetriou.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * i386-dependent ptrace definitions
+ */
+#define	PT_STEP		(PT_FIRSTMACH + 0)
+#define	PT_GETREGS	(PT_FIRSTMACH + 1)
+#define	PT_SETREGS	(PT_FIRSTMACH + 2)
+#define	PT_GETFPREGS	(PT_FIRSTMACH + 3)
+#define	PT_SETFPREGS	(PT_FIRSTMACH + 4)
diff --git a/sys/arch/amd64/include/reg.h b/sys/arch/amd64/include/reg.h
new file mode 100644
index 00000000000..f594a44c6fc
--- /dev/null
+++ b/sys/arch/amd64/include/reg.h
@@ -0,0 +1,102 @@
+/*	$OpenBSD: reg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: reg.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)reg.h	5.5 (Berkeley) 1/18/91
+ */
+
+#ifndef _AMD64_REG_H_
+#define _AMD64_REG_H_
+
+#include <machine/mcontext.h>
+#include <machine/fpu.h>
+
+/*
+ * XXX
+ * The #defines aren't used in the kernel, but some user-level code still
+ * expects them.
+ */
+
+/* When referenced during a trap/exception, registers are at these offsets */
+
+#define tR15	0
+#define tR14	1
+#define tR13	2
+#define tR12	3
+#define tR11	4
+#define tR10	5
+#define tR9	6
+#define tR8	7
+#define	tRDI	8
+#define	tRSI	9
+#define	tRBP	10
+#define	tRBX	11
+#define	tRDX	12
+#define	tRCX	13
+#define	tRAX	14
+
+#define	tRIP	17
+#define	tCS	18
+#define	tRFLAGS	19
+#define	tRSP	20
+#define	tSS	21
+
+/*
+ * Registers accessible to ptrace(2) syscall for debugger use.
+ * Same as mcontext.__gregs and struct trapframe, they must
+ * remain synced (XXX should use common structure).
+ */
+struct reg {
+	long	regs[_NGREG];
+};
+
+struct fpreg {
+	struct fxsave64 fxstate;
+};
+
+#define fp_fcw		fxstate.fx_fcw
+#define fp_fsw		fxstate.fx_fsw
+#define fp_ftw		fxstate.fx_ftw
+#define fp_fop		fxstate.fx_fop
+#define fp_rip		fxstate.fx_rip
+#define fp_rdp		fxstate.fx_rdp
+#define fp_mxcsr	fxstate.fx_mxcsr
+#define fp_mxcsr_mask	fxstate.fx_mxcsr_mask
+#define fp_st		fxstate.fx_st
+#define fp_xmm		fxstate.fx_xmm
+
+#endif /* !_AMD64_REG_H_ */
diff --git a/sys/arch/amd64/include/segments.h b/sys/arch/amd64/include/segments.h
new file mode 100644
index 00000000000..636f3a38fee
--- /dev/null
+++ b/sys/arch/amd64/include/segments.h
@@ -0,0 +1,305 @@
+/*	$OpenBSD: segments.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: segments.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1995, 1997
+ *	Charles M. Hannum.  All rights reserved.
+ * Copyright (c) 1989, 1990 William F. Jolitz
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)segments.h	7.1 (Berkeley) 5/9/91
+ */
+
+/*
+ * Adapted for NetBSD/amd64 by fvdl@wasabisystems.com.
+ */
+
+/*
+ * 386 Segmentation Data Structures and definitions
+ *	William F. Jolitz (william@ernie.berkeley.edu) 6/20/1989
+ */
+
+#ifndef _AMD64_SEGMENTS_H_
+#define _AMD64_SEGMENTS_H_
+
+/*
+ * Selectors
+ */
+
+#define	ISPL(s)		((s) & SEL_RPL)	/* what is the priority level of a selector */
+#define	SEL_KPL		0		/* kernel privilege level */	
+#define	SEL_UPL		3		/* user privilege level */	
+#define	SEL_RPL		3		/* requester's privilege level mask */
+#define	ISLDT(s)	((s) & SEL_LDT)	/* is it local or global */
+#define	SEL_LDT		4		/* local descriptor table */	
+
+/* Dynamically allocated TSSs and LDTs start (byte offset) */
+#define SYSSEL_START	(NGDT_MEM << 3)
+#define DYNSEL_START	(SYSSEL_START + (NGDT_SYS << 4))
+
+/*
+ * These define the index not from the start of the GDT, but from
+ * the part of the GDT that they're allocated from.
+ * First NGDT_MEM entries are 8-byte descriptors for CS and DS.
+ * Next NGDT_SYS entries are 16-byte descriptors defining LDTs.
+ *
+ * The rest is 16-byte descriptors for TSS and LDT.
+ */
+
+#define	IDXSEL(s)	(((s) >> 3) & 0x1fff)
+#define IDXDYNSEL(s)	((((s) & ~SEL_RPL) - DYNSEL_START) >> 4)
+
+#define	GSEL(s,r)	(((s) << 3) | r)
+#define	GSYSSEL(s,r)	((((s) << 4) + SYSSEL_START) | r)
+#define GDYNSEL(s,r)	((((s) << 4) + DYNSEL_START) | r | SEL_KPL)
+
+#define LSEL(s,r)	((s) | r | SEL_LDT)
+
+#define	USERMODE(c, f)		(ISPL(c) == SEL_UPL)
+#define	KERNELMODE(c, f)	(ISPL(c) == SEL_KPL)
+
+#ifndef _LOCORE
+
+/*
+ * Memory and System segment descriptors
+ */
+
+/*
+ * Below is used for TSS and LDT.
+ */
+struct sys_segment_descriptor {
+/*BITFIELDTYPE*/ u_int64_t sd_lolimit:16;/* segment extent (lsb) */
+/*BITFIELDTYPE*/ u_int64_t sd_lobase:24;/* segment base address (lsb) */
+/*BITFIELDTYPE*/ u_int64_t sd_type:5;	/* segment type */
+/*BITFIELDTYPE*/ u_int64_t sd_dpl:2;	/* segment descriptor priority level */
+/*BITFIELDTYPE*/ u_int64_t sd_p:1;	/* segment descriptor present */
+/*BITFIELDTYPE*/ u_int64_t sd_hilimit:4;/* segment extent (msb) */
+/*BITFIELDTYPE*/ u_int64_t sd_xx1:3;	/* avl, long and def32 (not used) */
+/*BITFIELDTYPE*/ u_int64_t sd_gran:1;	/* limit granularity (byte/page) */
+/*BITFIELDTYPE*/ u_int64_t sd_hibase:40;/* segment base address (msb) */
+/*BITFIELDTYPE*/ u_int64_t sd_xx2:8;	/* reserved */
+/*BITFIELDTYPE*/ u_int64_t sd_zero:5;	/* must be zero */
+/*BITFIELDTYPE*/ u_int64_t sd_xx3:19;	/* reserved */
+} __attribute__((packed));
+
+/*
+ * Below is used for cs, ds, etc.
+ */
+struct mem_segment_descriptor {
+	unsigned sd_lolimit:16;         /* segment extent (lsb) */
+	unsigned sd_lobase:24;          /* segment base address (lsb) */
+	unsigned sd_type:5;             /* segment type */
+	unsigned sd_dpl:2;              /* segment descriptor priority level */
+	unsigned sd_p:1;                /* segment descriptor present */
+	unsigned sd_hilimit:4;          /* segment extent (msb) */
+	unsigned sd_avl:1;		/* available */
+	unsigned sd_long:1;		/* long mode */
+	unsigned sd_def32:1;            /* default 32 vs 16 bit size */
+	unsigned sd_gran:1;             /* limit granularity (byte/page) */
+	unsigned sd_hibase:8;           /* segment base address (msb) */
+} __attribute__((packed));
+
+/*
+ * Gate descriptors (e.g. indirect descriptors)
+ */
+struct gate_descriptor {
+/*BITFIELDTYPE*/ u_int64_t gd_looffset:16;/* gate offset (lsb) */
+/*BITFIELDTYPE*/ u_int64_t gd_selector:16;/* gate segment selector */
+/*BITFIELDTYPE*/ u_int64_t gd_ist:3;	/* IST select */
+/*BITFIELDTYPE*/ u_int64_t gd_xx1:5;	/* reserved */
+/*BITFIELDTYPE*/ u_int64_t gd_type:5;	/* segment type */
+/*BITFIELDTYPE*/ u_int64_t gd_dpl:2;	/* segment descriptor priority level */
+/*BITFIELDTYPE*/ u_int64_t gd_p:1;	/* segment descriptor present */
+/*BITFIELDTYPE*/ u_int64_t gd_hioffset:48;/* gate offset (msb) */
+/*BITFIELDTYPE*/ u_int64_t gd_xx2:8;	/* reserved */
+/*BITFIELDTYPE*/ u_int64_t gd_zero:5;	/* must be zero */
+/*BITFIELDTYPE*/ u_int64_t gd_xx3:19;	/* reserved */
+} __attribute__((packed));
+
+/*
+ * region descriptors, used to load gdt/idt tables before segments yet exist.
+ */
+struct region_descriptor {
+	u_int16_t rd_limit;		/* segment extent */
+	u_int64_t rd_base;		/* base address  */
+} __attribute__((packed));
+
+#ifdef _KERNEL
+#if 0
+extern struct sys_segment_descriptor *ldt;
+#endif
+extern struct gate_descriptor *idt;
+extern char *gdtstore;
+extern char *ldtstore;
+
+void setgate(struct gate_descriptor *, void *, int, int, int, int);
+void unsetgate(struct gate_descriptor *);
+void setregion(struct region_descriptor *, void *, u_int16_t);
+void set_sys_segment(struct sys_segment_descriptor *, void *, size_t,
+			  int, int, int);
+void set_mem_segment(struct mem_segment_descriptor *, void *, size_t,
+			  int, int, int, int, int);
+int idt_vec_alloc(int, int);
+void idt_vec_set(int, void (*)(void));
+void idt_vec_free(int);
+void cpu_init_idt(void);
+
+#endif /* _KERNEL */
+
+#endif /* !_LOCORE */
+
+/* system segments and gate types */
+#define	SDT_SYSNULL	 0	/* system null */
+#define	SDT_SYS286TSS	 1	/* system 286 TSS available */
+#define	SDT_SYSLDT	 2	/* system local descriptor table */
+#define	SDT_SYS286BSY	 3	/* system 286 TSS busy */
+#define	SDT_SYS286CGT	 4	/* system 286 call gate */
+#define	SDT_SYSTASKGT	 5	/* system task gate */
+#define	SDT_SYS286IGT	 6	/* system 286 interrupt gate */
+#define	SDT_SYS286TGT	 7	/* system 286 trap gate */
+#define	SDT_SYSNULL2	 8	/* system null again */
+#define	SDT_SYS386TSS	 9	/* system 386 TSS available */
+#define	SDT_SYSNULL3	10	/* system null again */
+#define	SDT_SYS386BSY	11	/* system 386 TSS busy */
+#define	SDT_SYS386CGT	12	/* system 386 call gate */
+#define	SDT_SYSNULL4	13	/* system null again */
+#define	SDT_SYS386IGT	14	/* system 386 interrupt gate */
+#define	SDT_SYS386TGT	15	/* system 386 trap gate */
+
+/* memory segment types */
+#define	SDT_MEMRO	16	/* memory read only */
+#define	SDT_MEMROA	17	/* memory read only accessed */
+#define	SDT_MEMRW	18	/* memory read write */
+#define	SDT_MEMRWA	19	/* memory read write accessed */
+#define	SDT_MEMROD	20	/* memory read only expand dwn limit */
+#define	SDT_MEMRODA	21	/* memory read only expand dwn limit accessed */
+#define	SDT_MEMRWD	22	/* memory read write expand dwn limit */
+#define	SDT_MEMRWDA	23	/* memory read write expand dwn limit acessed */
+#define	SDT_MEME	24	/* memory execute only */
+#define	SDT_MEMEA	25	/* memory execute only accessed */
+#define	SDT_MEMER	26	/* memory execute read */
+#define	SDT_MEMERA	27	/* memory execute read accessed */
+#define	SDT_MEMEC	28	/* memory execute only conforming */
+#define	SDT_MEMEAC	29	/* memory execute only accessed conforming */
+#define	SDT_MEMERC	30	/* memory execute read conforming */
+#define	SDT_MEMERAC	31	/* memory execute read accessed conforming */
+
+/* is memory segment descriptor pointer ? */
+#define ISMEMSDP(s)	((s->d_type) >= SDT_MEMRO && \
+			 (s->d_type) <= SDT_MEMERAC)
+
+/* is 286 gate descriptor pointer ? */
+#define IS286GDP(s)	((s->d_type) >= SDT_SYS286CGT && \
+			 (s->d_type) < SDT_SYS286TGT)
+
+/* is 386 gate descriptor pointer ? */
+#define IS386GDP(s)	((s->d_type) >= SDT_SYS386CGT && \
+			 (s->d_type) < SDT_SYS386TGT)
+
+/* is gate descriptor pointer ? */
+#define ISGDP(s)	(IS286GDP(s) || IS386GDP(s))
+
+/* is segment descriptor pointer ? */
+#define ISSDP(s)	(ISMEMSDP(s) || !ISGDP(s))
+
+/* is system segment descriptor pointer ? */
+#define ISSYSSDP(s)	(!ISMEMSDP(s) && !ISGDP(s))
+
+/*
+ * Segment Protection Exception code bits
+ */
+#define	SEGEX_EXT	0x01	/* recursive or externally induced */
+#define	SEGEX_IDT	0x02	/* interrupt descriptor table */
+#define	SEGEX_TI	0x04	/* local descriptor table */
+
+/*
+ * Entries in the Interrupt Descriptor Table (IDT)
+ */
+#define	NIDT	256
+#define	NRSVIDT	32		/* reserved entries for cpu exceptions */
+
+/*
+ * Entries in the Global Descriptor Table (GDT)
+ * The code and data descriptors must come first. There
+ * are NGDT_MEM of them.
+ *
+ * Then come the predefined LDT (and possibly TSS) descriptors.
+ * There are NGDT_SYS of them.
+ */
+#define	GNULL_SEL	0	/* Null descriptor */
+#define	GCODE_SEL	1	/* Kernel code descriptor */
+#define	GDATA_SEL	2	/* Kernel data descriptor */
+#define	GUCODE_SEL	3	/* User code descriptor */
+#define	GUDATA_SEL	4	/* User data descriptor */
+#define	GAPM32CODE_SEL	5
+#define	GAPM16CODE_SEL	6
+#define	GAPMDATA_SEL	7
+#define	GBIOSCODE_SEL	8
+#define	GBIOSDATA_SEL	9
+#define GPNPBIOSCODE_SEL 10
+#define GPNPBIOSDATA_SEL 11
+#define GPNPBIOSSCRATCH_SEL 12
+#define GPNPBIOSTRAMP_SEL 13
+#define GUCODE32_SEL	14
+#define GUDATA32_SEL	15
+#define NGDT_MEM 16
+
+#define	GLDT_SEL	0	/* Default LDT descriptor */
+#define NGDT_SYS	1
+
+#define GDT_SYS_OFFSET	(NGDT_MEM << 3)
+
+#define GDT_ADDR_MEM(s,i)	\
+    ((struct mem_segment_descriptor *)((s) + ((i) << 3)))
+#define GDT_ADDR_SYS(s,i)	\
+   ((struct sys_segment_descriptor *)((s) + (((i) << 4) + SYSSEL_START)))
+
+/*
+ * Byte offsets in the Local Descriptor Table (LDT)
+ * Strange order because of syscall/sysret insns
+ */
+#define	LSYS5CALLS_SEL	0	/* iBCS system call gate */
+#define LUCODE32_SEL	8	/* 32 bit user code descriptor */
+#define	LUDATA_SEL	16	/* User data descriptor */
+#define	LUCODE_SEL	24	/* User code descriptor */
+#define	LSOL26CALLS_SEL	32	/* Solaris 2.6 system call gate */
+#define LUDATA32_SEL	56	/* 32 bit user data descriptor (needed?)*/
+#define	LBSDICALLS_SEL	128	/* BSDI system call gate */
+
+#define LDT_SIZE	144
+
+#define LSYSRETBASE_SEL	LUCODE32_SEL
+
+#endif /* _AMD64_SEGMENTS_H_ */
diff --git a/sys/arch/amd64/include/setjmp.h b/sys/arch/amd64/include/setjmp.h
new file mode 100644
index 00000000000..01d6066450f
--- /dev/null
+++ b/sys/arch/amd64/include/setjmp.h
@@ -0,0 +1,21 @@
+/*	$OpenBSD: setjmp.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: setjmp.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
+
+/*
+ * machine/setjmp.h: machine dependent setjmp-related information.
+ * These are only the callee-saved registers, code calling setjmp
+ * will expect the rest to be clobbered anyway.
+ */
+
+#define _JB_RBX		0
+#define _JB_RBP		1
+#define _JB_R12		2
+#define _JB_R13		3
+#define _JB_R14		4
+#define _JB_R15		5
+#define _JB_RSP		6
+#define _JB_PC		7
+#define _JB_SIGFLAG	8
+#define _JB_SIGMASK	9
+
+#define	_JBLEN	11		/* size, in longs, of a jmp_buf */
diff --git a/sys/arch/amd64/include/signal.h b/sys/arch/amd64/include/signal.h
new file mode 100644
index 00000000000..79227ad5f6e
--- /dev/null
+++ b/sys/arch/amd64/include/signal.h
@@ -0,0 +1,88 @@
+/*	$NetBSD: signal.h,v 1.2 2003/04/28 23:16:17 bjh21 Exp $	*/
+
+/*
+ * Copyright (c) 1982, 1986, 1989, 1991 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)signal.h	7.16 (Berkeley) 3/17/91
+ */
+
+#ifndef _AMD64_SIGNAL_H_
+#define _AMD64_SIGNAL_H_
+
+typedef int sig_atomic_t;
+
+#ifndef _ANSI_SOURCE
+#include <machine/trap.h>
+
+/*
+ * Information pushed on stack when a signal is delivered.
+ * This is used by the kernel to restore state following
+ * execution of the signal handler.  It is also made available
+ * to the handler to allow it to restore state properly if
+ * a non-standard exit is performed.
+ */
+struct sigcontext {
+	/* plain match trapframe */
+	long	sc_rdi;
+	long	sc_rsi;
+	long	sc_rdx;
+	long	sc_rcx;
+	long	sc_r8;
+	long	sc_r9;
+	long	sc_r10;
+	long	sc_r11;
+	long	sc_r12;
+	long	sc_r13;
+	long	sc_r14;
+	long	sc_r15;
+	long	sc_rbp;
+	long	sc_rbx;
+	long	sc_rax;
+	long	sc_gs;
+	long	sc_fs;
+	long	sc_es;
+	long	sc_ds;
+	long	sc_trapno;
+	long	sc_err;
+	long	sc_rip;
+	long	sc_cs;
+	long	sc_rflags;
+	long	sc_rsp;
+	long	sc_ss;
+
+	int	sc_onstack;
+	int	sc_mask;
+};
+
+#endif	/* !_ANSI_SOURCE */
+#endif	/* !_AMD64_SIGNAL_H_ */
+
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
new file mode 100644
index 00000000000..ef6db41a1fc
--- /dev/null
+++ b/sys/arch/amd64/include/specialreg.h
@@ -0,0 +1,604 @@
+/*	$OpenBSD: specialreg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
+/*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)specialreg.h	7.1 (Berkeley) 5/9/91
+ */
+
+/*
+ * Bits in 386 special registers:
+ */
+#define	CR0_PE	0x00000001	/* Protected mode Enable */
+#define	CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
+#define	CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
+#define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
+#define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
+#define	CR0_PG	0x80000000	/* PaGing enable */
+
+/*
+ * Bits in 486 special registers:
+ */
+#define CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
+#define CR0_WP	0x00010000	/* Write Protect (honor PG_RW in all modes) */
+#define CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
+#define	CR0_NW	0x20000000	/* Not Write-through */
+#define	CR0_CD	0x40000000	/* Cache Disable */
+
+/*
+ * Cyrix 486 DLC special registers, accessible as IO ports.
+ */
+#define CCR0	0xc0		/* configuration control register 0 */
+#define CCR0_NC0	0x01	/* first 64K of each 1M memory region is non-cacheable */
+#define CCR0_NC1	0x02	/* 640K-1M region is non-cacheable */
+#define CCR0_A20M	0x04	/* enables A20M# input pin */
+#define CCR0_KEN	0x08	/* enables KEN# input pin */
+#define CCR0_FLUSH	0x10	/* enables FLUSH# input pin */
+#define CCR0_BARB	0x20	/* flushes internal cache when entering hold state */
+#define CCR0_CO		0x40	/* cache org: 1=direct mapped, 0=2x set assoc */
+#define CCR0_SUSPEND	0x80	/* enables SUSP# and SUSPA# pins */
+
+#define CCR1	0xc1		/* configuration control register 1 */
+#define CCR1_RPL	0x01	/* enables RPLSET and RPLVAL# pins */
+/* the remaining 7 bits of this register are reserved */
+
+/*
+ * bits in the pentiums %cr4 register:
+ */
+
+#define CR4_VME	0x00000001	/* virtual 8086 mode extension enable */
+#define CR4_PVI 0x00000002	/* protected mode virtual interrupt enable */
+#define CR4_TSD 0x00000004	/* restrict RDTSC instruction to cpl 0 only */
+#define CR4_DE	0x00000008	/* debugging extension */
+#define CR4_PSE	0x00000010	/* large (4MB) page size enable */
+#define CR4_PAE 0x00000020	/* physical address extension enable */
+#define CR4_MCE	0x00000040	/* machine check enable */
+#define CR4_PGE	0x00000080	/* page global enable */
+#define CR4_PCE	0x00000100	/* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR	0x00000200	/* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT	0x00000400	/* enable unmasked SSE exceptions */
+
+/*
+ * CPUID "features" bits:
+ */
+
+#define	CPUID_FPU	0x00000001	/* processor has an FPU? */
+#define	CPUID_VME	0x00000002	/* has virtual mode (%cr4's VME/PVI) */
+#define	CPUID_DE	0x00000004	/* has debugging extension */
+#define	CPUID_PSE	0x00000008	/* has page 4MB page size extension */
+#define	CPUID_TSC	0x00000010	/* has time stamp counter */
+#define	CPUID_MSR	0x00000020	/* has mode specific registers */
+#define	CPUID_PAE	0x00000040	/* has phys address extension */
+#define	CPUID_MCE	0x00000080	/* has machine check exception */
+#define	CPUID_CX8	0x00000100	/* has CMPXCHG8B instruction */
+#define	CPUID_APIC	0x00000200	/* has enabled APIC */
+#define	CPUID_B10	0x00000400	/* reserved, MTRR */
+#define	CPUID_SEP	0x00000800	/* has SYSENTER/SYSEXIT extension */
+#define	CPUID_MTRR	0x00001000	/* has memory type range register */
+#define	CPUID_PGE	0x00002000	/* has page global extension */
+#define	CPUID_MCA	0x00004000	/* has machine check architecture */
+#define	CPUID_CMOV	0x00008000	/* has CMOVcc instruction */
+#define	CPUID_PAT	0x00010000	/* Page Attribute Table */
+#define	CPUID_PSE36	0x00020000	/* 36-bit PSE */
+#define	CPUID_PN	0x00040000	/* processor serial number */
+#define	CPUID_CFLUSH	0x00080000	/* CFLUSH insn supported */
+#define	CPUID_B20	0x00100000	/* reserved */
+#define	CPUID_DS	0x00200000	/* Debug Store */
+#define	CPUID_ACPI	0x00400000	/* ACPI performance modulation regs */
+#define	CPUID_MMX	0x00800000	/* MMX supported */
+#define	CPUID_FXSR	0x01000000	/* fast FP/MMX save/restore */
+#define	CPUID_SSE	0x02000000	/* streaming SIMD extensions */
+#define	CPUID_SSE2	0x04000000	/* streaming SIMD extensions #2 */
+#define	CPUID_SS	0x08000000	/* self-snoop */
+#define	CPUID_HTT	0x10000000	/* Hyper-Threading Technology */
+#define	CPUID_TM	0x20000000	/* thermal monitor (TCC) */
+#define	CPUID_IA64	0x40000000	/* IA-64 architecture */
+#define	CPUID_SBF	0x80000000	/* signal break on FERR */
+
+#define CPUID_FLAGS1	"\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
+			    "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
+#define CPUID_MASK1	0x00001fff
+#define CPUID_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \
+			    "\25B20\26DS\27ACPI\30MMX"
+#define CPUID_MASK2	0x00ffe000
+#define CPUID_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF"
+#define CPUID_MASK3	0xff000000
+
+/*
+ * AMD/VIA processor specific flags.
+ */
+
+#define CPUID_MPC	0x00080000	/* Multiprocessing Capable */
+#define	CPUID_NXE	0x00100000	/* No-Execute Extension */
+#define CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
+#define CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
+#define CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
+
+#define CPUID_EXT_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
+				    "\24MPC\25NXE\26B21\27MMXX\30MMX"
+#define CPUID_EXT_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34B27\35B28\36LONG" \
+				    "\0373DNOW2\0403DNOW"
+
+#define CPUID2FAMILY(cpuid)	(((cpuid) >> 8) & 15)
+#define CPUID2MODEL(cpuid)	(((cpuid) >> 4) & 15)
+#define CPUID2STEPPING(cpuid)	((cpuid) & 15)
+
+#define CPUID(code, eax, ebx, ecx, edx)                         \
+	__asm("cpuid"                                           \
+	    : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)    \
+	    : "a" (code));
+
+
+/*
+ * Model-specific registers for the i386 family
+ */
+#define MSR_P5_MC_ADDR		0x000	/* P5 only */
+#define MSR_P5_MC_TYPE		0x001	/* P5 only */
+#define MSR_TSC			0x010
+#define	MSR_CESR		0x011	/* P5 only (trap on P6) */
+#define	MSR_CTR0		0x012	/* P5 only (trap on P6) */
+#define	MSR_CTR1		0x013	/* P5 only (trap on P6) */
+#define MSR_APICBASE		0x01b
+#define MSR_EBL_CR_POWERON	0x02a
+#define	MSR_TEST_CTL		0x033
+#define MSR_BIOS_UPDT_TRIG	0x079
+#define	MSR_BBL_CR_D0		0x088	/* PII+ only */
+#define	MSR_BBL_CR_D1		0x089	/* PII+ only */
+#define	MSR_BBL_CR_D2		0x08a	/* PII+ only */
+#define MSR_BIOS_SIGN		0x08b
+#define MSR_PERFCTR0		0x0c1
+#define MSR_PERFCTR1		0x0c2
+#define MSR_MTRRcap		0x0fe
+#define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
+#define	MSR_BBL_CR_DECC		0x118	/* PII+ only */
+#define	MSR_BBL_CR_CTL		0x119	/* PII+ only */
+#define	MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
+#define	MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
+#define	MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
+#define	MSR_SYSENTER_CS		0x174 	/* PII+ only */
+#define	MSR_SYSENTER_ESP	0x175 	/* PII+ only */
+#define	MSR_SYSENTER_EIP	0x176   /* PII+ only */
+#define MSR_MCG_CAP		0x179
+#define MSR_MCG_STATUS		0x17a
+#define MSR_MCG_CTL		0x17b
+#define MSR_EVNTSEL0		0x186
+#define MSR_EVNTSEL1		0x187
+#define MSR_DEBUGCTLMSR		0x1d9
+#define MSR_LASTBRANCHFROMIP	0x1db
+#define MSR_LASTBRANCHTOIP	0x1dc
+#define MSR_LASTINTFROMIP	0x1dd
+#define MSR_LASTINTTOIP		0x1de
+#define MSR_ROB_CR_BKUPTMPDR6	0x1e0
+#define	MSR_MTRRphysBase0	0x200
+#define	MSR_MTRRphysMask0	0x201
+#define	MSR_MTRRphysBase1	0x202
+#define	MSR_MTRRphysMask1	0x203
+#define	MSR_MTRRphysBase2	0x204
+#define	MSR_MTRRphysMask2	0x205
+#define	MSR_MTRRphysBase3	0x206
+#define	MSR_MTRRphysMask3	0x207
+#define	MSR_MTRRphysBase4	0x208
+#define	MSR_MTRRphysMask4	0x209
+#define	MSR_MTRRphysBase5	0x20a
+#define	MSR_MTRRphysMask5	0x20b
+#define	MSR_MTRRphysBase6	0x20c
+#define	MSR_MTRRphysMask6	0x20d
+#define	MSR_MTRRphysBase7	0x20e
+#define	MSR_MTRRphysMask7	0x20f
+#define	MSR_MTRRfix64K_00000	0x250
+#define	MSR_MTRRfix16K_80000	0x258
+#define	MSR_MTRRfix16K_A0000	0x259
+#define	MSR_MTRRfix4K_C0000	0x268
+#define	MSR_MTRRfix4K_C8000	0x269
+#define	MSR_MTRRfix4K_D0000	0x26a
+#define	MSR_MTRRfix4K_D8000	0x26b
+#define	MSR_MTRRfix4K_E0000	0x26c
+#define	MSR_MTRRfix4K_E8000	0x26d
+#define	MSR_MTRRfix4K_F0000	0x26e
+#define	MSR_MTRRfix4K_F8000	0x26f
+#define MSR_MTRRdefType		0x2ff
+#define MSR_MC0_CTL		0x400
+#define MSR_MC0_STATUS		0x401
+#define MSR_MC0_ADDR		0x402
+#define MSR_MC0_MISC		0x403
+#define MSR_MC1_CTL		0x404
+#define MSR_MC1_STATUS		0x405
+#define MSR_MC1_ADDR		0x406
+#define MSR_MC1_MISC		0x407
+#define MSR_MC2_CTL		0x408
+#define MSR_MC2_STATUS		0x409
+#define MSR_MC2_ADDR		0x40a
+#define MSR_MC2_MISC		0x40b
+#define MSR_MC4_CTL		0x40c
+#define MSR_MC4_STATUS		0x40d
+#define MSR_MC4_ADDR		0x40e
+#define MSR_MC4_MISC		0x40f
+#define MSR_MC3_CTL		0x410
+#define MSR_MC3_STATUS		0x411
+#define MSR_MC3_ADDR		0x412
+#define MSR_MC3_MISC		0x413
+
+/*
+ * AMD K6/K7 MSRs.
+ */
+#define	MSR_K6_UWCCR		0xc0000085
+#define	MSR_K7_EVNTSEL0		0xc0010000
+#define	MSR_K7_EVNTSEL1		0xc0010001
+#define	MSR_K7_EVNTSEL2		0xc0010002
+#define	MSR_K7_EVNTSEL3		0xc0010003
+#define	MSR_K7_PERFCTR0		0xc0010004
+#define	MSR_K7_PERFCTR1		0xc0010005
+#define	MSR_K7_PERFCTR2		0xc0010006
+#define	MSR_K7_PERFCTR3		0xc0010007
+
+/*
+ * Constants related to MTRRs
+ */
+#define MTRR_N64K		8	/* numbers of fixed-size entries */
+#define MTRR_N16K		16
+#define MTRR_N4K		64
+
+/*
+ * the following four 3-byte registers control the non-cacheable regions.
+ * These registers must be written as three separate bytes.
+ *
+ * NCRx+0: A31-A24 of starting address
+ * NCRx+1: A23-A16 of starting address
+ * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
+ * 
+ * The non-cacheable region's starting address must be aligned to the
+ * size indicated by the NCR_SIZE_xx field.
+ */
+#define NCR1	0xc4
+#define NCR2	0xc7
+#define NCR3	0xca
+#define NCR4	0xcd
+
+#define NCR_SIZE_0K	0
+#define NCR_SIZE_4K	1
+#define NCR_SIZE_8K	2
+#define NCR_SIZE_16K	3
+#define NCR_SIZE_32K	4
+#define NCR_SIZE_64K	5
+#define NCR_SIZE_128K	6
+#define NCR_SIZE_256K	7
+#define NCR_SIZE_512K	8
+#define NCR_SIZE_1M	9
+#define NCR_SIZE_2M	10
+#define NCR_SIZE_4M	11
+#define NCR_SIZE_8M	12
+#define NCR_SIZE_16M	13
+#define NCR_SIZE_32M	14
+#define NCR_SIZE_4G	15
+
+/*
+ * Performance monitor events.
+ *
+ * Note that 586-class and 686-class CPUs have different performance
+ * monitors available, and they are accessed differently:
+ *
+ *	686-class: `rdpmc' instruction
+ *	586-class: `rdmsr' instruction, CESR MSR
+ *
+ * The descriptions of these events are too lenghy to include here.
+ * See Appendix A of "Intel Architecture Software Developer's
+ * Manual, Volume 3: System Programming" for more information.
+ */
+
+/*
+ * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
+ * is CTR1.
+ */
+
+#define	PMC5_CESR_EVENT			0x003f
+#define	PMC5_CESR_OS			0x0040
+#define	PMC5_CESR_USR			0x0080
+#define	PMC5_CESR_E			0x0100
+#define	PMC5_CESR_P			0x0200
+
+#define PMC5_DATA_READ			0x00
+#define PMC5_DATA_WRITE			0x01
+#define PMC5_DATA_TLB_MISS		0x02
+#define PMC5_DATA_READ_MISS		0x03
+#define PMC5_DATA_WRITE_MISS		0x04
+#define PMC5_WRITE_M_E			0x05
+#define PMC5_DATA_LINES_WBACK		0x06
+#define PMC5_DATA_CACHE_SNOOP		0x07
+#define PMC5_DATA_CACHE_SNOOP_HIT	0x08
+#define PMC5_MEM_ACCESS_BOTH_PIPES	0x09
+#define PMC5_BANK_CONFLICTS		0x0a
+#define PMC5_MISALIGNED_DATA		0x0b
+#define PMC5_INST_READ			0x0c
+#define PMC5_INST_TLB_MISS		0x0d
+#define PMC5_INST_CACHE_MISS		0x0e
+#define PMC5_SEGMENT_REG_LOAD		0x0f
+#define PMC5_BRANCHES		 	0x12
+#define PMC5_BTB_HITS		 	0x13
+#define PMC5_BRANCH_TAKEN		0x14
+#define PMC5_PIPELINE_FLUSH		0x15
+#define PMC5_INST_EXECUTED		0x16
+#define PMC5_INST_EXECUTED_V_PIPE	0x17
+#define PMC5_BUS_UTILIZATION		0x18
+#define PMC5_WRITE_BACKUP_STALL		0x19
+#define PMC5_DATA_READ_STALL		0x1a
+#define PMC5_WRITE_E_M_STALL		0x1b
+#define PMC5_LOCKED_BUS			0x1c
+#define PMC5_IO_CYCLE			0x1d
+#define PMC5_NONCACHE_MEM_READ		0x1e
+#define PMC5_AGI_STALL			0x1f
+#define PMC5_FLOPS			0x22
+#define PMC5_BP0_MATCH			0x23
+#define PMC5_BP1_MATCH			0x24
+#define PMC5_BP2_MATCH			0x25
+#define PMC5_BP3_MATCH			0x26
+#define PMC5_HARDWARE_INTR		0x27
+#define PMC5_DATA_RW			0x28
+#define PMC5_DATA_RW_MISS		0x29
+
+/*
+ * 686-class Event Selector MSR format.
+ */
+
+#define	PMC6_EVTSEL_EVENT		0x000000ff
+#define	PMC6_EVTSEL_UNIT		0x0000ff00
+#define	PMC6_EVTSEL_UNIT_SHIFT		8
+#define	PMC6_EVTSEL_USR			(1 << 16)
+#define	PMC6_EVTSEL_OS			(1 << 17)
+#define	PMC6_EVTSEL_E			(1 << 18)
+#define	PMC6_EVTSEL_PC			(1 << 19)
+#define	PMC6_EVTSEL_INT			(1 << 20)
+#define	PMC6_EVTSEL_EN			(1 << 22)	/* PerfEvtSel0 only */
+#define	PMC6_EVTSEL_INV			(1 << 23)
+#define	PMC6_EVTSEL_COUNTER_MASK	0xff000000
+#define	PMC6_EVTSEL_COUNTER_MASK_SHIFT	24
+
+/* Data Cache Unit */
+#define	PMC6_DATA_MEM_REFS		0x43
+#define	PMC6_DCU_LINES_IN		0x45
+#define	PMC6_DCU_M_LINES_IN		0x46
+#define	PMC6_DCU_M_LINES_OUT		0x47
+#define	PMC6_DCU_MISS_OUTSTANDING	0x48
+
+/* Instruction Fetch Unit */
+#define	PMC6_IFU_IFETCH			0x80
+#define	PMC6_IFU_IFETCH_MISS		0x81
+#define	PMC6_ITLB_MISS			0x85
+#define	PMC6_IFU_MEM_STALL		0x86
+#define	PMC6_ILD_STALL			0x87
+
+/* L2 Cache */
+#define	PMC6_L2_IFETCH			0x28
+#define	PMC6_L2_LD			0x29
+#define	PMC6_L2_ST			0x2a
+#define	PMC6_L2_LINES_IN		0x24
+#define	PMC6_L2_LINES_OUT		0x26
+#define	PMC6_L2_M_LINES_INM		0x25
+#define	PMC6_L2_M_LINES_OUTM		0x27
+#define	PMC6_L2_RQSTS			0x2e
+#define	PMC6_L2_ADS			0x21
+#define	PMC6_L2_DBUS_BUSY		0x22
+#define	PMC6_L2_DBUS_BUSY_RD		0x23
+
+/* External Bus Logic */
+#define	PMC6_BUS_DRDY_CLOCKS		0x62
+#define	PMC6_BUS_LOCK_CLOCKS		0x63
+#define	PMC6_BUS_REQ_OUTSTANDING	0x60
+#define	PMC6_BUS_TRAN_BRD		0x65
+#define	PMC6_BUS_TRAN_RFO		0x66
+#define	PMC6_BUS_TRANS_WB		0x67
+#define	PMC6_BUS_TRAN_IFETCH		0x68
+#define	PMC6_BUS_TRAN_INVAL		0x69
+#define	PMC6_BUS_TRAN_PWR		0x6a
+#define	PMC6_BUS_TRANS_P		0x6b
+#define	PMC6_BUS_TRANS_IO		0x6c
+#define	PMC6_BUS_TRAN_DEF		0x6d
+#define	PMC6_BUS_TRAN_BURST		0x6e
+#define	PMC6_BUS_TRAN_ANY		0x70
+#define	PMC6_BUS_TRAN_MEM		0x6f
+#define	PMC6_BUS_DATA_RCV		0x64
+#define	PMC6_BUS_BNR_DRV		0x61
+#define	PMC6_BUS_HIT_DRV		0x7a
+#define	PMC6_BUS_HITM_DRDV		0x7b
+#define	PMC6_BUS_SNOOP_STALL		0x7e
+
+/* Floating Point Unit */
+#define	PMC6_FLOPS			0xc1
+#define	PMC6_FP_COMP_OPS_EXE		0x10
+#define	PMC6_FP_ASSIST			0x11
+#define	PMC6_MUL			0x12
+#define	PMC6_DIV			0x12
+#define	PMC6_CYCLES_DIV_BUSY		0x14
+
+/* Memory Ordering */
+#define	PMC6_LD_BLOCKS			0x03
+#define	PMC6_SB_DRAINS			0x04
+#define	PMC6_MISALIGN_MEM_REF		0x05
+#define	PMC6_EMON_KNI_PREF_DISPATCHED	0x07	/* P-III only */
+#define	PMC6_EMON_KNI_PREF_MISS		0x4b	/* P-III only */
+
+/* Instruction Decoding and Retirement */
+#define	PMC6_INST_RETIRED		0xc0
+#define	PMC6_UOPS_RETIRED		0xc2
+#define	PMC6_INST_DECODED		0xd0
+#define	PMC6_EMON_KNI_INST_RETIRED	0xd8
+#define	PMC6_EMON_KNI_COMP_INST_RET	0xd9
+
+/* Interrupts */
+#define	PMC6_HW_INT_RX			0xc8
+#define	PMC6_CYCLES_INT_MASKED		0xc6
+#define	PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
+
+/* Branches */
+#define	PMC6_BR_INST_RETIRED		0xc4
+#define	PMC6_BR_MISS_PRED_RETIRED	0xc5
+#define	PMC6_BR_TAKEN_RETIRED		0xc9
+#define	PMC6_BR_MISS_PRED_TAKEN_RET	0xca
+#define	PMC6_BR_INST_DECODED		0xe0
+#define	PMC6_BTB_MISSES			0xe2
+#define	PMC6_BR_BOGUS			0xe4
+#define	PMC6_BACLEARS			0xe6
+
+/* Stalls */
+#define	PMC6_RESOURCE_STALLS		0xa2
+#define	PMC6_PARTIAL_RAT_STALLS		0xd2
+
+/* Segment Register Loads */
+#define	PMC6_SEGMENT_REG_LOADS		0x06
+
+/* Clocks */
+#define	PMC6_CPU_CLK_UNHALTED		0x79
+
+/* MMX Unit */
+#define	PMC6_MMX_INSTR_EXEC		0xb0	/* Celeron, P-II, P-IIX only */
+#define	PMC6_MMX_SAT_INSTR_EXEC		0xb1	/* P-II and P-III only */
+#define	PMC6_MMX_UOPS_EXEC		0xb2	/* P-II and P-III only */
+#define	PMC6_MMX_INSTR_TYPE_EXEC	0xb3	/* P-II and P-III only */
+#define	PMC6_FP_MMX_TRANS		0xcc	/* P-II and P-III only */
+#define	PMC6_MMX_ASSIST			0xcd	/* P-II and P-III only */
+#define	PMC6_MMX_INSTR_RET		0xc3	/* P-II only */
+
+/* Segment Register Renaming */
+#define	PMC6_SEG_RENAME_STALLS		0xd4	/* P-II and P-III only */
+#define	PMC6_SEG_REG_RENAMES		0xd5	/* P-II and P-III only */
+#define	PMC6_RET_SEG_RENAMES		0xd6	/* P-II and P-III only */
+
+/*
+ * AMD K7 Event Selector MSR format.
+ */
+
+#define	K7_EVTSEL_EVENT			0x000000ff
+#define	K7_EVTSEL_UNIT			0x0000ff00
+#define	K7_EVTSEL_UNIT_SHIFT		8
+#define	K7_EVTSEL_USR			(1 << 16)
+#define	K7_EVTSEL_OS			(1 << 17)
+#define	K7_EVTSEL_E			(1 << 18)
+#define	K7_EVTSEL_PC			(1 << 19)
+#define	K7_EVTSEL_INT			(1 << 20)
+#define	K7_EVTSEL_EN			(1 << 22)
+#define	K7_EVTSEL_INV			(1 << 23)
+#define	K7_EVTSEL_COUNTER_MASK		0xff000000
+#define	K7_EVTSEL_COUNTER_MASK_SHIFT	24
+
+/* Segment Register Loads */
+#define	K7_SEGMENT_REG_LOADS		0x20
+
+#define	K7_STORES_TO_ACTIVE_INST_STREAM	0x21
+
+/* Data Cache Unit */
+#define	K7_DATA_CACHE_ACCESS		0x40
+#define	K7_DATA_CACHE_MISS		0x41
+#define	K7_DATA_CACHE_REFILL		0x42
+#define	K7_DATA_CACHE_REFILL_SYSTEM	0x43
+#define	K7_DATA_CACHE_WBACK		0x44
+#define	K7_L2_DTLB_HIT			0x45
+#define	K7_L2_DTLB_MISS			0x46
+#define	K7_MISALIGNED_DATA_REF		0x47
+#define	K7_SYSTEM_REQUEST		0x64
+#define	K7_SYSTEM_REQUEST_TYPE		0x65
+
+#define	K7_SNOOP_HIT			0x73
+#define	K7_SINGLE_BIT_ECC_ERROR		0x74
+#define	K7_CACHE_LINE_INVAL		0x75
+#define	K7_CYCLES_PROCESSOR_IS_RUNNING	0x76
+#define	K7_L2_REQUEST			0x79
+#define	K7_L2_REQUEST_BUSY		0x7a
+
+/* Instruction Fetch Unit */
+#define	K7_IFU_IFETCH			0x80
+#define	K7_IFU_IFETCH_MISS		0x81
+#define	K7_IFU_REFILL_FROM_L2		0x82
+#define	K7_IFU_REFILL_FROM_SYSTEM	0x83
+#define	K7_ITLB_L1_MISS			0x84
+#define	K7_ITLB_L2_MISS			0x85
+#define	K7_SNOOP_RESYNC			0x86
+#define	K7_IFU_STALL			0x87
+
+#define	K7_RETURN_STACK_HITS		0x88
+#define	K7_RETURN_STACK_OVERFLOW	0x89
+
+/* Retired */
+#define	K7_RETIRED_INST			0xc0
+#define	K7_RETIRED_OPS			0xc1
+#define	K7_RETIRED_BRANCHES		0xc2
+#define	K7_RETIRED_BRANCH_MISPREDICTED	0xc3
+#define	K7_RETIRED_TAKEN_BRANCH		0xc4
+#define	K7_RETIRED_TAKEN_BRANCH_MISPREDICTED	0xc5
+#define	K7_RETIRED_FAR_CONTROL_TRANSFER	0xc6
+#define	K7_RETIRED_RESYNC_BRANCH	0xc7
+#define	K7_RETIRED_NEAR_RETURNS		0xc8
+#define	K7_RETIRED_NEAR_RETURNS_MISPREDICTED	0xc9
+#define	K7_RETIRED_INDIRECT_MISPREDICTED	0xca
+
+/* Interrupts */
+#define	K7_CYCLES_INT_MASKED		0xcd
+#define	K7_CYCLES_INT_PENDING_AND_MASKED	0xce
+#define	K7_HW_INTR_RECV			0xcf
+
+#define	K7_INSTRUCTION_DECODER_EMPTY	0xd0
+#define	K7_DISPATCH_STALLS		0xd1
+#define	K7_BRANCH_ABORTS_TO_RETIRE	0xd2
+#define	K7_SERIALIZE			0xd3
+#define	K7_SEGMENT_LOAD_STALL		0xd4
+#define	K7_ICU_FULL			0xd5
+#define	K7_RESERVATION_STATIONS_FULL	0xd6
+#define	K7_FPU_FULL			0xd7
+#define	K7_LS_FULL			0xd8
+#define	K7_ALL_QUIET_STALL		0xd9
+#define	K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING	0xda
+
+#define	K7_BP0_MATCH			0xdc
+#define	K7_BP1_MATCH			0xdd
+#define	K7_BP2_MATCH			0xde
+#define	K7_BP3_MATCH			0xdf
+
+/*
+ * Extended Feature Enable Register of the x86-64
+ */
+
+#define MSR_EFER	0xc0000080
+
+#define EFER_SCE	0x00000001	/* SYSCALL extension */
+#define EFER_LME	0x00000100	/* Long Mode Enabled */
+#define EFER_LMA	0x00000400	/* Long Mode Active */
+#define EFER_NXE	0x00000800	/* No-Execute Enable */
+#define EFER_FFXSR	0x00004000	/* Fast FXSAVE/FXRSTOR */
+
+#define MSR_STAR	0xc0000081		/* 32 bit syscall gate addr */
+#define MSR_LSTAR	0xc0000082		/* 64 bit syscall gate addr */
+#define MSR_CSTAR	0xc0000083		/* compat syscall gate addr */
+#define MSR_SFMASK	0xc0000084		/* flags to clear on syscall */
+
+#define MSR_FSBASE		0xc0000100	/* 64bit offset for fs: */
+#define MSR_GSBASE		0xc0000101	/* 64bit offset for gs: */
+#define MSR_KERNELGSBASE	0xc0000102	/* storage for swapgs ins */
diff --git a/sys/arch/amd64/include/spinlock.h b/sys/arch/amd64/include/spinlock.h
new file mode 100644
index 00000000000..be9e806ff5e
--- /dev/null
+++ b/sys/arch/amd64/include/spinlock.h
@@ -0,0 +1,10 @@
+/*	$OpenBSD: spinlock.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+#ifndef _MACHINE_SPINLOCK_H_
+#define _MACHINE_SPINLOCK_H_
+
+#define _SPINLOCK_UNLOCKED	(0)
+#define _SPINLOCK_LOCKED	(1)
+typedef int _spinlock_lock_t;
+
+#endif
diff --git a/sys/arch/amd64/include/stdarg.h b/sys/arch/amd64/include/stdarg.h
new file mode 100644
index 00000000000..671b1e4d191
--- /dev/null
+++ b/sys/arch/amd64/include/stdarg.h
@@ -0,0 +1,57 @@
+/*	$OpenBSD: stdarg.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: stdarg.h,v 1.2 2003/04/28 23:16:17 bjh21 Exp $	*/
+
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)stdarg.h	8.1 (Berkeley) 6/10/93
+ */
+
+#ifndef _AMD64_STDARG_H_
+#define	_AMD64_STDARG_H_
+
+#include <machine/ansi.h>
+
+typedef _BSD_VA_LIST_	va_list;
+
+#define	va_start(ap, last)	__builtin_stdarg_start((ap), (last))
+#define	va_arg			__builtin_va_arg
+#define	va_end(ap)		__builtin_va_end(ap)
+#define	__va_copy(dest, src)	__builtin_va_copy((dest), (src))
+
+#if !defined(_ANSI_SOURCE) && \
+    (!defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) || \
+     defined(_ISOC99_SOURCE) || (__STDC_VERSION__ - 0) >= 199901L)
+#define	va_copy(dest, src)	__va_copy((dest), (src))
+#endif
+
+#endif /* !_AMD64_STDARG_H_ */
diff --git a/sys/arch/amd64/include/sysarch.h b/sys/arch/amd64/include/sysarch.h
new file mode 100644
index 00000000000..6ae6d006262
--- /dev/null
+++ b/sys/arch/amd64/include/sysarch.h
@@ -0,0 +1,120 @@
+/*	$OpenBSD: sysarch.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: sysarch.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
+
+#ifndef _AMD64_SYSARCH_H_
+#define _AMD64_SYSARCH_H_
+
+/*
+ * Architecture specific syscalls (amd64)
+ */
+#define X86_64_GET_LDT	0
+#define X86_64_SET_LDT	1
+#define	X86_64_IOPL	2
+#define	X86_64_GET_IOPERM	3
+#define	X86_64_SET_IOPERM	4
+#define	X86_64_VM86	5
+#define	X86_64_PMC_INFO	8
+#define	X86_64_PMC_STARTSTOP 9
+#define	X86_64_PMC_READ	10
+#define X86_64_GET_MTRR   11
+#define X86_64_SET_MTRR   12
+
+/*
+ * XXXfvdl todo.
+ */
+
+#if 0
+
+struct x86_64_get_ldt_args {
+	int start;
+	union descriptor *desc;
+	int num;
+};
+
+struct x86_64_set_ldt_args {
+	int start;
+	union descriptor *desc;
+	int num;
+};
+
+#endif
+
+struct x86_64_iopl_args {
+	int iopl;
+};
+
+#if 0
+
+struct x86_64_get_ioperm_args {
+	u_long *iomap;
+};
+
+struct x86_64_set_ioperm_args {
+	u_long *iomap;
+};
+
+struct x86_64_pmc_info_args {
+	int	type;
+	int	flags;
+};
+
+#define	PMC_TYPE_NONE		0
+#define	PMC_TYPE_I586		1
+#define	PMC_TYPE_I686		2
+
+#define	PMC_INFO_HASTSC		0x01
+
+#define	PMC_NCOUNTERS		2
+
+struct x86_64_pmc_startstop_args {
+	int counter;
+	u_int64_t val;
+	u_int8_t event;
+	u_int8_t unit;
+	u_int8_t compare;
+	u_int8_t flags;
+};
+
+#define	PMC_SETUP_KERNEL	0x01
+#define	PMC_SETUP_USER		0x02
+#define	PMC_SETUP_EDGE		0x04
+#define	PMC_SETUP_INV		0x08
+
+struct x86_64_pmc_read_args {
+	int counter;
+	u_int64_t val;
+	u_int64_t time;
+};
+
+#endif /* todo */
+
+struct x86_64_get_mtrr_args {
+	struct mtrr *mtrrp;
+	int *n;
+};
+
+struct x86_64_set_mtrr_args {
+	struct mtrr *mtrrp;
+	int *n;
+};
+
+
+#ifdef _KERNEL
+int x86_64_iopl(struct proc *, void *, register_t *);
+int x86_64_get_mtrr(struct proc *, void *, register_t *);
+int x86_64_set_mtrr(struct proc *, void *, register_t *);
+#else
+int x86_64_get_ldt(int, union descriptor *, int);
+int x86_64_set_ldt(int, union descriptor *, int);
+int x86_64_iopl(int);
+int x86_64_get_ioperm(u_long *);
+int x86_64_set_ioperm(u_long *);
+int x86_64_pmc_info(struct x86_64_pmc_info_args *);
+int x86_64_pmc_startstop(struct x86_64_pmc_startstop_args *);
+int x86_64_pmc_read(struct x86_64_pmc_read_args *);
+int x86_64_set_mtrr(struct mtrr *, int *);
+int x86_64_get_mtrr(struct mtrr *, int *);
+int sysarch(int, void *);
+#endif
+
+#endif /* !_AMD64_SYSARCH_H_ */
diff --git a/sys/arch/amd64/include/trap.h b/sys/arch/amd64/include/trap.h
new file mode 100644
index 00000000000..f3353efc973
--- /dev/null
+++ b/sys/arch/amd64/include/trap.h
@@ -0,0 +1,74 @@
+/*	$OpenBSD: trap.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: trap.h,v 1.4 1994/10/27 04:16:30 cgd Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)trap.h	5.4 (Berkeley) 5/9/91
+ */
+
+/*
+ * Trap type values
+ * also known in trap.c for name strings
+ */
+
+#define	T_PRIVINFLT	 0	/* privileged instruction */
+#define	T_BPTFLT	 1	/* breakpoint trap */
+#define	T_ARITHTRAP	 2	/* arithmetic trap */
+#define	T_ASTFLT	 3	/* asynchronous system trap */
+#define	T_PROTFLT	 4	/* protection fault */
+#define	T_TRCTRAP	 5	/* trace trap */
+#define	T_PAGEFLT	 6	/* page fault */
+#define	T_ALIGNFLT	 7	/* alignment fault */
+#define	T_DIVIDE	 8	/* integer divide fault */
+#define	T_NMI		 9	/* non-maskable interrupt */
+#define	T_OFLOW		10	/* overflow trap */
+#define	T_BOUND		11	/* bounds check fault */
+#define	T_DNA		12	/* device not available fault */
+#define	T_DOUBLEFLT	13	/* double fault */
+#define	T_FPOPFLT	14	/* fp coprocessor operand fetch fault (![P]Pro)*/
+#define	T_TSSFLT	15	/* invalid tss fault */
+#define	T_SEGNPFLT	16	/* segment not present fault */
+#define	T_STKFLT	17	/* stack fault */
+#define	T_MCA		18	/* machine check ([P]Pro) */
+#define	T_XMM		19	/* SSE FP exception */
+#define	T_RESERVED	20	/* reserved fault base */
+
+/* Trap's coming from user mode */
+#define	T_USER	0x100
+
+/* Flags kludged into the trap code */
+#define TC_TSS		0x80000000
+#define TC_FLAGMASK	(TC_TSS)
diff --git a/sys/arch/amd64/include/tss.h b/sys/arch/amd64/include/tss.h
new file mode 100644
index 00000000000..c674e0952dd
--- /dev/null
+++ b/sys/arch/amd64/include/tss.h
@@ -0,0 +1,62 @@
+/*	$OpenBSD: tss.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: tss.h,v 1.1 2003/04/26 18:39:49 fvdl Exp $	*/
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AMD64_TSS_H_
+#define _AMD64_TSS_H_
+
+/*
+ * TSS structure. Since TSS hw switching is not supported in long
+ * mode, this is mainly there for the I/O permission map in
+ * normal processes.
+ */
+
+struct x86_64_tss {
+	u_int32_t	tss_reserved1;
+	u_int64_t	tss_rsp0;
+	u_int64_t	tss_rsp1;
+	u_int64_t	tss_rsp3;
+	u_int32_t	tss_reserved2;
+	u_int32_t	tss_reserved3;
+	u_int64_t	tss_ist[7];
+	u_int32_t	tss_reserved4;
+	u_int32_t	tss_reserved5;
+	u_int16_t	tss_reserved6;
+	u_int16_t	tss_iobase;
+} __attribute__((packed));
+
+#endif /* _AMD64_TSS_H_ */
diff --git a/sys/arch/amd64/include/types.h b/sys/arch/amd64/include/types.h
new file mode 100644
index 00000000000..dc95c7e0a4e
--- /dev/null
+++ b/sys/arch/amd64/include/types.h
@@ -0,0 +1,81 @@
+/*	$OpenBSD: types.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)types.h	7.5 (Berkeley) 3/9/91
+ */
+
+#ifndef	_MACHTYPES_H_
+#define	_MACHTYPES_H_
+
+#include <sys/cdefs.h>
+
+#if defined(_KERNEL)
+typedef struct label_t {
+	long val[8];
+} label_t;
+#endif
+
+typedef unsigned long	paddr_t;
+typedef unsigned long	psize_t;
+typedef unsigned long	vaddr_t;
+typedef unsigned long	vsize_t;
+
+#define	__BIT_TYPES_DEFINED__
+typedef __signed char		int8_t;
+typedef	unsigned char		u_int8_t;
+typedef	unsigned char		uint8_t;
+typedef	short			int16_t;
+typedef	unsigned short		u_int16_t;
+typedef	unsigned short		uint16_t;
+typedef	int			int32_t;
+typedef	unsigned int		u_int32_t;
+typedef	unsigned int		uint32_t;
+typedef	long long		int64_t;
+typedef	unsigned long long	u_int64_t;
+typedef	unsigned long long	uint64_t;
+
+typedef long			register_t;
+
+/* The amd64 does not have strict alignment requirements. */
+#define	__NO_STRICT_ALIGNMENT
+
+#define	__HAVE_DEVICE_REGISTER
+#define	__HAVE_NWSCONS
+#define	__HAVE_CPU_COUNTER
+#define	__HAVE_SYSCALL_INTERN
+#define	__HAVE_MINIMAL_EMUL
+#define __HAVE_GENERIC_SOFT_INTERRUPTS
+#define __HAVE_CPU_MAXPROC
+
+#endif	/* _MACHTYPES_H_ */
diff --git a/sys/arch/amd64/include/userret.h b/sys/arch/amd64/include/userret.h
new file mode 100644
index 00000000000..4422d1b25dd
--- /dev/null
+++ b/sys/arch/amd64/include/userret.h
@@ -0,0 +1,99 @@
+/*	$OpenBSD: userret.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: userret.h,v 1.1 2003/04/26 18:39:49 fvdl Exp $	*/
+
+/*
+ * XXXfvdl same as i386 counterpart, but should probably be independent.
+ */
+
+/*-
+ * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/signalvar.h>
+#include <machine/cpu.h>
+
+static __inline void userret(struct proc *);
+
+/*
+ * Define the code needed before returning to user mode, for
+ * trap and syscall.
+ */
+static __inline void
+userret(struct proc *p)
+{
+	int sig;
+
+	while ((sig = CURSIG(p)) != 0)
+		postsig(sig);
+
+	curpriority = p->p_priority = p->p_usrpri;
+}
diff --git a/sys/arch/amd64/include/vmparam.h b/sys/arch/amd64/include/vmparam.h
new file mode 100644
index 00000000000..a7657f1bbff
--- /dev/null
+++ b/sys/arch/amd64/include/vmparam.h
@@ -0,0 +1,132 @@
+/*	$OpenBSD: vmparam.h,v 1.1 2004/01/28 01:39:39 mickey Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.1 2003/04/26 18:39:49 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)vmparam.h	5.9 (Berkeley) 5/12/91
+ */
+
+#ifndef _VMPARAM_H_
+#define _VMPARAM_H_
+
+/*
+ * Machine dependent constants for amd64.
+ */
+
+/*
+ * USRSTACK is the top (end) of the user stack. Immediately above the
+ * user stack resides the user structure, which is UPAGES long and contains
+ * the kernel stack.
+ *
+ * Immediately after the user structure is the page table map, and then
+ * kernal address space.
+ */
+#define	USRSTACK	VM_MAXUSER_ADDRESS
+
+/*
+ * Virtual memory related constants, all in bytes
+ */
+#define	MAXTSIZ		(64*1024*1024)		/* max text size */
+#ifndef DFLDSIZ
+#define	DFLDSIZ		(128*1024*1024)		/* initial data size limit */
+#endif
+#ifndef MAXDSIZ
+#define	MAXDSIZ		(1*1024*1024*1024)	/* max data size */
+#endif
+#ifndef	DFLSSIZ
+#define	DFLSSIZ		(2*1024*1024)		/* initial stack size limit */
+#endif
+#ifndef	MAXSSIZ
+#define	MAXSSIZ		(32*1024*1024)		/* max stack size */
+#endif
+
+/*
+ * Size of shared memory map
+ */
+#ifndef SHMMAXPGS
+#define SHMMAXPGS	8192
+#endif
+
+/*
+ * Size of User Raw I/O map
+ */
+#define	USRIOSIZE 	300
+
+/*
+ * The time for a process to be blocked before being very swappable.
+ * This is a number of seconds which the system takes as being a non-trivial
+ * amount of real time.  You probably shouldn't change this;
+ * it is used in subtle ways (fractions and multiples of it are, that is, like
+ * half of a ``long time'', almost a long time, etc.)
+ * It is related to human patience and other factors which don't really
+ * change over time.
+ */
+#define MAXSLP	20
+
+/*
+ * Mach derived constants
+ */
+
+/* user/kernel map constants */
+#define VM_MIN_ADDRESS		0
+#define VM_MAXUSER_ADDRESS	0x00007f7fffffc000
+#define VM_MAX_ADDRESS		0x00007fbfdfeff000
+#define VM_MIN_KERNEL_ADDRESS	0xffff800000000000
+#define VM_MAX_KERNEL_ADDRESS	0xffff800100000000
+
+#define VM_MAXUSER_ADDRESS32	0xffffc000
+
+/* virtual sizes (bytes) for various kernel submaps */
+#define VM_PHYS_SIZE		(USRIOSIZE*PAGE_SIZE)
+
+#define VM_PHYSSEG_MAX		5	/* 1 "hole" + 4 free lists */
+#define VM_PHYSSEG_STRAT	VM_PSTRAT_BIGFIRST
+#define VM_PHYSSEG_NOADD		/* can't add RAM after vm_mem_init */
+
+#define	VM_NFREELIST		2
+#define	VM_FREELIST_DEFAULT	0
+#define	VM_FREELIST_FIRST16	1
+
+/*
+ * pmap specific data stored in the vm_physmem[] array
+ */
+#define __HAVE_PMAP_PHYSSEG
+struct pmap_physseg {
+	struct pv_head *pvhead;		/* pv_head array */
+	unsigned char *attrs;		/* attrs array */
+};
+
+#endif /* _VMPARAM_H_ */