diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2018-01-07 01:08:21 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2018-01-07 01:08:21 +0000 |
| commit | f8cdee28d49d0ea1407da4123e60fa88029a8b4e (patch) | |
| tree | 55afbe3d419cd949963ab12690feb663cbfc86b9 /sys/arch/amd64/include | |
| parent | 53828664d422d437707b8d62a2031cdac6589f71 (diff) | |
Add identcpu.c and specialreg.h definitions for the new Intel/AMD MSRs
that should help mitigate spectre. This is just the detection piece, these
features are not yet used.
Part of a larger ongoing effort to mitigate meltdown/spectre. i386 will
come later; it needs some machdep.c cleanup first.
ok kettenis@
Diffstat (limited to 'sys/arch/amd64/include')
| -rw-r--r-- | sys/arch/amd64/include/cpu.h | 4 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 16 |
2 files changed, 17 insertions, 3 deletions
diff --git a/sys/arch/amd64/include/cpu.h b/sys/arch/amd64/include/cpu.h index f70193d8f21..59f99ebdc8a 100644 --- a/sys/arch/amd64/include/cpu.h +++ b/sys/arch/amd64/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.117 2017/10/23 15:41:29 mikeb Exp $ */ +/* $OpenBSD: cpu.h,v 1.118 2018/01/07 01:08:20 mlarkin Exp $ */ /* $NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $ */ /*- @@ -127,6 +127,8 @@ struct cpu_info { u_int32_t ci_feature_eflags; u_int32_t ci_feature_sefflags_ebx; u_int32_t ci_feature_sefflags_ecx; + u_int32_t ci_feature_sefflags_edx; + u_int32_t ci_feature_amdspec_ebx; u_int32_t ci_feature_tpmflags; u_int32_t ci_pnfeatset; u_int32_t ci_efeature_eax; diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 5f8da22c148..c1c0a47e46b 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.62 2017/12/06 16:26:12 fcambus Exp $ */ +/* $OpenBSD: specialreg.h,v 1.63 2018/01/07 01:08:20 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -214,6 +214,9 @@ #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ +/* SEFF EDX bits */ +#define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ +#define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ /* * Thermal and Power Management (CPUID function 0x6) EAX bits @@ -285,9 +288,13 @@ * "Advanced Power Management Information" bits (CPUID function 0x80000007): * EDX bits. */ - #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ +/* + * AMD CPUID function 0x80000008 EBX bits + */ +#define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */ + #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) #define CPUID2STEPPING(cpuid) ((cpuid) & 15) @@ -319,6 +326,11 @@ #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ #define MSR_TEST_CTL 0x033 #define MSR_IA32_FEATURE_CONTROL 0x03a +#define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ +#define SPEC_CTRL_IBRS (1ULL << 0) +#define SPEC_CTRL_STIBP (1ULL << 1) +#define MSR_PRED_CMD 0x049 /* Speculation Control IBPB */ +#define PRED_CMD_IBPB (1ULL << 0) #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ #define MSR_BBL_CR_D1 0x089 /* PII+ only */ |