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authorTed Unangst <tedu@cvs.openbsd.org>2007-06-01 22:28:22 +0000
committerTed Unangst <tedu@cvs.openbsd.org>2007-06-01 22:28:22 +0000
commit8e6616c399a7ffa90d49afd4e3bf01016b49dac8 (patch)
tree844d1977c24a04685fa6d62131acf820c7696d30 /sys/arch/amd64/include
parent88154fd1fd69bfb65f6e9bd703776f1fc823dac7 (diff)
some pentium 4 machines are 64-bit and have EST, but a different msr to
get bus clock. copy in some more code from i386 to deal with both families, and be more watchful for unknown models. fixes a panic reported by johan lindman. ok gwk
Diffstat (limited to 'sys/arch/amd64/include')
-rw-r--r--sys/arch/amd64/include/specialreg.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index fbc856244a4..568d3470051 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: specialreg.h,v 1.10 2007/05/29 06:40:15 tedu Exp $ */
+/* $OpenBSD: specialreg.h,v 1.11 2007/06/01 22:28:21 tedu Exp $ */
/* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
/* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
@@ -165,6 +165,7 @@
#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
#define MSR_APICBASE 0x01b
#define MSR_EBL_CR_POWERON 0x02a
+#define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */
#define MSR_TEST_CTL 0x033
#define MSR_BIOS_UPDT_TRIG 0x079
#define MSR_BBL_CR_D0 0x088 /* PII+ only */