fix new agp code on amd64

- internal intel graphics semi-agp chipsets need special handling in pchb.c
- re-add the i965GM device
- use the correct major device id for /dev/agp0 on amd64 (not the i386 one)

ok deraadt@

1 files changed, 26 insertions, 1 deletions

diff --git a/sys/arch/amd64/pci/pchb.c b/sys/arch/amd64/pci/pchb.c
index dfd27f45f4b..571bdc5b814 100644
--- a/sys/arch/amd64/pci/pchb.c
+++ b/sys/arch/amd64/pci/pchb.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pchb.c,v 1.12 2007/11/25 17:11:12 oga Exp $	*/
+/*	$OpenBSD: pchb.c,v 1.13 2007/11/26 10:35:42 reyk Exp $	*/
 /*	$NetBSD: pchb.c,v 1.1 2003/04/26 18:39:50 fvdl Exp $	*/
 /*
  * Copyright (c) 2000 Michael Shalayeff
@@ -166,6 +166,31 @@ pchbattach(struct device *parent, struct device *self, void *aux)
 	has_agp = 0;
 
 	switch (PCI_VENDOR(pa->pa_id)) {
+	case PCI_VENDOR_INTEL:
+		switch (PCI_PRODUCT(pa->pa_id)) {
+		case PCI_PRODUCT_INTEL_82915G_HB:
+		case PCI_PRODUCT_INTEL_82915GM_HB:
+		case PCI_PRODUCT_INTEL_82945GP_MCH:
+		case PCI_PRODUCT_INTEL_82945GM_MCH:
+		case PCI_PRODUCT_INTEL_82Q963_HB:
+		case PCI_PRODUCT_INTEL_82965_MCH:
+		case PCI_PRODUCT_INTEL_82965GM_MCH:
+			/*
+			 * The host bridge is either in GFX mode (internal
+			 * graphics) or in AGP mode. In GFX mode, we pretend
+			 * to have AGP because the graphics memory access
+			 * is very similar and the AGP GATT code will
+			 * deal with this. In the latter case, the
+			 * pci_get_capability(PCI_CAP_AGP) test below will
+			 * fire, so we do no harm by already setting the flag.
+			 */
+			has_agp = 1;
+			break;
+		}
+		break;
+	}
+
+	switch (PCI_VENDOR(pa->pa_id)) {
 	case PCI_VENDOR_AMD:
 		switch (PCI_PRODUCT(pa->pa_id)) {
 		case PCI_PRODUCT_AMD_AMD64_HT: