diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2018-08-15 02:07:36 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2018-08-15 02:07:36 +0000 |
| commit | 7319a0c386713d88685873f7a2e1f969936e4a49 (patch) | |
| tree | 6f68b818a842302fca6800812ad0493e7e110f6e /sys/arch/amd64 | |
| parent | f8657318773c909383f54a447038f8cf16fb0e4f (diff) | |
add cpuid and msr bits from
'Deep Dive: CPUID Enumeration and Architectural MSRs'
ok deraadt@
Diffstat (limited to 'sys/arch/amd64')
| -rw-r--r-- | sys/arch/amd64/amd64/identcpu.c | 3 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 10 |
2 files changed, 11 insertions, 2 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 23610e396a8..cd433d578ba 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.105 2018/08/08 05:07:46 jsg Exp $ */ +/* $OpenBSD: identcpu.c,v 1.106 2018/08/15 02:07:35 jsg Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -209,6 +209,7 @@ const struct { { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, { SEFF0EDX_IBRS, "IBRS,IBPB" }, { SEFF0EDX_STIBP, "STIBP" }, + { SEFF0EDX_L1DF, "L1DF" }, /* SEFF0EDX_ARCH_CAP (not printed) */ { SEFF0EDX_SSBD, "SSBD" }, }, cpu_tpm_eaxfeatures[] = { diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 37e9bee8f2a..5457379dc99 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.77 2018/08/08 05:07:46 jsg Exp $ */ +/* $OpenBSD: specialreg.h,v 1.78 2018/08/15 02:07:35 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -219,6 +219,7 @@ #define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */ #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ +#define SEFF0EDX_L1DF 0x10000000 /* L1D_FLUSH */ #define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */ #define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */ @@ -347,6 +348,7 @@ #define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ #define SPEC_CTRL_IBRS (1ULL << 0) #define SPEC_CTRL_STIBP (1ULL << 1) +#define SPEC_CTRL_SSBD (1ULL << 2) #define MSR_PRED_CMD 0x049 /* Speculation Control IBPB */ #define PRED_CMD_IBPB (1ULL << 0) #define MSR_BIOS_UPDT_TRIG 0x079 @@ -363,6 +365,12 @@ #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ #define MSR_ARCH_CAPABILITIES 0x10a #define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */ +#define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */ +#define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */ +#define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3) +#define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */ +#define MSR_FLUSH_CMD 0x10b +#define FLUSH_CMD_L1D_FLUSH (1ULL << 0) #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ |