Next try. ARC tree import. "New" Mips (spim) ARC compliant systems tree.

This tree will eventually suport viritualy all ARC compliant Mips systems,
that is all we can lay our hands on for porting/testing. It will supersede
the pica tree which will be removed shortly when this tree is functioning.

2 files changed, 491 insertions, 0 deletions

diff --git a/sys/arch/arc/pica/pica.h b/sys/arch/arc/pica/pica.h
new file mode 100644
index 00000000000..454e674f81f
--- /dev/null
+++ b/sys/arch/arc/pica/pica.h
@@ -0,0 +1,168 @@
+/*	$OpenBSD	*/
+/*-
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * The Mach Operating System project at Carnegie-Mellon University,
+ * Ralph Campbell and Rick Macklem.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: @(#)pica.h	8.1 (Berkeley) 6/10/93
+ *      $Id: pica.h,v 1.1 1996/06/24 09:07:18 pefo Exp $
+ */
+
+/*
+ * HISTORY
+ * Log:	pica.h,v
+ * 	Created, from the ALI specs:
+ */
+/*
+ *	File: pica.h
+ * 	Author: Per Fogelstrom
+ *	Date:	1/95
+ *
+ */
+
+#ifndef	_PICA_H_
+#define	_PICA_H_ 1
+
+/*
+ * PICA's Physical address space
+ */
+
+#define PICA_PHYS_MIN		0x00000000	/* 256 Meg */
+#define PICA_PHYS_MAX		0x0fffffff
+
+/*
+ * Memory map
+ */
+
+#define PICA_PHYS_MEMORY_START	0x00000000
+#define PICA_PHYS_MEMORY_END	0x0fffffff	/* 256 Meg in 8 slots */
+
+#define PICA_MEMORY_SIZE_REG	0xe00fffe0	/* Memory size register */
+#define	PICA_CONFIG_REG		0xe00ffff0	/* Hardware config reg  */
+
+/*
+ * I/O map
+ */
+
+#define	PICA_P_LOCAL_IO_BASE	0x80000000	/* I/O Base address */
+#define	PICA_V_LOCAL_IO_BASE	0xe0000000
+#define	PICA_S_LOCAL_IO_BASE	0x00040000	/* Size */
+#define PVLB PICA_V_LOCAL_IO_BASE
+#define	PICA_SYS_TL_BASE	(PVLB+0x0018)	/* DMA transl. table base */
+#define	PICA_SYS_TL_LIMIT	(PVLB+0x0020)	/* DMA transl. table limit */
+#define	PICA_SYS_TL_IVALID	(PVLB+0x0028)	/* DMA transl. cache inval */
+#define	PICA_SYS_DMA0_REGS	(PVLB+0x0100)	/* DMA ch0 base address */
+#define	PICA_SYS_DMA1_REGS	(PVLB+0x0120)	/* DMA ch0 base address */
+#define	PICA_SYS_DMA2_REGS	(PVLB+0x0140)	/* DMA ch0 base address */
+#define	PICA_SYS_DMA3_REGS	(PVLB+0x0160)	/* DMA ch0 base address */
+#define	PICA_SYS_IT_VALUE	(PVLB+0x0228)	/* Interval timer reload */
+#define	PICA_SYS_IT_STAT	(PVLB+0x0230)	/* Interval timer count */
+#define	PICA_SYS_ISA_VECTOR	(PVLB+0x0238)	/* ISA Interrupt vector */
+#define	PICA_SYS_EXT_IMASK	(PVLB+0x00e8)	/* External int enable mask */
+#define	PICA_SYS_SONIC		(PVLB+0x1000)	/* SONIC base address */
+#define	PICA_SYS_SCSI		(PVLB+0x2000)	/* SCSI base address */
+#define	PICA_SYS_FLOPPY		(PVLB+0x3000)	/* Floppy base address */
+#define	PICA_SYS_CLOCK		(PVLB+0x4000)	/* Clock base address */
+#define	PICA_SYS_KBD		(PVLB+0x5000)	/* Keybrd/mouse base address */
+#define	PICA_SYS_COM1		(PVLB+0x6000)	/* Com port 1 */
+#define	PICA_SYS_COM2		(PVLB+0x7000)	/* Com port 2 */
+#define	PICA_SYS_PAR1		(PVLB+0x8000)	/* Parallel port 1 */
+#define	PICA_SYS_NVRAM		(PVLB+0x9000)	/* Unprotected NV-ram */
+#define	PICA_SYS_PNVRAM		(PVLB+0xa000)	/* Protected NV-ram */
+#define	PICA_SYS_NVPROM		(PVLB+0xb000)	/* Read only NV-ram */
+#define	PICA_SYS_SOUND		(PVLB+0xc000)	/* Sound port */
+
+#define	PICA_SYS_ISA_AS		(PICA_V_ISA_IO+0x70)
+
+#define	PICA_P_DRAM_CONF	0x800e0000	/* Dram config registers */
+#define	PICA_V_DRAM_CONF	0xe00e0000
+#define	PICA_S_DRAM_CONF	0x00020000
+
+#define	PICA_P_INT_SOURCE	0xf0000000	/* Interrupt src registers */
+#define	PICA_V_INT_SOURCE	PICA_V_LOCAL_IO_BASE+PICA_S_LOCAL_IO_BASE
+#define	PICA_S_INT_SOURCE	0x00001000
+#define PVIS PICA_V_INT_SOURCE
+#define	PICA_SYS_LB_IS		(PVIS+0x0000)	/* Local bus int source */
+#define	PICA_SYS_LB_IE		(PVIS+0x0002)	/* Local bus int enables */
+#define PICA_SYS_LB_IE_PAR1	0x0001		/* Parallel port enable */
+#define	PICA_SYS_LB_IE_FLOPPY	0x0002		/* Floppy ctrl enable */
+#define	PICA_SYS_LB_IE_SOUND	0x0004		/* Sound port enable */
+#define	PICA_SYS_LB_IE_VIDEO	0x0008		/* Video int enable */
+#define	PICA_SYS_LB_IE_SONIC	0x0010		/* Ethernet ctrl enable */
+#define	PICA_SYS_LB_IE_SCSI	0x0020		/* Scsi crtl enable */
+#define PICA_SYS_LB_IE_KBD	0x0040		/* Keyboard ctrl enable */
+#define PICA_SYS_LB_IE_MOUSE	0x0080		/* Mouse ctrl enable */
+#define	PICA_SYS_LB_IE_COM1	0x0100		/* Serial port 1 enable */
+#define	PICA_SYS_LB_IE_COM2	0x0200		/* Serial port 2 enable */
+
+#define	PICA_P_LOCAL_VIDEO_CTRL	0x60000000	/* Local video control */
+#define	PICA_V_LOCAL_VIDEO_CTRL	0xe0200000
+#define	PICA_S_LOCAL_VIDEO_CTRL	0x00200000
+
+#define	PICA_P_EXTND_VIDEO_CTRL	0x60200000	/* Extended video control */
+#define	PICA_V_EXTND_VIDEO_CTRL	0xe0400000
+#define	PICA_S_EXTND_VIDEO_CTRL	0x00200000
+
+#define	PICA_P_LOCAL_VIDEO	0x40000000	/* Local video memory */
+#define	PICA_V_LOCAL_VIDEO	0xe0800000
+#define	PICA_S_LOCAL_VIDEO	0x00800000
+
+#define	PICA_P_ISA_IO		0x90000000	/* ISA I/O control */
+#define	PICA_V_ISA_IO		0xe2000000
+#define	PICA_S_ISA_IO		0x01000000
+
+#define	PICA_P_ISA_MEM		0x91000000	/* ISA Memory control */
+#define	PICA_V_ISA_MEM		0xe3000000
+#define	PICA_S_ISA_MEM		0x01000000
+
+/*
+ *  Addresses used by various display drivers.
+ */
+#define MONO_BASE	(PICA_V_LOCAL_VIDEO_CTRL + 0x3B4)
+#define MONO_BUF	(PICA_V_LOCAL_VIDEO + 0xB0000)
+#define CGA_BASE	(PICA_V_LOCAL_VIDEO_CTRL + 0x3D4)
+#define CGA_BUF		(PICA_V_LOCAL_VIDEO + 0xB8000)
+
+/*
+ *  Interrupt vector descriptor for device on pica bus.
+ */
+struct pica_int_desc {
+	int		int_mask;	/* Mask used in PICA_SYS_LB_IE */
+	intr_handler_t	int_hand;	/* Interrupt handler */
+	void		*param;		/* Parameter to send to handler */
+	int		spl_mask;	/* Spl mask for interrupt */
+};
+
+int	pica_intrnull __P((void *));
+#endif	/* _PICA_H_ */
diff --git a/sys/arch/arc/pica/picabus.c b/sys/arch/arc/pica/picabus.c
new file mode 100644
index 00000000000..f6058cf8b4d
--- /dev/null
+++ b/sys/arch/arc/pica/picabus.c
@@ -0,0 +1,323 @@
+/*	$OpenBSD: picabus.c,v 1.1 1996/06/24 09:07:18 pefo Exp $	*/
+/*	$NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp $	*/
+
+/*
+ * Copyright (c) 1994, 1995 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ * Author: Per Fogelstrom. (Mips R4x00)
+ * 
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+#include <sys/param.h>
+#include <sys/device.h>
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+#include <machine/autoconf.h>
+
+#include <arc/pica/pica.h>
+#include <arc/arc/arctype.h>
+
+struct pica_softc {
+	struct	device sc_dv;
+	struct	abus sc_bus;
+	struct	pica_dev *sc_devs;
+};
+
+/* Definition of the driver for autoconfig. */
+int	picamatch(struct device *, void *, void *);
+void	picaattach(struct device *, struct device *, void *);
+int	picaprint(void *, char *);
+
+struct cfattach pica_ca = {
+	sizeof(struct pica_softc), picamatch, picaattach
+};
+struct cfdriver pica_cd = {
+	NULL, "pica", DV_DULL, NULL, 0
+};
+
+void	pica_intr_establish __P((struct confargs *, int (*)(void *), void *));
+void	pica_intr_disestablish __P((struct confargs *));
+caddr_t	pica_cvtaddr __P((struct confargs *));
+int	pica_matchname __P((struct confargs *, char *));
+int	pica_iointr __P((void *));
+int	pica_clkintr __P((unsigned, unsigned, unsigned, unsigned));
+
+extern int cputype;
+
+/*
+ *  Interrupt dispatch table.
+ */
+struct pica_int_desc int_table[] = {
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  0 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  1 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  2 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  3 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  4 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  5 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  6 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  7 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  8 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /*  9 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 10 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 11 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 12 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 13 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 14 */
+	{0, pica_intrnull, (void *)NULL, 0 },  /* 15 */
+};
+
+struct pica_dev {
+	struct confargs	ps_ca;
+	u_int		ps_mask;
+	intr_handler_t	ps_handler;
+	void 		*ps_base;
+};
+#ifdef ACER_PICA_61
+struct pica_dev acer_pica_61_cpu[] = {
+	{{ "dallas_rtc",0, 0, },
+	   0,			 pica_intrnull, (void *)PICA_SYS_CLOCK, },
+	{{ "lpt",	1, 0, },
+	   PICA_SYS_LB_IE_PAR1,	 pica_intrnull, (void *)PICA_SYS_PAR1, },
+	{{ "fdc",	2, 0, },
+	   PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
+	{{ NULL,	3, NULL, },
+	   0, pica_intrnull, (void *)NULL, },
+	{{ NULL,	4, NULL, },
+	   0, pica_intrnull, (void *)NULL, },
+	{{ "sonic",	5, 0, },
+	   PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
+	{{ "asc",	6, 0, },
+	   PICA_SYS_LB_IE_SCSI,  pica_intrnull, (void *)PICA_SYS_SCSI, },
+	{{ "pc",	7, 0, },
+	   PICA_SYS_LB_IE_KBD,	 pica_intrnull, (void *)PICA_SYS_KBD, },
+	{{ "pms",	8, NULL, },
+	   PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
+	{{ "com",	9, 0, },
+	   PICA_SYS_LB_IE_COM1,	 pica_intrnull, (void *)PICA_SYS_COM1, },
+	{{ "com",      10, 0, },
+	   PICA_SYS_LB_IE_COM2,	 pica_intrnull, (void *)PICA_SYS_COM2, },
+	{{ NULL,       -1, NULL, },
+	   0, NULL, (void *)NULL, },
+};
+#endif
+
+struct pica_dev *pica_cpu_devs[] = {
+        NULL,                   /* Unused */
+#ifdef ACER_PICA_61
+        acer_pica_61_cpu,       /* Acer PICA */
+#else
+	NULL,
+#endif
+};
+int npica_cpu_devs = sizeof pica_cpu_devs / sizeof pica_cpu_devs[0];
+
+int local_int_mask = 0;	/* Local interrupt enable mask */
+
+int
+picamatch(parent, cfdata, aux)
+	struct device *parent;
+	void *cfdata;
+	void *aux;
+{
+	struct cfdata *cf = cfdata;
+	struct confargs *ca = aux;
+
+        /* Make sure that we're looking for a PICA. */
+        if (strcmp(ca->ca_name, pica_cd.cd_name) != 0)
+                return (0);
+
+        /* Make sure that unit exists. */
+	if (cf->cf_unit != 0 ||
+	    cputype > npica_cpu_devs || pica_cpu_devs[cputype] == NULL)
+		return (0);
+
+	return (1);
+}
+
+void
+picaattach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	struct pica_softc *sc = (struct pica_softc *)self;
+	struct confargs *nca;
+	int i;
+
+	printf("\n");
+
+	/* keep our CPU device description handy */
+	sc->sc_devs = pica_cpu_devs[cputype];
+
+	/* set up interrupt handlers */
+	set_intr(INT_MASK_1, pica_iointr, 2);
+
+	sc->sc_bus.ab_dv = (struct device *)sc;
+	sc->sc_bus.ab_type = BUS_PICA;
+	sc->sc_bus.ab_intr_establish = pica_intr_establish;
+	sc->sc_bus.ab_intr_disestablish = pica_intr_disestablish;
+	sc->sc_bus.ab_cvtaddr = pica_cvtaddr;
+	sc->sc_bus.ab_matchname = pica_matchname;
+
+	/* Initialize PICA Dma */
+	picaDmaInit();
+
+	/* Try to configure each PICA attached device */
+	for (i = 0; sc->sc_devs[i].ps_ca.ca_slot >= 0; i++) {
+
+		if(sc->sc_devs[i].ps_ca.ca_name == NULL)
+			continue; /* Empty slot */
+
+		nca = &sc->sc_devs[i].ps_ca;
+		nca->ca_bus = &sc->sc_bus;
+
+		/* Tell the autoconfig machinery we've found the hardware. */
+		config_found(self, nca, picaprint);
+	}
+}
+
+int
+picaprint(aux, pnp)
+	void *aux;
+	char *pnp;
+{
+	struct confargs *ca = aux;
+
+        if (pnp)
+                printf("%s at %s", ca->ca_name, pnp);
+        printf(" slot %ld offset 0x%lx", ca->ca_slot, ca->ca_offset);
+        return (UNCONF);
+}
+
+caddr_t
+pica_cvtaddr(ca)
+	struct confargs *ca;
+{
+	struct pica_softc *sc = pica_cd.cd_devs[0];
+
+	return(sc->sc_devs[ca->ca_slot].ps_base + ca->ca_offset);
+
+}
+
+void
+pica_intr_establish(ca, handler, val)
+	struct confargs *ca;
+	intr_handler_t handler;
+	void *val;
+{
+	struct pica_softc *sc = pica_cd.cd_devs[0];
+
+	int slot;
+
+	slot = ca->ca_slot;
+	if(slot == 0) {		/* Slot 0 is special, clock */
+		set_intr(INT_MASK_4, pica_clkintr, 1);
+	}
+
+	if(int_table[slot].int_mask != 0) {
+		panic("pica intr already set");
+	}
+	else {
+		int_table[slot].int_mask = sc->sc_devs[slot].ps_mask;;
+		local_int_mask |= int_table[slot].int_mask;
+		int_table[slot].int_hand = handler;
+		int_table[slot].param = val;
+	}
+	out16(PICA_SYS_LB_IE, local_int_mask);
+}
+
+void
+pica_intr_disestablish(ca)
+	struct confargs *ca;
+{
+	struct pica_softc *sc = pica_cd.cd_devs[0];
+
+	int slot;
+
+	slot = ca->ca_slot;
+	if(slot = 0) {		/* Slot 0 is special, clock */
+	}
+	else {
+		local_int_mask &= ~int_table[slot].int_mask;
+		int_table[slot].int_mask = 0;
+		int_table[slot].int_hand = pica_intrnull;
+		int_table[slot].param = (void *)NULL;
+	}
+}
+
+int
+pica_matchname(ca, name)
+	struct confargs *ca;
+	char *name;
+{
+	return (strcmp(name, ca->ca_name) == 0);
+}
+
+int
+pica_intrnull(val)
+	void *val;
+{
+	panic("uncaught PICA intr for slot %d\n", val);
+}
+
+/*
+ *   Handle pica i/o interrupt.
+ */
+int
+pica_iointr(val)
+	void *val;
+{
+	int vector;
+
+	while((vector = inb(PVIS) >> 2) != 0) {
+		(*int_table[vector].int_hand)(int_table[vector].param);
+	}
+	return(~0);  /* Dont reenable */
+}
+
+/*
+ * Handle pica interval clock interrupt.
+ */
+int
+pica_clkintr(mask, pc, statusReg, causeReg)
+	unsigned mask;
+	unsigned pc;
+	unsigned statusReg;
+	unsigned causeReg;
+{
+	struct clockframe cf;
+	int temp;
+
+	temp = inw(PICA_SYS_IT_STAT);
+	cf.pc = pc;
+	cf.sr = statusReg;
+	hardclock(&cf);
+
+	/* Re-enable clock interrupts */
+	splx(INT_MASK_4 | SR_INT_ENAB);
+
+	return(~INT_MASK_4); /* Keep clock interrupts enabled */
+}
+