Changes and bugfixes in memory handling system.

Sysmap too small.
Alloc map page failure.
Support for discontigous memory. Needs testing.
Name changes. "Mach" removal.
Kernel memory size increased.

15 files changed, 443 insertions, 229 deletions

diff --git a/sys/arch/arc/arc/cpu.c b/sys/arch/arc/arc/cpu.c
index 5917761ebf6..cc24baf78d4 100644
--- a/sys/arch/arc/arc/cpu.c
+++ b/sys/arch/arc/arc/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.1 1996/06/24 09:07:20 pefo Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.2 1996/08/26 11:11:52 pefo Exp $	*/
 
 /*
  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -86,7 +86,7 @@ cpuattach(parent, dev, aux)
 		printf("MIPS R6000 CPU");
 		break;
 	case MIPS_R4000:
-		if(machPrimaryInstCacheSize == 16384)
+		if(CpuPrimaryInstCacheSize == 16384)
 			printf("MIPS R4400 CPU");
 		else
 			printf("MIPS R4000 CPU");
@@ -181,8 +181,12 @@ cpuattach(parent, dev, aux)
 	printf(" Rev. %d.%d", fpu_id.cpu.cp_majrev, fpu_id.cpu.cp_minrev);
 	printf("\n");
 
-	printf("        Primary cache size: %dkb Instruction, %dkb Data.\n",
-		machPrimaryInstCacheSize / 1024,
-		machPrimaryDataCacheSize / 1024);
+	printf("        Primary cache size: %dkb Instruction, %dkb Data.",
+		CpuPrimaryInstCacheSize / 1024,
+		CpuPrimaryDataCacheSize / 1024);
+	if(CpuTwoWayCache)
+		printf("Two way set associative.\n");
+	else
+		printf("Direct mapped.\n");
 }
 
diff --git a/sys/arch/arc/arc/locore.S b/sys/arch/arc/arc/locore.S
index 38f2ee06538..60c04307fed 100644
--- a/sys/arch/arc/arc/locore.S
+++ b/sys/arch/arc/arc/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.2 1996/07/30 20:24:15 pefo Exp $	*/
+/*	$OpenBSD: locore.S,v 1.3 1996/08/26 11:11:53 pefo Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -50,7 +50,7 @@
  *	v 1.1 89/07/10 14:27:41 nelson Exp  SPRITE (DECWRL)
  *
  *	from: @(#)locore.s	8.5 (Berkeley) 1/4/94
- *	$Id: locore.S,v 1.2 1996/07/30 20:24:15 pefo Exp $
+ *	$Id: locore.S,v 1.3 1996/08/26 11:11:53 pefo Exp $
  */
 
 /*
@@ -163,7 +163,7 @@ start:
  */
 	.globl	onfault_table
 	.data
-	.align	2
+	.align	3
 onfault_table:
 	.word	0		# invalid index number
 #define BADERR		1
@@ -702,7 +702,7 @@ LEAF(suiword)
 	sw	a1, 0(a0)		# store word
 	sw	zero, UADDR+U_PCB_ONFAULT
 	move	v0, zero
-	b	MachFlushICache		# NOTE: this should not clobber v0!
+	b	R4K_FlushICache		# NOTE: this should not clobber v0!
 	li	a1, 4			# size of word
 END(suiword)
 
@@ -1416,7 +1416,7 @@ END(MachUserIntr)
 
 /*----------------------------------------------------------------------------
  *
- * MachTLBMInvalidException --
+ * MachTLBInvalidException --
  *
  *	Handle a TLB invalid exception from kernel mode in kernel space.
  *	The BaddVAddr, Context, and EntryHi registers contain the failed
@@ -1772,11 +1772,11 @@ END(wbflush)
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBWriteIndexed --
+ * R4K_TLBWriteIndexed --
  *
  *	Write the given entry into the TLB at the given index.
  *
- *	MachTLBWriteIndexed(index, tlb)
+ *	R4K_TLBWriteIndexed(index, tlb)
  *		unsigned index;
  *		tlb *tlb;
  *
@@ -1788,7 +1788,7 @@ END(wbflush)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBWriteIndexed)
+LEAF(R4K_TLBWriteIndexed)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
 	nop
@@ -1815,15 +1815,15 @@ LEAF(MachTLBWriteIndexed)
 	dmtc0	zero, COP_0_TLB_PG_MASK	# Default mask value.
 	j	ra
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
-END(MachTLBWriteIndexed)
+END(R4K_TLBWriteIndexed)
 
 /*--------------------------------------------------------------------------
  *
- * MachSetPID --
+ * R4K_SetPID --
  *
  *	Write the given pid into the TLB pid reg.
  *
- *	MachSetPID(pid)
+ *	R4K_SetPID(pid)
  *		int pid;
  *
  * Results:
@@ -1834,19 +1834,19 @@ END(MachTLBWriteIndexed)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachSetPID)
+LEAF(R4K_SetPID)
 	dmtc0	a0, COP_0_TLB_HI		# Write the hi reg value
 	j	ra
 	nop
-END(MachSetPID)
+END(R4K_SetPID)
 
 /*--------------------------------------------------------------------------
  *
- * MachSetWIRED --
+ * R4K_SetWIRED --
  *
  *	Write the given value into the TLB wired reg.
  *
- *	MachSetPID(wired)
+ *	R4K_SetPID(wired)
  *		int wired;
  *
  * Results:
@@ -1857,19 +1857,19 @@ END(MachSetPID)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachSetWIRED)
+LEAF(R4K_SetWIRED)
 	mtc0	a0, COP_0_TLB_WIRED
 	j	ra
 	nop
-END(MachSetWIRED)
+END(R4K_SetWIRED)
 
 /*--------------------------------------------------------------------------
  *
- * MachGetWIRED --
+ * R4K_GetWIRED --
  *
  *	Get the value from the TLB wired reg.
  *
- *	MachGetWIRED(void)
+ *	R4K_GetWIRED(void)
  *
  * Results:
  *	Value of wired reg.
@@ -1879,20 +1879,20 @@ END(MachSetWIRED)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachGetWIRED)
+LEAF(R4K_GetWIRED)
 	mfc0	v0, COP_0_TLB_WIRED
 	j	ra
 	nop
-END(MachGetWIRED)
+END(R4K_GetWIRED)
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBFlush --
+ * R4K_TLBFlush --
  *
  *	Flush the "random" entries from the TLB.
  *	Uses "wired" register to determine what register to start with.
  *
- *	MachTLBFlush()
+ *	R4K_TLBFlush()
  *
  * Results:
  *	None.
@@ -1902,15 +1902,15 @@ END(MachGetWIRED)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBFlush)
+LEAF(R4K_TLBFlush)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
 	mfc0	t1, COP_0_TLB_WIRED
 	li	t2, VMNUM_TLB_ENTRIES
 	li	v0, CACHED_MEMORY_ADDR	# invalid address
-	dmfc0	t0, COP_0_TLB_HI		# Save the PID
+	dmfc0	t0, COP_0_TLB_HI	# Save the PID
 
-	dmtc0	v0, COP_0_TLB_HI		# Mark entry high as invalid
+	dmtc0	v0, COP_0_TLB_HI	# Mark entry high as invalid
 	dmtc0	zero, COP_0_TLB_LO0	# Zero out low entry0.
 	dmtc0	zero, COP_0_TLB_LO1	# Zero out low entry1.
 	mtc0	zero, COP_0_TLB_PG_MASK	# Zero out mask entry.
@@ -1919,26 +1919,26 @@ LEAF(MachTLBFlush)
  */
 1:
 	mtc0	t1, COP_0_TLB_INDEX	# Set the index register.
-	addu	t1, t1, 1			# Increment index.
-	tlbwi					# Write the TLB entry.
+	addu	t1, t1, 1		# Increment index.
+	tlbwi				# Write the TLB entry.
 	nop
 	nop
 	bne	t1, t2, 1b
 	nop
 
-	dmtc0	t0, COP_0_TLB_HI		# Restore the PID
+	dmtc0	t0, COP_0_TLB_HI	# Restore the PID
 	j	ra
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
-END(MachTLBFlush)
+END(R4K_TLBFlush)
 
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBFlushAddr --
+ * R4K_TLBFlushAddr --
  *
  *	Flush any TLB entries for the given address and TLB PID.
  *
- *	MachTLBFlushAddr(TLBhi)
+ *	R4K_TLBFlushAddr(TLBhi)
  *		unsigned TLBhi;
  *
  * Results:
@@ -1949,26 +1949,26 @@ END(MachTLBFlush)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBFlushAddr)
+LEAF(R4K_TLBFlushAddr)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
 	nop
 	li	v0, (PG_HVPN | PG_ASID)
-	and	a0, a0, v0			# Make shure valid hi value.
-	dmfc0	t0, COP_0_TLB_HI		# Get current PID
-	dmtc0	a0, COP_0_TLB_HI		# look for addr & PID
+	and	a0, a0, v0		# Make shure valid hi value.
+	dmfc0	t0, COP_0_TLB_HI	# Get current PID
+	dmtc0	a0, COP_0_TLB_HI	# look for addr & PID
 	nop
 	nop
 	nop
-	tlbp					# Probe for the entry.
+	tlbp				# Probe for the entry.
 	nop
-	nop					# Delay for effect
+	nop				# Delay for effect
 	nop
 	mfc0	v0, COP_0_TLB_INDEX	# See what we got
 	li	t1, CACHED_MEMORY_ADDR	# Load invalid entry.
-	bltz	v0, 1f				# index < 0 => !found
+	bltz	v0, 1f			# index < 0 => !found
 	nop
-	dmtc0	t1, COP_0_TLB_HI		# Mark entry high as invalid
+	dmtc0	t1, COP_0_TLB_HI	# Mark entry high as invalid
 
 	dmtc0	zero, COP_0_TLB_LO0	# Zero out low entry.
 	dmtc0	zero, COP_0_TLB_LO1	# Zero out low entry.
@@ -1979,18 +1979,18 @@ LEAF(MachTLBFlushAddr)
 	nop
 	nop
 1:
-	dmtc0	t0, COP_0_TLB_HI		# restore PID
+	dmtc0	t0, COP_0_TLB_HI	# restore PID
 	j	ra
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
-END(MachTLBFlushAddr)
+END(R4K_TLBFlushAddr)
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBUpdate --
+ * R4K_TLBUpdate --
  *
  *	Update the TLB if highreg is found; otherwise, enter the data.
  *
- *	MachTLBUpdate(virpageadr, lowregx)
+ *	R4K_TLBUpdate(virpageadr, lowregx)
  *		unsigned virpageadr, lowregx;
  *
  * Results:
@@ -2001,85 +2001,85 @@ END(MachTLBFlushAddr)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBUpdate)
+LEAF(R4K_TLBUpdate)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
-	and	t1, a0, 0x1000			# t1 = Even/Odd flag
+	and	t1, a0, 0x1000		# t1 = Even/Odd flag
 	li	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0
-	dmfc0	t0, COP_0_TLB_HI		# Save current PID
-	dmtc0	a0, COP_0_TLB_HI		# Init high reg
-	and	a2, a1, PG_G			# Copy global bit
+	dmfc0	t0, COP_0_TLB_HI	# Save current PID
+	dmtc0	a0, COP_0_TLB_HI	# Init high reg
+	and	a2, a1, PG_G		# Copy global bit
 	nop
 	nop
-	tlbp					# Probe for the entry.
+	tlbp				# Probe for the entry.
 	dsll	a1, a1, 34
 	dsrl	a1, a1, 34
-	bne	t1, zero, 2f			# Decide even odd
+	bne	t1, zero, 2f		# Decide even odd
 	mfc0	v0, COP_0_TLB_INDEX	# See what we got
 # EVEN
 	nop
-	bltz	v0, 1f				# index < 0 => !found
+	bltz	v0, 1f			# index < 0 => !found
 	nop
 
-	tlbr					# update, read entry first
+	tlbr				# update, read entry first
 	nop
 	nop
 	nop
-	dmtc0	a1, COP_0_TLB_LO0		# init low reg0.
+	dmtc0	a1, COP_0_TLB_LO0	# init low reg0.
 	nop
-	tlbwi					# update slot found
+	tlbwi				# update slot found
 	b	4f
 	nop
 1:
 	mtc0	zero, COP_0_TLB_PG_MASK	# init mask.
-	dmtc0	a0, COP_0_TLB_HI		# init high reg.
-	dmtc0	a1, COP_0_TLB_LO0		# init low reg0.
-	dmtc0	a2, COP_0_TLB_LO1		# init low reg1.
+	dmtc0	a0, COP_0_TLB_HI	# init high reg.
+	dmtc0	a1, COP_0_TLB_LO0	# init low reg0.
+	dmtc0	a2, COP_0_TLB_LO1	# init low reg1.
 	nop
-	tlbwr					# enter into a random slot
+	tlbwr				# enter into a random slot
 	b	4f
 	nop
 # ODD
 2:
 	nop
-	bltz	v0, 3f				# index < 0 => !found
+	bltz	v0, 3f			# index < 0 => !found
 	nop
 
-	tlbr					# read the entry first
+	tlbr				# read the entry first
 	nop
 	nop
 	nop
-	dmtc0	a1, COP_0_TLB_LO1		# init low reg1.
+	dmtc0	a1, COP_0_TLB_LO1	# init low reg1.
 	nop
-	tlbwi					# update slot found
+	tlbwi				# update slot found
 	b	4f
 	nop
 3:
 	mtc0	zero, COP_0_TLB_PG_MASK	# init mask.
-	dmtc0	a0, COP_0_TLB_HI		# init high reg.
-	dmtc0	a2, COP_0_TLB_LO0		# init low reg0.
-	dmtc0	a1, COP_0_TLB_LO1		# init low reg1.
+	dmtc0	a0, COP_0_TLB_HI	# init high reg.
+	dmtc0	a2, COP_0_TLB_LO0	# init low reg0.
+	dmtc0	a1, COP_0_TLB_LO1	# init low reg1.
 	nop
-	tlbwr					# enter into a random slot
+	tlbwr				# enter into a random slot
 
-4:						# Make shure pipeline
-	nop					# advances before we
-	nop					# uses the tlb.
+4:					# Make shure pipeline
+	nop				# advances before we
+	nop				# uses the tlb.
 	nop
 	nop
-	dmtc0	t0, COP_0_TLB_HI		# restore PID
+	dmtc0	t0, COP_0_TLB_HI	# restore PID
 	j	ra
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
-END(MachTLBUpdate)
+END(R4K_TLBUpdate)
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBRead --
+ * R4K_TLBRead --
  *
  *	Read the TLB entry.
  *
- *	MachTLBRead(entry, tlb)
+ *	R4K_TLBRead(entry, tlb)
  *		unsigned entry;
  *		struct tlb *tlb;
  *
@@ -2091,41 +2091,41 @@ END(MachTLBUpdate)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBRead)
+LEAF(R4K_TLBRead)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
 	nop
 	nop
 	nop
-	dmfc0	t0, COP_0_TLB_HI		# Get current PID
+	dmfc0	t0, COP_0_TLB_HI	# Get current PID
 
 	mtc0	a0, COP_0_TLB_INDEX	# Set the index register
 	nop
-	tlbr					# Read from the TLB
+	tlbr				# Read from the TLB
 	nop
 	nop
 	nop
 	mfc0	t2, COP_0_TLB_PG_MASK	# fetch the hi entry
-	dmfc0	t3, COP_0_TLB_HI		# fetch the hi entry
-	dmfc0	t4, COP_0_TLB_LO0		# See what we got
-	dmfc0	t5, COP_0_TLB_LO1		# See what we got
-	dmtc0	t0, COP_0_TLB_HI		# restore PID
+	dmfc0	t3, COP_0_TLB_HI	# fetch the hi entry
+	dmfc0	t4, COP_0_TLB_LO0	# See what we got
+	dmfc0	t5, COP_0_TLB_LO1	# See what we got
+	dmtc0	t0, COP_0_TLB_HI	# restore PID
 	nop
 	nop
-	nop					# wait for PID active
+	nop				# wait for PID active
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
 	sw	t2, 0(a1)
 	sw	t3, 4(a1)
 	sw	t4, 8(a1)
 	j	ra
 	sw	t5, 12(a1)
-END(MachTLBRead)
+END(R4K_TLBRead)
 
 /*--------------------------------------------------------------------------
  *
- * MachTLBGetPID --
+ * R4K_TLBGetPID --
  *
- *	MachTLBGetPID()
+ *	R4K_TLBGetPID()
  *
  * Results:
  *	Returns the current TLB pid reg.
@@ -2135,11 +2135,11 @@ END(MachTLBRead)
  *
  *--------------------------------------------------------------------------
  */
-LEAF(MachTLBGetPID)
-	dmfc0	v0, COP_0_TLB_HI		# get PID
+LEAF(R4K_TLBGetPID)
+	dmfc0	v0, COP_0_TLB_HI	# get PID
 	j	ra
-	and	v0, v0, VMTLB_PID		# mask off PID
-END(MachTLBGetPID)
+	and	v0, v0, VMTLB_PID	# mask off PID
+END(R4K_TLBGetPID)
 
 
 /*----------------------------------------------------------------------------
@@ -2162,16 +2162,16 @@ END(MachTLBGetPID)
  */
 LEAF(MachSwitchFPState)
 	mfc0	t1, COP_0_STATUS_REG	# Save old SR
-	li	t0, SR_COP_1_BIT		# enable the coprocessor
+	li	t0, SR_COP_1_BIT	# enable the coprocessor
 	mtc0	t0, COP_0_STATUS_REG
 
-	beq	a0, zero, 1f			# skip save if NULL pointer
+	beq	a0, zero, 1f		# skip save if NULL pointer
 	nop
 /*
  * First read out the status register to make sure that all FP operations
  * have completed.
  */
-	lw	a0, P_ADDR(a0)			# get pointer to pcb for proc
+	lw	a0, P_ADDR(a0)		# get pointer to pcb for proc
 	cfc1	t0, FPC_CSR		# stall til FP done
 	cfc1	t0, FPC_CSR		# now get status
 	li	t3, ~SR_COP_1_BIT
@@ -2446,54 +2446,62 @@ END(MachFPTrap)
 
 /*----------------------------------------------------------------------------
  *
- * MachConfigCache --
+ * R4K_ConfigCache --
  *
  *	Size the caches.
- *	NOTE: should only be called from mach_init().
+ *	NOTE: should only be called from mips_init().
  *
  * Results:
  *     	None.
  *
  * Side effects:
- *	The size of the data cache is stored into machPrimaryDataCacheSize.
- *	The size of instruction cache is stored into machPrimaryInstCacheSize.
- *	Alignment mask for cache aliasing test is stored in machCacheAliasMask.
+ *	The size of the data cache is stored into CpuPrimaryDataCacheSize.
+ *	The size of instruction cache is stored into CpuPrimaryInstCacheSize.
+ *	Alignment mask for cache aliasing test is stored in CpuCacheAliasMask.
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachConfigCache)
+LEAF(R4K_ConfigCache)
+	.set	noreorder
 	mfc0	v0, COP_0_CONFIG		# Get configuration register
-	nop
+	mfc0	v1, COP_0_PRID
 	srl	t1, v0, 9			# Get I cache size.
 	and	t1, 3
 	li	t2, 4096
 	sllv	t2, t2, t1
-	sw	t2, machPrimaryDataCacheSize
+	sw	t2, CpuPrimaryDataCacheSize
 	addiu	t2, -1
 	and	t2, ~(NBPG - 1)
-	sw	t2, machCacheAliasMask
+	sw	t2, CpuCacheAliasMask
 
 	and	t2, v0, 0x20
 	srl	t2, t2, 1
 	addu	t2, t2, 16
-	sw	t2, machPrimaryDataCacheLSize
+	sw	t2, CpuPrimaryDataCacheLSize
 
 	srl	t1, v0, 6			# Get I cache size.
 	and	t1, 3
 	li	t2, 4096
 	sllv	t2, t2, t1
-	sw	t2, machPrimaryInstCacheSize
+	sw	t2, CpuPrimaryInstCacheSize
 
 	and	t2, v0, 0x10
 	addu	t2, t2, 16
-	sw	t2, machPrimaryInstCacheLSize
+	sw	t2, CpuPrimaryInstCacheLSize
+	and	v1, 0xff00
+	li	t1, (MIPS_R4600 << 4)
+	li	t2, 1
+	bnel	v1, t1, 1f
+	li	t2, 0
+1:
+	sw	t2, CpuTwoWayCache
 	j	ra
 	nop
-END(MachConfigCache)
+END(R4K_ConfigCache)
 
 /*----------------------------------------------------------------------------
  *
- * MachFlushCache --
+ * R4K_FlushCache --
  *
  *	Flush the caches. Assumes a line size of 16 bytes for speed.
  *
@@ -2505,11 +2513,13 @@ END(MachConfigCache)
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachFlushCache)
-	lw	t1, machPrimaryInstCacheSize
-	lw	t2, machPrimaryDataCacheSize
- #	lw	t3, machPrimaryInstCacheLSize
- #	lw	t4, machPrimaryDataCacheLSize
+LEAF(R4K_FlushCache)
+	.set	noreorder
+	lw	v0, CpuTwoWayCache
+	lw	t1, CpuPrimaryInstCacheSize
+	lw	t2, CpuPrimaryDataCacheSize
+ #	lw	t3, CpuPrimaryInstCacheLSize
+ #	lw	t4, CpuPrimaryDataCacheLSize
 /*
  * Flush the instruction cache.
  */
@@ -2548,13 +2558,13 @@ LEAF(MachFlushCache)
 
 	j	ra
 	nop
-END(MachFlushCache)
+END(R4K_FlushCache)
 
 /*----------------------------------------------------------------------------
  *
- * MachFlushICache --
+ * R4K_FlushICache --
  *
- *	void MachFlushICache(addr, len)
+ *	void R4K_FlushICache(addr, len)
  *		vm_offset_t addr, len;
  *
  *	Flush instruction cache for range of addr to addr + len - 1.
@@ -2570,7 +2580,7 @@ END(MachFlushCache)
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachFlushICache)
+LEAF(R4K_FlushICache)
 	addu	a1, 127		# Align
 	srl	a1, a1, 7	# Number of unrolled loops
 1:
@@ -2588,13 +2598,13 @@ LEAF(MachFlushICache)
 
 	j	ra
 	nop
-END(MachFlushICache)
+END(R4K_FlushICache)
 
 /*----------------------------------------------------------------------------
  *
- * MachFlushDCache --
+ * R4K_FlushDCache --
  *
- *	void MachFlushDCache(addr, len)
+ *	void R4K_FlushDCache(addr, len)
  *		vm_offset_t addr, len;
  *
  *	Flush data cache for index range of addr to addr + len - 1.
@@ -2609,8 +2619,8 @@ END(MachFlushICache)
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachFlushDCache)
-	lw	a2, machPrimaryDataCacheSize
+LEAF(R4K_FlushDCache)
+	lw	a2, CpuPrimaryDataCacheSize
 	addiu	a2, -1
 	and	a0, a0, a2
 	addu	a1, 127		# Align
@@ -2635,13 +2645,13 @@ LEAF(MachFlushDCache)
 
 	j	ra
 	nop
-END(MachFlushDCache)
+END(R4K_FlushDCache)
 
 /*----------------------------------------------------------------------------
  *
- * MachHitFlushDCache --
+ * R4K_HitFlushDCache --
  *
- *	void MachHitFlushDCache(addr, len)
+ *	void R4K_HitFlushDCache(addr, len)
  *		vm_offset_t addr, len;
  *
  *	Flush data cache for range of addr to addr + len - 1.
@@ -2658,7 +2668,7 @@ END(MachFlushDCache)
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachHitFlushDCache)
+LEAF(R4K_HitFlushDCache)
 	beq	a1, zero, 2f
 	addu	a1, 127		# Align
 	addu	a1, a1, a0
@@ -2681,12 +2691,12 @@ LEAF(MachHitFlushDCache)
 2:
 	j	ra
 	nop
-END(MachHitFlushDCache)
+END(R4K_HitFlushDCache)
 /*----------------------------------------------------------------------------
  *
- * MachInvalidateDCache --
+ * R4K_InvalidateDCache --
  *
- *	void MachFlushDCache(addr, len)
+ *	void R4K_FlushDCache(addr, len)
  *		vm_offset_t addr, len;
  *
  *	Flush data cache for range of addr to addr + len - 1.
@@ -2700,7 +2710,7 @@ END(MachHitFlushDCache)
  *
  *----------------------------------------------------------------------------
  */
-LEAF(MachInvalidateDCache)
+LEAF(R4K_InvalidateDCache)
 	addu	a1, a1, a0			# compute ending address
 1:
 	addu	a0, a0, 4
@@ -2709,7 +2719,7 @@ LEAF(MachInvalidateDCache)
 
 	j	ra
 	nop
-END(MachInvalidateDCache)
+END(R4K_InvalidateDCache)
 
 #ifdef DEBUG
 /*
@@ -2770,7 +2780,7 @@ LEAF(mdbpoke)
 	and	a0, a0, ~3		# align address for cache flush
 2:
 	sw	zero, UADDR+U_PCB_ONFAULT
-	b	MachFlushICache		# flush instruction cache
+	b	R4K_FlushICache		# flush instruction cache
 	li	a1, 8
 END(mdbpoke)
 
@@ -2874,7 +2884,7 @@ intrnames:
 	.asciiz	"clock"
 	.asciiz	"statclock"
 eintrnames:
-	.align	2
+	.align	3
 intrcnt:
 	.word	0,0,0,0,0,0,0,0
 eintrcnt:
diff --git a/sys/arch/arc/arc/machdep.c b/sys/arch/arc/arc/machdep.c
index 991f8fdd231..060d1a22aff 100644
--- a/sys/arch/arc/arc/machdep.c
+++ b/sys/arch/arc/arc/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.4 1996/07/30 20:24:17 pefo Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.5 1996/08/26 11:11:54 pefo Exp $	*/
 /*
  * Copyright (c) 1988 University of Utah.
  * Copyright (c) 1992, 1993
@@ -38,7 +38,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)machdep.c	8.3 (Berkeley) 1/12/94
- *      $Id: machdep.c,v 1.4 1996/07/30 20:24:17 pefo Exp $
+ *      $Id: machdep.c,v 1.5 1996/08/26 11:11:54 pefo Exp $
  */
 
 /* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@@ -83,6 +83,7 @@
 #include <machine/psl.h>
 #include <machine/pte.h>
 #include <machine/autoconf.h>
+#include <machine/memconf.h>
 
 #include <sys/exec_ecoff.h>
 
@@ -130,6 +131,8 @@ int	ncpu = 1;		/* At least one cpu in the system */
 int	isa_io_base;		/* Base address of ISA io port space */
 int	isa_mem_base;		/* Base address of ISA memory space */
 
+struct mem_descriptor mem_layout[MAXMEMSEGS];
+
 extern	int Mach_spl0(), Mach_spl1(), Mach_spl2(), Mach_spl3();
 extern	int Mach_spl4(), Mach_spl5(), splhigh();
 int	(*Mach_splnet)() = splhigh;
@@ -276,9 +279,9 @@ mips_init(argc, argv, code)
 	 * Now its time to abandon the BIOS and be self supplying.
 	 * Start with cleaning out the TLB. Bye bye Microsoft....
 	 */
-	MachSetWIRED(0);
-	MachTLBFlush();
-	MachSetWIRED(VMWIRED_ENTRIES);
+	R4K_SetWIRED(0);
+	R4K_TLBFlush();
+	R4K_SetWIRED(VMWIRED_ENTRIES);
 
 	/*
 	 * Set up mapping for hardware the way we want it!
@@ -288,31 +291,31 @@ mips_init(argc, argv, code)
 	tlb.tlb_hi = vad_to_vpn(R4030_V_LOCAL_IO_BASE);
 	tlb.tlb_lo0 = vad_to_pfn(R4030_P_LOCAL_IO_BASE) | PG_IOPAGE;
 	tlb.tlb_lo1 = vad_to_pfn(PICA_P_INT_SOURCE) | PG_IOPAGE;
-	MachTLBWriteIndexed(1, &tlb);
+	R4K_TLBWriteIndexed(1, &tlb);
 
 	tlb.tlb_mask = PG_SIZE_1M;
 	tlb.tlb_hi = vad_to_vpn(PICA_V_LOCAL_VIDEO_CTRL);
 	tlb.tlb_lo0 = vad_to_pfn(PICA_P_LOCAL_VIDEO_CTRL) | PG_IOPAGE;
 	tlb.tlb_lo1 = vad_to_pfn(PICA_P_LOCAL_VIDEO_CTRL + PICA_S_LOCAL_VIDEO_CTRL/2) | PG_IOPAGE;
-	MachTLBWriteIndexed(2, &tlb);
+	R4K_TLBWriteIndexed(2, &tlb);
 	
 	tlb.tlb_mask = PG_SIZE_1M;
 	tlb.tlb_hi = vad_to_vpn(PICA_V_EXTND_VIDEO_CTRL);
 	tlb.tlb_lo0 = vad_to_pfn(PICA_P_EXTND_VIDEO_CTRL) | PG_IOPAGE;
 	tlb.tlb_lo1 = vad_to_pfn(PICA_P_EXTND_VIDEO_CTRL + PICA_S_EXTND_VIDEO_CTRL/2) | PG_IOPAGE;
-	MachTLBWriteIndexed(3, &tlb);
+	R4K_TLBWriteIndexed(3, &tlb);
 	
 	tlb.tlb_mask = PG_SIZE_4M;
 	tlb.tlb_hi = vad_to_vpn(PICA_V_LOCAL_VIDEO);
 	tlb.tlb_lo0 = vad_to_pfn(PICA_P_LOCAL_VIDEO) | PG_IOPAGE;
 	tlb.tlb_lo1 = vad_to_pfn(PICA_P_LOCAL_VIDEO + PICA_S_LOCAL_VIDEO/2) | PG_IOPAGE;
-	MachTLBWriteIndexed(4, &tlb);
+	R4K_TLBWriteIndexed(4, &tlb);
 	
 	tlb.tlb_mask = PG_SIZE_16M;
 	tlb.tlb_hi = vad_to_vpn(PICA_V_ISA_IO);
 	tlb.tlb_lo0 = vad_to_pfn(PICA_P_ISA_IO) | PG_IOPAGE;
 	tlb.tlb_lo1 = vad_to_pfn(PICA_P_ISA_MEM) | PG_IOPAGE;
-	MachTLBWriteIndexed(5, &tlb);
+	R4K_TLBWriteIndexed(5, &tlb);
 	
 	/*
 	 * Init mapping for u page(s) for proc[0], pm_tlbpid 1.
@@ -329,12 +332,12 @@ mips_init(argc, argv, code)
 		tlb.tlb_lo1 = vad_to_pfn(firstaddr + NBPG) | PG_V | PG_M | PG_CACHED;
 		curproc->p_md.md_upte[i] = tlb.tlb_lo0;
 		curproc->p_md.md_upte[i+1] = tlb.tlb_lo1;
-		MachTLBWriteIndexed(i,&tlb);
+		R4K_TLBWriteIndexed(i,&tlb);
 		firstaddr += NBPG * 2;
 	}
 	v += UPAGES * NBPG;
 	v = (caddr_t)((int)v+3 & -4);
-	MachSetPID(1);
+	R4K_SetPID(1);
 
 	/*
 	 * init nullproc for swtch_exit().
@@ -368,8 +371,8 @@ mips_init(argc, argv, code)
 	/*
 	 * Clear out the I and D caches.
 	 */
-	cpucfg = MachConfigCache();
-	MachFlushCache();
+	cpucfg = R4K_ConfigCache();
+	R4K_FlushCache();
 
 	/* check what model platform we are running on */
 	switch (cputype) {
@@ -420,14 +423,31 @@ mips_init(argc, argv, code)
 		if((memcfg & 0x40) == 0)
 			physmem += physmem;	/* 128 bit config */
 
+		mem_layout[0].mem_start = 0x00100000;
+		mem_layout[0].mem_size = physmem - mem_layout[0].mem_start;
+		mem_layout[1].mem_start = 0x00020000;
+		mem_layout[1].mem_size =  0x00100000 - mem_layout[1].mem_start;
+		mem_layout[2].mem_start = 0x0;
+		
 		physmem = btoc(physmem);
 		break;
 
 	case MAGNUM:
 		memcfg = in32(R4030_SYS_CONFIG);
+
+		physmem = btoc(physmem);
 		break;
 
 	case DESKSTATION:
+		/*XXX Need to find out how to size mem */
+		physmem = 1024 * 1024 * 32;
+		mem_layout[0].mem_start = 0x00100000;
+		mem_layout[0].mem_size = physmem - mem_layout[0].mem_start;
+		mem_layout[1].mem_start = 0x00008000;
+		mem_layout[1].mem_size = 0x000a0000 - mem_layout[1].mem_start;
+		mem_layout[2].mem_start = 0x0;
+
+		physmem = btoc(physmem);
 		break;
 
 	default:
diff --git a/sys/arch/arc/arc/minidebug.c b/sys/arch/arc/arc/minidebug.c
index dae2760638b..c1babc64a88 100644
--- a/sys/arch/arc/arc/minidebug.c
+++ b/sys/arch/arc/arc/minidebug.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: minidebug.c,v 1.1 1996/06/24 09:07:21 pefo Exp $	*/
+/*	$OpenBSD: minidebug.c,v 1.2 1996/08/26 11:11:55 pefo Exp $	*/
 /*-
  * Copyright (c) 1991, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -35,7 +35,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)kadb.c	8.1 (Berkeley) 6/10/93
- *      $Id: minidebug.c,v 1.1 1996/06/24 09:07:21 pefo Exp $
+ *      $Id: minidebug.c,v 1.2 1996/08/26 11:11:55 pefo Exp $
  */
 
 /*
@@ -254,8 +254,8 @@ break_insert()
 		if(brk_tab[i].addr != 0) {
 			brk_tab[i].inst = *(u_int *)brk_tab[i].addr;
 			*(u_int *)brk_tab[i].addr = BREAK_BRKPT;
-			MachFlushDCache(brk_tab[i].addr,4);
-			MachFlushICache(brk_tab[i].addr,4);
+			R4K_FlushDCache(brk_tab[i].addr,4);
+			R4K_FlushICache(brk_tab[i].addr,4);
 		}
 	}
 }
@@ -267,8 +267,8 @@ break_restore()
 	for(i = 0; i < MAXBRK; i++) {
 		if(brk_tab[i].addr != 0) {
 			*(u_int *)brk_tab[i].addr = brk_tab[i].inst;
-			MachFlushDCache(brk_tab[i].addr,4);
-			MachFlushICache(brk_tab[i].addr,4);
+			R4K_FlushDCache(brk_tab[i].addr,4);
+			R4K_FlushICache(brk_tab[i].addr,4);
 		}
 	}
 }
@@ -522,12 +522,12 @@ static int ssandrun;	/* Single step and run flag (when cont at brk) */
 			switch(c) {
 			case 't':
 				printf("tlb");
-				MachTLBFlush();
+				R4K_TLBFlush();
 				break;
 
 			case 'c':
 				printf("cache");
-				MachFlushCache();
+				R4K_FlushCache();
 				break;
 			}
 			break;
@@ -567,8 +567,8 @@ mdbsetsstep()
 		/* kernel address */
 		mdb_ss_instr = mdbpeek(va);
 		mdbpoke((caddr_t)va, BREAK_SSTEP);
-		MachFlushDCache(va,4);
-		MachFlushICache(va,4);
+		R4K_FlushDCache(va,4);
+		R4K_FlushICache(va,4);
 		return;
 	}
 }
@@ -597,8 +597,8 @@ mdbclrsstep(cr)
 	if ((int)va < 0) {
 		/* kernel address */
 		mdbpoke((caddr_t)va, mdb_ss_instr);
-		MachFlushDCache(va,4);
-		MachFlushICache(va,4);
+		R4K_FlushDCache(va,4);
+		R4K_FlushICache(va,4);
 		mdb_ss_addr = 0;
 		return(TRUE);
 	}
@@ -1089,7 +1089,7 @@ void arc_dump_tlb(int first,int last)
 	tlbno = first;
 
 	while(tlbno <= last) {
-		MachTLBRead(tlbno, &tlb);
+		R4K_TLBRead(tlbno, &tlb);
 		if(tlb.tlb_lo0 & PG_V || tlb.tlb_lo1 & PG_V) {
 			printf("TLB %2d vad 0x%08x ", tlbno, tlb.tlb_hi);
 		}
diff --git a/sys/arch/arc/arc/pmap.c b/sys/arch/arc/arc/pmap.c
index f350e213396..04a32737908 100644
--- a/sys/arch/arc/arc/pmap.c
+++ b/sys/arch/arc/arc/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.2 1996/07/16 07:46:13 pefo Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.3 1996/08/26 11:11:56 pefo Exp $	*/
 /* 
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -36,7 +36,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)pmap.c	8.4 (Berkeley) 1/26/94
- *      $Id: pmap.c,v 1.2 1996/07/16 07:46:13 pefo Exp $
+ *      $Id: pmap.c,v 1.3 1996/08/26 11:11:56 pefo Exp $
  */
 
 /*
@@ -81,6 +81,7 @@
 
 #include <machine/cpu.h>
 #include <machine/pte.h>
+#include <machine/memconf.h>
 
 extern vm_page_t vm_page_alloc1 __P((void));
 extern void vm_page_free1 __P((vm_page_t));
@@ -107,8 +108,23 @@ typedef struct pv_entry {
 pv_entry_t	pv_table;	/* array of entries, one per page */
 int	pmap_remove_pv();
 
+#ifdef MACHINE_NONCONTIG
+static	vm_offset_t	avail_next;
+static	vm_offset_t	avail_remaining;
+
+struct physseg {
+	vm_offset_t	start;
+	vm_offset_t	end;
+	int		first_page;
+} physsegs[MAXMEMSEGS+1];
+
+#define	pa_index(pa)	pmap_page_index(pa)
+
+#else
 #define pa_index(pa)		atop((pa) - first_phys_addr)
-#define pa_to_pvh(pa)		(&pv_table[pa_index(pa)])
+#endif /* MACHINE_NONCONTIG */
+
+#define pa_to_pvh(pa)	(&pv_table[pa_index(pa)])
 
 #ifdef DEBUG
 struct {
@@ -135,7 +151,6 @@ struct {
 	int pvsearch;
 } remove_stats;
 
-int pmapdebug = 0;
 #define PDB_FOLLOW	0x0001
 #define PDB_INIT	0x0002
 #define PDB_ENTER	0x0004
@@ -151,6 +166,8 @@ int pmapdebug = 0;
 #define PDB_WIRING	0x4000
 #define PDB_PVDUMP	0x8000
 
+int pmapdebug = 0x0;
+
 #endif /* DEBUG */
 
 struct pmap	kernel_pmap_store;
@@ -177,7 +194,7 @@ void
 pmap_bootstrap(firstaddr)
 	vm_offset_t firstaddr;
 {
-	register int i;
+	register int i, n;
 	register pt_entry_t *spte;
 	vm_offset_t start = firstaddr;
 	extern int maxmem, physmem;
@@ -192,6 +209,7 @@ pmap_bootstrap(firstaddr)
 	 */
 	Sysmapsize = (VM_KMEM_SIZE + VM_MBUF_SIZE + VM_PHYS_SIZE +
 		nbuf * MAXBSIZE + 16 * NCARGS) / NBPG + 1024 + 256;
+	Sysmapsize += maxproc * UPAGES * 2;
 #ifdef SYSVSHM
 	Sysmapsize += shminfo.shmall;
 #endif
@@ -207,6 +225,13 @@ pmap_bootstrap(firstaddr)
 	 * rather than kernel virtual addresses mapped through the TLB.
 	 */
 	i = maxmem - mips_btop(CACHED_TO_PHYS(firstaddr));
+#ifdef MACHINE_NONCONTIG
+	for( n = 1; n < MAXMEMSEGS; n++) {
+		if(mem_layout[n].mem_start == 0)
+			break;
+		i += mips_btop(mem_layout[n].mem_size);
+	}
+#endif /*MACHINE_NONCONTIG*/
 	valloc(pv_table, struct pv_entry, i);
 
 	/*
@@ -217,7 +242,27 @@ pmap_bootstrap(firstaddr)
 
 	avail_start = CACHED_TO_PHYS(firstaddr);
 	avail_end = mips_ptob(maxmem);
-	mem_size = avail_end - avail_start;
+
+#ifdef MACHINE_NONCONTIG
+	avail_next = avail_start;
+	avail_remaining = mips_btop(avail_end - avail_start);
+	physsegs[0].start = avail_start;
+	physsegs[0].end = avail_end;
+	physsegs[0].first_page = 0;
+
+	/*
+	 * Now reclaim the "lost" memory areas. Skip the first one
+         * as that is the segment where the os was loaded.
+         */
+	for( i = 1; i < MAXMEMSEGS; i++) {
+		if((physsegs[i].start = mem_layout[i].mem_start) == 0)
+			break;
+		physsegs[i].end = physsegs[i].start + mem_layout[i].mem_size;
+		physsegs[i].first_page = physsegs[i-1].first_page +
+		    (physsegs[i-1].end - physsegs[i-1].start) / NBPG;
+		avail_remaining += (physsegs[i].end - physsegs[i].start) / NBPG;
+	}
+#endif /* MACHINE_NONCONTIG */
 
 	virtual_avail = VM_MIN_KERNEL_ADDRESS;
 	virtual_end = VM_MIN_KERNEL_ADDRESS + Sysmapsize * NBPG;
@@ -272,16 +317,75 @@ pmap_bootstrap_alloc(size)
  *	system needs to map virtual memory.
  */
 void
+#ifdef MACHINE_NONCONTIG
+pmap_init()
+#else
 pmap_init(phys_start, phys_end)
 	vm_offset_t phys_start, phys_end;
+#endif
 {
 
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_INIT))
-		printf("pmap_init(%x, %x)\n", phys_start, phys_end);
+#ifdef MACHINE_NONCONTIG
+		printf("pmap_init(%lx, %lx)\n", avail_start, avail_end);
+#else
+		printf("pmap_init(%lx, %lx)\n", phys_start, phys_end);
 #endif
+#endif /*DEBUG*/
 }
 
+#ifdef MACHINE_NONCONTIG
+inline int
+pmap_page_index(pa)
+    vm_offset_t pa;
+{
+	struct physseg *ps = &physsegs[0];
+	while (ps->start) {
+		if(pa >= ps->start && pa < ps->end) {
+			return(atop(pa - ps->start) + ps->first_page);
+		}
+		ps++;
+	}
+	return -1;
+}
+
+unsigned int
+pmap_free_pages()
+{
+	 return avail_remaining;
+}
+
+void
+pmap_virtual_space(startp, endp)
+	vm_offset_t  *startp;
+	vm_offset_t  *endp;
+{
+	*startp = virtual_avail;
+	*endp = virtual_end;
+}
+
+int
+pmap_next_page(p_addr)
+	vm_offset_t *p_addr;
+{
+	static int cur_seg = 0;
+
+	if (physsegs[cur_seg].start == 0)
+		return FALSE;
+	if (avail_next == physsegs[cur_seg].end) {
+		avail_next = physsegs[++cur_seg].start;
+	}
+
+	if (avail_next == 0)
+		return FALSE;
+	*p_addr = avail_next;
+	avail_next += NBPG;
+	avail_remaining--;
+	return TRUE;
+}
+#endif /*MACHINE_NONCONTIG*/
+
 /*
  *	Create and return a physical map.
  *
@@ -351,7 +455,13 @@ pmap_pinit(pmap)
 		vm_page_t mem;
 		void pmap_zero_page();
 
-		mem = vm_page_alloc1();
+		do {
+			mem = vm_page_alloc1();
+			if (mem == NULL) {
+				VM_WAIT;	/* XXX What else can we do */
+			}			/* XXX Deadlock situations? */
+		} while (mem == NULL);
+
 		pmap_zero_page(VM_PAGE_TO_PHYS(mem));
 		pmap->pm_segtab = stp = (struct segtab *)
 			PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
@@ -444,7 +554,7 @@ pmap_release(pmap)
 					panic("pmap_release: segmap not empty");
 			}
 #endif
-			MachHitFlushDCache(pte, PAGE_SIZE);
+			R4K_HitFlushDCache(pte, PAGE_SIZE);
 			vm_page_free1(
 				PHYS_TO_VM_PAGE(CACHED_TO_PHYS(pte)));
 			pmap->pm_segtab->seg_tab[i] = NULL;
@@ -517,7 +627,7 @@ pmap_remove(pmap, sva, eva)
 				pmap->pm_stats.wired_count--;
 			pmap->pm_stats.resident_count--;
 			if(pmap_remove_pv(pmap, sva, pfn_to_vad(entry))) {
-				MachFlushDCache(sva, PAGE_SIZE);
+				R4K_FlushDCache(sva, PAGE_SIZE);
 			}
 #ifdef ATTR
 			pmap_attributes[atop(pfn_to_vad(entry))] = 0;
@@ -526,7 +636,7 @@ pmap_remove(pmap, sva, eva)
 			 * Flush the TLB for the given address.
 			 */
 			pte->pt_entry = PG_NV | PG_G; /* See above about G bit */
-			MachTLBFlushAddr(sva);
+			R4K_TLBFlushAddr(sva);
 #ifdef DEBUG
 			remove_stats.flushes++;
 
@@ -563,7 +673,7 @@ pmap_remove(pmap, sva, eva)
 				pmap->pm_stats.wired_count--;
 			pmap->pm_stats.resident_count--;
 			if(pmap_remove_pv(pmap, sva, pfn_to_vad(entry))) {
-				MachFlushDCache(sva, PAGE_SIZE);
+				R4K_FlushDCache(sva, PAGE_SIZE);
 			}
 #ifdef ATTR
 			pmap_attributes[atop(pfn_to_vad(entry))] = 0;
@@ -573,7 +683,7 @@ pmap_remove(pmap, sva, eva)
 			 * Flush the TLB for the given address.
 			 */
 			if (pmap->pm_tlbgen == tlbpid_gen) {
-				MachTLBFlushAddr(sva | (pmap->pm_tlbpid <<
+				R4K_TLBFlushAddr(sva | (pmap->pm_tlbpid <<
 					VMTLB_PID_SHIFT));
 #ifdef DEBUG
 				remove_stats.flushes++;
@@ -700,7 +810,7 @@ pmap_protect(pmap, sva, eva, prot)
 			/*
 			 * Update the TLB if the given address is in the cache.
 			 */
-			MachTLBUpdate(sva, entry);
+			R4K_TLBUpdate(sva, entry);
 		}
 		return;
 	}
@@ -735,7 +845,7 @@ pmap_protect(pmap, sva, eva, prot)
 			 * Update the TLB if the given address is in the cache.
 			 */
 			if (pmap->pm_tlbgen == tlbpid_gen)
-				MachTLBUpdate(sva | (pmap->pm_tlbpid <<
+				R4K_TLBUpdate(sva | (pmap->pm_tlbpid <<
 					VMTLB_PID_SHIFT), entry);
 		}
 	}
@@ -790,7 +900,7 @@ pmap_page_cache(pa,mode)
 			if (entry & PG_V) {
 				entry = (entry & ~PG_CACHEMODE) | newmode;
 				pte->pt_entry = entry;
-				MachTLBUpdate(pv->pv_va, entry);
+				R4K_TLBUpdate(pv->pv_va, entry);
 			}
 		}
 		else {
@@ -801,7 +911,7 @@ pmap_page_cache(pa,mode)
 					entry = (entry & ~PG_CACHEMODE) | newmode;
 					pte->pt_entry = entry;
 					if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
-						MachTLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
+						R4K_TLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
 							VMTLB_PID_SHIFT), entry);
 				}
 			}
@@ -876,7 +986,9 @@ pmap_enter(pmap, va, pa, prot, wired)
 				 * just record page as dirty.
 				 */
 				npte = PG_RWPAGE;
+#if 0 /*XXX*/
 				mem->flags &= ~PG_CLEAN;
+#endif
 			} else
 #ifdef ATTR
 				if ((pmap_attributes[atop(pa)] &
@@ -930,10 +1042,10 @@ pmap_enter(pmap, va, pa, prot, wired)
 					/*
 					 * Check cache aliasing incompatibility
 					 */
-					if((npv->pv_va & machCacheAliasMask) != (va & machCacheAliasMask)) {
+					if((npv->pv_va & CpuCacheAliasMask) != (va & CpuCacheAliasMask)) {
 						printf("pmap_enter: creating uncached mapping 0x%x, 0x%x.\n",npv->pv_va, va);
 						pmap_page_cache(pa,PV_UNCACHED);
-						MachFlushDCache(pv->pv_va, PAGE_SIZE);
+						R4K_FlushDCache(pv->pv_va, PAGE_SIZE);
 						npte = (npte & ~PG_CACHEMODE) | PG_UNCACHED;
 						break;
 					}
@@ -1015,7 +1127,7 @@ pmap_enter(pmap, va, pa, prot, wired)
 	 * NOTE: we only support cache flush for read only text.
 	 */
 	if (prot == (VM_PROT_READ | VM_PROT_EXECUTE))
-		MachFlushICache(PHYS_TO_CACHED(pa), PAGE_SIZE);
+		R4K_FlushICache(PHYS_TO_CACHED(pa), PAGE_SIZE);
 
 	if (!pmap->pm_segtab) {
 		/* enter entries into kernel pmap */
@@ -1036,13 +1148,19 @@ pmap_enter(pmap, va, pa, prot, wired)
 		/*
 		 * Update the same virtual address entry.
 		 */
-		j = MachTLBUpdate(va, npte);
+		j = R4K_TLBUpdate(va, npte);
 		pte->pt_entry = npte;
 		return;
 	}
 
 	if (!(pte = pmap_segmap(pmap, va))) {
-		mem = vm_page_alloc1();
+		do {
+			mem = vm_page_alloc1();
+			if (mem == NULL) {
+				VM_WAIT;	/* XXX What else can we do */
+			}			/* XXX Deadlock situations? */
+		} while (mem == NULL);
+
 		pmap_zero_page(VM_PAGE_TO_PHYS(mem));
 		pmap_segmap(pmap, va) = pte = (pt_entry_t *)
 			PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
@@ -1078,7 +1196,7 @@ pmap_enter(pmap, va, pa, prot, wired)
 	}
 	pte->pt_entry = npte;
 	if (pmap->pm_tlbgen == tlbpid_gen)
-		j = MachTLBUpdate(va | (pmap->pm_tlbpid <<
+		j = R4K_TLBUpdate(va | (pmap->pm_tlbpid <<
 			VMTLB_PID_SHIFT), npte);
 }
 
@@ -1255,7 +1373,7 @@ pmap_zero_page(phys)
 		printf("pmap_zero_page(%x)\n", phys);
 #endif
 /*XXX FIXME Not very sophisticated */
-	MachFlushCache();
+	R4K_FlushCache();
 	p = (int *)PHYS_TO_CACHED(phys);
 	end = p + PAGE_SIZE / sizeof(int);
 	do {
@@ -1266,7 +1384,7 @@ pmap_zero_page(phys)
 		p += 4;
 	} while (p != end);
 /*XXX FIXME Not very sophisticated */
-	MachFlushCache();
+	R4K_FlushCache();
 }
 
 /*
@@ -1285,7 +1403,7 @@ pmap_copy_page(src, dst)
 		printf("pmap_copy_page(%x, %x)\n", src, dst);
 #endif
 /*XXX FIXME Not very sophisticated */
-	MachFlushCache();
+	R4K_FlushCache();
 	s = (int *)PHYS_TO_CACHED(src);
 	d = (int *)PHYS_TO_CACHED(dst);
 	end = s + PAGE_SIZE / sizeof(int);
@@ -1302,7 +1420,7 @@ pmap_copy_page(src, dst)
 		d += 4;
 	} while (s != end);
 /*XXX FIXME Not very sophisticated */
-	MachFlushCache();
+	R4K_FlushCache();
 }
 
 /*
@@ -1439,7 +1557,7 @@ pmap_alloc_tlbpid(p)
 	if (pmap->pm_tlbgen != tlbpid_gen) {
 		id = tlbpid_cnt;
 		if (id == VMNUM_PIDS) {
-			MachTLBFlush();
+			R4K_TLBFlush();
 			/* reserve tlbpid_gen == 0 to alway mean invalid */
 			if (++tlbpid_gen == 0)
 				tlbpid_gen = 1;
diff --git a/sys/arch/arc/arc/trap.c b/sys/arch/arc/arc/trap.c
index 41c4c009f82..a3b65a018c0 100644
--- a/sys/arch/arc/arc/trap.c
+++ b/sys/arch/arc/arc/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.3 1996/07/30 20:24:18 pefo Exp $	*/
+/*	$OpenBSD: trap.c,v 1.4 1996/08/26 11:11:56 pefo Exp $	*/
 /*
  * Copyright (c) 1988 University of Utah.
  * Copyright (c) 1992, 1993
@@ -39,7 +39,7 @@
  * from: Utah Hdr: trap.c 1.32 91/04/06
  *
  *	from: @(#)trap.c	8.5 (Berkeley) 1/11/94
- *      $Id: trap.c,v 1.3 1996/07/30 20:24:18 pefo Exp $
+ *      $Id: trap.c,v 1.4 1996/08/26 11:11:56 pefo Exp $
  */
 
 #include <sys/param.h>
@@ -299,7 +299,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 			entry |= PG_M;
 			pte->pt_entry = entry;
 			vadr &= ~PGOFSET;
-			MachTLBUpdate(vadr, entry);
+			R4K_TLBUpdate(vadr, entry);
 			pa = pfn_to_vad(entry);
 #ifdef ATTR
 			pmap_attributes[atop(pa)] |= PMAP_ATTR_MOD;
@@ -337,7 +337,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		pte->pt_entry = entry;
 		vadr = (vadr & ~PGOFSET) |
 			(pmap->pm_tlbpid << VMTLB_PID_SHIFT);
-		MachTLBUpdate(vadr, entry);
+		R4K_TLBUpdate(vadr, entry);
 		pa = pfn_to_vad(entry);
 #ifdef ATTR
 		pmap_attributes[atop(pa)] |= PMAP_ATTR_MOD;
@@ -621,7 +621,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 			locr0[A3] = 1;
 		}
 		if(code == SYS_ptrace)
-			MachFlushCache();
+			R4K_FlushCache();
 	done:
 #ifdef SYSCALL_DEBUG
 		scdebug_ret(p, code, i, rval);
@@ -669,7 +669,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		uio.uio_rw = UIO_WRITE;
 		uio.uio_procp = curproc;
 		i = procfs_domem(p, p, NULL, &uio);
-		MachFlushCache();
+		R4K_FlushCache();
 
 		if (i < 0)
 			printf("Warning: can't restore instruction at %x: %x\n",
@@ -1257,7 +1257,7 @@ cpu_singlestep(p)
 	uio.uio_rw = UIO_WRITE;
 	uio.uio_procp = curproc;
 	i = procfs_domem(curproc, p, NULL, &uio);
-	MachFlushCache();
+	R4K_FlushCache();
 
 	if (i < 0)
 		return (EFAULT);
diff --git a/sys/arch/arc/arc/vm_machdep.c b/sys/arch/arc/arc/vm_machdep.c
index a2875520867..d27e6b7df69 100644
--- a/sys/arch/arc/arc/vm_machdep.c
+++ b/sys/arch/arc/arc/vm_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: vm_machdep.c,v 1.1 1996/06/24 09:07:21 pefo Exp $	*/
+/*	$OpenBSD: vm_machdep.c,v 1.2 1996/08/26 11:11:57 pefo Exp $	*/
 /*
  * Copyright (c) 1988 University of Utah.
  * Copyright (c) 1992, 1993
@@ -39,7 +39,7 @@
  * from: Utah Hdr: vm_machdep.c 1.21 91/04/06
  *
  *	from: @(#)vm_machdep.c	8.3 (Berkeley) 1/4/94
- *      $Id: vm_machdep.c,v 1.1 1996/06/24 09:07:21 pefo Exp $
+ *      $Id: vm_machdep.c,v 1.2 1996/08/26 11:11:57 pefo Exp $
  */
 
 
@@ -217,12 +217,12 @@ pagemove(from, to, size)
 		panic("pagemove");
 	fpte = kvtopte(from);
 	tpte = kvtopte(to);
-	if(((int)from & machCacheAliasMask) != ((int)to & machCacheAliasMask)) {
-		MachHitFlushDCache(from, size);
+	if(((int)from & CpuCacheAliasMask) != ((int)to & CpuCacheAliasMask)) {
+		R4K_HitFlushDCache(from, size);
 	}
 	while (size > 0) {
-		MachTLBFlushAddr(from);
-		MachTLBUpdate(to, *fpte);
+		R4K_TLBFlushAddr(from);
+		R4K_TLBUpdate(to, *fpte);
 		*tpte++ = *fpte;
 		fpte->pt_entry = PG_NV | PG_G;
 		fpte++;
@@ -269,7 +269,7 @@ vmapbuf(bp, len)
 	off = (int)addr & PGOFSET;
 	p = bp->b_proc;
 	sz = round_page(off + len);
-	kva = kmem_alloc_wait_align(phys_map, sz, (vm_size_t)addr & machCacheAliasMask);
+	kva = kmem_alloc_wait_align(phys_map, sz, (vm_size_t)addr & CpuCacheAliasMask);
 	bp->b_un.b_addr = (caddr_t) (kva + off);
 	sz = atop(sz);
 	while (sz--) {
@@ -427,11 +427,11 @@ vm_map_findspace_align(map, start, length, addr, align)
 		 * win.
 		 */
 		start = ((start + NBPG -1) & ~(NBPG - 1)); /* Paranoia */
-		if((start & machCacheAliasMask) <= align) {
-			start += align - (start & machCacheAliasMask);
+		if((start & CpuCacheAliasMask) <= align) {
+			start += align - (start & CpuCacheAliasMask);
 		}
 		else {
-			start = ((start + machCacheAliasMask) & ~machCacheAliasMask);
+			start = ((start + CpuCacheAliasMask) & ~CpuCacheAliasMask);
 			start += align;
 		}
 			
diff --git a/sys/arch/arc/conf/PICA b/sys/arch/arc/conf/PICA
index 03718922ed1..8d3a628f7c8 100644
--- a/sys/arch/arc/conf/PICA
+++ b/sys/arch/arc/conf/PICA
@@ -1,4 +1,4 @@
-#
+
 #	Generic configuration file for MIPS R4400 PICA system
 #
 
@@ -58,8 +58,15 @@ options		GATEWAY		# IP packet forwarding
 #options	TPIP
 #options	EON
 
+# Special options
+#options		MACHINE_NONCONTIG # Support noncontigous memory.
+
+# Specify storage configuration
 config		bsd	root on sd0 swap on sd0 and sd1
 
+#
+# Definition of system
+#
 mainbus0	at root
 cpu*		at mainbus0
 
diff --git a/sys/arch/arc/dev/asc.c b/sys/arch/arc/dev/asc.c
index 0a8af5464b9..24780814358 100644
--- a/sys/arch/arc/dev/asc.c
+++ b/sys/arch/arc/dev/asc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asc.c,v 1.1 1996/06/24 09:07:19 pefo Exp $	*/
+/*	$OpenBSD: asc.c,v 1.2 1996/08/26 11:11:59 pefo Exp $	*/
 /*	$NetBSD: asc.c,v 1.10 1994/12/05 19:11:12 dean Exp $	*/
 
 /*-
@@ -642,7 +642,7 @@ asc_scsi_cmd(xs)
 	 *  Flush caches for any data buffer
 	 */
 	if(xs->datalen != 0) {
-		MachHitFlushDCache(xs->data, xs->datalen);
+		R4K_HitFlushDCache(xs->data, xs->datalen);
 	}
 	/*
 	 *  The hack on the next few lines are to avoid buffers
@@ -1397,7 +1397,7 @@ asc_end(asc, status, ss, ir)
 			state->buf = (vm_offset_t)&scsicmd->sense;
 			state->buflen = sizeof(struct scsi_sense_data);
 			state->flags |= CHECK_SENSE;
-			MachHitFlushDCache(state->buf, state->buflen);
+			R4K_HitFlushDCache(state->buf, state->buflen);
 			asc->cmd[target] = scsicmd;
 			asc_startcmd(asc, target);
 			return(0);
diff --git a/sys/arch/arc/dev/dma.c b/sys/arch/arc/dev/dma.c
index 433655983de..085ec063793 100644
--- a/sys/arch/arc/dev/dma.c
+++ b/sys/arch/arc/dev/dma.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dma.c,v 1.2 1996/07/30 20:24:20 pefo Exp $	*/
+/*	$OpenBSD: dma.c,v 1.3 1996/08/26 11:11:59 pefo Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -32,7 +32,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)rz.c	8.1 (Berkeley) 7/29/93
- *      $Id: dma.c,v 1.2 1996/07/30 20:24:20 pefo Exp $
+ *      $Id: dma.c,v 1.3 1996/08/26 11:11:59 pefo Exp $
  */
 
 /*
@@ -79,7 +79,7 @@ picaDmaInit()
 {
 	int map = PICA_TL_BASE;
 
-	MachFlushCache();	/* Make shure no map entries are cached */
+	R4K_FlushCache();	/* Make shure no map entries are cached */
 
 	bzero((char *)map, PICA_TL_SIZE);
 	free_dma_pte = (dma_pte_t *)map;
diff --git a/sys/arch/arc/dev/fd.c b/sys/arch/arc/dev/fd.c
index aee3df4d52d..fc5d4443775 100644
--- a/sys/arch/arc/dev/fd.c
+++ b/sys/arch/arc/dev/fd.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fd.c,v 1.1 1996/06/24 09:07:19 pefo Exp $	*/
+/*	$OpenBSD: fd.c,v 1.2 1996/08/26 11:12:00 pefo Exp $	*/
 /*	$NetBSD: fd.c,v 1.78 1995/07/04 07:23:09 mycroft Exp $	*/
 
 /*-
@@ -877,7 +877,7 @@ loop:
 #endif
 		 }}
 #endif
-		MachFlushDCache(bp->b_data + fd->sc_skip, fd->sc_nbytes);
+		R4K_FlushDCache(bp->b_data + fd->sc_skip, fd->sc_nbytes);
 		read = bp->b_flags & B_READ ? DMA_FROM_DEV : DMA_TO_DEV;
 		DMA_START(fdc->dma, bp->b_data + fd->sc_skip, fd->sc_nbytes, read);
 		outb(iobase + fdctl, type->rate);
diff --git a/sys/arch/arc/dev/if_sn.c b/sys/arch/arc/dev/if_sn.c
index c5148833611..fc9044253fc 100644
--- a/sys/arch/arc/dev/if_sn.c
+++ b/sys/arch/arc/dev/if_sn.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_sn.c,v 1.2 1996/07/30 20:24:22 pefo Exp $	*/
+/*	$OpenBSD: if_sn.c,v 1.3 1996/08/26 11:12:01 pefo Exp $	*/
 /*
  * National Semiconductor  SONIC Driver
  * Copyright (c) 1991   Algorithmics Ltd (http://www.algor.co.uk)
@@ -326,6 +326,7 @@ snattach(parent, self, aux)
 	p += NRBA * RBASIZE;
 
 	DMA_MAP(sc->dma, (caddr_t)SONICBUF, p - SONICBUF, SONICBUF - pp);
+	printf(" buf:%d",p - SONICBUF);
 
 #if 0
 	camdump(sc);
@@ -663,7 +664,7 @@ sonicput(sc, m0)
 		int resid = m->m_len;
 
 		if(resid != 0) {
-			MachHitFlushDCache(va, resid);
+			R4K_HitFlushDCache(va, resid);
 			DMA_MAP(sc->dma, (caddr_t)va, resid, fragoffset);
 		}
 		len += resid;
diff --git a/sys/arch/arc/include/cpu.h b/sys/arch/arc/include/cpu.h
index f43cf199abf..3330f03c8b9 100644
--- a/sys/arch/arc/include/cpu.h
+++ b/sys/arch/arc/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.2 1996/07/16 07:46:17 pefo Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.3 1996/08/26 11:12:02 pefo Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -62,7 +62,9 @@
 #define	PHYS_TO_UNCACHED(x) 	((unsigned)(x) | UNCACHED_MEMORY_ADDR)
 #define VA_TO_CINDEX(x) 	((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR)
 
+#if 0
 #define CODE_START		0x80080000
+#endif
 
 #ifdef _KERNEL
 /*
@@ -401,11 +403,12 @@ union cpuprid {
 #if defined(_KERNEL) && !defined(_LOCORE)
 union	cpuprid cpu_id;
 union	cpuprid fpu_id;
-u_int	machPrimaryDataCacheSize;
-u_int	machPrimaryInstCacheSize;
-u_int	machPrimaryDataCacheLSize;
-u_int	machPrimaryInstCacheLSize;
-u_int	machCacheAliasMask;
+u_int	CpuPrimaryDataCacheSize;
+u_int	CpuPrimaryInstCacheSize;
+u_int	CpuPrimaryDataCacheLSize;
+u_int	CpuPrimaryInstCacheLSize;
+u_int	CpuCacheAliasMask;
+u_int	CpuTwoWayCache;
 extern	struct intr_tab intr_tab[];
 #endif
 
diff --git a/sys/arch/arc/include/memconf.h b/sys/arch/arc/include/memconf.h
new file mode 100644
index 00000000000..c4e4e760b52
--- /dev/null
+++ b/sys/arch/arc/include/memconf.h
@@ -0,0 +1,50 @@
+/*	$OpenBSD: memconf.h,v 1.1 1996/08/26 11:12:02 pefo Exp $	*/
+
+/*
+ * Copyright (c) 1996 Per Fogelstrom
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Memory config list used by pmap_bootstrap.
+ */
+
+#ifndef _MEMCONF_H_
+#define _MEMCONF_H_
+
+struct mem_descriptor {
+	vm_offset_t	mem_start;
+	u_int		mem_size;
+};
+
+#ifdef _KERNEL
+#define	MAXMEMSEGS	8
+extern struct mem_descriptor mem_layout[];
+#endif
+
+#endif
diff --git a/sys/arch/arc/include/param.h b/sys/arch/arc/include/param.h
index d9883c9bf0b..1e3dc7102c2 100644
--- a/sys/arch/arc/include/param.h
+++ b/sys/arch/arc/include/param.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: param.h,v 1.3 1996/08/24 18:10:37 imp Exp $ */
+/*      $OpenBSD: param.h,v 1.4 1996/08/26 11:12:03 pefo Exp $ */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -50,8 +50,7 @@
  */
 #define	MACHINE	     "arc"
 #define MACHINE_ARCH "mips"
-#define MID_PICA MID_PMAX /* For the moment */
-#define MID_MACHINE  MID_PICA
+#define MID_MACHINE  MID_PMAX	/* XXX Bogus, but we need it for now... */
 
 /*
  * Round p (pointer or byte index) up to a correctly-aligned value for all
@@ -71,7 +70,9 @@
 #define	SEGSHIFT	22		/* LOG2(NBSEG) */
 
 #define	KERNBASE	0x80000000	/* start of kernel virtual */
+#if 0
 #define	KERNTEXTOFF	0x80080000	/* start of kernel text for kvm_mkdb */
+#endif
 #define	BTOPKERNBASE	((u_long)KERNBASE >> PGSHIFT)
 
 #define	DEV_BSIZE	512
@@ -115,7 +116,7 @@
  * Size of kernel malloc arena in CLBYTES-sized logical pages
  */ 
 #ifndef NKMEMCLUSTERS
-#define	NKMEMCLUSTERS	(512*1024/CLBYTES)
+#define	NKMEMCLUSTERS	(4096*1024/CLBYTES)
 #endif
 
 /* pages ("clicks") (4096 bytes) to disk blocks */