DDB.

Support for Algorithmics R5000/R10000 evaluation board. So far only the
RM5260 is supported. RM5270 - RM7000 later. R5000 and R10000 depending
on access to cpu modules.

vm_machdep.c moved to arch/mips/mips.

20 files changed, 725 insertions, 1081 deletions

diff --git a/sys/arch/arc/algor/algor.h b/sys/arch/arc/algor/algor.h
index c5fc4604120..31e6f896824 100644
--- a/sys/arch/arc/algor/algor.h
+++ b/sys/arch/arc/algor/algor.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: algor.h,v 1.3 1997/04/19 17:19:36 pefo Exp $ */
+/*	$OpenBSD: algor.h,v 1.4 1998/03/16 09:38:23 pefo Exp $ */
 
 /*
  * Copyright (c) 1996 Per Fogelstrom
@@ -36,12 +36,15 @@
 #define	_ALGOR_H_ 1
 
 /*
- * P-4032's Physical address space
+ * Physical address space
  */
 
 #define P4032_PHYS_MIN		0x00000000	/* 256 Meg */
 #define P4032_PHYS_MAX		0x0fffffff
 
+#define P5064_PHYS_MIN		0x00000000	/* 256 Meg */
+#define P5064_PHYS_MAX		0x0fffffff
+
 /*
  * Memory map
  */
@@ -49,8 +52,11 @@
 #define P4032_PHYS_MEMORY_START	0x00000000
 #define P4032_PHYS_MEMORY_END	0x0fffffff	/* 256 Meg in 2 slots */
 
+#define P5064_PHYS_MEMORY_START	0x00000000
+#define P5064_PHYS_MEMORY_END	0x0fffffff	/* 256 Meg in 2 slots */
+
 /*
- * I/O map
+ * I/O map P-4032
  */
 
 #define	P4032_V96x		0xbef00000	/* PCI Bus bridge ctrlregs */
@@ -76,6 +82,36 @@
 #define	P4032_IXR2		0xbff90014	/* Int crossbar register 0 */
 
 /*
+ * I/O map P-5064
+ */
+
+#define	P5064_V96x		P4032_V96x	/* PCI Bus bridge ctrlregs */
+
+#define	P5064_CLOCK		0xbd000070	/* RTC clock ptr reg, data +1 */
+#define	P5064_KEYB		0xbd000064	/* PC Keyboard controller */
+#define	P5064_LED		P4032_LED	/* 4 Char LED display */
+#define	P5064_LCD		P4032_LCD	/* LCD option display */
+#define	P5064_GPIO		P4032_GPIO	/* General purpose I/O */
+#define	P5064_GPIO_IACK		P4032_GPIO_IACK	/* General purpose I/O Iack */
+#define	P5064_FPY		0xbd0003f0	/* Floppy controller */
+#define	P5064_COM1		0xbd0003f8	/* Serial port com1 */
+#define	P5064_COM2		0xbd0002f8	/* Serial port com2 */
+#define	P5064_CENTR		0xbd000378	/* Centronics paralell port */
+#define	P5064_IMR		0xbff90000	/* Int mask reg (wr) */
+#define	P5064_IRR		0xbff90000	/* Int request reg (rd) */
+#define	P5064_EIRR		0xbff90004	/* Error int request reg (rd) */
+#define	P5064_ICR		0xbff90004	/* Int clear register (wr) */
+#define	P5064_PCIIMR		0xbff90008	/* PCI Int mask reg (wr) */
+#define	P5064_PCIIRR		0xbff90008	/* PCI Int req reg (rd) */
+#define	P5064_IDEIMR		0xbff9000c	/* IDE Int req reg (rd) */
+#define	P5064_IDEIRR		0xbff9000c	/* IDE Int req reg (rd) */
+#define	P5064_IXR0		0xbff90010	/* Int crossbar register 0 */
+#define	P5064_IXR1		0xbff90014	/* Int crossbar register 1 */
+#define	P5064_IXR2		0xbff90018	/* Int crossbar register 2 */
+#define	P5064_IXR3		0xbff9001c	/* Int crossbar register 3 */
+#define	P5064_IXR4		0xbff90020	/* Int crossbar register 4 */
+
+/*
  * Interrupt controller interrupt masks
  */
 
diff --git a/sys/arch/arc/algor/algorbus.c b/sys/arch/arc/algor/algorbus.c
index bd80dab664f..b3dda7ae362 100644
--- a/sys/arch/arc/algor/algorbus.c
+++ b/sys/arch/arc/algor/algorbus.c
@@ -1,7 +1,7 @@
-/*	$OpenBSD: algorbus.c,v 1.4 1998/01/29 14:54:45 pefo Exp $ */
+/*	$OpenBSD: algorbus.c,v 1.5 1998/03/16 09:38:25 pefo Exp $ */
 
 /*
- * Copyright (c) 1996 Per Fogelstrom
+ * Copyright (c) 1996, 1997, 1998 Per Fogelstrom, Opsycon AB
  * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -14,7 +14,7 @@
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed under OpenBSD by
- *	Per Fogelstrom.
+ *	Per Fogelstrom, Opsycon AB.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
@@ -44,7 +44,7 @@
 #include <machine/intr.h>
 #include <machine/autoconf.h>
 
-#include <arc/arc/arctype.h>
+#include <mips/archtype.h>
 #include <arc/algor/algor.h>
 
 #include <dev/ic/mc146818reg.h>
@@ -76,7 +76,8 @@ int	algor_clkintr __P((unsigned, struct clockframe *));
 int	algor_errintr __P((unsigned, struct clockframe *));
 
 int p4032_imask = 0;
-int p4032_ixr = 0;
+int p4032_ixr0 = 0;	/* Routing for local and panic ints. */
+int p4032_ixr1 = 0;	/* Routing for pci and ide ints. */
 
 /*
  *  Interrupt dispatch table.
@@ -98,14 +99,18 @@ static struct algor_int_desc int_table[] = {
 	{0, algor_intrnull, (void *)NULL, 0 },  /* 13 */
 	{0, algor_intrnull, (void *)NULL, 0 },  /* 14 */
 	{0, algor_intrnull, (void *)NULL, 0 },  /* 15 */
+	{0, algor_intrnull, (void *)NULL, 0 },  /* 16 */
+	{0, algor_intrnull, (void *)NULL, 0 },  /* 17 */
+	{0, algor_intrnull, (void *)NULL, 0 },  /* 18 */
+	{0, algor_intrnull, (void *)NULL, 0 },  /* 19 */
 };
 #define NUM_INT_SLOTS (sizeof(int_table) / sizeof(struct algor_int_desc))
 
 struct algor_dev {
 	struct confargs	ps_ca;
-	u_int8_t	ps_mask;
-	u_int8_t	ps_ipl;
-	u_int16_t	ps_route;
+	u_int8_t	ps_mask;	/* Interrupt mask register value */
+	u_int8_t	ps_ipl;		/* IPL to route int to */
+	u_int16_t	ps_route;	/* int routing mask bits */
 	intr_handler_t	ps_handler;
 	void 		*ps_base;
 };
@@ -121,27 +126,34 @@ struct algor_dev algor_4032_cpu[] = {
     {{ NULL,     	 -1, NULL, },
        0, 		0x0000,	NULL,		(void *)NULL, },
 };
-#define NUM_ALGOR_DEVS (sizeof(algor_4032_cpu) / sizeof(struct algor_dev))
+
+struct algor_dev algor_5064_cpu[] = {
+    {{ "dallas_rtc",	 0, 0, },
+       P4032_IM_RTC,  IPL_CLOCK, 0xc000, algor_intrnull, (void *)P5064_CLOCK, },
+    {{ "com",		 1, 0, },
+       P4032_IM_COM1, IPL_TTY,   0x00c0, algor_intrnull, (void *)P5064_COM1,  },
+    {{ "com",      	 2, 0, },
+       P4032_IM_COM2, IPL_TTY,   0x0300, algor_intrnull, (void *)P5064_COM2,  },
+    {{ "lpt",      	 3, 0, },
+       P4032_IM_CENTR,IPL_TTY,   0x0c00, algor_intrnull, (void *)P5064_CENTR, },
+    {{ NULL,     	 -1, NULL, },
+       0, 		0x0000,	NULL,		(void *)NULL, },
+};
 
 /* IPL routing values */
 static int ipxrtab[] = {
-	0x000000,	/* IPL_BIO */
-	0x555555,	/* IPL_NET */
-	0xaaaaaa,	/* IPL_TTY */
-	0xffffff,	/* IPL_CLOCK */
+	0x00000000,	/* IPL_BIO */
+	0x55555555,	/* IPL_NET */
+	0xaaaaaaaa,	/* IPL_TTY */
+	0xffffffff,	/* IPL_CLOCK */
 };
 	
 
 
 struct algor_dev *algor_cpu_devs[] = {
 	NULL,			/* Unused */
-	NULL,			/* Unused */
-	NULL,			/* Unused */
-	NULL,			/* Unused */
-	NULL,			/* Unused */
-	NULL,			/* Unused */
-	algor_4032_cpu,		/* 6 = ALGORITHMICS R4032 Board */
-	NULL,
+	algor_4032_cpu,		/* 0x21 = ALGORITHMICS P-4032 board */
+	algor_5064_cpu,		/* 0x22 = ALGORITHMICS P-5064 board */
 };
 int nalgor_cpu_devs = sizeof algor_cpu_devs / sizeof algor_cpu_devs[0];
 
@@ -159,8 +171,8 @@ algormatch(parent, cfdata, aux)
                 return (0);
 
         /* Make sure that unit exists. */
-	if (cf->cf_unit != 0 || system_type > nalgor_cpu_devs
-	    || algor_cpu_devs[system_type] == NULL)
+	if (cf->cf_unit != 0 || (system_type - ALGOR_CLASS) > nalgor_cpu_devs
+	    || algor_cpu_devs[system_type - ALGOR_CLASS] == NULL)
 		return (0);
 
 	return (1);
@@ -179,10 +191,10 @@ algorattach(parent, self, aux)
 	printf("\n");
 
 	/* keep our CPU device description handy */
-	sc->sc_devs = algor_cpu_devs[system_type];
+	sc->sc_devs = algor_cpu_devs[system_type - ALGOR_CLASS];
 
 	/* set up interrupt handlers */
-	set_intr(INT_MASK_1, algor_iointr, 2);
+	set_intr(INT_MASK_1, algor_iointr, 3);
 	set_intr(INT_MASK_4, algor_errintr, 0);
 
 	sc->sc_bus.ab_dv = (struct device *)sc;
@@ -248,21 +260,27 @@ algor_intr_establish(ca, handler, arg)
 		int_table[slot].int_hand = handler;
 		int_table[slot].param = arg;
 	}
-	p4032_ixr |= ipxrtab[ipl] & dev->ps_route;
-	outb(P4032_IXR0, p4032_ixr);
-	outb(P4032_IXR1, p4032_ixr >> 8);
-	outb(P4032_IXR2, p4032_ixr >> 16);
+	p4032_ixr0 |= ipxrtab[ipl] & dev->ps_route;
+	switch(system_type) {
+	case ALGOR_P4032:
+		outb(P4032_IXR0, p4032_ixr0);
+		outb(P4032_IXR1, p4032_ixr0 >> 8);
+		break;
+	case ALGOR_P5064:
+		outb(P5064_IXR0, p4032_ixr0);
+		outb(P5064_IXR1, p4032_ixr0 >> 8);
+		break;
+	}
 
 	if(slot == 0) {		/* Slot 0 is special, clock */
-		set_intr(INT_MASK_0 << ipl, algor_clkintr, ipl + 1);
+		set_intr(INT_MASK_0 << ipl, algor_clkintr, ipl + 2);
 	}
 	else {
-		set_intr(INT_MASK_0 << ipl, algor_iointr, ipl + 1);
+		set_intr(INT_MASK_0 << ipl, algor_iointr, ipl + 2);
 	}
 
 	p4032_imask |= dev->ps_mask;
 	outb(P4032_IMR, p4032_imask);
-	outb(P4032_PCIIMR, p4032_imask >> 8);
 }
 
 void *
@@ -280,12 +298,25 @@ algor_pci_intr_establish(ih, level, handler, arg, name)
 	if(level < IPL_BIO || level >= IPL_CLOCK) {
 		panic("pci intr: ipl level out of range");
 	}
-	if(ih < 0 || ih >= 4) {
+	if(ih < 0 || ih >= 12 || ih == 7 || ih == 8) {
 		panic("pci intr: irq out of range");
 	}
 
-	imask = (0x1000 << ih);
-	route = (0x30000 << (ih+ih));
+	switch(system_type) {
+	case ALGOR_P4032:
+		imask = (0x00001000 << ih);
+		route = (0x3 << (ih+ih));
+		break;
+	case ALGOR_P5064:
+		if(ih > 8) {
+			imask = (0x00000100 << (ih - 8));
+		}
+		else {
+			imask = (0x00001000 << ih);
+		}
+		route = (0x3 << (ih+ih));
+		break;
+	}
 
 	slot = NUM_INT_SLOTS;
 	while(slot > 0) {
@@ -301,12 +332,19 @@ algor_pci_intr_establish(ih, level, handler, arg, name)
 	int_table[slot].int_hand = handler;
 	int_table[slot].param = arg;
 
-	p4032_ixr |= ipxrtab[level] & route;
-	outb(P4032_IXR0, p4032_ixr);
-	outb(P4032_IXR1, p4032_ixr >> 8);
-	outb(P4032_IXR2, p4032_ixr >> 16);
+	p4032_ixr1 |= ipxrtab[level] & route;
+	switch(system_type) {
+	case ALGOR_P4032:
+		outb(P4032_IXR2, p4032_ixr1);
+		break;
+	case ALGOR_P5064:
+		outb(P5064_IXR2, p4032_ixr1);
+		outb(P5064_IXR3, p4032_ixr1 >> 8);
+		outb(P5064_IXR4, p4032_ixr1 >> 16);
+		break;
+	}
 
-	set_intr(INT_MASK_0 << level, algor_iointr, level + 1);
+	set_intr(INT_MASK_0 << level, algor_iointr, level + 2);
 
 	p4032_imask |= imask;
 	outb(P4032_IMR, p4032_imask);
@@ -395,8 +433,14 @@ algor_clkintr(mask, cf)
 	struct clockframe *cf;
 {
 	/* Ack clock interrupt */
-	outb(P4032_CLOCK, MC_REGC);
-	(void) inb(P4032_CLOCK + 4);
+	if(system_type == ALGOR_P4032) {
+		outb(P4032_CLOCK, MC_REGC);
+		(void) inb(P4032_CLOCK + 4);
+	}
+	else {
+		outb(P5064_CLOCK, MC_REGC);
+		(void) inb(P5064_CLOCK + 1);
+	}
 
 	hardclock(cf);
 
@@ -407,7 +451,7 @@ algor_clkintr(mask, cf)
 }
 
 /*
- * Handle algor interval clock interrupt.
+ * Handle algor error interrupt.
  */
 int
 algor_errintr(mask, cf)
@@ -421,18 +465,21 @@ algor_errintr(mask, cf)
 	if(why & P4032_IRR_BER) {
 		printf("Bus error interrupt\n");
 		outb(P4032_ICR, P4032_IRR_BER);
+#ifdef DDB
+		Debugger();
+#endif
 	}
 	if(why & P4032_IRR_PFAIL) {
 		printf("Power failure!\n");
 	}
 	if(why & P4032_IRR_DBG) {
 		printf("Debug switch\n");
-		outb(P4032_ICR, P4032_IRR_DBG);
-#ifdef DEBUG
-		mdbpanic();
+#ifdef DDB
+		Debugger();
 #else
-		printf("Not DEBUG compiled, sorry!\n");
+		printf("Sorry, recompile kernel with DDB!\n");
 #endif
+		outb(P4032_ICR, P4032_IRR_DBG);
 	}
 	return(~0);
 }
diff --git a/sys/arch/arc/arc/clock_mc.c b/sys/arch/arc/arc/clock_mc.c
index c8ce08742d5..430f158df79 100644
--- a/sys/arch/arc/arc/clock_mc.c
+++ b/sys/arch/arc/arc/clock_mc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: clock_mc.c,v 1.8 1998/01/28 13:45:47 pefo Exp $	*/
+/*	$OpenBSD: clock_mc.c,v 1.9 1998/03/16 09:38:26 pefo Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -71,7 +71,7 @@ void		md_clk_attach __P((struct device *parent,
 		    struct device *self, void *aux));
 static void	mcclock_init_pica __P((struct clock_softc *csc));
 static void	mcclock_init_tyne __P((struct clock_softc *csc));
-static void	mcclock_init_p4032 __P((struct clock_softc *csc));
+static void	mcclock_init_algor __P((struct clock_softc *csc));
 static void	mcclock_get __P((struct clock_softc *csc, time_t base,
 		    struct tod_time *ct));
 static void	mcclock_set __P((struct clock_softc *csc,
@@ -100,11 +100,11 @@ static void	mc_write_tyne __P((struct clock_softc *csc, u_int reg,
 static u_int	mc_read_tyne __P((struct clock_softc *csc, u_int reg));
 static struct mcclockdata mcclockdata_tyne = { mc_write_tyne, mc_read_tyne };
 
-/* Algorithmics P4032 clock access code */
-static void	mc_write_p4032 __P((struct clock_softc *csc, u_int reg,
+/* Algorithmics clock access code */
+static void	mc_write_algor __P((struct clock_softc *csc, u_int reg,
 		    u_int datum));
-static u_int	mc_read_p4032 __P((struct clock_softc *csc, u_int reg));
-static struct mcclockdata mcclockdata_p4032 = { mc_write_p4032, mc_read_p4032 };
+static u_int	mc_read_algor __P((struct clock_softc *csc, u_int reg));
+static struct mcclockdata mcclockdata_algor = { mc_write_algor, mc_read_algor };
 
 void
 md_clk_attach(parent, self, aux)
@@ -122,6 +122,7 @@ md_clk_attach(parent, self, aux)
         switch (system_type) {
 
         case ACER_PICA_61:
+	case MAGNUM:
 		csc->sc_init = mcclock_init_pica;
 		csc->sc_data = &mcclockdata_pica;
 		mc146818_write(csc, MC_REGB, MC_REGB_BINARY | MC_REGB_24HR);
@@ -135,8 +136,9 @@ md_clk_attach(parent, self, aux)
 		break;
 
 	case ALGOR_P4032:
-		csc->sc_init = mcclock_init_p4032;
-		csc->sc_data = &mcclockdata_p4032;
+	case ALGOR_P5064:
+		csc->sc_init = mcclock_init_algor;
+		csc->sc_data = &mcclockdata_algor;
 		mc146818_write(csc, MC_REGB, MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_SQWE);
 		break;
 
@@ -175,7 +177,7 @@ clockintr(cf)
 }
 
 static void
-mcclock_init_p4032(csc)
+mcclock_init_algor(csc)
 	struct clock_softc *csc;
 {
 	int s;
@@ -213,8 +215,10 @@ mcclock_get(csc, base, ct)
 	ct->day = regs[MC_DOM];
 	ct->mon = regs[MC_MONTH];
 	ct->year = regs[MC_YEAR];
-	if(system_type == ALGOR_P4032)
+	if(system_type == ALGOR_P4032 ||
+	   system_type == ALGOR_P5064) {
 		ct->year -= 80;
+	}
 }
 
 /*
@@ -238,10 +242,13 @@ printf("%d-%d-%d, %d:%d:%d\n", regs[MC_YEAR], regs[MC_MONTH], regs[MC_DOM], regs
 	regs[MC_DOW] = ct->dow;
 	regs[MC_DOM] = ct->day;
 	regs[MC_MONTH] = ct->mon;
-	if(system_type == ALGOR_P4032)
+	if(system_type == ALGOR_P4032 ||
+	   system_type == ALGOR_P4032) {
 		regs[MC_YEAR] = ct->year + 80;
-	else
+	}
+	else {
 		regs[MC_YEAR] = ct->year;
+	}
 
 	MC146818_PUTTOD(csc, &regs);
 	MC146818_GETTOD(csc, &regs);
@@ -296,22 +303,34 @@ mc_read_tyne(csc, reg)
 }
 
 static void
-mc_write_p4032(csc, reg, datum)
+mc_write_algor(csc, reg, datum)
 	struct clock_softc *csc;
 	u_int reg, datum;
 {
-	outb(P4032_CLOCK, reg);
-	outb(P4032_CLOCK+4, datum);
+	if(system_type == ALGOR_P4032) {
+		outb(P4032_CLOCK, reg);
+		outb(P4032_CLOCK+4, datum);
+	}
+	else {
+		outb(P5064_CLOCK, reg);
+		outb(P5064_CLOCK+1, datum);
+	}
 }
 
 static u_int
-mc_read_p4032(csc, reg)
+mc_read_algor(csc, reg)
 	struct clock_softc *csc;
 	u_int reg;
 {
 	int i;
 
-	outb(P4032_CLOCK, reg);
-	i = inb(P4032_CLOCK+4) & 0xff;
+	if(system_type == ALGOR_P4032) {
+		outb(P4032_CLOCK, reg);
+		i = inb(P4032_CLOCK+4) & 0xff;
+	}
+	else {
+		outb(P5064_CLOCK, reg);
+		i = inb(P5064_CLOCK+1) & 0xff;
+	}
 	return(i);
 }
diff --git a/sys/arch/arc/arc/locore.S b/sys/arch/arc/arc/locore.S
index b1352065795..031cd21d539 100644
--- a/sys/arch/arc/arc/locore.S
+++ b/sys/arch/arc/arc/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.15 1998/03/01 18:58:26 niklas Exp $	*/
+/*	$OpenBSD: locore.S,v 1.16 1998/03/16 09:38:28 pefo Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -50,7 +50,7 @@
  *	v 1.1 89/07/10 14:27:41 nelson Exp  SPRITE (DECWRL)
  *
  *	from: @(#)locore.s	8.5 (Berkeley) 1/4/94
- *	$Id: locore.S,v 1.15 1998/03/01 18:58:26 niklas Exp $
+ *	$Id: locore.S,v 1.16 1998/03/16 09:38:28 pefo Exp $
  */
 
 /*
@@ -78,8 +78,8 @@
 #define START_FRAME	((4 * 4) + 4 + 4)
 
 	.globl	start
-	.globl	kernel_start
-kernel_start = start
+	.globl	kernel_text
+kernel_text = start
 start:
 	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
 	mtc0	zero, COP_0_CAUSE_REG	# Clear soft interrupts
@@ -175,9 +175,11 @@ onfault_table:
 	.word	fswberr
 #define FSWINTRBERR	4
 	.word	fswintrberr
-#ifdef MDB
-#define MDBERR		5
-	.word	mdberr
+#if defined(DDB)
+#define	DDBERR		5
+	.word	ddberr
+#else
+	.word	0
 #endif
 	.text
 
@@ -1041,107 +1043,128 @@ SlowFault:
  *
  *----------------------------------------------------------------------------
  */
+#ifndef MIPS_ISAIII
+#define	STORE	sw	/* 32 bit mode regsave instruction */
+#define	LOAD	lw	/* 32 bit mode regload instruction */
+#define	RSIZE	4	/* 32 bit mode register size */
+#else
+#define	STORE	sd	/* 64 bit mode regsave instruction */
+#define	STORE	ld	/* 64 bit mode regload instruction */
+#define	RSIZE	8	/* 64 bit mode register size */
+#endif
+
+#define	SAVE_REG(reg, offs, base) \
+	STORE	reg, STAND_ARG_SIZE + (RSIZE * offs) (base)
+
+#define	SAVE_CPU \
+	SAVE_REG(AT, AST, sp)		;\
+	SAVE_REG(v0, V0, sp)		;\
+	SAVE_REG(v1, V1, sp)		;\
+	mflo	v0			;\
+	mfhi	v1			;\
+	SAVE_REG(a0, A0, sp)		;\
+	SAVE_REG(a1, A1, sp)		;\
+	SAVE_REG(a2, A2, sp)		;\
+	SAVE_REG(a3, A3, sp)		;\
+	mfc0	a0, COP_0_STATUS_REG	;\
+	mfc0	a1, COP_0_CAUSE_REG	;\
+	mfc0	a2, COP_0_BAD_VADDR	;\
+	mfc0	a3, COP_0_EXC_PC	;\
+	SAVE_REG(t0, T0, sp)		;\
+	SAVE_REG(t1, T1, sp)		;\
+	SAVE_REG(t2, T2, sp)		;\
+	SAVE_REG(t3, T3, sp)		;\
+	SAVE_REG(t4, T4, sp)		;\
+	SAVE_REG(t5, T5, sp)		;\
+	SAVE_REG(t6, T6, sp)		;\
+	SAVE_REG(t7, T7, sp)		;\
+	SAVE_REG(t8, T8, sp)		;\
+	SAVE_REG(t9, T9, sp)		;\
+	SAVE_REG(v0, MULLO, sp)		;\
+	SAVE_REG(v1, MULHI, sp)		;\
+	SAVE_REG(a0, SR, sp)		;\
+	SAVE_REG(a1, CAUSE, sp)		;\
+	SAVE_REG(ra, RA, sp)		;\
+	SAVE_REG(a2, BADVADDR, sp)	;\
+	SAVE_REG(a3, PC, sp)		;\
+	addu	v0, sp, KERN_EXC_FRAME_SIZE ;\
+	SAVE_REG(v0, SP, sp)		;\
+	mtc0	zero,COP_0_STATUS_REG
+
+#ifdef DDB
+#define	SAVE_CPU_DDB \
+	SAVE_REG(s0, S0, sp)		;\
+	SAVE_REG(s1, S1, sp)		;\
+	SAVE_REG(s2, S2, sp)		;\
+	SAVE_REG(s3, S3, sp)		;\
+	SAVE_REG(s4, S4, sp)		;\
+	SAVE_REG(s5, S5, sp)		;\
+	SAVE_REG(s6, S6, sp)		;\
+	SAVE_REG(s7, S7, sp)		;\
+	SAVE_REG(s8, S8, sp)
+#else
+#define	SAVE_CPU_DDB
+#endif
+
+#define	RESTORE_REG(reg, offs, base) \
+	LOAD	reg, STAND_ARG_SIZE + (RSIZE * offs) (base)
+
+#define	RESTORE_CPU \
+	mtc0	zero,COP_0_STATUS_REG	;\
+	RESTORE_REG(a0, SR, sp)		;\
+	RESTORE_REG(t0, MULLO, sp)	;\
+	RESTORE_REG(t1, MULHI, sp)	;\
+	mtc0	a0, COP_0_STATUS_REG	;\
+	mtlo	t0			;\
+	mthi	t1			;\
+	dmtc0	v0, COP_0_EXC_PC	;\
+	RESTORE_REG(AT, AST, sp)		;\
+	RESTORE_REG(v0, V0, sp)		;\
+	RESTORE_REG(v1, V1, sp)		;\
+	RESTORE_REG(a0, A0, sp)		;\
+	RESTORE_REG(a1, A1, sp)		;\
+	RESTORE_REG(a2, A2, sp)		;\
+	RESTORE_REG(a3, A3, sp)		;\
+	RESTORE_REG(t0, T0, sp)		;\
+	RESTORE_REG(t1, T1, sp)		;\
+	RESTORE_REG(t2, T2, sp)		;\
+	RESTORE_REG(t3, T3, sp)		;\
+	RESTORE_REG(t4, T4, sp)		;\
+	RESTORE_REG(t5, T5, sp)		;\
+	RESTORE_REG(t6, T6, sp)		;\
+	RESTORE_REG(t7, T7, sp)		;\
+	RESTORE_REG(t8, T8, sp)		;\
+	RESTORE_REG(t9, T9, sp)		;\
+	RESTORE_REG(ra, RA, sp)		;\
+	addu	sp, sp, KERN_EXC_FRAME_SIZE
 
 /*
  * The kernel exception stack contains 18 saved general registers,
  * the status register and the multiply lo and high registers.
  * In addition, we set this up for linkage conventions.
  */
-#define KERN_REG_SIZE		(18 * 4)
-#define KERN_REG_OFFSET		(STAND_FRAME_SIZE)
-#define KERN_SR_OFFSET		(STAND_FRAME_SIZE + KERN_REG_SIZE)
-#define KERN_MULT_LO_OFFSET	(STAND_FRAME_SIZE + KERN_REG_SIZE + 4)
-#define KERN_MULT_HI_OFFSET	(STAND_FRAME_SIZE + KERN_REG_SIZE + 8)
-#define	KERN_EXC_FRAME_SIZE	(STAND_FRAME_SIZE + KERN_REG_SIZE + 12)
+#define KERN_REG_SIZE		(NUMSAVEREGS * RSIZE)
+#define	KERN_EXC_FRAME_SIZE	(STAND_FRAME_SIZE + KERN_REG_SIZE + 16)
 
 NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra)
 	.set	noat
-#ifdef MDB
-	la	k0, mdbpcb			# save registers for mdb
-	sw	s0, (S0 * 4)(k0)
-	sw	s1, (S1 * 4)(k0)
-	sw	s2, (S2 * 4)(k0)
-	sw	s3, (S3 * 4)(k0)
-	sw	s4, (S4 * 4)(k0)
-	sw	s5, (S5 * 4)(k0)
-	sw	s6, (S6 * 4)(k0)
-	sw	s7, (S7 * 4)(k0)
-	sw	s8, (S8 * 4)(k0)
-	sw	gp, (GP * 4)(k0)
-	sw	sp, (SP * 4)(k0)
-#endif
 	subu	sp, sp, KERN_EXC_FRAME_SIZE
 	.mask	0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE)
 /*
- * Save the relevant kernel registers onto the stack.
- * We don't need to save s0 - s8, sp and gp because
- * the compiler does it for us.
+ *  Save CPU state, building 'frame'.
  */
-	sw	AT, KERN_REG_OFFSET + 0(sp)
-	sw	v0, KERN_REG_OFFSET + 4(sp)
-	sw	v1, KERN_REG_OFFSET + 8(sp)
-	sw	a0, KERN_REG_OFFSET + 12(sp)
-	mflo	v0
-	mfhi	v1
-	sw	a1, KERN_REG_OFFSET + 16(sp)
-	sw	a2, KERN_REG_OFFSET + 20(sp)
-	sw	a3, KERN_REG_OFFSET + 24(sp)
-	sw	t0, KERN_REG_OFFSET + 28(sp)
-	mfc0	a0, COP_0_STATUS_REG	# First arg is the status reg.
-	sw	t1, KERN_REG_OFFSET + 32(sp)
-	sw	t2, KERN_REG_OFFSET + 36(sp)
-	sw	t3, KERN_REG_OFFSET + 40(sp)
-	sw	t4, KERN_REG_OFFSET + 44(sp)
-	mfc0	a1, COP_0_CAUSE_REG	# Second arg is the cause reg.
-	sw	t5, KERN_REG_OFFSET + 48(sp)
-	sw	t6, KERN_REG_OFFSET + 52(sp)
-	sw	t7, KERN_REG_OFFSET + 56(sp)
-	sw	t8, KERN_REG_OFFSET + 60(sp)
-	mfc0	a2, COP_0_BAD_VADDR	# Third arg is the fault addr.
-	sw	t9, KERN_REG_OFFSET + 64(sp)
-	sw	ra, KERN_REG_OFFSET + 68(sp)
-	sw	v0, KERN_MULT_LO_OFFSET(sp)
-	sw	v1, KERN_MULT_HI_OFFSET(sp)
-	mfc0	a3, COP_0_EXC_PC		# Fourth arg is the pc.
-	sw	a0, KERN_SR_OFFSET(sp)
-
-	mtc0	zero,COP_0_STATUS_REG	# Set kernel no error level
+	SAVE_CPU
+	SAVE_CPU_DDB
 /*
- * Call the exception handler.
+ *  Call the exception handler.
  */
 	jal	trap
-	sw	a3, STAND_RA_OFFSET(sp)		# for debugging
+	sw	a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp)		# for debugging
 /*
  * Restore registers and return from the exception.
  * v0 contains the return address.
  */
-	mtc0	zero,COP_0_STATUS_REG	# Make shure int disabled
-	lw	a0, KERN_SR_OFFSET(sp)
-	lw	t0, KERN_MULT_LO_OFFSET(sp)
-	lw	t1, KERN_MULT_HI_OFFSET(sp)
-	mtc0	a0, COP_0_STATUS_REG	# Restore the SR, disable intrs
-	mtlo	t0
-	mthi	t1
-	dmtc0	v0, COP_0_EXC_PC		# set return address
-	lw	AT, KERN_REG_OFFSET + 0(sp)
-	lw	v0, KERN_REG_OFFSET + 4(sp)
-	lw	v1, KERN_REG_OFFSET + 8(sp)
-	lw	a0, KERN_REG_OFFSET + 12(sp)
-	lw	a1, KERN_REG_OFFSET + 16(sp)
-	lw	a2, KERN_REG_OFFSET + 20(sp)
-	lw	a3, KERN_REG_OFFSET + 24(sp)
-	lw	t0, KERN_REG_OFFSET + 28(sp)
-	lw	t1, KERN_REG_OFFSET + 32(sp)
-	lw	t2, KERN_REG_OFFSET + 36(sp)
-	lw	t3, KERN_REG_OFFSET + 40(sp)
-	lw	t4, KERN_REG_OFFSET + 44(sp)
-	lw	t5, KERN_REG_OFFSET + 48(sp)
-	lw	t6, KERN_REG_OFFSET + 52(sp)
-	lw	t7, KERN_REG_OFFSET + 56(sp)
-	lw	t8, KERN_REG_OFFSET + 60(sp)
-	lw	t9, KERN_REG_OFFSET + 64(sp)
-	lw	ra, KERN_REG_OFFSET + 68(sp)
-	addu	sp, sp, KERN_EXC_FRAME_SIZE
+	RESTORE_CPU
 	eret					#  exception.
 	.set	at
 END(MipsKernGenException)
@@ -1285,87 +1308,28 @@ END(MipsUserGenException)
  *
  *----------------------------------------------------------------------------
  */
-#define KINTR_REG_OFFSET	(STAND_FRAME_SIZE)
-#define KINTR_SR_OFFSET		(STAND_FRAME_SIZE + KERN_REG_SIZE)
-#define KINTR_MULT_LO_OFFSET	(STAND_FRAME_SIZE + KERN_REG_SIZE + 4)
-#define KINTR_MULT_HI_OFFSET	(STAND_FRAME_SIZE + KERN_REG_SIZE + 8)
-#define KINTR_MULT_GP_OFFSET	(STAND_FRAME_SIZE + KERN_REG_SIZE + 12)
-#define	KINTR_FRAME_SIZE	(STAND_FRAME_SIZE + KERN_REG_SIZE + 16)
 
-NNON_LEAF(MipsKernIntr, KINTR_FRAME_SIZE, ra)
+NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
 	.set	noat
-	subu	sp, sp, KINTR_FRAME_SIZE	# allocate stack frame
-	.mask	0x80000000, (STAND_RA_OFFSET - KINTR_FRAME_SIZE)
+	subu	sp, sp, KERN_EXC_FRAME_SIZE
+	.mask	0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE)
 /*
  * Save the relevant kernel registers onto the stack.
  * We don't need to save s0 - s8, sp and gp because
  * the compiler does it for us.
  */
-	sw	AT, KINTR_REG_OFFSET + 0(sp)
-	sw	v0, KINTR_REG_OFFSET + 4(sp)
-	sw	v1, KINTR_REG_OFFSET + 8(sp)
-	sw	a0, KINTR_REG_OFFSET + 12(sp)
-	mflo	v0
-	mfhi	v1
-	sw	a1, KINTR_REG_OFFSET + 16(sp)
-	sw	a2, KINTR_REG_OFFSET + 20(sp)
-	sw	a3, KINTR_REG_OFFSET + 24(sp)
-	sw	t0, KINTR_REG_OFFSET + 28(sp)
-	mfc0	a0, COP_0_STATUS_REG	# First arg is the status reg.
-	sw	t1, KINTR_REG_OFFSET + 32(sp)
-	sw	t2, KINTR_REG_OFFSET + 36(sp)
-	sw	t3, KINTR_REG_OFFSET + 40(sp)
-	sw	t4, KINTR_REG_OFFSET + 44(sp)
-	mfc0	a1, COP_0_CAUSE_REG	# Second arg is the cause reg.
-	sw	t5, KINTR_REG_OFFSET + 48(sp)
-	sw	t6, KINTR_REG_OFFSET + 52(sp)
-	sw	t7, KINTR_REG_OFFSET + 56(sp)
-	sw	t8, KINTR_REG_OFFSET + 60(sp)
-	mfc0	a2, COP_0_EXC_PC		# Third arg is the pc.
-	sw	t9, KINTR_REG_OFFSET + 64(sp)
-	sw	ra, KINTR_REG_OFFSET + 68(sp)
-	sw	v0, KINTR_MULT_LO_OFFSET(sp)
-	sw	v1, KINTR_MULT_HI_OFFSET(sp)
-	sw	a0, KINTR_SR_OFFSET(sp)
-
-	mtc0	zero, COP_0_STATUS_REG	# Reset exl, trap possible.
+	SAVE_CPU
 /*
  * Call the interrupt handler.
  */
 	jal	interrupt
-	sw	a2, STAND_RA_OFFSET(sp)		# for debugging
+	sw	a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp)
 /*
  * Restore registers and return from the interrupt.
  */
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupt
-	lw	a0, KINTR_SR_OFFSET(sp)
-	lw	t0, KINTR_MULT_LO_OFFSET(sp)
-	lw	t1, KINTR_MULT_HI_OFFSET(sp)
-	mtc0	a0, COP_0_STATUS_REG	# Restore the SR, disable intrs
-	mtlo	t0
-	mthi	t1
-	lw	a0, STAND_RA_OFFSET(sp)
-	lw	AT, KINTR_REG_OFFSET + 0(sp)
-	lw	v0, KINTR_REG_OFFSET + 4(sp)
-	dmtc0	a0, COP_0_EXC_PC		# set return address
-	lw	v1, KINTR_REG_OFFSET + 8(sp)
-	lw	a0, KINTR_REG_OFFSET + 12(sp)
-	lw	a1, KINTR_REG_OFFSET + 16(sp)
-	lw	a2, KINTR_REG_OFFSET + 20(sp)
-	lw	a3, KINTR_REG_OFFSET + 24(sp)
-	lw	t0, KINTR_REG_OFFSET + 28(sp)
-	lw	t1, KINTR_REG_OFFSET + 32(sp)
-	lw	t2, KINTR_REG_OFFSET + 36(sp)
-	lw	t3, KINTR_REG_OFFSET + 40(sp)
-	lw	t4, KINTR_REG_OFFSET + 44(sp)
-	lw	t5, KINTR_REG_OFFSET + 48(sp)
-	lw	t6, KINTR_REG_OFFSET + 52(sp)
-	lw	t7, KINTR_REG_OFFSET + 56(sp)
-	lw	t8, KINTR_REG_OFFSET + 60(sp)
-	lw	t9, KINTR_REG_OFFSET + 64(sp)
-	lw	ra, KINTR_REG_OFFSET + 68(sp)
-	addu	sp, sp, KINTR_FRAME_SIZE
-	eret					#  interrupt.
+	lw	v0, STAND_RA_OFFSET + KERN_REG_SIZE(sp)
+	RESTORE_CPU
+	eret
 	.set	at
 END(MipsKernIntr)
 
@@ -1415,7 +1379,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
 	sw	t6, UADDR+U_PCB_REGS+(T6 * 4)
 	sw	t7, UADDR+U_PCB_REGS+(T7 * 4)
 	sw	t8, UADDR+U_PCB_REGS+(T8 * 4)
-	mfc0	a2, COP_0_EXC_PC		# Third arg is the pc.
+	mfc0	a3, COP_0_EXC_PC		# Fourth arg is the pc.
 	sw	t9, UADDR+U_PCB_REGS+(T9 * 4)
 	sw	gp, UADDR+U_PCB_REGS+(GP * 4)
 	sw	sp, UADDR+U_PCB_REGS+(SP * 4)
@@ -1424,7 +1388,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
 	sw	v0, UADDR+U_PCB_REGS+(MULLO * 4)
 	sw	v1, UADDR+U_PCB_REGS+(MULHI * 4)
 	sw	a0, UADDR+U_PCB_REGS+(SR * 4)
-	sw	a2, UADDR+U_PCB_REGS+(PC * 4)
+	sw	a3, UADDR+U_PCB_REGS+(PC * 4)
 	la	gp, _gp				# switch to kernel GP
 # Turn off fpu and enter kernel mode
 	.set	at
@@ -1435,7 +1399,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
  * Call the interrupt handler.
  */
 	jal	interrupt
-	sw	a2, STAND_RA_OFFSET(sp)		# for debugging
+	sw	a3, STAND_RA_OFFSET(sp)		# for debugging
 /*
  * Restore registers and return from the interrupt.
  */
@@ -2677,7 +2641,7 @@ LEAF(R4K_ConfigCache)
 	beq	v1, t1, 1f
 	li	t1, (MIPS_R5000 << 8)
 	beq	v1, t1, 1f
-	li	t1, (MIPS_RM5230 << 8)
+	li	t1, (MIPS_RM52X0 << 8)
 	beq	v1, t1, 1f
 	li	t2, 1
 
@@ -2974,159 +2938,101 @@ END(R4K_HitFlushDCache)
 LEAF(R4K_InvalidateDCache)
 	addu	a1, a1, a0			# compute ending address
 1:
-	cache	0x11,8194(a0)
+	cache	0x11, 8194(a0)
 	addu	a0, a0, 4
 	bne	a0, a1, 1b
-	cache	0x11,-4(a0)
+	cache	0x11, -4(a0)
 
 	j	ra
 	nop
 END(R4K_InvalidateDCache)
 
-#ifdef MDB
-/*
- * Read a long and return it.
- * Note: addresses can be unaligned!
- *
- * long
-L* mdbpeek(addr)
-L*	caddt_t addr;
-L* {
-L*	return (*(long *)addr);
-L* }
- */
-LEAF(mdbpeek)
-	li	v0, MDBERR
-	sw	v0, UADDR+U_PCB_ONFAULT
-	and	v0, a0, 3		# unaligned address?
+#if defined(DDB)
+LEAF(kdbpeek)
+	li	v0, DDBERR
+	and	v0, a0, 3			# unaligned ?
 	bne	v0, zero, 1f
-	nop
-	b	2f
-	lw	v0, (a0)		# aligned access
+	sw	v0, UADDR+U_PCB_ONFAULT
+
+	lw	v0, (a0)
+	jr	ra
+	sw	zero, UADDR+U_PCB_ONFAULT
+
 1:
-	LWHI	v0, 0(a0)		# get next 4 bytes (unaligned)
+	LWHI	v0, 0(a0)
 	LWLO	v0, 3(a0)
-2:
-	j	ra			# made it w/o errors
+	jr	ra
 	sw	zero, UADDR+U_PCB_ONFAULT
-mdberr:
-	li	v0, 1			# trap sends us here
-	sw	v0, mdbmkfault
-	j	ra
-	nop
-END(mdbpeek)
+END(kdbpeek)
 
-/*
- * Write a long to 'addr'.
- * Note: addresses can be unaligned!
- *
-L* void
-L* mdbpoke(addr, value)
-L*	caddt_t addr;
-L*	long value;
-L* {
-L*	*(long *)addr = value;
-L* }
- */
-LEAF(mdbpoke)
-	li	v0, MDBERR
-	sw	v0, UADDR+U_PCB_ONFAULT
-	and	v0, a0, 3		# unaligned address?
+LEAF(kdbpoke)
+	li	v0, DDBERR
+	and	v0, a0, 3			# unaligned ?
 	bne	v0, zero, 1f
-	nop
-	b	2f
-	sw	a1, (a0)		# aligned access
+	sw	v0, UADDR+U_PCB_ONFAULT
+
+	sw	a1, (a0)
+	jr	ra
+	sw	zero, UADDR+U_PCB_ONFAULT
+
 1:
-	SWHI	a1, 0(a0)		# store next 4 bytes (unaligned)
+	SWHI	a1, 0(a0)
 	SWLO	a1, 3(a0)
-	and	a0, a0, ~3		# align address for cache flush
-2:
+	jr	ra
 	sw	zero, UADDR+U_PCB_ONFAULT
-	b	R4K_FlushICache		# flush instruction cache
-	li	a1, 8
-END(mdbpoke)
-
-/*
- * Save registers and state so we can do a 'mdbreset' (like longjmp) later.
- * Always returns zero.
- *
-L* int mdb_savearea[11];
-L*
-L* int
-L* mdbsetexit()
-L* {
-L*	mdb_savearea[0] = 0;
-L*	return (0);
-L* }
- */
-	.comm	mdb_savearea, (11 * 4)
-
-LEAF(mdbsetexit)
-	la	a0, mdb_savearea
-	sw	s0, 0(a0)
-	sw	s1, 4(a0)
-	sw	s2, 8(a0)
-	sw	s3, 12(a0)
-	sw	s4, 16(a0)
-	sw	s5, 20(a0)
-	sw	s6, 24(a0)
-	sw	s7, 28(a0)
-	sw	sp, 32(a0)
-	sw	s8, 36(a0)
-	sw	ra, 40(a0)
-	j	ra
-	move	v0, zero
-END(mdbsetexit)
-
-/*
- * Restore registers and state (like longjmp) and return x.
- *
-L* int
-L* mdbreset(x)
-L* {
-L*	return (x);
-L* }
- */
-LEAF(mdbreset)
-	la	v0, mdb_savearea
-	lw	ra, 40(v0)
-	lw	s0, 0(v0)
-	lw	s1, 4(v0)
-	lw	s2, 8(v0)
-	lw	s3, 12(v0)
-	lw	s4, 16(v0)
-	lw	s5, 20(v0)
-	lw	s6, 24(v0)
-	lw	s7, 28(v0)
-	lw	sp, 32(v0)
-	lw	s8, 36(v0)
-	j	ra
-	move	v0, a0
-END(mdbreset)
+END(kdbpoke)
 
-/*
- * Trap into the debugger.
- *
-L* void
-L* mdbpanic()
-L* {
-L* }
- */
-LEAF(mdbpanic)
-	break	BREAK_SOVER_VAL
-	j	ra
+ddberr:
+	jr	ra
 	nop
-END(mdbpanic)
-#endif /* MDB */
 
-#ifdef MDB
-LEAF(cpu_getregs)
-	sw	sp, 0(a0)
-	sw	ra, 4(a0)
-	j	ra
-	sw	s8, 8(a0)
-END(cpu_getregs)
-#endif /* MDB */
+LEAF(Debugger)
+	break   BREAK_SOVER_VAL
+	jr	ra
+	nop
+END(Debugger)
+
+LEAF(setjmp)
+	mfc0	v0, COP_0_STATUS_REG	# Later the "real" spl value!
+	STORE	s0, RSIZE * 0(a0)
+	STORE	s1, RSIZE * 1(a0)
+	STORE	s2, RSIZE * 2(a0)
+	STORE	s3, RSIZE * 3(a0)
+	STORE	s4, RSIZE * 4(a0)
+	STORE	s5, RSIZE * 5(a0)
+	STORE	s6, RSIZE * 6(a0)
+	STORE	s7, RSIZE * 7(a0)
+	STORE	s8, RSIZE * 8(a0)
+	STORE	sp, RSIZE * 9(a0)
+	STORE	ra, RSIZE * 10(a0)
+	STORE	v0, RSIZE * 11(a0)
+	jr	ra
+	li	v0, 0			# setjmp return
+END(setjmp)
+
+LEAF(longjmp)
+	LOAD	v0, RSIZE * 11(a0)
+	LOAD	ra, RSIZE * 10(a0)
+	LOAD	s0, RSIZE * 0(a0)
+	LOAD	s1, RSIZE * 1(a0)
+	LOAD	s2, RSIZE * 2(a0)
+	LOAD	s3, RSIZE * 3(a0)
+	LOAD	s4, RSIZE * 4(a0)
+	LOAD	s5, RSIZE * 5(a0)
+	LOAD	s6, RSIZE * 6(a0)
+	LOAD	s7, RSIZE * 7(a0)
+	LOAD	s8, RSIZE * 8(a0)
+	LOAD	sp, RSIZE * 9(a0)
+	mtc0	v0, COP_0_STATUS_REG	# Later the "real" spl value!
+	jr	ra
+	li	v0, 1			# longjmp return
+END(longjmp)
+
+	.data
+	.globl	esym
+esym:	.word	0
+
+#endif
 
 /*
  * Interrupt counters for vmstat.
diff --git a/sys/arch/arc/arc/machdep.c b/sys/arch/arc/arc/machdep.c
index 3a40637c822..42020b3cf2d 100644
--- a/sys/arch/arc/arc/machdep.c
+++ b/sys/arch/arc/arc/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.30 1998/01/28 13:45:55 pefo Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.31 1998/03/16 09:38:30 pefo Exp $	*/
 /*
  * Copyright (c) 1988 University of Utah.
  * Copyright (c) 1992, 1993
@@ -38,7 +38,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)machdep.c	8.3 (Berkeley) 1/12/94
- *      $Id: machdep.c,v 1.30 1998/01/28 13:45:55 pefo Exp $
+ *      $Id: machdep.c,v 1.31 1998/03/16 09:38:30 pefo Exp $
  */
 
 /* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@@ -100,7 +100,7 @@
 #include <arc/algor/algor.h>
 
 extern struct consdev *cn_tab;
-extern char kernel_start[];
+extern char kernel_text[];
 extern void makebootdev __P((char *));
 extern void stacktrace __P((void));
 extern void configure __P((void));
@@ -222,17 +222,6 @@ mips_init(argc, argv, envv)
 		arc_bus_io.bus_base = PICA_V_ISA_IO;
 		arc_bus_mem.bus_base = PICA_V_ISA_MEM;
 		CONADDR = 0;
-
-		/*
-		 * Set up interrupt handling and I/O addresses.
-		 */
-#if 0 /* XXX FIXME */
-		Mips_splnet = Mips_spl1;
-		Mips_splbio = Mips_spl0;
-		Mips_splimp = Mips_spl1;
-		Mips_spltty = Mips_spl2;
-		Mips_splstatclock = Mips_spl3;
-#endif
 		break;
 
 	case DESKSTATION_RPC44:
@@ -263,6 +252,7 @@ mips_init(argc, argv, envv)
 
 			/* Make this more fancy when more comes in here */
 		environment = envv;
+#if 0
 		system_type = ALGOR_P4032;
 		strcpy(cpu_model, "Algorithmics P-4032");
 		arc_bus_io.bus_sparse1 = 2;
@@ -270,9 +260,18 @@ mips_init(argc, argv, envv)
 		arc_bus_io.bus_sparse4 = 0;
 		arc_bus_io.bus_sparse8 = 0;
 		CONADDR = P4032_COM1;
+#else
+		system_type = ALGOR_P5064;
+		strcpy(cpu_model, "Algorithmics P-5064");
+		arc_bus_io.bus_sparse1 = 0;
+		arc_bus_io.bus_sparse2 = 0;
+		arc_bus_io.bus_sparse4 = 0;
+		arc_bus_io.bus_sparse8 = 0;
+		CONADDR = P5064_COM1;
+#endif
 
 		mem_layout[0].mem_start = 0;
-		mem_layout[0].mem_size = mips_trunc_page(CACHED_TO_PHYS(kernel_start));
+		mem_layout[0].mem_size = mips_trunc_page(CACHED_TO_PHYS(kernel_text));
 		mem_layout[1].mem_start = CACHED_TO_PHYS((int)sysend);
 		if(getenv("memsize") != 0) {
 			i = atoi(getenv("memsize"), 10);
@@ -319,9 +318,11 @@ mips_init(argc, argv, envv)
 #else
 	boothowto = RB_SINGLE | RB_ASKNAME;
 #endif /* RAMDISK_HOOKS */
+
 #ifdef KADB
 	boothowto |= RB_KDB;
 #endif
+
 	get_eth_hw_addr(getenv("ethaddr"));
 	cp = getenv("osloadoptions");
 	if(cp) {
@@ -342,6 +343,10 @@ mips_init(argc, argv, envv)
 			case 'N': /* don't ask for names */
 				boothowto &= ~RB_ASKNAME;
 				break;
+
+			case 's': /* use serial console */
+				boothowto |= RB_SERCONS;
+				break;
 			}
 
 		}
@@ -379,6 +384,7 @@ mips_init(argc, argv, envv)
 		break;
 
 	case ALGOR_P4032:
+	case ALGOR_P5064:
 		break;
 
 	case SNI_RM200:
@@ -1280,6 +1286,7 @@ initcpu()
 
 	switch(system_type) {
 	case ACER_PICA_61:
+	case MAGNUM:
 		/*
 		 * Disable all interrupts. New masks will be set up
 		 * during system configuration
diff --git a/sys/arch/arc/arc/pmap.c b/sys/arch/arc/arc/pmap.c
index 139ca419e5d..6c84e9f372e 100644
--- a/sys/arch/arc/arc/pmap.c
+++ b/sys/arch/arc/arc/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.12 1998/03/01 00:37:24 niklas Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.13 1998/03/16 09:38:32 pefo Exp $	*/
 /* 
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -36,7 +36,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)pmap.c	8.4 (Berkeley) 1/26/94
- *      $Id: pmap.c,v 1.12 1998/03/01 00:37:24 niklas Exp $
+ *      $Id: pmap.c,v 1.13 1998/03/16 09:38:32 pefo Exp $
  */
 
 /*
@@ -170,7 +170,7 @@ struct {
 #define PDB_WIRING	0x4000
 #define PDB_PVDUMP	0x8000
 
-extern int kernel_start[];
+extern int kernel_text[];
 extern int _end[];
 int pmapdebug = 0x0;
 
@@ -273,7 +273,7 @@ pmap_bootstrap(firstaddr)
 			mem_layout[i].mem_start = 0x20000;  /* Adjust to be above vec's */
 		}
 		/* Adjust for the kernel expansion area (bufs etc) */
-		if((mem_layout[i].mem_start + mem_layout[i].mem_size > CACHED_TO_PHYS(kernel_start)) && 
+		if((mem_layout[i].mem_start + mem_layout[i].mem_size > CACHED_TO_PHYS(kernel_text)) && 
 		   (mem_layout[i].mem_start < CACHED_TO_PHYS(avail_start))) { 
 			mem_layout[i].mem_size -= CACHED_TO_PHYS(avail_start) - mem_layout[i].mem_start;
 			mem_layout[i].mem_start = CACHED_TO_PHYS(avail_start);
diff --git a/sys/arch/arc/arc/trap.c b/sys/arch/arc/arc/trap.c
index 6c1ff722e71..873b1d0e553 100644
--- a/sys/arch/arc/arc/trap.c
+++ b/sys/arch/arc/arc/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.15 1998/03/01 18:58:30 niklas Exp $	*/
+/*	$OpenBSD: trap.c,v 1.16 1998/03/16 09:38:33 pefo Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -69,6 +69,7 @@
 #include <machine/pte.h>
 #include <machine/pmap.h>
 #include <machine/mips_opcode.h>
+#include <machine/frame.h>
 
 #include <vm/vm.h>
 #include <vm/vm_kern.h>
@@ -77,6 +78,11 @@
 #include <arc/pica/pica.h>
 #include <mips/archtype.h>
 
+#ifdef DDB
+#include <mips/db_machdep.h>
+#include <ddb/db_sym.h>
+#endif
+
 #include <sys/cdefs.h>
 #include <sys/syslog.h>
 
@@ -204,7 +210,7 @@ struct {
 
 int cpu_int_mask;	/* External cpu interrupt mask */
 
-#ifdef MDB
+#ifdef DDB
 #define TRAPSIZE	10
 struct trapdebug {		/* trap history buffer for debugging */
 	u_int	status;
@@ -217,18 +223,18 @@ struct trapdebug {		/* trap history buffer for debugging */
 } trapdebug[TRAPSIZE], *trp = trapdebug;
 
 void trapDump __P((char *));
-#endif	/* MDB */
+#endif	/* DDB */
 
-#ifdef MDB	/* stack trace code, also useful for DDB one day */
-void stacktrace __P((int, int, int, int));
-void logstacktrace __P((int, int, int, int));
+#ifdef DEBUG	/* stack trace code, also useful for DDB one day */
+void stacktrace __P((int *));
+void logstacktrace __P((int *));
+int  kdbpeek __P((int *));
+int  kdb_trap __P((int, db_regs_t *));
 
 /* extern functions printed by name in stack backtraces */
 extern void idle __P((void));
 extern void MipsTLBMiss __P((void));
-extern u_int mdbpeek __P((int));
-extern int mdb __P((u_int, u_int, struct proc *, int));
-#endif	/* MDB */
+#endif	/* DEBUG */
 
 extern const struct callback *callv;
 extern u_long intrcnt[];
@@ -238,7 +244,7 @@ extern void arpintr __P((void));
 extern void ipintr __P((void));
 extern void pppintr __P((void));
 
-u_int trap __P((u_int, u_int, u_int, u_int, u_int));
+u_int trap __P((u_int, u_int, u_int, u_int, struct trap_frame));
 void interrupt __P((u_int, u_int, u_int, u_int, u_int));
 void softintr __P((u_int, u_int));
 int cpu_singlestep __P((struct proc *));
@@ -252,12 +258,12 @@ u_int MipsEmulateBranch __P((int *, int, int, u_int));
  * ((struct pcb *)UADDR)->pcb_onfault is set, otherwise, return old pc.
  */
 u_int
-trap(statusReg, causeReg, vadr, pc, args)
+trap(statusReg, causeReg, vadr, pc, f)
 	u_int statusReg;	/* status register at time of the exception */
 	u_int causeReg;		/* cause register at time of exception */
 	u_int vadr;		/* address (if any) the fault occured on */
 	u_int pc;		/* program counter where to continue */
-	u_int args;
+	struct trap_frame f;
 {
 	int type, i;
 	unsigned ucode = 0;
@@ -268,14 +274,14 @@ trap(statusReg, causeReg, vadr, pc, args)
 	int typ = 0;
 	union sigval sv;
 
-#ifdef MDB
+#ifdef DDB
 	trp->status = statusReg;
 	trp->cause = causeReg;
 	trp->vadr = vadr;
 	trp->pc = pc;
-	trp->ra = !USERMODE(statusReg) ? ((int *)&args)[19] :
+	trp->ra = !USERMODE(statusReg) ? f.reg[PC] :
 		p->p_md.md_regs[RA];
-	trp->sp = (int)&args;
+	trp->sp = (int)&f;
 	trp->code = 0;
 	if (++trp == &trapdebug[TRAPSIZE])
 		trp = trapdebug;
@@ -298,9 +304,9 @@ trap(statusReg, causeReg, vadr, pc, args)
 	case T_TLB_MOD:
 		/* check for kernel address */
 		if ((int)vadr < 0) {
-			register pt_entry_t *pte;
-			register unsigned entry;
-			register vm_offset_t pa;
+			pt_entry_t *pte;
+			unsigned int entry;
+			vm_offset_t pa;
 
 			pte = kvtopte(vadr);
 			entry = pte->pt_entry;
@@ -331,9 +337,9 @@ trap(statusReg, causeReg, vadr, pc, args)
 
 	case T_TLB_MOD+T_USER:
 	    {
-		register pt_entry_t *pte;
-		register unsigned entry;
-		register vm_offset_t pa;
+		pt_entry_t *pte;
+		unsigned int entry;
+		vm_offset_t pa;
 		pmap_t pmap = &p->p_vmspace->vm_pmap;
 
 		if (!(pte = pmap_segmap(pmap, vadr)))
@@ -373,7 +379,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
 		/* check for kernel address */
 		if ((int)vadr < 0) {
-			register vm_offset_t va;
+			vm_offset_t va;
 			int rv;
 
 		kernel_fault:
@@ -406,9 +412,9 @@ trap(statusReg, causeReg, vadr, pc, args)
 		ftype = VM_PROT_WRITE;
 	dofault:
 	    {
-		register vm_offset_t va;
-		register struct vmspace *vm;
-		register vm_map_t map;
+		vm_offset_t va;
+		struct vmspace *vm;
+		vm_map_t map;
 		int rv;
 
 		vm = p->p_vmspace;
@@ -469,8 +475,8 @@ trap(statusReg, causeReg, vadr, pc, args)
 
 	case T_SYSCALL+T_USER:
 	    {
-		register int *locr0 = p->p_md.md_regs;
-		register struct sysent *callp;
+		int *locr0 = p->p_md.md_regs;
+		struct sysent *callp;
 		unsigned int code;
 		int numsys;
 		struct args {
@@ -480,10 +486,12 @@ trap(statusReg, causeReg, vadr, pc, args)
 
 		cnt.v_syscall++;
 		/* compute next PC after syscall instruction */
-		if ((int)causeReg < 0)
+		if ((int)causeReg < 0) {	/* Check BD bit */
 			locr0[PC] = MipsEmulateBranch(locr0, pc, 0, 0);
-		else
+		}
+		else {
 			locr0[PC] += 4;
+		}
 		callp = p->p_emul->e_sysent;
 		numsys = p->p_emul->e_nsysent;
 		code = locr0[V0];
@@ -598,7 +606,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 #endif
 		rval[0] = 0;
 		rval[1] = locr0[V1];
-#ifdef MDB
+#ifdef DDB
 		if (trp == trapdebug)
 			trapdebug[TRAPSIZE - 1].code = code;
 		else
@@ -611,7 +619,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		 */
 		p = curproc;
 		locr0 = p->p_md.md_regs;
-#ifdef MDB
+#ifdef DDB
 		{ int s;
 		s = splhigh();
 		trp->status = statusReg;
@@ -656,9 +664,15 @@ trap(statusReg, causeReg, vadr, pc, args)
 		goto out;
 	    }
 
+#ifdef DDB
+	case T_BREAK:
+		kdb_trap(type, &f);
+		return(f.reg[PC]);
+#endif
+
 	case T_BREAK+T_USER:
 	    {
-		register unsigned va, instr;
+		unsigned int va, instr;
 		struct uio uio;
 		struct iovec iov;
 
@@ -723,7 +737,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		goto out;
 
 	case T_FPE:
-#ifdef MDB
+#ifdef DDB
 		trapDump("fpintr");
 #else
 		printf("FPU Trap: PC %x CR %x SR %x\n",
@@ -751,47 +765,10 @@ trap(statusReg, causeReg, vadr, pc, args)
 
 	default:
 	err:
-#ifdef MDB
-	    {
-		extern struct pcb mdbpcb;
-
-		if (USERMODE(statusReg))
-			mdbpcb = p->p_addr->u_pcb;
-		else {
-			mdbpcb.pcb_regs[ZERO] = 0;
-			mdbpcb.pcb_regs[AST] = ((int *)&args)[2];
-			mdbpcb.pcb_regs[V0] = ((int *)&args)[3];
-			mdbpcb.pcb_regs[V1] = ((int *)&args)[4];
-			mdbpcb.pcb_regs[A0] = ((int *)&args)[5];
-			mdbpcb.pcb_regs[A1] = ((int *)&args)[6];
-			mdbpcb.pcb_regs[A2] = ((int *)&args)[7];
-			mdbpcb.pcb_regs[A3] = ((int *)&args)[8];
-			mdbpcb.pcb_regs[T0] = ((int *)&args)[9];
-			mdbpcb.pcb_regs[T1] = ((int *)&args)[10];
-			mdbpcb.pcb_regs[T2] = ((int *)&args)[11];
-			mdbpcb.pcb_regs[T3] = ((int *)&args)[12];
-			mdbpcb.pcb_regs[T4] = ((int *)&args)[13];
-			mdbpcb.pcb_regs[T5] = ((int *)&args)[14];
-			mdbpcb.pcb_regs[T6] = ((int *)&args)[15];
-			mdbpcb.pcb_regs[T7] = ((int *)&args)[16];
-			mdbpcb.pcb_regs[T8] = ((int *)&args)[17];
-			mdbpcb.pcb_regs[T9] = ((int *)&args)[18];
-			mdbpcb.pcb_regs[RA] = ((int *)&args)[19];
-			mdbpcb.pcb_regs[MULLO] = ((int *)&args)[21];
-			mdbpcb.pcb_regs[MULHI] = ((int *)&args)[22];
-			mdbpcb.pcb_regs[PC] = pc;
-			mdbpcb.pcb_regs[SR] = statusReg;
-			bzero((caddr_t)&mdbpcb.pcb_regs[F0], 33 * sizeof(int));
-		}
-		if (mdb(causeReg, vadr, p, !USERMODE(statusReg)))
-			return (mdbpcb.pcb_regs[PC]);
-	    }
-#else
-#ifdef MDB
-		stacktrace();
+#ifdef DEBUG
+		stacktrace(!USERMODE(statusReg) ? f.reg : p->p_md.md_regs);
 		trapDump("trap");
 #endif
-#endif
 		panic("trap");
 	}
 	p->p_md.md_regs[PC] = pc;
@@ -847,19 +824,19 @@ out:
  * Note: curproc might be NULL.
  */
 void
-interrupt(statusReg, causeReg, pc, what, args)
+interrupt(statusReg, causeReg, what, pc, args)
 	u_int statusReg;	/* status register at time of the exception */
 	u_int causeReg;		/* cause register at time of exception */
-	u_int pc;		/* program counter where to continue */
 	u_int what;
+	u_int pc;		/* program counter where to continue */
 	u_int args;
 {
-	register unsigned mask;
-	register int i;
+	unsigned mask;
+	int i;
 	struct clockframe cf;
 
 	cnt.v_trap++;
-#ifdef MDB
+#ifdef DDB
 	trp->status = statusReg;
 	trp->cause = causeReg;
 	trp->vadr = 0;
@@ -881,7 +858,7 @@ interrupt(statusReg, causeReg, pc, what, args)
 	 *  Check off all enabled interrupts. Called interrupt routine
 	 *  returns mask of interrupts to reenable.
 	 */
-	for(i = 0; i < 5; i++) {
+	for(i = 0; i < 8; i++) {
 		if(cpu_int_tab[i].int_mask & mask) {
 			causeReg &= (*cpu_int_tab[i].int_hand)(mask, &cf);
 		}
@@ -958,13 +935,14 @@ set_intr(mask, int_hand, prio)
 	int	(*int_hand)(u_int, struct clockframe *);
 	int	prio;
 {
-	if(prio > 5)
+	if(prio >= 8)
 		panic("set_intr: to high priority");
 
 	if(cpu_int_tab[prio].int_mask != 0 &&
 	   (cpu_int_tab[prio].int_mask != mask ||
-	    cpu_int_tab[prio].int_hand != int_hand))
-		panic("set_intr: int already set");
+	    cpu_int_tab[prio].int_hand != int_hand)) {
+		panic("set_intr: int already set %x", prio);
+	}
 
 	cpu_int_tab[prio].int_hand = int_hand;
 	cpu_int_tab[prio].int_mask = mask;
@@ -984,6 +962,7 @@ set_intr(mask, int_hand, prio)
 	case DESKSTATION_RPC44:
 		break;
 	case ALGOR_P4032:
+	case ALGOR_P5064:
 		break;
 	}
 }
@@ -997,7 +976,7 @@ softintr(statusReg, pc)
 	unsigned statusReg;	/* status register at time of the exception */
 	unsigned pc;		/* program counter where to continue */
 {
-	register struct proc *p = curproc;
+	struct proc *p = curproc;
 	int sig;
 
 	cnt.v_soft++;
@@ -1032,12 +1011,12 @@ softintr(statusReg, pc)
 	curpriority = p->p_priority;
 }
 
-#ifdef MDB
+#ifdef DDB
 void
 trapDump(msg)
 	char *msg;
 {
-	register int i;
+	int i;
 	int s;
 
 	s = splhigh();
@@ -1234,10 +1213,10 @@ MipsEmulateBranch(regsPtr, instPC, fpcCSR, instptr)
  */
 int
 cpu_singlestep(p)
-	register struct proc *p;
+	struct proc *p;
 {
-	register unsigned va;
-	register int *locr0 = p->p_md.md_regs;
+	unsigned va;
+	int *locr0 = p->p_md.md_regs;
 	int i;
 	int bpinstr = BREAK_SSTEP;
 	int curinstr;
@@ -1310,55 +1289,55 @@ cpu_singlestep(p)
 	return (0);
 }
 
-#ifdef MDB
+#ifdef DDB
 #define MIPS_JR_RA	0x03e00008	/* instruction code for jr ra */
 
 /* forward */
 char *fn_name(unsigned addr);
-void stacktrace_subr __P((int, int, int, int, int (*)(const char*, ...)));
+void stacktrace_subr __P((int *, int (*)(const char*, ...)));
 
 /*
  * Print a stack backtrace.
  */
 void
-stacktrace(a0, a1, a2, a3)
-	int a0, a1, a2, a3;
+stacktrace(regs)
+	int *regs;
 {
-	stacktrace_subr(a0, a1, a2, a3, printf);
+	stacktrace_subr(regs, printf);
 }
 
 void
-logstacktrace(a0, a1, a2, a3)
-	int a0, a1, a2, a3;
+logstacktrace(regs)
+	int *regs;
 {
-	stacktrace_subr(a0, a1, a2, a3, addlog);
+	stacktrace_subr(regs, addlog);
 }
 
 void
-stacktrace_subr(a0, a1, a2, a3, printfn)
-	int a0, a1, a2, a3;
+stacktrace_subr(regs, printfn)
+	int *regs;
 	int (*printfn) __P((const char*, ...));
 {
 	unsigned pc, sp, fp, ra, va, subr;
+	unsigned a0, a1, a2, a3;
 	unsigned instr, mask;
 	InstFmt i;
 	int more, stksize;
-	int regs[3];
 	extern char edata[];
-	extern void cpu_getregs __P((int *));
 	unsigned int frames =  0;
 
-	cpu_getregs(regs);
-
 	/* get initial values from the exception frame */
-	sp = regs[0];
-	pc = regs[1];
-	ra = 0;
-	fp = regs[2];
+	sp = regs[SP];
+	pc = regs[PC];
+	fp = regs[S8];
+	ra = regs[RA];		/* May be a 'leaf' function */
+	a0 = regs[A0];
+	a1 = regs[A1];
+	a2 = regs[A2];
+	a3 = regs[A3];
 
 /* Jump here when done with a frame, to start a new one */
 loop:
-	ra = 0;
 
 /* Jump here after a nonstandard (interrupt handler) frame */
 specialframe:
@@ -1380,17 +1359,17 @@ specialframe:
 
 	/* Backtraces should contine through interrupts from kernel mode */
 	if (pc >= (unsigned)MipsKernIntr && pc < (unsigned)MipsUserIntr) {
-		/* NOTE: the offsets depend on the code in locore.s */
 		(*printfn)("MipsKernIntr+%x: (%x, %x ,%x) -------\n",
 		       pc-(unsigned)MipsKernIntr, a0, a1, a2);
-		a0 = mdbpeek(sp + 36);
-		a1 = mdbpeek(sp + 40);
-		a2 = mdbpeek(sp + 44);
-		a3 = mdbpeek(sp + 48);
-
-		pc = mdbpeek(sp + 20);	/* exc_pc - pc at time of exception */
-		ra = mdbpeek(sp + 92);	/* ra at time of exception */
-		sp = sp + 108;
+		regs = (int *)(sp + STAND_ARG_SIZE);
+		a0 = kdbpeek(&regs[A0]);
+		a1 = kdbpeek(&regs[A1]);
+		a2 = kdbpeek(&regs[A2]);
+		a3 = kdbpeek(&regs[A3]);
+
+		pc = kdbpeek(&regs[PC]); /* exc_pc - pc at time of exception */
+		ra = kdbpeek(&regs[RA]); /* ra at time of exception */
+		sp = kdbpeek(&regs[SP]);
 		goto specialframe;
 	}
 
@@ -1440,17 +1419,17 @@ specialframe:
 	 */
 	if (!subr) {
 		va = pc - sizeof(int);
-		while ((instr = mdbpeek(va)) != MIPS_JR_RA)
+		while ((instr = kdbpeek((int *)va)) != MIPS_JR_RA)
 		va -= sizeof(int);
 		va += 2 * sizeof(int);	/* skip back over branch & delay slot */
 		/* skip over nulls which might separate .o files */
-		while ((instr = mdbpeek(va)) == 0)
+		while ((instr = kdbpeek((int *)va)) == 0)
 			va += sizeof(int);
 		subr = va;
 	}
 
 	/*
-	 * Jump here for locore entry pointsn for which the preceding
+	 * Jump here for locore entry points for which the preceding
 	 * function doesn't end in "j ra"
 	 */
 	/* scan forwards to find stack size and any saved registers */
@@ -1462,7 +1441,7 @@ specialframe:
 		/* stop if hit our current position */
 		if (va >= pc)
 			break;
-		instr = mdbpeek(va);
+		instr = kdbpeek((int *)va);
 		i.word = instr;
 		switch (i.JType.op) {
 		case OP_SPECIAL:
@@ -1509,27 +1488,27 @@ specialframe:
 			mask |= (1 << i.IType.rt);
 			switch (i.IType.rt) {
 			case 4: /* a0 */
-				a0 = mdbpeek(sp + (short)i.IType.imm);
+				a0 = kdbpeek((int *)(sp + (short)i.IType.imm));
 				break;
 
 			case 5: /* a1 */
-				a1 = mdbpeek(sp + (short)i.IType.imm);
+				a1 = kdbpeek((int *)(sp + (short)i.IType.imm));
 				break;
 
 			case 6: /* a2 */
-				a2 = mdbpeek(sp + (short)i.IType.imm);
+				a2 = kdbpeek((int *)(sp + (short)i.IType.imm));
 				break;
 
 			case 7: /* a3 */
-				a3 = mdbpeek(sp + (short)i.IType.imm);
+				a3 = kdbpeek((int *)(sp + (short)i.IType.imm));
 				break;
 
 			case 30: /* fp */
-				fp = mdbpeek(sp + (short)i.IType.imm);
+				fp = kdbpeek((int *)(sp + (short)i.IType.imm));
 				break;
 
 			case 31: /* ra */
-				ra = mdbpeek(sp + (short)i.IType.imm);
+				ra = kdbpeek((int *)(sp + (short)i.IType.imm));
 			}
 			break;
 
@@ -1601,4 +1580,4 @@ fn_name(unsigned addr)
 	return (buf);
 }
 
-#endif /* MDB */
+#endif /* DDB */
diff --git a/sys/arch/arc/arc/vm_machdep.c b/sys/arch/arc/arc/vm_machdep.c
deleted file mode 100644
index b3db107794a..00000000000
--- a/sys/arch/arc/arc/vm_machdep.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*	$OpenBSD: vm_machdep.c,v 1.8 1998/03/01 00:37:25 niklas Exp $	*/
-/*
- * Copyright (c) 1988 University of Utah.
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * the Systems Programming Group of the University of Utah Computer
- * Science Department and Ralph Campbell.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * from: Utah Hdr: vm_machdep.c 1.21 91/04/06
- *
- *	from: @(#)vm_machdep.c	8.3 (Berkeley) 1/4/94
- *      $Id: vm_machdep.c,v 1.8 1998/03/01 00:37:25 niklas Exp $
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/proc.h>
-#include <sys/malloc.h>
-#include <sys/buf.h>
-#include <sys/vnode.h>
-#include <sys/user.h>
-#include <sys/core.h>
-#include <sys/exec.h>
-
-#include <vm/vm.h>
-#include <vm/vm_kern.h>
-#include <vm/vm_page.h>
-
-#include <machine/pte.h>
-#include <machine/cpu.h>
-
-vm_offset_t kmem_alloc_wait_align __P((vm_map_t, vm_size_t, vm_size_t));
-static int vm_map_findspace_align __P((vm_map_t map, vm_offset_t, vm_size_t,
-					vm_offset_t *, vm_size_t));
-int vm_map_find_U __P((vm_map_t, vm_object_t, vm_offset_t, vm_offset_t *,
-			vm_size_t, boolean_t));
-
-/*
- * Finish a fork operation, with process p2 nearly set up.
- * Copy and update the kernel stack and pcb, making the child
- * ready to run, and marking it so that it can return differently
- * than the parent.  Returns 1 in the child process, 0 in the parent.
- * We currently double-map the user area so that the stack is at the same
- * address in each process; in the future we will probably relocate
- * the frame pointers on the stack after copying.
- */
-int
-cpu_fork(p1, p2)
-	register struct proc *p1, *p2;
-{
-	struct user *up = p2->p_addr;
-	pt_entry_t *pte;
-	int i;
-	extern struct proc *machFPCurProcPtr;
-
-	p2->p_md.md_regs = up->u_pcb.pcb_regs;
-	p2->p_md.md_flags = p1->p_md.md_flags & MDP_FPUSED;
-
-	/*
-	 * Cache the PTEs for the user area in the machine dependent
-	 * part of the proc struct so cpu_switch() can quickly map in
-	 * the user struct and kernel stack. Note: if the virtual address
-	 * translation changes (e.g. swapout) we have to update this.
-	 */
-	pte = kvtopte(up);
-	for (i = 0; i < UPAGES; i++) {
-		p2->p_md.md_upte[i] = pte->pt_entry & ~(PG_G | PG_RO | PG_WIRED);
-		pte++;
-	}
-
-	/*
-	 * Copy floating point state from the FP chip if this process
-	 * has state stored there.
-	 */
-	if (p1 == machFPCurProcPtr)
-		MipsSaveCurFPState(p1);
-
-	/*
-	 * Copy pcb and stack from proc p1 to p2. 
-	 * We do this as cheaply as possible, copying only the active
-	 * part of the stack.  The stack and pcb need to agree;
-	 */
-	p2->p_addr->u_pcb = p1->p_addr->u_pcb;
-	/* cache segtab for ULTBMiss() */
-	p2->p_addr->u_pcb.pcb_segtab = (void *)p2->p_vmspace->vm_pmap.pm_segtab;
-
-	/*
-	 * Arrange for a non-local goto when the new process
-	 * is started, to resume here, returning nonzero from setjmp.
-	 */
-#ifdef DIAGNOSTIC
-	if (p1 != curproc)
-		panic("cpu_fork: curproc");
-#endif
-	if (copykstack(up)) {
-		/*
-		 * Return 1 in child.
-		 */
-		return (1);
-	}
-	return (0);
-}
-
-/*
- * Finish a swapin operation.
- * We neded to update the cached PTEs for the user area in the
- * machine dependent part of the proc structure.
- */
-void
-cpu_swapin(p)
-	register struct proc *p;
-{
-	register struct user *up = p->p_addr;
-	register pt_entry_t *pte;
-	register int i;
-
-	/*
-	 * Cache the PTEs for the user area in the machine dependent
-	 * part of the proc struct so cpu_switch() can quickly map in
-	 * the user struct and kernel stack.
-	 */
-	pte = kvtopte(up);
-	for (i = 0; i < UPAGES; i++) {
-		p->p_md.md_upte[i] = pte->pt_entry & ~(PG_G | PG_RO | PG_WIRED);
-		pte++;
-	}
-}
-
-/*
- * cpu_exit is called as the last action during exit.
- * We release the address space and machine-dependent resources,
- * including the memory for the user structure and kernel stack.
- * Once finished, we call switch_exit, which switches to a temporary
- * pcb and stack and never returns.  We block memory allocation
- * until switch_exit has made things safe again.
- */
-void
-cpu_exit(p)
-	struct proc *p;
-{
-	extern struct proc *machFPCurProcPtr;
-
-	if (machFPCurProcPtr == p)
-		machFPCurProcPtr = (struct proc *)0;
-
-	vmspace_free(p->p_vmspace);
-
-	(void) splhigh();
-	kmem_free(kernel_map, (vm_offset_t)p->p_addr, ctob(UPAGES));
-	switch_exit();
-	/* NOTREACHED */
-}
-
-/*
- * Dump the machine specific header information at the start of a core dump.
- */
-int
-cpu_coredump(p, vp, cred, chdr)
-	struct proc *p;
-	struct vnode *vp;
-	struct ucred *cred;
-	struct core *chdr;
-{
-	int error;
-	/*register struct user *up = p->p_addr;*/
-	struct coreseg cseg;
-	extern struct proc *machFPCurProcPtr;
-
-	CORE_SETMAGIC(*chdr, COREMAGIC, MID_MIPS, 0);
-	chdr->c_hdrsize = ALIGN(sizeof(*chdr));
-	chdr->c_seghdrsize = ALIGN(sizeof(cseg));
-	chdr->c_cpusize = sizeof (p -> p_addr -> u_pcb.pcb_regs);
-
-	/*
-	 * Copy floating point state from the FP chip if this process
-	 * has state stored there.
-	 */
-	if (p == machFPCurProcPtr)
-		MipsSaveCurFPState(p);
-
-	CORE_SETMAGIC(cseg, CORESEGMAGIC, MID_MIPS, CORE_CPU);
-	cseg.c_addr = 0;
-	cseg.c_size = chdr->c_cpusize;
-
-	error = vn_rdwr(UIO_WRITE, vp, (caddr_t)&cseg, chdr->c_seghdrsize,
-	    (off_t)chdr->c_hdrsize, UIO_SYSSPACE,
-	    IO_NODELOCKED|IO_UNIT, cred, (int *)NULL, p);
-	if (error)
-		return error;
-
-	error = vn_rdwr(UIO_WRITE, vp,
-			(caddr_t)(&(p -> p_addr -> u_pcb.pcb_regs)),
-			(off_t)chdr -> c_cpusize,
-	    		(off_t)(chdr->c_hdrsize + chdr->c_seghdrsize),
-			UIO_SYSSPACE, IO_NODELOCKED|IO_UNIT,
-			cred, (int *)NULL, p);
-
-	if (!error)
-		chdr->c_nseg++;
-
-	return error;
-}
-
-/*
- * Move pages from one kernel virtual address to another.
- * Both addresses are assumed to reside in the Sysmap,
- * and size must be a multiple of CLSIZE.
- */
-void
-pagemove(from, to, size)
-	caddr_t from, to;
-	size_t size;
-{
-	pt_entry_t *fpte, *tpte;
-
-	if (size % CLBYTES)
-		panic("pagemove");
-	fpte = kvtopte(from);
-	tpte = kvtopte(to);
-	if(((int)from & CpuCacheAliasMask) != ((int)to & CpuCacheAliasMask)) {
-		R4K_HitFlushDCache((vm_offset_t)from, size);
-	}
-	while (size > 0) {
-		R4K_TLBFlushAddr((vm_offset_t)from);
-		R4K_TLBUpdate((vm_offset_t)to, fpte->pt_entry);
-		*tpte++ = *fpte;
-		fpte->pt_entry = PG_NV | PG_G;
-		fpte++;
-		size -= NBPG;
-		from += NBPG;
-		to += NBPG;
-	}
-}
-
-extern vm_map_t phys_map;
-
-/*
- * Map an IO request into kernel virtual address space.  Requests fall into
- * one of five catagories:
- *
- *	B_PHYS|B_UAREA:	User u-area swap.
- *			Address is relative to start of u-area (p_addr).
- *	B_PHYS|B_PAGET:	User page table swap.
- *			Address is a kernel VA in usrpt (Usrptmap).
- *	B_PHYS|B_DIRTY:	Dirty page push.
- *			Address is a VA in proc2's address space.
- *	B_PHYS|B_PGIN:	Kernel pagein of user pages.
- *			Address is VA in user's address space.
- *	B_PHYS:		User "raw" IO request.
- *			Address is VA in user's address space.
- *
- * All requests are (re)mapped into kernel VA space via the phys_map
- */
-void
-vmapbuf(bp, len)
-	struct buf *bp;
-	vm_size_t len;
-{
-	register caddr_t addr;
-	register vm_size_t sz;
-	struct proc *p;
-	int off;
-	vm_offset_t kva;
-	register vm_offset_t pa;
-
-	if ((bp->b_flags & B_PHYS) == 0)
-		panic("vmapbuf");
-	addr = bp->b_saveaddr = bp->b_un.b_addr;
-	off = (int)addr & PGOFSET;
-	p = bp->b_proc;
-	sz = round_page(off + len);
-	kva = kmem_alloc_wait_align(phys_map, sz, (vm_size_t)addr & CpuCacheAliasMask);
-	bp->b_un.b_addr = (caddr_t) (kva + off);
-	sz = atop(sz);
-	while (sz--) {
-		pa = pmap_extract(vm_map_pmap(&p->p_vmspace->vm_map),
-			(vm_offset_t)addr);
-		if (pa == 0)
-			panic("vmapbuf: null page frame");
-		pmap_enter(vm_map_pmap(phys_map), kva, trunc_page(pa),
-			VM_PROT_READ|VM_PROT_WRITE, TRUE);
-		addr += PAGE_SIZE;
-		kva += PAGE_SIZE;
-	}
-}
-
-/*
- * Free the io map PTEs associated with this IO operation.
- * We also invalidate the TLB entries and restore the original b_addr.
- */
-void
-vunmapbuf(bp, len)
-	struct buf *bp;
-	vm_size_t len;
-{
-	register caddr_t addr = bp->b_un.b_addr;
-	register vm_size_t sz;
-	vm_offset_t kva;
-
-	if ((bp->b_flags & B_PHYS) == 0)
-		panic("vunmapbuf");
-	sz = round_page(len + ((int)addr & PGOFSET));
-	kva = (vm_offset_t)((int)addr & ~PGOFSET);
-	kmem_free_wakeup(phys_map, kva, sz);
-	bp->b_un.b_addr = bp->b_saveaddr;
-	bp->b_saveaddr = NULL;
-}
-
-
-/*
- *	SAVE_HINT:
- *
- *	Saves the specified entry as the hint for
- *	future lookups.  Performs necessary interlocks.
- */
-#define	SAVE_HINT(map,value) \
-		simple_lock(&(map)->hint_lock); \
-		(map)->hint = (value); \
-		simple_unlock(&(map)->hint_lock);
-
-
-/*
- *	kmem_alloc_upage:
- *
- *	Allocate pageable memory to the kernel's address map.
- *	map must be "kernel_map" below.
- *	(Currently only used when allocating U pages).
- */
-vm_offset_t
-kmem_alloc_upage(map, size)
-	vm_map_t		map;
-	register vm_size_t	size;
-{
-	vm_offset_t		addr;
-	register int		result;
-
-
-	size = round_page(size);
-
-	addr = vm_map_min(map);
-	result = vm_map_find_U(map, NULL, (vm_offset_t) 0,
-				&addr, size, TRUE);
-	if (result != KERN_SUCCESS) {
-		return(0);
-	}
-
-	return(addr);
-}
-
-/*
- *	vm_map_find finds an unallocated region in the target address
- *	map with the given length aligned on U virtual address.
- *	The search is defined to be first-fit from the specified address;
- *	the region found is returned in the same parameter.
- *
- */
-int
-vm_map_find_U(map, object, offset, addr, length, find_space)
-	vm_map_t	map;
-	vm_object_t	object;
-	vm_offset_t	offset;
-	vm_offset_t	*addr;		/* IN/OUT */
-	vm_size_t	length;
-	boolean_t	find_space;
-{
-	register vm_offset_t	start;
-	int			result;
-
-	start = *addr;
-	vm_map_lock(map);
-	if (find_space) {
-		if (vm_map_findspace_align(map, start, length, addr, 0)) {
-			vm_map_unlock(map);
-			return (KERN_NO_SPACE);
-		}
-		start = *addr;
-	}
-	result = vm_map_insert(map, object, offset, start, start + length);
-	vm_map_unlock(map);
-	return (result);
-}
-
-/*
- * Find sufficient space for `length' bytes in the given map, starting at
- * `start'.  The map must be locked.  Returns 0 on success, 1 on no space.
- */
-static int
-vm_map_findspace_align(map, start, length, addr, align)
-	vm_map_t map;
-	vm_offset_t start;
-	vm_size_t length;
-	vm_offset_t *addr;
-	vm_size_t align;
-{
-	register vm_map_entry_t entry, next;
-	register vm_offset_t end;
-
-	if (start < map->min_offset)
-		start = map->min_offset;
-	if (start > map->max_offset)
-		return (1);
-
-	/*
-	 * Look for the first possible address; if there's already
-	 * something at this address, we have to start after it.
-	 */
-	if (start == map->min_offset) {
-		if ((entry = map->first_free) != &map->header)
-			start = entry->end;
-	} else {
-		vm_map_entry_t tmp;
-		if (vm_map_lookup_entry(map, start, &tmp))
-			start = tmp->end;
-		entry = tmp;
-	}
-
-	/*
-	 * Look through the rest of the map, trying to fit a new region in
-	 * the gap between existing regions, or after the very last region.
-	 */
-	for (;; start = (entry = next)->end) {
-		/*
-		 * Find the end of the proposed new region.  Be sure we didn't
-		 * go beyond the end of the map, or wrap around the address;
-		 * if so, we lose.  Otherwise, if this is the last entry, or
-		 * if the proposed new region fits before the next entry, we
-		 * win.
-		 */
-		start = ((start + NBPG -1) & ~(NBPG - 1)); /* Paranoia */
-		if((start & CpuCacheAliasMask) <= align) {
-			start += align - (start & CpuCacheAliasMask);
-		}
-		else {
-			start = ((start + CpuCacheAliasMask) & ~CpuCacheAliasMask);
-			start += align;
-		}
-			
-		end = start + length;
-		if (end > map->max_offset || end < start)
-			return (1);
-		next = entry->next;
-		if (next == &map->header || next->start >= end)
-			break;
-	}
-	SAVE_HINT(map, entry);
-	*addr = start;
-	return (0);
-}
-
-/*
- *	kmem_alloc_wait_align
- *
- *	Allocates pageable memory from a sub-map of the kernel.  If the submap
- *	has no room, the caller sleeps waiting for more memory in the submap.
- *
- */
-vm_offset_t
-kmem_alloc_wait_align(map, size, align)
-	vm_map_t	map;
-	vm_size_t	size;
-	vm_size_t	align;
-{
-	vm_offset_t	addr;
-
-	size = round_page(size);
-
-	for (;;) {
-		/*
-		 * To make this work for more than one map,
-		 * use the map's lock to lock out sleepers/wakers.
-		 */
-		vm_map_lock(map);
-		if (vm_map_findspace_align(map, 0, size, &addr, align) == 0)
-			break;
-		/* no space now; see if we can ever get space */
-		if (vm_map_max(map) - vm_map_min(map) < size) {
-			vm_map_unlock(map);
-			return (0);
-		}
-		assert_wait(map, TRUE);
-		vm_map_unlock(map);
-		thread_block("kmawa");
-	}
-	vm_map_insert(map, NULL, (vm_offset_t)0, addr, addr + size);
-	vm_map_unlock(map);
-	return (addr);
-}
diff --git a/sys/arch/arc/conf/P4032 b/sys/arch/arc/conf/P4032
index 6640bb9e306..3fdfee97de5 100644
--- a/sys/arch/arc/conf/P4032
+++ b/sys/arch/arc/conf/P4032
@@ -1,9 +1,9 @@
-#	$OpenBSD: P4032,v 1.4 1997/08/01 11:31:22 deraadt Exp $
+#	$OpenBSD: P4032,v 1.5 1998/03/16 09:38:36 pefo Exp $
 #
 #	Generic configuration file for Algorithmics P4032 board
 #
 
-machine		arc
+machine		arc mips
 
 maxusers	32
 
@@ -20,6 +20,8 @@ option		KTRACE			# system call tracing support
 option		DEBUG			# extra kernel debugging support
 option		COMPAT_43		# compatibility with 4.3BSD binaries
 
+option		DDB
+
 # System V options
 option		SYSVMSG		# System V-like message queues
 option		SYSVSEM		# System V-like semaphores
@@ -33,7 +35,6 @@ option		FDESC		# user file descriptor filesystem (/dev/fd)
 option		FIFO		# POSIX fifo support (in all filesystems)
 option		FFS,QUOTA	# fast filesystem with user and group quotas
 option		KERNFS		# kernel data-structure filesystem
-#option		LFS		# Log-based filesystem (still experimental)
 option		MFS		# memory-based filesystem
 option		MSDOSFS		# Ability to read write MS-Dos filsystem
 option		NFSCLIENT	# Sun NFS-compatible filesystem (client)
diff --git a/sys/arch/arc/conf/files.arc b/sys/arch/arc/conf/files.arc
index d215e6bc1f2..44de6aca062 100644
--- a/sys/arch/arc/conf/files.arc
+++ b/sys/arch/arc/conf/files.arc
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.arc,v 1.17 1998/01/28 13:46:03 pefo Exp $
+#	$OpenBSD: files.arc,v 1.18 1998/03/16 09:38:38 pefo Exp $
 #
 # maxpartitions must be first item in files.${ARCH}
 #
@@ -14,7 +14,6 @@ file	arch/arc/dev/dma.c
 file	arch/arc/arc/machdep.c
 file	arch/arc/arc/pmap.c
 file	arch/arc/arc/trap.c
-file	arch/arc/arc/vm_machdep.c
 
 file	arch/mips/mips/arcbios.c
 
diff --git a/sys/arch/arc/dev/asc.c b/sys/arch/arc/dev/asc.c
index 961cdabe6d5..1e9105c569e 100644
--- a/sys/arch/arc/dev/asc.c
+++ b/sys/arch/arc/dev/asc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asc.c,v 1.8 1998/01/29 14:54:50 pefo Exp $	*/
+/*	$OpenBSD: asc.c,v 1.9 1998/03/16 09:38:39 pefo Exp $	*/
 /*	$NetBSD: asc.c,v 1.10 1994/12/05 19:11:12 dean Exp $	*/
 
 /*-
@@ -535,6 +535,7 @@ ascattach(parent, self, aux)
 	 */
 	switch (system_type) {
 	case ACER_PICA_61:
+	case MAGNUM:
 		bufsiz = 63 * 1024; /*XXX check if code handles 0 as 64k */
 		asc->dma = &asc->__dma;
 		asc_dma_init(asc->dma);
@@ -547,6 +548,7 @@ ascattach(parent, self, aux)
 	 */
 	switch (system_type) {
 	case ACER_PICA_61:
+	case MAGNUM:
 		asc->min_period = ASC_MIN_PERIOD25;
 		asc->max_period = ASC_MAX_PERIOD25;
 		asc->ccf = ASC_CCF(25);
diff --git a/sys/arch/arc/dev/com_lbus.c b/sys/arch/arc/dev/com_lbus.c
index 0b6109075b6..c88bce3df0c 100644
--- a/sys/arch/arc/dev/com_lbus.c
+++ b/sys/arch/arc/dev/com_lbus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: com_lbus.c,v 1.6 1998/03/01 16:19:13 niklas Exp $	*/
+/*	$OpenBSD: com_lbus.c,v 1.7 1998/03/16 09:38:41 pefo Exp $	*/
 
 /*
  * Copyright (c) 1993, 1994 Charles Hannum.
@@ -141,6 +141,7 @@ com_localbus_attach(parent, self, aux)
 
 
 	/* look for a NS 16550AF UART with FIFOs */
+	sc->sc_fifolen = 1;
 	bus_space_write_1(iot, ioh, com_fifo,
 	    FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
 	delay(100);
@@ -150,10 +151,15 @@ com_localbus_attach(parent, self, aux)
 		    FIFO_TRIGGER_14) == FIFO_TRIGGER_14) {
 			SET(sc->sc_hwflags, COM_HW_FIFO);
 			printf(": ns16550a, working fifo\n");
-		} else
+			sc->sc_fifolen = 16;
+		}
+		else {
 			printf(": ns16550, broken fifo\n");
-	} else
+		}
+	}
+	else {
 		printf(": ns8250 or ns16450, no fifo\n");
+	}
 	bus_space_write_1(iot, ioh, com_fifo, 0);
 
 	/* disable interrupts */
diff --git a/sys/arch/arc/dev/pccons.c b/sys/arch/arc/dev/pccons.c
index 63c7f3caae1..7e4b07dd537 100644
--- a/sys/arch/arc/dev/pccons.c
+++ b/sys/arch/arc/dev/pccons.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pccons.c,v 1.18 1998/03/01 16:45:50 niklas Exp $	*/
+/*	$OpenBSD: pccons.c,v 1.19 1998/03/16 09:38:43 pefo Exp $	*/
 /*	$NetBSD: pccons.c,v 1.89 1995/05/04 19:35:20 cgd Exp $	*/
 
 /*-
@@ -493,6 +493,9 @@ pcprobe(parent, cfdata, aux)
 			return(0);
 	}
 
+	if(system_type == MAGNUM)
+		return(0);	/* Magnums have different graphics */
+
 	/* Enable interrupts and keyboard, etc. */
 	if (!kbc_put8042cmd(CMDBYTE)) {
 		printf("pcprobe: command error\n");
@@ -856,7 +859,9 @@ pccnprobe(cp)
 
 	/* initialize required fields */
 	cp->cn_dev = makedev(maj, 0);
-	if(system_type == ALGOR_P4032) {
+	if(system_type == ALGOR_P4032 ||
+	   system_type == ALGOR_P5064 ||
+	   system_type == MAGNUM) {
 		cp->cn_pri = CN_DEAD;	/* XXX For now... */
 	}
 	else {
diff --git a/sys/arch/arc/include/db_machdep.h b/sys/arch/arc/include/db_machdep.h
new file mode 100644
index 00000000000..866b7342083
--- /dev/null
+++ b/sys/arch/arc/include/db_machdep.h
@@ -0,0 +1,5 @@
+/*	$OpenBSD: db_machdep.h,v 1.1 1998/03/16 09:38:44 pefo Exp $ */
+
+/* Use Mips generic include file */
+
+#include <mips/db_machdep.h>
diff --git a/sys/arch/arc/include/frame.h b/sys/arch/arc/include/frame.h
index e69de29bb2d..58760d190dd 100644
--- a/sys/arch/arc/include/frame.h
+++ b/sys/arch/arc/include/frame.h
@@ -0,0 +1,5 @@
+/*	$OpenBSD: frame.h,v 1.2 1998/03/16 09:38:45 pefo Exp $ */
+
+/* Use Mips generic include file */
+
+#include <mips/frame.h>
diff --git a/sys/arch/arc/isa/isabus.c b/sys/arch/arc/isa/isabus.c
index fbc8ea90884..8486aa5ef58 100644
--- a/sys/arch/arc/isa/isabus.c
+++ b/sys/arch/arc/isa/isabus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: isabus.c,v 1.14 1998/03/01 16:50:30 niklas Exp $	*/
+/*	$OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $	*/
 /*	$NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp $	*/
 
 /*-
@@ -174,6 +174,7 @@ isabrattach(parent, self, aux)
 	/* set up interrupt handlers */
 	switch(system_type) {
 	case ACER_PICA_61:
+	case MAGNUM:
 		set_intr(INT_MASK_2, isabr_iointr, 3);
 		break;
 	case DESKSTATION_TYNE:
@@ -391,6 +392,7 @@ isabr_iointr(mask, cf)
 
 	switch(system_type) {
 	case ACER_PICA_61:
+	case MAGNUM:
 		isa_vector = in32(R4030_SYS_ISA_VECTOR) & (ICU_LEN - 1);
 		break;
 
diff --git a/sys/arch/arc/pci/pbcpcibus.c b/sys/arch/arc/pci/pbcpcibus.c
index d3055a1dae2..d084dc427bc 100644
--- a/sys/arch/arc/pci/pbcpcibus.c
+++ b/sys/arch/arc/pci/pbcpcibus.c
@@ -1,7 +1,7 @@
-/*	$OpenBSD: pbcpcibus.c,v 1.5 1998/01/29 14:54:55 pefo Exp $ */
+/*	$OpenBSD: pbcpcibus.c,v 1.6 1998/03/16 09:38:48 pefo Exp $ */
 
 /*
- * Copyright (c) 1997 Per Fogelstrom
+ * Copyright (c) 1997, 1998 Per Fogelstrom, Opsycon AB
  * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -14,7 +14,7 @@
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed under OpenBSD by
- *	Per Fogelstrom.
+ *	Per Fogelstrom, Opsycon AB.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
@@ -51,7 +51,7 @@
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 
-#include <arc/arc/arctype.h>
+#include <mips/archtype.h>
 #include <arc/algor/algor.h>
 #include <arc/pci/pcibrvar.h>
 #include <arc/pci/v962pcbreg.h>
@@ -85,9 +85,27 @@ struct cfdriver pbcpcibr_cd = {
 	NULL, "pbcpcibr", DV_DULL,
 };
 
+/*
+ * Code from "pci/if_de.c" used to calculate crc32 of ether rom data.
+ * Another example can be found in document EC-QPQWA-TE from DEC.
+ */
+#define      TULIP_CRC32_POLY  0xEDB88320UL
+static __inline__ unsigned
+srom_crc32(
+    const unsigned char *databuf,
+    size_t datalen)
+{
+    u_int idx, bit, data, crc = 0xFFFFFFFFUL;
+
+    for (idx = 0; idx < datalen; idx++)
+        for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1)
+            crc = (crc >> 1) ^ (((crc ^ data) & 1) ? TULIP_CRC32_POLY : 0);
+    return crc;
+}
 static int      pbcpcibrprint __P((void *, const char *pnp));
 
 struct pcibr_config pbc_config;
+static int pbc_version;
 
 int
 pbcpcibrmatch(parent, match, aux)
@@ -114,6 +132,7 @@ pbcpcibrattach(parent, self, aux)
 
 	switch(system_type) {
 	case ALGOR_P4032:
+	case ALGOR_P5064:
 		V96X_PCI_BASE0 = V96X_PCI_BASE0 & 0xffff0000;
 
 		lcp = sc->sc_pcibr = &pbc_config;
@@ -132,6 +151,7 @@ pbcpcibrattach(parent, self, aux)
 		lcp->lc_pc.pc_conf_read = pbc_conf_read;
 		lcp->lc_pc.pc_conf_write = pbc_conf_write;
 		lcp->lc_pc.pc_ether_hw_addr = pbc_ether_hw_addr;
+		lcp->lc_pc.pc_flush_cache = R4K_HitFlushDCache;
 
 	        lcp->lc_pc.pc_intr_v = lcp;
 		lcp->lc_pc.pc_intr_map = pbc_intr_map;
@@ -139,7 +159,8 @@ pbcpcibrattach(parent, self, aux)
 		lcp->lc_pc.pc_intr_establish = pbc_intr_establish;
 		lcp->lc_pc.pc_intr_disestablish = pbc_intr_disestablish;
 
-		printf(": V3 V962, Revision %x.\n", V96X_PCI_CC_REV);
+		pbc_version = V96X_PCI_CC_REV;
+		printf(": V3 V962, Revision %x.\n", pbc_version);
 		break;
 	}
 
@@ -170,13 +191,14 @@ pbcpcibrprint(aux, pnp)
  */
 
 vm_offset_t
-vtophys(p)
-	void *p;
+vtophysaddr(dp, p)
+	struct device *dp;
+	vm_offset_t p;
 {
 	vm_offset_t pa;
 	vm_offset_t va;
 
-	va = (vm_offset_t)p;
+	va = p;
 	if(va >= UADDR) {	/* Stupid driver have buf on stack!! */
 		va = (vm_offset_t)curproc->p_addr + (va & ~UADDR);
 	}
@@ -186,6 +208,10 @@ vtophys(p)
 	else {
 		pa = pmap_extract(vm_map_pmap(phys_map), va);
 	}
+	if(dp->dv_class == DV_IFNET && pbc_version < V96X_VREV_C0) { 
+					/* BUG in early V962PBC's */
+		pa |= 0xc0000000;	/* Use aparture II */
+	}
 	return(pa);
 }
 
@@ -219,7 +245,7 @@ pbc_decompose_tag(cpv, tag, busp, devp, fncp)
 	int *busp, *devp, *fncp;
 {
 	if (busp != NULL)
-		*busp = (tag >> 16) & 0xff;
+		*busp = (tag >> 16) & 0x7;
 	if (devp != NULL)
 		*devp = (tag >> 11) & 0x1f;
 	if (fncp != NULL)
@@ -234,26 +260,50 @@ pbc_conf_read(cpv, tag, offset)
 {
 	pcireg_t data;
 	u_int32_t addr;
-	int device;
+	int bus, device, func, ad_low;
 	int s;
 
-	if((tag >> 16) != 0)
-		return(~0);
 	if(offset & 3 || offset < 0 || offset >= 0x100) {
 		printf ("pci_conf_read: bad reg %x\n", offset);
 		return(~0);
 	}
+	pbc_decompose_tag(cpv, tag, &bus, &device, &func);
+	ad_low = 0;
 
-	device = (tag >> 11) & 0x1f;
-	addr = (0x800 << device) | (tag & 0x380) | offset;
+	if(system_type == ALGOR_P4032) {
+		if(bus != 0 || device > 5 || func > 7) {
+			return(~0);
+		}
+		addr = (0x800 << device) | (func << 8) | offset;
+		ad_low = 0;
+	}
+	else {	/* P5064 */
+		if(bus == 0) {
+			if(device > 5 || func > 7) {
+				return(~0);
+			}
+			addr = (1L << (device + 24)) | (func << 8) | offset;
+			ad_low = 0;
+		}
+		else if(pbc_version >= V96X_VREV_C0) {
+			if(bus > 255 || device > 15 || func > 7) {
+				return(~0);
+			}
+			addr = (bus << 16) | (device << 11) | (func << 8);
+			ad_low = V96X_LB_MAPx_AD_LOW_EN;
+		}
+		else {
+			return(~0);
+		}
+	}
 
 	s = splhigh();
 
+	/* high 12 bits of address go in map register, and set for conf space */
+	V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | ad_low | V96X_LB_TYPE_CONF;
 	/* clear aborts */
 	V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
 
-	/* high 12 bits of address go in map register, and set for conf space */
-	V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
 	wbflush();
 
 	/* low 20 bits of address are in the actual address */
@@ -261,14 +311,13 @@ pbc_conf_read(cpv, tag, offset)
 
 	if (V96X_PCI_STAT & V96X_PCI_STAT_M_ABORT) {
 		V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT;
-		printf ("device %d: master abort\n", device);
-		return(~0);
+		return(~0);	/* Nothing there */
 	}
 
 	if (V96X_PCI_STAT & V96X_PCI_STAT_T_ABORT) {
 		V96X_PCI_STAT |= V96X_PCI_STAT_T_ABORT;
 		printf ("PCI slot %d: target abort!\n", device);
-		return(~0);
+		return(~0);	/* Ooops! */
 	}
 
 	splx(s);
@@ -283,19 +332,46 @@ pbc_conf_write(cpv, tag, offset, data)
 	pcireg_t data;
 {
 	u_int32_t addr;
-	int device;
+	int bus, device, func, ad_low;
 	int s;
 
-	device = (tag >> 11) & 0x1f;
-	addr = (0x800 << device) | (tag & 0x380) | offset;
+	pbc_decompose_tag(cpv, tag, &bus, &device, &func);
+	ad_low = 0;
+
+	if(system_type == ALGOR_P4032) {
+		if(bus != 0 || device > 5 || func > 7) {
+			return;
+		}
+		addr = (0x800 << device) | (func << 8) | offset;
+		ad_low = 0;
+	}
+	else {	/* P5064 */
+		if(bus == 0) {
+			if(device > 5 || func > 7) {
+				return;
+			}
+			addr = (1L << (device + 24)) | (func << 8) | offset;
+			ad_low = 0;
+		}
+		else if(pbc_version >= V96X_VREV_C0) {
+			if(bus > 255 || device > 15 || func > 7) {
+				return;
+			}
+			addr = (bus << 16) | (device << 11) | (func << 8);
+			ad_low = V96X_LB_MAPx_AD_LOW_EN;
+		}
+		else {
+			return;
+		}
+	}
 
 	s = splhigh();
 
+	/* high 12 bits of address go in map register, and set for conf space */
+	V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | ad_low | V96X_LB_TYPE_CONF;
 	/* clear aborts */
 	V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
 
-	/* high 12 bits of address go in map register, and set for conf space */
-	V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
 	wbflush();
 
 	/* low 20 bits of address are in the actual address */
@@ -319,17 +395,60 @@ pbc_conf_write(cpv, tag, offset, data)
 }
 
 /*
- *	Hook to get ethernet hardware address when not in dev rom
+ *	Build the serial rom info normaly stored in an EEROM on
+ *	PCI DEC21x4x boards. Cheapo designs skips the rom so
+ *	we do the job here. The setup is not 100% correct but
+ *	close enough to make the driver happy!
  */
 int
-pbc_ether_hw_addr(cp)
-	u_int8_t *cp;
+pbc_ether_hw_addr(p)
+	u_int8_t *p;
 {
-	if(system_type == ALGOR_P4032) {
-		bcopy(eth_hw_addr, cp, 6);
-		return(0);
+	int i;
+
+	for(i = 0; i < 128; i++)
+		p[i] = 0x00;
+	p[18] = 0x03;	/* Srom version. */
+	p[19] = 0x01;	/* One chip. */
+	/* Next six, ethernet address. */
+	bcopy(eth_hw_addr, &p[20], 6);
+
+	p[26] = 0x00;	/* Chip 0 device number */
+	p[27] = 30;		/* Descriptor offset */
+	p[28] = 00;
+	p[29] = 00;		/* MBZ */
+					/* Descriptor */
+	p[30] = 0x00;	/* Autosense. */
+	p[31] = 0x08;
+	if(system_type == ALGOR_P4032 ||
+	   system_type == ALGOR_P5064) {
+		p[32] = 0x01;	/* Block cnt */
+		p[33] = 0x02;	/* Medium type is AUI */
+	}
+	else {
+		p[32] = 0xff;	/* GP cntrl */
+		p[33] = 0x01;	/* Block cnt */
+#define GPR_LEN 0
+#define	RES_LEN 0
+		p[34] = 0x80 + 12 + GPR_LEN + RES_LEN;
+		p[35] = 0x01;	/* MII PHY type */
+		p[36] = 0x00;	/* PHY number 0 */
+		p[37] = 0x00;	/* GPR Length */
+		p[38] = 0x00;	/* Reset Length */
+		p[39] = 0x00;	/* Media capabilities */
+		p[40] = 0x78;	/* Media capabilities */
+		p[41] = 0x00;	/* Autoneg advertisment */
+		p[42] = 0x78;	/* Autoneg advertisment */
+		p[43] = 0x00;	/* Full duplex map */
+		p[44] = 0x50;	/* Full duplex map */
+		p[45] = 0x00;	/* Treshold map */
+		p[46] = 0x18;	/* Treshold map */
 	}
-	return(-1);
+
+	i = (srom_crc32(p, 126) & 0xFFFF) ^ 0xFFFF;
+	p[126] = i;
+	p[127] = i >> 8;
+	return(1);	/* Got it! */
 }
 
 int
@@ -358,11 +477,11 @@ pbc_intr_map(lcv, bustag, buspin, line, ihp)
 	pirq = buspin - 1;
 
 	switch(device) {
-	case 5:				/* DC21041 */
-		pirq = 1;
+	case 0:				/* DC21041 */
+		pirq = 9;
 		break;
-	case 8:				/* NCR SCSI */
-		pirq = 0;
+	case 1:				/* NCR SCSI */
+		pirq = 10;
 		break;
 	default:
 		switch (buspin) {
diff --git a/sys/arch/arc/pci/pci_machdep.h b/sys/arch/arc/pci/pci_machdep.h
index 5543d2c1f7e..dfeb5995c67 100644
--- a/sys/arch/arc/pci/pci_machdep.h
+++ b/sys/arch/arc/pci/pci_machdep.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pci_machdep.h,v 1.2 1997/04/19 17:20:02 pefo Exp $	*/
+/*	$OpenBSD: pci_machdep.h,v 1.3 1998/03/16 09:38:49 pefo Exp $	*/
 
 /*
  * Copyright (c) 1996 Carnegie-Mellon University.
@@ -61,6 +61,7 @@ struct arc_pci_chipset {
 			    int, int (*)(void *), void *, char *));
 	void		(*pc_intr_disestablish) __P((void *, void *));
 	int		(*pc_ether_hw_addr) __P((u_int8_t *));
+	void		(*pc_flush_cache) __P((vm_offset_t, int));
 };
 
 /*
@@ -88,6 +89,10 @@ struct arc_pci_chipset {
     (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
 #define	pci_ether_hw_addr(c, p)						\
     (*(c)->pc_ether_hw_addr)((p))
+#define	pci_flush_cache(p, s)						\
+    (*(c)->pc_flush_cache)((p, s))
 
-vm_offset_t vtophys __P((void *));
+vm_offset_t vtophysaddr __P((struct device *, vm_offset_t));
 
+#define	TULIP_KVATOPHYS(sc, va)	vtophysaddr(&sc->tulip_dev, (vm_offset_t)va)
+#define	NCR_KVATOPHYS(sc, va)	vtophysaddr(&sc->sc_dev, (vm_offset_t)va)
diff --git a/sys/arch/arc/pci/v962pcbreg.h b/sys/arch/arc/pci/v962pcbreg.h
index e0e4865213b..9320bafee6b 100644
--- a/sys/arch/arc/pci/v962pcbreg.h
+++ b/sys/arch/arc/pci/v962pcbreg.h
@@ -11,7 +11,7 @@
 /* offsets from base pointer, this construct allows optimisation */
 static char * const _v96xp = (char *)P4032_V96x;
 
-#if #endian(little)
+#if BYTE_ORDER == LITTLE_ENDIAN
 #define V96XW(x)		*(volatile unsigned long *)(_v96xp + (x))
 #define V96XH(x)		*(volatile unsigned short *)(_v96xp + (x))
 #define V96XB(x)		*(volatile unsigned char *)(_v96xp + (x))
@@ -26,10 +26,11 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_PCI_CMD		V96XH(0x04)
 #define V96X_PCI_STAT		V96XH(0x06)
 #define V96X_PCI_CC_REV		V96XW(0x08)
+#define V96X_PCI_I20_BASE	V96XW(0x10) /* B.2 only */
 #define V96X_PCI_HDR_CFG	V96XW(0x0c)	
 #define V96X_PCI_IO_BASE	V96XW(0x10)
 #define V96X_PCI_BASE0		V96XW(0x14)
-#define V96X_PCI_BASE1		V96XW(0x1c)
+#define V96X_PCI_BASE1		V96XW(0x18)
 #define V96X_PCI_BPARAM		V96XW(0x3c)
 #define V96X_PCI_MAP0		V96XW(0x40)
 #define V96X_PCI_MAP1		V96XW(0x44)
@@ -39,6 +40,9 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_LB_BASE1		V96XW(0x58)
 #define V96X_LB_MAP0		V96XH(0x5e)
 #define V96X_LB_MAP1		V96XH(0x62)
+#define V96X_LB_BASE2		V96XH(0x64) /* B.2 only */
+#define V96X_LB_MAP2		V96XH(0x66) /* B.2 only */
+#define V96X_LB_SIZE		V96XW(0x68) /* B.2 only */
 #define V96X_LB_IO_BASE		V96XW(0x6c)
 #define V96X_FIFO_CFG		V96XH(0x70)
 #define V96X_FIFO_PRIORITY	V96XH(0x72)
@@ -46,7 +50,9 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_LB_ISTAT		V96XB(0x76)
 #define V96X_LB_IMASK		V96XB(0x77)
 #define V96X_SYSTEM		V96XH(0x78)
+#define V96X_LB_CFGL		V96XB(0x7a)
 #define V96X_LB_CFG		V96XB(0x7b)
+#define V96X_PCI_CFG		V96XB(0x7c) /* B.2 only */
 #define V96X_DMA_PCI_ADDR0	V96XW(0x80)
 #define V96X_DMA_LOCAL_ADDR0	V96XW(0x84)
 #define V96X_DMA_LENGTH0	V96XW(0x88)
@@ -87,7 +93,8 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_VREV_A	0x0
 #define V96X_VREV_B0	0x1
 #define V96X_VREV_B1	0x2
-#define V96X_VREV_C0	0x3
+#define V96X_VREV_B2	0x3
+#define V96X_VREV_C0	0x4
 
 #define V96X_PCI_HDR_CFG_LT		0x0000ff00
 #define V96X_PCI_HDR_CFG_LT_SHIFT	8
@@ -143,8 +150,9 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_SWAP_NONE			(0x0<<8)
 #define V96X_SWAP_16BIT			(0x1<<8)
 #define V96X_SWAP_8BIT			(0x2<<8)
+#define V96X_SWAP_AUTO			(0x3<<8)
 
-/* pci interruprt status register */
+/* pci interrupt status register */
 #define V96X_PCI_INT_STAT_MAILBOX	0x80000000
 #define V96X_PCI_INT_STAT_LOCAL		0x40000000
 #define V96X_PCI_INT_STAT_DMA1		0x02000000
@@ -210,6 +218,7 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define  V96X_LB_TYPE_IO		 (0x1<<1)
 #define  V96X_LB_TYPE_MEM		 (0x3<<1)
 #define  V96X_LB_TYPE_CONF		 (0x5<<1)
+#define V96X_LB_MAPx_AD_LOW_EN		0x0001 /* C.0 only */
 
 /* local bus interrupt control, status and masks */
 #define V96X_LB_INTR_MAILBOX		0x80
@@ -226,6 +235,16 @@ static char * const _v96xp = (char *)P4032_V96x;
 #define V96X_LB_CFG_ERR_EN		0x02
 #define V96X_LB_CFG_RDY_EN		0x01
 
+/* PCI bus configuration */
+#define V96X_PCI_CFG_I2O_EN		0x8000
+#define V96X_PCI_CFG_IO_REG_DIS		0x4000
+#define V96X_PCI_CFG_IO_DIS		0x2000
+#define V96X_PCI_CFG_EN3V		0x1000
+#define V96X_PCI_CFG_AD_LOW		0x0300
+#define V96X_PCI_CFG_AD_LOW_SHIFT	8
+#define V96X_PCI_CFG_DMA_RTYPE		0x00e0
+#define V96X_PCI_CFG_DMA_WTYPE		0x000e    
+
 /* fifo configuration register */ 
 #define V96X_FIFO_CFG_PBRST_MAX		0xc000
 #define V96X_FIFO_CFG_PBRST_MAX_SHIFT	14
diff --git a/sys/arch/arc/pica/picabus.c b/sys/arch/arc/pica/picabus.c
index 13a381b5cf0..48a4e69b5b8 100644
--- a/sys/arch/arc/pica/picabus.c
+++ b/sys/arch/arc/pica/picabus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: picabus.c,v 1.9 1998/01/29 14:54:56 pefo Exp $	*/
+/*	$OpenBSD: picabus.c,v 1.10 1998/03/16 09:38:52 pefo Exp $	*/
 /*	$NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp $	*/
 
 /*
@@ -98,7 +98,6 @@ struct pica_dev {
 	intr_handler_t	ps_handler;
 	void 		*ps_base;
 };
-#ifdef ACER_PICA_61
 struct pica_dev acer_pica_61_cpu[] = {
 	{{ "dallas_rtc",0, 0, },
 	   0,			 pica_intrnull, (void *)PICA_SYS_CLOCK, },
@@ -125,15 +124,15 @@ struct pica_dev acer_pica_61_cpu[] = {
 	{{ NULL,       -1, NULL, },
 	   0, NULL, (void *)NULL, },
 };
-#endif
 
 struct pica_dev *pica_cpu_devs[] = {
         NULL,                   /* Unused */
-#ifdef ACER_PICA_61
         acer_pica_61_cpu,       /* Acer PICA */
-#else
+        acer_pica_61_cpu,       /* MAGNUMS same as Acer PICA */
 	NULL,
-#endif
+	NULL,
+	NULL,
+        acer_pica_61_cpu,       /* NEC-R94 same as MAGNUM */
 };
 int npica_cpu_devs = sizeof pica_cpu_devs / sizeof pica_cpu_devs[0];