xscale bits, taken from NetBSD with modifications as appropriate for OpenBSD.

5 files changed, 731 insertions, 0 deletions

diff --git a/sys/arch/arm/sa11x0/sa1111_reg.h b/sys/arch/arm/sa11x0/sa1111_reg.h
new file mode 100644
index 00000000000..f34a7dcaf81
--- /dev/null
+++ b/sys/arch/arm/sa11x0/sa1111_reg.h
@@ -0,0 +1,128 @@
+/*	$NetBSD: sa1111_reg.h,v 1.3 2002/12/18 04:09:31 bsh Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_SA11X0_SA1111_REG_H
+#define _ARM_SA11X0_SA1111_REG_H
+
+
+/* Interrupt Controller */
+
+/* number of interrupt bits */
+#define SACCIC_LEN	55
+
+/* System Bus Interface */
+#define SACCSBI_SKCR		0x0000
+#define  SKCR_PLLBYPASS  	(1<<0)
+#define  SKCR_RCLKEN    	(1<<1)
+#define  SKCR_SLEEP     	(1<<2)
+#define  SKCR_DOZE		(1<<3)
+#define  SKCR_VCOOFF		(1<<4)
+#define  SKCR_RDYEN		(1<<7)
+#define  SKCR_SELAC		(1<<8)	/* AC Link or I2S */
+#define  SKCR_NOEEN		(1<<12)	/* Enable nOE */
+#define SACCSBI_SMCR		0x0004
+#define SACCSBI_SKID		0x0008
+
+/* System Controller */
+#define SACCSC_SKPCR		0x0200
+
+/* USB Host Controller */
+#define SACCUSB_REVISION	0x0400
+#define SACCUSB_CONTROL		0x0404
+#define SACCUSB_STATUS		0x0408
+#define SACCUSB_RESET		0x051C
+
+/* Interrupt Controller */
+#define SACCIC_INTTEST0		0x1600
+#define SACCIC_INTTEST1		0x1604
+#define SACCIC_INTEN0		0x1608
+#define SACCIC_INTEN1		0x160C
+#define SACCIC_INTPOL0		0x1610
+#define SACCIC_INTPOL1		0x1614
+#define SACCIC_INTTSTSEL	0x1618
+#define SACCIC_INTSTATCLR0	0x161C
+#define SACCIC_INTSTATCLR1	0x1620
+#define SACCIC_INTSET0		0x1624
+#define SACCIC_INTSET1		0x1628
+#define SACCIC_WAKE_EN0		0x162C
+#define SACCIC_WAKE_EN1		0x1630
+#define SACCIC_WAKE_POL0	0x1634
+#define SACCIC_WAKE_POL1	0x1638
+
+/* GPIO registers */
+#define SACCGPIOA_DDR		0x1000		/* data direction */
+#define SACCGPIOA_DVR		0x1004		/* data value */
+#define SACCGPIOA_SDR		0x1008		/* sleep direction */
+#define SACCGPIOA_SSR		0x100C		/* sleep state */
+#define SACCGPIOB_DDR		0x1010
+#define SACCGPIOB_DVR		0x1014
+#define SACCGPIOB_SDR		0x1018
+#define SACCGPIOB_SSR		0x101C
+#define SACCGPIOC_DDR		0x1020
+#define SACCGPIOC_DVR		0x1024
+#define SACCGPIOC_SDR		0x1028
+#define SACCGPIOC_SSR		0x102C
+
+#define SACC_KBD0		0x0a00
+#define SACC_KBD1		0x0c00
+
+#define SACCKBD_CR		0x00
+#define  KBDCR_FKC		(1<<0) /* Force MSCLK/TPCLK low */
+#define  KBDCR_FKD		(1<<1) /* Force MSDATA/TPDATA low */
+#define  KBDCR_ENA		(1<<3) /* Enable */
+#define SACCKBD_STAT		0x04
+#define  KBDSTAT_KBC		(1<<0) /* KBCLK pin value */
+#define  KBDSTAT_KBD		(1<<1) /* KBDATA pin value */
+#define  KBDSTAT_RXP		(1<<2) /* Parity */
+#define  KBDSTAT_ENA		(1<<3) /* Enable */
+#define  KBDSTAT_RXB		(1<<4) /* Rx busy */
+#define  KBDSTAT_RXF		(1<<5) /* Rx full */
+#define  KBDSTAT_TXB		(1<<6) /* Tx busy */
+#define  KBDSTAT_TXE		(1<<7) /* Tx empty */
+#define  KBDSTAT_STP		(1<<8) /* Stop bit error */
+#define SACCKBD_DATA		0x08
+#define SACCKBD_CLKDIV		0x0c
+#define  KBDCLKDIV_DIV8		0
+#define  KBDCLKDIV_DIV4		1
+#define  KBDCLKDIV_DIV2		2
+#define SACCKBD_CLKPRECNT	0x10
+#define SACCKBD_KBDITR		0x14 /* Interrupt test */
+
+#define SACCKBD_SIZE  		0x18
+
+#endif /* _ARM_SA11X0_SA1111_REG_H */
diff --git a/sys/arch/arm/sa11x0/sa11x0_ost.c b/sys/arch/arm/sa11x0/sa11x0_ost.c
new file mode 100644
index 00000000000..76a02f3080b
--- /dev/null
+++ b/sys/arch/arm/sa11x0/sa11x0_ost.c
@@ -0,0 +1,369 @@
+/*	$NetBSD: sa11x0_ost.c,v 1.11 2003/07/15 00:24:51 lukem Exp $	*/
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+/*
+__KERNEL_RCSID(0, "$NetBSD: sa11x0_ost.c,v 1.11 2003/07/15 00:24:51 lukem Exp $");
+*/
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <arm/cpufunc.h>
+
+#include <arm/sa11x0/sa11x0_reg.h> 
+#include <arm/sa11x0/sa11x0_var.h>
+#include <arm/sa11x0/sa11x0_ostreg.h>
+
+static int	saost_match(struct device *, void *, void *);
+static void	saost_attach(struct device *, struct device *, void *);
+
+int		gettick(void);
+static int	clockintr(void *);
+static int	statintr(void *);
+void		rtcinit(void);
+
+struct saost_softc {
+	struct device		sc_dev;
+	bus_addr_t		sc_baseaddr;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+
+	u_int32_t	sc_clock_count;
+	u_int32_t	sc_statclock_count;
+	u_int32_t	sc_statclock_step;
+};
+
+static struct saost_softc *saost_sc = NULL;
+
+#define TIMER_FREQUENCY         3686400         /* 3.6864MHz */
+#define TICKS_PER_MICROSECOND   (TIMER_FREQUENCY/1000000)
+
+#ifndef STATHZ
+#define STATHZ	64
+#endif
+
+#if 0
+CFATTACH_DECL(saost, sizeof(struct saost_softc),
+    saost_match, saost_attach, NULL, NULL);
+#endif
+
+struct cfattach saost_ca = {
+	sizeof (struct saost_softc), saost_match, saost_attach
+};
+
+struct cfdriver saost_cd = {
+	NULL, "saost", DV_DULL
+};
+
+static int
+saost_match(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	return (1);
+}
+
+void
+saost_attach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	struct saost_softc *sc = (struct saost_softc*)self;
+	struct sa11x0_attach_args *sa = aux;
+
+	printf("\n");
+
+	sc->sc_iot = sa->sa_iot;
+	sc->sc_baseaddr = sa->sa_addr;
+
+	saost_sc = sc;
+
+	if(bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 
+			&sc->sc_ioh))
+		panic("%s: Cannot map registers", self->dv_xname);
+
+	/* disable all channel and clear interrupt status */
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 0);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf);
+
+	printf("%s: SA-11x0 OS Timer\n",  sc->sc_dev.dv_xname);
+}
+
+static int
+clockintr(arg)
+	void *arg;
+{
+	struct clockframe *frame = arg;
+	u_int32_t oscr, nextmatch, oldmatch;
+	int s;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_SR, 1);
+
+	/* schedule next clock intr */
+	oldmatch = saost_sc->sc_clock_count;
+	nextmatch = oldmatch + TIMER_FREQUENCY / hz;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0,
+			  nextmatch);
+	oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				SAOST_CR);
+
+	if ((nextmatch > oldmatch &&
+	     (oscr > nextmatch || oscr < oldmatch)) ||
+	    (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) {
+		/*
+		 * we couldn't set the matching register in time.
+		 * just set it to some value so that next interrupt happens.
+		 * XXX is it possible to compansate lost interrupts?
+		 */
+
+		s = splhigh();
+		oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+					SAOST_CR);
+		nextmatch = oscr + 10;
+		bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				  SAOST_MR0, nextmatch);
+		splx(s);
+	}
+
+	saost_sc->sc_clock_count = nextmatch;
+	hardclock(frame);
+
+	return(1);
+}
+
+static int
+statintr(arg)
+	void *arg;
+{
+	struct clockframe *frame = arg;
+	u_int32_t oscr, nextmatch, oldmatch;
+	int s;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_SR, 2);
+
+	/* schedule next clock intr */
+	oldmatch = saost_sc->sc_statclock_count;
+	nextmatch = oldmatch + saost_sc->sc_statclock_step;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1,
+			  nextmatch);
+	oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				SAOST_CR);
+
+	if ((nextmatch > oldmatch &&
+	     (oscr > nextmatch || oscr < oldmatch)) ||
+	    (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) {
+		/*
+		 * we couldn't set the matching register in time.
+		 * just set it to some value so that next interrupt happens.
+		 * XXX is it possible to compansate lost interrupts?
+		 */
+
+		s = splhigh();
+		oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+					SAOST_CR);
+		nextmatch = oscr + 10;
+		bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				  SAOST_MR1, nextmatch);
+		splx(s);
+	}
+
+	saost_sc->sc_statclock_count = nextmatch;
+	statclock(frame);
+
+	return(1);
+}
+
+
+void
+setstatclockrate(hz)
+	int hz;
+{
+	u_int32_t count;
+
+	saost_sc->sc_statclock_step = TIMER_FREQUENCY / hz;
+	count = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR);
+	count += saost_sc->sc_statclock_step;
+	saost_sc->sc_statclock_count = count;
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_MR1, count);
+}
+
+void
+cpu_initclocks()
+{
+	stathz = STATHZ;
+	profhz = stathz;
+	saost_sc->sc_statclock_step = TIMER_FREQUENCY / stathz;
+
+	printf("clock: hz=%d stathz = %d\n", hz, stathz);
+
+	/* Use the channels 0 and 1 for hardclock and statclock, respectively */
+	saost_sc->sc_clock_count = TIMER_FREQUENCY / hz;
+	saost_sc->sc_statclock_count = TIMER_FREQUENCY / stathz;
+
+	sa11x0_intr_establish(0, 26, 1, IPL_CLOCK, clockintr, 0);
+	sa11x0_intr_establish(0, 27, 1, IPL_CLOCK, statintr, 0);
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 3);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0,
+			  saost_sc->sc_clock_count);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1,
+			  saost_sc->sc_statclock_count);
+
+	/* Zero the counter value */
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR, 0);
+}
+
+int
+gettick()
+{
+	int counter;
+	u_int savedints;
+	savedints = disable_interrupts(I32_bit);
+
+	counter = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_CR);
+
+	restore_interrupts(savedints);
+	return counter;
+}
+
+void
+microtime(tvp)
+	register struct timeval *tvp;
+{
+	int s, tm, deltatm;
+	static struct timeval lasttime;
+
+	if(saost_sc == NULL) {
+		tvp->tv_sec = 0;
+		tvp->tv_usec = 0;
+		return;
+	}
+
+	s = splhigh();
+	tm = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_CR);
+
+	deltatm = saost_sc->sc_clock_count - tm;
+
+#ifdef OST_DEBUG
+	printf("deltatm = %d\n",deltatm);
+#endif
+
+	*tvp = time;
+	tvp->tv_usec++;		/* XXX */
+	while (tvp->tv_usec >= 1000000) {
+		tvp->tv_sec++;
+		tvp->tv_usec -= 1000000;
+	}
+
+	if (tvp->tv_sec == lasttime.tv_sec &&
+		tvp->tv_usec <= lasttime.tv_usec &&
+		(tvp->tv_usec = lasttime.tv_usec + 1) >= 1000000)
+	{
+		tvp->tv_sec++;
+		tvp->tv_usec -= 1000000;
+	}
+	lasttime = *tvp;
+	splx(s);
+}
+
+void
+delay(usecs)
+	u_int usecs;
+{
+	u_int32_t tick, otick, delta;
+	int j, csec, usec;
+
+	csec = usecs / 10000;
+	usec = usecs % 10000;
+	
+	usecs = (TIMER_FREQUENCY / 100) * csec
+	    + (TIMER_FREQUENCY / 100) * usec / 10000;
+
+	if (! saost_sc) {
+		/* clock isn't initialized yet */
+		for(; usecs > 0; usecs--)
+			for(j = 100; j > 0; j--)
+				;
+		return;
+	}
+
+	otick = gettick();
+
+	while (1) {
+		for(j = 100; j > 0; j--)
+			;
+		tick = gettick();
+		delta = tick - otick;
+		if (delta > usecs)
+			break;
+		usecs -= delta;
+		otick = tick;
+	}
+}
+
+void
+resettodr()
+{
+}
+
+void
+inittodr(base)
+	time_t base;
+{
+	time.tv_sec = base;
+	time.tv_usec = 0;
+}
diff --git a/sys/arch/arm/sa11x0/sa11x0_ostreg.h b/sys/arch/arm/sa11x0/sa11x0_ostreg.h
new file mode 100644
index 00000000000..0db7282c265
--- /dev/null
+++ b/sys/arch/arm/sa11x0/sa11x0_ostreg.h
@@ -0,0 +1,80 @@
+/*	$NetBSD: sa11x0_ostreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * SA-11x0 OS Timer Register 
+ */
+
+/* OS Timer Match Register */
+#define SAOST_MR0	0x00
+#define SAOST_MR1	0x04
+#define SAOST_MR2	0x08
+#define SAOST_MR3	0x0C
+
+/* OS Timer Count Register */
+#define SAOST_CR	0x10
+
+/* OS Timer Status Register */
+#define SAOST_SR	0x14
+#define SR_CH0		(1<<0)
+#define SR_CH1		(1<<1)
+#define SR_CH2		(1<<2)
+#define SR_CH3		(1<<3)
+
+/* OS Timer Watchdog Match Enable Register */
+#define SAOST_WR	0x18
+
+/* OS Timer Interrupt Enable Register */
+#define SAOST_IR	0x1C
+
+/*
+ * SA-1110 Real Time Clock
+ */
+
+/* RTC Alarm Register */
+#define SARTC_AR	0x00
+
+/* RTC Counter Register */
+#define SARTC_CR	0x04
+
+/* RTC Trim Register */
+#define SARTC_TR	0x08
+
+/* RTC Status Register */
+#define SARTC_SR	0x0C
+
+/* end of sa11x0_ostreg.h */
diff --git a/sys/arch/arm/sa11x0/sa11x0_reg.h b/sys/arch/arm/sa11x0/sa11x0_reg.h
new file mode 100644
index 00000000000..3c94c1725ee
--- /dev/null
+++ b/sys/arch/arm/sa11x0/sa11x0_reg.h
@@ -0,0 +1,78 @@
+/*	$NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_SA11X0_REG_H_
+#define _ARM_SA11X0_REG_H_
+
+/* Physical register base addresses */
+#define SAOST_BASE		0x90000000	/* OS Timer */
+#define SARTC_BASE		0x90010000	/* Real-Time Clock */
+#define SAPMR_BASE		0x90020000	/* Power Manager */
+#define SARCR_BASE		0x90030000	/* Reset Controller */
+#define SAGPIO_BASE		0x90040000	/* GPIO */
+#define SAIPIC_BASE		0x90050000	/* Interrupt Controller */
+#define SAPPC_BASE		0x90060000	/* Peripheral Pin Controller */
+#define SAUDC_BASE		0x80000000	/* USB Device Controller*/
+#define	SACOM1_BASE		0x80010000	/* GPCLK/UART 1 */
+#define SACOM3_HW_BASE		0x80050000	/* UART 3  */
+#define SAMCP_BASE		0x80060000	/* MCP Controller */
+#define SASSP_BASE		0x80070000	/* Synchronous serial port */
+
+#define SADMAC_BASE		0xB0000000	/* DMA Controller */
+#define SALCD_BASE		0xB0100000	/* LCD */
+
+/* Register base virtual addresses mapped by initarm() */
+#define SACOM3_BASE             0xd000d000
+
+/* Interrupt controller registers */
+#define SAIPIC_NPORTS		9
+#define SAIPIC_IP		0x00		/* IRQ pending register */
+#define SAIPIC_MR		0x04		/* Mask register */
+#define SAIPIC_LR		0x08		/* Level register */
+#define SAIPIC_FP		0x10		/* FIQ pending register */
+#define SAIPIC_PR		0x20		/* Pending register */
+#define SAIPIC_CR		0x0C		/* Control register */
+
+/* width of interrupt controller */
+#define ICU_LEN			32
+
+/* Reset controller registers */
+#define SARCR_RSRR		0x0		/* Software reset register */
+#define SARCR_RCSR		0x4		/* Reset status register */
+#define SARCR_TUCR		0x8		/* Test Unit control reg */
+
+#endif /* _ARM_SA11X0_REG_H_ */
diff --git a/sys/arch/arm/sa11x0/sa11x0_var.h b/sys/arch/arm/sa11x0/sa11x0_var.h
new file mode 100644
index 00000000000..5c966a0bd92
--- /dev/null
+++ b/sys/arch/arm/sa11x0/sa11x0_var.h
@@ -0,0 +1,76 @@
+/*      $NetBSD: sa11x0_var.h,v 1.4 2003/04/14 14:18:41 rjs Exp $        */
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef _SA11X0_VAR_H
+#define _SA11X0_VAR_H
+
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+
+struct sa11x0_softc {
+	struct device sc_dev;
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+	bus_space_handle_t sc_gpioh;
+	bus_space_handle_t sc_ppch;
+	bus_space_handle_t sc_dmach;
+	bus_space_handle_t sc_reseth;
+	u_int32_t sc_intrmask;
+};
+
+/* Attach args all devices */
+
+typedef void *sa11x0_chipset_tag_t;
+
+struct sa11x0_attach_args {
+	sa11x0_chipset_tag_t	sa_sc;		
+	bus_space_tag_t		sa_iot;		/* Bus tag */
+	bus_addr_t		sa_addr;	/* i/o address  */
+	bus_size_t		sa_size;
+
+	int			sa_intr;
+	int			sa_gpio;
+};
+
+void *sa11x0_intr_establish(sa11x0_chipset_tag_t, int, int, int, 
+			    int (*)(void *), void *);
+void sa11x0_intr_disestablish(sa11x0_chipset_tag_t, void *);
+
+#endif /* _SA11X0_VAR_H */