Rearrange the interrupt handler so that it handlers "error status bits"

first instead of trying to push data transfers forward.  Also, ensure that
DONE interrupts are only un-masked when we are on the last sub-block, and
that otherwise we process based on RD_REQ and WR_REQ interrupts coming in.
Done with drahn and marex (starting from bizzare workarounds by marex
which we could not explain)
This appears to make Zaurus SD reads & writes completely reliable, even at
very low cpu speeds.
ok drahn marex

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