s/Mhz/MHz/ in comments and printf() strings

ok jsg@

3 files changed, 14 insertions, 14 deletions

diff --git a/sys/arch/arm/xscale/pxa2x0_apm.c b/sys/arch/arm/xscale/pxa2x0_apm.c
index 8fc2bc84623..f66c4ff8df5 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm.c
+++ b/sys/arch/arm/xscale/pxa2x0_apm.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_apm.c,v 1.25 2005/12/22 00:42:14 deraadt Exp $	*/
+/*	$OpenBSD: pxa2x0_apm.c,v 1.26 2006/10/19 10:55:56 tom Exp $	*/
 
 /*-
  * Copyright (c) 2001 Alexander Guy.  All rights reserved.
@@ -881,7 +881,7 @@ pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc)
 	sd.sd_osmr5 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSMR5);
 	sd.sd_oier = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OIER);
 
-	/* Bring the PXA27x into 416Mhz turbo mode. */
+	/* Bring the PXA27x into 416MHz turbo mode. */
         if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X &&
 	    bus_space_read_4(sc->sc_iot, pxa2x0_clkman_ioh, CLKMAN_CCCR) !=
 	    (CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16)) {
@@ -999,7 +999,7 @@ suspend_again:
 	bus_space_write_4(sc->sc_iot, sc->sc_pm_ioh, POWMAN_RCSR,
 	    RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR);
 
-	/* Stop 3/13Mhz oscillator; do not float PCMCIA and chip-selects. */
+	/* Stop 3/13MHz oscillator; do not float PCMCIA and chip-selects. */
 	rv = PCFR_OPDE;
         if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X)
 		/* Enable nRESET_GPIO as a GPIO reset input. */
@@ -1141,13 +1141,13 @@ suspend_again:
 
 	pxa2x0_pi2c_setvoltage(sc->sc_iot, sc->sc_pm_ioh, PI2C_VOLTAGE_HIGH);
 
-	/* Change to 208Mhz run mode with fast-bus still disabled. */
+	/* Change to 208MHz run mode with fast-bus still disabled. */
 	pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16,
 	    CLKCFG_F, &pxa2x0_memcfg);
 	delay(1); /* XXX is the delay long enough, and necessary at all? */
 	pxa27x_fastbus_run_mode(1, pxa2x0_memcfg.mdrefr_high);
 
-	/* Change to 416Mhz turbo mode with fast-bus enabled. */
+	/* Change to 416MHz turbo mode with fast-bus enabled. */
 	pxa27x_frequency_change(CCCR_A | CCCR_TURBO_X2 | CCCR_RUN_X16,
 	    CLKCFG_B | CLKCFG_F | CLKCFG_T, &pxa2x0_memcfg);
 
diff --git a/sys/arch/arm/xscale/pxa2x0_apm_asm.S b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
index d4c79ec4484..72b307f2590 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm_asm.S
+++ b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_apm_asm.S,v 1.1 2005/02/22 21:53:03 uwe Exp $	*/
+/*	$OpenBSD: pxa2x0_apm_asm.S,v 1.2 2006/10/19 10:55:56 tom Exp $	*/
 
 /*
  * Copyright (c) 2005 Uwe Stuehler <uwe@openbsd.org>
@@ -486,7 +486,7 @@ ENTRY(pxa27x_frequency_change)
 	and	r3, r0, #CCCR_L_MASK
 	ldr	r0, .Lmemctliohp
 	ldr	r0, [r0]
-	cmp	r3, #CCCR_RUN_X7		/* L=7 is 91Mhz mode */
+	cmp	r3, #CCCR_RUN_X7		/* L=7 is 91MHz mode */
 	beq	frequency_change_91
 	and	r3, r1, #CLKCFG_B
 	cmp	r3, #CLKCFG_B
@@ -520,7 +520,7 @@ frequency_change_on_cache:
 	/* Program new CLKCFG value, starting a core PLL frequency change
 	 * if CLKCFG_F is set. */
 	mcr	p14, 0, r1, c6, c0, 0
-	/* Change SDRAM clock frequency to 104Mhz, and ensure that the
+	/* Change SDRAM clock frequency to 104MHz, and ensure that the
 	 * store to MDREFR is complete before the next SDRAM access. */
 	str	r4, [r0, #MEMCTL_MDREFR]
 	ldr	r5, [r0, #MEMCTL_MDREFR]
@@ -537,7 +537,7 @@ frequency_change_on_cache:
 /*
  * void pxa27x_cpu_speed_91(void)
  *
- * Switch core run frequency to 91 Mhz.
+ * Switch core run frequency to 91 MHz.
  */
 	.align 5
 ENTRY(pxa27x_cpu_speed_91)
diff --git a/sys/arch/arm/xscale/pxa2x0reg.h b/sys/arch/arm/xscale/pxa2x0reg.h
index 953f16a17f2..19287398112 100644
--- a/sys/arch/arm/xscale/pxa2x0reg.h
+++ b/sys/arch/arm/xscale/pxa2x0reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0reg.h,v 1.27 2006/03/07 22:35:57 uwe Exp $ */
+/*	$OpenBSD: pxa2x0reg.h,v 1.28 2006/10/19 10:55:56 tom Exp $ */
 /* $NetBSD: pxa2x0reg.h,v 1.4 2003/06/11 20:43:01 scw Exp $ */
 
 /*
@@ -314,10 +314,10 @@ struct pxa2x0_dma_desc {
 #define  CCCR_MEM_X40	 (4<<0)	/* x27, 99.53MHz */
 #define  CCCR_MEM_X45	 (5<<0)	/* x27, 99.53MHz */
 #define  CCCR_MEM_X9	 (0x1f<<0)	/* x9, 33.2MHz */
-/* PXA27x: L is the core run frequency to 13Mhz oscillator ratio. */
-#define  CCCR_RUN_X7	 (7<<0)	 /* 91Mhz, 91Mhz mem, 91Mhz LCD */
-#define  CCCR_RUN_X8	 (8<<0)	 /* 104Mhz, 104Mhz mem, 52Mhz LCD */
-#define  CCCR_RUN_X16	 (16<<0) /* 208Mhz, 104/208Mhz mem, 104Mhz LCD */
+/* PXA27x: L is the core run frequency to 13MHz oscillator ratio. */
+#define  CCCR_RUN_X7	 (7<<0)	 /* 91MHz, 91MHz mem, 91MHz LCD */
+#define  CCCR_RUN_X8	 (8<<0)	 /* 104MHz, 104MHz mem, 52MHz LCD */
+#define  CCCR_RUN_X16	 (16<<0) /* 208MHz, 104/208MHz mem, 104MHz LCD */
 
 #define CLKMAN_CKEN	0x04	/* Clock Enable Register */
 #define CLKMAN_OSCC	0x08	/* Oscillator Configuration Register */