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authorMark Kettenis <kettenis@cvs.openbsd.org>2021-02-16 12:33:23 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2021-02-16 12:33:23 +0000
commit11c6522fa0bc4270221b9d632cdcd8f1d58d2512 (patch)
tree9d1499c4289774a7bdf762ecf45e5caa5d253462 /sys/arch/arm64/include
parent1d7aedfe1f364b32777f615944a46ebaa0be3764 (diff)
Introduce BUS_SPACE_MAP_POSTED such that we can distinguish between
posted and non-posted device memory mappings and set the right memory attributes for them. Needed because on the Apple M1 using the wrong mapping will fault. ok patrick@, dlg@
Diffstat (limited to 'sys/arch/arm64/include')
-rw-r--r--sys/arch/arm64/include/bus.h10
-rw-r--r--sys/arch/arm64/include/pmap.h5
-rw-r--r--sys/arch/arm64/include/pte.h12
3 files changed, 14 insertions, 13 deletions
diff --git a/sys/arch/arm64/include/bus.h b/sys/arch/arm64/include/bus.h
index 73678b5bf81..092a4869212 100644
--- a/sys/arch/arm64/include/bus.h
+++ b/sys/arch/arm64/include/bus.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: bus.h,v 1.7 2020/04/13 21:34:54 kettenis Exp $ */
+/* $OpenBSD: bus.h,v 1.8 2021/02/16 12:33:22 kettenis Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
*
@@ -129,10 +129,10 @@ struct bus_space {
#define bus_space_subregion(t, h, o, s, p) \
(*(t)->_space_subregion)((t), (h), (o), (s), (p))
-#define BUS_SPACE_MAP_CACHEABLE 0x01
-#define BUS_SPACE_MAP_KSEG0 0x02
-#define BUS_SPACE_MAP_LINEAR 0x04
-#define BUS_SPACE_MAP_PREFETCHABLE 0x08
+#define BUS_SPACE_MAP_CACHEABLE 0x01
+#define BUS_SPACE_MAP_POSTED 0x02
+#define BUS_SPACE_MAP_LINEAR 0x04
+#define BUS_SPACE_MAP_PREFETCHABLE 0x08
#define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
#define bus_space_mmap(t, a, o, p, f) \
diff --git a/sys/arch/arm64/include/pmap.h b/sys/arch/arm64/include/pmap.h
index 28f76b5dae1..d0c486ae17a 100644
--- a/sys/arch/arm64/include/pmap.h
+++ b/sys/arch/arm64/include/pmap.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.h,v 1.15 2021/02/15 20:44:08 kettenis Exp $ */
+/* $OpenBSD: pmap.h,v 1.16 2021/02/16 12:33:22 kettenis Exp $ */
/*
* Copyright (c) 2008,2009,2014 Dale Rahn <drahn@dalerahn.com>
*
@@ -42,7 +42,8 @@
#define PMAP_CACHE_CI (PMAP_MD0) /* cache inhibit */
#define PMAP_CACHE_WT (PMAP_MD1) /* writethru */
#define PMAP_CACHE_WB (PMAP_MD1|PMAP_MD0) /* writeback */
-#define PMAP_CACHE_DEV (PMAP_MD2) /* device mapping */
+#define PMAP_CACHE_DEV_NGNRNE (PMAP_MD2) /* device nGnRnE */
+#define PMAP_CACHE_DEV_NGNRE (PMAP_MD2|PMAP_MD0) /* device nGnRE */
#define PMAP_CACHE_BITS (PMAP_MD0|PMAP_MD1|PMAP_MD2)
#define PTED_VA_MANAGED_M (PMAP_MD3)
diff --git a/sys/arch/arm64/include/pte.h b/sys/arch/arm64/include/pte.h
index 10500aca24f..9c566b872cc 100644
--- a/sys/arch/arm64/include/pte.h
+++ b/sys/arch/arm64/include/pte.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pte.h,v 1.5 2017/04/13 23:29:02 kettenis Exp $ */
+/* $OpenBSD: pte.h,v 1.6 2021/02/16 12:33:22 kettenis Exp $ */
/*
* Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
*
@@ -53,11 +53,11 @@
#define ATTR_IDX(x) ((x) << 2)
#define ATTR_IDX_MASK (7 << 2)
-#define PTE_ATTR_DEV 0
-#define PTE_ATTR_CI 1
-#define PTE_ATTR_WB 2
-#define PTE_ATTR_WT 3
-
+#define PTE_ATTR_DEV_NGNRNE 0
+#define PTE_ATTR_DEV_NGNRE 1
+#define PTE_ATTR_CI 2
+#define PTE_ATTR_WB 3
+#define PTE_ATTR_WT 4
#define SH_INNER 3
#define SH_OUTER 2