Update the ARM CPU ID information. The IDs aren't vendor/product

specific, they are specific to the ARM CPUs themselves.

ok bmercer@ jsg@ deraadt@

3 files changed, 56 insertions, 12 deletions

diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c
index 2adba2dcd64..e3f14e15e4e 100644
--- a/sys/arch/arm/arm/cpu.c
+++ b/sys/arch/arm/arm/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.14 2011/09/20 22:02:10 miod Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.15 2013/01/18 00:20:20 patrick Exp $	*/
 /*	$NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $	*/
 
 
@@ -296,11 +296,37 @@ const struct cpuidtab cpuids[] = {
 	{ CPU_ID_ARM1136JSR1,	CPU_CLASS_ARM11J,	"ARM1136J-S R1",
 	  generic_steppings },
 
-	{ CPU_ID_OMAP3430,	CPU_CLASS_ARMv7,	"ARM OMAP3[45]30",
+	{ CPU_ID_CORTEX_A5,	CPU_CLASS_ARMv7,	"ARM Cortex A5",
 	  generic_steppings },
-	{ CPU_ID_OMAP3530,	CPU_CLASS_ARMv7,	"ARM OMAP3530",
+	{ CPU_ID_CORTEX_A7,	CPU_CLASS_ARMv7,	"ARM Cortex A7",
 	  generic_steppings },
-	{ CPU_ID_OMAP3630,	CPU_CLASS_ARMv7,	"ARM OMAP3630/DM3730",
+	{ CPU_ID_CORTEX_A8,	CPU_CLASS_ARMv7,	"ARM Cortex A8",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A8,	CPU_CLASS_ARMv7,	"ARM Cortex A8",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A8_R1,	CPU_CLASS_ARMv7,	"ARM Cortex A8 R1",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A8_R2,	CPU_CLASS_ARMv7,	"ARM Cortex A8 R2",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A8_R3,	CPU_CLASS_ARMv7,	"ARM Cortex A8 R3",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A9,	CPU_CLASS_ARMv7,	"ARM Cortex A9",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A9_R1,	CPU_CLASS_ARMv7,	"ARM Cortex A9 R1",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A9_R2,	CPU_CLASS_ARMv7,	"ARM Cortex A9 R2",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A9_R3,	CPU_CLASS_ARMv7,	"ARM Cortex A9 R3",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A9_R4,	CPU_CLASS_ARMv7,	"ARM Cortex A9 R4",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A15,	CPU_CLASS_ARMv7,	"ARM Cortex A15",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A15_R1,	CPU_CLASS_ARMv7,	"ARM Cortex A15 R1",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A15_R2,	CPU_CLASS_ARMv7,	"ARM Cortex A15 R2",
+	  generic_steppings },
+	{ CPU_ID_CORTEX_A15_R3,	CPU_CLASS_ARMv7,	"ARM Cortex A15 R3",
 	  generic_steppings },
 
 
diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index bfaf97f001b..5eea5d48143 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.c,v 1.16 2011/11/08 17:06:51 deraadt Exp $	*/
+/*	$OpenBSD: cpufunc.c,v 1.17 2013/01/18 00:20:20 patrick Exp $	*/
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*
@@ -975,7 +975,11 @@ set_cpufuncs()
 	}
 #endif /* CPU_ARM11 */
 #ifdef CPU_ARMv7
-	if ((cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8) {
+	if ((cputype & CPU_ID_CORTEX_A5_MASK) == CPU_ID_CORTEX_A5 ||
+	    (cputype & CPU_ID_CORTEX_A7_MASK) == CPU_ID_CORTEX_A7 ||
+	    (cputype & CPU_ID_CORTEX_A8_MASK) == CPU_ID_CORTEX_A8 ||
+	    (cputype & CPU_ID_CORTEX_A9_MASK) == CPU_ID_CORTEX_A9 ||
+	    (cputype & CPU_ID_CORTEX_A15_MASK) == CPU_ID_CORTEX_A15) {
 		cpufuncs = armv7_cpufuncs;
 		cpu_reset_needs_v4_MMU_disable = 1;	/* V4 or higher */
 		arm_get_cachetype_cp15v7();
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index 50bccc49766..fa332675910 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: armreg.h,v 1.10 2011/09/20 22:02:13 miod Exp $	*/
+/*	$OpenBSD: armreg.h,v 1.11 2013/01/18 00:20:20 patrick Exp $	*/
 /*	$NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $	*/
 
 /*
@@ -200,12 +200,26 @@
 #define CPU_ID_IXP425_533	0x690541c0
 #define CPU_ID_IXP425_400	0x690541d0
 #define CPU_ID_IXP425_266	0x690541f0
+#define CPU_ID_CORTEX_A5	0x410fc050
+#define CPU_ID_CORTEX_A5_MASK	0xff0ffff0
+#define CPU_ID_CORTEX_A7	0x410fc070
+#define CPU_ID_CORTEX_A7_MASK	0xff0ffff0
+#define CPU_ID_CORTEX_A8_R1	0x411fc080
+#define CPU_ID_CORTEX_A8_R2	0x412fc080
+#define CPU_ID_CORTEX_A8_R3	0x413fc080
 #define CPU_ID_CORTEX_A8	0x410fc080
-#define CPU_ID_CORTEX_A8_MASK	0xff0fffe0
-#define CPU_ID_OMAP3430		0x411fc080
-#define CPU_ID_OMAP3530		0x411fc090      /* XXX */
-#define	CPU_ID_OMAP3630		0x413fc080
-
+#define CPU_ID_CORTEX_A8_MASK	0xff0ffff0
+#define CPU_ID_CORTEX_A9	0x410fc090
+#define CPU_ID_CORTEX_A9_R1	0x411fc090
+#define CPU_ID_CORTEX_A9_R2	0x412fc090
+#define CPU_ID_CORTEX_A9_R3	0x413fc090
+#define CPU_ID_CORTEX_A9_R4	0x414fc090
+#define CPU_ID_CORTEX_A9_MASK	0xff0ffff0
+#define CPU_ID_CORTEX_A15	0x410fc0f0
+#define CPU_ID_CORTEX_A15_R1	0x411fc0f0
+#define CPU_ID_CORTEX_A15_R2	0x412fc0f0
+#define CPU_ID_CORTEX_A15_R3	0x413fc0f0
+#define CPU_ID_CORTEX_A15_MASK	0xff0ffff0
 
 
 /* ARM3-specific coprocessor 15 registers */