None of the mainbus child devices care about getting a bus_space_tag_t from

its parent, because they know better; so don't bother providing one, which
allows more unused code to go to the Attic.

While there, redo the config machinery for mainbus child devices, to bring
it to our current standards. This also allows them to be disabled in UKC,
should there be a need for this in the future.

6 files changed, 22 insertions, 992 deletions

diff --git a/sys/arch/arm/arm/blockio.S b/sys/arch/arm/arm/blockio.S
deleted file mode 100644
index 590c3e6a7d4..00000000000
--- a/sys/arch/arm/arm/blockio.S
+++ /dev/null
@@ -1,588 +0,0 @@
-/*	$OpenBSD: blockio.S,v 1.1 2004/02/01 05:09:48 drahn Exp $	*/
-/*	$NetBSD: blockio.S,v 1.5 2002/08/15 01:38:16 briggs Exp $	*/
-
-/*
- * Copyright (c) 2001 Ben Harris.
- * Copyright (c) 1994 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * blockio.S
- *
- * optimised block read/write from/to IO routines.
- *
- * Created      : 08/10/94
- * Modified	: 22/01/99  -- R.Earnshaw
- *			       Faster, and small tweaks for StrongARM 	
- */
-
-#include <machine/asm.h>
-
-RCSID("$NetBSD: blockio.S,v 1.4 2001/06/02 11:15:56 bjh21 Exp $")
-
-/*
- * Read bytes from an I/O address into a block of memory
- *
- * r0 = address to read from (IO)
- * r1 = address to write to (memory)
- * r2 = length
- */
-
-/* This code will look very familiar if you've read _memcpy(). */
-ENTRY(read_multi_1)
-	mov	ip, sp
-	stmfd	sp!, {fp, ip, lr, pc}
-	sub	fp, ip, #4
-	subs	r2, r2, #4		/* r2 = length - 4 */
-	blt	.Lrm1_l4			/* less than 4 bytes */
-	ands	r12, r1, #3
-	beq	.Lrm1_main		/* aligned destination */
-	rsb	r12, r12, #4
-	cmp	r12, #2
-	ldrb	r3, [r0]
-	strb	r3, [r1], #1
-	ldrgeb	r3, [r0]
-	strgeb	r3, [r1], #1
-	ldrgtb	r3, [r0]
-	strgtb	r3, [r1], #1
-	subs	r2, r2, r12
-	blt	.Lrm1_l4
-.Lrm1_main:
-.Lrm1loop:
-	ldrb	r3, [r0]
-	ldrb	r12, [r0]
-	orr	r3, r3, r12, lsl #8
-	ldrb	r12, [r0]
-	orr	r3, r3, r12, lsl #16
-	ldrb	r12, [r0]
-	orr	r3, r3, r12, lsl #24
-	str	r3, [r1], #4
-	subs	r2, r2, #4
-	bge	.Lrm1loop
-.Lrm1_l4:
-	adds	r2, r2, #4			/* r2 = length again */
-	ldmeqdb	fp, {fp, sp, pc}
-	moveq	pc, r14
-	cmp	r2, #2
-	ldrb	r3, [r0]
-	strb	r3, [r1], #1
-	ldrgeb	r3, [r0]
-	strgeb	r3, [r1], #1
-	ldrgtb	r3, [r0]
-	strgtb	r3, [r1], #1
-	ldmdb	fp, {fp, sp, pc}
-
-/*
- * Write bytes to an I/O address from a block of memory
- *
- * r0 = address to write to (IO)
- * r1 = address to read from (memory)
- * r2 = length
- */
-
-/* This code will look very familiar if you've read _memcpy(). */
-ENTRY(write_multi_1)
-	mov	ip, sp
-	stmfd	sp!, {fp, ip, lr, pc}
-	sub	fp, ip, #4
-	subs	r2, r2, #4		/* r2 = length - 4 */
-	blt	.Lwm1_l4		/* less than 4 bytes */
-	ands	r12, r1, #3
-	beq	.Lwm1_main		/* aligned source */
-	rsb	r12, r12, #4
-	cmp	r12, #2
-	ldrb	r3, [r1], #1
-	strb	r3, [r0]
-	ldrgeb	r3, [r1], #1
-	strgeb	r3, [r0]
-	ldrgtb	r3, [r1], #1
-	strgtb	r3, [r0]
-	subs	r2, r2, r12
-	blt	.Lwm1_l4
-.Lwm1_main:
-.Lwm1loop:
-	ldr	r3, [r1], #4
-	strb	r3, [r0]
-	mov	r3, r3, lsr #8
-	strb	r3, [r0]
-	mov	r3, r3, lsr #8
-	strb	r3, [r0]
-	mov	r3, r3, lsr #8
-	strb	r3, [r0]
-	subs	r2, r2, #4
-	bge	.Lwm1loop
-.Lwm1_l4:
-	adds	r2, r2, #4			/* r2 = length again */
-	ldmeqdb	fp, {fp, sp, pc}
-	cmp	r2, #2
-	ldrb	r3, [r1], #1
-	strb	r3, [r0]
-	ldrgeb	r3, [r1], #1
-	strgeb	r3, [r0]
-	ldrgtb	r3, [r1], #1
-	strgtb	r3, [r0]
-	ldmdb	fp, {fp, sp, pc}
-
-/*
- * Reads short ints (16 bits) from an I/O address into a block of memory
- *
- * r0 = address to read from (IO)
- * r1 = address to write to (memory)
- * r2 = length
- */
-
-ENTRY(insw)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address and the size is word aligned, do it fast */
-
-	tst	r2, #0x00000001
-	tsteq	r1, #0x00000003
-	beq	.Lfastinsw
-
-/* Non aligned insw */
-
-.Linswloop:
-	ldr	r3, [r0]
-	subs	r2, r2, #0x00000001	/* Loop test in load delay slot */
-	strb	r3, [r1], #0x0001
-	mov	r3, r3, lsr #8
-	strb	r3, [r1], #0x0001
-	bgt	.Linswloop
-
-	mov	pc, lr
-
-/* Word aligned insw */
-
-.Lfastinsw:
-
-.Lfastinswloop:
-	ldr	r3, [r0, #0x0002]	/* take advantage of nonaligned
-					 * word accesses */
-	ldr	ip, [r0]
-	mov	r3, r3, lsr #16		/* Put the two shorts together */
-	orr	r3, r3, ip, lsl #16
-	str	r3, [r1], #0x0004	/* Store */
-	subs	r2, r2, #0x00000002	/* Next */
-	bgt	.Lfastinswloop
-
-	mov	pc, lr
-
-
-/*
- * Writes short ints (16 bits) from a block of memory to an I/O address
- *
- * r0 = address to write to (IO)
- * r1 = address to read from (memory)
- * r2 = length
- */
-
-ENTRY(outsw)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address and the size is word aligned, do it fast */
-
-	tst	r2, #0x00000001
-	tsteq	r1, #0x00000003
-	beq	.Lfastoutsw
-
-/* Non aligned outsw */
-
-.Loutswloop:
-	ldrb	r3, [r1], #0x0001
-	ldrb	ip, [r1], #0x0001
-	subs	r2, r2, #0x00000001	/* Loop test in load delay slot */
-	orr	r3, r3, ip, lsl #8
-	orr	r3, r3, r3, lsl #16
-	str	r3, [r0]
-	bgt	.Loutswloop
-
-	mov	pc, lr
-
-/* Word aligned outsw */
-
-.Lfastoutsw:
-
-.Lfastoutswloop:
-	ldr	r3, [r1], #0x0004	/* r3 = (H)(L) */
-	subs	r2, r2, #0x00000002	/* Loop test in load delay slot */
-
-	eor	ip, r3, r3, lsr #16	/* ip = (H)(H^L) */
-	eor	r3, r3, ip, lsl #16	/* r3 = (H^H^L)(L) = (L)(L) */
-	eor	ip, ip, r3, lsr #16	/* ip = (H)(H^L^L) = (H)(H) */
-
-	str	r3, [r0]
-	str	ip, [r0]
-	
-/*	mov	ip, r3, lsl #16
- *	orr	ip, ip, ip, lsr #16
- *	str	ip, [r0]
- *
- *	mov	ip, r3, lsr #16
- *	orr	ip, ip, ip, lsl #16
- *	str	ip, [r0]
- */
-
-	bgt	.Lfastoutswloop
-
-	mov	pc, lr
-
-/*
- * reads short ints (16 bits) from an I/O address into a block of memory
- * with a length garenteed to be a multiple of 16 bytes
- * with a word aligned destination address
- *
- * r0 = address to read from (IO)
- * r1 = address to write to (memory)
- * r2 = length
- */
-
-ENTRY(insw16)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address is word aligned and the size suitably
-   aligned, do it fast */
-
-	tst	r2, #0x00000007
-	tsteq	r1, #0x00000003
-
-	bne	_C_LABEL(insw)
-
-/* Word aligned insw */
-
-	stmfd	sp!, {r4,r5,lr}
-
-.Linsw16loop:
-	ldr	r3, [r0, #0x0002]	/* take advantage of nonaligned
-					 * word accesses */
-	ldr	lr, [r0]
-	mov	r3, r3, lsr #16		/* Put the two shorts together */
-	orr	r3, r3, lr, lsl #16
-
-	ldr	r4, [r0, #0x0002]	/* take advantage of nonaligned
-					 * word accesses */
-	ldr	lr, [r0]
-	mov	r4, r4, lsr #16		/* Put the two shorts together */
-	orr	r4, r4, lr, lsl #16
-
-	ldr	r5, [r0, #0x0002]	/* take advantage of nonaligned
-					 * word accesses */
-	ldr	lr, [r0]
-	mov	r5, r5, lsr #16		/* Put the two shorts together */
-	orr	r5, r5, lr, lsl #16
-
-	ldr	ip, [r0, #0x0002]	/* take advantage of nonaligned
-					 * word accesses */
-	ldr	lr, [r0]
-	mov	ip, ip, lsr #16		/* Put the two shorts together */
-	orr	ip, ip, lr, lsl #16
-
-	stmia	r1!, {r3-r5,ip}
-	subs	r2, r2, #0x00000008	/* Next */
-	bgt	.Linsw16loop
-
-	ldmfd	sp!, {r4,r5,pc}		/* Restore regs and go home */
-
-
-/*
- * Writes short ints (16 bits) from a block of memory to an I/O address
- *
- * r0 = address to write to (IO)
- * r1 = address to read from (memory)
- * r2 = length
- */
-
-ENTRY(outsw16)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address is word aligned and the size suitably
-   aligned, do it fast */
-
-	tst	r2, #0x00000007
-	tsteq	r1, #0x00000003
-
-	bne	_C_LABEL(outsw)
-
-/* Word aligned outsw */
-
-	stmfd	sp!, {r4,r5,lr}
-
-.Loutsw16loop:
-	ldmia	r1!, {r4,r5,ip,lr}
-
-	eor	r3, r4, r4, lsl #16	/* r3 = (A^B)(B) */
-	eor	r4, r4, r3, lsr #16	/* r4 = (A)(B^A^B) = (A)(A) */
-	eor	r3, r3, r4, lsl #16	/* r3 = (A^B^A)(B) = (B)(B) */
-	str	r3, [r0]
-	str	r4, [r0]
-	
-/*	mov	r3, r4, lsl #16
- *	orr	r3, r3, r3, lsr #16
- *	str	r3, [r0]
- *
- *	mov	r3, r4, lsr #16
- *	orr	r3, r3, r3, lsl #16
- *	str	r3, [r0]
- */
-
-	eor	r3, r5, r5, lsl #16	/* r3 = (A^B)(B) */
-	eor	r5, r5, r3, lsr #16	/* r4 = (A)(B^A^B) = (A)(A) */
-	eor	r3, r3, r5, lsl #16	/* r3 = (A^B^A)(B) = (B)(B) */
-	str	r3, [r0]
-	str	r5, [r0]
-
-	eor	r3, ip, ip, lsl #16	/* r3 = (A^B)(B) */
-	eor	ip, ip, r3, lsr #16	/* r4 = (A)(B^A^B) = (A)(A) */
-	eor	r3, r3, ip, lsl #16	/* r3 = (A^B^A)(B) = (B)(B) */
-	str	r3, [r0]
-	str	ip, [r0]
-
-	eor	r3, lr, lr, lsl #16	/* r3 = (A^B)(B) */
-	eor	lr, lr, r3, lsr #16	/* r4 = (A)(B^A^B) = (A)(A) */
-	eor	r3, r3, lr, lsl #16	/* r3 = (A^B^A)(B) = (B)(B) */
-	str	r3, [r0]
-	str	lr, [r0]
-
-	subs	r2, r2, #0x00000008
-	bgt	.Loutsw16loop
-
-	ldmfd	sp!, {r4,r5,pc}		/* and go home */
-
-/*
- * reads short ints (16 bits) from an I/O address into a block of memory
- * The I/O address is assumed to be mapped multiple times in a block of
- * 8 words.
- * The destination address should be word aligned.
- *
- * r0 = address to read from (IO)
- * r1 = address to write to (memory)
- * r2 = length
- */
-
-ENTRY(inswm8)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address is word aligned and the size suitably
-   aligned, do it fast */
-
-	tst	r1, #0x00000003
-
-	bne	_C_LABEL(insw)
-
-/* Word aligned insw */
-
-	stmfd	sp!, {r4-r9,lr}
-
-	mov	lr, #0xff000000
-	orr	lr, lr, #0x00ff0000
-
-.Linswm8_loop8:
-	cmp	r2, #8
-	bcc	.Linswm8_l8
-
-	ldmia	r0, {r3-r9,ip}
-
-	bic	r3, r3, lr
-	orr	r3, r3, r4, lsl #16
-	bic	r5, r5, lr
-	orr	r4, r5, r6, lsl #16
-	bic	r7, r7, lr
-	orr	r5, r7, r8, lsl #16
-	bic	r9, r9, lr
-	orr	r6, r9, ip, lsl #16
-
-	stmia	r1!, {r3-r6}
-
-	subs	r2, r2, #0x00000008	/* Next */
-	bne	.Linswm8_loop8
-	beq	.Linswm8_l1
-
-.Linswm8_l8:
-	cmp	r2, #4
-	bcc	.Linswm8_l4
-
-	ldmia	r0, {r3-r6}
-
-	bic	r3, r3, lr
-	orr	r3, r3, r4, lsl #16
-	bic	r5, r5, lr
-	orr	r4, r5, r6, lsl #16
-
-	stmia	r1!, {r3-r4}
-
-	subs	r2, r2, #0x00000004
-	beq	.Linswm8_l1
-
-.Linswm8_l4:
-	cmp	r2, #2
-	bcc	.Linswm8_l2
-
-	ldmia	r0, {r3-r4}
-
-	bic	r3, r3, lr
-	orr	r3, r3, r4, lsl #16
-	str	r3, [r1], #0x0004
-
-	subs	r2, r2, #0x00000002
-	beq	.Linswm8_l1
-
-.Linswm8_l2:
-	cmp	r2, #1
-	bcc	.Linswm8_l1
-
-	ldr	r3, [r0]
-	subs	r2, r2, #0x00000001	/* Test in load delay slot */
-					/* XXX, why don't we use result?  */
-
-	strb	r3, [r1], #0x0001
-	mov	r3, r3, lsr #8
-	strb	r3, [r1], #0x0001
-
-
-.Linswm8_l1:
-	ldmfd	sp!, {r4-r9,pc}		/* And go home */
-
-/*
- * write short ints (16 bits) to an I/O address from a block of memory
- * The I/O address is assumed to be mapped multiple times in a block of
- * 8 words.
- * The source address should be word aligned.
- *
- * r0 = address to read to (IO)
- * r1 = address to write from (memory)
- * r2 = length
- */
-
-ENTRY(outswm8)
-/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-/* If the destination address is word aligned and the size suitably
-   aligned, do it fast */
-
-	tst	r1, #0x00000003
-
-	bne	_C_LABEL(outsw)
-
-/* Word aligned outsw */
-
-	stmfd	sp!, {r4-r8,lr}
-
-.Loutswm8_loop8:
-	cmp	r2, #8
-	bcc	.Loutswm8_l8
-
-	ldmia	r1!, {r3,r5,r7,ip}
-
-	eor	r4, r3, r3, lsr #16	/* r4 = (A)(A^B) */
-	eor	r3, r3, r4, lsl #16	/* r3 = (A^A^B)(B) = (B)(B) */
-	eor	r4, r4, r3, lsr #16	/* r4 = (A)(B^A^B) = (A)(A) */
-
-	eor	r6, r5, r5, lsr #16	/* r6 = (A)(A^B) */
-	eor	r5, r5, r6, lsl #16	/* r5 = (A^A^B)(B) = (B)(B) */
-	eor	r6, r6, r5, lsr #16	/* r6 = (A)(B^A^B) = (A)(A) */
-
-	eor	r8, r7, r7, lsr #16	/* r8 = (A)(A^B) */
-	eor	r7, r7, r8, lsl #16	/* r7 = (A^A^B)(B) = (B)(B) */
-	eor	r8, r8, r7, lsr #16	/* r8 = (A)(B^A^B) = (A)(A) */
-
-	eor	lr, ip, ip, lsr #16	/* lr = (A)(A^B) */
-	eor	ip, ip, lr, lsl #16	/* ip = (A^A^B)(B) = (B)(B) */
-	eor	lr, lr, ip, lsr #16	/* lr = (A)(B^A^B) = (A)(A) */
-
-	stmia	r0, {r3-r8,ip,lr}
-
-	subs	r2, r2, #0x00000008	/* Next */
-	bne	.Loutswm8_loop8
-	beq	.Loutswm8_l1
-
-.Loutswm8_l8:
-	cmp	r2, #4
-	bcc	.Loutswm8_l4
-
-	ldmia	r1!, {r3-r4}
-
-	eor	r6, r3, r3, lsr #16	/* r6 = (A)(A^B) */
-	eor	r5, r3, r6, lsl #16	/* r5 = (A^A^B)(B) = (B)(B) */
-	eor	r6, r6, r5, lsr #16	/* r6 = (A)(B^A^B) = (A)(A) */
-
-	eor	r8, r4, r4, lsr #16	/* r8 = (A)(A^B) */
-	eor	r7, r4, r8, lsl #16	/* r7 = (A^A^B)(B) = (B)(B) */
-	eor	r8, r8, r7, lsr #16	/* r8 = (A)(B^A^B) = (A)(A) */
-
-	stmia	r0, {r5-r8}
-
-	subs	r2, r2, #0x00000004
-	beq	.Loutswm8_l1
-
-.Loutswm8_l4:
-	cmp	r2, #2
-	bcc	.Loutswm8_l2
-
-	ldr	r3, [r1], #0x0004	/* r3 = (A)(B) */
-	subs	r2, r2, #0x00000002	/* Done test in Load delay slot */
-
-	eor	r5, r3, r3, lsr #16	/* r5 = (A)(A^B)*/
-	eor	r4, r3, r5, lsl #16	/* r4 = (A^A^B)(B) = (B)(B) */
-	eor	r5, r5, r4, lsr #16	/* r5 = (A)(B^A^B) = (A)(A) */
-
-	stmia	r0, {r4, r5}
-
-	beq	.Loutswm8_l1
-
-.Loutswm8_l2:
-	cmp	r2, #1
-	bcc	.Loutswm8_l1
-
-	ldrb	r3, [r1], #0x0001
-	ldrb	r4, [r1], #0x0001
-	subs	r2, r2, #0x00000001	/* Done test in load delay slot */
-					/* XXX This test isn't used?  */
-	orr	r3, r3, r4, lsl #8
-	orr	r3, r3, r3, lsl #16
-	str	r3, [r0]
-
-.Loutswm8_l1:
-	ldmfd	sp!, {r4-r8,pc}		/* And go home */
diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm
index 38e4dc3d0d4..7f8359560b7 100644
--- a/sys/arch/arm/conf/files.arm
+++ b/sys/arch/arm/conf/files.arm
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.arm,v 1.17 2011/09/20 22:02:12 miod Exp $
+#	$OpenBSD: files.arm,v 1.18 2011/09/22 17:45:59 miod Exp $
 #	$NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $
 
 # generic networking files
@@ -16,11 +16,9 @@ file	arch/arm/arm/fiq.c			fiq
 file	arch/arm/arm/fiq_subr.S			fiq
 
 # mainbus files
-device	mainbus {[base = -1], [dack = -1], [irq = -1]}
+device	mainbus {}
 attach	mainbus at root
 file	arch/arm/mainbus/mainbus.c		mainbus
-file	arch/arm/mainbus/mainbus_io.c		mainbus
-file	arch/arm/mainbus/mainbus_io_asm.S	mainbus
 
 device	cpu {}
 attach	cpu at mainbus with cpu_mainbus
@@ -37,7 +35,6 @@ file	arch/arm/arm/bus_space_notimpl.S
 file	arch/arm/arm/arm_machdep.c
 file	arch/arm/arm/ast.c
 file	arch/arm/arm/bcopyinout.S
-file	arch/arm/arm/blockio.S
 file	arch/arm/arm/compat_13_machdep.c	compat_13
 file	arch/arm/arm/copystr.S
 file	arch/arm/arm/cpufunc.c
diff --git a/sys/arch/arm/mainbus/mainbus.c b/sys/arch/arm/mainbus/mainbus.c
index 8f2a1e9f1b1..d50219f78b1 100644
--- a/sys/arch/arm/mainbus/mainbus.c
+++ b/sys/arch/arm/mainbus/mainbus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mainbus.c,v 1.5 2010/08/30 21:35:57 deraadt Exp $	*/
+/*	$OpenBSD: mainbus.c,v 1.6 2011/09/22 17:45:59 miod Exp $	*/
 /* $NetBSD: mainbus.c,v 1.3 2001/06/13 17:52:43 nathanw Exp $ */
 
 /*
@@ -45,27 +45,16 @@
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
-#include <sys/conf.h>
-#include <sys/malloc.h>
 #include <sys/device.h>
 
-#include <machine/bus.h>
 #include <arm/mainbus/mainbus.h>
 
-/*
- * mainbus is a root device so we a bus space tag to pass to children
- *
- * The tag is provided by mainbus_io.c and mainbus_io_asm.S
- */
-
-extern struct bus_space mainbus_bs_tag;
-
 /* Prototypes for functions provided */
 
-int  mainbusmatch  (struct device *, void *, void *);
-void mainbusattach (struct device *, struct device *, void *);
-int  mainbusprint  (void *aux, const char *mainbus);
-int mainbussearch (struct device *,  void *, void *);
+int  mainbusmatch(struct device *, void *, void *);
+void mainbusattach(struct device *, struct device *, void *);
+int  mainbusprint(void *aux, const char *mainbus);
+int mainbussearch(struct device *,  void *, void *);
 
 /* attach and device structures for the device */
 
@@ -80,8 +69,6 @@ struct cfdriver mainbus_cd = {
 
 /*
  * int mainbusmatch(struct device *parent, struct cfdata *cf, void *aux)
- *
- * Always match for unit 0
  */
 
 int
@@ -101,21 +88,22 @@ mainbusattach(struct device *parent, struct device *self, void *aux)
 {
 	printf("\n");
 
-	config_search(mainbussearch, self, self);
+	config_search(mainbussearch, self, aux);
 }
 
 int
-mainbussearch(struct device *parent, void *c, void *aux)
+mainbussearch(struct device *parent, void *vcf, void *aux)
 {
 	struct mainbus_attach_args ma;
-	struct cfdata *cf = c;
-
+	struct cfdata *cf = vcf;
 
-	ma.ma_iot = &mainbus_bs_tag;
 	ma.ma_name = cf->cf_driver->cd_name;
 
-	config_found(parent, &ma, mainbusprint);
+	/* allow for devices to be disabled in UKC */
+	if ((*cf->cf_attach->ca_match)(parent, cf, &ma) == 0)
+		return 0;
 
+	config_attach(parent, cf, &ma, mainbusprint);
 	return 1;
 }
 
@@ -128,6 +116,10 @@ mainbussearch(struct device *parent, void *c, void *aux)
 int
 mainbusprint(void *aux, const char *mainbus)
 {
-/* XXXX print flags */
-	return (QUIET);
+	struct mainbus_attach_args *ma = aux;
+
+	if (mainbus != NULL)
+		printf("%s at %s", ma->ma_name, mainbus);
+
+	return (UNCONF);
 }
diff --git a/sys/arch/arm/mainbus/mainbus.h b/sys/arch/arm/mainbus/mainbus.h
index 11fa23ecba8..3e1799628de 100644
--- a/sys/arch/arm/mainbus/mainbus.h
+++ b/sys/arch/arm/mainbus/mainbus.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mainbus.h,v 1.1 2004/02/01 05:09:49 drahn Exp $	*/
+/*	$OpenBSD: mainbus.h,v 1.2 2011/09/22 17:45:59 miod Exp $	*/
 /* $NetBSD: mainbus.h,v 1.1 2001/02/24 19:38:02 reinoud Exp $ */
 
 /*
@@ -42,20 +42,10 @@
  * Created      : 15/12/94
  */
 
-#include <machine/bus.h>
-
 /*
  * mainbus driver attach arguments
  */
 
 struct mainbus_attach_args {
-	u_int		ma_iobase;	/* base i/o address */
-	int		ma_iosize;	/* span of ports used */
-	int		ma_irq;		/* interrupt request */
-	int		ma_drq;		/* DMA request */
-	void		*ma_aux;	/* driver specific */
-	bus_space_tag_t	ma_iot;		/* bus space tag */
-	char		*ma_name;
+	const char	*ma_name;
 };
-
-/* End of mainbus.h */
diff --git a/sys/arch/arm/mainbus/mainbus_io.c b/sys/arch/arm/mainbus/mainbus_io.c
deleted file mode 100644
index 6519ce9bd60..00000000000
--- a/sys/arch/arm/mainbus/mainbus_io.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*	$OpenBSD: mainbus_io.c,v 1.5 2010/12/26 15:40:59 miod Exp $ */
-/*	$NetBSD: mainbus_io.c,v 1.14 2003/12/06 22:05:33 bjh21 Exp $	*/
-
-/*
- * Copyright (c) 1997 Mark Brinicombe.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Mark Brinicombe.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * bus_space I/O functions for mainbus
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/queue.h>
-
-#include <uvm/uvm.h>
-
-#include <machine/bus.h>
-#include <machine/pmap.h>
-
-/* Prototypes for all the bus_space structure functions */
-
-bs_protos(mainbus);
-bs_protos(bs_notimpl);
-
-/* Declare the mainbus bus space tag */
-
-struct bus_space mainbus_bs_tag = {
-	/* cookie */
-	NULL,
-
-	/* mapping/unmapping */
-	mainbus_bs_map,
-	mainbus_bs_unmap,
-	mainbus_bs_subregion,
-
-	/* allocation/deallocation */
-	mainbus_bs_alloc,
-	mainbus_bs_free,
-
-	/* get kernel virtual address */
-	0, /* there is no linear mapping */
-
-	/* Mmap bus space for user */
-	mainbus_bs_mmap,
-
-	/* barrier */
-	mainbus_bs_barrier,
-
-	/* read (single) */
-	mainbus_bs_r_1,
-	mainbus_bs_r_2,
-	mainbus_bs_r_4,
-	bs_notimpl_bs_r_8,
-
-	/* read multiple */
-	bs_notimpl_bs_rm_1,
-	mainbus_bs_rm_2,
-	bs_notimpl_bs_rm_4,
-	bs_notimpl_bs_rm_8,
-
-	/* read region */
-	bs_notimpl_bs_rr_1,
-	bs_notimpl_bs_rr_2,
-	bs_notimpl_bs_rr_4,
-	bs_notimpl_bs_rr_8,
-
-	/* write (single) */
-	mainbus_bs_w_1,
-	mainbus_bs_w_2,
-	mainbus_bs_w_4,
-	bs_notimpl_bs_w_8,
-
-	/* write multiple */
-	mainbus_bs_wm_1,
-	mainbus_bs_wm_2,
-	bs_notimpl_bs_wm_4,
-	bs_notimpl_bs_wm_8,
-
-	/* write region */
-	bs_notimpl_bs_wr_1,
-	bs_notimpl_bs_wr_2,
-	bs_notimpl_bs_wr_4,
-	bs_notimpl_bs_wr_8,
-
-	bs_notimpl_bs_sm_1,
-	bs_notimpl_bs_sm_2,
-	bs_notimpl_bs_sm_4,
-	bs_notimpl_bs_sm_8,
-
-	/* set region */
-	bs_notimpl_bs_sr_1,
-	bs_notimpl_bs_sr_2,
-	bs_notimpl_bs_sr_4,
-	bs_notimpl_bs_sr_8,
-
-	/* copy */
-	bs_notimpl_bs_c_1,
-	bs_notimpl_bs_c_2,
-	bs_notimpl_bs_c_4,
-	bs_notimpl_bs_c_8,
-};
-
-/* bus space functions */
-
-int
-mainbus_bs_map(t, bpa, size, flags, bshp)
-	void *t;
-	bus_addr_t bpa;
-	bus_size_t size;
-	int flags;
-	bus_space_handle_t *bshp;
-{
-	u_long startpa, endpa, pa;
-	vaddr_t va;
-	pt_entry_t *pte;
-
-	if ((u_long)bpa > (u_long)KERNEL_BASE) {
-		/* XXX This is a temporary hack to aid transition. */
-		*bshp = bpa;
-		return(0);
-	}
-
-	startpa = trunc_page(bpa);
-	endpa = round_page(bpa + size);
-
-	/* XXX use extent manager to check duplicate mapping */
-
-	va = uvm_km_valloc(kernel_map, endpa - startpa);
-	if (! va)
-		return(ENOMEM);
-
-	*bshp = (bus_space_handle_t)(va + (bpa - startpa));
-
-	for(pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
-		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
-		if ((flags & BUS_SPACE_MAP_CACHEABLE) == 0) {
-			pte = vtopte(va);
-			*pte &= ~L2_S_CACHE_MASK;
-			PTE_SYNC(pte);
-		}
-	}
-	pmap_update(pmap_kernel());
-
-	return(0);
-}
-
-int
-mainbus_bs_alloc(t, rstart, rend, size, alignment, boundary, flags,
-    bpap, bshp)
-	void *t;
-	bus_addr_t rstart, rend;
-	bus_size_t size, alignment, boundary;
-	int flags;
-	bus_addr_t *bpap;
-	bus_space_handle_t *bshp;
-{
-	panic("mainbus_bs_alloc(): Help!");
-}
-
-
-void
-mainbus_bs_unmap(t, bsh, size)
-	void *t;
-	bus_space_handle_t bsh;
-	bus_size_t size;
-{
-	/*
-	 * Temporary implementation
-	 */
-}
-
-void    
-mainbus_bs_free(t, bsh, size)
-	void *t;
-	bus_space_handle_t bsh;
-	bus_size_t size;
-{
-
-	panic("mainbus_bs_free(): Help!");
-	/* mainbus_bs_unmap() does all that we need to do. */
-/*	mainbus_bs_unmap(t, bsh, size);*/
-}
-
-int
-mainbus_bs_subregion(t, bsh, offset, size, nbshp)
-	void *t;
-	bus_space_handle_t bsh;
-	bus_size_t offset, size;
-	bus_space_handle_t *nbshp;
-{
-
-	*nbshp = bsh + (offset << 2);
-	return (0);
-}
-
-paddr_t
-mainbus_bs_mmap(t, paddr, offset, prot, flags)
-	void *t;
-	bus_addr_t paddr;
-	off_t offset;
-	int prot;
-	int flags;
-{
-	/*
-	 * mmap from address `paddr+offset' for one page
-	 */
-	 return (paddr + offset);
-}
-
-void
-mainbus_bs_barrier(t, bsh, offset, len, flags)
-	void *t;
-	bus_space_handle_t bsh;
-	bus_size_t offset, len;
-	int flags;
-{
-}	
-
-/* End of mainbus_io.c */
diff --git a/sys/arch/arm/mainbus/mainbus_io_asm.S b/sys/arch/arm/mainbus/mainbus_io_asm.S
deleted file mode 100644
index af052ad3513..00000000000
--- a/sys/arch/arm/mainbus/mainbus_io_asm.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/*	$OpenBSD: mainbus_io_asm.S,v 1.1 2004/02/01 05:09:49 drahn Exp $	*/
-/*	$NetBSD: mainbus_io_asm.S,v 1.1 2001/02/24 19:38:02 reinoud Exp $	*/
-
-/*
- * Copyright (c) 1997 Mark Brinicombe.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Mark Brinicombe.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <machine/asm.h>
-
-/*
- * bus_space I/O functions for mainbus
- */
-
-
-/*
- * read single
- */
-
-ENTRY(mainbus_bs_r_1)
-	ldrb	r0, [r1, r2, lsl #2]
-	mov	pc, lr
-
-ENTRY(mainbus_bs_r_2)
-	ldr	r0, [r1, r2, lsl #2]
-	bic	r0, r0, #0xff000000
-	bic	r0, r0, #0x00ff0000
-	mov	pc, lr
-
-ENTRY(mainbus_bs_r_4)
-	ldr	r0, [r1, r2, lsl #2]
-	mov	pc, lr
-
-/*
- * write single
- */
-
-ENTRY(mainbus_bs_w_1)
-	strb	r3, [r1, r2, lsl #2]
-	mov	pc, lr
-
-ENTRY(mainbus_bs_w_2)
-	mov	r3, r3, lsl #16
-	orr	r3, r3, r3, lsr #16
-	str	r3, [r1, r2, lsl #2]
-	mov	pc, lr
-
-ENTRY(mainbus_bs_w_4)
-	str	r3, [r1, r2, lsl #2]
-	mov	pc, lr
-
-/*
- * read multiple
- */
-
-ENTRY(mainbus_bs_rm_2)
-	add	r0, r1, r2, lsl #2
-	mov	r1, r3
-	ldr	r2, [sp, #0]
-	b	_C_LABEL(insw16)
-
-/*
- * write multiple
- */
-
-ENTRY(mainbus_bs_wm_1)
-	add	r0, r1, r2, lsl #2
-	ldr	r2, [sp, #0]
-
-	/* Make sure that we have a positive length */
-	cmp	r2, #0x00000000
-	movle	pc, lr
-
-mainbus_wm_1_loop:
-	ldrb	r1, [r3], #0x0001
-	str	r1, [r0]
-	subs	r2, r2, #0x00000001
-	bgt	mainbus_wm_1_loop
-
-	mov	pc, lr
-
-ENTRY(mainbus_bs_wm_2)
-	add	r0, r1, r2, lsl #2
-	mov	r1, r3
-	ldr	r2, [sp, #0]
-	b	_C_LABEL(outsw16)