I2C support for 80321/80219

5 files changed, 540 insertions, 1 deletions

diff --git a/sys/arch/arm/xscale/files.i80321 b/sys/arch/arm/xscale/files.i80321
index cd18fb66d7d..0f2032f6fc4 100644
--- a/sys/arch/arm/xscale/files.i80321
+++ b/sys/arch/arm/xscale/files.i80321
@@ -1,4 +1,4 @@
-# $OpenBSD: files.i80321,v 1.1 2006/05/29 17:01:42 drahn Exp $
+# $OpenBSD: files.i80321,v 1.2 2006/06/10 03:51:50 drahn Exp $
 device  iopxs {}: pcibus, bus_space_generic, gpiobus
 file	arch/arm/xscale/i80321_space.c			iopxs
 file	arch/arm/xscale/i80321_mcu.c			iopxs
@@ -7,3 +7,9 @@ file	arch/arm/xscale/i80321_pci.c			iopxs
 
 file	arch/arm/xscale/i80321_intr.c			iopxs
 file	arch/arm/xscale/i80321_timer.c			iopxs
+
+# I2C controller unit
+device	iopiic: i2cbus
+attach	iopiic at iopxs with i80321_i2c
+file	arch/arm/xscale/i80321_i2c.c			iopiic
+file	arch/arm/xscale/iopi2c.c			iopiic
diff --git a/sys/arch/arm/xscale/i80321_i2c.c b/sys/arch/arm/xscale/i80321_i2c.c
new file mode 100644
index 00000000000..5c6dad1e981
--- /dev/null
+++ b/sys/arch/arm/xscale/i80321_i2c.c
@@ -0,0 +1,135 @@
+/*	$NetBSD: i80321_i2c.c,v 1.2 2005/12/11 12:16:51 christos Exp $	*/
+
+/*
+ * Copyright (c) 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Intel i80321 I/O Processor I2C Controller Unit support.
+ */
+
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <arm/xscale/i80321reg.h>
+#include <arm/xscale/i80321var.h>
+
+#include <dev/i2c/i2cvar.h>
+
+#include <arm/xscale/iopi2creg.h>
+#include <arm/xscale/iopi2cvar.h>
+
+int i80321_i2c_match(struct device *parent, void *v, void *aux);
+void i80321_i2c_attach(struct device *parent, struct device *self, void *aux);
+
+struct cfattach i80321_i2c_ca = {
+	sizeof(struct iopiic_softc), i80321_i2c_match, i80321_i2c_attach
+};
+        
+int
+i80321_i2c_match(struct device *parent, void *v, void *aux)
+{
+	struct cfdata *cf = v;
+	struct iopxs_attach_args *ia = aux;
+
+	/* XXX thecus will reboot if iopiic1 attaches */
+	if (ia->ia_offset == VERDE_I2C_BASE1)
+		return 0;
+
+	if (strcmp(cf->cf_driver->cd_name, ia->ia_name) == 0)
+		return (1);
+
+	return (0);
+}
+
+void
+i80321_i2c_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct iopiic_softc *sc = (void *) self;
+	struct iopxs_attach_args *ia = aux;
+	int error;
+#ifdef LATER
+	uint8_t gpio_bits;
+#endif
+
+	printf(": I2C controller\n");
+
+	sc->sc_st = ia->ia_st;
+	if ((error = bus_space_subregion(sc->sc_st, ia->ia_sh,
+					 ia->ia_offset, ia->ia_size,
+					 &sc->sc_sh)) != 0) {
+		printf("%s: unable to subregion registers, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		return;
+	}
+
+#ifdef LATER
+	gpio_bits = (ia->ia_offset == VERDE_I2C_BASE0) ?
+	    (1U << 7) | (1U << 6) : (1U << 5) | (1U << 4);
+	i80321_gpio_set_val(gpio_bits, 0);
+	i80321_gpio_set_direction(gpio_bits, 0);
+#endif
+
+	/* XXX Reset the I2C unit? */
+
+	lockinit(&sc->sc_buslock, PRIBIO|PCATCH, "iopiiclk", 0, 0);
+
+	/* XXX We don't currently use interrupts.  Fix this some day. */
+#if 0
+	sc->sc_ih = i80321_intr_establish((ia->ia_offset == VERDE_I2C_BASE0) ?
+	    ICU_INT_I2C0 : ICU_INT_I2C1, IPL_BIO, iopiic_intr, sc);
+	if (sc->sc_ih == NULL) {
+		aprint_error("%s: unable to establish interrupt handler\n",
+		    sc->sc_dev.dv_xname);
+		return;
+	}
+#endif
+
+	/*
+	 * Enable the I2C unit as a master.
+	 * No, we do not support slave mode.
+	 */
+	sc->sc_icr = IIC_ICR_GCD | IIC_ICR_UE | IIC_ICR_SCLE;
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISAR, 0);
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, sc->sc_icr);
+
+	iopiic_attach(sc);
+}
diff --git a/sys/arch/arm/xscale/iopi2c.c b/sys/arch/arm/xscale/iopi2c.c
new file mode 100644
index 00000000000..ce636de5898
--- /dev/null
+++ b/sys/arch/arm/xscale/iopi2c.c
@@ -0,0 +1,266 @@
+/*	$NetBSD: iopi2c.c,v 1.3 2005/12/11 12:16:51 christos Exp $	*/
+
+/*
+ * Copyright (c) 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Intel i80321 I/O Processor I2C Controller Unit support.
+ */
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/i2c/i2cvar.h>
+
+#include <arm/xscale/iopi2creg.h>
+#include <arm/xscale/iopi2cvar.h>
+
+static int iopiic_acquire_bus(void *, int);
+static void iopiic_release_bus(void *, int);
+
+static int iopiic_send_start(void *, int);
+static int iopiic_send_stop(void *, int);
+static int iopiic_initiate_xfer(void *, uint16_t, int);
+static int iopiic_read_byte(void *, uint8_t *, int);
+static int iopiic_write_byte(void *, uint8_t, int);
+
+struct cfdriver iopiic_cd = {
+	NULL, "iopiic", DV_DULL
+};
+
+void
+iopiic_attach(struct iopiic_softc *sc)
+{
+	struct i2cbus_attach_args iba;
+
+	sc->sc_i2c.ic_exec = NULL;
+	sc->sc_i2c.ic_cookie = sc;
+	sc->sc_i2c.ic_acquire_bus = iopiic_acquire_bus;
+	sc->sc_i2c.ic_release_bus = iopiic_release_bus;
+	sc->sc_i2c.ic_send_start = iopiic_send_start;
+	sc->sc_i2c.ic_send_stop = iopiic_send_stop;
+	sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer;
+	sc->sc_i2c.ic_read_byte = iopiic_read_byte;
+	sc->sc_i2c.ic_write_byte = iopiic_write_byte;
+
+	bzero(&iba, sizeof iba);
+	iba.iba_name = "iic";
+	iba.iba_tag = &sc->sc_i2c;
+	(void) config_found(&sc->sc_dev, &iba, iicbus_print);
+}
+
+static int
+iopiic_acquire_bus(void *cookie, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+
+	/* XXX What should we do for the polling case? */
+	if (flags & I2C_F_POLL)
+		return (0);
+
+	return (lockmgr(&sc->sc_buslock, LK_EXCLUSIVE, NULL));
+}
+
+static void
+iopiic_release_bus(void *cookie, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+
+	/* XXX See above. */
+	if (flags & I2C_F_POLL)
+		return;
+
+	(void) lockmgr(&sc->sc_buslock, LK_RELEASE, NULL);
+}
+
+#define	IOPIIC_TIMEOUT		100	/* protocol timeout, in uSecs */
+
+static int
+iopiic_wait(struct iopiic_softc *sc, int bit, int flags)
+{
+	uint32_t isr;
+	int timeout, error=0;
+
+	/* XXX We never sleep, we always poll.  Fix me. */
+
+	/*
+	 * For some reason, we seem to run into problems if we poll
+	 * the ISR while the transfer is in progress--at least on the
+	 * i80312.  The condition that we're looking for never seems
+	 * to appear on a read, and it's not clear why; perhaps reads
+	 * of the I2C register file interfere with its proper operation?
+	 * For now, just delay for a while up front.
+	 *
+	 * We _really_ need this to be interrupt-driven, but a problem
+	 * with that is that the i80312 has no way to mask interrupts...
+	 * So we need to deal with that.  For DMA and AAU, too, for that
+	 * matter.
+	 * Note that delay(100) doesn't quite work on the npwr w/ m41t00.
+	 */
+	delay(200);
+	for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) {
+		isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR);
+		if (isr & (bit | IIC_ISR_BED))
+			break;
+		delay(1);
+	}
+
+	if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD)))
+		error = EIO;
+	else if (isr & (bit & ~IIC_ISR_ALD))
+		error = 0;
+	else
+		error = ETIMEDOUT;
+
+#if 0
+	if (error)
+		printf("%s: iopiic_wait, (%08x) error %d: ISR = 0x%08x\n",
+		    sc->sc_dev.dv_xname, bit, error, isr);
+#endif
+
+	/*
+	 * The IIC_ISR is Read/Clear apart from the bottom 4 bits, which are
+	 * read-only. So simply write back our copy of the ISR to clear any
+	 * latched status.
+	 */
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr);
+
+	return (error);
+}
+
+static int
+iopiic_send_start(void *cookie, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+
+	/*
+	 * This may only work in conjunction with a data transfer;
+	 * we might need to un-export the "start" primitive.
+	 */
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
+	    sc->sc_icr | IIC_ICR_START);
+	delay(IOPIIC_TIMEOUT);
+
+	return (0);
+}
+
+static int
+iopiic_send_stop(void *cookie, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+
+	/*
+	 * The STOP bit is only used in conjunction with
+	 * a data transfer, so we need to use MA in this
+	 * case.
+	 *
+	 * Consider adding an I2C_F_STOP so we can
+	 * do a read-with-STOP and write-with-STOP.
+	 */
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
+	    sc->sc_icr | IIC_ICR_MA);
+	delay(IOPIIC_TIMEOUT);
+
+	return (0);
+}
+
+static int
+iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+	int error, rd_req = (flags & I2C_F_READ) != 0;
+	uint32_t idbr;
+
+	/* We only support 7-bit addressing. */
+	if ((addr & 0x78) == 0x78)
+		return (EINVAL);
+
+	idbr = (addr << 1) | (rd_req ? 1 : 0);
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr);
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
+	    sc->sc_icr | IIC_ICR_START | IIC_ICR_TB);
+
+	error = iopiic_wait(sc, IIC_ISR_ITE, flags);
+#if 0
+	if (error)
+		printf("%s: failed to initiate %s xfer\n", sc->sc_dev.dv_xname,
+		    rd_req ? "read" : "write");
+#endif
+	return (error);
+}
+
+static int
+iopiic_read_byte(void *cookie, uint8_t *bytep, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+	int error, last_byte = (flags & I2C_F_LAST) != 0,
+	    send_stop = (flags & I2C_F_STOP) != 0;
+
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
+	    sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) |
+	    (send_stop ? IIC_ICR_STOP : 0));
+	if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0)
+		*bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR);
+#if 0
+	if (error)
+		printf("%s: read byte failed\n", sc->sc_dev.dv_xname);
+#endif
+
+	return (error);
+}
+
+static int
+iopiic_write_byte(void *cookie, uint8_t byte, int flags)
+{
+	struct iopiic_softc *sc = cookie;
+	int error, send_stop = (flags & I2C_F_STOP) != 0;
+
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte);
+	bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
+	    sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0));
+	error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags);
+
+#if 0
+	if (error)
+		printf("%s: write byte failed\n", sc->sc_dev.dv_xname);
+#endif
+
+	return (error);
+}
diff --git a/sys/arch/arm/xscale/iopi2creg.h b/sys/arch/arm/xscale/iopi2creg.h
new file mode 100644
index 00000000000..908c337ef97
--- /dev/null
+++ b/sys/arch/arm/xscale/iopi2creg.h
@@ -0,0 +1,77 @@
+/*	$NetBSD: iopi2creg.h,v 1.2 2005/12/11 12:16:51 christos Exp $	*/
+
+/*
+ * Copyright (c) 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_XSCALE_IOPIICREG_H_ 
+#define _ARM_XSCALE_IOPIICREG_H_ 
+
+#define	IIC_ICR		0x00	/* i2c control register */
+#define	IIC_ISR		0x04	/* i2c status register */
+#define	IIC_ISAR	0x08	/* i2c slave address register */
+#define	IIC_IDBR	0x0c	/* i2c data buffer register */
+#define	IIC_ICCR	0x10	/* i2c clock control register (i80312 only) */
+#define	IIC_IBMR	0x14	/* i2c bus monitor register */
+
+#define	IIC_ICR_FM		(1U << 15)	/* fast mode (i80321 only) */
+#define	IIC_ICR_RESET		(1U << 14)	/* i2c unit reset */
+#define	IIC_ICR_SADIE		(1U << 13)	/* slave addr det int en */
+#define	IIC_ICR_ALDIE		(1U << 12)	/* arb loss det int en */
+#define	IIC_ICR_SSDIE		(1U << 11)	/* slave stop det in en */
+#define	IIC_ICR_BEIE		(1U << 10)	/* bus error int en */
+#define	IIC_ICR_IRFIE		(1U << 9)	/* IDBR Rx full int en */
+#define	IIC_ICR_ITEIE		(1U << 8)	/* IDBR Tx empty int en */
+#define	IIC_ICR_GCD		(1U << 7)	/* general call disable */
+#define	IIC_ICR_UE		(1U << 6)	/* i2c unit enable */
+#define	IIC_ICR_SCLE		(1U << 5)	/* SCL master enable */
+#define	IIC_ICR_MA		(1U << 4)	/* abort as master */
+#define	IIC_ICR_TB		(1U << 3)	/* transfer byte */
+#define	IIC_ICR_NACK		(1U << 2)	/* 0=ACK, 1=NACK */
+#define	IIC_ICR_STOP		(1U << 1)	/* initiate STOP condition */
+#define	IIC_ICR_START		(1U << 0)	/* initiate START condition */
+
+#define	IIC_ISR_BED		(1U << 10)	/* bus error detected */
+#define	IIC_ISR_SAD		(1U << 9)	/* slave address detected */
+#define	IIC_ISR_GCAD		(1U << 8)	/* general call addr detected */
+#define	IIC_ISR_IRF		(1U << 7)	/* IDBR Rx full */
+#define	IIC_ISR_ITE		(1U << 6)	/* IDBR Tx empty */
+#define	IIC_ISR_ALD		(1U << 5)	/* arb loss detected */
+#define	IIC_ISR_SSD		(1U << 4)	/* slave STOP detected */
+#define	IIC_ISR_IBB		(1U << 3)	/* i2c bus busy */
+#define	IIC_ISR_UB		(1U << 2)	/* unit busy */
+#define	IIC_ISR_NACK		(1U << 1)	/* NACK received */
+#define	IIC_ISR_RW		(1U << 0)	/* 0=mt/sr, 1=mr/st */
+
+#endif /* _ARM_XSCALE_IOPIICREG_H_  */
diff --git a/sys/arch/arm/xscale/iopi2cvar.h b/sys/arch/arm/xscale/iopi2cvar.h
new file mode 100644
index 00000000000..91842e82792
--- /dev/null
+++ b/sys/arch/arm/xscale/iopi2cvar.h
@@ -0,0 +1,55 @@
+/*	$NetBSD: iopi2cvar.h,v 1.2 2005/12/11 12:16:51 christos Exp $	*/
+
+/*
+ * Copyright (c) 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_XSCALE_IOPIICVAR_H_ 
+#define _ARM_XSCALE_IOPIICVAR_H_ 
+
+struct iopiic_softc {
+	struct device sc_dev;
+	bus_space_tag_t sc_st;
+	bus_space_handle_t sc_sh;
+
+	void *sc_ih;
+
+	struct i2c_controller sc_i2c;
+	struct lock sc_buslock;
+	uint32_t sc_icr;
+};
+
+void iopiic_attach(struct iopiic_softc *sc);
+
+#endif /* _ARM_XSCALE_IOPIICVAR_H_  */