diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2016-10-08 03:42:21 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2016-10-08 03:42:21 +0000 |
| commit | 729811e9fd8867344db291678555ca04ad857936 (patch) | |
| tree | 7cae82e3bd94e4aed9dcae31bc762c03d7d85348 /sys/arch/armv7 | |
| parent | 19ac1b698da1939c04cbda39cc6e6e899bbeedf6 (diff) | |
Only set the highspeed bit in bus_clock if highspeed is supported
by the controller. Needed as the bus_clock callback is called with
SDMMC_TIMING_HIGHSPEED even if the controller capability is not set.
Required to raise the bus width on pandaboard which doesn't have the
highspeed capability.
As anything other than 1 bit mode results in the emmc on the bbb
timing out waiting for command completion, limit higher bus
modes to the first hsmmc controller. This at least lets 4 bit
modes work with sd cards on bbb and pandaboard.
Diffstat (limited to 'sys/arch/armv7')
| -rw-r--r-- | sys/arch/armv7/omap/ommmc.c | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/sys/arch/armv7/omap/ommmc.c b/sys/arch/armv7/omap/ommmc.c index 0ece1e3e15d..184f182d8cf 100644 --- a/sys/arch/armv7/omap/ommmc.c +++ b/sys/arch/armv7/omap/ommmc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ommmc.c,v 1.29 2016/08/12 03:22:41 jsg Exp $ */ +/* $OpenBSD: ommmc.c,v 1.30 2016/10/08 03:42:20 jsg Exp $ */ /* * Copyright (c) 2009 Dale Rahn <drahn@openbsd.org> @@ -193,6 +193,7 @@ struct ommmc_softc { bus_space_handle_t sc_ioh; void *sc_ih; /* Interrupt handler */ uint32_t sc_flags; +#define FL_HSS (1 << 0) struct device *sdmmc; /* generic SD/MMC device */ int clockbit; /* clock control bit */ @@ -298,7 +299,7 @@ ommmc_attach(struct device *parent, struct device *self, void *aux) struct ommmc_softc *sc = (struct ommmc_softc *) self; struct fdt_attach_args *faa = aux; struct sdmmcbus_attach_args saa; - uint32_t caps; + uint32_t caps, width; uint32_t addr, size; int len, unit; char hwmods[128]; @@ -432,8 +433,19 @@ ommmc_attach(struct device *parent, struct device *self, void *aux) saa.saa_busname = "sdmmc"; saa.sct = &ommmc_functions; saa.sch = sc; - if (caps & MMCHS_CAPA_HSS) - saa.caps |= SMC_CAPS_MMC_HIGHSPEED; + if (OF_getproplen(faa->fa_node, "ti,needs-special-hs-handling") == 0 && + (caps & MMCHS_CAPA_HSS)) { + sc->sc_flags |= FL_HSS; + saa.caps |= SMC_CAPS_MMC_HIGHSPEED | SMC_CAPS_SD_HIGHSPEED; + } + width = OF_getpropint(faa->fa_node, "bus-width", 1); + /* with bbb emmc width > 1 ommmc_wait_intr MMCHS_STAT_CC times out */ + if (unit != 0) + width = 1; + if (width >= 8) + saa.caps |= SMC_CAPS_8BIT_MODE; + if (width >= 4) + saa.caps |= SMC_CAPS_4BIT_MODE; sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); if (sc->sdmmc == NULL) { @@ -717,10 +729,10 @@ ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) reg |= div << MMCHS_SYSCTL_CLKD_SH; HWRITE4(sc, MMCHS_SYSCTL, reg); - if (timing == SDMMC_TIMING_LEGACY) - HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); - else + if ((timing == SDMMC_TIMING_HIGHSPEED) && (sc->sc_flags & FL_HSS)) HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); + else + HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); /* * Start internal clock. Wait 10ms for stabilization. |