Add cad(4), a driver for Cadence GEM.

This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.

OK kettenis@

2 files changed, 4 insertions, 2 deletions

diff --git a/sys/arch/armv7/conf/GENERIC b/sys/arch/armv7/conf/GENERIC
index 345889a9e7e..1af5eb8dd85 100644
--- a/sys/arch/armv7/conf/GENERIC
+++ b/sys/arch/armv7/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.137 2021/04/30 13:25:24 visa Exp $
+#	$OpenBSD: GENERIC,v 1.138 2021/05/28 15:52:11 visa Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -212,6 +212,7 @@ rktemp*		at fdt?
 dwdog*		at fdt?
 
 # Xilinx Zynq-7000
+cad*		at fdt?			# Ethernet controller
 cduart*		at fdt?
 zqclock*	at fdt?
 zqreset*	at fdt?
diff --git a/sys/arch/armv7/conf/RAMDISK b/sys/arch/armv7/conf/RAMDISK
index a16fe82efbb..57a266ea9fd 100644
--- a/sys/arch/armv7/conf/RAMDISK
+++ b/sys/arch/armv7/conf/RAMDISK
@@ -1,4 +1,4 @@
-#	$OpenBSD: RAMDISK,v 1.124 2021/05/19 16:57:04 deraadt Exp $
+#	$OpenBSD: RAMDISK,v 1.125 2021/05/28 15:52:11 visa Exp $
 
 machine		armv7 arm
 
@@ -197,6 +197,7 @@ iic*		at rkiic?
 dwdog*		at fdt?
 
 # Xilinx Zynq-7000
+cad*		at fdt?			# Ethernet controller
 cduart*		at fdt?
 zqclock*	at fdt?
 zqreset*	at fdt?